text
stringlengths 938
1.05M
|
|---|
module all_case (
clk_in,clk0,clk1,clk2,clk3,
rst,rst0,rst1,rst2,rst3,
sel_o,sell,
pa,pb,pc,p0,p1,p2,p00,p01,p02,ps,pd,ph,
ddd,ddd0,df_0,df,
);
input clk_in,rst,pa,pb,pc,ddd,ddd0;
input [1:0] sell;
output clk0,clk1,clk2,clk3;
output rst0,rst1,rst2,rst3;
output p0,p1,p2,p00,p01,p02,ps,pd,ph;
output df,df_0;
output [1:0] sel_o;
wire clk_in,rst,pa,pb,pc,ddd,ddd0;
reg clk0,clk1,clk2,clk3;
reg rst0,rst1,rst2,rst3;
reg p0,p1,p2,p00,p01,p02,ps,pd,ph;
reg df,df_0;
always@(sell)
begin
case (sell)
0:
begin
clk0=clk_in;
rst0=rst;
p0=pa;
p1=pb;
p2=pc;
clk1=0;
rst1=1;
p00=1;
p01=1;
p02=1;
clk2=0;
rst2=0;
ps=1;
pd=1;
ph=1;
df=0;
df_0=0;
clk3=0;
rst3=0;
end
1:
begin
clk1=clk_in;
rst1=rst;
p00=pa;
p01=pb;
p02=pc;
clk0=clk_in;
rst0=1;
p0=1;
p1=1;
p2=1;
clk2=0;
rst2=0;
ps=1;
pd=1;
ph=1;
df=0;
df_0=0;
clk3=0;
rst3=0;
end
2 :
begin
clk2=clk_in;
rst2=rst;
ps=pa;
pd=pb;
ph=pc;
df=ddd;
df_0=ddd0;
clk0=0;
rst0=0;
p00=1;
p01=1;
p02=1;
clk1=0;
rst1=0;
p0=1;
p1=1;
p2=1;
clk3=0;
rst3=0;
end
3 :
begin
clk3=clk_in;
rst3=rst;
clk0=0;
rst0=0;
p00=1;
p01=1;
p02=1;
clk1=0;
rst1=0;
p0=1;
p1=1;
p2=1;
clk2=0;
rst2=0;
ps=1;
pd=1;
ph=1;
df=0;
df_0=0;
end
endcase
end
assign sel_o = sell;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_M_V
`define SKY130_FD_SC_LP__A41O_M_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_m (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_m (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_M_V
|
//======================================================================
//
// rosc_entropy.v
// --------------
// Top level wrapper for the ring oscillator entropy core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module rosc_entropy(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
input wire discard,
input wire test_mode,
output wire security_error,
output wire entropy_enabled,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_CTRL = 8'h10;
parameter ADDR_STATUS = 8'h11;
parameter STATUS_ENTROPY_VALID_BIT = 0;
parameter ADDR_ROSC_CYCLES = 8'h14;
parameter ADDR_OP_A = 8'h18;
parameter ADDR_OP_B = 8'h19;
parameter ADDR_ENTROPY = 8'h20;
parameter ADDR_RAW = 8'h21;
parameter ADDR_ROSC_OUTPUTS = 8'h22;
parameter DEFAULT_ROSC_EN = 32'hffffffff;
parameter DEFAULT_ROSC_CYCLES = 8'hff;
parameter DEFAULT_OP_A = 32'haaaaaaaa;
parameter DEFAULT_OP_B = ~DEFAULT_OP_A;
parameter CORE_NAME0 = 32'h726f7363; // "rosc"
parameter CORE_NAME1 = 32'h20656e74; // " ent"
parameter CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] enable_reg;
reg enable_we;
reg [7 : 0] rosc_cycles_reg;
reg [7 : 0] rosc_cycles_we;
reg [31 : 0] op_a_reg;
reg op_a_we;
reg [31 : 0] op_b_reg;
reg op_b_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] raw_entropy;
wire [31 : 0] rosc_outputs;
wire [31 : 0] internal_entropy_data;
wire internal_entropy_valid;
wire internal_entropy_ack;
reg api_entropy_ack;
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
assign security_error = 0;
assign entropy_enabled = |enable_reg;
assign entropy_data = internal_entropy_data;
assign entropy_valid = internal_entropy_valid;
assign internal_entropy_ack = api_entropy_ack | entropy_ack;
//----------------------------------------------------------------
// module instantiations.
//----------------------------------------------------------------
rosc_entropy_core core(
.clk(clk),
.reset_n(reset_n),
.opa(op_a_reg),
.opb(op_b_reg),
.rosc_en(enable_reg),
.rosc_cycles(rosc_cycles_reg),
.raw_entropy(raw_entropy),
.rosc_outputs(rosc_outputs),
.entropy_data(internal_entropy_data),
.entropy_valid(internal_entropy_valid),
.entropy_ack(internal_entropy_ack),
.debug(debug),
.debug_update(debug_update)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
enable_reg <= 32'hffffffff;
rosc_cycles_reg <= 8'hff;
op_a_reg <= DEFAULT_OP_A;
op_b_reg <= DEFAULT_OP_B;
end
else
begin
if (enable_we)
begin
enable_reg <= write_data;
end
if (rosc_cycles_we)
begin
rosc_cycles_reg <= write_data[7 : 0];
end
if (op_a_we)
begin
op_a_reg <= write_data;
end
if (op_b_we)
begin
op_b_reg <= write_data;
end
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If cs is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
enable_we = 0;
rosc_cycles_we = 0;
op_a_we = 0;
op_b_we = 0;
api_entropy_ack = 0;
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
case (address)
// Write operations.
ADDR_CTRL:
begin
enable_we = 1;
end
ADDR_ROSC_CYCLES:
begin
rosc_cycles_we = 1;
end
ADDR_OP_A:
begin
op_a_we = 1;
end
ADDR_OP_B:
begin
op_b_we = 1;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
else
begin
case (address)
ADDR_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
ADDR_CTRL:
begin
tmp_read_data = enable_reg;
end
ADDR_STATUS:
begin
tmp_read_data[STATUS_ENTROPY_VALID_BIT] = internal_entropy_valid;
end
ADDR_ROSC_CYCLES:
begin
tmp_read_data = rosc_cycles_reg;
end
ADDR_OP_A:
begin
tmp_read_data = op_a_reg;
end
ADDR_OP_B:
begin
tmp_read_data = op_b_reg;
end
ADDR_ENTROPY:
begin
tmp_read_data = entropy_data;
api_entropy_ack = 1;
end
ADDR_RAW:
begin
tmp_read_data = raw_entropy;
end
ADDR_ROSC_OUTPUTS:
begin
tmp_read_data = rosc_outputs;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end
endmodule // rosc_entropy_core
//======================================================================
// EOF rosc_entropy_core.v
//======================================================================
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/wordregister.v:1" *)
module WordRegister(Reset_n_i, Clk_i, D_i, Q_o, Enable_i);
(* src = "../../verilog/wordregister.v:14" *)
wire [15:0] \$0\Q_o[15:0] ;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/wordregister.v:5" *)
input Clk_i;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/wordregister.v:7" *)
input [15:0] D_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/wordregister.v:11" *)
input Enable_i;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/wordregister.v:9" *)
output [15:0] Q_o;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/wordregister.v:3" *)
input Reset_n_i;
(* src = "../../verilog/wordregister.v:14" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$16 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Q_o[15:0] ),
.Q(Q_o)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$8 (
.A(Q_o),
.B(D_i),
.S(Enable_i),
.Y(\$0\Q_o[15:0] )
);
endmodule
|
/*
Copyright (c) 2016-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
inout wire phy_mdio,
output wire phy_mdc,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
wire clk_125mhz_mmcm_out;
// Internal 125 MHz clock
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 8, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(8),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
wire i2c_scl_i;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_i;
wire i2c_sda_o;
wire i2c_sda_t;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] gig_eth_pcspma_status_vector;
wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0];
wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1];
wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2];
wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3];
wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4];
wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5];
wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6];
wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7];
wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8];
wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10];
wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12];
wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13];
wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14];
wire [4:0] gig_eth_pcspma_config_vector;
assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate
assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down
assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable
assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] gig_eth_pcspma_an_config_vector;
assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
eth_pcspma (
// SGMII
.txp_0 (phy_sgmii_tx_p),
.txn_0 (phy_sgmii_tx_n),
.rxp_0 (phy_sgmii_rx_p),
.rxn_0 (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.tx_logic_reset (),
.rx_logic_reset (),
.tx_locked (),
.rx_locked (),
.tx_pll_clk_out (),
.rx_pll_clk_out (),
// MAC clocking
.sgmii_clk_r_0 (),
.sgmii_clk_f_0 (),
.sgmii_clk_en_0 (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100_0 (gig_eth_pcspma_status_speed != 2'b10),
.speed_is_100_0 (gig_eth_pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd_0 (phy_gmii_txd_int),
.gmii_tx_en_0 (phy_gmii_tx_en_int),
.gmii_tx_er_0 (phy_gmii_tx_er_int),
.gmii_rxd_0 (phy_gmii_rxd_int),
.gmii_rx_dv_0 (phy_gmii_rx_dv_int),
.gmii_rx_er_0 (phy_gmii_rx_er_int),
.gmii_isolate_0 (),
// Configuration
.configuration_vector_0 (gig_eth_pcspma_config_vector),
.an_interrupt_0 (),
.an_adv_config_vector_0 (gig_eth_pcspma_an_config_vector),
.an_restart_config_0 (1'b0),
// Status
.status_vector_0 (gig_eth_pcspma_status_vector),
.signal_detect_0 (1'b1),
// Cascade
.tx_bsc_rst_out (),
.rx_bsc_rst_out (),
.tx_bs_rst_out (),
.rx_bs_rst_out (),
.tx_rst_dly_out (),
.rx_rst_dly_out (),
.tx_bsc_en_vtc_out (),
.rx_bsc_en_vtc_out (),
.tx_bs_en_vtc_out (),
.rx_bs_en_vtc_out (),
.riu_clk_out (),
.riu_addr_out (),
.riu_wr_data_out (),
.riu_wr_en_out (),
.riu_nibble_sel_out (),
.riu_rddata_1 (16'b0),
.riu_valid_1 (1'b0),
.riu_prsnt_1 (1'b0),
.riu_rddata_2 (16'b0),
.riu_valid_2 (1'b0),
.riu_prsnt_2 (1'b0),
.riu_rddata_3 (16'b0),
.riu_valid_3 (1'b0),
.riu_prsnt_3 (1'b0),
.rx_btval_1 (),
.rx_btval_2 (),
.rx_btval_3 (),
.tx_dly_rdy_1 (1'b1),
.rx_dly_rdy_1 (1'b1),
.rx_vtc_rdy_1 (1'b1),
.tx_vtc_rdy_1 (1'b1),
.tx_dly_rdy_2 (1'b1),
.rx_dly_rdy_2 (1'b1),
.rx_vtc_rdy_2 (1'b1),
.tx_vtc_rdy_2 (1'b1),
.tx_dly_rdy_3 (1'b1),
.rx_dly_rdy_3 (1'b1),
.rx_vtc_rdy_3 (1'b1),
.tx_vtc_rdy_3 (1'b1),
.tx_rdclk_out ()
);
reg [19:0] delay_reg = 20'hfffff;
reg [4:0] mdio_cmd_phy_addr = 5'h03;
reg [4:0] mdio_cmd_reg_addr = 5'h00;
reg [15:0] mdio_cmd_data = 16'd0;
reg [1:0] mdio_cmd_opcode = 2'b01;
reg mdio_cmd_valid = 1'b0;
wire mdio_cmd_ready;
reg [3:0] state_reg = 0;
always @(posedge clk_125mhz_int) begin
if (rst_125mhz_int) begin
state_reg <= 0;
delay_reg <= 20'hfffff;
mdio_cmd_reg_addr <= 5'h00;
mdio_cmd_data <= 16'd0;
mdio_cmd_valid <= 1'b0;
end else begin
mdio_cmd_valid <= mdio_cmd_valid & !mdio_cmd_ready;
if (delay_reg > 0) begin
delay_reg <= delay_reg - 1;
end else if (!mdio_cmd_ready) begin
// wait for ready
state_reg <= state_reg;
end else begin
mdio_cmd_valid <= 1'b0;
case (state_reg)
// set SGMII autonegotiation timer to 11 ms
// write 0x0070 to CFG4 (0x0031)
4'd0: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd1;
end
4'd1: begin
// write address of CFG4 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0031;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd2;
end
4'd2: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd3;
end
4'd3: begin
// write data for CFG4 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0070;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd4;
end
// enable SGMII clock output
// write 0x4000 to SGMIICTL1 (0x00D3)
4'd4: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd5;
end
4'd5: begin
// write address of SGMIICTL1 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h00D3;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd6;
end
4'd6: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd7;
end
4'd7: begin
// write data for SGMIICTL1 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h4000;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd8;
end
// enable 10Mbps operation
// write 0x0015 to 10M_SGMII_CFG (0x016F)
4'd8: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd9;
end
4'd9: begin
// write address of 10M_SGMII_CFG to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h016F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd10;
end
4'd10: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd11;
end
4'd11: begin
// write data for 10M_SGMII_CFG to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0015;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd12;
end
4'd12: begin
// done
state_reg <= 4'd12;
end
endcase
end
end
end
wire mdc;
wire mdio_i;
wire mdio_o;
wire mdio_t;
mdio_master
mdio_master_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.cmd_phy_addr(mdio_cmd_phy_addr),
.cmd_reg_addr(mdio_cmd_reg_addr),
.cmd_data(mdio_cmd_data),
.cmd_opcode(mdio_cmd_opcode),
.cmd_valid(mdio_cmd_valid),
.cmd_ready(mdio_cmd_ready),
.data_out(),
.data_out_valid(),
.data_out_ready(1'b1),
.mdc_o(mdc),
.mdio_i(mdio_i),
.mdio_o(mdio_o),
.mdio_t(mdio_t),
.busy(),
.prescale(8'd3)
);
assign phy_mdc = mdc;
assign mdio_i = phy_mdio;
assign phy_mdio = mdio_t ? 1'bz : mdio_o;
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* I2C
*/
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_TB_V
`define SKY130_FD_SC_HS__EDFXBP_TB_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__edfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 DE = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 DE = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 DE = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 DE = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__edfxbp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_TB_V
|
// Generated by FIR Compiler
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
// 00
// altera message_off 10036
(* altera_attribute = "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410" *)
module matchfilter_st (clk,
rst,
data_in,
clk_en,
rdy_to_ld,
done,
fir_result);
parameter DATA_WIDTH = 15;
parameter COEF_WIDTH = 13;
parameter ACCUM_WIDTH = 31;
parameter MSB_RM = 0;
parameter LSB_RM = 1;
parameter WIDTH_SAT = ACCUM_WIDTH-LSB_RM;
input clk, rst;
input [DATA_WIDTH-1:0] data_in;
input clk_en;
output rdy_to_ld;
wire rdy_to_ld;
wire rdy_int;
wire data_ld;
output done;
wire done;
wire done_int;
output [ACCUM_WIDTH-MSB_RM-LSB_RM-1:0] fir_result;
wire addr_low;
assign addr_low = 1'b0;
//--- Parallel TDL Storage ---
wire inv_rst;
assign inv_rst = ~rst;
assign data_ld = rdy_int;
wire [14:0] tdl_0_n;
wire [14:0] tdl_1_n;
wire [14:0] tdl_2_n;
wire [14:0] tdl_3_n;
wire [14:0] tdl_4_n;
wire [14:0] tdl_5_n;
wire [14:0] tdl_6_n;
wire [14:0] tdl_7_n;
wire [14:0] tdl_8_n;
wire [14:0] tdl_9_n;
wire [14:0] tdl_10_n;
wire [14:0] tdl_11_n;
wire [14:0] tdl_12_n;
wire [14:0] tdl_13_n;
wire [14:0] tdl_14_n;
wire [14:0] tdl_15_n;
wire [14:0] tdl_16_n;
wire [14:0] tdl_17_n;
wire [14:0] tdl_18_n;
wire [14:0] tdl_19_n;
wire [14:0] tdl_20_n;
wire [14:0] tdl_21_n;
wire [14:0] tdl_22_n;
wire [14:0] tdl_23_n;
wire [14:0] tdl_24_n;
wire [14:0] tdl_25_n;
wire [14:0] tdl_26_n;
wire [14:0] tdl_27_n;
wire [14:0] tdl_28_n;
wire [14:0] tdl_29_n;
wire [14:0] tdl_30_n;
wire [14:0] tdl_31_n;
wire [14:0] tdl_32_n;
wire [14:0] tdl_33_n;
wire [14:0] tdl_34_n;
wire [14:0] tdl_35_n;
wire [14:0] tdl_36_n;
wire [14:0] tdl_37_n;
wire [14:0] tdl_38_n;
wire [14:0] tdl_39_n;
wire [14:0] tdl_40_n;
wire [14:0] tdl_41_n;
wire [14:0] tdl_42_n;
wire [14:0] tdl_43_n;
wire [14:0] tdl_44_n;
wire [14:0] tdl_45_n;
wire [14:0] tdl_46_n;
wire [14:0] tdl_47_n;
wire [14:0] tdl_48_n;
wire [14:0] tdl_49_n;
wire [14:0] tdl_50_n;
wire [14:0] tdl_51_n;
wire [14:0] tdl_52_n;
wire [14:0] tdl_53_n;
wire [14:0] tdl_54_n;
wire [14:0] tdl_55_n;
wire [14:0] tdl_56_n;
wire [14:0] tdl_57_n;
wire [14:0] tdl_58_n;
wire [14:0] tdl_59_n;
wire [14:0] tdl_60_n;
wire [14:0] tdl_61_n;
wire [14:0] tdl_62_n;
wire [14:0] tdl_63_n;
wire [14:0] tdl_64_n;
wire [14:0] tdl_65_n;
wire [14:0] tdl_66_n;
wire [14:0] tdl_67_n;
wire [14:0] tdl_68_n;
wire [14:0] tdl_69_n;
wire [14:0] tdl_70_n;
wire [14:0] tdl_71_n;
wire [14:0] tdl_72_n;
wire [14:0] tdl_73_n;
wire [14:0] tdl_74_n;
wire [14:0] tdl_75_n;
wire [14:0] tdl_76_n;
wire [14:0] tdl_77_n;
wire [14:0] tdl_78_n;
wire [14:0] tdl_79_n;
wire [14:0] tdl_80_n;
//--- TDL ---
tdl_da_lc Utdldalc0n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(data_in), .data_out(tdl_0_n) );
defparam Utdldalc0n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc1n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_0_n), .data_out(tdl_1_n) );
defparam Utdldalc1n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc2n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_1_n), .data_out(tdl_2_n) );
defparam Utdldalc2n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc3n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_2_n), .data_out(tdl_3_n) );
defparam Utdldalc3n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc4n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_3_n), .data_out(tdl_4_n) );
defparam Utdldalc4n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc5n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_4_n), .data_out(tdl_5_n) );
defparam Utdldalc5n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc6n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_5_n), .data_out(tdl_6_n) );
defparam Utdldalc6n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc7n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_6_n), .data_out(tdl_7_n) );
defparam Utdldalc7n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc8n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_7_n), .data_out(tdl_8_n) );
defparam Utdldalc8n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc9n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_8_n), .data_out(tdl_9_n) );
defparam Utdldalc9n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc10n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_9_n), .data_out(tdl_10_n) );
defparam Utdldalc10n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc11n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_10_n), .data_out(tdl_11_n) );
defparam Utdldalc11n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc12n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_11_n), .data_out(tdl_12_n) );
defparam Utdldalc12n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc13n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_12_n), .data_out(tdl_13_n) );
defparam Utdldalc13n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc14n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_13_n), .data_out(tdl_14_n) );
defparam Utdldalc14n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc15n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_14_n), .data_out(tdl_15_n) );
defparam Utdldalc15n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc16n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_15_n), .data_out(tdl_16_n) );
defparam Utdldalc16n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc17n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_16_n), .data_out(tdl_17_n) );
defparam Utdldalc17n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc18n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_17_n), .data_out(tdl_18_n) );
defparam Utdldalc18n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc19n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_18_n), .data_out(tdl_19_n) );
defparam Utdldalc19n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc20n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_19_n), .data_out(tdl_20_n) );
defparam Utdldalc20n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc21n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_20_n), .data_out(tdl_21_n) );
defparam Utdldalc21n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc22n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_21_n), .data_out(tdl_22_n) );
defparam Utdldalc22n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc23n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_22_n), .data_out(tdl_23_n) );
defparam Utdldalc23n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc24n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_23_n), .data_out(tdl_24_n) );
defparam Utdldalc24n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc25n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_24_n), .data_out(tdl_25_n) );
defparam Utdldalc25n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc26n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_25_n), .data_out(tdl_26_n) );
defparam Utdldalc26n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc27n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_26_n), .data_out(tdl_27_n) );
defparam Utdldalc27n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc28n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_27_n), .data_out(tdl_28_n) );
defparam Utdldalc28n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc29n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_28_n), .data_out(tdl_29_n) );
defparam Utdldalc29n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc30n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_29_n), .data_out(tdl_30_n) );
defparam Utdldalc30n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc31n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_30_n), .data_out(tdl_31_n) );
defparam Utdldalc31n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc32n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_31_n), .data_out(tdl_32_n) );
defparam Utdldalc32n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc33n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_32_n), .data_out(tdl_33_n) );
defparam Utdldalc33n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc34n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_33_n), .data_out(tdl_34_n) );
defparam Utdldalc34n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc35n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_34_n), .data_out(tdl_35_n) );
defparam Utdldalc35n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc36n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_35_n), .data_out(tdl_36_n) );
defparam Utdldalc36n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc37n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_36_n), .data_out(tdl_37_n) );
defparam Utdldalc37n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc38n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_37_n), .data_out(tdl_38_n) );
defparam Utdldalc38n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc39n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_38_n), .data_out(tdl_39_n) );
defparam Utdldalc39n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc40n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_39_n), .data_out(tdl_40_n) );
defparam Utdldalc40n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc41n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_40_n), .data_out(tdl_41_n) );
defparam Utdldalc41n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc42n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_41_n), .data_out(tdl_42_n) );
defparam Utdldalc42n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc43n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_42_n), .data_out(tdl_43_n) );
defparam Utdldalc43n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc44n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_43_n), .data_out(tdl_44_n) );
defparam Utdldalc44n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc45n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_44_n), .data_out(tdl_45_n) );
defparam Utdldalc45n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc46n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_45_n), .data_out(tdl_46_n) );
defparam Utdldalc46n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc47n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_46_n), .data_out(tdl_47_n) );
defparam Utdldalc47n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc48n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_47_n), .data_out(tdl_48_n) );
defparam Utdldalc48n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc49n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_48_n), .data_out(tdl_49_n) );
defparam Utdldalc49n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc50n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_49_n), .data_out(tdl_50_n) );
defparam Utdldalc50n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc51n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_50_n), .data_out(tdl_51_n) );
defparam Utdldalc51n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc52n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_51_n), .data_out(tdl_52_n) );
defparam Utdldalc52n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc53n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_52_n), .data_out(tdl_53_n) );
defparam Utdldalc53n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc54n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_53_n), .data_out(tdl_54_n) );
defparam Utdldalc54n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc55n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_54_n), .data_out(tdl_55_n) );
defparam Utdldalc55n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc56n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_55_n), .data_out(tdl_56_n) );
defparam Utdldalc56n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc57n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_56_n), .data_out(tdl_57_n) );
defparam Utdldalc57n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc58n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_57_n), .data_out(tdl_58_n) );
defparam Utdldalc58n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc59n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_58_n), .data_out(tdl_59_n) );
defparam Utdldalc59n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc60n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_59_n), .data_out(tdl_60_n) );
defparam Utdldalc60n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc61n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_60_n), .data_out(tdl_61_n) );
defparam Utdldalc61n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc62n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_61_n), .data_out(tdl_62_n) );
defparam Utdldalc62n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc63n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_62_n), .data_out(tdl_63_n) );
defparam Utdldalc63n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc64n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_63_n), .data_out(tdl_64_n) );
defparam Utdldalc64n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc65n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_64_n), .data_out(tdl_65_n) );
defparam Utdldalc65n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc66n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_65_n), .data_out(tdl_66_n) );
defparam Utdldalc66n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc67n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_66_n), .data_out(tdl_67_n) );
defparam Utdldalc67n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc68n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_67_n), .data_out(tdl_68_n) );
defparam Utdldalc68n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc69n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_68_n), .data_out(tdl_69_n) );
defparam Utdldalc69n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc70n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_69_n), .data_out(tdl_70_n) );
defparam Utdldalc70n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc71n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_70_n), .data_out(tdl_71_n) );
defparam Utdldalc71n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc72n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_71_n), .data_out(tdl_72_n) );
defparam Utdldalc72n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc73n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_72_n), .data_out(tdl_73_n) );
defparam Utdldalc73n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc74n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_73_n), .data_out(tdl_74_n) );
defparam Utdldalc74n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc75n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_74_n), .data_out(tdl_75_n) );
defparam Utdldalc75n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc76n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_75_n), .data_out(tdl_76_n) );
defparam Utdldalc76n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc77n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_76_n), .data_out(tdl_77_n) );
defparam Utdldalc77n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc78n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_77_n), .data_out(tdl_78_n) );
defparam Utdldalc78n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc79n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_78_n), .data_out(tdl_79_n) );
defparam Utdldalc79n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc80n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_79_n), .data_out(tdl_80_n) );
defparam Utdldalc80n.WIDTH = DATA_WIDTH;
// --- ROM LUTs ----
// symmetrical adders ...
wire [15:0] sym_res_0_n;
uadd_cen U_0_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_0_n), .bin(tdl_80_n), .res(sym_res_0_n) );
defparam U_0_sym_add.IN_WIDTH = 15;
defparam U_0_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_1_n;
uadd_cen U_1_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_1_n), .bin(tdl_79_n), .res(sym_res_1_n) );
defparam U_1_sym_add.IN_WIDTH = 15;
defparam U_1_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_2_n;
uadd_cen U_2_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_2_n), .bin(tdl_78_n), .res(sym_res_2_n) );
defparam U_2_sym_add.IN_WIDTH = 15;
defparam U_2_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_3_n;
uadd_cen U_3_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_3_n), .bin(tdl_77_n), .res(sym_res_3_n) );
defparam U_3_sym_add.IN_WIDTH = 15;
defparam U_3_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_4_n;
uadd_cen U_4_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_4_n), .bin(tdl_76_n), .res(sym_res_4_n) );
defparam U_4_sym_add.IN_WIDTH = 15;
defparam U_4_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_5_n;
uadd_cen U_5_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_5_n), .bin(tdl_75_n), .res(sym_res_5_n) );
defparam U_5_sym_add.IN_WIDTH = 15;
defparam U_5_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_6_n;
uadd_cen U_6_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_6_n), .bin(tdl_74_n), .res(sym_res_6_n) );
defparam U_6_sym_add.IN_WIDTH = 15;
defparam U_6_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_7_n;
uadd_cen U_7_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_7_n), .bin(tdl_73_n), .res(sym_res_7_n) );
defparam U_7_sym_add.IN_WIDTH = 15;
defparam U_7_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_8_n;
uadd_cen U_8_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_8_n), .bin(tdl_72_n), .res(sym_res_8_n) );
defparam U_8_sym_add.IN_WIDTH = 15;
defparam U_8_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_9_n;
uadd_cen U_9_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_9_n), .bin(tdl_71_n), .res(sym_res_9_n) );
defparam U_9_sym_add.IN_WIDTH = 15;
defparam U_9_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_10_n;
uadd_cen U_10_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_10_n), .bin(tdl_70_n), .res(sym_res_10_n) );
defparam U_10_sym_add.IN_WIDTH = 15;
defparam U_10_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_11_n;
uadd_cen U_11_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_11_n), .bin(tdl_69_n), .res(sym_res_11_n) );
defparam U_11_sym_add.IN_WIDTH = 15;
defparam U_11_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_12_n;
uadd_cen U_12_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_12_n), .bin(tdl_68_n), .res(sym_res_12_n) );
defparam U_12_sym_add.IN_WIDTH = 15;
defparam U_12_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_13_n;
uadd_cen U_13_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_13_n), .bin(tdl_67_n), .res(sym_res_13_n) );
defparam U_13_sym_add.IN_WIDTH = 15;
defparam U_13_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_14_n;
uadd_cen U_14_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_14_n), .bin(tdl_66_n), .res(sym_res_14_n) );
defparam U_14_sym_add.IN_WIDTH = 15;
defparam U_14_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_15_n;
uadd_cen U_15_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_15_n), .bin(tdl_65_n), .res(sym_res_15_n) );
defparam U_15_sym_add.IN_WIDTH = 15;
defparam U_15_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_16_n;
uadd_cen U_16_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_16_n), .bin(tdl_64_n), .res(sym_res_16_n) );
defparam U_16_sym_add.IN_WIDTH = 15;
defparam U_16_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_17_n;
uadd_cen U_17_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_17_n), .bin(tdl_63_n), .res(sym_res_17_n) );
defparam U_17_sym_add.IN_WIDTH = 15;
defparam U_17_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_18_n;
uadd_cen U_18_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_18_n), .bin(tdl_62_n), .res(sym_res_18_n) );
defparam U_18_sym_add.IN_WIDTH = 15;
defparam U_18_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_19_n;
uadd_cen U_19_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_19_n), .bin(tdl_61_n), .res(sym_res_19_n) );
defparam U_19_sym_add.IN_WIDTH = 15;
defparam U_19_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_20_n;
uadd_cen U_20_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_20_n), .bin(tdl_60_n), .res(sym_res_20_n) );
defparam U_20_sym_add.IN_WIDTH = 15;
defparam U_20_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_21_n;
uadd_cen U_21_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_21_n), .bin(tdl_59_n), .res(sym_res_21_n) );
defparam U_21_sym_add.IN_WIDTH = 15;
defparam U_21_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_22_n;
uadd_cen U_22_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_22_n), .bin(tdl_58_n), .res(sym_res_22_n) );
defparam U_22_sym_add.IN_WIDTH = 15;
defparam U_22_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_23_n;
uadd_cen U_23_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_23_n), .bin(tdl_57_n), .res(sym_res_23_n) );
defparam U_23_sym_add.IN_WIDTH = 15;
defparam U_23_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_24_n;
uadd_cen U_24_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_24_n), .bin(tdl_56_n), .res(sym_res_24_n) );
defparam U_24_sym_add.IN_WIDTH = 15;
defparam U_24_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_25_n;
uadd_cen U_25_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_25_n), .bin(tdl_55_n), .res(sym_res_25_n) );
defparam U_25_sym_add.IN_WIDTH = 15;
defparam U_25_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_26_n;
uadd_cen U_26_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_26_n), .bin(tdl_54_n), .res(sym_res_26_n) );
defparam U_26_sym_add.IN_WIDTH = 15;
defparam U_26_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_27_n;
uadd_cen U_27_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_27_n), .bin(tdl_53_n), .res(sym_res_27_n) );
defparam U_27_sym_add.IN_WIDTH = 15;
defparam U_27_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_28_n;
uadd_cen U_28_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_28_n), .bin(tdl_52_n), .res(sym_res_28_n) );
defparam U_28_sym_add.IN_WIDTH = 15;
defparam U_28_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_29_n;
uadd_cen U_29_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_29_n), .bin(tdl_51_n), .res(sym_res_29_n) );
defparam U_29_sym_add.IN_WIDTH = 15;
defparam U_29_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_30_n;
uadd_cen U_30_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_30_n), .bin(tdl_50_n), .res(sym_res_30_n) );
defparam U_30_sym_add.IN_WIDTH = 15;
defparam U_30_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_31_n;
uadd_cen U_31_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_31_n), .bin(tdl_49_n), .res(sym_res_31_n) );
defparam U_31_sym_add.IN_WIDTH = 15;
defparam U_31_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_32_n;
uadd_cen U_32_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_32_n), .bin(tdl_48_n), .res(sym_res_32_n) );
defparam U_32_sym_add.IN_WIDTH = 15;
defparam U_32_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_33_n;
uadd_cen U_33_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_33_n), .bin(tdl_47_n), .res(sym_res_33_n) );
defparam U_33_sym_add.IN_WIDTH = 15;
defparam U_33_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_34_n;
uadd_cen U_34_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_34_n), .bin(tdl_46_n), .res(sym_res_34_n) );
defparam U_34_sym_add.IN_WIDTH = 15;
defparam U_34_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_35_n;
uadd_cen U_35_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_35_n), .bin(tdl_45_n), .res(sym_res_35_n) );
defparam U_35_sym_add.IN_WIDTH = 15;
defparam U_35_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_36_n;
uadd_cen U_36_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_36_n), .bin(tdl_44_n), .res(sym_res_36_n) );
defparam U_36_sym_add.IN_WIDTH = 15;
defparam U_36_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_37_n;
uadd_cen U_37_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_37_n), .bin(tdl_43_n), .res(sym_res_37_n) );
defparam U_37_sym_add.IN_WIDTH = 15;
defparam U_37_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_38_n;
uadd_cen U_38_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_38_n), .bin(tdl_42_n), .res(sym_res_38_n) );
defparam U_38_sym_add.IN_WIDTH = 15;
defparam U_38_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_39_n;
uadd_cen U_39_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_39_n), .bin(tdl_41_n), .res(sym_res_39_n) );
defparam U_39_sym_add.IN_WIDTH = 15;
defparam U_39_sym_add.PIPE_DEPTH = 1;
wire [15:0] sym_res_40_n;
uadd_cen U_40_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_40_n), .bin(15'd0), .res(sym_res_40_n) );
defparam U_40_sym_add.IN_WIDTH = 15;
defparam U_40_sym_add.PIPE_DEPTH = 1;
wire [13:0] lut_val_0_n_0_pp;
rom_lut_r_cen Ur0_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[0],sym_res_2_n[0],sym_res_1_n[0],sym_res_0_n[0] } ), .data_out( lut_val_0_n_0_pp[6:0]) ) ;
defparam Ur0_n_0_pp.DATA_WIDTH = 7;
defparam Ur0_n_0_pp.C0 = 7'd 0;
defparam Ur0_n_0_pp.C1 = 7'd 6;
defparam Ur0_n_0_pp.C2 = 7'd 121;
defparam Ur0_n_0_pp.C3 = 7'd 127;
defparam Ur0_n_0_pp.C4 = 7'd 101;
defparam Ur0_n_0_pp.C5 = 7'd 107;
defparam Ur0_n_0_pp.C6 = 7'd 94;
defparam Ur0_n_0_pp.C7 = 7'd 100;
defparam Ur0_n_0_pp.C8 = 7'd 101;
defparam Ur0_n_0_pp.C9 = 7'd 107;
defparam Ur0_n_0_pp.CA = 7'd 94;
defparam Ur0_n_0_pp.CB = 7'd 100;
defparam Ur0_n_0_pp.CC = 7'd 74;
defparam Ur0_n_0_pp.CD = 7'd 80;
defparam Ur0_n_0_pp.CE = 7'd 67;
defparam Ur0_n_0_pp.CF = 7'd 73;
assign lut_val_0_n_0_pp[13] = lut_val_0_n_0_pp[6];
assign lut_val_0_n_0_pp[12] = lut_val_0_n_0_pp[6];
assign lut_val_0_n_0_pp[11] = lut_val_0_n_0_pp[6];
assign lut_val_0_n_0_pp[10] = lut_val_0_n_0_pp[6];
assign lut_val_0_n_0_pp[9] = lut_val_0_n_0_pp[6];
assign lut_val_0_n_0_pp[8] = lut_val_0_n_0_pp[6];
assign lut_val_0_n_0_pp[7] = lut_val_0_n_0_pp[6];
wire [13:0] lut_val_0_n_1_pp;
rom_lut_r_cen Ur0_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[1],sym_res_2_n[1],sym_res_1_n[1],sym_res_0_n[1] } ), .data_out( lut_val_0_n_1_pp[6:0]) ) ;
defparam Ur0_n_1_pp.DATA_WIDTH = 7;
defparam Ur0_n_1_pp.C0 = 7'd 0;
defparam Ur0_n_1_pp.C1 = 7'd 6;
defparam Ur0_n_1_pp.C2 = 7'd 121;
defparam Ur0_n_1_pp.C3 = 7'd 127;
defparam Ur0_n_1_pp.C4 = 7'd 101;
defparam Ur0_n_1_pp.C5 = 7'd 107;
defparam Ur0_n_1_pp.C6 = 7'd 94;
defparam Ur0_n_1_pp.C7 = 7'd 100;
defparam Ur0_n_1_pp.C8 = 7'd 101;
defparam Ur0_n_1_pp.C9 = 7'd 107;
defparam Ur0_n_1_pp.CA = 7'd 94;
defparam Ur0_n_1_pp.CB = 7'd 100;
defparam Ur0_n_1_pp.CC = 7'd 74;
defparam Ur0_n_1_pp.CD = 7'd 80;
defparam Ur0_n_1_pp.CE = 7'd 67;
defparam Ur0_n_1_pp.CF = 7'd 73;
assign lut_val_0_n_1_pp[13] = lut_val_0_n_1_pp[6];
assign lut_val_0_n_1_pp[12] = lut_val_0_n_1_pp[6];
assign lut_val_0_n_1_pp[11] = lut_val_0_n_1_pp[6];
assign lut_val_0_n_1_pp[10] = lut_val_0_n_1_pp[6];
assign lut_val_0_n_1_pp[9] = lut_val_0_n_1_pp[6];
assign lut_val_0_n_1_pp[8] = lut_val_0_n_1_pp[6];
assign lut_val_0_n_1_pp[7] = lut_val_0_n_1_pp[6];
wire [13:0] lut_val_0_n_2_pp;
rom_lut_r_cen Ur0_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[2],sym_res_2_n[2],sym_res_1_n[2],sym_res_0_n[2] } ), .data_out( lut_val_0_n_2_pp[6:0]) ) ;
defparam Ur0_n_2_pp.DATA_WIDTH = 7;
defparam Ur0_n_2_pp.C0 = 7'd 0;
defparam Ur0_n_2_pp.C1 = 7'd 6;
defparam Ur0_n_2_pp.C2 = 7'd 121;
defparam Ur0_n_2_pp.C3 = 7'd 127;
defparam Ur0_n_2_pp.C4 = 7'd 101;
defparam Ur0_n_2_pp.C5 = 7'd 107;
defparam Ur0_n_2_pp.C6 = 7'd 94;
defparam Ur0_n_2_pp.C7 = 7'd 100;
defparam Ur0_n_2_pp.C8 = 7'd 101;
defparam Ur0_n_2_pp.C9 = 7'd 107;
defparam Ur0_n_2_pp.CA = 7'd 94;
defparam Ur0_n_2_pp.CB = 7'd 100;
defparam Ur0_n_2_pp.CC = 7'd 74;
defparam Ur0_n_2_pp.CD = 7'd 80;
defparam Ur0_n_2_pp.CE = 7'd 67;
defparam Ur0_n_2_pp.CF = 7'd 73;
assign lut_val_0_n_2_pp[13] = lut_val_0_n_2_pp[6];
assign lut_val_0_n_2_pp[12] = lut_val_0_n_2_pp[6];
assign lut_val_0_n_2_pp[11] = lut_val_0_n_2_pp[6];
assign lut_val_0_n_2_pp[10] = lut_val_0_n_2_pp[6];
assign lut_val_0_n_2_pp[9] = lut_val_0_n_2_pp[6];
assign lut_val_0_n_2_pp[8] = lut_val_0_n_2_pp[6];
assign lut_val_0_n_2_pp[7] = lut_val_0_n_2_pp[6];
wire [13:0] lut_val_0_n_3_pp;
rom_lut_r_cen Ur0_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[3],sym_res_2_n[3],sym_res_1_n[3],sym_res_0_n[3] } ), .data_out( lut_val_0_n_3_pp[6:0]) ) ;
defparam Ur0_n_3_pp.DATA_WIDTH = 7;
defparam Ur0_n_3_pp.C0 = 7'd 0;
defparam Ur0_n_3_pp.C1 = 7'd 6;
defparam Ur0_n_3_pp.C2 = 7'd 121;
defparam Ur0_n_3_pp.C3 = 7'd 127;
defparam Ur0_n_3_pp.C4 = 7'd 101;
defparam Ur0_n_3_pp.C5 = 7'd 107;
defparam Ur0_n_3_pp.C6 = 7'd 94;
defparam Ur0_n_3_pp.C7 = 7'd 100;
defparam Ur0_n_3_pp.C8 = 7'd 101;
defparam Ur0_n_3_pp.C9 = 7'd 107;
defparam Ur0_n_3_pp.CA = 7'd 94;
defparam Ur0_n_3_pp.CB = 7'd 100;
defparam Ur0_n_3_pp.CC = 7'd 74;
defparam Ur0_n_3_pp.CD = 7'd 80;
defparam Ur0_n_3_pp.CE = 7'd 67;
defparam Ur0_n_3_pp.CF = 7'd 73;
assign lut_val_0_n_3_pp[13] = lut_val_0_n_3_pp[6];
assign lut_val_0_n_3_pp[12] = lut_val_0_n_3_pp[6];
assign lut_val_0_n_3_pp[11] = lut_val_0_n_3_pp[6];
assign lut_val_0_n_3_pp[10] = lut_val_0_n_3_pp[6];
assign lut_val_0_n_3_pp[9] = lut_val_0_n_3_pp[6];
assign lut_val_0_n_3_pp[8] = lut_val_0_n_3_pp[6];
assign lut_val_0_n_3_pp[7] = lut_val_0_n_3_pp[6];
wire [13:0] lut_val_0_n_4_pp;
rom_lut_r_cen Ur0_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[4],sym_res_2_n[4],sym_res_1_n[4],sym_res_0_n[4] } ), .data_out( lut_val_0_n_4_pp[6:0]) ) ;
defparam Ur0_n_4_pp.DATA_WIDTH = 7;
defparam Ur0_n_4_pp.C0 = 7'd 0;
defparam Ur0_n_4_pp.C1 = 7'd 6;
defparam Ur0_n_4_pp.C2 = 7'd 121;
defparam Ur0_n_4_pp.C3 = 7'd 127;
defparam Ur0_n_4_pp.C4 = 7'd 101;
defparam Ur0_n_4_pp.C5 = 7'd 107;
defparam Ur0_n_4_pp.C6 = 7'd 94;
defparam Ur0_n_4_pp.C7 = 7'd 100;
defparam Ur0_n_4_pp.C8 = 7'd 101;
defparam Ur0_n_4_pp.C9 = 7'd 107;
defparam Ur0_n_4_pp.CA = 7'd 94;
defparam Ur0_n_4_pp.CB = 7'd 100;
defparam Ur0_n_4_pp.CC = 7'd 74;
defparam Ur0_n_4_pp.CD = 7'd 80;
defparam Ur0_n_4_pp.CE = 7'd 67;
defparam Ur0_n_4_pp.CF = 7'd 73;
assign lut_val_0_n_4_pp[13] = lut_val_0_n_4_pp[6];
assign lut_val_0_n_4_pp[12] = lut_val_0_n_4_pp[6];
assign lut_val_0_n_4_pp[11] = lut_val_0_n_4_pp[6];
assign lut_val_0_n_4_pp[10] = lut_val_0_n_4_pp[6];
assign lut_val_0_n_4_pp[9] = lut_val_0_n_4_pp[6];
assign lut_val_0_n_4_pp[8] = lut_val_0_n_4_pp[6];
assign lut_val_0_n_4_pp[7] = lut_val_0_n_4_pp[6];
wire [13:0] lut_val_0_n_5_pp;
rom_lut_r_cen Ur0_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[5],sym_res_2_n[5],sym_res_1_n[5],sym_res_0_n[5] } ), .data_out( lut_val_0_n_5_pp[6:0]) ) ;
defparam Ur0_n_5_pp.DATA_WIDTH = 7;
defparam Ur0_n_5_pp.C0 = 7'd 0;
defparam Ur0_n_5_pp.C1 = 7'd 6;
defparam Ur0_n_5_pp.C2 = 7'd 121;
defparam Ur0_n_5_pp.C3 = 7'd 127;
defparam Ur0_n_5_pp.C4 = 7'd 101;
defparam Ur0_n_5_pp.C5 = 7'd 107;
defparam Ur0_n_5_pp.C6 = 7'd 94;
defparam Ur0_n_5_pp.C7 = 7'd 100;
defparam Ur0_n_5_pp.C8 = 7'd 101;
defparam Ur0_n_5_pp.C9 = 7'd 107;
defparam Ur0_n_5_pp.CA = 7'd 94;
defparam Ur0_n_5_pp.CB = 7'd 100;
defparam Ur0_n_5_pp.CC = 7'd 74;
defparam Ur0_n_5_pp.CD = 7'd 80;
defparam Ur0_n_5_pp.CE = 7'd 67;
defparam Ur0_n_5_pp.CF = 7'd 73;
assign lut_val_0_n_5_pp[13] = lut_val_0_n_5_pp[6];
assign lut_val_0_n_5_pp[12] = lut_val_0_n_5_pp[6];
assign lut_val_0_n_5_pp[11] = lut_val_0_n_5_pp[6];
assign lut_val_0_n_5_pp[10] = lut_val_0_n_5_pp[6];
assign lut_val_0_n_5_pp[9] = lut_val_0_n_5_pp[6];
assign lut_val_0_n_5_pp[8] = lut_val_0_n_5_pp[6];
assign lut_val_0_n_5_pp[7] = lut_val_0_n_5_pp[6];
wire [13:0] lut_val_0_n_6_pp;
rom_lut_r_cen Ur0_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[6],sym_res_2_n[6],sym_res_1_n[6],sym_res_0_n[6] } ), .data_out( lut_val_0_n_6_pp[6:0]) ) ;
defparam Ur0_n_6_pp.DATA_WIDTH = 7;
defparam Ur0_n_6_pp.C0 = 7'd 0;
defparam Ur0_n_6_pp.C1 = 7'd 6;
defparam Ur0_n_6_pp.C2 = 7'd 121;
defparam Ur0_n_6_pp.C3 = 7'd 127;
defparam Ur0_n_6_pp.C4 = 7'd 101;
defparam Ur0_n_6_pp.C5 = 7'd 107;
defparam Ur0_n_6_pp.C6 = 7'd 94;
defparam Ur0_n_6_pp.C7 = 7'd 100;
defparam Ur0_n_6_pp.C8 = 7'd 101;
defparam Ur0_n_6_pp.C9 = 7'd 107;
defparam Ur0_n_6_pp.CA = 7'd 94;
defparam Ur0_n_6_pp.CB = 7'd 100;
defparam Ur0_n_6_pp.CC = 7'd 74;
defparam Ur0_n_6_pp.CD = 7'd 80;
defparam Ur0_n_6_pp.CE = 7'd 67;
defparam Ur0_n_6_pp.CF = 7'd 73;
assign lut_val_0_n_6_pp[13] = lut_val_0_n_6_pp[6];
assign lut_val_0_n_6_pp[12] = lut_val_0_n_6_pp[6];
assign lut_val_0_n_6_pp[11] = lut_val_0_n_6_pp[6];
assign lut_val_0_n_6_pp[10] = lut_val_0_n_6_pp[6];
assign lut_val_0_n_6_pp[9] = lut_val_0_n_6_pp[6];
assign lut_val_0_n_6_pp[8] = lut_val_0_n_6_pp[6];
assign lut_val_0_n_6_pp[7] = lut_val_0_n_6_pp[6];
wire [13:0] lut_val_0_n_7_pp;
rom_lut_r_cen Ur0_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[7],sym_res_2_n[7],sym_res_1_n[7],sym_res_0_n[7] } ), .data_out( lut_val_0_n_7_pp[6:0]) ) ;
defparam Ur0_n_7_pp.DATA_WIDTH = 7;
defparam Ur0_n_7_pp.C0 = 7'd 0;
defparam Ur0_n_7_pp.C1 = 7'd 6;
defparam Ur0_n_7_pp.C2 = 7'd 121;
defparam Ur0_n_7_pp.C3 = 7'd 127;
defparam Ur0_n_7_pp.C4 = 7'd 101;
defparam Ur0_n_7_pp.C5 = 7'd 107;
defparam Ur0_n_7_pp.C6 = 7'd 94;
defparam Ur0_n_7_pp.C7 = 7'd 100;
defparam Ur0_n_7_pp.C8 = 7'd 101;
defparam Ur0_n_7_pp.C9 = 7'd 107;
defparam Ur0_n_7_pp.CA = 7'd 94;
defparam Ur0_n_7_pp.CB = 7'd 100;
defparam Ur0_n_7_pp.CC = 7'd 74;
defparam Ur0_n_7_pp.CD = 7'd 80;
defparam Ur0_n_7_pp.CE = 7'd 67;
defparam Ur0_n_7_pp.CF = 7'd 73;
assign lut_val_0_n_7_pp[13] = lut_val_0_n_7_pp[6];
assign lut_val_0_n_7_pp[12] = lut_val_0_n_7_pp[6];
assign lut_val_0_n_7_pp[11] = lut_val_0_n_7_pp[6];
assign lut_val_0_n_7_pp[10] = lut_val_0_n_7_pp[6];
assign lut_val_0_n_7_pp[9] = lut_val_0_n_7_pp[6];
assign lut_val_0_n_7_pp[8] = lut_val_0_n_7_pp[6];
assign lut_val_0_n_7_pp[7] = lut_val_0_n_7_pp[6];
wire [13:0] lut_val_0_n_8_pp;
rom_lut_r_cen Ur0_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[8],sym_res_2_n[8],sym_res_1_n[8],sym_res_0_n[8] } ), .data_out( lut_val_0_n_8_pp[6:0]) ) ;
defparam Ur0_n_8_pp.DATA_WIDTH = 7;
defparam Ur0_n_8_pp.C0 = 7'd 0;
defparam Ur0_n_8_pp.C1 = 7'd 6;
defparam Ur0_n_8_pp.C2 = 7'd 121;
defparam Ur0_n_8_pp.C3 = 7'd 127;
defparam Ur0_n_8_pp.C4 = 7'd 101;
defparam Ur0_n_8_pp.C5 = 7'd 107;
defparam Ur0_n_8_pp.C6 = 7'd 94;
defparam Ur0_n_8_pp.C7 = 7'd 100;
defparam Ur0_n_8_pp.C8 = 7'd 101;
defparam Ur0_n_8_pp.C9 = 7'd 107;
defparam Ur0_n_8_pp.CA = 7'd 94;
defparam Ur0_n_8_pp.CB = 7'd 100;
defparam Ur0_n_8_pp.CC = 7'd 74;
defparam Ur0_n_8_pp.CD = 7'd 80;
defparam Ur0_n_8_pp.CE = 7'd 67;
defparam Ur0_n_8_pp.CF = 7'd 73;
assign lut_val_0_n_8_pp[13] = lut_val_0_n_8_pp[6];
assign lut_val_0_n_8_pp[12] = lut_val_0_n_8_pp[6];
assign lut_val_0_n_8_pp[11] = lut_val_0_n_8_pp[6];
assign lut_val_0_n_8_pp[10] = lut_val_0_n_8_pp[6];
assign lut_val_0_n_8_pp[9] = lut_val_0_n_8_pp[6];
assign lut_val_0_n_8_pp[8] = lut_val_0_n_8_pp[6];
assign lut_val_0_n_8_pp[7] = lut_val_0_n_8_pp[6];
wire [13:0] lut_val_0_n_9_pp;
rom_lut_r_cen Ur0_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[9],sym_res_2_n[9],sym_res_1_n[9],sym_res_0_n[9] } ), .data_out( lut_val_0_n_9_pp[6:0]) ) ;
defparam Ur0_n_9_pp.DATA_WIDTH = 7;
defparam Ur0_n_9_pp.C0 = 7'd 0;
defparam Ur0_n_9_pp.C1 = 7'd 6;
defparam Ur0_n_9_pp.C2 = 7'd 121;
defparam Ur0_n_9_pp.C3 = 7'd 127;
defparam Ur0_n_9_pp.C4 = 7'd 101;
defparam Ur0_n_9_pp.C5 = 7'd 107;
defparam Ur0_n_9_pp.C6 = 7'd 94;
defparam Ur0_n_9_pp.C7 = 7'd 100;
defparam Ur0_n_9_pp.C8 = 7'd 101;
defparam Ur0_n_9_pp.C9 = 7'd 107;
defparam Ur0_n_9_pp.CA = 7'd 94;
defparam Ur0_n_9_pp.CB = 7'd 100;
defparam Ur0_n_9_pp.CC = 7'd 74;
defparam Ur0_n_9_pp.CD = 7'd 80;
defparam Ur0_n_9_pp.CE = 7'd 67;
defparam Ur0_n_9_pp.CF = 7'd 73;
assign lut_val_0_n_9_pp[13] = lut_val_0_n_9_pp[6];
assign lut_val_0_n_9_pp[12] = lut_val_0_n_9_pp[6];
assign lut_val_0_n_9_pp[11] = lut_val_0_n_9_pp[6];
assign lut_val_0_n_9_pp[10] = lut_val_0_n_9_pp[6];
assign lut_val_0_n_9_pp[9] = lut_val_0_n_9_pp[6];
assign lut_val_0_n_9_pp[8] = lut_val_0_n_9_pp[6];
assign lut_val_0_n_9_pp[7] = lut_val_0_n_9_pp[6];
wire [13:0] lut_val_0_n_10_pp;
rom_lut_r_cen Ur0_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[10],sym_res_2_n[10],sym_res_1_n[10],sym_res_0_n[10] } ), .data_out( lut_val_0_n_10_pp[6:0]) ) ;
defparam Ur0_n_10_pp.DATA_WIDTH = 7;
defparam Ur0_n_10_pp.C0 = 7'd 0;
defparam Ur0_n_10_pp.C1 = 7'd 6;
defparam Ur0_n_10_pp.C2 = 7'd 121;
defparam Ur0_n_10_pp.C3 = 7'd 127;
defparam Ur0_n_10_pp.C4 = 7'd 101;
defparam Ur0_n_10_pp.C5 = 7'd 107;
defparam Ur0_n_10_pp.C6 = 7'd 94;
defparam Ur0_n_10_pp.C7 = 7'd 100;
defparam Ur0_n_10_pp.C8 = 7'd 101;
defparam Ur0_n_10_pp.C9 = 7'd 107;
defparam Ur0_n_10_pp.CA = 7'd 94;
defparam Ur0_n_10_pp.CB = 7'd 100;
defparam Ur0_n_10_pp.CC = 7'd 74;
defparam Ur0_n_10_pp.CD = 7'd 80;
defparam Ur0_n_10_pp.CE = 7'd 67;
defparam Ur0_n_10_pp.CF = 7'd 73;
assign lut_val_0_n_10_pp[13] = lut_val_0_n_10_pp[6];
assign lut_val_0_n_10_pp[12] = lut_val_0_n_10_pp[6];
assign lut_val_0_n_10_pp[11] = lut_val_0_n_10_pp[6];
assign lut_val_0_n_10_pp[10] = lut_val_0_n_10_pp[6];
assign lut_val_0_n_10_pp[9] = lut_val_0_n_10_pp[6];
assign lut_val_0_n_10_pp[8] = lut_val_0_n_10_pp[6];
assign lut_val_0_n_10_pp[7] = lut_val_0_n_10_pp[6];
wire [13:0] lut_val_0_n_11_pp;
rom_lut_r_cen Ur0_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[11],sym_res_2_n[11],sym_res_1_n[11],sym_res_0_n[11] } ), .data_out( lut_val_0_n_11_pp[6:0]) ) ;
defparam Ur0_n_11_pp.DATA_WIDTH = 7;
defparam Ur0_n_11_pp.C0 = 7'd 0;
defparam Ur0_n_11_pp.C1 = 7'd 6;
defparam Ur0_n_11_pp.C2 = 7'd 121;
defparam Ur0_n_11_pp.C3 = 7'd 127;
defparam Ur0_n_11_pp.C4 = 7'd 101;
defparam Ur0_n_11_pp.C5 = 7'd 107;
defparam Ur0_n_11_pp.C6 = 7'd 94;
defparam Ur0_n_11_pp.C7 = 7'd 100;
defparam Ur0_n_11_pp.C8 = 7'd 101;
defparam Ur0_n_11_pp.C9 = 7'd 107;
defparam Ur0_n_11_pp.CA = 7'd 94;
defparam Ur0_n_11_pp.CB = 7'd 100;
defparam Ur0_n_11_pp.CC = 7'd 74;
defparam Ur0_n_11_pp.CD = 7'd 80;
defparam Ur0_n_11_pp.CE = 7'd 67;
defparam Ur0_n_11_pp.CF = 7'd 73;
assign lut_val_0_n_11_pp[13] = lut_val_0_n_11_pp[6];
assign lut_val_0_n_11_pp[12] = lut_val_0_n_11_pp[6];
assign lut_val_0_n_11_pp[11] = lut_val_0_n_11_pp[6];
assign lut_val_0_n_11_pp[10] = lut_val_0_n_11_pp[6];
assign lut_val_0_n_11_pp[9] = lut_val_0_n_11_pp[6];
assign lut_val_0_n_11_pp[8] = lut_val_0_n_11_pp[6];
assign lut_val_0_n_11_pp[7] = lut_val_0_n_11_pp[6];
wire [13:0] lut_val_0_n_12_pp;
rom_lut_r_cen Ur0_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[12],sym_res_2_n[12],sym_res_1_n[12],sym_res_0_n[12] } ), .data_out( lut_val_0_n_12_pp[6:0]) ) ;
defparam Ur0_n_12_pp.DATA_WIDTH = 7;
defparam Ur0_n_12_pp.C0 = 7'd 0;
defparam Ur0_n_12_pp.C1 = 7'd 6;
defparam Ur0_n_12_pp.C2 = 7'd 121;
defparam Ur0_n_12_pp.C3 = 7'd 127;
defparam Ur0_n_12_pp.C4 = 7'd 101;
defparam Ur0_n_12_pp.C5 = 7'd 107;
defparam Ur0_n_12_pp.C6 = 7'd 94;
defparam Ur0_n_12_pp.C7 = 7'd 100;
defparam Ur0_n_12_pp.C8 = 7'd 101;
defparam Ur0_n_12_pp.C9 = 7'd 107;
defparam Ur0_n_12_pp.CA = 7'd 94;
defparam Ur0_n_12_pp.CB = 7'd 100;
defparam Ur0_n_12_pp.CC = 7'd 74;
defparam Ur0_n_12_pp.CD = 7'd 80;
defparam Ur0_n_12_pp.CE = 7'd 67;
defparam Ur0_n_12_pp.CF = 7'd 73;
assign lut_val_0_n_12_pp[13] = lut_val_0_n_12_pp[6];
assign lut_val_0_n_12_pp[12] = lut_val_0_n_12_pp[6];
assign lut_val_0_n_12_pp[11] = lut_val_0_n_12_pp[6];
assign lut_val_0_n_12_pp[10] = lut_val_0_n_12_pp[6];
assign lut_val_0_n_12_pp[9] = lut_val_0_n_12_pp[6];
assign lut_val_0_n_12_pp[8] = lut_val_0_n_12_pp[6];
assign lut_val_0_n_12_pp[7] = lut_val_0_n_12_pp[6];
wire [13:0] lut_val_0_n_13_pp;
rom_lut_r_cen Ur0_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[13],sym_res_2_n[13],sym_res_1_n[13],sym_res_0_n[13] } ), .data_out( lut_val_0_n_13_pp[6:0]) ) ;
defparam Ur0_n_13_pp.DATA_WIDTH = 7;
defparam Ur0_n_13_pp.C0 = 7'd 0;
defparam Ur0_n_13_pp.C1 = 7'd 6;
defparam Ur0_n_13_pp.C2 = 7'd 121;
defparam Ur0_n_13_pp.C3 = 7'd 127;
defparam Ur0_n_13_pp.C4 = 7'd 101;
defparam Ur0_n_13_pp.C5 = 7'd 107;
defparam Ur0_n_13_pp.C6 = 7'd 94;
defparam Ur0_n_13_pp.C7 = 7'd 100;
defparam Ur0_n_13_pp.C8 = 7'd 101;
defparam Ur0_n_13_pp.C9 = 7'd 107;
defparam Ur0_n_13_pp.CA = 7'd 94;
defparam Ur0_n_13_pp.CB = 7'd 100;
defparam Ur0_n_13_pp.CC = 7'd 74;
defparam Ur0_n_13_pp.CD = 7'd 80;
defparam Ur0_n_13_pp.CE = 7'd 67;
defparam Ur0_n_13_pp.CF = 7'd 73;
assign lut_val_0_n_13_pp[13] = lut_val_0_n_13_pp[6];
assign lut_val_0_n_13_pp[12] = lut_val_0_n_13_pp[6];
assign lut_val_0_n_13_pp[11] = lut_val_0_n_13_pp[6];
assign lut_val_0_n_13_pp[10] = lut_val_0_n_13_pp[6];
assign lut_val_0_n_13_pp[9] = lut_val_0_n_13_pp[6];
assign lut_val_0_n_13_pp[8] = lut_val_0_n_13_pp[6];
assign lut_val_0_n_13_pp[7] = lut_val_0_n_13_pp[6];
wire [13:0] lut_val_0_n_14_pp;
rom_lut_r_cen Ur0_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[14],sym_res_2_n[14],sym_res_1_n[14],sym_res_0_n[14] } ), .data_out( lut_val_0_n_14_pp[6:0]) ) ;
defparam Ur0_n_14_pp.DATA_WIDTH = 7;
defparam Ur0_n_14_pp.C0 = 7'd 0;
defparam Ur0_n_14_pp.C1 = 7'd 6;
defparam Ur0_n_14_pp.C2 = 7'd 121;
defparam Ur0_n_14_pp.C3 = 7'd 127;
defparam Ur0_n_14_pp.C4 = 7'd 101;
defparam Ur0_n_14_pp.C5 = 7'd 107;
defparam Ur0_n_14_pp.C6 = 7'd 94;
defparam Ur0_n_14_pp.C7 = 7'd 100;
defparam Ur0_n_14_pp.C8 = 7'd 101;
defparam Ur0_n_14_pp.C9 = 7'd 107;
defparam Ur0_n_14_pp.CA = 7'd 94;
defparam Ur0_n_14_pp.CB = 7'd 100;
defparam Ur0_n_14_pp.CC = 7'd 74;
defparam Ur0_n_14_pp.CD = 7'd 80;
defparam Ur0_n_14_pp.CE = 7'd 67;
defparam Ur0_n_14_pp.CF = 7'd 73;
assign lut_val_0_n_14_pp[13] = lut_val_0_n_14_pp[6];
assign lut_val_0_n_14_pp[12] = lut_val_0_n_14_pp[6];
assign lut_val_0_n_14_pp[11] = lut_val_0_n_14_pp[6];
assign lut_val_0_n_14_pp[10] = lut_val_0_n_14_pp[6];
assign lut_val_0_n_14_pp[9] = lut_val_0_n_14_pp[6];
assign lut_val_0_n_14_pp[8] = lut_val_0_n_14_pp[6];
assign lut_val_0_n_14_pp[7] = lut_val_0_n_14_pp[6];
wire [13:0] lut_val_0_n_15_pp;
rom_lut_r_cen Ur0_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[15],sym_res_2_n[15],sym_res_1_n[15],sym_res_0_n[15] } ), .data_out( lut_val_0_n_15_pp[6:0]) ) ;
defparam Ur0_n_15_pp.DATA_WIDTH = 7;
defparam Ur0_n_15_pp.C0 = 7'd 0;
defparam Ur0_n_15_pp.C1 = 7'd 6;
defparam Ur0_n_15_pp.C2 = 7'd 121;
defparam Ur0_n_15_pp.C3 = 7'd 127;
defparam Ur0_n_15_pp.C4 = 7'd 101;
defparam Ur0_n_15_pp.C5 = 7'd 107;
defparam Ur0_n_15_pp.C6 = 7'd 94;
defparam Ur0_n_15_pp.C7 = 7'd 100;
defparam Ur0_n_15_pp.C8 = 7'd 101;
defparam Ur0_n_15_pp.C9 = 7'd 107;
defparam Ur0_n_15_pp.CA = 7'd 94;
defparam Ur0_n_15_pp.CB = 7'd 100;
defparam Ur0_n_15_pp.CC = 7'd 74;
defparam Ur0_n_15_pp.CD = 7'd 80;
defparam Ur0_n_15_pp.CE = 7'd 67;
defparam Ur0_n_15_pp.CF = 7'd 73;
assign lut_val_0_n_15_pp[13] = lut_val_0_n_15_pp[6];
assign lut_val_0_n_15_pp[12] = lut_val_0_n_15_pp[6];
assign lut_val_0_n_15_pp[11] = lut_val_0_n_15_pp[6];
assign lut_val_0_n_15_pp[10] = lut_val_0_n_15_pp[6];
assign lut_val_0_n_15_pp[9] = lut_val_0_n_15_pp[6];
assign lut_val_0_n_15_pp[8] = lut_val_0_n_15_pp[6];
assign lut_val_0_n_15_pp[7] = lut_val_0_n_15_pp[6];
wire [13:0] lut_val_1_n_0_pp;
rom_lut_r_cen Ur1_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[0],sym_res_6_n[0],sym_res_5_n[0],sym_res_4_n[0] } ), .data_out( lut_val_1_n_0_pp[5:0]) ) ;
defparam Ur1_n_0_pp.DATA_WIDTH = 6;
defparam Ur1_n_0_pp.C0 = 6'd 0;
defparam Ur1_n_0_pp.C1 = 6'd 49;
defparam Ur1_n_0_pp.C2 = 6'd 9;
defparam Ur1_n_0_pp.C3 = 6'd 58;
defparam Ur1_n_0_pp.C4 = 6'd 10;
defparam Ur1_n_0_pp.C5 = 6'd 59;
defparam Ur1_n_0_pp.C6 = 6'd 19;
defparam Ur1_n_0_pp.C7 = 6'd 4;
defparam Ur1_n_0_pp.C8 = 6'd 57;
defparam Ur1_n_0_pp.C9 = 6'd 42;
defparam Ur1_n_0_pp.CA = 6'd 2;
defparam Ur1_n_0_pp.CB = 6'd 51;
defparam Ur1_n_0_pp.CC = 6'd 3;
defparam Ur1_n_0_pp.CD = 6'd 52;
defparam Ur1_n_0_pp.CE = 6'd 12;
defparam Ur1_n_0_pp.CF = 6'd 61;
assign lut_val_1_n_0_pp[13] = lut_val_1_n_0_pp[5];
assign lut_val_1_n_0_pp[12] = lut_val_1_n_0_pp[5];
assign lut_val_1_n_0_pp[11] = lut_val_1_n_0_pp[5];
assign lut_val_1_n_0_pp[10] = lut_val_1_n_0_pp[5];
assign lut_val_1_n_0_pp[9] = lut_val_1_n_0_pp[5];
assign lut_val_1_n_0_pp[8] = lut_val_1_n_0_pp[5];
assign lut_val_1_n_0_pp[7] = lut_val_1_n_0_pp[5];
assign lut_val_1_n_0_pp[6] = lut_val_1_n_0_pp[5];
wire [13:0] lut_val_1_n_1_pp;
rom_lut_r_cen Ur1_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[1],sym_res_6_n[1],sym_res_5_n[1],sym_res_4_n[1] } ), .data_out( lut_val_1_n_1_pp[5:0]) ) ;
defparam Ur1_n_1_pp.DATA_WIDTH = 6;
defparam Ur1_n_1_pp.C0 = 6'd 0;
defparam Ur1_n_1_pp.C1 = 6'd 49;
defparam Ur1_n_1_pp.C2 = 6'd 9;
defparam Ur1_n_1_pp.C3 = 6'd 58;
defparam Ur1_n_1_pp.C4 = 6'd 10;
defparam Ur1_n_1_pp.C5 = 6'd 59;
defparam Ur1_n_1_pp.C6 = 6'd 19;
defparam Ur1_n_1_pp.C7 = 6'd 4;
defparam Ur1_n_1_pp.C8 = 6'd 57;
defparam Ur1_n_1_pp.C9 = 6'd 42;
defparam Ur1_n_1_pp.CA = 6'd 2;
defparam Ur1_n_1_pp.CB = 6'd 51;
defparam Ur1_n_1_pp.CC = 6'd 3;
defparam Ur1_n_1_pp.CD = 6'd 52;
defparam Ur1_n_1_pp.CE = 6'd 12;
defparam Ur1_n_1_pp.CF = 6'd 61;
assign lut_val_1_n_1_pp[13] = lut_val_1_n_1_pp[5];
assign lut_val_1_n_1_pp[12] = lut_val_1_n_1_pp[5];
assign lut_val_1_n_1_pp[11] = lut_val_1_n_1_pp[5];
assign lut_val_1_n_1_pp[10] = lut_val_1_n_1_pp[5];
assign lut_val_1_n_1_pp[9] = lut_val_1_n_1_pp[5];
assign lut_val_1_n_1_pp[8] = lut_val_1_n_1_pp[5];
assign lut_val_1_n_1_pp[7] = lut_val_1_n_1_pp[5];
assign lut_val_1_n_1_pp[6] = lut_val_1_n_1_pp[5];
wire [13:0] lut_val_1_n_2_pp;
rom_lut_r_cen Ur1_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[2],sym_res_6_n[2],sym_res_5_n[2],sym_res_4_n[2] } ), .data_out( lut_val_1_n_2_pp[5:0]) ) ;
defparam Ur1_n_2_pp.DATA_WIDTH = 6;
defparam Ur1_n_2_pp.C0 = 6'd 0;
defparam Ur1_n_2_pp.C1 = 6'd 49;
defparam Ur1_n_2_pp.C2 = 6'd 9;
defparam Ur1_n_2_pp.C3 = 6'd 58;
defparam Ur1_n_2_pp.C4 = 6'd 10;
defparam Ur1_n_2_pp.C5 = 6'd 59;
defparam Ur1_n_2_pp.C6 = 6'd 19;
defparam Ur1_n_2_pp.C7 = 6'd 4;
defparam Ur1_n_2_pp.C8 = 6'd 57;
defparam Ur1_n_2_pp.C9 = 6'd 42;
defparam Ur1_n_2_pp.CA = 6'd 2;
defparam Ur1_n_2_pp.CB = 6'd 51;
defparam Ur1_n_2_pp.CC = 6'd 3;
defparam Ur1_n_2_pp.CD = 6'd 52;
defparam Ur1_n_2_pp.CE = 6'd 12;
defparam Ur1_n_2_pp.CF = 6'd 61;
assign lut_val_1_n_2_pp[13] = lut_val_1_n_2_pp[5];
assign lut_val_1_n_2_pp[12] = lut_val_1_n_2_pp[5];
assign lut_val_1_n_2_pp[11] = lut_val_1_n_2_pp[5];
assign lut_val_1_n_2_pp[10] = lut_val_1_n_2_pp[5];
assign lut_val_1_n_2_pp[9] = lut_val_1_n_2_pp[5];
assign lut_val_1_n_2_pp[8] = lut_val_1_n_2_pp[5];
assign lut_val_1_n_2_pp[7] = lut_val_1_n_2_pp[5];
assign lut_val_1_n_2_pp[6] = lut_val_1_n_2_pp[5];
wire [13:0] lut_val_1_n_3_pp;
rom_lut_r_cen Ur1_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[3],sym_res_6_n[3],sym_res_5_n[3],sym_res_4_n[3] } ), .data_out( lut_val_1_n_3_pp[5:0]) ) ;
defparam Ur1_n_3_pp.DATA_WIDTH = 6;
defparam Ur1_n_3_pp.C0 = 6'd 0;
defparam Ur1_n_3_pp.C1 = 6'd 49;
defparam Ur1_n_3_pp.C2 = 6'd 9;
defparam Ur1_n_3_pp.C3 = 6'd 58;
defparam Ur1_n_3_pp.C4 = 6'd 10;
defparam Ur1_n_3_pp.C5 = 6'd 59;
defparam Ur1_n_3_pp.C6 = 6'd 19;
defparam Ur1_n_3_pp.C7 = 6'd 4;
defparam Ur1_n_3_pp.C8 = 6'd 57;
defparam Ur1_n_3_pp.C9 = 6'd 42;
defparam Ur1_n_3_pp.CA = 6'd 2;
defparam Ur1_n_3_pp.CB = 6'd 51;
defparam Ur1_n_3_pp.CC = 6'd 3;
defparam Ur1_n_3_pp.CD = 6'd 52;
defparam Ur1_n_3_pp.CE = 6'd 12;
defparam Ur1_n_3_pp.CF = 6'd 61;
assign lut_val_1_n_3_pp[13] = lut_val_1_n_3_pp[5];
assign lut_val_1_n_3_pp[12] = lut_val_1_n_3_pp[5];
assign lut_val_1_n_3_pp[11] = lut_val_1_n_3_pp[5];
assign lut_val_1_n_3_pp[10] = lut_val_1_n_3_pp[5];
assign lut_val_1_n_3_pp[9] = lut_val_1_n_3_pp[5];
assign lut_val_1_n_3_pp[8] = lut_val_1_n_3_pp[5];
assign lut_val_1_n_3_pp[7] = lut_val_1_n_3_pp[5];
assign lut_val_1_n_3_pp[6] = lut_val_1_n_3_pp[5];
wire [13:0] lut_val_1_n_4_pp;
rom_lut_r_cen Ur1_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[4],sym_res_6_n[4],sym_res_5_n[4],sym_res_4_n[4] } ), .data_out( lut_val_1_n_4_pp[5:0]) ) ;
defparam Ur1_n_4_pp.DATA_WIDTH = 6;
defparam Ur1_n_4_pp.C0 = 6'd 0;
defparam Ur1_n_4_pp.C1 = 6'd 49;
defparam Ur1_n_4_pp.C2 = 6'd 9;
defparam Ur1_n_4_pp.C3 = 6'd 58;
defparam Ur1_n_4_pp.C4 = 6'd 10;
defparam Ur1_n_4_pp.C5 = 6'd 59;
defparam Ur1_n_4_pp.C6 = 6'd 19;
defparam Ur1_n_4_pp.C7 = 6'd 4;
defparam Ur1_n_4_pp.C8 = 6'd 57;
defparam Ur1_n_4_pp.C9 = 6'd 42;
defparam Ur1_n_4_pp.CA = 6'd 2;
defparam Ur1_n_4_pp.CB = 6'd 51;
defparam Ur1_n_4_pp.CC = 6'd 3;
defparam Ur1_n_4_pp.CD = 6'd 52;
defparam Ur1_n_4_pp.CE = 6'd 12;
defparam Ur1_n_4_pp.CF = 6'd 61;
assign lut_val_1_n_4_pp[13] = lut_val_1_n_4_pp[5];
assign lut_val_1_n_4_pp[12] = lut_val_1_n_4_pp[5];
assign lut_val_1_n_4_pp[11] = lut_val_1_n_4_pp[5];
assign lut_val_1_n_4_pp[10] = lut_val_1_n_4_pp[5];
assign lut_val_1_n_4_pp[9] = lut_val_1_n_4_pp[5];
assign lut_val_1_n_4_pp[8] = lut_val_1_n_4_pp[5];
assign lut_val_1_n_4_pp[7] = lut_val_1_n_4_pp[5];
assign lut_val_1_n_4_pp[6] = lut_val_1_n_4_pp[5];
wire [13:0] lut_val_1_n_5_pp;
rom_lut_r_cen Ur1_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[5],sym_res_6_n[5],sym_res_5_n[5],sym_res_4_n[5] } ), .data_out( lut_val_1_n_5_pp[5:0]) ) ;
defparam Ur1_n_5_pp.DATA_WIDTH = 6;
defparam Ur1_n_5_pp.C0 = 6'd 0;
defparam Ur1_n_5_pp.C1 = 6'd 49;
defparam Ur1_n_5_pp.C2 = 6'd 9;
defparam Ur1_n_5_pp.C3 = 6'd 58;
defparam Ur1_n_5_pp.C4 = 6'd 10;
defparam Ur1_n_5_pp.C5 = 6'd 59;
defparam Ur1_n_5_pp.C6 = 6'd 19;
defparam Ur1_n_5_pp.C7 = 6'd 4;
defparam Ur1_n_5_pp.C8 = 6'd 57;
defparam Ur1_n_5_pp.C9 = 6'd 42;
defparam Ur1_n_5_pp.CA = 6'd 2;
defparam Ur1_n_5_pp.CB = 6'd 51;
defparam Ur1_n_5_pp.CC = 6'd 3;
defparam Ur1_n_5_pp.CD = 6'd 52;
defparam Ur1_n_5_pp.CE = 6'd 12;
defparam Ur1_n_5_pp.CF = 6'd 61;
assign lut_val_1_n_5_pp[13] = lut_val_1_n_5_pp[5];
assign lut_val_1_n_5_pp[12] = lut_val_1_n_5_pp[5];
assign lut_val_1_n_5_pp[11] = lut_val_1_n_5_pp[5];
assign lut_val_1_n_5_pp[10] = lut_val_1_n_5_pp[5];
assign lut_val_1_n_5_pp[9] = lut_val_1_n_5_pp[5];
assign lut_val_1_n_5_pp[8] = lut_val_1_n_5_pp[5];
assign lut_val_1_n_5_pp[7] = lut_val_1_n_5_pp[5];
assign lut_val_1_n_5_pp[6] = lut_val_1_n_5_pp[5];
wire [13:0] lut_val_1_n_6_pp;
rom_lut_r_cen Ur1_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[6],sym_res_6_n[6],sym_res_5_n[6],sym_res_4_n[6] } ), .data_out( lut_val_1_n_6_pp[5:0]) ) ;
defparam Ur1_n_6_pp.DATA_WIDTH = 6;
defparam Ur1_n_6_pp.C0 = 6'd 0;
defparam Ur1_n_6_pp.C1 = 6'd 49;
defparam Ur1_n_6_pp.C2 = 6'd 9;
defparam Ur1_n_6_pp.C3 = 6'd 58;
defparam Ur1_n_6_pp.C4 = 6'd 10;
defparam Ur1_n_6_pp.C5 = 6'd 59;
defparam Ur1_n_6_pp.C6 = 6'd 19;
defparam Ur1_n_6_pp.C7 = 6'd 4;
defparam Ur1_n_6_pp.C8 = 6'd 57;
defparam Ur1_n_6_pp.C9 = 6'd 42;
defparam Ur1_n_6_pp.CA = 6'd 2;
defparam Ur1_n_6_pp.CB = 6'd 51;
defparam Ur1_n_6_pp.CC = 6'd 3;
defparam Ur1_n_6_pp.CD = 6'd 52;
defparam Ur1_n_6_pp.CE = 6'd 12;
defparam Ur1_n_6_pp.CF = 6'd 61;
assign lut_val_1_n_6_pp[13] = lut_val_1_n_6_pp[5];
assign lut_val_1_n_6_pp[12] = lut_val_1_n_6_pp[5];
assign lut_val_1_n_6_pp[11] = lut_val_1_n_6_pp[5];
assign lut_val_1_n_6_pp[10] = lut_val_1_n_6_pp[5];
assign lut_val_1_n_6_pp[9] = lut_val_1_n_6_pp[5];
assign lut_val_1_n_6_pp[8] = lut_val_1_n_6_pp[5];
assign lut_val_1_n_6_pp[7] = lut_val_1_n_6_pp[5];
assign lut_val_1_n_6_pp[6] = lut_val_1_n_6_pp[5];
wire [13:0] lut_val_1_n_7_pp;
rom_lut_r_cen Ur1_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[7],sym_res_6_n[7],sym_res_5_n[7],sym_res_4_n[7] } ), .data_out( lut_val_1_n_7_pp[5:0]) ) ;
defparam Ur1_n_7_pp.DATA_WIDTH = 6;
defparam Ur1_n_7_pp.C0 = 6'd 0;
defparam Ur1_n_7_pp.C1 = 6'd 49;
defparam Ur1_n_7_pp.C2 = 6'd 9;
defparam Ur1_n_7_pp.C3 = 6'd 58;
defparam Ur1_n_7_pp.C4 = 6'd 10;
defparam Ur1_n_7_pp.C5 = 6'd 59;
defparam Ur1_n_7_pp.C6 = 6'd 19;
defparam Ur1_n_7_pp.C7 = 6'd 4;
defparam Ur1_n_7_pp.C8 = 6'd 57;
defparam Ur1_n_7_pp.C9 = 6'd 42;
defparam Ur1_n_7_pp.CA = 6'd 2;
defparam Ur1_n_7_pp.CB = 6'd 51;
defparam Ur1_n_7_pp.CC = 6'd 3;
defparam Ur1_n_7_pp.CD = 6'd 52;
defparam Ur1_n_7_pp.CE = 6'd 12;
defparam Ur1_n_7_pp.CF = 6'd 61;
assign lut_val_1_n_7_pp[13] = lut_val_1_n_7_pp[5];
assign lut_val_1_n_7_pp[12] = lut_val_1_n_7_pp[5];
assign lut_val_1_n_7_pp[11] = lut_val_1_n_7_pp[5];
assign lut_val_1_n_7_pp[10] = lut_val_1_n_7_pp[5];
assign lut_val_1_n_7_pp[9] = lut_val_1_n_7_pp[5];
assign lut_val_1_n_7_pp[8] = lut_val_1_n_7_pp[5];
assign lut_val_1_n_7_pp[7] = lut_val_1_n_7_pp[5];
assign lut_val_1_n_7_pp[6] = lut_val_1_n_7_pp[5];
wire [13:0] lut_val_1_n_8_pp;
rom_lut_r_cen Ur1_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[8],sym_res_6_n[8],sym_res_5_n[8],sym_res_4_n[8] } ), .data_out( lut_val_1_n_8_pp[5:0]) ) ;
defparam Ur1_n_8_pp.DATA_WIDTH = 6;
defparam Ur1_n_8_pp.C0 = 6'd 0;
defparam Ur1_n_8_pp.C1 = 6'd 49;
defparam Ur1_n_8_pp.C2 = 6'd 9;
defparam Ur1_n_8_pp.C3 = 6'd 58;
defparam Ur1_n_8_pp.C4 = 6'd 10;
defparam Ur1_n_8_pp.C5 = 6'd 59;
defparam Ur1_n_8_pp.C6 = 6'd 19;
defparam Ur1_n_8_pp.C7 = 6'd 4;
defparam Ur1_n_8_pp.C8 = 6'd 57;
defparam Ur1_n_8_pp.C9 = 6'd 42;
defparam Ur1_n_8_pp.CA = 6'd 2;
defparam Ur1_n_8_pp.CB = 6'd 51;
defparam Ur1_n_8_pp.CC = 6'd 3;
defparam Ur1_n_8_pp.CD = 6'd 52;
defparam Ur1_n_8_pp.CE = 6'd 12;
defparam Ur1_n_8_pp.CF = 6'd 61;
assign lut_val_1_n_8_pp[13] = lut_val_1_n_8_pp[5];
assign lut_val_1_n_8_pp[12] = lut_val_1_n_8_pp[5];
assign lut_val_1_n_8_pp[11] = lut_val_1_n_8_pp[5];
assign lut_val_1_n_8_pp[10] = lut_val_1_n_8_pp[5];
assign lut_val_1_n_8_pp[9] = lut_val_1_n_8_pp[5];
assign lut_val_1_n_8_pp[8] = lut_val_1_n_8_pp[5];
assign lut_val_1_n_8_pp[7] = lut_val_1_n_8_pp[5];
assign lut_val_1_n_8_pp[6] = lut_val_1_n_8_pp[5];
wire [13:0] lut_val_1_n_9_pp;
rom_lut_r_cen Ur1_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[9],sym_res_6_n[9],sym_res_5_n[9],sym_res_4_n[9] } ), .data_out( lut_val_1_n_9_pp[5:0]) ) ;
defparam Ur1_n_9_pp.DATA_WIDTH = 6;
defparam Ur1_n_9_pp.C0 = 6'd 0;
defparam Ur1_n_9_pp.C1 = 6'd 49;
defparam Ur1_n_9_pp.C2 = 6'd 9;
defparam Ur1_n_9_pp.C3 = 6'd 58;
defparam Ur1_n_9_pp.C4 = 6'd 10;
defparam Ur1_n_9_pp.C5 = 6'd 59;
defparam Ur1_n_9_pp.C6 = 6'd 19;
defparam Ur1_n_9_pp.C7 = 6'd 4;
defparam Ur1_n_9_pp.C8 = 6'd 57;
defparam Ur1_n_9_pp.C9 = 6'd 42;
defparam Ur1_n_9_pp.CA = 6'd 2;
defparam Ur1_n_9_pp.CB = 6'd 51;
defparam Ur1_n_9_pp.CC = 6'd 3;
defparam Ur1_n_9_pp.CD = 6'd 52;
defparam Ur1_n_9_pp.CE = 6'd 12;
defparam Ur1_n_9_pp.CF = 6'd 61;
assign lut_val_1_n_9_pp[13] = lut_val_1_n_9_pp[5];
assign lut_val_1_n_9_pp[12] = lut_val_1_n_9_pp[5];
assign lut_val_1_n_9_pp[11] = lut_val_1_n_9_pp[5];
assign lut_val_1_n_9_pp[10] = lut_val_1_n_9_pp[5];
assign lut_val_1_n_9_pp[9] = lut_val_1_n_9_pp[5];
assign lut_val_1_n_9_pp[8] = lut_val_1_n_9_pp[5];
assign lut_val_1_n_9_pp[7] = lut_val_1_n_9_pp[5];
assign lut_val_1_n_9_pp[6] = lut_val_1_n_9_pp[5];
wire [13:0] lut_val_1_n_10_pp;
rom_lut_r_cen Ur1_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[10],sym_res_6_n[10],sym_res_5_n[10],sym_res_4_n[10] } ), .data_out( lut_val_1_n_10_pp[5:0]) ) ;
defparam Ur1_n_10_pp.DATA_WIDTH = 6;
defparam Ur1_n_10_pp.C0 = 6'd 0;
defparam Ur1_n_10_pp.C1 = 6'd 49;
defparam Ur1_n_10_pp.C2 = 6'd 9;
defparam Ur1_n_10_pp.C3 = 6'd 58;
defparam Ur1_n_10_pp.C4 = 6'd 10;
defparam Ur1_n_10_pp.C5 = 6'd 59;
defparam Ur1_n_10_pp.C6 = 6'd 19;
defparam Ur1_n_10_pp.C7 = 6'd 4;
defparam Ur1_n_10_pp.C8 = 6'd 57;
defparam Ur1_n_10_pp.C9 = 6'd 42;
defparam Ur1_n_10_pp.CA = 6'd 2;
defparam Ur1_n_10_pp.CB = 6'd 51;
defparam Ur1_n_10_pp.CC = 6'd 3;
defparam Ur1_n_10_pp.CD = 6'd 52;
defparam Ur1_n_10_pp.CE = 6'd 12;
defparam Ur1_n_10_pp.CF = 6'd 61;
assign lut_val_1_n_10_pp[13] = lut_val_1_n_10_pp[5];
assign lut_val_1_n_10_pp[12] = lut_val_1_n_10_pp[5];
assign lut_val_1_n_10_pp[11] = lut_val_1_n_10_pp[5];
assign lut_val_1_n_10_pp[10] = lut_val_1_n_10_pp[5];
assign lut_val_1_n_10_pp[9] = lut_val_1_n_10_pp[5];
assign lut_val_1_n_10_pp[8] = lut_val_1_n_10_pp[5];
assign lut_val_1_n_10_pp[7] = lut_val_1_n_10_pp[5];
assign lut_val_1_n_10_pp[6] = lut_val_1_n_10_pp[5];
wire [13:0] lut_val_1_n_11_pp;
rom_lut_r_cen Ur1_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[11],sym_res_6_n[11],sym_res_5_n[11],sym_res_4_n[11] } ), .data_out( lut_val_1_n_11_pp[5:0]) ) ;
defparam Ur1_n_11_pp.DATA_WIDTH = 6;
defparam Ur1_n_11_pp.C0 = 6'd 0;
defparam Ur1_n_11_pp.C1 = 6'd 49;
defparam Ur1_n_11_pp.C2 = 6'd 9;
defparam Ur1_n_11_pp.C3 = 6'd 58;
defparam Ur1_n_11_pp.C4 = 6'd 10;
defparam Ur1_n_11_pp.C5 = 6'd 59;
defparam Ur1_n_11_pp.C6 = 6'd 19;
defparam Ur1_n_11_pp.C7 = 6'd 4;
defparam Ur1_n_11_pp.C8 = 6'd 57;
defparam Ur1_n_11_pp.C9 = 6'd 42;
defparam Ur1_n_11_pp.CA = 6'd 2;
defparam Ur1_n_11_pp.CB = 6'd 51;
defparam Ur1_n_11_pp.CC = 6'd 3;
defparam Ur1_n_11_pp.CD = 6'd 52;
defparam Ur1_n_11_pp.CE = 6'd 12;
defparam Ur1_n_11_pp.CF = 6'd 61;
assign lut_val_1_n_11_pp[13] = lut_val_1_n_11_pp[5];
assign lut_val_1_n_11_pp[12] = lut_val_1_n_11_pp[5];
assign lut_val_1_n_11_pp[11] = lut_val_1_n_11_pp[5];
assign lut_val_1_n_11_pp[10] = lut_val_1_n_11_pp[5];
assign lut_val_1_n_11_pp[9] = lut_val_1_n_11_pp[5];
assign lut_val_1_n_11_pp[8] = lut_val_1_n_11_pp[5];
assign lut_val_1_n_11_pp[7] = lut_val_1_n_11_pp[5];
assign lut_val_1_n_11_pp[6] = lut_val_1_n_11_pp[5];
wire [13:0] lut_val_1_n_12_pp;
rom_lut_r_cen Ur1_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[12],sym_res_6_n[12],sym_res_5_n[12],sym_res_4_n[12] } ), .data_out( lut_val_1_n_12_pp[5:0]) ) ;
defparam Ur1_n_12_pp.DATA_WIDTH = 6;
defparam Ur1_n_12_pp.C0 = 6'd 0;
defparam Ur1_n_12_pp.C1 = 6'd 49;
defparam Ur1_n_12_pp.C2 = 6'd 9;
defparam Ur1_n_12_pp.C3 = 6'd 58;
defparam Ur1_n_12_pp.C4 = 6'd 10;
defparam Ur1_n_12_pp.C5 = 6'd 59;
defparam Ur1_n_12_pp.C6 = 6'd 19;
defparam Ur1_n_12_pp.C7 = 6'd 4;
defparam Ur1_n_12_pp.C8 = 6'd 57;
defparam Ur1_n_12_pp.C9 = 6'd 42;
defparam Ur1_n_12_pp.CA = 6'd 2;
defparam Ur1_n_12_pp.CB = 6'd 51;
defparam Ur1_n_12_pp.CC = 6'd 3;
defparam Ur1_n_12_pp.CD = 6'd 52;
defparam Ur1_n_12_pp.CE = 6'd 12;
defparam Ur1_n_12_pp.CF = 6'd 61;
assign lut_val_1_n_12_pp[13] = lut_val_1_n_12_pp[5];
assign lut_val_1_n_12_pp[12] = lut_val_1_n_12_pp[5];
assign lut_val_1_n_12_pp[11] = lut_val_1_n_12_pp[5];
assign lut_val_1_n_12_pp[10] = lut_val_1_n_12_pp[5];
assign lut_val_1_n_12_pp[9] = lut_val_1_n_12_pp[5];
assign lut_val_1_n_12_pp[8] = lut_val_1_n_12_pp[5];
assign lut_val_1_n_12_pp[7] = lut_val_1_n_12_pp[5];
assign lut_val_1_n_12_pp[6] = lut_val_1_n_12_pp[5];
wire [13:0] lut_val_1_n_13_pp;
rom_lut_r_cen Ur1_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[13],sym_res_6_n[13],sym_res_5_n[13],sym_res_4_n[13] } ), .data_out( lut_val_1_n_13_pp[5:0]) ) ;
defparam Ur1_n_13_pp.DATA_WIDTH = 6;
defparam Ur1_n_13_pp.C0 = 6'd 0;
defparam Ur1_n_13_pp.C1 = 6'd 49;
defparam Ur1_n_13_pp.C2 = 6'd 9;
defparam Ur1_n_13_pp.C3 = 6'd 58;
defparam Ur1_n_13_pp.C4 = 6'd 10;
defparam Ur1_n_13_pp.C5 = 6'd 59;
defparam Ur1_n_13_pp.C6 = 6'd 19;
defparam Ur1_n_13_pp.C7 = 6'd 4;
defparam Ur1_n_13_pp.C8 = 6'd 57;
defparam Ur1_n_13_pp.C9 = 6'd 42;
defparam Ur1_n_13_pp.CA = 6'd 2;
defparam Ur1_n_13_pp.CB = 6'd 51;
defparam Ur1_n_13_pp.CC = 6'd 3;
defparam Ur1_n_13_pp.CD = 6'd 52;
defparam Ur1_n_13_pp.CE = 6'd 12;
defparam Ur1_n_13_pp.CF = 6'd 61;
assign lut_val_1_n_13_pp[13] = lut_val_1_n_13_pp[5];
assign lut_val_1_n_13_pp[12] = lut_val_1_n_13_pp[5];
assign lut_val_1_n_13_pp[11] = lut_val_1_n_13_pp[5];
assign lut_val_1_n_13_pp[10] = lut_val_1_n_13_pp[5];
assign lut_val_1_n_13_pp[9] = lut_val_1_n_13_pp[5];
assign lut_val_1_n_13_pp[8] = lut_val_1_n_13_pp[5];
assign lut_val_1_n_13_pp[7] = lut_val_1_n_13_pp[5];
assign lut_val_1_n_13_pp[6] = lut_val_1_n_13_pp[5];
wire [13:0] lut_val_1_n_14_pp;
rom_lut_r_cen Ur1_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[14],sym_res_6_n[14],sym_res_5_n[14],sym_res_4_n[14] } ), .data_out( lut_val_1_n_14_pp[5:0]) ) ;
defparam Ur1_n_14_pp.DATA_WIDTH = 6;
defparam Ur1_n_14_pp.C0 = 6'd 0;
defparam Ur1_n_14_pp.C1 = 6'd 49;
defparam Ur1_n_14_pp.C2 = 6'd 9;
defparam Ur1_n_14_pp.C3 = 6'd 58;
defparam Ur1_n_14_pp.C4 = 6'd 10;
defparam Ur1_n_14_pp.C5 = 6'd 59;
defparam Ur1_n_14_pp.C6 = 6'd 19;
defparam Ur1_n_14_pp.C7 = 6'd 4;
defparam Ur1_n_14_pp.C8 = 6'd 57;
defparam Ur1_n_14_pp.C9 = 6'd 42;
defparam Ur1_n_14_pp.CA = 6'd 2;
defparam Ur1_n_14_pp.CB = 6'd 51;
defparam Ur1_n_14_pp.CC = 6'd 3;
defparam Ur1_n_14_pp.CD = 6'd 52;
defparam Ur1_n_14_pp.CE = 6'd 12;
defparam Ur1_n_14_pp.CF = 6'd 61;
assign lut_val_1_n_14_pp[13] = lut_val_1_n_14_pp[5];
assign lut_val_1_n_14_pp[12] = lut_val_1_n_14_pp[5];
assign lut_val_1_n_14_pp[11] = lut_val_1_n_14_pp[5];
assign lut_val_1_n_14_pp[10] = lut_val_1_n_14_pp[5];
assign lut_val_1_n_14_pp[9] = lut_val_1_n_14_pp[5];
assign lut_val_1_n_14_pp[8] = lut_val_1_n_14_pp[5];
assign lut_val_1_n_14_pp[7] = lut_val_1_n_14_pp[5];
assign lut_val_1_n_14_pp[6] = lut_val_1_n_14_pp[5];
wire [13:0] lut_val_1_n_15_pp;
rom_lut_r_cen Ur1_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_7_n[15],sym_res_6_n[15],sym_res_5_n[15],sym_res_4_n[15] } ), .data_out( lut_val_1_n_15_pp[5:0]) ) ;
defparam Ur1_n_15_pp.DATA_WIDTH = 6;
defparam Ur1_n_15_pp.C0 = 6'd 0;
defparam Ur1_n_15_pp.C1 = 6'd 49;
defparam Ur1_n_15_pp.C2 = 6'd 9;
defparam Ur1_n_15_pp.C3 = 6'd 58;
defparam Ur1_n_15_pp.C4 = 6'd 10;
defparam Ur1_n_15_pp.C5 = 6'd 59;
defparam Ur1_n_15_pp.C6 = 6'd 19;
defparam Ur1_n_15_pp.C7 = 6'd 4;
defparam Ur1_n_15_pp.C8 = 6'd 57;
defparam Ur1_n_15_pp.C9 = 6'd 42;
defparam Ur1_n_15_pp.CA = 6'd 2;
defparam Ur1_n_15_pp.CB = 6'd 51;
defparam Ur1_n_15_pp.CC = 6'd 3;
defparam Ur1_n_15_pp.CD = 6'd 52;
defparam Ur1_n_15_pp.CE = 6'd 12;
defparam Ur1_n_15_pp.CF = 6'd 61;
assign lut_val_1_n_15_pp[13] = lut_val_1_n_15_pp[5];
assign lut_val_1_n_15_pp[12] = lut_val_1_n_15_pp[5];
assign lut_val_1_n_15_pp[11] = lut_val_1_n_15_pp[5];
assign lut_val_1_n_15_pp[10] = lut_val_1_n_15_pp[5];
assign lut_val_1_n_15_pp[9] = lut_val_1_n_15_pp[5];
assign lut_val_1_n_15_pp[8] = lut_val_1_n_15_pp[5];
assign lut_val_1_n_15_pp[7] = lut_val_1_n_15_pp[5];
assign lut_val_1_n_15_pp[6] = lut_val_1_n_15_pp[5];
wire [13:0] lut_val_2_n_0_pp;
rom_lut_r_cen Ur2_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[0],sym_res_10_n[0],sym_res_9_n[0],sym_res_8_n[0] } ), .data_out( lut_val_2_n_0_pp[8:0]) ) ;
defparam Ur2_n_0_pp.DATA_WIDTH = 9;
defparam Ur2_n_0_pp.C0 = 9'd 0;
defparam Ur2_n_0_pp.C1 = 9'd 492;
defparam Ur2_n_0_pp.C2 = 9'd 13;
defparam Ur2_n_0_pp.C3 = 9'd 505;
defparam Ur2_n_0_pp.C4 = 9'd 74;
defparam Ur2_n_0_pp.C5 = 9'd 54;
defparam Ur2_n_0_pp.C6 = 9'd 87;
defparam Ur2_n_0_pp.C7 = 9'd 67;
defparam Ur2_n_0_pp.C8 = 9'd 110;
defparam Ur2_n_0_pp.C9 = 9'd 90;
defparam Ur2_n_0_pp.CA = 9'd 123;
defparam Ur2_n_0_pp.CB = 9'd 103;
defparam Ur2_n_0_pp.CC = 9'd 184;
defparam Ur2_n_0_pp.CD = 9'd 164;
defparam Ur2_n_0_pp.CE = 9'd 197;
defparam Ur2_n_0_pp.CF = 9'd 177;
assign lut_val_2_n_0_pp[13] = lut_val_2_n_0_pp[8];
assign lut_val_2_n_0_pp[12] = lut_val_2_n_0_pp[8];
assign lut_val_2_n_0_pp[11] = lut_val_2_n_0_pp[8];
assign lut_val_2_n_0_pp[10] = lut_val_2_n_0_pp[8];
assign lut_val_2_n_0_pp[9] = lut_val_2_n_0_pp[8];
wire [13:0] lut_val_2_n_1_pp;
rom_lut_r_cen Ur2_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[1],sym_res_10_n[1],sym_res_9_n[1],sym_res_8_n[1] } ), .data_out( lut_val_2_n_1_pp[8:0]) ) ;
defparam Ur2_n_1_pp.DATA_WIDTH = 9;
defparam Ur2_n_1_pp.C0 = 9'd 0;
defparam Ur2_n_1_pp.C1 = 9'd 492;
defparam Ur2_n_1_pp.C2 = 9'd 13;
defparam Ur2_n_1_pp.C3 = 9'd 505;
defparam Ur2_n_1_pp.C4 = 9'd 74;
defparam Ur2_n_1_pp.C5 = 9'd 54;
defparam Ur2_n_1_pp.C6 = 9'd 87;
defparam Ur2_n_1_pp.C7 = 9'd 67;
defparam Ur2_n_1_pp.C8 = 9'd 110;
defparam Ur2_n_1_pp.C9 = 9'd 90;
defparam Ur2_n_1_pp.CA = 9'd 123;
defparam Ur2_n_1_pp.CB = 9'd 103;
defparam Ur2_n_1_pp.CC = 9'd 184;
defparam Ur2_n_1_pp.CD = 9'd 164;
defparam Ur2_n_1_pp.CE = 9'd 197;
defparam Ur2_n_1_pp.CF = 9'd 177;
assign lut_val_2_n_1_pp[13] = lut_val_2_n_1_pp[8];
assign lut_val_2_n_1_pp[12] = lut_val_2_n_1_pp[8];
assign lut_val_2_n_1_pp[11] = lut_val_2_n_1_pp[8];
assign lut_val_2_n_1_pp[10] = lut_val_2_n_1_pp[8];
assign lut_val_2_n_1_pp[9] = lut_val_2_n_1_pp[8];
wire [13:0] lut_val_2_n_2_pp;
rom_lut_r_cen Ur2_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[2],sym_res_10_n[2],sym_res_9_n[2],sym_res_8_n[2] } ), .data_out( lut_val_2_n_2_pp[8:0]) ) ;
defparam Ur2_n_2_pp.DATA_WIDTH = 9;
defparam Ur2_n_2_pp.C0 = 9'd 0;
defparam Ur2_n_2_pp.C1 = 9'd 492;
defparam Ur2_n_2_pp.C2 = 9'd 13;
defparam Ur2_n_2_pp.C3 = 9'd 505;
defparam Ur2_n_2_pp.C4 = 9'd 74;
defparam Ur2_n_2_pp.C5 = 9'd 54;
defparam Ur2_n_2_pp.C6 = 9'd 87;
defparam Ur2_n_2_pp.C7 = 9'd 67;
defparam Ur2_n_2_pp.C8 = 9'd 110;
defparam Ur2_n_2_pp.C9 = 9'd 90;
defparam Ur2_n_2_pp.CA = 9'd 123;
defparam Ur2_n_2_pp.CB = 9'd 103;
defparam Ur2_n_2_pp.CC = 9'd 184;
defparam Ur2_n_2_pp.CD = 9'd 164;
defparam Ur2_n_2_pp.CE = 9'd 197;
defparam Ur2_n_2_pp.CF = 9'd 177;
assign lut_val_2_n_2_pp[13] = lut_val_2_n_2_pp[8];
assign lut_val_2_n_2_pp[12] = lut_val_2_n_2_pp[8];
assign lut_val_2_n_2_pp[11] = lut_val_2_n_2_pp[8];
assign lut_val_2_n_2_pp[10] = lut_val_2_n_2_pp[8];
assign lut_val_2_n_2_pp[9] = lut_val_2_n_2_pp[8];
wire [13:0] lut_val_2_n_3_pp;
rom_lut_r_cen Ur2_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[3],sym_res_10_n[3],sym_res_9_n[3],sym_res_8_n[3] } ), .data_out( lut_val_2_n_3_pp[8:0]) ) ;
defparam Ur2_n_3_pp.DATA_WIDTH = 9;
defparam Ur2_n_3_pp.C0 = 9'd 0;
defparam Ur2_n_3_pp.C1 = 9'd 492;
defparam Ur2_n_3_pp.C2 = 9'd 13;
defparam Ur2_n_3_pp.C3 = 9'd 505;
defparam Ur2_n_3_pp.C4 = 9'd 74;
defparam Ur2_n_3_pp.C5 = 9'd 54;
defparam Ur2_n_3_pp.C6 = 9'd 87;
defparam Ur2_n_3_pp.C7 = 9'd 67;
defparam Ur2_n_3_pp.C8 = 9'd 110;
defparam Ur2_n_3_pp.C9 = 9'd 90;
defparam Ur2_n_3_pp.CA = 9'd 123;
defparam Ur2_n_3_pp.CB = 9'd 103;
defparam Ur2_n_3_pp.CC = 9'd 184;
defparam Ur2_n_3_pp.CD = 9'd 164;
defparam Ur2_n_3_pp.CE = 9'd 197;
defparam Ur2_n_3_pp.CF = 9'd 177;
assign lut_val_2_n_3_pp[13] = lut_val_2_n_3_pp[8];
assign lut_val_2_n_3_pp[12] = lut_val_2_n_3_pp[8];
assign lut_val_2_n_3_pp[11] = lut_val_2_n_3_pp[8];
assign lut_val_2_n_3_pp[10] = lut_val_2_n_3_pp[8];
assign lut_val_2_n_3_pp[9] = lut_val_2_n_3_pp[8];
wire [13:0] lut_val_2_n_4_pp;
rom_lut_r_cen Ur2_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[4],sym_res_10_n[4],sym_res_9_n[4],sym_res_8_n[4] } ), .data_out( lut_val_2_n_4_pp[8:0]) ) ;
defparam Ur2_n_4_pp.DATA_WIDTH = 9;
defparam Ur2_n_4_pp.C0 = 9'd 0;
defparam Ur2_n_4_pp.C1 = 9'd 492;
defparam Ur2_n_4_pp.C2 = 9'd 13;
defparam Ur2_n_4_pp.C3 = 9'd 505;
defparam Ur2_n_4_pp.C4 = 9'd 74;
defparam Ur2_n_4_pp.C5 = 9'd 54;
defparam Ur2_n_4_pp.C6 = 9'd 87;
defparam Ur2_n_4_pp.C7 = 9'd 67;
defparam Ur2_n_4_pp.C8 = 9'd 110;
defparam Ur2_n_4_pp.C9 = 9'd 90;
defparam Ur2_n_4_pp.CA = 9'd 123;
defparam Ur2_n_4_pp.CB = 9'd 103;
defparam Ur2_n_4_pp.CC = 9'd 184;
defparam Ur2_n_4_pp.CD = 9'd 164;
defparam Ur2_n_4_pp.CE = 9'd 197;
defparam Ur2_n_4_pp.CF = 9'd 177;
assign lut_val_2_n_4_pp[13] = lut_val_2_n_4_pp[8];
assign lut_val_2_n_4_pp[12] = lut_val_2_n_4_pp[8];
assign lut_val_2_n_4_pp[11] = lut_val_2_n_4_pp[8];
assign lut_val_2_n_4_pp[10] = lut_val_2_n_4_pp[8];
assign lut_val_2_n_4_pp[9] = lut_val_2_n_4_pp[8];
wire [13:0] lut_val_2_n_5_pp;
rom_lut_r_cen Ur2_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[5],sym_res_10_n[5],sym_res_9_n[5],sym_res_8_n[5] } ), .data_out( lut_val_2_n_5_pp[8:0]) ) ;
defparam Ur2_n_5_pp.DATA_WIDTH = 9;
defparam Ur2_n_5_pp.C0 = 9'd 0;
defparam Ur2_n_5_pp.C1 = 9'd 492;
defparam Ur2_n_5_pp.C2 = 9'd 13;
defparam Ur2_n_5_pp.C3 = 9'd 505;
defparam Ur2_n_5_pp.C4 = 9'd 74;
defparam Ur2_n_5_pp.C5 = 9'd 54;
defparam Ur2_n_5_pp.C6 = 9'd 87;
defparam Ur2_n_5_pp.C7 = 9'd 67;
defparam Ur2_n_5_pp.C8 = 9'd 110;
defparam Ur2_n_5_pp.C9 = 9'd 90;
defparam Ur2_n_5_pp.CA = 9'd 123;
defparam Ur2_n_5_pp.CB = 9'd 103;
defparam Ur2_n_5_pp.CC = 9'd 184;
defparam Ur2_n_5_pp.CD = 9'd 164;
defparam Ur2_n_5_pp.CE = 9'd 197;
defparam Ur2_n_5_pp.CF = 9'd 177;
assign lut_val_2_n_5_pp[13] = lut_val_2_n_5_pp[8];
assign lut_val_2_n_5_pp[12] = lut_val_2_n_5_pp[8];
assign lut_val_2_n_5_pp[11] = lut_val_2_n_5_pp[8];
assign lut_val_2_n_5_pp[10] = lut_val_2_n_5_pp[8];
assign lut_val_2_n_5_pp[9] = lut_val_2_n_5_pp[8];
wire [13:0] lut_val_2_n_6_pp;
rom_lut_r_cen Ur2_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[6],sym_res_10_n[6],sym_res_9_n[6],sym_res_8_n[6] } ), .data_out( lut_val_2_n_6_pp[8:0]) ) ;
defparam Ur2_n_6_pp.DATA_WIDTH = 9;
defparam Ur2_n_6_pp.C0 = 9'd 0;
defparam Ur2_n_6_pp.C1 = 9'd 492;
defparam Ur2_n_6_pp.C2 = 9'd 13;
defparam Ur2_n_6_pp.C3 = 9'd 505;
defparam Ur2_n_6_pp.C4 = 9'd 74;
defparam Ur2_n_6_pp.C5 = 9'd 54;
defparam Ur2_n_6_pp.C6 = 9'd 87;
defparam Ur2_n_6_pp.C7 = 9'd 67;
defparam Ur2_n_6_pp.C8 = 9'd 110;
defparam Ur2_n_6_pp.C9 = 9'd 90;
defparam Ur2_n_6_pp.CA = 9'd 123;
defparam Ur2_n_6_pp.CB = 9'd 103;
defparam Ur2_n_6_pp.CC = 9'd 184;
defparam Ur2_n_6_pp.CD = 9'd 164;
defparam Ur2_n_6_pp.CE = 9'd 197;
defparam Ur2_n_6_pp.CF = 9'd 177;
assign lut_val_2_n_6_pp[13] = lut_val_2_n_6_pp[8];
assign lut_val_2_n_6_pp[12] = lut_val_2_n_6_pp[8];
assign lut_val_2_n_6_pp[11] = lut_val_2_n_6_pp[8];
assign lut_val_2_n_6_pp[10] = lut_val_2_n_6_pp[8];
assign lut_val_2_n_6_pp[9] = lut_val_2_n_6_pp[8];
wire [13:0] lut_val_2_n_7_pp;
rom_lut_r_cen Ur2_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[7],sym_res_10_n[7],sym_res_9_n[7],sym_res_8_n[7] } ), .data_out( lut_val_2_n_7_pp[8:0]) ) ;
defparam Ur2_n_7_pp.DATA_WIDTH = 9;
defparam Ur2_n_7_pp.C0 = 9'd 0;
defparam Ur2_n_7_pp.C1 = 9'd 492;
defparam Ur2_n_7_pp.C2 = 9'd 13;
defparam Ur2_n_7_pp.C3 = 9'd 505;
defparam Ur2_n_7_pp.C4 = 9'd 74;
defparam Ur2_n_7_pp.C5 = 9'd 54;
defparam Ur2_n_7_pp.C6 = 9'd 87;
defparam Ur2_n_7_pp.C7 = 9'd 67;
defparam Ur2_n_7_pp.C8 = 9'd 110;
defparam Ur2_n_7_pp.C9 = 9'd 90;
defparam Ur2_n_7_pp.CA = 9'd 123;
defparam Ur2_n_7_pp.CB = 9'd 103;
defparam Ur2_n_7_pp.CC = 9'd 184;
defparam Ur2_n_7_pp.CD = 9'd 164;
defparam Ur2_n_7_pp.CE = 9'd 197;
defparam Ur2_n_7_pp.CF = 9'd 177;
assign lut_val_2_n_7_pp[13] = lut_val_2_n_7_pp[8];
assign lut_val_2_n_7_pp[12] = lut_val_2_n_7_pp[8];
assign lut_val_2_n_7_pp[11] = lut_val_2_n_7_pp[8];
assign lut_val_2_n_7_pp[10] = lut_val_2_n_7_pp[8];
assign lut_val_2_n_7_pp[9] = lut_val_2_n_7_pp[8];
wire [13:0] lut_val_2_n_8_pp;
rom_lut_r_cen Ur2_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[8],sym_res_10_n[8],sym_res_9_n[8],sym_res_8_n[8] } ), .data_out( lut_val_2_n_8_pp[8:0]) ) ;
defparam Ur2_n_8_pp.DATA_WIDTH = 9;
defparam Ur2_n_8_pp.C0 = 9'd 0;
defparam Ur2_n_8_pp.C1 = 9'd 492;
defparam Ur2_n_8_pp.C2 = 9'd 13;
defparam Ur2_n_8_pp.C3 = 9'd 505;
defparam Ur2_n_8_pp.C4 = 9'd 74;
defparam Ur2_n_8_pp.C5 = 9'd 54;
defparam Ur2_n_8_pp.C6 = 9'd 87;
defparam Ur2_n_8_pp.C7 = 9'd 67;
defparam Ur2_n_8_pp.C8 = 9'd 110;
defparam Ur2_n_8_pp.C9 = 9'd 90;
defparam Ur2_n_8_pp.CA = 9'd 123;
defparam Ur2_n_8_pp.CB = 9'd 103;
defparam Ur2_n_8_pp.CC = 9'd 184;
defparam Ur2_n_8_pp.CD = 9'd 164;
defparam Ur2_n_8_pp.CE = 9'd 197;
defparam Ur2_n_8_pp.CF = 9'd 177;
assign lut_val_2_n_8_pp[13] = lut_val_2_n_8_pp[8];
assign lut_val_2_n_8_pp[12] = lut_val_2_n_8_pp[8];
assign lut_val_2_n_8_pp[11] = lut_val_2_n_8_pp[8];
assign lut_val_2_n_8_pp[10] = lut_val_2_n_8_pp[8];
assign lut_val_2_n_8_pp[9] = lut_val_2_n_8_pp[8];
wire [13:0] lut_val_2_n_9_pp;
rom_lut_r_cen Ur2_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[9],sym_res_10_n[9],sym_res_9_n[9],sym_res_8_n[9] } ), .data_out( lut_val_2_n_9_pp[8:0]) ) ;
defparam Ur2_n_9_pp.DATA_WIDTH = 9;
defparam Ur2_n_9_pp.C0 = 9'd 0;
defparam Ur2_n_9_pp.C1 = 9'd 492;
defparam Ur2_n_9_pp.C2 = 9'd 13;
defparam Ur2_n_9_pp.C3 = 9'd 505;
defparam Ur2_n_9_pp.C4 = 9'd 74;
defparam Ur2_n_9_pp.C5 = 9'd 54;
defparam Ur2_n_9_pp.C6 = 9'd 87;
defparam Ur2_n_9_pp.C7 = 9'd 67;
defparam Ur2_n_9_pp.C8 = 9'd 110;
defparam Ur2_n_9_pp.C9 = 9'd 90;
defparam Ur2_n_9_pp.CA = 9'd 123;
defparam Ur2_n_9_pp.CB = 9'd 103;
defparam Ur2_n_9_pp.CC = 9'd 184;
defparam Ur2_n_9_pp.CD = 9'd 164;
defparam Ur2_n_9_pp.CE = 9'd 197;
defparam Ur2_n_9_pp.CF = 9'd 177;
assign lut_val_2_n_9_pp[13] = lut_val_2_n_9_pp[8];
assign lut_val_2_n_9_pp[12] = lut_val_2_n_9_pp[8];
assign lut_val_2_n_9_pp[11] = lut_val_2_n_9_pp[8];
assign lut_val_2_n_9_pp[10] = lut_val_2_n_9_pp[8];
assign lut_val_2_n_9_pp[9] = lut_val_2_n_9_pp[8];
wire [13:0] lut_val_2_n_10_pp;
rom_lut_r_cen Ur2_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[10],sym_res_10_n[10],sym_res_9_n[10],sym_res_8_n[10] } ), .data_out( lut_val_2_n_10_pp[8:0]) ) ;
defparam Ur2_n_10_pp.DATA_WIDTH = 9;
defparam Ur2_n_10_pp.C0 = 9'd 0;
defparam Ur2_n_10_pp.C1 = 9'd 492;
defparam Ur2_n_10_pp.C2 = 9'd 13;
defparam Ur2_n_10_pp.C3 = 9'd 505;
defparam Ur2_n_10_pp.C4 = 9'd 74;
defparam Ur2_n_10_pp.C5 = 9'd 54;
defparam Ur2_n_10_pp.C6 = 9'd 87;
defparam Ur2_n_10_pp.C7 = 9'd 67;
defparam Ur2_n_10_pp.C8 = 9'd 110;
defparam Ur2_n_10_pp.C9 = 9'd 90;
defparam Ur2_n_10_pp.CA = 9'd 123;
defparam Ur2_n_10_pp.CB = 9'd 103;
defparam Ur2_n_10_pp.CC = 9'd 184;
defparam Ur2_n_10_pp.CD = 9'd 164;
defparam Ur2_n_10_pp.CE = 9'd 197;
defparam Ur2_n_10_pp.CF = 9'd 177;
assign lut_val_2_n_10_pp[13] = lut_val_2_n_10_pp[8];
assign lut_val_2_n_10_pp[12] = lut_val_2_n_10_pp[8];
assign lut_val_2_n_10_pp[11] = lut_val_2_n_10_pp[8];
assign lut_val_2_n_10_pp[10] = lut_val_2_n_10_pp[8];
assign lut_val_2_n_10_pp[9] = lut_val_2_n_10_pp[8];
wire [13:0] lut_val_2_n_11_pp;
rom_lut_r_cen Ur2_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[11],sym_res_10_n[11],sym_res_9_n[11],sym_res_8_n[11] } ), .data_out( lut_val_2_n_11_pp[8:0]) ) ;
defparam Ur2_n_11_pp.DATA_WIDTH = 9;
defparam Ur2_n_11_pp.C0 = 9'd 0;
defparam Ur2_n_11_pp.C1 = 9'd 492;
defparam Ur2_n_11_pp.C2 = 9'd 13;
defparam Ur2_n_11_pp.C3 = 9'd 505;
defparam Ur2_n_11_pp.C4 = 9'd 74;
defparam Ur2_n_11_pp.C5 = 9'd 54;
defparam Ur2_n_11_pp.C6 = 9'd 87;
defparam Ur2_n_11_pp.C7 = 9'd 67;
defparam Ur2_n_11_pp.C8 = 9'd 110;
defparam Ur2_n_11_pp.C9 = 9'd 90;
defparam Ur2_n_11_pp.CA = 9'd 123;
defparam Ur2_n_11_pp.CB = 9'd 103;
defparam Ur2_n_11_pp.CC = 9'd 184;
defparam Ur2_n_11_pp.CD = 9'd 164;
defparam Ur2_n_11_pp.CE = 9'd 197;
defparam Ur2_n_11_pp.CF = 9'd 177;
assign lut_val_2_n_11_pp[13] = lut_val_2_n_11_pp[8];
assign lut_val_2_n_11_pp[12] = lut_val_2_n_11_pp[8];
assign lut_val_2_n_11_pp[11] = lut_val_2_n_11_pp[8];
assign lut_val_2_n_11_pp[10] = lut_val_2_n_11_pp[8];
assign lut_val_2_n_11_pp[9] = lut_val_2_n_11_pp[8];
wire [13:0] lut_val_2_n_12_pp;
rom_lut_r_cen Ur2_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[12],sym_res_10_n[12],sym_res_9_n[12],sym_res_8_n[12] } ), .data_out( lut_val_2_n_12_pp[8:0]) ) ;
defparam Ur2_n_12_pp.DATA_WIDTH = 9;
defparam Ur2_n_12_pp.C0 = 9'd 0;
defparam Ur2_n_12_pp.C1 = 9'd 492;
defparam Ur2_n_12_pp.C2 = 9'd 13;
defparam Ur2_n_12_pp.C3 = 9'd 505;
defparam Ur2_n_12_pp.C4 = 9'd 74;
defparam Ur2_n_12_pp.C5 = 9'd 54;
defparam Ur2_n_12_pp.C6 = 9'd 87;
defparam Ur2_n_12_pp.C7 = 9'd 67;
defparam Ur2_n_12_pp.C8 = 9'd 110;
defparam Ur2_n_12_pp.C9 = 9'd 90;
defparam Ur2_n_12_pp.CA = 9'd 123;
defparam Ur2_n_12_pp.CB = 9'd 103;
defparam Ur2_n_12_pp.CC = 9'd 184;
defparam Ur2_n_12_pp.CD = 9'd 164;
defparam Ur2_n_12_pp.CE = 9'd 197;
defparam Ur2_n_12_pp.CF = 9'd 177;
assign lut_val_2_n_12_pp[13] = lut_val_2_n_12_pp[8];
assign lut_val_2_n_12_pp[12] = lut_val_2_n_12_pp[8];
assign lut_val_2_n_12_pp[11] = lut_val_2_n_12_pp[8];
assign lut_val_2_n_12_pp[10] = lut_val_2_n_12_pp[8];
assign lut_val_2_n_12_pp[9] = lut_val_2_n_12_pp[8];
wire [13:0] lut_val_2_n_13_pp;
rom_lut_r_cen Ur2_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[13],sym_res_10_n[13],sym_res_9_n[13],sym_res_8_n[13] } ), .data_out( lut_val_2_n_13_pp[8:0]) ) ;
defparam Ur2_n_13_pp.DATA_WIDTH = 9;
defparam Ur2_n_13_pp.C0 = 9'd 0;
defparam Ur2_n_13_pp.C1 = 9'd 492;
defparam Ur2_n_13_pp.C2 = 9'd 13;
defparam Ur2_n_13_pp.C3 = 9'd 505;
defparam Ur2_n_13_pp.C4 = 9'd 74;
defparam Ur2_n_13_pp.C5 = 9'd 54;
defparam Ur2_n_13_pp.C6 = 9'd 87;
defparam Ur2_n_13_pp.C7 = 9'd 67;
defparam Ur2_n_13_pp.C8 = 9'd 110;
defparam Ur2_n_13_pp.C9 = 9'd 90;
defparam Ur2_n_13_pp.CA = 9'd 123;
defparam Ur2_n_13_pp.CB = 9'd 103;
defparam Ur2_n_13_pp.CC = 9'd 184;
defparam Ur2_n_13_pp.CD = 9'd 164;
defparam Ur2_n_13_pp.CE = 9'd 197;
defparam Ur2_n_13_pp.CF = 9'd 177;
assign lut_val_2_n_13_pp[13] = lut_val_2_n_13_pp[8];
assign lut_val_2_n_13_pp[12] = lut_val_2_n_13_pp[8];
assign lut_val_2_n_13_pp[11] = lut_val_2_n_13_pp[8];
assign lut_val_2_n_13_pp[10] = lut_val_2_n_13_pp[8];
assign lut_val_2_n_13_pp[9] = lut_val_2_n_13_pp[8];
wire [13:0] lut_val_2_n_14_pp;
rom_lut_r_cen Ur2_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[14],sym_res_10_n[14],sym_res_9_n[14],sym_res_8_n[14] } ), .data_out( lut_val_2_n_14_pp[8:0]) ) ;
defparam Ur2_n_14_pp.DATA_WIDTH = 9;
defparam Ur2_n_14_pp.C0 = 9'd 0;
defparam Ur2_n_14_pp.C1 = 9'd 492;
defparam Ur2_n_14_pp.C2 = 9'd 13;
defparam Ur2_n_14_pp.C3 = 9'd 505;
defparam Ur2_n_14_pp.C4 = 9'd 74;
defparam Ur2_n_14_pp.C5 = 9'd 54;
defparam Ur2_n_14_pp.C6 = 9'd 87;
defparam Ur2_n_14_pp.C7 = 9'd 67;
defparam Ur2_n_14_pp.C8 = 9'd 110;
defparam Ur2_n_14_pp.C9 = 9'd 90;
defparam Ur2_n_14_pp.CA = 9'd 123;
defparam Ur2_n_14_pp.CB = 9'd 103;
defparam Ur2_n_14_pp.CC = 9'd 184;
defparam Ur2_n_14_pp.CD = 9'd 164;
defparam Ur2_n_14_pp.CE = 9'd 197;
defparam Ur2_n_14_pp.CF = 9'd 177;
assign lut_val_2_n_14_pp[13] = lut_val_2_n_14_pp[8];
assign lut_val_2_n_14_pp[12] = lut_val_2_n_14_pp[8];
assign lut_val_2_n_14_pp[11] = lut_val_2_n_14_pp[8];
assign lut_val_2_n_14_pp[10] = lut_val_2_n_14_pp[8];
assign lut_val_2_n_14_pp[9] = lut_val_2_n_14_pp[8];
wire [13:0] lut_val_2_n_15_pp;
rom_lut_r_cen Ur2_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_11_n[15],sym_res_10_n[15],sym_res_9_n[15],sym_res_8_n[15] } ), .data_out( lut_val_2_n_15_pp[8:0]) ) ;
defparam Ur2_n_15_pp.DATA_WIDTH = 9;
defparam Ur2_n_15_pp.C0 = 9'd 0;
defparam Ur2_n_15_pp.C1 = 9'd 492;
defparam Ur2_n_15_pp.C2 = 9'd 13;
defparam Ur2_n_15_pp.C3 = 9'd 505;
defparam Ur2_n_15_pp.C4 = 9'd 74;
defparam Ur2_n_15_pp.C5 = 9'd 54;
defparam Ur2_n_15_pp.C6 = 9'd 87;
defparam Ur2_n_15_pp.C7 = 9'd 67;
defparam Ur2_n_15_pp.C8 = 9'd 110;
defparam Ur2_n_15_pp.C9 = 9'd 90;
defparam Ur2_n_15_pp.CA = 9'd 123;
defparam Ur2_n_15_pp.CB = 9'd 103;
defparam Ur2_n_15_pp.CC = 9'd 184;
defparam Ur2_n_15_pp.CD = 9'd 164;
defparam Ur2_n_15_pp.CE = 9'd 197;
defparam Ur2_n_15_pp.CF = 9'd 177;
assign lut_val_2_n_15_pp[13] = lut_val_2_n_15_pp[8];
assign lut_val_2_n_15_pp[12] = lut_val_2_n_15_pp[8];
assign lut_val_2_n_15_pp[11] = lut_val_2_n_15_pp[8];
assign lut_val_2_n_15_pp[10] = lut_val_2_n_15_pp[8];
assign lut_val_2_n_15_pp[9] = lut_val_2_n_15_pp[8];
wire [13:0] lut_val_3_n_0_pp;
rom_lut_r_cen Ur3_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[0],sym_res_14_n[0],sym_res_13_n[0],sym_res_12_n[0] } ), .data_out( lut_val_3_n_0_pp[7:0]) ) ;
defparam Ur3_n_0_pp.DATA_WIDTH = 8;
defparam Ur3_n_0_pp.C0 = 8'd 0;
defparam Ur3_n_0_pp.C1 = 8'd 72;
defparam Ur3_n_0_pp.C2 = 8'd 251;
defparam Ur3_n_0_pp.C3 = 8'd 67;
defparam Ur3_n_0_pp.C4 = 8'd 214;
defparam Ur3_n_0_pp.C5 = 8'd 30;
defparam Ur3_n_0_pp.C6 = 8'd 209;
defparam Ur3_n_0_pp.C7 = 8'd 25;
defparam Ur3_n_0_pp.C8 = 8'd 1;
defparam Ur3_n_0_pp.C9 = 8'd 73;
defparam Ur3_n_0_pp.CA = 8'd 252;
defparam Ur3_n_0_pp.CB = 8'd 68;
defparam Ur3_n_0_pp.CC = 8'd 215;
defparam Ur3_n_0_pp.CD = 8'd 31;
defparam Ur3_n_0_pp.CE = 8'd 210;
defparam Ur3_n_0_pp.CF = 8'd 26;
assign lut_val_3_n_0_pp[13] = lut_val_3_n_0_pp[7];
assign lut_val_3_n_0_pp[12] = lut_val_3_n_0_pp[7];
assign lut_val_3_n_0_pp[11] = lut_val_3_n_0_pp[7];
assign lut_val_3_n_0_pp[10] = lut_val_3_n_0_pp[7];
assign lut_val_3_n_0_pp[9] = lut_val_3_n_0_pp[7];
assign lut_val_3_n_0_pp[8] = lut_val_3_n_0_pp[7];
wire [13:0] lut_val_3_n_1_pp;
rom_lut_r_cen Ur3_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[1],sym_res_14_n[1],sym_res_13_n[1],sym_res_12_n[1] } ), .data_out( lut_val_3_n_1_pp[7:0]) ) ;
defparam Ur3_n_1_pp.DATA_WIDTH = 8;
defparam Ur3_n_1_pp.C0 = 8'd 0;
defparam Ur3_n_1_pp.C1 = 8'd 72;
defparam Ur3_n_1_pp.C2 = 8'd 251;
defparam Ur3_n_1_pp.C3 = 8'd 67;
defparam Ur3_n_1_pp.C4 = 8'd 214;
defparam Ur3_n_1_pp.C5 = 8'd 30;
defparam Ur3_n_1_pp.C6 = 8'd 209;
defparam Ur3_n_1_pp.C7 = 8'd 25;
defparam Ur3_n_1_pp.C8 = 8'd 1;
defparam Ur3_n_1_pp.C9 = 8'd 73;
defparam Ur3_n_1_pp.CA = 8'd 252;
defparam Ur3_n_1_pp.CB = 8'd 68;
defparam Ur3_n_1_pp.CC = 8'd 215;
defparam Ur3_n_1_pp.CD = 8'd 31;
defparam Ur3_n_1_pp.CE = 8'd 210;
defparam Ur3_n_1_pp.CF = 8'd 26;
assign lut_val_3_n_1_pp[13] = lut_val_3_n_1_pp[7];
assign lut_val_3_n_1_pp[12] = lut_val_3_n_1_pp[7];
assign lut_val_3_n_1_pp[11] = lut_val_3_n_1_pp[7];
assign lut_val_3_n_1_pp[10] = lut_val_3_n_1_pp[7];
assign lut_val_3_n_1_pp[9] = lut_val_3_n_1_pp[7];
assign lut_val_3_n_1_pp[8] = lut_val_3_n_1_pp[7];
wire [13:0] lut_val_3_n_2_pp;
rom_lut_r_cen Ur3_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[2],sym_res_14_n[2],sym_res_13_n[2],sym_res_12_n[2] } ), .data_out( lut_val_3_n_2_pp[7:0]) ) ;
defparam Ur3_n_2_pp.DATA_WIDTH = 8;
defparam Ur3_n_2_pp.C0 = 8'd 0;
defparam Ur3_n_2_pp.C1 = 8'd 72;
defparam Ur3_n_2_pp.C2 = 8'd 251;
defparam Ur3_n_2_pp.C3 = 8'd 67;
defparam Ur3_n_2_pp.C4 = 8'd 214;
defparam Ur3_n_2_pp.C5 = 8'd 30;
defparam Ur3_n_2_pp.C6 = 8'd 209;
defparam Ur3_n_2_pp.C7 = 8'd 25;
defparam Ur3_n_2_pp.C8 = 8'd 1;
defparam Ur3_n_2_pp.C9 = 8'd 73;
defparam Ur3_n_2_pp.CA = 8'd 252;
defparam Ur3_n_2_pp.CB = 8'd 68;
defparam Ur3_n_2_pp.CC = 8'd 215;
defparam Ur3_n_2_pp.CD = 8'd 31;
defparam Ur3_n_2_pp.CE = 8'd 210;
defparam Ur3_n_2_pp.CF = 8'd 26;
assign lut_val_3_n_2_pp[13] = lut_val_3_n_2_pp[7];
assign lut_val_3_n_2_pp[12] = lut_val_3_n_2_pp[7];
assign lut_val_3_n_2_pp[11] = lut_val_3_n_2_pp[7];
assign lut_val_3_n_2_pp[10] = lut_val_3_n_2_pp[7];
assign lut_val_3_n_2_pp[9] = lut_val_3_n_2_pp[7];
assign lut_val_3_n_2_pp[8] = lut_val_3_n_2_pp[7];
wire [13:0] lut_val_3_n_3_pp;
rom_lut_r_cen Ur3_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[3],sym_res_14_n[3],sym_res_13_n[3],sym_res_12_n[3] } ), .data_out( lut_val_3_n_3_pp[7:0]) ) ;
defparam Ur3_n_3_pp.DATA_WIDTH = 8;
defparam Ur3_n_3_pp.C0 = 8'd 0;
defparam Ur3_n_3_pp.C1 = 8'd 72;
defparam Ur3_n_3_pp.C2 = 8'd 251;
defparam Ur3_n_3_pp.C3 = 8'd 67;
defparam Ur3_n_3_pp.C4 = 8'd 214;
defparam Ur3_n_3_pp.C5 = 8'd 30;
defparam Ur3_n_3_pp.C6 = 8'd 209;
defparam Ur3_n_3_pp.C7 = 8'd 25;
defparam Ur3_n_3_pp.C8 = 8'd 1;
defparam Ur3_n_3_pp.C9 = 8'd 73;
defparam Ur3_n_3_pp.CA = 8'd 252;
defparam Ur3_n_3_pp.CB = 8'd 68;
defparam Ur3_n_3_pp.CC = 8'd 215;
defparam Ur3_n_3_pp.CD = 8'd 31;
defparam Ur3_n_3_pp.CE = 8'd 210;
defparam Ur3_n_3_pp.CF = 8'd 26;
assign lut_val_3_n_3_pp[13] = lut_val_3_n_3_pp[7];
assign lut_val_3_n_3_pp[12] = lut_val_3_n_3_pp[7];
assign lut_val_3_n_3_pp[11] = lut_val_3_n_3_pp[7];
assign lut_val_3_n_3_pp[10] = lut_val_3_n_3_pp[7];
assign lut_val_3_n_3_pp[9] = lut_val_3_n_3_pp[7];
assign lut_val_3_n_3_pp[8] = lut_val_3_n_3_pp[7];
wire [13:0] lut_val_3_n_4_pp;
rom_lut_r_cen Ur3_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[4],sym_res_14_n[4],sym_res_13_n[4],sym_res_12_n[4] } ), .data_out( lut_val_3_n_4_pp[7:0]) ) ;
defparam Ur3_n_4_pp.DATA_WIDTH = 8;
defparam Ur3_n_4_pp.C0 = 8'd 0;
defparam Ur3_n_4_pp.C1 = 8'd 72;
defparam Ur3_n_4_pp.C2 = 8'd 251;
defparam Ur3_n_4_pp.C3 = 8'd 67;
defparam Ur3_n_4_pp.C4 = 8'd 214;
defparam Ur3_n_4_pp.C5 = 8'd 30;
defparam Ur3_n_4_pp.C6 = 8'd 209;
defparam Ur3_n_4_pp.C7 = 8'd 25;
defparam Ur3_n_4_pp.C8 = 8'd 1;
defparam Ur3_n_4_pp.C9 = 8'd 73;
defparam Ur3_n_4_pp.CA = 8'd 252;
defparam Ur3_n_4_pp.CB = 8'd 68;
defparam Ur3_n_4_pp.CC = 8'd 215;
defparam Ur3_n_4_pp.CD = 8'd 31;
defparam Ur3_n_4_pp.CE = 8'd 210;
defparam Ur3_n_4_pp.CF = 8'd 26;
assign lut_val_3_n_4_pp[13] = lut_val_3_n_4_pp[7];
assign lut_val_3_n_4_pp[12] = lut_val_3_n_4_pp[7];
assign lut_val_3_n_4_pp[11] = lut_val_3_n_4_pp[7];
assign lut_val_3_n_4_pp[10] = lut_val_3_n_4_pp[7];
assign lut_val_3_n_4_pp[9] = lut_val_3_n_4_pp[7];
assign lut_val_3_n_4_pp[8] = lut_val_3_n_4_pp[7];
wire [13:0] lut_val_3_n_5_pp;
rom_lut_r_cen Ur3_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[5],sym_res_14_n[5],sym_res_13_n[5],sym_res_12_n[5] } ), .data_out( lut_val_3_n_5_pp[7:0]) ) ;
defparam Ur3_n_5_pp.DATA_WIDTH = 8;
defparam Ur3_n_5_pp.C0 = 8'd 0;
defparam Ur3_n_5_pp.C1 = 8'd 72;
defparam Ur3_n_5_pp.C2 = 8'd 251;
defparam Ur3_n_5_pp.C3 = 8'd 67;
defparam Ur3_n_5_pp.C4 = 8'd 214;
defparam Ur3_n_5_pp.C5 = 8'd 30;
defparam Ur3_n_5_pp.C6 = 8'd 209;
defparam Ur3_n_5_pp.C7 = 8'd 25;
defparam Ur3_n_5_pp.C8 = 8'd 1;
defparam Ur3_n_5_pp.C9 = 8'd 73;
defparam Ur3_n_5_pp.CA = 8'd 252;
defparam Ur3_n_5_pp.CB = 8'd 68;
defparam Ur3_n_5_pp.CC = 8'd 215;
defparam Ur3_n_5_pp.CD = 8'd 31;
defparam Ur3_n_5_pp.CE = 8'd 210;
defparam Ur3_n_5_pp.CF = 8'd 26;
assign lut_val_3_n_5_pp[13] = lut_val_3_n_5_pp[7];
assign lut_val_3_n_5_pp[12] = lut_val_3_n_5_pp[7];
assign lut_val_3_n_5_pp[11] = lut_val_3_n_5_pp[7];
assign lut_val_3_n_5_pp[10] = lut_val_3_n_5_pp[7];
assign lut_val_3_n_5_pp[9] = lut_val_3_n_5_pp[7];
assign lut_val_3_n_5_pp[8] = lut_val_3_n_5_pp[7];
wire [13:0] lut_val_3_n_6_pp;
rom_lut_r_cen Ur3_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[6],sym_res_14_n[6],sym_res_13_n[6],sym_res_12_n[6] } ), .data_out( lut_val_3_n_6_pp[7:0]) ) ;
defparam Ur3_n_6_pp.DATA_WIDTH = 8;
defparam Ur3_n_6_pp.C0 = 8'd 0;
defparam Ur3_n_6_pp.C1 = 8'd 72;
defparam Ur3_n_6_pp.C2 = 8'd 251;
defparam Ur3_n_6_pp.C3 = 8'd 67;
defparam Ur3_n_6_pp.C4 = 8'd 214;
defparam Ur3_n_6_pp.C5 = 8'd 30;
defparam Ur3_n_6_pp.C6 = 8'd 209;
defparam Ur3_n_6_pp.C7 = 8'd 25;
defparam Ur3_n_6_pp.C8 = 8'd 1;
defparam Ur3_n_6_pp.C9 = 8'd 73;
defparam Ur3_n_6_pp.CA = 8'd 252;
defparam Ur3_n_6_pp.CB = 8'd 68;
defparam Ur3_n_6_pp.CC = 8'd 215;
defparam Ur3_n_6_pp.CD = 8'd 31;
defparam Ur3_n_6_pp.CE = 8'd 210;
defparam Ur3_n_6_pp.CF = 8'd 26;
assign lut_val_3_n_6_pp[13] = lut_val_3_n_6_pp[7];
assign lut_val_3_n_6_pp[12] = lut_val_3_n_6_pp[7];
assign lut_val_3_n_6_pp[11] = lut_val_3_n_6_pp[7];
assign lut_val_3_n_6_pp[10] = lut_val_3_n_6_pp[7];
assign lut_val_3_n_6_pp[9] = lut_val_3_n_6_pp[7];
assign lut_val_3_n_6_pp[8] = lut_val_3_n_6_pp[7];
wire [13:0] lut_val_3_n_7_pp;
rom_lut_r_cen Ur3_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[7],sym_res_14_n[7],sym_res_13_n[7],sym_res_12_n[7] } ), .data_out( lut_val_3_n_7_pp[7:0]) ) ;
defparam Ur3_n_7_pp.DATA_WIDTH = 8;
defparam Ur3_n_7_pp.C0 = 8'd 0;
defparam Ur3_n_7_pp.C1 = 8'd 72;
defparam Ur3_n_7_pp.C2 = 8'd 251;
defparam Ur3_n_7_pp.C3 = 8'd 67;
defparam Ur3_n_7_pp.C4 = 8'd 214;
defparam Ur3_n_7_pp.C5 = 8'd 30;
defparam Ur3_n_7_pp.C6 = 8'd 209;
defparam Ur3_n_7_pp.C7 = 8'd 25;
defparam Ur3_n_7_pp.C8 = 8'd 1;
defparam Ur3_n_7_pp.C9 = 8'd 73;
defparam Ur3_n_7_pp.CA = 8'd 252;
defparam Ur3_n_7_pp.CB = 8'd 68;
defparam Ur3_n_7_pp.CC = 8'd 215;
defparam Ur3_n_7_pp.CD = 8'd 31;
defparam Ur3_n_7_pp.CE = 8'd 210;
defparam Ur3_n_7_pp.CF = 8'd 26;
assign lut_val_3_n_7_pp[13] = lut_val_3_n_7_pp[7];
assign lut_val_3_n_7_pp[12] = lut_val_3_n_7_pp[7];
assign lut_val_3_n_7_pp[11] = lut_val_3_n_7_pp[7];
assign lut_val_3_n_7_pp[10] = lut_val_3_n_7_pp[7];
assign lut_val_3_n_7_pp[9] = lut_val_3_n_7_pp[7];
assign lut_val_3_n_7_pp[8] = lut_val_3_n_7_pp[7];
wire [13:0] lut_val_3_n_8_pp;
rom_lut_r_cen Ur3_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[8],sym_res_14_n[8],sym_res_13_n[8],sym_res_12_n[8] } ), .data_out( lut_val_3_n_8_pp[7:0]) ) ;
defparam Ur3_n_8_pp.DATA_WIDTH = 8;
defparam Ur3_n_8_pp.C0 = 8'd 0;
defparam Ur3_n_8_pp.C1 = 8'd 72;
defparam Ur3_n_8_pp.C2 = 8'd 251;
defparam Ur3_n_8_pp.C3 = 8'd 67;
defparam Ur3_n_8_pp.C4 = 8'd 214;
defparam Ur3_n_8_pp.C5 = 8'd 30;
defparam Ur3_n_8_pp.C6 = 8'd 209;
defparam Ur3_n_8_pp.C7 = 8'd 25;
defparam Ur3_n_8_pp.C8 = 8'd 1;
defparam Ur3_n_8_pp.C9 = 8'd 73;
defparam Ur3_n_8_pp.CA = 8'd 252;
defparam Ur3_n_8_pp.CB = 8'd 68;
defparam Ur3_n_8_pp.CC = 8'd 215;
defparam Ur3_n_8_pp.CD = 8'd 31;
defparam Ur3_n_8_pp.CE = 8'd 210;
defparam Ur3_n_8_pp.CF = 8'd 26;
assign lut_val_3_n_8_pp[13] = lut_val_3_n_8_pp[7];
assign lut_val_3_n_8_pp[12] = lut_val_3_n_8_pp[7];
assign lut_val_3_n_8_pp[11] = lut_val_3_n_8_pp[7];
assign lut_val_3_n_8_pp[10] = lut_val_3_n_8_pp[7];
assign lut_val_3_n_8_pp[9] = lut_val_3_n_8_pp[7];
assign lut_val_3_n_8_pp[8] = lut_val_3_n_8_pp[7];
wire [13:0] lut_val_3_n_9_pp;
rom_lut_r_cen Ur3_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[9],sym_res_14_n[9],sym_res_13_n[9],sym_res_12_n[9] } ), .data_out( lut_val_3_n_9_pp[7:0]) ) ;
defparam Ur3_n_9_pp.DATA_WIDTH = 8;
defparam Ur3_n_9_pp.C0 = 8'd 0;
defparam Ur3_n_9_pp.C1 = 8'd 72;
defparam Ur3_n_9_pp.C2 = 8'd 251;
defparam Ur3_n_9_pp.C3 = 8'd 67;
defparam Ur3_n_9_pp.C4 = 8'd 214;
defparam Ur3_n_9_pp.C5 = 8'd 30;
defparam Ur3_n_9_pp.C6 = 8'd 209;
defparam Ur3_n_9_pp.C7 = 8'd 25;
defparam Ur3_n_9_pp.C8 = 8'd 1;
defparam Ur3_n_9_pp.C9 = 8'd 73;
defparam Ur3_n_9_pp.CA = 8'd 252;
defparam Ur3_n_9_pp.CB = 8'd 68;
defparam Ur3_n_9_pp.CC = 8'd 215;
defparam Ur3_n_9_pp.CD = 8'd 31;
defparam Ur3_n_9_pp.CE = 8'd 210;
defparam Ur3_n_9_pp.CF = 8'd 26;
assign lut_val_3_n_9_pp[13] = lut_val_3_n_9_pp[7];
assign lut_val_3_n_9_pp[12] = lut_val_3_n_9_pp[7];
assign lut_val_3_n_9_pp[11] = lut_val_3_n_9_pp[7];
assign lut_val_3_n_9_pp[10] = lut_val_3_n_9_pp[7];
assign lut_val_3_n_9_pp[9] = lut_val_3_n_9_pp[7];
assign lut_val_3_n_9_pp[8] = lut_val_3_n_9_pp[7];
wire [13:0] lut_val_3_n_10_pp;
rom_lut_r_cen Ur3_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[10],sym_res_14_n[10],sym_res_13_n[10],sym_res_12_n[10] } ), .data_out( lut_val_3_n_10_pp[7:0]) ) ;
defparam Ur3_n_10_pp.DATA_WIDTH = 8;
defparam Ur3_n_10_pp.C0 = 8'd 0;
defparam Ur3_n_10_pp.C1 = 8'd 72;
defparam Ur3_n_10_pp.C2 = 8'd 251;
defparam Ur3_n_10_pp.C3 = 8'd 67;
defparam Ur3_n_10_pp.C4 = 8'd 214;
defparam Ur3_n_10_pp.C5 = 8'd 30;
defparam Ur3_n_10_pp.C6 = 8'd 209;
defparam Ur3_n_10_pp.C7 = 8'd 25;
defparam Ur3_n_10_pp.C8 = 8'd 1;
defparam Ur3_n_10_pp.C9 = 8'd 73;
defparam Ur3_n_10_pp.CA = 8'd 252;
defparam Ur3_n_10_pp.CB = 8'd 68;
defparam Ur3_n_10_pp.CC = 8'd 215;
defparam Ur3_n_10_pp.CD = 8'd 31;
defparam Ur3_n_10_pp.CE = 8'd 210;
defparam Ur3_n_10_pp.CF = 8'd 26;
assign lut_val_3_n_10_pp[13] = lut_val_3_n_10_pp[7];
assign lut_val_3_n_10_pp[12] = lut_val_3_n_10_pp[7];
assign lut_val_3_n_10_pp[11] = lut_val_3_n_10_pp[7];
assign lut_val_3_n_10_pp[10] = lut_val_3_n_10_pp[7];
assign lut_val_3_n_10_pp[9] = lut_val_3_n_10_pp[7];
assign lut_val_3_n_10_pp[8] = lut_val_3_n_10_pp[7];
wire [13:0] lut_val_3_n_11_pp;
rom_lut_r_cen Ur3_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[11],sym_res_14_n[11],sym_res_13_n[11],sym_res_12_n[11] } ), .data_out( lut_val_3_n_11_pp[7:0]) ) ;
defparam Ur3_n_11_pp.DATA_WIDTH = 8;
defparam Ur3_n_11_pp.C0 = 8'd 0;
defparam Ur3_n_11_pp.C1 = 8'd 72;
defparam Ur3_n_11_pp.C2 = 8'd 251;
defparam Ur3_n_11_pp.C3 = 8'd 67;
defparam Ur3_n_11_pp.C4 = 8'd 214;
defparam Ur3_n_11_pp.C5 = 8'd 30;
defparam Ur3_n_11_pp.C6 = 8'd 209;
defparam Ur3_n_11_pp.C7 = 8'd 25;
defparam Ur3_n_11_pp.C8 = 8'd 1;
defparam Ur3_n_11_pp.C9 = 8'd 73;
defparam Ur3_n_11_pp.CA = 8'd 252;
defparam Ur3_n_11_pp.CB = 8'd 68;
defparam Ur3_n_11_pp.CC = 8'd 215;
defparam Ur3_n_11_pp.CD = 8'd 31;
defparam Ur3_n_11_pp.CE = 8'd 210;
defparam Ur3_n_11_pp.CF = 8'd 26;
assign lut_val_3_n_11_pp[13] = lut_val_3_n_11_pp[7];
assign lut_val_3_n_11_pp[12] = lut_val_3_n_11_pp[7];
assign lut_val_3_n_11_pp[11] = lut_val_3_n_11_pp[7];
assign lut_val_3_n_11_pp[10] = lut_val_3_n_11_pp[7];
assign lut_val_3_n_11_pp[9] = lut_val_3_n_11_pp[7];
assign lut_val_3_n_11_pp[8] = lut_val_3_n_11_pp[7];
wire [13:0] lut_val_3_n_12_pp;
rom_lut_r_cen Ur3_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[12],sym_res_14_n[12],sym_res_13_n[12],sym_res_12_n[12] } ), .data_out( lut_val_3_n_12_pp[7:0]) ) ;
defparam Ur3_n_12_pp.DATA_WIDTH = 8;
defparam Ur3_n_12_pp.C0 = 8'd 0;
defparam Ur3_n_12_pp.C1 = 8'd 72;
defparam Ur3_n_12_pp.C2 = 8'd 251;
defparam Ur3_n_12_pp.C3 = 8'd 67;
defparam Ur3_n_12_pp.C4 = 8'd 214;
defparam Ur3_n_12_pp.C5 = 8'd 30;
defparam Ur3_n_12_pp.C6 = 8'd 209;
defparam Ur3_n_12_pp.C7 = 8'd 25;
defparam Ur3_n_12_pp.C8 = 8'd 1;
defparam Ur3_n_12_pp.C9 = 8'd 73;
defparam Ur3_n_12_pp.CA = 8'd 252;
defparam Ur3_n_12_pp.CB = 8'd 68;
defparam Ur3_n_12_pp.CC = 8'd 215;
defparam Ur3_n_12_pp.CD = 8'd 31;
defparam Ur3_n_12_pp.CE = 8'd 210;
defparam Ur3_n_12_pp.CF = 8'd 26;
assign lut_val_3_n_12_pp[13] = lut_val_3_n_12_pp[7];
assign lut_val_3_n_12_pp[12] = lut_val_3_n_12_pp[7];
assign lut_val_3_n_12_pp[11] = lut_val_3_n_12_pp[7];
assign lut_val_3_n_12_pp[10] = lut_val_3_n_12_pp[7];
assign lut_val_3_n_12_pp[9] = lut_val_3_n_12_pp[7];
assign lut_val_3_n_12_pp[8] = lut_val_3_n_12_pp[7];
wire [13:0] lut_val_3_n_13_pp;
rom_lut_r_cen Ur3_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[13],sym_res_14_n[13],sym_res_13_n[13],sym_res_12_n[13] } ), .data_out( lut_val_3_n_13_pp[7:0]) ) ;
defparam Ur3_n_13_pp.DATA_WIDTH = 8;
defparam Ur3_n_13_pp.C0 = 8'd 0;
defparam Ur3_n_13_pp.C1 = 8'd 72;
defparam Ur3_n_13_pp.C2 = 8'd 251;
defparam Ur3_n_13_pp.C3 = 8'd 67;
defparam Ur3_n_13_pp.C4 = 8'd 214;
defparam Ur3_n_13_pp.C5 = 8'd 30;
defparam Ur3_n_13_pp.C6 = 8'd 209;
defparam Ur3_n_13_pp.C7 = 8'd 25;
defparam Ur3_n_13_pp.C8 = 8'd 1;
defparam Ur3_n_13_pp.C9 = 8'd 73;
defparam Ur3_n_13_pp.CA = 8'd 252;
defparam Ur3_n_13_pp.CB = 8'd 68;
defparam Ur3_n_13_pp.CC = 8'd 215;
defparam Ur3_n_13_pp.CD = 8'd 31;
defparam Ur3_n_13_pp.CE = 8'd 210;
defparam Ur3_n_13_pp.CF = 8'd 26;
assign lut_val_3_n_13_pp[13] = lut_val_3_n_13_pp[7];
assign lut_val_3_n_13_pp[12] = lut_val_3_n_13_pp[7];
assign lut_val_3_n_13_pp[11] = lut_val_3_n_13_pp[7];
assign lut_val_3_n_13_pp[10] = lut_val_3_n_13_pp[7];
assign lut_val_3_n_13_pp[9] = lut_val_3_n_13_pp[7];
assign lut_val_3_n_13_pp[8] = lut_val_3_n_13_pp[7];
wire [13:0] lut_val_3_n_14_pp;
rom_lut_r_cen Ur3_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[14],sym_res_14_n[14],sym_res_13_n[14],sym_res_12_n[14] } ), .data_out( lut_val_3_n_14_pp[7:0]) ) ;
defparam Ur3_n_14_pp.DATA_WIDTH = 8;
defparam Ur3_n_14_pp.C0 = 8'd 0;
defparam Ur3_n_14_pp.C1 = 8'd 72;
defparam Ur3_n_14_pp.C2 = 8'd 251;
defparam Ur3_n_14_pp.C3 = 8'd 67;
defparam Ur3_n_14_pp.C4 = 8'd 214;
defparam Ur3_n_14_pp.C5 = 8'd 30;
defparam Ur3_n_14_pp.C6 = 8'd 209;
defparam Ur3_n_14_pp.C7 = 8'd 25;
defparam Ur3_n_14_pp.C8 = 8'd 1;
defparam Ur3_n_14_pp.C9 = 8'd 73;
defparam Ur3_n_14_pp.CA = 8'd 252;
defparam Ur3_n_14_pp.CB = 8'd 68;
defparam Ur3_n_14_pp.CC = 8'd 215;
defparam Ur3_n_14_pp.CD = 8'd 31;
defparam Ur3_n_14_pp.CE = 8'd 210;
defparam Ur3_n_14_pp.CF = 8'd 26;
assign lut_val_3_n_14_pp[13] = lut_val_3_n_14_pp[7];
assign lut_val_3_n_14_pp[12] = lut_val_3_n_14_pp[7];
assign lut_val_3_n_14_pp[11] = lut_val_3_n_14_pp[7];
assign lut_val_3_n_14_pp[10] = lut_val_3_n_14_pp[7];
assign lut_val_3_n_14_pp[9] = lut_val_3_n_14_pp[7];
assign lut_val_3_n_14_pp[8] = lut_val_3_n_14_pp[7];
wire [13:0] lut_val_3_n_15_pp;
rom_lut_r_cen Ur3_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[15],sym_res_14_n[15],sym_res_13_n[15],sym_res_12_n[15] } ), .data_out( lut_val_3_n_15_pp[7:0]) ) ;
defparam Ur3_n_15_pp.DATA_WIDTH = 8;
defparam Ur3_n_15_pp.C0 = 8'd 0;
defparam Ur3_n_15_pp.C1 = 8'd 72;
defparam Ur3_n_15_pp.C2 = 8'd 251;
defparam Ur3_n_15_pp.C3 = 8'd 67;
defparam Ur3_n_15_pp.C4 = 8'd 214;
defparam Ur3_n_15_pp.C5 = 8'd 30;
defparam Ur3_n_15_pp.C6 = 8'd 209;
defparam Ur3_n_15_pp.C7 = 8'd 25;
defparam Ur3_n_15_pp.C8 = 8'd 1;
defparam Ur3_n_15_pp.C9 = 8'd 73;
defparam Ur3_n_15_pp.CA = 8'd 252;
defparam Ur3_n_15_pp.CB = 8'd 68;
defparam Ur3_n_15_pp.CC = 8'd 215;
defparam Ur3_n_15_pp.CD = 8'd 31;
defparam Ur3_n_15_pp.CE = 8'd 210;
defparam Ur3_n_15_pp.CF = 8'd 26;
assign lut_val_3_n_15_pp[13] = lut_val_3_n_15_pp[7];
assign lut_val_3_n_15_pp[12] = lut_val_3_n_15_pp[7];
assign lut_val_3_n_15_pp[11] = lut_val_3_n_15_pp[7];
assign lut_val_3_n_15_pp[10] = lut_val_3_n_15_pp[7];
assign lut_val_3_n_15_pp[9] = lut_val_3_n_15_pp[7];
assign lut_val_3_n_15_pp[8] = lut_val_3_n_15_pp[7];
wire [13:0] lut_val_4_n_0_pp;
rom_lut_r_cen Ur4_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[0],sym_res_18_n[0],sym_res_17_n[0],sym_res_16_n[0] } ), .data_out( lut_val_4_n_0_pp[9:0]) ) ;
defparam Ur4_n_0_pp.DATA_WIDTH = 10;
defparam Ur4_n_0_pp.C0 = 10'd 0;
defparam Ur4_n_0_pp.C1 = 10'd 55;
defparam Ur4_n_0_pp.C2 = 10'd 9;
defparam Ur4_n_0_pp.C3 = 10'd 64;
defparam Ur4_n_0_pp.C4 = 10'd 877;
defparam Ur4_n_0_pp.C5 = 10'd 932;
defparam Ur4_n_0_pp.C6 = 10'd 886;
defparam Ur4_n_0_pp.C7 = 10'd 941;
defparam Ur4_n_0_pp.C8 = 10'd 743;
defparam Ur4_n_0_pp.C9 = 10'd 798;
defparam Ur4_n_0_pp.CA = 10'd 752;
defparam Ur4_n_0_pp.CB = 10'd 807;
defparam Ur4_n_0_pp.CC = 10'd 596;
defparam Ur4_n_0_pp.CD = 10'd 651;
defparam Ur4_n_0_pp.CE = 10'd 605;
defparam Ur4_n_0_pp.CF = 10'd 660;
assign lut_val_4_n_0_pp[13] = lut_val_4_n_0_pp[9];
assign lut_val_4_n_0_pp[12] = lut_val_4_n_0_pp[9];
assign lut_val_4_n_0_pp[11] = lut_val_4_n_0_pp[9];
assign lut_val_4_n_0_pp[10] = lut_val_4_n_0_pp[9];
wire [13:0] lut_val_4_n_1_pp;
rom_lut_r_cen Ur4_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[1],sym_res_18_n[1],sym_res_17_n[1],sym_res_16_n[1] } ), .data_out( lut_val_4_n_1_pp[9:0]) ) ;
defparam Ur4_n_1_pp.DATA_WIDTH = 10;
defparam Ur4_n_1_pp.C0 = 10'd 0;
defparam Ur4_n_1_pp.C1 = 10'd 55;
defparam Ur4_n_1_pp.C2 = 10'd 9;
defparam Ur4_n_1_pp.C3 = 10'd 64;
defparam Ur4_n_1_pp.C4 = 10'd 877;
defparam Ur4_n_1_pp.C5 = 10'd 932;
defparam Ur4_n_1_pp.C6 = 10'd 886;
defparam Ur4_n_1_pp.C7 = 10'd 941;
defparam Ur4_n_1_pp.C8 = 10'd 743;
defparam Ur4_n_1_pp.C9 = 10'd 798;
defparam Ur4_n_1_pp.CA = 10'd 752;
defparam Ur4_n_1_pp.CB = 10'd 807;
defparam Ur4_n_1_pp.CC = 10'd 596;
defparam Ur4_n_1_pp.CD = 10'd 651;
defparam Ur4_n_1_pp.CE = 10'd 605;
defparam Ur4_n_1_pp.CF = 10'd 660;
assign lut_val_4_n_1_pp[13] = lut_val_4_n_1_pp[9];
assign lut_val_4_n_1_pp[12] = lut_val_4_n_1_pp[9];
assign lut_val_4_n_1_pp[11] = lut_val_4_n_1_pp[9];
assign lut_val_4_n_1_pp[10] = lut_val_4_n_1_pp[9];
wire [13:0] lut_val_4_n_2_pp;
rom_lut_r_cen Ur4_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[2],sym_res_18_n[2],sym_res_17_n[2],sym_res_16_n[2] } ), .data_out( lut_val_4_n_2_pp[9:0]) ) ;
defparam Ur4_n_2_pp.DATA_WIDTH = 10;
defparam Ur4_n_2_pp.C0 = 10'd 0;
defparam Ur4_n_2_pp.C1 = 10'd 55;
defparam Ur4_n_2_pp.C2 = 10'd 9;
defparam Ur4_n_2_pp.C3 = 10'd 64;
defparam Ur4_n_2_pp.C4 = 10'd 877;
defparam Ur4_n_2_pp.C5 = 10'd 932;
defparam Ur4_n_2_pp.C6 = 10'd 886;
defparam Ur4_n_2_pp.C7 = 10'd 941;
defparam Ur4_n_2_pp.C8 = 10'd 743;
defparam Ur4_n_2_pp.C9 = 10'd 798;
defparam Ur4_n_2_pp.CA = 10'd 752;
defparam Ur4_n_2_pp.CB = 10'd 807;
defparam Ur4_n_2_pp.CC = 10'd 596;
defparam Ur4_n_2_pp.CD = 10'd 651;
defparam Ur4_n_2_pp.CE = 10'd 605;
defparam Ur4_n_2_pp.CF = 10'd 660;
assign lut_val_4_n_2_pp[13] = lut_val_4_n_2_pp[9];
assign lut_val_4_n_2_pp[12] = lut_val_4_n_2_pp[9];
assign lut_val_4_n_2_pp[11] = lut_val_4_n_2_pp[9];
assign lut_val_4_n_2_pp[10] = lut_val_4_n_2_pp[9];
wire [13:0] lut_val_4_n_3_pp;
rom_lut_r_cen Ur4_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[3],sym_res_18_n[3],sym_res_17_n[3],sym_res_16_n[3] } ), .data_out( lut_val_4_n_3_pp[9:0]) ) ;
defparam Ur4_n_3_pp.DATA_WIDTH = 10;
defparam Ur4_n_3_pp.C0 = 10'd 0;
defparam Ur4_n_3_pp.C1 = 10'd 55;
defparam Ur4_n_3_pp.C2 = 10'd 9;
defparam Ur4_n_3_pp.C3 = 10'd 64;
defparam Ur4_n_3_pp.C4 = 10'd 877;
defparam Ur4_n_3_pp.C5 = 10'd 932;
defparam Ur4_n_3_pp.C6 = 10'd 886;
defparam Ur4_n_3_pp.C7 = 10'd 941;
defparam Ur4_n_3_pp.C8 = 10'd 743;
defparam Ur4_n_3_pp.C9 = 10'd 798;
defparam Ur4_n_3_pp.CA = 10'd 752;
defparam Ur4_n_3_pp.CB = 10'd 807;
defparam Ur4_n_3_pp.CC = 10'd 596;
defparam Ur4_n_3_pp.CD = 10'd 651;
defparam Ur4_n_3_pp.CE = 10'd 605;
defparam Ur4_n_3_pp.CF = 10'd 660;
assign lut_val_4_n_3_pp[13] = lut_val_4_n_3_pp[9];
assign lut_val_4_n_3_pp[12] = lut_val_4_n_3_pp[9];
assign lut_val_4_n_3_pp[11] = lut_val_4_n_3_pp[9];
assign lut_val_4_n_3_pp[10] = lut_val_4_n_3_pp[9];
wire [13:0] lut_val_4_n_4_pp;
rom_lut_r_cen Ur4_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[4],sym_res_18_n[4],sym_res_17_n[4],sym_res_16_n[4] } ), .data_out( lut_val_4_n_4_pp[9:0]) ) ;
defparam Ur4_n_4_pp.DATA_WIDTH = 10;
defparam Ur4_n_4_pp.C0 = 10'd 0;
defparam Ur4_n_4_pp.C1 = 10'd 55;
defparam Ur4_n_4_pp.C2 = 10'd 9;
defparam Ur4_n_4_pp.C3 = 10'd 64;
defparam Ur4_n_4_pp.C4 = 10'd 877;
defparam Ur4_n_4_pp.C5 = 10'd 932;
defparam Ur4_n_4_pp.C6 = 10'd 886;
defparam Ur4_n_4_pp.C7 = 10'd 941;
defparam Ur4_n_4_pp.C8 = 10'd 743;
defparam Ur4_n_4_pp.C9 = 10'd 798;
defparam Ur4_n_4_pp.CA = 10'd 752;
defparam Ur4_n_4_pp.CB = 10'd 807;
defparam Ur4_n_4_pp.CC = 10'd 596;
defparam Ur4_n_4_pp.CD = 10'd 651;
defparam Ur4_n_4_pp.CE = 10'd 605;
defparam Ur4_n_4_pp.CF = 10'd 660;
assign lut_val_4_n_4_pp[13] = lut_val_4_n_4_pp[9];
assign lut_val_4_n_4_pp[12] = lut_val_4_n_4_pp[9];
assign lut_val_4_n_4_pp[11] = lut_val_4_n_4_pp[9];
assign lut_val_4_n_4_pp[10] = lut_val_4_n_4_pp[9];
wire [13:0] lut_val_4_n_5_pp;
rom_lut_r_cen Ur4_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[5],sym_res_18_n[5],sym_res_17_n[5],sym_res_16_n[5] } ), .data_out( lut_val_4_n_5_pp[9:0]) ) ;
defparam Ur4_n_5_pp.DATA_WIDTH = 10;
defparam Ur4_n_5_pp.C0 = 10'd 0;
defparam Ur4_n_5_pp.C1 = 10'd 55;
defparam Ur4_n_5_pp.C2 = 10'd 9;
defparam Ur4_n_5_pp.C3 = 10'd 64;
defparam Ur4_n_5_pp.C4 = 10'd 877;
defparam Ur4_n_5_pp.C5 = 10'd 932;
defparam Ur4_n_5_pp.C6 = 10'd 886;
defparam Ur4_n_5_pp.C7 = 10'd 941;
defparam Ur4_n_5_pp.C8 = 10'd 743;
defparam Ur4_n_5_pp.C9 = 10'd 798;
defparam Ur4_n_5_pp.CA = 10'd 752;
defparam Ur4_n_5_pp.CB = 10'd 807;
defparam Ur4_n_5_pp.CC = 10'd 596;
defparam Ur4_n_5_pp.CD = 10'd 651;
defparam Ur4_n_5_pp.CE = 10'd 605;
defparam Ur4_n_5_pp.CF = 10'd 660;
assign lut_val_4_n_5_pp[13] = lut_val_4_n_5_pp[9];
assign lut_val_4_n_5_pp[12] = lut_val_4_n_5_pp[9];
assign lut_val_4_n_5_pp[11] = lut_val_4_n_5_pp[9];
assign lut_val_4_n_5_pp[10] = lut_val_4_n_5_pp[9];
wire [13:0] lut_val_4_n_6_pp;
rom_lut_r_cen Ur4_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[6],sym_res_18_n[6],sym_res_17_n[6],sym_res_16_n[6] } ), .data_out( lut_val_4_n_6_pp[9:0]) ) ;
defparam Ur4_n_6_pp.DATA_WIDTH = 10;
defparam Ur4_n_6_pp.C0 = 10'd 0;
defparam Ur4_n_6_pp.C1 = 10'd 55;
defparam Ur4_n_6_pp.C2 = 10'd 9;
defparam Ur4_n_6_pp.C3 = 10'd 64;
defparam Ur4_n_6_pp.C4 = 10'd 877;
defparam Ur4_n_6_pp.C5 = 10'd 932;
defparam Ur4_n_6_pp.C6 = 10'd 886;
defparam Ur4_n_6_pp.C7 = 10'd 941;
defparam Ur4_n_6_pp.C8 = 10'd 743;
defparam Ur4_n_6_pp.C9 = 10'd 798;
defparam Ur4_n_6_pp.CA = 10'd 752;
defparam Ur4_n_6_pp.CB = 10'd 807;
defparam Ur4_n_6_pp.CC = 10'd 596;
defparam Ur4_n_6_pp.CD = 10'd 651;
defparam Ur4_n_6_pp.CE = 10'd 605;
defparam Ur4_n_6_pp.CF = 10'd 660;
assign lut_val_4_n_6_pp[13] = lut_val_4_n_6_pp[9];
assign lut_val_4_n_6_pp[12] = lut_val_4_n_6_pp[9];
assign lut_val_4_n_6_pp[11] = lut_val_4_n_6_pp[9];
assign lut_val_4_n_6_pp[10] = lut_val_4_n_6_pp[9];
wire [13:0] lut_val_4_n_7_pp;
rom_lut_r_cen Ur4_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[7],sym_res_18_n[7],sym_res_17_n[7],sym_res_16_n[7] } ), .data_out( lut_val_4_n_7_pp[9:0]) ) ;
defparam Ur4_n_7_pp.DATA_WIDTH = 10;
defparam Ur4_n_7_pp.C0 = 10'd 0;
defparam Ur4_n_7_pp.C1 = 10'd 55;
defparam Ur4_n_7_pp.C2 = 10'd 9;
defparam Ur4_n_7_pp.C3 = 10'd 64;
defparam Ur4_n_7_pp.C4 = 10'd 877;
defparam Ur4_n_7_pp.C5 = 10'd 932;
defparam Ur4_n_7_pp.C6 = 10'd 886;
defparam Ur4_n_7_pp.C7 = 10'd 941;
defparam Ur4_n_7_pp.C8 = 10'd 743;
defparam Ur4_n_7_pp.C9 = 10'd 798;
defparam Ur4_n_7_pp.CA = 10'd 752;
defparam Ur4_n_7_pp.CB = 10'd 807;
defparam Ur4_n_7_pp.CC = 10'd 596;
defparam Ur4_n_7_pp.CD = 10'd 651;
defparam Ur4_n_7_pp.CE = 10'd 605;
defparam Ur4_n_7_pp.CF = 10'd 660;
assign lut_val_4_n_7_pp[13] = lut_val_4_n_7_pp[9];
assign lut_val_4_n_7_pp[12] = lut_val_4_n_7_pp[9];
assign lut_val_4_n_7_pp[11] = lut_val_4_n_7_pp[9];
assign lut_val_4_n_7_pp[10] = lut_val_4_n_7_pp[9];
wire [13:0] lut_val_4_n_8_pp;
rom_lut_r_cen Ur4_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[8],sym_res_18_n[8],sym_res_17_n[8],sym_res_16_n[8] } ), .data_out( lut_val_4_n_8_pp[9:0]) ) ;
defparam Ur4_n_8_pp.DATA_WIDTH = 10;
defparam Ur4_n_8_pp.C0 = 10'd 0;
defparam Ur4_n_8_pp.C1 = 10'd 55;
defparam Ur4_n_8_pp.C2 = 10'd 9;
defparam Ur4_n_8_pp.C3 = 10'd 64;
defparam Ur4_n_8_pp.C4 = 10'd 877;
defparam Ur4_n_8_pp.C5 = 10'd 932;
defparam Ur4_n_8_pp.C6 = 10'd 886;
defparam Ur4_n_8_pp.C7 = 10'd 941;
defparam Ur4_n_8_pp.C8 = 10'd 743;
defparam Ur4_n_8_pp.C9 = 10'd 798;
defparam Ur4_n_8_pp.CA = 10'd 752;
defparam Ur4_n_8_pp.CB = 10'd 807;
defparam Ur4_n_8_pp.CC = 10'd 596;
defparam Ur4_n_8_pp.CD = 10'd 651;
defparam Ur4_n_8_pp.CE = 10'd 605;
defparam Ur4_n_8_pp.CF = 10'd 660;
assign lut_val_4_n_8_pp[13] = lut_val_4_n_8_pp[9];
assign lut_val_4_n_8_pp[12] = lut_val_4_n_8_pp[9];
assign lut_val_4_n_8_pp[11] = lut_val_4_n_8_pp[9];
assign lut_val_4_n_8_pp[10] = lut_val_4_n_8_pp[9];
wire [13:0] lut_val_4_n_9_pp;
rom_lut_r_cen Ur4_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[9],sym_res_18_n[9],sym_res_17_n[9],sym_res_16_n[9] } ), .data_out( lut_val_4_n_9_pp[9:0]) ) ;
defparam Ur4_n_9_pp.DATA_WIDTH = 10;
defparam Ur4_n_9_pp.C0 = 10'd 0;
defparam Ur4_n_9_pp.C1 = 10'd 55;
defparam Ur4_n_9_pp.C2 = 10'd 9;
defparam Ur4_n_9_pp.C3 = 10'd 64;
defparam Ur4_n_9_pp.C4 = 10'd 877;
defparam Ur4_n_9_pp.C5 = 10'd 932;
defparam Ur4_n_9_pp.C6 = 10'd 886;
defparam Ur4_n_9_pp.C7 = 10'd 941;
defparam Ur4_n_9_pp.C8 = 10'd 743;
defparam Ur4_n_9_pp.C9 = 10'd 798;
defparam Ur4_n_9_pp.CA = 10'd 752;
defparam Ur4_n_9_pp.CB = 10'd 807;
defparam Ur4_n_9_pp.CC = 10'd 596;
defparam Ur4_n_9_pp.CD = 10'd 651;
defparam Ur4_n_9_pp.CE = 10'd 605;
defparam Ur4_n_9_pp.CF = 10'd 660;
assign lut_val_4_n_9_pp[13] = lut_val_4_n_9_pp[9];
assign lut_val_4_n_9_pp[12] = lut_val_4_n_9_pp[9];
assign lut_val_4_n_9_pp[11] = lut_val_4_n_9_pp[9];
assign lut_val_4_n_9_pp[10] = lut_val_4_n_9_pp[9];
wire [13:0] lut_val_4_n_10_pp;
rom_lut_r_cen Ur4_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[10],sym_res_18_n[10],sym_res_17_n[10],sym_res_16_n[10] } ), .data_out( lut_val_4_n_10_pp[9:0]) ) ;
defparam Ur4_n_10_pp.DATA_WIDTH = 10;
defparam Ur4_n_10_pp.C0 = 10'd 0;
defparam Ur4_n_10_pp.C1 = 10'd 55;
defparam Ur4_n_10_pp.C2 = 10'd 9;
defparam Ur4_n_10_pp.C3 = 10'd 64;
defparam Ur4_n_10_pp.C4 = 10'd 877;
defparam Ur4_n_10_pp.C5 = 10'd 932;
defparam Ur4_n_10_pp.C6 = 10'd 886;
defparam Ur4_n_10_pp.C7 = 10'd 941;
defparam Ur4_n_10_pp.C8 = 10'd 743;
defparam Ur4_n_10_pp.C9 = 10'd 798;
defparam Ur4_n_10_pp.CA = 10'd 752;
defparam Ur4_n_10_pp.CB = 10'd 807;
defparam Ur4_n_10_pp.CC = 10'd 596;
defparam Ur4_n_10_pp.CD = 10'd 651;
defparam Ur4_n_10_pp.CE = 10'd 605;
defparam Ur4_n_10_pp.CF = 10'd 660;
assign lut_val_4_n_10_pp[13] = lut_val_4_n_10_pp[9];
assign lut_val_4_n_10_pp[12] = lut_val_4_n_10_pp[9];
assign lut_val_4_n_10_pp[11] = lut_val_4_n_10_pp[9];
assign lut_val_4_n_10_pp[10] = lut_val_4_n_10_pp[9];
wire [13:0] lut_val_4_n_11_pp;
rom_lut_r_cen Ur4_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[11],sym_res_18_n[11],sym_res_17_n[11],sym_res_16_n[11] } ), .data_out( lut_val_4_n_11_pp[9:0]) ) ;
defparam Ur4_n_11_pp.DATA_WIDTH = 10;
defparam Ur4_n_11_pp.C0 = 10'd 0;
defparam Ur4_n_11_pp.C1 = 10'd 55;
defparam Ur4_n_11_pp.C2 = 10'd 9;
defparam Ur4_n_11_pp.C3 = 10'd 64;
defparam Ur4_n_11_pp.C4 = 10'd 877;
defparam Ur4_n_11_pp.C5 = 10'd 932;
defparam Ur4_n_11_pp.C6 = 10'd 886;
defparam Ur4_n_11_pp.C7 = 10'd 941;
defparam Ur4_n_11_pp.C8 = 10'd 743;
defparam Ur4_n_11_pp.C9 = 10'd 798;
defparam Ur4_n_11_pp.CA = 10'd 752;
defparam Ur4_n_11_pp.CB = 10'd 807;
defparam Ur4_n_11_pp.CC = 10'd 596;
defparam Ur4_n_11_pp.CD = 10'd 651;
defparam Ur4_n_11_pp.CE = 10'd 605;
defparam Ur4_n_11_pp.CF = 10'd 660;
assign lut_val_4_n_11_pp[13] = lut_val_4_n_11_pp[9];
assign lut_val_4_n_11_pp[12] = lut_val_4_n_11_pp[9];
assign lut_val_4_n_11_pp[11] = lut_val_4_n_11_pp[9];
assign lut_val_4_n_11_pp[10] = lut_val_4_n_11_pp[9];
wire [13:0] lut_val_4_n_12_pp;
rom_lut_r_cen Ur4_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[12],sym_res_18_n[12],sym_res_17_n[12],sym_res_16_n[12] } ), .data_out( lut_val_4_n_12_pp[9:0]) ) ;
defparam Ur4_n_12_pp.DATA_WIDTH = 10;
defparam Ur4_n_12_pp.C0 = 10'd 0;
defparam Ur4_n_12_pp.C1 = 10'd 55;
defparam Ur4_n_12_pp.C2 = 10'd 9;
defparam Ur4_n_12_pp.C3 = 10'd 64;
defparam Ur4_n_12_pp.C4 = 10'd 877;
defparam Ur4_n_12_pp.C5 = 10'd 932;
defparam Ur4_n_12_pp.C6 = 10'd 886;
defparam Ur4_n_12_pp.C7 = 10'd 941;
defparam Ur4_n_12_pp.C8 = 10'd 743;
defparam Ur4_n_12_pp.C9 = 10'd 798;
defparam Ur4_n_12_pp.CA = 10'd 752;
defparam Ur4_n_12_pp.CB = 10'd 807;
defparam Ur4_n_12_pp.CC = 10'd 596;
defparam Ur4_n_12_pp.CD = 10'd 651;
defparam Ur4_n_12_pp.CE = 10'd 605;
defparam Ur4_n_12_pp.CF = 10'd 660;
assign lut_val_4_n_12_pp[13] = lut_val_4_n_12_pp[9];
assign lut_val_4_n_12_pp[12] = lut_val_4_n_12_pp[9];
assign lut_val_4_n_12_pp[11] = lut_val_4_n_12_pp[9];
assign lut_val_4_n_12_pp[10] = lut_val_4_n_12_pp[9];
wire [13:0] lut_val_4_n_13_pp;
rom_lut_r_cen Ur4_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[13],sym_res_18_n[13],sym_res_17_n[13],sym_res_16_n[13] } ), .data_out( lut_val_4_n_13_pp[9:0]) ) ;
defparam Ur4_n_13_pp.DATA_WIDTH = 10;
defparam Ur4_n_13_pp.C0 = 10'd 0;
defparam Ur4_n_13_pp.C1 = 10'd 55;
defparam Ur4_n_13_pp.C2 = 10'd 9;
defparam Ur4_n_13_pp.C3 = 10'd 64;
defparam Ur4_n_13_pp.C4 = 10'd 877;
defparam Ur4_n_13_pp.C5 = 10'd 932;
defparam Ur4_n_13_pp.C6 = 10'd 886;
defparam Ur4_n_13_pp.C7 = 10'd 941;
defparam Ur4_n_13_pp.C8 = 10'd 743;
defparam Ur4_n_13_pp.C9 = 10'd 798;
defparam Ur4_n_13_pp.CA = 10'd 752;
defparam Ur4_n_13_pp.CB = 10'd 807;
defparam Ur4_n_13_pp.CC = 10'd 596;
defparam Ur4_n_13_pp.CD = 10'd 651;
defparam Ur4_n_13_pp.CE = 10'd 605;
defparam Ur4_n_13_pp.CF = 10'd 660;
assign lut_val_4_n_13_pp[13] = lut_val_4_n_13_pp[9];
assign lut_val_4_n_13_pp[12] = lut_val_4_n_13_pp[9];
assign lut_val_4_n_13_pp[11] = lut_val_4_n_13_pp[9];
assign lut_val_4_n_13_pp[10] = lut_val_4_n_13_pp[9];
wire [13:0] lut_val_4_n_14_pp;
rom_lut_r_cen Ur4_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[14],sym_res_18_n[14],sym_res_17_n[14],sym_res_16_n[14] } ), .data_out( lut_val_4_n_14_pp[9:0]) ) ;
defparam Ur4_n_14_pp.DATA_WIDTH = 10;
defparam Ur4_n_14_pp.C0 = 10'd 0;
defparam Ur4_n_14_pp.C1 = 10'd 55;
defparam Ur4_n_14_pp.C2 = 10'd 9;
defparam Ur4_n_14_pp.C3 = 10'd 64;
defparam Ur4_n_14_pp.C4 = 10'd 877;
defparam Ur4_n_14_pp.C5 = 10'd 932;
defparam Ur4_n_14_pp.C6 = 10'd 886;
defparam Ur4_n_14_pp.C7 = 10'd 941;
defparam Ur4_n_14_pp.C8 = 10'd 743;
defparam Ur4_n_14_pp.C9 = 10'd 798;
defparam Ur4_n_14_pp.CA = 10'd 752;
defparam Ur4_n_14_pp.CB = 10'd 807;
defparam Ur4_n_14_pp.CC = 10'd 596;
defparam Ur4_n_14_pp.CD = 10'd 651;
defparam Ur4_n_14_pp.CE = 10'd 605;
defparam Ur4_n_14_pp.CF = 10'd 660;
assign lut_val_4_n_14_pp[13] = lut_val_4_n_14_pp[9];
assign lut_val_4_n_14_pp[12] = lut_val_4_n_14_pp[9];
assign lut_val_4_n_14_pp[11] = lut_val_4_n_14_pp[9];
assign lut_val_4_n_14_pp[10] = lut_val_4_n_14_pp[9];
wire [13:0] lut_val_4_n_15_pp;
rom_lut_r_cen Ur4_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[15],sym_res_18_n[15],sym_res_17_n[15],sym_res_16_n[15] } ), .data_out( lut_val_4_n_15_pp[9:0]) ) ;
defparam Ur4_n_15_pp.DATA_WIDTH = 10;
defparam Ur4_n_15_pp.C0 = 10'd 0;
defparam Ur4_n_15_pp.C1 = 10'd 55;
defparam Ur4_n_15_pp.C2 = 10'd 9;
defparam Ur4_n_15_pp.C3 = 10'd 64;
defparam Ur4_n_15_pp.C4 = 10'd 877;
defparam Ur4_n_15_pp.C5 = 10'd 932;
defparam Ur4_n_15_pp.C6 = 10'd 886;
defparam Ur4_n_15_pp.C7 = 10'd 941;
defparam Ur4_n_15_pp.C8 = 10'd 743;
defparam Ur4_n_15_pp.C9 = 10'd 798;
defparam Ur4_n_15_pp.CA = 10'd 752;
defparam Ur4_n_15_pp.CB = 10'd 807;
defparam Ur4_n_15_pp.CC = 10'd 596;
defparam Ur4_n_15_pp.CD = 10'd 651;
defparam Ur4_n_15_pp.CE = 10'd 605;
defparam Ur4_n_15_pp.CF = 10'd 660;
assign lut_val_4_n_15_pp[13] = lut_val_4_n_15_pp[9];
assign lut_val_4_n_15_pp[12] = lut_val_4_n_15_pp[9];
assign lut_val_4_n_15_pp[11] = lut_val_4_n_15_pp[9];
assign lut_val_4_n_15_pp[10] = lut_val_4_n_15_pp[9];
wire [13:0] lut_val_5_n_0_pp;
rom_lut_r_cen Ur5_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[0],sym_res_22_n[0],sym_res_21_n[0],sym_res_20_n[0] } ), .data_out( lut_val_5_n_0_pp[9:0]) ) ;
defparam Ur5_n_0_pp.DATA_WIDTH = 10;
defparam Ur5_n_0_pp.C0 = 10'd 0;
defparam Ur5_n_0_pp.C1 = 10'd 782;
defparam Ur5_n_0_pp.C2 = 10'd 974;
defparam Ur5_n_0_pp.C3 = 10'd 732;
defparam Ur5_n_0_pp.C4 = 10'd 100;
defparam Ur5_n_0_pp.C5 = 10'd 882;
defparam Ur5_n_0_pp.C6 = 10'd 50;
defparam Ur5_n_0_pp.C7 = 10'd 832;
defparam Ur5_n_0_pp.C8 = 10'd 51;
defparam Ur5_n_0_pp.C9 = 10'd 833;
defparam Ur5_n_0_pp.CA = 10'd 1;
defparam Ur5_n_0_pp.CB = 10'd 783;
defparam Ur5_n_0_pp.CC = 10'd 151;
defparam Ur5_n_0_pp.CD = 10'd 933;
defparam Ur5_n_0_pp.CE = 10'd 101;
defparam Ur5_n_0_pp.CF = 10'd 883;
assign lut_val_5_n_0_pp[13] = lut_val_5_n_0_pp[9];
assign lut_val_5_n_0_pp[12] = lut_val_5_n_0_pp[9];
assign lut_val_5_n_0_pp[11] = lut_val_5_n_0_pp[9];
assign lut_val_5_n_0_pp[10] = lut_val_5_n_0_pp[9];
wire [13:0] lut_val_5_n_1_pp;
rom_lut_r_cen Ur5_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[1],sym_res_22_n[1],sym_res_21_n[1],sym_res_20_n[1] } ), .data_out( lut_val_5_n_1_pp[9:0]) ) ;
defparam Ur5_n_1_pp.DATA_WIDTH = 10;
defparam Ur5_n_1_pp.C0 = 10'd 0;
defparam Ur5_n_1_pp.C1 = 10'd 782;
defparam Ur5_n_1_pp.C2 = 10'd 974;
defparam Ur5_n_1_pp.C3 = 10'd 732;
defparam Ur5_n_1_pp.C4 = 10'd 100;
defparam Ur5_n_1_pp.C5 = 10'd 882;
defparam Ur5_n_1_pp.C6 = 10'd 50;
defparam Ur5_n_1_pp.C7 = 10'd 832;
defparam Ur5_n_1_pp.C8 = 10'd 51;
defparam Ur5_n_1_pp.C9 = 10'd 833;
defparam Ur5_n_1_pp.CA = 10'd 1;
defparam Ur5_n_1_pp.CB = 10'd 783;
defparam Ur5_n_1_pp.CC = 10'd 151;
defparam Ur5_n_1_pp.CD = 10'd 933;
defparam Ur5_n_1_pp.CE = 10'd 101;
defparam Ur5_n_1_pp.CF = 10'd 883;
assign lut_val_5_n_1_pp[13] = lut_val_5_n_1_pp[9];
assign lut_val_5_n_1_pp[12] = lut_val_5_n_1_pp[9];
assign lut_val_5_n_1_pp[11] = lut_val_5_n_1_pp[9];
assign lut_val_5_n_1_pp[10] = lut_val_5_n_1_pp[9];
wire [13:0] lut_val_5_n_2_pp;
rom_lut_r_cen Ur5_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[2],sym_res_22_n[2],sym_res_21_n[2],sym_res_20_n[2] } ), .data_out( lut_val_5_n_2_pp[9:0]) ) ;
defparam Ur5_n_2_pp.DATA_WIDTH = 10;
defparam Ur5_n_2_pp.C0 = 10'd 0;
defparam Ur5_n_2_pp.C1 = 10'd 782;
defparam Ur5_n_2_pp.C2 = 10'd 974;
defparam Ur5_n_2_pp.C3 = 10'd 732;
defparam Ur5_n_2_pp.C4 = 10'd 100;
defparam Ur5_n_2_pp.C5 = 10'd 882;
defparam Ur5_n_2_pp.C6 = 10'd 50;
defparam Ur5_n_2_pp.C7 = 10'd 832;
defparam Ur5_n_2_pp.C8 = 10'd 51;
defparam Ur5_n_2_pp.C9 = 10'd 833;
defparam Ur5_n_2_pp.CA = 10'd 1;
defparam Ur5_n_2_pp.CB = 10'd 783;
defparam Ur5_n_2_pp.CC = 10'd 151;
defparam Ur5_n_2_pp.CD = 10'd 933;
defparam Ur5_n_2_pp.CE = 10'd 101;
defparam Ur5_n_2_pp.CF = 10'd 883;
assign lut_val_5_n_2_pp[13] = lut_val_5_n_2_pp[9];
assign lut_val_5_n_2_pp[12] = lut_val_5_n_2_pp[9];
assign lut_val_5_n_2_pp[11] = lut_val_5_n_2_pp[9];
assign lut_val_5_n_2_pp[10] = lut_val_5_n_2_pp[9];
wire [13:0] lut_val_5_n_3_pp;
rom_lut_r_cen Ur5_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[3],sym_res_22_n[3],sym_res_21_n[3],sym_res_20_n[3] } ), .data_out( lut_val_5_n_3_pp[9:0]) ) ;
defparam Ur5_n_3_pp.DATA_WIDTH = 10;
defparam Ur5_n_3_pp.C0 = 10'd 0;
defparam Ur5_n_3_pp.C1 = 10'd 782;
defparam Ur5_n_3_pp.C2 = 10'd 974;
defparam Ur5_n_3_pp.C3 = 10'd 732;
defparam Ur5_n_3_pp.C4 = 10'd 100;
defparam Ur5_n_3_pp.C5 = 10'd 882;
defparam Ur5_n_3_pp.C6 = 10'd 50;
defparam Ur5_n_3_pp.C7 = 10'd 832;
defparam Ur5_n_3_pp.C8 = 10'd 51;
defparam Ur5_n_3_pp.C9 = 10'd 833;
defparam Ur5_n_3_pp.CA = 10'd 1;
defparam Ur5_n_3_pp.CB = 10'd 783;
defparam Ur5_n_3_pp.CC = 10'd 151;
defparam Ur5_n_3_pp.CD = 10'd 933;
defparam Ur5_n_3_pp.CE = 10'd 101;
defparam Ur5_n_3_pp.CF = 10'd 883;
assign lut_val_5_n_3_pp[13] = lut_val_5_n_3_pp[9];
assign lut_val_5_n_3_pp[12] = lut_val_5_n_3_pp[9];
assign lut_val_5_n_3_pp[11] = lut_val_5_n_3_pp[9];
assign lut_val_5_n_3_pp[10] = lut_val_5_n_3_pp[9];
wire [13:0] lut_val_5_n_4_pp;
rom_lut_r_cen Ur5_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[4],sym_res_22_n[4],sym_res_21_n[4],sym_res_20_n[4] } ), .data_out( lut_val_5_n_4_pp[9:0]) ) ;
defparam Ur5_n_4_pp.DATA_WIDTH = 10;
defparam Ur5_n_4_pp.C0 = 10'd 0;
defparam Ur5_n_4_pp.C1 = 10'd 782;
defparam Ur5_n_4_pp.C2 = 10'd 974;
defparam Ur5_n_4_pp.C3 = 10'd 732;
defparam Ur5_n_4_pp.C4 = 10'd 100;
defparam Ur5_n_4_pp.C5 = 10'd 882;
defparam Ur5_n_4_pp.C6 = 10'd 50;
defparam Ur5_n_4_pp.C7 = 10'd 832;
defparam Ur5_n_4_pp.C8 = 10'd 51;
defparam Ur5_n_4_pp.C9 = 10'd 833;
defparam Ur5_n_4_pp.CA = 10'd 1;
defparam Ur5_n_4_pp.CB = 10'd 783;
defparam Ur5_n_4_pp.CC = 10'd 151;
defparam Ur5_n_4_pp.CD = 10'd 933;
defparam Ur5_n_4_pp.CE = 10'd 101;
defparam Ur5_n_4_pp.CF = 10'd 883;
assign lut_val_5_n_4_pp[13] = lut_val_5_n_4_pp[9];
assign lut_val_5_n_4_pp[12] = lut_val_5_n_4_pp[9];
assign lut_val_5_n_4_pp[11] = lut_val_5_n_4_pp[9];
assign lut_val_5_n_4_pp[10] = lut_val_5_n_4_pp[9];
wire [13:0] lut_val_5_n_5_pp;
rom_lut_r_cen Ur5_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[5],sym_res_22_n[5],sym_res_21_n[5],sym_res_20_n[5] } ), .data_out( lut_val_5_n_5_pp[9:0]) ) ;
defparam Ur5_n_5_pp.DATA_WIDTH = 10;
defparam Ur5_n_5_pp.C0 = 10'd 0;
defparam Ur5_n_5_pp.C1 = 10'd 782;
defparam Ur5_n_5_pp.C2 = 10'd 974;
defparam Ur5_n_5_pp.C3 = 10'd 732;
defparam Ur5_n_5_pp.C4 = 10'd 100;
defparam Ur5_n_5_pp.C5 = 10'd 882;
defparam Ur5_n_5_pp.C6 = 10'd 50;
defparam Ur5_n_5_pp.C7 = 10'd 832;
defparam Ur5_n_5_pp.C8 = 10'd 51;
defparam Ur5_n_5_pp.C9 = 10'd 833;
defparam Ur5_n_5_pp.CA = 10'd 1;
defparam Ur5_n_5_pp.CB = 10'd 783;
defparam Ur5_n_5_pp.CC = 10'd 151;
defparam Ur5_n_5_pp.CD = 10'd 933;
defparam Ur5_n_5_pp.CE = 10'd 101;
defparam Ur5_n_5_pp.CF = 10'd 883;
assign lut_val_5_n_5_pp[13] = lut_val_5_n_5_pp[9];
assign lut_val_5_n_5_pp[12] = lut_val_5_n_5_pp[9];
assign lut_val_5_n_5_pp[11] = lut_val_5_n_5_pp[9];
assign lut_val_5_n_5_pp[10] = lut_val_5_n_5_pp[9];
wire [13:0] lut_val_5_n_6_pp;
rom_lut_r_cen Ur5_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[6],sym_res_22_n[6],sym_res_21_n[6],sym_res_20_n[6] } ), .data_out( lut_val_5_n_6_pp[9:0]) ) ;
defparam Ur5_n_6_pp.DATA_WIDTH = 10;
defparam Ur5_n_6_pp.C0 = 10'd 0;
defparam Ur5_n_6_pp.C1 = 10'd 782;
defparam Ur5_n_6_pp.C2 = 10'd 974;
defparam Ur5_n_6_pp.C3 = 10'd 732;
defparam Ur5_n_6_pp.C4 = 10'd 100;
defparam Ur5_n_6_pp.C5 = 10'd 882;
defparam Ur5_n_6_pp.C6 = 10'd 50;
defparam Ur5_n_6_pp.C7 = 10'd 832;
defparam Ur5_n_6_pp.C8 = 10'd 51;
defparam Ur5_n_6_pp.C9 = 10'd 833;
defparam Ur5_n_6_pp.CA = 10'd 1;
defparam Ur5_n_6_pp.CB = 10'd 783;
defparam Ur5_n_6_pp.CC = 10'd 151;
defparam Ur5_n_6_pp.CD = 10'd 933;
defparam Ur5_n_6_pp.CE = 10'd 101;
defparam Ur5_n_6_pp.CF = 10'd 883;
assign lut_val_5_n_6_pp[13] = lut_val_5_n_6_pp[9];
assign lut_val_5_n_6_pp[12] = lut_val_5_n_6_pp[9];
assign lut_val_5_n_6_pp[11] = lut_val_5_n_6_pp[9];
assign lut_val_5_n_6_pp[10] = lut_val_5_n_6_pp[9];
wire [13:0] lut_val_5_n_7_pp;
rom_lut_r_cen Ur5_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[7],sym_res_22_n[7],sym_res_21_n[7],sym_res_20_n[7] } ), .data_out( lut_val_5_n_7_pp[9:0]) ) ;
defparam Ur5_n_7_pp.DATA_WIDTH = 10;
defparam Ur5_n_7_pp.C0 = 10'd 0;
defparam Ur5_n_7_pp.C1 = 10'd 782;
defparam Ur5_n_7_pp.C2 = 10'd 974;
defparam Ur5_n_7_pp.C3 = 10'd 732;
defparam Ur5_n_7_pp.C4 = 10'd 100;
defparam Ur5_n_7_pp.C5 = 10'd 882;
defparam Ur5_n_7_pp.C6 = 10'd 50;
defparam Ur5_n_7_pp.C7 = 10'd 832;
defparam Ur5_n_7_pp.C8 = 10'd 51;
defparam Ur5_n_7_pp.C9 = 10'd 833;
defparam Ur5_n_7_pp.CA = 10'd 1;
defparam Ur5_n_7_pp.CB = 10'd 783;
defparam Ur5_n_7_pp.CC = 10'd 151;
defparam Ur5_n_7_pp.CD = 10'd 933;
defparam Ur5_n_7_pp.CE = 10'd 101;
defparam Ur5_n_7_pp.CF = 10'd 883;
assign lut_val_5_n_7_pp[13] = lut_val_5_n_7_pp[9];
assign lut_val_5_n_7_pp[12] = lut_val_5_n_7_pp[9];
assign lut_val_5_n_7_pp[11] = lut_val_5_n_7_pp[9];
assign lut_val_5_n_7_pp[10] = lut_val_5_n_7_pp[9];
wire [13:0] lut_val_5_n_8_pp;
rom_lut_r_cen Ur5_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[8],sym_res_22_n[8],sym_res_21_n[8],sym_res_20_n[8] } ), .data_out( lut_val_5_n_8_pp[9:0]) ) ;
defparam Ur5_n_8_pp.DATA_WIDTH = 10;
defparam Ur5_n_8_pp.C0 = 10'd 0;
defparam Ur5_n_8_pp.C1 = 10'd 782;
defparam Ur5_n_8_pp.C2 = 10'd 974;
defparam Ur5_n_8_pp.C3 = 10'd 732;
defparam Ur5_n_8_pp.C4 = 10'd 100;
defparam Ur5_n_8_pp.C5 = 10'd 882;
defparam Ur5_n_8_pp.C6 = 10'd 50;
defparam Ur5_n_8_pp.C7 = 10'd 832;
defparam Ur5_n_8_pp.C8 = 10'd 51;
defparam Ur5_n_8_pp.C9 = 10'd 833;
defparam Ur5_n_8_pp.CA = 10'd 1;
defparam Ur5_n_8_pp.CB = 10'd 783;
defparam Ur5_n_8_pp.CC = 10'd 151;
defparam Ur5_n_8_pp.CD = 10'd 933;
defparam Ur5_n_8_pp.CE = 10'd 101;
defparam Ur5_n_8_pp.CF = 10'd 883;
assign lut_val_5_n_8_pp[13] = lut_val_5_n_8_pp[9];
assign lut_val_5_n_8_pp[12] = lut_val_5_n_8_pp[9];
assign lut_val_5_n_8_pp[11] = lut_val_5_n_8_pp[9];
assign lut_val_5_n_8_pp[10] = lut_val_5_n_8_pp[9];
wire [13:0] lut_val_5_n_9_pp;
rom_lut_r_cen Ur5_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[9],sym_res_22_n[9],sym_res_21_n[9],sym_res_20_n[9] } ), .data_out( lut_val_5_n_9_pp[9:0]) ) ;
defparam Ur5_n_9_pp.DATA_WIDTH = 10;
defparam Ur5_n_9_pp.C0 = 10'd 0;
defparam Ur5_n_9_pp.C1 = 10'd 782;
defparam Ur5_n_9_pp.C2 = 10'd 974;
defparam Ur5_n_9_pp.C3 = 10'd 732;
defparam Ur5_n_9_pp.C4 = 10'd 100;
defparam Ur5_n_9_pp.C5 = 10'd 882;
defparam Ur5_n_9_pp.C6 = 10'd 50;
defparam Ur5_n_9_pp.C7 = 10'd 832;
defparam Ur5_n_9_pp.C8 = 10'd 51;
defparam Ur5_n_9_pp.C9 = 10'd 833;
defparam Ur5_n_9_pp.CA = 10'd 1;
defparam Ur5_n_9_pp.CB = 10'd 783;
defparam Ur5_n_9_pp.CC = 10'd 151;
defparam Ur5_n_9_pp.CD = 10'd 933;
defparam Ur5_n_9_pp.CE = 10'd 101;
defparam Ur5_n_9_pp.CF = 10'd 883;
assign lut_val_5_n_9_pp[13] = lut_val_5_n_9_pp[9];
assign lut_val_5_n_9_pp[12] = lut_val_5_n_9_pp[9];
assign lut_val_5_n_9_pp[11] = lut_val_5_n_9_pp[9];
assign lut_val_5_n_9_pp[10] = lut_val_5_n_9_pp[9];
wire [13:0] lut_val_5_n_10_pp;
rom_lut_r_cen Ur5_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[10],sym_res_22_n[10],sym_res_21_n[10],sym_res_20_n[10] } ), .data_out( lut_val_5_n_10_pp[9:0]) ) ;
defparam Ur5_n_10_pp.DATA_WIDTH = 10;
defparam Ur5_n_10_pp.C0 = 10'd 0;
defparam Ur5_n_10_pp.C1 = 10'd 782;
defparam Ur5_n_10_pp.C2 = 10'd 974;
defparam Ur5_n_10_pp.C3 = 10'd 732;
defparam Ur5_n_10_pp.C4 = 10'd 100;
defparam Ur5_n_10_pp.C5 = 10'd 882;
defparam Ur5_n_10_pp.C6 = 10'd 50;
defparam Ur5_n_10_pp.C7 = 10'd 832;
defparam Ur5_n_10_pp.C8 = 10'd 51;
defparam Ur5_n_10_pp.C9 = 10'd 833;
defparam Ur5_n_10_pp.CA = 10'd 1;
defparam Ur5_n_10_pp.CB = 10'd 783;
defparam Ur5_n_10_pp.CC = 10'd 151;
defparam Ur5_n_10_pp.CD = 10'd 933;
defparam Ur5_n_10_pp.CE = 10'd 101;
defparam Ur5_n_10_pp.CF = 10'd 883;
assign lut_val_5_n_10_pp[13] = lut_val_5_n_10_pp[9];
assign lut_val_5_n_10_pp[12] = lut_val_5_n_10_pp[9];
assign lut_val_5_n_10_pp[11] = lut_val_5_n_10_pp[9];
assign lut_val_5_n_10_pp[10] = lut_val_5_n_10_pp[9];
wire [13:0] lut_val_5_n_11_pp;
rom_lut_r_cen Ur5_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[11],sym_res_22_n[11],sym_res_21_n[11],sym_res_20_n[11] } ), .data_out( lut_val_5_n_11_pp[9:0]) ) ;
defparam Ur5_n_11_pp.DATA_WIDTH = 10;
defparam Ur5_n_11_pp.C0 = 10'd 0;
defparam Ur5_n_11_pp.C1 = 10'd 782;
defparam Ur5_n_11_pp.C2 = 10'd 974;
defparam Ur5_n_11_pp.C3 = 10'd 732;
defparam Ur5_n_11_pp.C4 = 10'd 100;
defparam Ur5_n_11_pp.C5 = 10'd 882;
defparam Ur5_n_11_pp.C6 = 10'd 50;
defparam Ur5_n_11_pp.C7 = 10'd 832;
defparam Ur5_n_11_pp.C8 = 10'd 51;
defparam Ur5_n_11_pp.C9 = 10'd 833;
defparam Ur5_n_11_pp.CA = 10'd 1;
defparam Ur5_n_11_pp.CB = 10'd 783;
defparam Ur5_n_11_pp.CC = 10'd 151;
defparam Ur5_n_11_pp.CD = 10'd 933;
defparam Ur5_n_11_pp.CE = 10'd 101;
defparam Ur5_n_11_pp.CF = 10'd 883;
assign lut_val_5_n_11_pp[13] = lut_val_5_n_11_pp[9];
assign lut_val_5_n_11_pp[12] = lut_val_5_n_11_pp[9];
assign lut_val_5_n_11_pp[11] = lut_val_5_n_11_pp[9];
assign lut_val_5_n_11_pp[10] = lut_val_5_n_11_pp[9];
wire [13:0] lut_val_5_n_12_pp;
rom_lut_r_cen Ur5_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[12],sym_res_22_n[12],sym_res_21_n[12],sym_res_20_n[12] } ), .data_out( lut_val_5_n_12_pp[9:0]) ) ;
defparam Ur5_n_12_pp.DATA_WIDTH = 10;
defparam Ur5_n_12_pp.C0 = 10'd 0;
defparam Ur5_n_12_pp.C1 = 10'd 782;
defparam Ur5_n_12_pp.C2 = 10'd 974;
defparam Ur5_n_12_pp.C3 = 10'd 732;
defparam Ur5_n_12_pp.C4 = 10'd 100;
defparam Ur5_n_12_pp.C5 = 10'd 882;
defparam Ur5_n_12_pp.C6 = 10'd 50;
defparam Ur5_n_12_pp.C7 = 10'd 832;
defparam Ur5_n_12_pp.C8 = 10'd 51;
defparam Ur5_n_12_pp.C9 = 10'd 833;
defparam Ur5_n_12_pp.CA = 10'd 1;
defparam Ur5_n_12_pp.CB = 10'd 783;
defparam Ur5_n_12_pp.CC = 10'd 151;
defparam Ur5_n_12_pp.CD = 10'd 933;
defparam Ur5_n_12_pp.CE = 10'd 101;
defparam Ur5_n_12_pp.CF = 10'd 883;
assign lut_val_5_n_12_pp[13] = lut_val_5_n_12_pp[9];
assign lut_val_5_n_12_pp[12] = lut_val_5_n_12_pp[9];
assign lut_val_5_n_12_pp[11] = lut_val_5_n_12_pp[9];
assign lut_val_5_n_12_pp[10] = lut_val_5_n_12_pp[9];
wire [13:0] lut_val_5_n_13_pp;
rom_lut_r_cen Ur5_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[13],sym_res_22_n[13],sym_res_21_n[13],sym_res_20_n[13] } ), .data_out( lut_val_5_n_13_pp[9:0]) ) ;
defparam Ur5_n_13_pp.DATA_WIDTH = 10;
defparam Ur5_n_13_pp.C0 = 10'd 0;
defparam Ur5_n_13_pp.C1 = 10'd 782;
defparam Ur5_n_13_pp.C2 = 10'd 974;
defparam Ur5_n_13_pp.C3 = 10'd 732;
defparam Ur5_n_13_pp.C4 = 10'd 100;
defparam Ur5_n_13_pp.C5 = 10'd 882;
defparam Ur5_n_13_pp.C6 = 10'd 50;
defparam Ur5_n_13_pp.C7 = 10'd 832;
defparam Ur5_n_13_pp.C8 = 10'd 51;
defparam Ur5_n_13_pp.C9 = 10'd 833;
defparam Ur5_n_13_pp.CA = 10'd 1;
defparam Ur5_n_13_pp.CB = 10'd 783;
defparam Ur5_n_13_pp.CC = 10'd 151;
defparam Ur5_n_13_pp.CD = 10'd 933;
defparam Ur5_n_13_pp.CE = 10'd 101;
defparam Ur5_n_13_pp.CF = 10'd 883;
assign lut_val_5_n_13_pp[13] = lut_val_5_n_13_pp[9];
assign lut_val_5_n_13_pp[12] = lut_val_5_n_13_pp[9];
assign lut_val_5_n_13_pp[11] = lut_val_5_n_13_pp[9];
assign lut_val_5_n_13_pp[10] = lut_val_5_n_13_pp[9];
wire [13:0] lut_val_5_n_14_pp;
rom_lut_r_cen Ur5_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[14],sym_res_22_n[14],sym_res_21_n[14],sym_res_20_n[14] } ), .data_out( lut_val_5_n_14_pp[9:0]) ) ;
defparam Ur5_n_14_pp.DATA_WIDTH = 10;
defparam Ur5_n_14_pp.C0 = 10'd 0;
defparam Ur5_n_14_pp.C1 = 10'd 782;
defparam Ur5_n_14_pp.C2 = 10'd 974;
defparam Ur5_n_14_pp.C3 = 10'd 732;
defparam Ur5_n_14_pp.C4 = 10'd 100;
defparam Ur5_n_14_pp.C5 = 10'd 882;
defparam Ur5_n_14_pp.C6 = 10'd 50;
defparam Ur5_n_14_pp.C7 = 10'd 832;
defparam Ur5_n_14_pp.C8 = 10'd 51;
defparam Ur5_n_14_pp.C9 = 10'd 833;
defparam Ur5_n_14_pp.CA = 10'd 1;
defparam Ur5_n_14_pp.CB = 10'd 783;
defparam Ur5_n_14_pp.CC = 10'd 151;
defparam Ur5_n_14_pp.CD = 10'd 933;
defparam Ur5_n_14_pp.CE = 10'd 101;
defparam Ur5_n_14_pp.CF = 10'd 883;
assign lut_val_5_n_14_pp[13] = lut_val_5_n_14_pp[9];
assign lut_val_5_n_14_pp[12] = lut_val_5_n_14_pp[9];
assign lut_val_5_n_14_pp[11] = lut_val_5_n_14_pp[9];
assign lut_val_5_n_14_pp[10] = lut_val_5_n_14_pp[9];
wire [13:0] lut_val_5_n_15_pp;
rom_lut_r_cen Ur5_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[15],sym_res_22_n[15],sym_res_21_n[15],sym_res_20_n[15] } ), .data_out( lut_val_5_n_15_pp[9:0]) ) ;
defparam Ur5_n_15_pp.DATA_WIDTH = 10;
defparam Ur5_n_15_pp.C0 = 10'd 0;
defparam Ur5_n_15_pp.C1 = 10'd 782;
defparam Ur5_n_15_pp.C2 = 10'd 974;
defparam Ur5_n_15_pp.C3 = 10'd 732;
defparam Ur5_n_15_pp.C4 = 10'd 100;
defparam Ur5_n_15_pp.C5 = 10'd 882;
defparam Ur5_n_15_pp.C6 = 10'd 50;
defparam Ur5_n_15_pp.C7 = 10'd 832;
defparam Ur5_n_15_pp.C8 = 10'd 51;
defparam Ur5_n_15_pp.C9 = 10'd 833;
defparam Ur5_n_15_pp.CA = 10'd 1;
defparam Ur5_n_15_pp.CB = 10'd 783;
defparam Ur5_n_15_pp.CC = 10'd 151;
defparam Ur5_n_15_pp.CD = 10'd 933;
defparam Ur5_n_15_pp.CE = 10'd 101;
defparam Ur5_n_15_pp.CF = 10'd 883;
assign lut_val_5_n_15_pp[13] = lut_val_5_n_15_pp[9];
assign lut_val_5_n_15_pp[12] = lut_val_5_n_15_pp[9];
assign lut_val_5_n_15_pp[11] = lut_val_5_n_15_pp[9];
assign lut_val_5_n_15_pp[10] = lut_val_5_n_15_pp[9];
wire [13:0] lut_val_6_n_0_pp;
rom_lut_r_cen Ur6_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[0],sym_res_26_n[0],sym_res_25_n[0],sym_res_24_n[0] } ), .data_out( lut_val_6_n_0_pp[10:0]) ) ;
defparam Ur6_n_0_pp.DATA_WIDTH = 11;
defparam Ur6_n_0_pp.C0 = 11'd 0;
defparam Ur6_n_0_pp.C1 = 11'd 1941;
defparam Ur6_n_0_pp.C2 = 11'd 1951;
defparam Ur6_n_0_pp.C3 = 11'd 1844;
defparam Ur6_n_0_pp.C4 = 11'd 216;
defparam Ur6_n_0_pp.C5 = 11'd 109;
defparam Ur6_n_0_pp.C6 = 11'd 119;
defparam Ur6_n_0_pp.C7 = 11'd 12;
defparam Ur6_n_0_pp.C8 = 11'd 612;
defparam Ur6_n_0_pp.C9 = 11'd 505;
defparam Ur6_n_0_pp.CA = 11'd 515;
defparam Ur6_n_0_pp.CB = 11'd 408;
defparam Ur6_n_0_pp.CC = 11'd 828;
defparam Ur6_n_0_pp.CD = 11'd 721;
defparam Ur6_n_0_pp.CE = 11'd 731;
defparam Ur6_n_0_pp.CF = 11'd 624;
assign lut_val_6_n_0_pp[13] = lut_val_6_n_0_pp[10];
assign lut_val_6_n_0_pp[12] = lut_val_6_n_0_pp[10];
assign lut_val_6_n_0_pp[11] = lut_val_6_n_0_pp[10];
wire [13:0] lut_val_6_n_1_pp;
rom_lut_r_cen Ur6_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[1],sym_res_26_n[1],sym_res_25_n[1],sym_res_24_n[1] } ), .data_out( lut_val_6_n_1_pp[10:0]) ) ;
defparam Ur6_n_1_pp.DATA_WIDTH = 11;
defparam Ur6_n_1_pp.C0 = 11'd 0;
defparam Ur6_n_1_pp.C1 = 11'd 1941;
defparam Ur6_n_1_pp.C2 = 11'd 1951;
defparam Ur6_n_1_pp.C3 = 11'd 1844;
defparam Ur6_n_1_pp.C4 = 11'd 216;
defparam Ur6_n_1_pp.C5 = 11'd 109;
defparam Ur6_n_1_pp.C6 = 11'd 119;
defparam Ur6_n_1_pp.C7 = 11'd 12;
defparam Ur6_n_1_pp.C8 = 11'd 612;
defparam Ur6_n_1_pp.C9 = 11'd 505;
defparam Ur6_n_1_pp.CA = 11'd 515;
defparam Ur6_n_1_pp.CB = 11'd 408;
defparam Ur6_n_1_pp.CC = 11'd 828;
defparam Ur6_n_1_pp.CD = 11'd 721;
defparam Ur6_n_1_pp.CE = 11'd 731;
defparam Ur6_n_1_pp.CF = 11'd 624;
assign lut_val_6_n_1_pp[13] = lut_val_6_n_1_pp[10];
assign lut_val_6_n_1_pp[12] = lut_val_6_n_1_pp[10];
assign lut_val_6_n_1_pp[11] = lut_val_6_n_1_pp[10];
wire [13:0] lut_val_6_n_2_pp;
rom_lut_r_cen Ur6_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[2],sym_res_26_n[2],sym_res_25_n[2],sym_res_24_n[2] } ), .data_out( lut_val_6_n_2_pp[10:0]) ) ;
defparam Ur6_n_2_pp.DATA_WIDTH = 11;
defparam Ur6_n_2_pp.C0 = 11'd 0;
defparam Ur6_n_2_pp.C1 = 11'd 1941;
defparam Ur6_n_2_pp.C2 = 11'd 1951;
defparam Ur6_n_2_pp.C3 = 11'd 1844;
defparam Ur6_n_2_pp.C4 = 11'd 216;
defparam Ur6_n_2_pp.C5 = 11'd 109;
defparam Ur6_n_2_pp.C6 = 11'd 119;
defparam Ur6_n_2_pp.C7 = 11'd 12;
defparam Ur6_n_2_pp.C8 = 11'd 612;
defparam Ur6_n_2_pp.C9 = 11'd 505;
defparam Ur6_n_2_pp.CA = 11'd 515;
defparam Ur6_n_2_pp.CB = 11'd 408;
defparam Ur6_n_2_pp.CC = 11'd 828;
defparam Ur6_n_2_pp.CD = 11'd 721;
defparam Ur6_n_2_pp.CE = 11'd 731;
defparam Ur6_n_2_pp.CF = 11'd 624;
assign lut_val_6_n_2_pp[13] = lut_val_6_n_2_pp[10];
assign lut_val_6_n_2_pp[12] = lut_val_6_n_2_pp[10];
assign lut_val_6_n_2_pp[11] = lut_val_6_n_2_pp[10];
wire [13:0] lut_val_6_n_3_pp;
rom_lut_r_cen Ur6_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[3],sym_res_26_n[3],sym_res_25_n[3],sym_res_24_n[3] } ), .data_out( lut_val_6_n_3_pp[10:0]) ) ;
defparam Ur6_n_3_pp.DATA_WIDTH = 11;
defparam Ur6_n_3_pp.C0 = 11'd 0;
defparam Ur6_n_3_pp.C1 = 11'd 1941;
defparam Ur6_n_3_pp.C2 = 11'd 1951;
defparam Ur6_n_3_pp.C3 = 11'd 1844;
defparam Ur6_n_3_pp.C4 = 11'd 216;
defparam Ur6_n_3_pp.C5 = 11'd 109;
defparam Ur6_n_3_pp.C6 = 11'd 119;
defparam Ur6_n_3_pp.C7 = 11'd 12;
defparam Ur6_n_3_pp.C8 = 11'd 612;
defparam Ur6_n_3_pp.C9 = 11'd 505;
defparam Ur6_n_3_pp.CA = 11'd 515;
defparam Ur6_n_3_pp.CB = 11'd 408;
defparam Ur6_n_3_pp.CC = 11'd 828;
defparam Ur6_n_3_pp.CD = 11'd 721;
defparam Ur6_n_3_pp.CE = 11'd 731;
defparam Ur6_n_3_pp.CF = 11'd 624;
assign lut_val_6_n_3_pp[13] = lut_val_6_n_3_pp[10];
assign lut_val_6_n_3_pp[12] = lut_val_6_n_3_pp[10];
assign lut_val_6_n_3_pp[11] = lut_val_6_n_3_pp[10];
wire [13:0] lut_val_6_n_4_pp;
rom_lut_r_cen Ur6_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[4],sym_res_26_n[4],sym_res_25_n[4],sym_res_24_n[4] } ), .data_out( lut_val_6_n_4_pp[10:0]) ) ;
defparam Ur6_n_4_pp.DATA_WIDTH = 11;
defparam Ur6_n_4_pp.C0 = 11'd 0;
defparam Ur6_n_4_pp.C1 = 11'd 1941;
defparam Ur6_n_4_pp.C2 = 11'd 1951;
defparam Ur6_n_4_pp.C3 = 11'd 1844;
defparam Ur6_n_4_pp.C4 = 11'd 216;
defparam Ur6_n_4_pp.C5 = 11'd 109;
defparam Ur6_n_4_pp.C6 = 11'd 119;
defparam Ur6_n_4_pp.C7 = 11'd 12;
defparam Ur6_n_4_pp.C8 = 11'd 612;
defparam Ur6_n_4_pp.C9 = 11'd 505;
defparam Ur6_n_4_pp.CA = 11'd 515;
defparam Ur6_n_4_pp.CB = 11'd 408;
defparam Ur6_n_4_pp.CC = 11'd 828;
defparam Ur6_n_4_pp.CD = 11'd 721;
defparam Ur6_n_4_pp.CE = 11'd 731;
defparam Ur6_n_4_pp.CF = 11'd 624;
assign lut_val_6_n_4_pp[13] = lut_val_6_n_4_pp[10];
assign lut_val_6_n_4_pp[12] = lut_val_6_n_4_pp[10];
assign lut_val_6_n_4_pp[11] = lut_val_6_n_4_pp[10];
wire [13:0] lut_val_6_n_5_pp;
rom_lut_r_cen Ur6_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[5],sym_res_26_n[5],sym_res_25_n[5],sym_res_24_n[5] } ), .data_out( lut_val_6_n_5_pp[10:0]) ) ;
defparam Ur6_n_5_pp.DATA_WIDTH = 11;
defparam Ur6_n_5_pp.C0 = 11'd 0;
defparam Ur6_n_5_pp.C1 = 11'd 1941;
defparam Ur6_n_5_pp.C2 = 11'd 1951;
defparam Ur6_n_5_pp.C3 = 11'd 1844;
defparam Ur6_n_5_pp.C4 = 11'd 216;
defparam Ur6_n_5_pp.C5 = 11'd 109;
defparam Ur6_n_5_pp.C6 = 11'd 119;
defparam Ur6_n_5_pp.C7 = 11'd 12;
defparam Ur6_n_5_pp.C8 = 11'd 612;
defparam Ur6_n_5_pp.C9 = 11'd 505;
defparam Ur6_n_5_pp.CA = 11'd 515;
defparam Ur6_n_5_pp.CB = 11'd 408;
defparam Ur6_n_5_pp.CC = 11'd 828;
defparam Ur6_n_5_pp.CD = 11'd 721;
defparam Ur6_n_5_pp.CE = 11'd 731;
defparam Ur6_n_5_pp.CF = 11'd 624;
assign lut_val_6_n_5_pp[13] = lut_val_6_n_5_pp[10];
assign lut_val_6_n_5_pp[12] = lut_val_6_n_5_pp[10];
assign lut_val_6_n_5_pp[11] = lut_val_6_n_5_pp[10];
wire [13:0] lut_val_6_n_6_pp;
rom_lut_r_cen Ur6_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[6],sym_res_26_n[6],sym_res_25_n[6],sym_res_24_n[6] } ), .data_out( lut_val_6_n_6_pp[10:0]) ) ;
defparam Ur6_n_6_pp.DATA_WIDTH = 11;
defparam Ur6_n_6_pp.C0 = 11'd 0;
defparam Ur6_n_6_pp.C1 = 11'd 1941;
defparam Ur6_n_6_pp.C2 = 11'd 1951;
defparam Ur6_n_6_pp.C3 = 11'd 1844;
defparam Ur6_n_6_pp.C4 = 11'd 216;
defparam Ur6_n_6_pp.C5 = 11'd 109;
defparam Ur6_n_6_pp.C6 = 11'd 119;
defparam Ur6_n_6_pp.C7 = 11'd 12;
defparam Ur6_n_6_pp.C8 = 11'd 612;
defparam Ur6_n_6_pp.C9 = 11'd 505;
defparam Ur6_n_6_pp.CA = 11'd 515;
defparam Ur6_n_6_pp.CB = 11'd 408;
defparam Ur6_n_6_pp.CC = 11'd 828;
defparam Ur6_n_6_pp.CD = 11'd 721;
defparam Ur6_n_6_pp.CE = 11'd 731;
defparam Ur6_n_6_pp.CF = 11'd 624;
assign lut_val_6_n_6_pp[13] = lut_val_6_n_6_pp[10];
assign lut_val_6_n_6_pp[12] = lut_val_6_n_6_pp[10];
assign lut_val_6_n_6_pp[11] = lut_val_6_n_6_pp[10];
wire [13:0] lut_val_6_n_7_pp;
rom_lut_r_cen Ur6_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[7],sym_res_26_n[7],sym_res_25_n[7],sym_res_24_n[7] } ), .data_out( lut_val_6_n_7_pp[10:0]) ) ;
defparam Ur6_n_7_pp.DATA_WIDTH = 11;
defparam Ur6_n_7_pp.C0 = 11'd 0;
defparam Ur6_n_7_pp.C1 = 11'd 1941;
defparam Ur6_n_7_pp.C2 = 11'd 1951;
defparam Ur6_n_7_pp.C3 = 11'd 1844;
defparam Ur6_n_7_pp.C4 = 11'd 216;
defparam Ur6_n_7_pp.C5 = 11'd 109;
defparam Ur6_n_7_pp.C6 = 11'd 119;
defparam Ur6_n_7_pp.C7 = 11'd 12;
defparam Ur6_n_7_pp.C8 = 11'd 612;
defparam Ur6_n_7_pp.C9 = 11'd 505;
defparam Ur6_n_7_pp.CA = 11'd 515;
defparam Ur6_n_7_pp.CB = 11'd 408;
defparam Ur6_n_7_pp.CC = 11'd 828;
defparam Ur6_n_7_pp.CD = 11'd 721;
defparam Ur6_n_7_pp.CE = 11'd 731;
defparam Ur6_n_7_pp.CF = 11'd 624;
assign lut_val_6_n_7_pp[13] = lut_val_6_n_7_pp[10];
assign lut_val_6_n_7_pp[12] = lut_val_6_n_7_pp[10];
assign lut_val_6_n_7_pp[11] = lut_val_6_n_7_pp[10];
wire [13:0] lut_val_6_n_8_pp;
rom_lut_r_cen Ur6_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[8],sym_res_26_n[8],sym_res_25_n[8],sym_res_24_n[8] } ), .data_out( lut_val_6_n_8_pp[10:0]) ) ;
defparam Ur6_n_8_pp.DATA_WIDTH = 11;
defparam Ur6_n_8_pp.C0 = 11'd 0;
defparam Ur6_n_8_pp.C1 = 11'd 1941;
defparam Ur6_n_8_pp.C2 = 11'd 1951;
defparam Ur6_n_8_pp.C3 = 11'd 1844;
defparam Ur6_n_8_pp.C4 = 11'd 216;
defparam Ur6_n_8_pp.C5 = 11'd 109;
defparam Ur6_n_8_pp.C6 = 11'd 119;
defparam Ur6_n_8_pp.C7 = 11'd 12;
defparam Ur6_n_8_pp.C8 = 11'd 612;
defparam Ur6_n_8_pp.C9 = 11'd 505;
defparam Ur6_n_8_pp.CA = 11'd 515;
defparam Ur6_n_8_pp.CB = 11'd 408;
defparam Ur6_n_8_pp.CC = 11'd 828;
defparam Ur6_n_8_pp.CD = 11'd 721;
defparam Ur6_n_8_pp.CE = 11'd 731;
defparam Ur6_n_8_pp.CF = 11'd 624;
assign lut_val_6_n_8_pp[13] = lut_val_6_n_8_pp[10];
assign lut_val_6_n_8_pp[12] = lut_val_6_n_8_pp[10];
assign lut_val_6_n_8_pp[11] = lut_val_6_n_8_pp[10];
wire [13:0] lut_val_6_n_9_pp;
rom_lut_r_cen Ur6_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[9],sym_res_26_n[9],sym_res_25_n[9],sym_res_24_n[9] } ), .data_out( lut_val_6_n_9_pp[10:0]) ) ;
defparam Ur6_n_9_pp.DATA_WIDTH = 11;
defparam Ur6_n_9_pp.C0 = 11'd 0;
defparam Ur6_n_9_pp.C1 = 11'd 1941;
defparam Ur6_n_9_pp.C2 = 11'd 1951;
defparam Ur6_n_9_pp.C3 = 11'd 1844;
defparam Ur6_n_9_pp.C4 = 11'd 216;
defparam Ur6_n_9_pp.C5 = 11'd 109;
defparam Ur6_n_9_pp.C6 = 11'd 119;
defparam Ur6_n_9_pp.C7 = 11'd 12;
defparam Ur6_n_9_pp.C8 = 11'd 612;
defparam Ur6_n_9_pp.C9 = 11'd 505;
defparam Ur6_n_9_pp.CA = 11'd 515;
defparam Ur6_n_9_pp.CB = 11'd 408;
defparam Ur6_n_9_pp.CC = 11'd 828;
defparam Ur6_n_9_pp.CD = 11'd 721;
defparam Ur6_n_9_pp.CE = 11'd 731;
defparam Ur6_n_9_pp.CF = 11'd 624;
assign lut_val_6_n_9_pp[13] = lut_val_6_n_9_pp[10];
assign lut_val_6_n_9_pp[12] = lut_val_6_n_9_pp[10];
assign lut_val_6_n_9_pp[11] = lut_val_6_n_9_pp[10];
wire [13:0] lut_val_6_n_10_pp;
rom_lut_r_cen Ur6_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[10],sym_res_26_n[10],sym_res_25_n[10],sym_res_24_n[10] } ), .data_out( lut_val_6_n_10_pp[10:0]) ) ;
defparam Ur6_n_10_pp.DATA_WIDTH = 11;
defparam Ur6_n_10_pp.C0 = 11'd 0;
defparam Ur6_n_10_pp.C1 = 11'd 1941;
defparam Ur6_n_10_pp.C2 = 11'd 1951;
defparam Ur6_n_10_pp.C3 = 11'd 1844;
defparam Ur6_n_10_pp.C4 = 11'd 216;
defparam Ur6_n_10_pp.C5 = 11'd 109;
defparam Ur6_n_10_pp.C6 = 11'd 119;
defparam Ur6_n_10_pp.C7 = 11'd 12;
defparam Ur6_n_10_pp.C8 = 11'd 612;
defparam Ur6_n_10_pp.C9 = 11'd 505;
defparam Ur6_n_10_pp.CA = 11'd 515;
defparam Ur6_n_10_pp.CB = 11'd 408;
defparam Ur6_n_10_pp.CC = 11'd 828;
defparam Ur6_n_10_pp.CD = 11'd 721;
defparam Ur6_n_10_pp.CE = 11'd 731;
defparam Ur6_n_10_pp.CF = 11'd 624;
assign lut_val_6_n_10_pp[13] = lut_val_6_n_10_pp[10];
assign lut_val_6_n_10_pp[12] = lut_val_6_n_10_pp[10];
assign lut_val_6_n_10_pp[11] = lut_val_6_n_10_pp[10];
wire [13:0] lut_val_6_n_11_pp;
rom_lut_r_cen Ur6_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[11],sym_res_26_n[11],sym_res_25_n[11],sym_res_24_n[11] } ), .data_out( lut_val_6_n_11_pp[10:0]) ) ;
defparam Ur6_n_11_pp.DATA_WIDTH = 11;
defparam Ur6_n_11_pp.C0 = 11'd 0;
defparam Ur6_n_11_pp.C1 = 11'd 1941;
defparam Ur6_n_11_pp.C2 = 11'd 1951;
defparam Ur6_n_11_pp.C3 = 11'd 1844;
defparam Ur6_n_11_pp.C4 = 11'd 216;
defparam Ur6_n_11_pp.C5 = 11'd 109;
defparam Ur6_n_11_pp.C6 = 11'd 119;
defparam Ur6_n_11_pp.C7 = 11'd 12;
defparam Ur6_n_11_pp.C8 = 11'd 612;
defparam Ur6_n_11_pp.C9 = 11'd 505;
defparam Ur6_n_11_pp.CA = 11'd 515;
defparam Ur6_n_11_pp.CB = 11'd 408;
defparam Ur6_n_11_pp.CC = 11'd 828;
defparam Ur6_n_11_pp.CD = 11'd 721;
defparam Ur6_n_11_pp.CE = 11'd 731;
defparam Ur6_n_11_pp.CF = 11'd 624;
assign lut_val_6_n_11_pp[13] = lut_val_6_n_11_pp[10];
assign lut_val_6_n_11_pp[12] = lut_val_6_n_11_pp[10];
assign lut_val_6_n_11_pp[11] = lut_val_6_n_11_pp[10];
wire [13:0] lut_val_6_n_12_pp;
rom_lut_r_cen Ur6_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[12],sym_res_26_n[12],sym_res_25_n[12],sym_res_24_n[12] } ), .data_out( lut_val_6_n_12_pp[10:0]) ) ;
defparam Ur6_n_12_pp.DATA_WIDTH = 11;
defparam Ur6_n_12_pp.C0 = 11'd 0;
defparam Ur6_n_12_pp.C1 = 11'd 1941;
defparam Ur6_n_12_pp.C2 = 11'd 1951;
defparam Ur6_n_12_pp.C3 = 11'd 1844;
defparam Ur6_n_12_pp.C4 = 11'd 216;
defparam Ur6_n_12_pp.C5 = 11'd 109;
defparam Ur6_n_12_pp.C6 = 11'd 119;
defparam Ur6_n_12_pp.C7 = 11'd 12;
defparam Ur6_n_12_pp.C8 = 11'd 612;
defparam Ur6_n_12_pp.C9 = 11'd 505;
defparam Ur6_n_12_pp.CA = 11'd 515;
defparam Ur6_n_12_pp.CB = 11'd 408;
defparam Ur6_n_12_pp.CC = 11'd 828;
defparam Ur6_n_12_pp.CD = 11'd 721;
defparam Ur6_n_12_pp.CE = 11'd 731;
defparam Ur6_n_12_pp.CF = 11'd 624;
assign lut_val_6_n_12_pp[13] = lut_val_6_n_12_pp[10];
assign lut_val_6_n_12_pp[12] = lut_val_6_n_12_pp[10];
assign lut_val_6_n_12_pp[11] = lut_val_6_n_12_pp[10];
wire [13:0] lut_val_6_n_13_pp;
rom_lut_r_cen Ur6_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[13],sym_res_26_n[13],sym_res_25_n[13],sym_res_24_n[13] } ), .data_out( lut_val_6_n_13_pp[10:0]) ) ;
defparam Ur6_n_13_pp.DATA_WIDTH = 11;
defparam Ur6_n_13_pp.C0 = 11'd 0;
defparam Ur6_n_13_pp.C1 = 11'd 1941;
defparam Ur6_n_13_pp.C2 = 11'd 1951;
defparam Ur6_n_13_pp.C3 = 11'd 1844;
defparam Ur6_n_13_pp.C4 = 11'd 216;
defparam Ur6_n_13_pp.C5 = 11'd 109;
defparam Ur6_n_13_pp.C6 = 11'd 119;
defparam Ur6_n_13_pp.C7 = 11'd 12;
defparam Ur6_n_13_pp.C8 = 11'd 612;
defparam Ur6_n_13_pp.C9 = 11'd 505;
defparam Ur6_n_13_pp.CA = 11'd 515;
defparam Ur6_n_13_pp.CB = 11'd 408;
defparam Ur6_n_13_pp.CC = 11'd 828;
defparam Ur6_n_13_pp.CD = 11'd 721;
defparam Ur6_n_13_pp.CE = 11'd 731;
defparam Ur6_n_13_pp.CF = 11'd 624;
assign lut_val_6_n_13_pp[13] = lut_val_6_n_13_pp[10];
assign lut_val_6_n_13_pp[12] = lut_val_6_n_13_pp[10];
assign lut_val_6_n_13_pp[11] = lut_val_6_n_13_pp[10];
wire [13:0] lut_val_6_n_14_pp;
rom_lut_r_cen Ur6_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[14],sym_res_26_n[14],sym_res_25_n[14],sym_res_24_n[14] } ), .data_out( lut_val_6_n_14_pp[10:0]) ) ;
defparam Ur6_n_14_pp.DATA_WIDTH = 11;
defparam Ur6_n_14_pp.C0 = 11'd 0;
defparam Ur6_n_14_pp.C1 = 11'd 1941;
defparam Ur6_n_14_pp.C2 = 11'd 1951;
defparam Ur6_n_14_pp.C3 = 11'd 1844;
defparam Ur6_n_14_pp.C4 = 11'd 216;
defparam Ur6_n_14_pp.C5 = 11'd 109;
defparam Ur6_n_14_pp.C6 = 11'd 119;
defparam Ur6_n_14_pp.C7 = 11'd 12;
defparam Ur6_n_14_pp.C8 = 11'd 612;
defparam Ur6_n_14_pp.C9 = 11'd 505;
defparam Ur6_n_14_pp.CA = 11'd 515;
defparam Ur6_n_14_pp.CB = 11'd 408;
defparam Ur6_n_14_pp.CC = 11'd 828;
defparam Ur6_n_14_pp.CD = 11'd 721;
defparam Ur6_n_14_pp.CE = 11'd 731;
defparam Ur6_n_14_pp.CF = 11'd 624;
assign lut_val_6_n_14_pp[13] = lut_val_6_n_14_pp[10];
assign lut_val_6_n_14_pp[12] = lut_val_6_n_14_pp[10];
assign lut_val_6_n_14_pp[11] = lut_val_6_n_14_pp[10];
wire [13:0] lut_val_6_n_15_pp;
rom_lut_r_cen Ur6_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_27_n[15],sym_res_26_n[15],sym_res_25_n[15],sym_res_24_n[15] } ), .data_out( lut_val_6_n_15_pp[10:0]) ) ;
defparam Ur6_n_15_pp.DATA_WIDTH = 11;
defparam Ur6_n_15_pp.C0 = 11'd 0;
defparam Ur6_n_15_pp.C1 = 11'd 1941;
defparam Ur6_n_15_pp.C2 = 11'd 1951;
defparam Ur6_n_15_pp.C3 = 11'd 1844;
defparam Ur6_n_15_pp.C4 = 11'd 216;
defparam Ur6_n_15_pp.C5 = 11'd 109;
defparam Ur6_n_15_pp.C6 = 11'd 119;
defparam Ur6_n_15_pp.C7 = 11'd 12;
defparam Ur6_n_15_pp.C8 = 11'd 612;
defparam Ur6_n_15_pp.C9 = 11'd 505;
defparam Ur6_n_15_pp.CA = 11'd 515;
defparam Ur6_n_15_pp.CB = 11'd 408;
defparam Ur6_n_15_pp.CC = 11'd 828;
defparam Ur6_n_15_pp.CD = 11'd 721;
defparam Ur6_n_15_pp.CE = 11'd 731;
defparam Ur6_n_15_pp.CF = 11'd 624;
assign lut_val_6_n_15_pp[13] = lut_val_6_n_15_pp[10];
assign lut_val_6_n_15_pp[12] = lut_val_6_n_15_pp[10];
assign lut_val_6_n_15_pp[11] = lut_val_6_n_15_pp[10];
wire [13:0] lut_val_7_n_0_pp;
rom_lut_r_cen Ur7_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[0],sym_res_30_n[0],sym_res_29_n[0],sym_res_28_n[0] } ), .data_out( lut_val_7_n_0_pp[10:0]) ) ;
defparam Ur7_n_0_pp.DATA_WIDTH = 11;
defparam Ur7_n_0_pp.C0 = 11'd 0;
defparam Ur7_n_0_pp.C1 = 11'd 684;
defparam Ur7_n_0_pp.C2 = 11'd 302;
defparam Ur7_n_0_pp.C3 = 11'd 986;
defparam Ur7_n_0_pp.C4 = 11'd 1876;
defparam Ur7_n_0_pp.C5 = 11'd 512;
defparam Ur7_n_0_pp.C6 = 11'd 130;
defparam Ur7_n_0_pp.C7 = 11'd 814;
defparam Ur7_n_0_pp.C8 = 11'd 1814;
defparam Ur7_n_0_pp.C9 = 11'd 450;
defparam Ur7_n_0_pp.CA = 11'd 68;
defparam Ur7_n_0_pp.CB = 11'd 752;
defparam Ur7_n_0_pp.CC = 11'd 1642;
defparam Ur7_n_0_pp.CD = 11'd 278;
defparam Ur7_n_0_pp.CE = 11'd 1944;
defparam Ur7_n_0_pp.CF = 11'd 580;
assign lut_val_7_n_0_pp[13] = lut_val_7_n_0_pp[10];
assign lut_val_7_n_0_pp[12] = lut_val_7_n_0_pp[10];
assign lut_val_7_n_0_pp[11] = lut_val_7_n_0_pp[10];
wire [13:0] lut_val_7_n_1_pp;
rom_lut_r_cen Ur7_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[1],sym_res_30_n[1],sym_res_29_n[1],sym_res_28_n[1] } ), .data_out( lut_val_7_n_1_pp[10:0]) ) ;
defparam Ur7_n_1_pp.DATA_WIDTH = 11;
defparam Ur7_n_1_pp.C0 = 11'd 0;
defparam Ur7_n_1_pp.C1 = 11'd 684;
defparam Ur7_n_1_pp.C2 = 11'd 302;
defparam Ur7_n_1_pp.C3 = 11'd 986;
defparam Ur7_n_1_pp.C4 = 11'd 1876;
defparam Ur7_n_1_pp.C5 = 11'd 512;
defparam Ur7_n_1_pp.C6 = 11'd 130;
defparam Ur7_n_1_pp.C7 = 11'd 814;
defparam Ur7_n_1_pp.C8 = 11'd 1814;
defparam Ur7_n_1_pp.C9 = 11'd 450;
defparam Ur7_n_1_pp.CA = 11'd 68;
defparam Ur7_n_1_pp.CB = 11'd 752;
defparam Ur7_n_1_pp.CC = 11'd 1642;
defparam Ur7_n_1_pp.CD = 11'd 278;
defparam Ur7_n_1_pp.CE = 11'd 1944;
defparam Ur7_n_1_pp.CF = 11'd 580;
assign lut_val_7_n_1_pp[13] = lut_val_7_n_1_pp[10];
assign lut_val_7_n_1_pp[12] = lut_val_7_n_1_pp[10];
assign lut_val_7_n_1_pp[11] = lut_val_7_n_1_pp[10];
wire [13:0] lut_val_7_n_2_pp;
rom_lut_r_cen Ur7_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[2],sym_res_30_n[2],sym_res_29_n[2],sym_res_28_n[2] } ), .data_out( lut_val_7_n_2_pp[10:0]) ) ;
defparam Ur7_n_2_pp.DATA_WIDTH = 11;
defparam Ur7_n_2_pp.C0 = 11'd 0;
defparam Ur7_n_2_pp.C1 = 11'd 684;
defparam Ur7_n_2_pp.C2 = 11'd 302;
defparam Ur7_n_2_pp.C3 = 11'd 986;
defparam Ur7_n_2_pp.C4 = 11'd 1876;
defparam Ur7_n_2_pp.C5 = 11'd 512;
defparam Ur7_n_2_pp.C6 = 11'd 130;
defparam Ur7_n_2_pp.C7 = 11'd 814;
defparam Ur7_n_2_pp.C8 = 11'd 1814;
defparam Ur7_n_2_pp.C9 = 11'd 450;
defparam Ur7_n_2_pp.CA = 11'd 68;
defparam Ur7_n_2_pp.CB = 11'd 752;
defparam Ur7_n_2_pp.CC = 11'd 1642;
defparam Ur7_n_2_pp.CD = 11'd 278;
defparam Ur7_n_2_pp.CE = 11'd 1944;
defparam Ur7_n_2_pp.CF = 11'd 580;
assign lut_val_7_n_2_pp[13] = lut_val_7_n_2_pp[10];
assign lut_val_7_n_2_pp[12] = lut_val_7_n_2_pp[10];
assign lut_val_7_n_2_pp[11] = lut_val_7_n_2_pp[10];
wire [13:0] lut_val_7_n_3_pp;
rom_lut_r_cen Ur7_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[3],sym_res_30_n[3],sym_res_29_n[3],sym_res_28_n[3] } ), .data_out( lut_val_7_n_3_pp[10:0]) ) ;
defparam Ur7_n_3_pp.DATA_WIDTH = 11;
defparam Ur7_n_3_pp.C0 = 11'd 0;
defparam Ur7_n_3_pp.C1 = 11'd 684;
defparam Ur7_n_3_pp.C2 = 11'd 302;
defparam Ur7_n_3_pp.C3 = 11'd 986;
defparam Ur7_n_3_pp.C4 = 11'd 1876;
defparam Ur7_n_3_pp.C5 = 11'd 512;
defparam Ur7_n_3_pp.C6 = 11'd 130;
defparam Ur7_n_3_pp.C7 = 11'd 814;
defparam Ur7_n_3_pp.C8 = 11'd 1814;
defparam Ur7_n_3_pp.C9 = 11'd 450;
defparam Ur7_n_3_pp.CA = 11'd 68;
defparam Ur7_n_3_pp.CB = 11'd 752;
defparam Ur7_n_3_pp.CC = 11'd 1642;
defparam Ur7_n_3_pp.CD = 11'd 278;
defparam Ur7_n_3_pp.CE = 11'd 1944;
defparam Ur7_n_3_pp.CF = 11'd 580;
assign lut_val_7_n_3_pp[13] = lut_val_7_n_3_pp[10];
assign lut_val_7_n_3_pp[12] = lut_val_7_n_3_pp[10];
assign lut_val_7_n_3_pp[11] = lut_val_7_n_3_pp[10];
wire [13:0] lut_val_7_n_4_pp;
rom_lut_r_cen Ur7_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[4],sym_res_30_n[4],sym_res_29_n[4],sym_res_28_n[4] } ), .data_out( lut_val_7_n_4_pp[10:0]) ) ;
defparam Ur7_n_4_pp.DATA_WIDTH = 11;
defparam Ur7_n_4_pp.C0 = 11'd 0;
defparam Ur7_n_4_pp.C1 = 11'd 684;
defparam Ur7_n_4_pp.C2 = 11'd 302;
defparam Ur7_n_4_pp.C3 = 11'd 986;
defparam Ur7_n_4_pp.C4 = 11'd 1876;
defparam Ur7_n_4_pp.C5 = 11'd 512;
defparam Ur7_n_4_pp.C6 = 11'd 130;
defparam Ur7_n_4_pp.C7 = 11'd 814;
defparam Ur7_n_4_pp.C8 = 11'd 1814;
defparam Ur7_n_4_pp.C9 = 11'd 450;
defparam Ur7_n_4_pp.CA = 11'd 68;
defparam Ur7_n_4_pp.CB = 11'd 752;
defparam Ur7_n_4_pp.CC = 11'd 1642;
defparam Ur7_n_4_pp.CD = 11'd 278;
defparam Ur7_n_4_pp.CE = 11'd 1944;
defparam Ur7_n_4_pp.CF = 11'd 580;
assign lut_val_7_n_4_pp[13] = lut_val_7_n_4_pp[10];
assign lut_val_7_n_4_pp[12] = lut_val_7_n_4_pp[10];
assign lut_val_7_n_4_pp[11] = lut_val_7_n_4_pp[10];
wire [13:0] lut_val_7_n_5_pp;
rom_lut_r_cen Ur7_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[5],sym_res_30_n[5],sym_res_29_n[5],sym_res_28_n[5] } ), .data_out( lut_val_7_n_5_pp[10:0]) ) ;
defparam Ur7_n_5_pp.DATA_WIDTH = 11;
defparam Ur7_n_5_pp.C0 = 11'd 0;
defparam Ur7_n_5_pp.C1 = 11'd 684;
defparam Ur7_n_5_pp.C2 = 11'd 302;
defparam Ur7_n_5_pp.C3 = 11'd 986;
defparam Ur7_n_5_pp.C4 = 11'd 1876;
defparam Ur7_n_5_pp.C5 = 11'd 512;
defparam Ur7_n_5_pp.C6 = 11'd 130;
defparam Ur7_n_5_pp.C7 = 11'd 814;
defparam Ur7_n_5_pp.C8 = 11'd 1814;
defparam Ur7_n_5_pp.C9 = 11'd 450;
defparam Ur7_n_5_pp.CA = 11'd 68;
defparam Ur7_n_5_pp.CB = 11'd 752;
defparam Ur7_n_5_pp.CC = 11'd 1642;
defparam Ur7_n_5_pp.CD = 11'd 278;
defparam Ur7_n_5_pp.CE = 11'd 1944;
defparam Ur7_n_5_pp.CF = 11'd 580;
assign lut_val_7_n_5_pp[13] = lut_val_7_n_5_pp[10];
assign lut_val_7_n_5_pp[12] = lut_val_7_n_5_pp[10];
assign lut_val_7_n_5_pp[11] = lut_val_7_n_5_pp[10];
wire [13:0] lut_val_7_n_6_pp;
rom_lut_r_cen Ur7_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[6],sym_res_30_n[6],sym_res_29_n[6],sym_res_28_n[6] } ), .data_out( lut_val_7_n_6_pp[10:0]) ) ;
defparam Ur7_n_6_pp.DATA_WIDTH = 11;
defparam Ur7_n_6_pp.C0 = 11'd 0;
defparam Ur7_n_6_pp.C1 = 11'd 684;
defparam Ur7_n_6_pp.C2 = 11'd 302;
defparam Ur7_n_6_pp.C3 = 11'd 986;
defparam Ur7_n_6_pp.C4 = 11'd 1876;
defparam Ur7_n_6_pp.C5 = 11'd 512;
defparam Ur7_n_6_pp.C6 = 11'd 130;
defparam Ur7_n_6_pp.C7 = 11'd 814;
defparam Ur7_n_6_pp.C8 = 11'd 1814;
defparam Ur7_n_6_pp.C9 = 11'd 450;
defparam Ur7_n_6_pp.CA = 11'd 68;
defparam Ur7_n_6_pp.CB = 11'd 752;
defparam Ur7_n_6_pp.CC = 11'd 1642;
defparam Ur7_n_6_pp.CD = 11'd 278;
defparam Ur7_n_6_pp.CE = 11'd 1944;
defparam Ur7_n_6_pp.CF = 11'd 580;
assign lut_val_7_n_6_pp[13] = lut_val_7_n_6_pp[10];
assign lut_val_7_n_6_pp[12] = lut_val_7_n_6_pp[10];
assign lut_val_7_n_6_pp[11] = lut_val_7_n_6_pp[10];
wire [13:0] lut_val_7_n_7_pp;
rom_lut_r_cen Ur7_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[7],sym_res_30_n[7],sym_res_29_n[7],sym_res_28_n[7] } ), .data_out( lut_val_7_n_7_pp[10:0]) ) ;
defparam Ur7_n_7_pp.DATA_WIDTH = 11;
defparam Ur7_n_7_pp.C0 = 11'd 0;
defparam Ur7_n_7_pp.C1 = 11'd 684;
defparam Ur7_n_7_pp.C2 = 11'd 302;
defparam Ur7_n_7_pp.C3 = 11'd 986;
defparam Ur7_n_7_pp.C4 = 11'd 1876;
defparam Ur7_n_7_pp.C5 = 11'd 512;
defparam Ur7_n_7_pp.C6 = 11'd 130;
defparam Ur7_n_7_pp.C7 = 11'd 814;
defparam Ur7_n_7_pp.C8 = 11'd 1814;
defparam Ur7_n_7_pp.C9 = 11'd 450;
defparam Ur7_n_7_pp.CA = 11'd 68;
defparam Ur7_n_7_pp.CB = 11'd 752;
defparam Ur7_n_7_pp.CC = 11'd 1642;
defparam Ur7_n_7_pp.CD = 11'd 278;
defparam Ur7_n_7_pp.CE = 11'd 1944;
defparam Ur7_n_7_pp.CF = 11'd 580;
assign lut_val_7_n_7_pp[13] = lut_val_7_n_7_pp[10];
assign lut_val_7_n_7_pp[12] = lut_val_7_n_7_pp[10];
assign lut_val_7_n_7_pp[11] = lut_val_7_n_7_pp[10];
wire [13:0] lut_val_7_n_8_pp;
rom_lut_r_cen Ur7_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[8],sym_res_30_n[8],sym_res_29_n[8],sym_res_28_n[8] } ), .data_out( lut_val_7_n_8_pp[10:0]) ) ;
defparam Ur7_n_8_pp.DATA_WIDTH = 11;
defparam Ur7_n_8_pp.C0 = 11'd 0;
defparam Ur7_n_8_pp.C1 = 11'd 684;
defparam Ur7_n_8_pp.C2 = 11'd 302;
defparam Ur7_n_8_pp.C3 = 11'd 986;
defparam Ur7_n_8_pp.C4 = 11'd 1876;
defparam Ur7_n_8_pp.C5 = 11'd 512;
defparam Ur7_n_8_pp.C6 = 11'd 130;
defparam Ur7_n_8_pp.C7 = 11'd 814;
defparam Ur7_n_8_pp.C8 = 11'd 1814;
defparam Ur7_n_8_pp.C9 = 11'd 450;
defparam Ur7_n_8_pp.CA = 11'd 68;
defparam Ur7_n_8_pp.CB = 11'd 752;
defparam Ur7_n_8_pp.CC = 11'd 1642;
defparam Ur7_n_8_pp.CD = 11'd 278;
defparam Ur7_n_8_pp.CE = 11'd 1944;
defparam Ur7_n_8_pp.CF = 11'd 580;
assign lut_val_7_n_8_pp[13] = lut_val_7_n_8_pp[10];
assign lut_val_7_n_8_pp[12] = lut_val_7_n_8_pp[10];
assign lut_val_7_n_8_pp[11] = lut_val_7_n_8_pp[10];
wire [13:0] lut_val_7_n_9_pp;
rom_lut_r_cen Ur7_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[9],sym_res_30_n[9],sym_res_29_n[9],sym_res_28_n[9] } ), .data_out( lut_val_7_n_9_pp[10:0]) ) ;
defparam Ur7_n_9_pp.DATA_WIDTH = 11;
defparam Ur7_n_9_pp.C0 = 11'd 0;
defparam Ur7_n_9_pp.C1 = 11'd 684;
defparam Ur7_n_9_pp.C2 = 11'd 302;
defparam Ur7_n_9_pp.C3 = 11'd 986;
defparam Ur7_n_9_pp.C4 = 11'd 1876;
defparam Ur7_n_9_pp.C5 = 11'd 512;
defparam Ur7_n_9_pp.C6 = 11'd 130;
defparam Ur7_n_9_pp.C7 = 11'd 814;
defparam Ur7_n_9_pp.C8 = 11'd 1814;
defparam Ur7_n_9_pp.C9 = 11'd 450;
defparam Ur7_n_9_pp.CA = 11'd 68;
defparam Ur7_n_9_pp.CB = 11'd 752;
defparam Ur7_n_9_pp.CC = 11'd 1642;
defparam Ur7_n_9_pp.CD = 11'd 278;
defparam Ur7_n_9_pp.CE = 11'd 1944;
defparam Ur7_n_9_pp.CF = 11'd 580;
assign lut_val_7_n_9_pp[13] = lut_val_7_n_9_pp[10];
assign lut_val_7_n_9_pp[12] = lut_val_7_n_9_pp[10];
assign lut_val_7_n_9_pp[11] = lut_val_7_n_9_pp[10];
wire [13:0] lut_val_7_n_10_pp;
rom_lut_r_cen Ur7_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[10],sym_res_30_n[10],sym_res_29_n[10],sym_res_28_n[10] } ), .data_out( lut_val_7_n_10_pp[10:0]) ) ;
defparam Ur7_n_10_pp.DATA_WIDTH = 11;
defparam Ur7_n_10_pp.C0 = 11'd 0;
defparam Ur7_n_10_pp.C1 = 11'd 684;
defparam Ur7_n_10_pp.C2 = 11'd 302;
defparam Ur7_n_10_pp.C3 = 11'd 986;
defparam Ur7_n_10_pp.C4 = 11'd 1876;
defparam Ur7_n_10_pp.C5 = 11'd 512;
defparam Ur7_n_10_pp.C6 = 11'd 130;
defparam Ur7_n_10_pp.C7 = 11'd 814;
defparam Ur7_n_10_pp.C8 = 11'd 1814;
defparam Ur7_n_10_pp.C9 = 11'd 450;
defparam Ur7_n_10_pp.CA = 11'd 68;
defparam Ur7_n_10_pp.CB = 11'd 752;
defparam Ur7_n_10_pp.CC = 11'd 1642;
defparam Ur7_n_10_pp.CD = 11'd 278;
defparam Ur7_n_10_pp.CE = 11'd 1944;
defparam Ur7_n_10_pp.CF = 11'd 580;
assign lut_val_7_n_10_pp[13] = lut_val_7_n_10_pp[10];
assign lut_val_7_n_10_pp[12] = lut_val_7_n_10_pp[10];
assign lut_val_7_n_10_pp[11] = lut_val_7_n_10_pp[10];
wire [13:0] lut_val_7_n_11_pp;
rom_lut_r_cen Ur7_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[11],sym_res_30_n[11],sym_res_29_n[11],sym_res_28_n[11] } ), .data_out( lut_val_7_n_11_pp[10:0]) ) ;
defparam Ur7_n_11_pp.DATA_WIDTH = 11;
defparam Ur7_n_11_pp.C0 = 11'd 0;
defparam Ur7_n_11_pp.C1 = 11'd 684;
defparam Ur7_n_11_pp.C2 = 11'd 302;
defparam Ur7_n_11_pp.C3 = 11'd 986;
defparam Ur7_n_11_pp.C4 = 11'd 1876;
defparam Ur7_n_11_pp.C5 = 11'd 512;
defparam Ur7_n_11_pp.C6 = 11'd 130;
defparam Ur7_n_11_pp.C7 = 11'd 814;
defparam Ur7_n_11_pp.C8 = 11'd 1814;
defparam Ur7_n_11_pp.C9 = 11'd 450;
defparam Ur7_n_11_pp.CA = 11'd 68;
defparam Ur7_n_11_pp.CB = 11'd 752;
defparam Ur7_n_11_pp.CC = 11'd 1642;
defparam Ur7_n_11_pp.CD = 11'd 278;
defparam Ur7_n_11_pp.CE = 11'd 1944;
defparam Ur7_n_11_pp.CF = 11'd 580;
assign lut_val_7_n_11_pp[13] = lut_val_7_n_11_pp[10];
assign lut_val_7_n_11_pp[12] = lut_val_7_n_11_pp[10];
assign lut_val_7_n_11_pp[11] = lut_val_7_n_11_pp[10];
wire [13:0] lut_val_7_n_12_pp;
rom_lut_r_cen Ur7_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[12],sym_res_30_n[12],sym_res_29_n[12],sym_res_28_n[12] } ), .data_out( lut_val_7_n_12_pp[10:0]) ) ;
defparam Ur7_n_12_pp.DATA_WIDTH = 11;
defparam Ur7_n_12_pp.C0 = 11'd 0;
defparam Ur7_n_12_pp.C1 = 11'd 684;
defparam Ur7_n_12_pp.C2 = 11'd 302;
defparam Ur7_n_12_pp.C3 = 11'd 986;
defparam Ur7_n_12_pp.C4 = 11'd 1876;
defparam Ur7_n_12_pp.C5 = 11'd 512;
defparam Ur7_n_12_pp.C6 = 11'd 130;
defparam Ur7_n_12_pp.C7 = 11'd 814;
defparam Ur7_n_12_pp.C8 = 11'd 1814;
defparam Ur7_n_12_pp.C9 = 11'd 450;
defparam Ur7_n_12_pp.CA = 11'd 68;
defparam Ur7_n_12_pp.CB = 11'd 752;
defparam Ur7_n_12_pp.CC = 11'd 1642;
defparam Ur7_n_12_pp.CD = 11'd 278;
defparam Ur7_n_12_pp.CE = 11'd 1944;
defparam Ur7_n_12_pp.CF = 11'd 580;
assign lut_val_7_n_12_pp[13] = lut_val_7_n_12_pp[10];
assign lut_val_7_n_12_pp[12] = lut_val_7_n_12_pp[10];
assign lut_val_7_n_12_pp[11] = lut_val_7_n_12_pp[10];
wire [13:0] lut_val_7_n_13_pp;
rom_lut_r_cen Ur7_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[13],sym_res_30_n[13],sym_res_29_n[13],sym_res_28_n[13] } ), .data_out( lut_val_7_n_13_pp[10:0]) ) ;
defparam Ur7_n_13_pp.DATA_WIDTH = 11;
defparam Ur7_n_13_pp.C0 = 11'd 0;
defparam Ur7_n_13_pp.C1 = 11'd 684;
defparam Ur7_n_13_pp.C2 = 11'd 302;
defparam Ur7_n_13_pp.C3 = 11'd 986;
defparam Ur7_n_13_pp.C4 = 11'd 1876;
defparam Ur7_n_13_pp.C5 = 11'd 512;
defparam Ur7_n_13_pp.C6 = 11'd 130;
defparam Ur7_n_13_pp.C7 = 11'd 814;
defparam Ur7_n_13_pp.C8 = 11'd 1814;
defparam Ur7_n_13_pp.C9 = 11'd 450;
defparam Ur7_n_13_pp.CA = 11'd 68;
defparam Ur7_n_13_pp.CB = 11'd 752;
defparam Ur7_n_13_pp.CC = 11'd 1642;
defparam Ur7_n_13_pp.CD = 11'd 278;
defparam Ur7_n_13_pp.CE = 11'd 1944;
defparam Ur7_n_13_pp.CF = 11'd 580;
assign lut_val_7_n_13_pp[13] = lut_val_7_n_13_pp[10];
assign lut_val_7_n_13_pp[12] = lut_val_7_n_13_pp[10];
assign lut_val_7_n_13_pp[11] = lut_val_7_n_13_pp[10];
wire [13:0] lut_val_7_n_14_pp;
rom_lut_r_cen Ur7_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[14],sym_res_30_n[14],sym_res_29_n[14],sym_res_28_n[14] } ), .data_out( lut_val_7_n_14_pp[10:0]) ) ;
defparam Ur7_n_14_pp.DATA_WIDTH = 11;
defparam Ur7_n_14_pp.C0 = 11'd 0;
defparam Ur7_n_14_pp.C1 = 11'd 684;
defparam Ur7_n_14_pp.C2 = 11'd 302;
defparam Ur7_n_14_pp.C3 = 11'd 986;
defparam Ur7_n_14_pp.C4 = 11'd 1876;
defparam Ur7_n_14_pp.C5 = 11'd 512;
defparam Ur7_n_14_pp.C6 = 11'd 130;
defparam Ur7_n_14_pp.C7 = 11'd 814;
defparam Ur7_n_14_pp.C8 = 11'd 1814;
defparam Ur7_n_14_pp.C9 = 11'd 450;
defparam Ur7_n_14_pp.CA = 11'd 68;
defparam Ur7_n_14_pp.CB = 11'd 752;
defparam Ur7_n_14_pp.CC = 11'd 1642;
defparam Ur7_n_14_pp.CD = 11'd 278;
defparam Ur7_n_14_pp.CE = 11'd 1944;
defparam Ur7_n_14_pp.CF = 11'd 580;
assign lut_val_7_n_14_pp[13] = lut_val_7_n_14_pp[10];
assign lut_val_7_n_14_pp[12] = lut_val_7_n_14_pp[10];
assign lut_val_7_n_14_pp[11] = lut_val_7_n_14_pp[10];
wire [13:0] lut_val_7_n_15_pp;
rom_lut_r_cen Ur7_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_31_n[15],sym_res_30_n[15],sym_res_29_n[15],sym_res_28_n[15] } ), .data_out( lut_val_7_n_15_pp[10:0]) ) ;
defparam Ur7_n_15_pp.DATA_WIDTH = 11;
defparam Ur7_n_15_pp.C0 = 11'd 0;
defparam Ur7_n_15_pp.C1 = 11'd 684;
defparam Ur7_n_15_pp.C2 = 11'd 302;
defparam Ur7_n_15_pp.C3 = 11'd 986;
defparam Ur7_n_15_pp.C4 = 11'd 1876;
defparam Ur7_n_15_pp.C5 = 11'd 512;
defparam Ur7_n_15_pp.C6 = 11'd 130;
defparam Ur7_n_15_pp.C7 = 11'd 814;
defparam Ur7_n_15_pp.C8 = 11'd 1814;
defparam Ur7_n_15_pp.C9 = 11'd 450;
defparam Ur7_n_15_pp.CA = 11'd 68;
defparam Ur7_n_15_pp.CB = 11'd 752;
defparam Ur7_n_15_pp.CC = 11'd 1642;
defparam Ur7_n_15_pp.CD = 11'd 278;
defparam Ur7_n_15_pp.CE = 11'd 1944;
defparam Ur7_n_15_pp.CF = 11'd 580;
assign lut_val_7_n_15_pp[13] = lut_val_7_n_15_pp[10];
assign lut_val_7_n_15_pp[12] = lut_val_7_n_15_pp[10];
assign lut_val_7_n_15_pp[11] = lut_val_7_n_15_pp[10];
wire [13:0] lut_val_8_n_0_pp;
rom_lut_r_cen Ur8_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[0],sym_res_34_n[0],sym_res_33_n[0],sym_res_32_n[0] } ), .data_out( lut_val_8_n_0_pp[11:0]) ) ;
defparam Ur8_n_0_pp.DATA_WIDTH = 12;
defparam Ur8_n_0_pp.C0 = 12'd 0;
defparam Ur8_n_0_pp.C1 = 12'd 154;
defparam Ur8_n_0_pp.C2 = 12'd 377;
defparam Ur8_n_0_pp.C3 = 12'd 531;
defparam Ur8_n_0_pp.C4 = 12'd 3846;
defparam Ur8_n_0_pp.C5 = 12'd 4000;
defparam Ur8_n_0_pp.C6 = 12'd 127;
defparam Ur8_n_0_pp.C7 = 12'd 281;
defparam Ur8_n_0_pp.C8 = 12'd 2476;
defparam Ur8_n_0_pp.C9 = 12'd 2630;
defparam Ur8_n_0_pp.CA = 12'd 2853;
defparam Ur8_n_0_pp.CB = 12'd 3007;
defparam Ur8_n_0_pp.CC = 12'd 2226;
defparam Ur8_n_0_pp.CD = 12'd 2380;
defparam Ur8_n_0_pp.CE = 12'd 2603;
defparam Ur8_n_0_pp.CF = 12'd 2757;
assign lut_val_8_n_0_pp[13] = lut_val_8_n_0_pp[11];
assign lut_val_8_n_0_pp[12] = lut_val_8_n_0_pp[11];
wire [13:0] lut_val_8_n_1_pp;
rom_lut_r_cen Ur8_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[1],sym_res_34_n[1],sym_res_33_n[1],sym_res_32_n[1] } ), .data_out( lut_val_8_n_1_pp[11:0]) ) ;
defparam Ur8_n_1_pp.DATA_WIDTH = 12;
defparam Ur8_n_1_pp.C0 = 12'd 0;
defparam Ur8_n_1_pp.C1 = 12'd 154;
defparam Ur8_n_1_pp.C2 = 12'd 377;
defparam Ur8_n_1_pp.C3 = 12'd 531;
defparam Ur8_n_1_pp.C4 = 12'd 3846;
defparam Ur8_n_1_pp.C5 = 12'd 4000;
defparam Ur8_n_1_pp.C6 = 12'd 127;
defparam Ur8_n_1_pp.C7 = 12'd 281;
defparam Ur8_n_1_pp.C8 = 12'd 2476;
defparam Ur8_n_1_pp.C9 = 12'd 2630;
defparam Ur8_n_1_pp.CA = 12'd 2853;
defparam Ur8_n_1_pp.CB = 12'd 3007;
defparam Ur8_n_1_pp.CC = 12'd 2226;
defparam Ur8_n_1_pp.CD = 12'd 2380;
defparam Ur8_n_1_pp.CE = 12'd 2603;
defparam Ur8_n_1_pp.CF = 12'd 2757;
assign lut_val_8_n_1_pp[13] = lut_val_8_n_1_pp[11];
assign lut_val_8_n_1_pp[12] = lut_val_8_n_1_pp[11];
wire [13:0] lut_val_8_n_2_pp;
rom_lut_r_cen Ur8_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[2],sym_res_34_n[2],sym_res_33_n[2],sym_res_32_n[2] } ), .data_out( lut_val_8_n_2_pp[11:0]) ) ;
defparam Ur8_n_2_pp.DATA_WIDTH = 12;
defparam Ur8_n_2_pp.C0 = 12'd 0;
defparam Ur8_n_2_pp.C1 = 12'd 154;
defparam Ur8_n_2_pp.C2 = 12'd 377;
defparam Ur8_n_2_pp.C3 = 12'd 531;
defparam Ur8_n_2_pp.C4 = 12'd 3846;
defparam Ur8_n_2_pp.C5 = 12'd 4000;
defparam Ur8_n_2_pp.C6 = 12'd 127;
defparam Ur8_n_2_pp.C7 = 12'd 281;
defparam Ur8_n_2_pp.C8 = 12'd 2476;
defparam Ur8_n_2_pp.C9 = 12'd 2630;
defparam Ur8_n_2_pp.CA = 12'd 2853;
defparam Ur8_n_2_pp.CB = 12'd 3007;
defparam Ur8_n_2_pp.CC = 12'd 2226;
defparam Ur8_n_2_pp.CD = 12'd 2380;
defparam Ur8_n_2_pp.CE = 12'd 2603;
defparam Ur8_n_2_pp.CF = 12'd 2757;
assign lut_val_8_n_2_pp[13] = lut_val_8_n_2_pp[11];
assign lut_val_8_n_2_pp[12] = lut_val_8_n_2_pp[11];
wire [13:0] lut_val_8_n_3_pp;
rom_lut_r_cen Ur8_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[3],sym_res_34_n[3],sym_res_33_n[3],sym_res_32_n[3] } ), .data_out( lut_val_8_n_3_pp[11:0]) ) ;
defparam Ur8_n_3_pp.DATA_WIDTH = 12;
defparam Ur8_n_3_pp.C0 = 12'd 0;
defparam Ur8_n_3_pp.C1 = 12'd 154;
defparam Ur8_n_3_pp.C2 = 12'd 377;
defparam Ur8_n_3_pp.C3 = 12'd 531;
defparam Ur8_n_3_pp.C4 = 12'd 3846;
defparam Ur8_n_3_pp.C5 = 12'd 4000;
defparam Ur8_n_3_pp.C6 = 12'd 127;
defparam Ur8_n_3_pp.C7 = 12'd 281;
defparam Ur8_n_3_pp.C8 = 12'd 2476;
defparam Ur8_n_3_pp.C9 = 12'd 2630;
defparam Ur8_n_3_pp.CA = 12'd 2853;
defparam Ur8_n_3_pp.CB = 12'd 3007;
defparam Ur8_n_3_pp.CC = 12'd 2226;
defparam Ur8_n_3_pp.CD = 12'd 2380;
defparam Ur8_n_3_pp.CE = 12'd 2603;
defparam Ur8_n_3_pp.CF = 12'd 2757;
assign lut_val_8_n_3_pp[13] = lut_val_8_n_3_pp[11];
assign lut_val_8_n_3_pp[12] = lut_val_8_n_3_pp[11];
wire [13:0] lut_val_8_n_4_pp;
rom_lut_r_cen Ur8_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[4],sym_res_34_n[4],sym_res_33_n[4],sym_res_32_n[4] } ), .data_out( lut_val_8_n_4_pp[11:0]) ) ;
defparam Ur8_n_4_pp.DATA_WIDTH = 12;
defparam Ur8_n_4_pp.C0 = 12'd 0;
defparam Ur8_n_4_pp.C1 = 12'd 154;
defparam Ur8_n_4_pp.C2 = 12'd 377;
defparam Ur8_n_4_pp.C3 = 12'd 531;
defparam Ur8_n_4_pp.C4 = 12'd 3846;
defparam Ur8_n_4_pp.C5 = 12'd 4000;
defparam Ur8_n_4_pp.C6 = 12'd 127;
defparam Ur8_n_4_pp.C7 = 12'd 281;
defparam Ur8_n_4_pp.C8 = 12'd 2476;
defparam Ur8_n_4_pp.C9 = 12'd 2630;
defparam Ur8_n_4_pp.CA = 12'd 2853;
defparam Ur8_n_4_pp.CB = 12'd 3007;
defparam Ur8_n_4_pp.CC = 12'd 2226;
defparam Ur8_n_4_pp.CD = 12'd 2380;
defparam Ur8_n_4_pp.CE = 12'd 2603;
defparam Ur8_n_4_pp.CF = 12'd 2757;
assign lut_val_8_n_4_pp[13] = lut_val_8_n_4_pp[11];
assign lut_val_8_n_4_pp[12] = lut_val_8_n_4_pp[11];
wire [13:0] lut_val_8_n_5_pp;
rom_lut_r_cen Ur8_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[5],sym_res_34_n[5],sym_res_33_n[5],sym_res_32_n[5] } ), .data_out( lut_val_8_n_5_pp[11:0]) ) ;
defparam Ur8_n_5_pp.DATA_WIDTH = 12;
defparam Ur8_n_5_pp.C0 = 12'd 0;
defparam Ur8_n_5_pp.C1 = 12'd 154;
defparam Ur8_n_5_pp.C2 = 12'd 377;
defparam Ur8_n_5_pp.C3 = 12'd 531;
defparam Ur8_n_5_pp.C4 = 12'd 3846;
defparam Ur8_n_5_pp.C5 = 12'd 4000;
defparam Ur8_n_5_pp.C6 = 12'd 127;
defparam Ur8_n_5_pp.C7 = 12'd 281;
defparam Ur8_n_5_pp.C8 = 12'd 2476;
defparam Ur8_n_5_pp.C9 = 12'd 2630;
defparam Ur8_n_5_pp.CA = 12'd 2853;
defparam Ur8_n_5_pp.CB = 12'd 3007;
defparam Ur8_n_5_pp.CC = 12'd 2226;
defparam Ur8_n_5_pp.CD = 12'd 2380;
defparam Ur8_n_5_pp.CE = 12'd 2603;
defparam Ur8_n_5_pp.CF = 12'd 2757;
assign lut_val_8_n_5_pp[13] = lut_val_8_n_5_pp[11];
assign lut_val_8_n_5_pp[12] = lut_val_8_n_5_pp[11];
wire [13:0] lut_val_8_n_6_pp;
rom_lut_r_cen Ur8_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[6],sym_res_34_n[6],sym_res_33_n[6],sym_res_32_n[6] } ), .data_out( lut_val_8_n_6_pp[11:0]) ) ;
defparam Ur8_n_6_pp.DATA_WIDTH = 12;
defparam Ur8_n_6_pp.C0 = 12'd 0;
defparam Ur8_n_6_pp.C1 = 12'd 154;
defparam Ur8_n_6_pp.C2 = 12'd 377;
defparam Ur8_n_6_pp.C3 = 12'd 531;
defparam Ur8_n_6_pp.C4 = 12'd 3846;
defparam Ur8_n_6_pp.C5 = 12'd 4000;
defparam Ur8_n_6_pp.C6 = 12'd 127;
defparam Ur8_n_6_pp.C7 = 12'd 281;
defparam Ur8_n_6_pp.C8 = 12'd 2476;
defparam Ur8_n_6_pp.C9 = 12'd 2630;
defparam Ur8_n_6_pp.CA = 12'd 2853;
defparam Ur8_n_6_pp.CB = 12'd 3007;
defparam Ur8_n_6_pp.CC = 12'd 2226;
defparam Ur8_n_6_pp.CD = 12'd 2380;
defparam Ur8_n_6_pp.CE = 12'd 2603;
defparam Ur8_n_6_pp.CF = 12'd 2757;
assign lut_val_8_n_6_pp[13] = lut_val_8_n_6_pp[11];
assign lut_val_8_n_6_pp[12] = lut_val_8_n_6_pp[11];
wire [13:0] lut_val_8_n_7_pp;
rom_lut_r_cen Ur8_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[7],sym_res_34_n[7],sym_res_33_n[7],sym_res_32_n[7] } ), .data_out( lut_val_8_n_7_pp[11:0]) ) ;
defparam Ur8_n_7_pp.DATA_WIDTH = 12;
defparam Ur8_n_7_pp.C0 = 12'd 0;
defparam Ur8_n_7_pp.C1 = 12'd 154;
defparam Ur8_n_7_pp.C2 = 12'd 377;
defparam Ur8_n_7_pp.C3 = 12'd 531;
defparam Ur8_n_7_pp.C4 = 12'd 3846;
defparam Ur8_n_7_pp.C5 = 12'd 4000;
defparam Ur8_n_7_pp.C6 = 12'd 127;
defparam Ur8_n_7_pp.C7 = 12'd 281;
defparam Ur8_n_7_pp.C8 = 12'd 2476;
defparam Ur8_n_7_pp.C9 = 12'd 2630;
defparam Ur8_n_7_pp.CA = 12'd 2853;
defparam Ur8_n_7_pp.CB = 12'd 3007;
defparam Ur8_n_7_pp.CC = 12'd 2226;
defparam Ur8_n_7_pp.CD = 12'd 2380;
defparam Ur8_n_7_pp.CE = 12'd 2603;
defparam Ur8_n_7_pp.CF = 12'd 2757;
assign lut_val_8_n_7_pp[13] = lut_val_8_n_7_pp[11];
assign lut_val_8_n_7_pp[12] = lut_val_8_n_7_pp[11];
wire [13:0] lut_val_8_n_8_pp;
rom_lut_r_cen Ur8_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[8],sym_res_34_n[8],sym_res_33_n[8],sym_res_32_n[8] } ), .data_out( lut_val_8_n_8_pp[11:0]) ) ;
defparam Ur8_n_8_pp.DATA_WIDTH = 12;
defparam Ur8_n_8_pp.C0 = 12'd 0;
defparam Ur8_n_8_pp.C1 = 12'd 154;
defparam Ur8_n_8_pp.C2 = 12'd 377;
defparam Ur8_n_8_pp.C3 = 12'd 531;
defparam Ur8_n_8_pp.C4 = 12'd 3846;
defparam Ur8_n_8_pp.C5 = 12'd 4000;
defparam Ur8_n_8_pp.C6 = 12'd 127;
defparam Ur8_n_8_pp.C7 = 12'd 281;
defparam Ur8_n_8_pp.C8 = 12'd 2476;
defparam Ur8_n_8_pp.C9 = 12'd 2630;
defparam Ur8_n_8_pp.CA = 12'd 2853;
defparam Ur8_n_8_pp.CB = 12'd 3007;
defparam Ur8_n_8_pp.CC = 12'd 2226;
defparam Ur8_n_8_pp.CD = 12'd 2380;
defparam Ur8_n_8_pp.CE = 12'd 2603;
defparam Ur8_n_8_pp.CF = 12'd 2757;
assign lut_val_8_n_8_pp[13] = lut_val_8_n_8_pp[11];
assign lut_val_8_n_8_pp[12] = lut_val_8_n_8_pp[11];
wire [13:0] lut_val_8_n_9_pp;
rom_lut_r_cen Ur8_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[9],sym_res_34_n[9],sym_res_33_n[9],sym_res_32_n[9] } ), .data_out( lut_val_8_n_9_pp[11:0]) ) ;
defparam Ur8_n_9_pp.DATA_WIDTH = 12;
defparam Ur8_n_9_pp.C0 = 12'd 0;
defparam Ur8_n_9_pp.C1 = 12'd 154;
defparam Ur8_n_9_pp.C2 = 12'd 377;
defparam Ur8_n_9_pp.C3 = 12'd 531;
defparam Ur8_n_9_pp.C4 = 12'd 3846;
defparam Ur8_n_9_pp.C5 = 12'd 4000;
defparam Ur8_n_9_pp.C6 = 12'd 127;
defparam Ur8_n_9_pp.C7 = 12'd 281;
defparam Ur8_n_9_pp.C8 = 12'd 2476;
defparam Ur8_n_9_pp.C9 = 12'd 2630;
defparam Ur8_n_9_pp.CA = 12'd 2853;
defparam Ur8_n_9_pp.CB = 12'd 3007;
defparam Ur8_n_9_pp.CC = 12'd 2226;
defparam Ur8_n_9_pp.CD = 12'd 2380;
defparam Ur8_n_9_pp.CE = 12'd 2603;
defparam Ur8_n_9_pp.CF = 12'd 2757;
assign lut_val_8_n_9_pp[13] = lut_val_8_n_9_pp[11];
assign lut_val_8_n_9_pp[12] = lut_val_8_n_9_pp[11];
wire [13:0] lut_val_8_n_10_pp;
rom_lut_r_cen Ur8_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[10],sym_res_34_n[10],sym_res_33_n[10],sym_res_32_n[10] } ), .data_out( lut_val_8_n_10_pp[11:0]) ) ;
defparam Ur8_n_10_pp.DATA_WIDTH = 12;
defparam Ur8_n_10_pp.C0 = 12'd 0;
defparam Ur8_n_10_pp.C1 = 12'd 154;
defparam Ur8_n_10_pp.C2 = 12'd 377;
defparam Ur8_n_10_pp.C3 = 12'd 531;
defparam Ur8_n_10_pp.C4 = 12'd 3846;
defparam Ur8_n_10_pp.C5 = 12'd 4000;
defparam Ur8_n_10_pp.C6 = 12'd 127;
defparam Ur8_n_10_pp.C7 = 12'd 281;
defparam Ur8_n_10_pp.C8 = 12'd 2476;
defparam Ur8_n_10_pp.C9 = 12'd 2630;
defparam Ur8_n_10_pp.CA = 12'd 2853;
defparam Ur8_n_10_pp.CB = 12'd 3007;
defparam Ur8_n_10_pp.CC = 12'd 2226;
defparam Ur8_n_10_pp.CD = 12'd 2380;
defparam Ur8_n_10_pp.CE = 12'd 2603;
defparam Ur8_n_10_pp.CF = 12'd 2757;
assign lut_val_8_n_10_pp[13] = lut_val_8_n_10_pp[11];
assign lut_val_8_n_10_pp[12] = lut_val_8_n_10_pp[11];
wire [13:0] lut_val_8_n_11_pp;
rom_lut_r_cen Ur8_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[11],sym_res_34_n[11],sym_res_33_n[11],sym_res_32_n[11] } ), .data_out( lut_val_8_n_11_pp[11:0]) ) ;
defparam Ur8_n_11_pp.DATA_WIDTH = 12;
defparam Ur8_n_11_pp.C0 = 12'd 0;
defparam Ur8_n_11_pp.C1 = 12'd 154;
defparam Ur8_n_11_pp.C2 = 12'd 377;
defparam Ur8_n_11_pp.C3 = 12'd 531;
defparam Ur8_n_11_pp.C4 = 12'd 3846;
defparam Ur8_n_11_pp.C5 = 12'd 4000;
defparam Ur8_n_11_pp.C6 = 12'd 127;
defparam Ur8_n_11_pp.C7 = 12'd 281;
defparam Ur8_n_11_pp.C8 = 12'd 2476;
defparam Ur8_n_11_pp.C9 = 12'd 2630;
defparam Ur8_n_11_pp.CA = 12'd 2853;
defparam Ur8_n_11_pp.CB = 12'd 3007;
defparam Ur8_n_11_pp.CC = 12'd 2226;
defparam Ur8_n_11_pp.CD = 12'd 2380;
defparam Ur8_n_11_pp.CE = 12'd 2603;
defparam Ur8_n_11_pp.CF = 12'd 2757;
assign lut_val_8_n_11_pp[13] = lut_val_8_n_11_pp[11];
assign lut_val_8_n_11_pp[12] = lut_val_8_n_11_pp[11];
wire [13:0] lut_val_8_n_12_pp;
rom_lut_r_cen Ur8_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[12],sym_res_34_n[12],sym_res_33_n[12],sym_res_32_n[12] } ), .data_out( lut_val_8_n_12_pp[11:0]) ) ;
defparam Ur8_n_12_pp.DATA_WIDTH = 12;
defparam Ur8_n_12_pp.C0 = 12'd 0;
defparam Ur8_n_12_pp.C1 = 12'd 154;
defparam Ur8_n_12_pp.C2 = 12'd 377;
defparam Ur8_n_12_pp.C3 = 12'd 531;
defparam Ur8_n_12_pp.C4 = 12'd 3846;
defparam Ur8_n_12_pp.C5 = 12'd 4000;
defparam Ur8_n_12_pp.C6 = 12'd 127;
defparam Ur8_n_12_pp.C7 = 12'd 281;
defparam Ur8_n_12_pp.C8 = 12'd 2476;
defparam Ur8_n_12_pp.C9 = 12'd 2630;
defparam Ur8_n_12_pp.CA = 12'd 2853;
defparam Ur8_n_12_pp.CB = 12'd 3007;
defparam Ur8_n_12_pp.CC = 12'd 2226;
defparam Ur8_n_12_pp.CD = 12'd 2380;
defparam Ur8_n_12_pp.CE = 12'd 2603;
defparam Ur8_n_12_pp.CF = 12'd 2757;
assign lut_val_8_n_12_pp[13] = lut_val_8_n_12_pp[11];
assign lut_val_8_n_12_pp[12] = lut_val_8_n_12_pp[11];
wire [13:0] lut_val_8_n_13_pp;
rom_lut_r_cen Ur8_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[13],sym_res_34_n[13],sym_res_33_n[13],sym_res_32_n[13] } ), .data_out( lut_val_8_n_13_pp[11:0]) ) ;
defparam Ur8_n_13_pp.DATA_WIDTH = 12;
defparam Ur8_n_13_pp.C0 = 12'd 0;
defparam Ur8_n_13_pp.C1 = 12'd 154;
defparam Ur8_n_13_pp.C2 = 12'd 377;
defparam Ur8_n_13_pp.C3 = 12'd 531;
defparam Ur8_n_13_pp.C4 = 12'd 3846;
defparam Ur8_n_13_pp.C5 = 12'd 4000;
defparam Ur8_n_13_pp.C6 = 12'd 127;
defparam Ur8_n_13_pp.C7 = 12'd 281;
defparam Ur8_n_13_pp.C8 = 12'd 2476;
defparam Ur8_n_13_pp.C9 = 12'd 2630;
defparam Ur8_n_13_pp.CA = 12'd 2853;
defparam Ur8_n_13_pp.CB = 12'd 3007;
defparam Ur8_n_13_pp.CC = 12'd 2226;
defparam Ur8_n_13_pp.CD = 12'd 2380;
defparam Ur8_n_13_pp.CE = 12'd 2603;
defparam Ur8_n_13_pp.CF = 12'd 2757;
assign lut_val_8_n_13_pp[13] = lut_val_8_n_13_pp[11];
assign lut_val_8_n_13_pp[12] = lut_val_8_n_13_pp[11];
wire [13:0] lut_val_8_n_14_pp;
rom_lut_r_cen Ur8_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[14],sym_res_34_n[14],sym_res_33_n[14],sym_res_32_n[14] } ), .data_out( lut_val_8_n_14_pp[11:0]) ) ;
defparam Ur8_n_14_pp.DATA_WIDTH = 12;
defparam Ur8_n_14_pp.C0 = 12'd 0;
defparam Ur8_n_14_pp.C1 = 12'd 154;
defparam Ur8_n_14_pp.C2 = 12'd 377;
defparam Ur8_n_14_pp.C3 = 12'd 531;
defparam Ur8_n_14_pp.C4 = 12'd 3846;
defparam Ur8_n_14_pp.C5 = 12'd 4000;
defparam Ur8_n_14_pp.C6 = 12'd 127;
defparam Ur8_n_14_pp.C7 = 12'd 281;
defparam Ur8_n_14_pp.C8 = 12'd 2476;
defparam Ur8_n_14_pp.C9 = 12'd 2630;
defparam Ur8_n_14_pp.CA = 12'd 2853;
defparam Ur8_n_14_pp.CB = 12'd 3007;
defparam Ur8_n_14_pp.CC = 12'd 2226;
defparam Ur8_n_14_pp.CD = 12'd 2380;
defparam Ur8_n_14_pp.CE = 12'd 2603;
defparam Ur8_n_14_pp.CF = 12'd 2757;
assign lut_val_8_n_14_pp[13] = lut_val_8_n_14_pp[11];
assign lut_val_8_n_14_pp[12] = lut_val_8_n_14_pp[11];
wire [13:0] lut_val_8_n_15_pp;
rom_lut_r_cen Ur8_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_35_n[15],sym_res_34_n[15],sym_res_33_n[15],sym_res_32_n[15] } ), .data_out( lut_val_8_n_15_pp[11:0]) ) ;
defparam Ur8_n_15_pp.DATA_WIDTH = 12;
defparam Ur8_n_15_pp.C0 = 12'd 0;
defparam Ur8_n_15_pp.C1 = 12'd 154;
defparam Ur8_n_15_pp.C2 = 12'd 377;
defparam Ur8_n_15_pp.C3 = 12'd 531;
defparam Ur8_n_15_pp.C4 = 12'd 3846;
defparam Ur8_n_15_pp.C5 = 12'd 4000;
defparam Ur8_n_15_pp.C6 = 12'd 127;
defparam Ur8_n_15_pp.C7 = 12'd 281;
defparam Ur8_n_15_pp.C8 = 12'd 2476;
defparam Ur8_n_15_pp.C9 = 12'd 2630;
defparam Ur8_n_15_pp.CA = 12'd 2853;
defparam Ur8_n_15_pp.CB = 12'd 3007;
defparam Ur8_n_15_pp.CC = 12'd 2226;
defparam Ur8_n_15_pp.CD = 12'd 2380;
defparam Ur8_n_15_pp.CE = 12'd 2603;
defparam Ur8_n_15_pp.CF = 12'd 2757;
assign lut_val_8_n_15_pp[13] = lut_val_8_n_15_pp[11];
assign lut_val_8_n_15_pp[12] = lut_val_8_n_15_pp[11];
wire [13:0] lut_val_9_n_0_pp;
rom_lut_r_cen Ur9_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[0],sym_res_38_n[0],sym_res_37_n[0],sym_res_36_n[0] } ), .data_out( lut_val_9_n_0_pp[13:0]) ) ;
defparam Ur9_n_0_pp.DATA_WIDTH = 14;
defparam Ur9_n_0_pp.C0 = 14'd 0;
defparam Ur9_n_0_pp.C1 = 14'd 13749;
defparam Ur9_n_0_pp.C2 = 14'd 14320;
defparam Ur9_n_0_pp.C3 = 14'd 11685;
defparam Ur9_n_0_pp.C4 = 14'd 232;
defparam Ur9_n_0_pp.C5 = 14'd 13981;
defparam Ur9_n_0_pp.C6 = 14'd 14552;
defparam Ur9_n_0_pp.C7 = 14'd 11917;
defparam Ur9_n_0_pp.C8 = 14'd 2911;
defparam Ur9_n_0_pp.C9 = 14'd 276;
defparam Ur9_n_0_pp.CA = 14'd 847;
defparam Ur9_n_0_pp.CB = 14'd 14596;
defparam Ur9_n_0_pp.CC = 14'd 3143;
defparam Ur9_n_0_pp.CD = 14'd 508;
defparam Ur9_n_0_pp.CE = 14'd 1079;
defparam Ur9_n_0_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_1_pp;
rom_lut_r_cen Ur9_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[1],sym_res_38_n[1],sym_res_37_n[1],sym_res_36_n[1] } ), .data_out( lut_val_9_n_1_pp[13:0]) ) ;
defparam Ur9_n_1_pp.DATA_WIDTH = 14;
defparam Ur9_n_1_pp.C0 = 14'd 0;
defparam Ur9_n_1_pp.C1 = 14'd 13749;
defparam Ur9_n_1_pp.C2 = 14'd 14320;
defparam Ur9_n_1_pp.C3 = 14'd 11685;
defparam Ur9_n_1_pp.C4 = 14'd 232;
defparam Ur9_n_1_pp.C5 = 14'd 13981;
defparam Ur9_n_1_pp.C6 = 14'd 14552;
defparam Ur9_n_1_pp.C7 = 14'd 11917;
defparam Ur9_n_1_pp.C8 = 14'd 2911;
defparam Ur9_n_1_pp.C9 = 14'd 276;
defparam Ur9_n_1_pp.CA = 14'd 847;
defparam Ur9_n_1_pp.CB = 14'd 14596;
defparam Ur9_n_1_pp.CC = 14'd 3143;
defparam Ur9_n_1_pp.CD = 14'd 508;
defparam Ur9_n_1_pp.CE = 14'd 1079;
defparam Ur9_n_1_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_2_pp;
rom_lut_r_cen Ur9_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[2],sym_res_38_n[2],sym_res_37_n[2],sym_res_36_n[2] } ), .data_out( lut_val_9_n_2_pp[13:0]) ) ;
defparam Ur9_n_2_pp.DATA_WIDTH = 14;
defparam Ur9_n_2_pp.C0 = 14'd 0;
defparam Ur9_n_2_pp.C1 = 14'd 13749;
defparam Ur9_n_2_pp.C2 = 14'd 14320;
defparam Ur9_n_2_pp.C3 = 14'd 11685;
defparam Ur9_n_2_pp.C4 = 14'd 232;
defparam Ur9_n_2_pp.C5 = 14'd 13981;
defparam Ur9_n_2_pp.C6 = 14'd 14552;
defparam Ur9_n_2_pp.C7 = 14'd 11917;
defparam Ur9_n_2_pp.C8 = 14'd 2911;
defparam Ur9_n_2_pp.C9 = 14'd 276;
defparam Ur9_n_2_pp.CA = 14'd 847;
defparam Ur9_n_2_pp.CB = 14'd 14596;
defparam Ur9_n_2_pp.CC = 14'd 3143;
defparam Ur9_n_2_pp.CD = 14'd 508;
defparam Ur9_n_2_pp.CE = 14'd 1079;
defparam Ur9_n_2_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_3_pp;
rom_lut_r_cen Ur9_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[3],sym_res_38_n[3],sym_res_37_n[3],sym_res_36_n[3] } ), .data_out( lut_val_9_n_3_pp[13:0]) ) ;
defparam Ur9_n_3_pp.DATA_WIDTH = 14;
defparam Ur9_n_3_pp.C0 = 14'd 0;
defparam Ur9_n_3_pp.C1 = 14'd 13749;
defparam Ur9_n_3_pp.C2 = 14'd 14320;
defparam Ur9_n_3_pp.C3 = 14'd 11685;
defparam Ur9_n_3_pp.C4 = 14'd 232;
defparam Ur9_n_3_pp.C5 = 14'd 13981;
defparam Ur9_n_3_pp.C6 = 14'd 14552;
defparam Ur9_n_3_pp.C7 = 14'd 11917;
defparam Ur9_n_3_pp.C8 = 14'd 2911;
defparam Ur9_n_3_pp.C9 = 14'd 276;
defparam Ur9_n_3_pp.CA = 14'd 847;
defparam Ur9_n_3_pp.CB = 14'd 14596;
defparam Ur9_n_3_pp.CC = 14'd 3143;
defparam Ur9_n_3_pp.CD = 14'd 508;
defparam Ur9_n_3_pp.CE = 14'd 1079;
defparam Ur9_n_3_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_4_pp;
rom_lut_r_cen Ur9_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[4],sym_res_38_n[4],sym_res_37_n[4],sym_res_36_n[4] } ), .data_out( lut_val_9_n_4_pp[13:0]) ) ;
defparam Ur9_n_4_pp.DATA_WIDTH = 14;
defparam Ur9_n_4_pp.C0 = 14'd 0;
defparam Ur9_n_4_pp.C1 = 14'd 13749;
defparam Ur9_n_4_pp.C2 = 14'd 14320;
defparam Ur9_n_4_pp.C3 = 14'd 11685;
defparam Ur9_n_4_pp.C4 = 14'd 232;
defparam Ur9_n_4_pp.C5 = 14'd 13981;
defparam Ur9_n_4_pp.C6 = 14'd 14552;
defparam Ur9_n_4_pp.C7 = 14'd 11917;
defparam Ur9_n_4_pp.C8 = 14'd 2911;
defparam Ur9_n_4_pp.C9 = 14'd 276;
defparam Ur9_n_4_pp.CA = 14'd 847;
defparam Ur9_n_4_pp.CB = 14'd 14596;
defparam Ur9_n_4_pp.CC = 14'd 3143;
defparam Ur9_n_4_pp.CD = 14'd 508;
defparam Ur9_n_4_pp.CE = 14'd 1079;
defparam Ur9_n_4_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_5_pp;
rom_lut_r_cen Ur9_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[5],sym_res_38_n[5],sym_res_37_n[5],sym_res_36_n[5] } ), .data_out( lut_val_9_n_5_pp[13:0]) ) ;
defparam Ur9_n_5_pp.DATA_WIDTH = 14;
defparam Ur9_n_5_pp.C0 = 14'd 0;
defparam Ur9_n_5_pp.C1 = 14'd 13749;
defparam Ur9_n_5_pp.C2 = 14'd 14320;
defparam Ur9_n_5_pp.C3 = 14'd 11685;
defparam Ur9_n_5_pp.C4 = 14'd 232;
defparam Ur9_n_5_pp.C5 = 14'd 13981;
defparam Ur9_n_5_pp.C6 = 14'd 14552;
defparam Ur9_n_5_pp.C7 = 14'd 11917;
defparam Ur9_n_5_pp.C8 = 14'd 2911;
defparam Ur9_n_5_pp.C9 = 14'd 276;
defparam Ur9_n_5_pp.CA = 14'd 847;
defparam Ur9_n_5_pp.CB = 14'd 14596;
defparam Ur9_n_5_pp.CC = 14'd 3143;
defparam Ur9_n_5_pp.CD = 14'd 508;
defparam Ur9_n_5_pp.CE = 14'd 1079;
defparam Ur9_n_5_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_6_pp;
rom_lut_r_cen Ur9_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[6],sym_res_38_n[6],sym_res_37_n[6],sym_res_36_n[6] } ), .data_out( lut_val_9_n_6_pp[13:0]) ) ;
defparam Ur9_n_6_pp.DATA_WIDTH = 14;
defparam Ur9_n_6_pp.C0 = 14'd 0;
defparam Ur9_n_6_pp.C1 = 14'd 13749;
defparam Ur9_n_6_pp.C2 = 14'd 14320;
defparam Ur9_n_6_pp.C3 = 14'd 11685;
defparam Ur9_n_6_pp.C4 = 14'd 232;
defparam Ur9_n_6_pp.C5 = 14'd 13981;
defparam Ur9_n_6_pp.C6 = 14'd 14552;
defparam Ur9_n_6_pp.C7 = 14'd 11917;
defparam Ur9_n_6_pp.C8 = 14'd 2911;
defparam Ur9_n_6_pp.C9 = 14'd 276;
defparam Ur9_n_6_pp.CA = 14'd 847;
defparam Ur9_n_6_pp.CB = 14'd 14596;
defparam Ur9_n_6_pp.CC = 14'd 3143;
defparam Ur9_n_6_pp.CD = 14'd 508;
defparam Ur9_n_6_pp.CE = 14'd 1079;
defparam Ur9_n_6_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_7_pp;
rom_lut_r_cen Ur9_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[7],sym_res_38_n[7],sym_res_37_n[7],sym_res_36_n[7] } ), .data_out( lut_val_9_n_7_pp[13:0]) ) ;
defparam Ur9_n_7_pp.DATA_WIDTH = 14;
defparam Ur9_n_7_pp.C0 = 14'd 0;
defparam Ur9_n_7_pp.C1 = 14'd 13749;
defparam Ur9_n_7_pp.C2 = 14'd 14320;
defparam Ur9_n_7_pp.C3 = 14'd 11685;
defparam Ur9_n_7_pp.C4 = 14'd 232;
defparam Ur9_n_7_pp.C5 = 14'd 13981;
defparam Ur9_n_7_pp.C6 = 14'd 14552;
defparam Ur9_n_7_pp.C7 = 14'd 11917;
defparam Ur9_n_7_pp.C8 = 14'd 2911;
defparam Ur9_n_7_pp.C9 = 14'd 276;
defparam Ur9_n_7_pp.CA = 14'd 847;
defparam Ur9_n_7_pp.CB = 14'd 14596;
defparam Ur9_n_7_pp.CC = 14'd 3143;
defparam Ur9_n_7_pp.CD = 14'd 508;
defparam Ur9_n_7_pp.CE = 14'd 1079;
defparam Ur9_n_7_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_8_pp;
rom_lut_r_cen Ur9_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[8],sym_res_38_n[8],sym_res_37_n[8],sym_res_36_n[8] } ), .data_out( lut_val_9_n_8_pp[13:0]) ) ;
defparam Ur9_n_8_pp.DATA_WIDTH = 14;
defparam Ur9_n_8_pp.C0 = 14'd 0;
defparam Ur9_n_8_pp.C1 = 14'd 13749;
defparam Ur9_n_8_pp.C2 = 14'd 14320;
defparam Ur9_n_8_pp.C3 = 14'd 11685;
defparam Ur9_n_8_pp.C4 = 14'd 232;
defparam Ur9_n_8_pp.C5 = 14'd 13981;
defparam Ur9_n_8_pp.C6 = 14'd 14552;
defparam Ur9_n_8_pp.C7 = 14'd 11917;
defparam Ur9_n_8_pp.C8 = 14'd 2911;
defparam Ur9_n_8_pp.C9 = 14'd 276;
defparam Ur9_n_8_pp.CA = 14'd 847;
defparam Ur9_n_8_pp.CB = 14'd 14596;
defparam Ur9_n_8_pp.CC = 14'd 3143;
defparam Ur9_n_8_pp.CD = 14'd 508;
defparam Ur9_n_8_pp.CE = 14'd 1079;
defparam Ur9_n_8_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_9_pp;
rom_lut_r_cen Ur9_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[9],sym_res_38_n[9],sym_res_37_n[9],sym_res_36_n[9] } ), .data_out( lut_val_9_n_9_pp[13:0]) ) ;
defparam Ur9_n_9_pp.DATA_WIDTH = 14;
defparam Ur9_n_9_pp.C0 = 14'd 0;
defparam Ur9_n_9_pp.C1 = 14'd 13749;
defparam Ur9_n_9_pp.C2 = 14'd 14320;
defparam Ur9_n_9_pp.C3 = 14'd 11685;
defparam Ur9_n_9_pp.C4 = 14'd 232;
defparam Ur9_n_9_pp.C5 = 14'd 13981;
defparam Ur9_n_9_pp.C6 = 14'd 14552;
defparam Ur9_n_9_pp.C7 = 14'd 11917;
defparam Ur9_n_9_pp.C8 = 14'd 2911;
defparam Ur9_n_9_pp.C9 = 14'd 276;
defparam Ur9_n_9_pp.CA = 14'd 847;
defparam Ur9_n_9_pp.CB = 14'd 14596;
defparam Ur9_n_9_pp.CC = 14'd 3143;
defparam Ur9_n_9_pp.CD = 14'd 508;
defparam Ur9_n_9_pp.CE = 14'd 1079;
defparam Ur9_n_9_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_10_pp;
rom_lut_r_cen Ur9_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[10],sym_res_38_n[10],sym_res_37_n[10],sym_res_36_n[10] } ), .data_out( lut_val_9_n_10_pp[13:0]) ) ;
defparam Ur9_n_10_pp.DATA_WIDTH = 14;
defparam Ur9_n_10_pp.C0 = 14'd 0;
defparam Ur9_n_10_pp.C1 = 14'd 13749;
defparam Ur9_n_10_pp.C2 = 14'd 14320;
defparam Ur9_n_10_pp.C3 = 14'd 11685;
defparam Ur9_n_10_pp.C4 = 14'd 232;
defparam Ur9_n_10_pp.C5 = 14'd 13981;
defparam Ur9_n_10_pp.C6 = 14'd 14552;
defparam Ur9_n_10_pp.C7 = 14'd 11917;
defparam Ur9_n_10_pp.C8 = 14'd 2911;
defparam Ur9_n_10_pp.C9 = 14'd 276;
defparam Ur9_n_10_pp.CA = 14'd 847;
defparam Ur9_n_10_pp.CB = 14'd 14596;
defparam Ur9_n_10_pp.CC = 14'd 3143;
defparam Ur9_n_10_pp.CD = 14'd 508;
defparam Ur9_n_10_pp.CE = 14'd 1079;
defparam Ur9_n_10_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_11_pp;
rom_lut_r_cen Ur9_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[11],sym_res_38_n[11],sym_res_37_n[11],sym_res_36_n[11] } ), .data_out( lut_val_9_n_11_pp[13:0]) ) ;
defparam Ur9_n_11_pp.DATA_WIDTH = 14;
defparam Ur9_n_11_pp.C0 = 14'd 0;
defparam Ur9_n_11_pp.C1 = 14'd 13749;
defparam Ur9_n_11_pp.C2 = 14'd 14320;
defparam Ur9_n_11_pp.C3 = 14'd 11685;
defparam Ur9_n_11_pp.C4 = 14'd 232;
defparam Ur9_n_11_pp.C5 = 14'd 13981;
defparam Ur9_n_11_pp.C6 = 14'd 14552;
defparam Ur9_n_11_pp.C7 = 14'd 11917;
defparam Ur9_n_11_pp.C8 = 14'd 2911;
defparam Ur9_n_11_pp.C9 = 14'd 276;
defparam Ur9_n_11_pp.CA = 14'd 847;
defparam Ur9_n_11_pp.CB = 14'd 14596;
defparam Ur9_n_11_pp.CC = 14'd 3143;
defparam Ur9_n_11_pp.CD = 14'd 508;
defparam Ur9_n_11_pp.CE = 14'd 1079;
defparam Ur9_n_11_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_12_pp;
rom_lut_r_cen Ur9_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[12],sym_res_38_n[12],sym_res_37_n[12],sym_res_36_n[12] } ), .data_out( lut_val_9_n_12_pp[13:0]) ) ;
defparam Ur9_n_12_pp.DATA_WIDTH = 14;
defparam Ur9_n_12_pp.C0 = 14'd 0;
defparam Ur9_n_12_pp.C1 = 14'd 13749;
defparam Ur9_n_12_pp.C2 = 14'd 14320;
defparam Ur9_n_12_pp.C3 = 14'd 11685;
defparam Ur9_n_12_pp.C4 = 14'd 232;
defparam Ur9_n_12_pp.C5 = 14'd 13981;
defparam Ur9_n_12_pp.C6 = 14'd 14552;
defparam Ur9_n_12_pp.C7 = 14'd 11917;
defparam Ur9_n_12_pp.C8 = 14'd 2911;
defparam Ur9_n_12_pp.C9 = 14'd 276;
defparam Ur9_n_12_pp.CA = 14'd 847;
defparam Ur9_n_12_pp.CB = 14'd 14596;
defparam Ur9_n_12_pp.CC = 14'd 3143;
defparam Ur9_n_12_pp.CD = 14'd 508;
defparam Ur9_n_12_pp.CE = 14'd 1079;
defparam Ur9_n_12_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_13_pp;
rom_lut_r_cen Ur9_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[13],sym_res_38_n[13],sym_res_37_n[13],sym_res_36_n[13] } ), .data_out( lut_val_9_n_13_pp[13:0]) ) ;
defparam Ur9_n_13_pp.DATA_WIDTH = 14;
defparam Ur9_n_13_pp.C0 = 14'd 0;
defparam Ur9_n_13_pp.C1 = 14'd 13749;
defparam Ur9_n_13_pp.C2 = 14'd 14320;
defparam Ur9_n_13_pp.C3 = 14'd 11685;
defparam Ur9_n_13_pp.C4 = 14'd 232;
defparam Ur9_n_13_pp.C5 = 14'd 13981;
defparam Ur9_n_13_pp.C6 = 14'd 14552;
defparam Ur9_n_13_pp.C7 = 14'd 11917;
defparam Ur9_n_13_pp.C8 = 14'd 2911;
defparam Ur9_n_13_pp.C9 = 14'd 276;
defparam Ur9_n_13_pp.CA = 14'd 847;
defparam Ur9_n_13_pp.CB = 14'd 14596;
defparam Ur9_n_13_pp.CC = 14'd 3143;
defparam Ur9_n_13_pp.CD = 14'd 508;
defparam Ur9_n_13_pp.CE = 14'd 1079;
defparam Ur9_n_13_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_14_pp;
rom_lut_r_cen Ur9_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[14],sym_res_38_n[14],sym_res_37_n[14],sym_res_36_n[14] } ), .data_out( lut_val_9_n_14_pp[13:0]) ) ;
defparam Ur9_n_14_pp.DATA_WIDTH = 14;
defparam Ur9_n_14_pp.C0 = 14'd 0;
defparam Ur9_n_14_pp.C1 = 14'd 13749;
defparam Ur9_n_14_pp.C2 = 14'd 14320;
defparam Ur9_n_14_pp.C3 = 14'd 11685;
defparam Ur9_n_14_pp.C4 = 14'd 232;
defparam Ur9_n_14_pp.C5 = 14'd 13981;
defparam Ur9_n_14_pp.C6 = 14'd 14552;
defparam Ur9_n_14_pp.C7 = 14'd 11917;
defparam Ur9_n_14_pp.C8 = 14'd 2911;
defparam Ur9_n_14_pp.C9 = 14'd 276;
defparam Ur9_n_14_pp.CA = 14'd 847;
defparam Ur9_n_14_pp.CB = 14'd 14596;
defparam Ur9_n_14_pp.CC = 14'd 3143;
defparam Ur9_n_14_pp.CD = 14'd 508;
defparam Ur9_n_14_pp.CE = 14'd 1079;
defparam Ur9_n_14_pp.CF = 14'd 14828;
wire [13:0] lut_val_9_n_15_pp;
rom_lut_r_cen Ur9_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_39_n[15],sym_res_38_n[15],sym_res_37_n[15],sym_res_36_n[15] } ), .data_out( lut_val_9_n_15_pp[13:0]) ) ;
defparam Ur9_n_15_pp.DATA_WIDTH = 14;
defparam Ur9_n_15_pp.C0 = 14'd 0;
defparam Ur9_n_15_pp.C1 = 14'd 13749;
defparam Ur9_n_15_pp.C2 = 14'd 14320;
defparam Ur9_n_15_pp.C3 = 14'd 11685;
defparam Ur9_n_15_pp.C4 = 14'd 232;
defparam Ur9_n_15_pp.C5 = 14'd 13981;
defparam Ur9_n_15_pp.C6 = 14'd 14552;
defparam Ur9_n_15_pp.C7 = 14'd 11917;
defparam Ur9_n_15_pp.C8 = 14'd 2911;
defparam Ur9_n_15_pp.C9 = 14'd 276;
defparam Ur9_n_15_pp.CA = 14'd 847;
defparam Ur9_n_15_pp.CB = 14'd 14596;
defparam Ur9_n_15_pp.CC = 14'd 3143;
defparam Ur9_n_15_pp.CD = 14'd 508;
defparam Ur9_n_15_pp.CE = 14'd 1079;
defparam Ur9_n_15_pp.CF = 14'd 14828;
wire [13:0] lut_val_10_n_0_pp;
rom_lut_r_cen Ur10_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[0] } ), .data_out( lut_val_10_n_0_pp[12:0]) ) ;
defparam Ur10_n_0_pp.DATA_WIDTH = 13;
defparam Ur10_n_0_pp.C0 = 13'd 0;
defparam Ur10_n_0_pp.C1 = 13'd 4095;
defparam Ur10_n_0_pp.C2 = 13'd 0;
defparam Ur10_n_0_pp.C3 = 13'd 4095;
defparam Ur10_n_0_pp.C4 = 13'd 0;
defparam Ur10_n_0_pp.C5 = 13'd 4095;
defparam Ur10_n_0_pp.C6 = 13'd 0;
defparam Ur10_n_0_pp.C7 = 13'd 4095;
defparam Ur10_n_0_pp.C8 = 13'd 0;
defparam Ur10_n_0_pp.C9 = 13'd 4095;
defparam Ur10_n_0_pp.CA = 13'd 0;
defparam Ur10_n_0_pp.CB = 13'd 4095;
defparam Ur10_n_0_pp.CC = 13'd 0;
defparam Ur10_n_0_pp.CD = 13'd 4095;
defparam Ur10_n_0_pp.CE = 13'd 0;
defparam Ur10_n_0_pp.CF = 13'd 4095;
assign lut_val_10_n_0_pp[13] = lut_val_10_n_0_pp[12];
wire [13:0] lut_val_10_n_1_pp;
rom_lut_r_cen Ur10_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[1] } ), .data_out( lut_val_10_n_1_pp[12:0]) ) ;
defparam Ur10_n_1_pp.DATA_WIDTH = 13;
defparam Ur10_n_1_pp.C0 = 13'd 0;
defparam Ur10_n_1_pp.C1 = 13'd 4095;
defparam Ur10_n_1_pp.C2 = 13'd 0;
defparam Ur10_n_1_pp.C3 = 13'd 4095;
defparam Ur10_n_1_pp.C4 = 13'd 0;
defparam Ur10_n_1_pp.C5 = 13'd 4095;
defparam Ur10_n_1_pp.C6 = 13'd 0;
defparam Ur10_n_1_pp.C7 = 13'd 4095;
defparam Ur10_n_1_pp.C8 = 13'd 0;
defparam Ur10_n_1_pp.C9 = 13'd 4095;
defparam Ur10_n_1_pp.CA = 13'd 0;
defparam Ur10_n_1_pp.CB = 13'd 4095;
defparam Ur10_n_1_pp.CC = 13'd 0;
defparam Ur10_n_1_pp.CD = 13'd 4095;
defparam Ur10_n_1_pp.CE = 13'd 0;
defparam Ur10_n_1_pp.CF = 13'd 4095;
assign lut_val_10_n_1_pp[13] = lut_val_10_n_1_pp[12];
wire [13:0] lut_val_10_n_2_pp;
rom_lut_r_cen Ur10_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[2] } ), .data_out( lut_val_10_n_2_pp[12:0]) ) ;
defparam Ur10_n_2_pp.DATA_WIDTH = 13;
defparam Ur10_n_2_pp.C0 = 13'd 0;
defparam Ur10_n_2_pp.C1 = 13'd 4095;
defparam Ur10_n_2_pp.C2 = 13'd 0;
defparam Ur10_n_2_pp.C3 = 13'd 4095;
defparam Ur10_n_2_pp.C4 = 13'd 0;
defparam Ur10_n_2_pp.C5 = 13'd 4095;
defparam Ur10_n_2_pp.C6 = 13'd 0;
defparam Ur10_n_2_pp.C7 = 13'd 4095;
defparam Ur10_n_2_pp.C8 = 13'd 0;
defparam Ur10_n_2_pp.C9 = 13'd 4095;
defparam Ur10_n_2_pp.CA = 13'd 0;
defparam Ur10_n_2_pp.CB = 13'd 4095;
defparam Ur10_n_2_pp.CC = 13'd 0;
defparam Ur10_n_2_pp.CD = 13'd 4095;
defparam Ur10_n_2_pp.CE = 13'd 0;
defparam Ur10_n_2_pp.CF = 13'd 4095;
assign lut_val_10_n_2_pp[13] = lut_val_10_n_2_pp[12];
wire [13:0] lut_val_10_n_3_pp;
rom_lut_r_cen Ur10_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[3] } ), .data_out( lut_val_10_n_3_pp[12:0]) ) ;
defparam Ur10_n_3_pp.DATA_WIDTH = 13;
defparam Ur10_n_3_pp.C0 = 13'd 0;
defparam Ur10_n_3_pp.C1 = 13'd 4095;
defparam Ur10_n_3_pp.C2 = 13'd 0;
defparam Ur10_n_3_pp.C3 = 13'd 4095;
defparam Ur10_n_3_pp.C4 = 13'd 0;
defparam Ur10_n_3_pp.C5 = 13'd 4095;
defparam Ur10_n_3_pp.C6 = 13'd 0;
defparam Ur10_n_3_pp.C7 = 13'd 4095;
defparam Ur10_n_3_pp.C8 = 13'd 0;
defparam Ur10_n_3_pp.C9 = 13'd 4095;
defparam Ur10_n_3_pp.CA = 13'd 0;
defparam Ur10_n_3_pp.CB = 13'd 4095;
defparam Ur10_n_3_pp.CC = 13'd 0;
defparam Ur10_n_3_pp.CD = 13'd 4095;
defparam Ur10_n_3_pp.CE = 13'd 0;
defparam Ur10_n_3_pp.CF = 13'd 4095;
assign lut_val_10_n_3_pp[13] = lut_val_10_n_3_pp[12];
wire [13:0] lut_val_10_n_4_pp;
rom_lut_r_cen Ur10_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[4] } ), .data_out( lut_val_10_n_4_pp[12:0]) ) ;
defparam Ur10_n_4_pp.DATA_WIDTH = 13;
defparam Ur10_n_4_pp.C0 = 13'd 0;
defparam Ur10_n_4_pp.C1 = 13'd 4095;
defparam Ur10_n_4_pp.C2 = 13'd 0;
defparam Ur10_n_4_pp.C3 = 13'd 4095;
defparam Ur10_n_4_pp.C4 = 13'd 0;
defparam Ur10_n_4_pp.C5 = 13'd 4095;
defparam Ur10_n_4_pp.C6 = 13'd 0;
defparam Ur10_n_4_pp.C7 = 13'd 4095;
defparam Ur10_n_4_pp.C8 = 13'd 0;
defparam Ur10_n_4_pp.C9 = 13'd 4095;
defparam Ur10_n_4_pp.CA = 13'd 0;
defparam Ur10_n_4_pp.CB = 13'd 4095;
defparam Ur10_n_4_pp.CC = 13'd 0;
defparam Ur10_n_4_pp.CD = 13'd 4095;
defparam Ur10_n_4_pp.CE = 13'd 0;
defparam Ur10_n_4_pp.CF = 13'd 4095;
assign lut_val_10_n_4_pp[13] = lut_val_10_n_4_pp[12];
wire [13:0] lut_val_10_n_5_pp;
rom_lut_r_cen Ur10_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[5] } ), .data_out( lut_val_10_n_5_pp[12:0]) ) ;
defparam Ur10_n_5_pp.DATA_WIDTH = 13;
defparam Ur10_n_5_pp.C0 = 13'd 0;
defparam Ur10_n_5_pp.C1 = 13'd 4095;
defparam Ur10_n_5_pp.C2 = 13'd 0;
defparam Ur10_n_5_pp.C3 = 13'd 4095;
defparam Ur10_n_5_pp.C4 = 13'd 0;
defparam Ur10_n_5_pp.C5 = 13'd 4095;
defparam Ur10_n_5_pp.C6 = 13'd 0;
defparam Ur10_n_5_pp.C7 = 13'd 4095;
defparam Ur10_n_5_pp.C8 = 13'd 0;
defparam Ur10_n_5_pp.C9 = 13'd 4095;
defparam Ur10_n_5_pp.CA = 13'd 0;
defparam Ur10_n_5_pp.CB = 13'd 4095;
defparam Ur10_n_5_pp.CC = 13'd 0;
defparam Ur10_n_5_pp.CD = 13'd 4095;
defparam Ur10_n_5_pp.CE = 13'd 0;
defparam Ur10_n_5_pp.CF = 13'd 4095;
assign lut_val_10_n_5_pp[13] = lut_val_10_n_5_pp[12];
wire [13:0] lut_val_10_n_6_pp;
rom_lut_r_cen Ur10_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[6] } ), .data_out( lut_val_10_n_6_pp[12:0]) ) ;
defparam Ur10_n_6_pp.DATA_WIDTH = 13;
defparam Ur10_n_6_pp.C0 = 13'd 0;
defparam Ur10_n_6_pp.C1 = 13'd 4095;
defparam Ur10_n_6_pp.C2 = 13'd 0;
defparam Ur10_n_6_pp.C3 = 13'd 4095;
defparam Ur10_n_6_pp.C4 = 13'd 0;
defparam Ur10_n_6_pp.C5 = 13'd 4095;
defparam Ur10_n_6_pp.C6 = 13'd 0;
defparam Ur10_n_6_pp.C7 = 13'd 4095;
defparam Ur10_n_6_pp.C8 = 13'd 0;
defparam Ur10_n_6_pp.C9 = 13'd 4095;
defparam Ur10_n_6_pp.CA = 13'd 0;
defparam Ur10_n_6_pp.CB = 13'd 4095;
defparam Ur10_n_6_pp.CC = 13'd 0;
defparam Ur10_n_6_pp.CD = 13'd 4095;
defparam Ur10_n_6_pp.CE = 13'd 0;
defparam Ur10_n_6_pp.CF = 13'd 4095;
assign lut_val_10_n_6_pp[13] = lut_val_10_n_6_pp[12];
wire [13:0] lut_val_10_n_7_pp;
rom_lut_r_cen Ur10_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[7] } ), .data_out( lut_val_10_n_7_pp[12:0]) ) ;
defparam Ur10_n_7_pp.DATA_WIDTH = 13;
defparam Ur10_n_7_pp.C0 = 13'd 0;
defparam Ur10_n_7_pp.C1 = 13'd 4095;
defparam Ur10_n_7_pp.C2 = 13'd 0;
defparam Ur10_n_7_pp.C3 = 13'd 4095;
defparam Ur10_n_7_pp.C4 = 13'd 0;
defparam Ur10_n_7_pp.C5 = 13'd 4095;
defparam Ur10_n_7_pp.C6 = 13'd 0;
defparam Ur10_n_7_pp.C7 = 13'd 4095;
defparam Ur10_n_7_pp.C8 = 13'd 0;
defparam Ur10_n_7_pp.C9 = 13'd 4095;
defparam Ur10_n_7_pp.CA = 13'd 0;
defparam Ur10_n_7_pp.CB = 13'd 4095;
defparam Ur10_n_7_pp.CC = 13'd 0;
defparam Ur10_n_7_pp.CD = 13'd 4095;
defparam Ur10_n_7_pp.CE = 13'd 0;
defparam Ur10_n_7_pp.CF = 13'd 4095;
assign lut_val_10_n_7_pp[13] = lut_val_10_n_7_pp[12];
wire [13:0] lut_val_10_n_8_pp;
rom_lut_r_cen Ur10_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[8] } ), .data_out( lut_val_10_n_8_pp[12:0]) ) ;
defparam Ur10_n_8_pp.DATA_WIDTH = 13;
defparam Ur10_n_8_pp.C0 = 13'd 0;
defparam Ur10_n_8_pp.C1 = 13'd 4095;
defparam Ur10_n_8_pp.C2 = 13'd 0;
defparam Ur10_n_8_pp.C3 = 13'd 4095;
defparam Ur10_n_8_pp.C4 = 13'd 0;
defparam Ur10_n_8_pp.C5 = 13'd 4095;
defparam Ur10_n_8_pp.C6 = 13'd 0;
defparam Ur10_n_8_pp.C7 = 13'd 4095;
defparam Ur10_n_8_pp.C8 = 13'd 0;
defparam Ur10_n_8_pp.C9 = 13'd 4095;
defparam Ur10_n_8_pp.CA = 13'd 0;
defparam Ur10_n_8_pp.CB = 13'd 4095;
defparam Ur10_n_8_pp.CC = 13'd 0;
defparam Ur10_n_8_pp.CD = 13'd 4095;
defparam Ur10_n_8_pp.CE = 13'd 0;
defparam Ur10_n_8_pp.CF = 13'd 4095;
assign lut_val_10_n_8_pp[13] = lut_val_10_n_8_pp[12];
wire [13:0] lut_val_10_n_9_pp;
rom_lut_r_cen Ur10_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[9] } ), .data_out( lut_val_10_n_9_pp[12:0]) ) ;
defparam Ur10_n_9_pp.DATA_WIDTH = 13;
defparam Ur10_n_9_pp.C0 = 13'd 0;
defparam Ur10_n_9_pp.C1 = 13'd 4095;
defparam Ur10_n_9_pp.C2 = 13'd 0;
defparam Ur10_n_9_pp.C3 = 13'd 4095;
defparam Ur10_n_9_pp.C4 = 13'd 0;
defparam Ur10_n_9_pp.C5 = 13'd 4095;
defparam Ur10_n_9_pp.C6 = 13'd 0;
defparam Ur10_n_9_pp.C7 = 13'd 4095;
defparam Ur10_n_9_pp.C8 = 13'd 0;
defparam Ur10_n_9_pp.C9 = 13'd 4095;
defparam Ur10_n_9_pp.CA = 13'd 0;
defparam Ur10_n_9_pp.CB = 13'd 4095;
defparam Ur10_n_9_pp.CC = 13'd 0;
defparam Ur10_n_9_pp.CD = 13'd 4095;
defparam Ur10_n_9_pp.CE = 13'd 0;
defparam Ur10_n_9_pp.CF = 13'd 4095;
assign lut_val_10_n_9_pp[13] = lut_val_10_n_9_pp[12];
wire [13:0] lut_val_10_n_10_pp;
rom_lut_r_cen Ur10_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[10] } ), .data_out( lut_val_10_n_10_pp[12:0]) ) ;
defparam Ur10_n_10_pp.DATA_WIDTH = 13;
defparam Ur10_n_10_pp.C0 = 13'd 0;
defparam Ur10_n_10_pp.C1 = 13'd 4095;
defparam Ur10_n_10_pp.C2 = 13'd 0;
defparam Ur10_n_10_pp.C3 = 13'd 4095;
defparam Ur10_n_10_pp.C4 = 13'd 0;
defparam Ur10_n_10_pp.C5 = 13'd 4095;
defparam Ur10_n_10_pp.C6 = 13'd 0;
defparam Ur10_n_10_pp.C7 = 13'd 4095;
defparam Ur10_n_10_pp.C8 = 13'd 0;
defparam Ur10_n_10_pp.C9 = 13'd 4095;
defparam Ur10_n_10_pp.CA = 13'd 0;
defparam Ur10_n_10_pp.CB = 13'd 4095;
defparam Ur10_n_10_pp.CC = 13'd 0;
defparam Ur10_n_10_pp.CD = 13'd 4095;
defparam Ur10_n_10_pp.CE = 13'd 0;
defparam Ur10_n_10_pp.CF = 13'd 4095;
assign lut_val_10_n_10_pp[13] = lut_val_10_n_10_pp[12];
wire [13:0] lut_val_10_n_11_pp;
rom_lut_r_cen Ur10_n_11_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[11] } ), .data_out( lut_val_10_n_11_pp[12:0]) ) ;
defparam Ur10_n_11_pp.DATA_WIDTH = 13;
defparam Ur10_n_11_pp.C0 = 13'd 0;
defparam Ur10_n_11_pp.C1 = 13'd 4095;
defparam Ur10_n_11_pp.C2 = 13'd 0;
defparam Ur10_n_11_pp.C3 = 13'd 4095;
defparam Ur10_n_11_pp.C4 = 13'd 0;
defparam Ur10_n_11_pp.C5 = 13'd 4095;
defparam Ur10_n_11_pp.C6 = 13'd 0;
defparam Ur10_n_11_pp.C7 = 13'd 4095;
defparam Ur10_n_11_pp.C8 = 13'd 0;
defparam Ur10_n_11_pp.C9 = 13'd 4095;
defparam Ur10_n_11_pp.CA = 13'd 0;
defparam Ur10_n_11_pp.CB = 13'd 4095;
defparam Ur10_n_11_pp.CC = 13'd 0;
defparam Ur10_n_11_pp.CD = 13'd 4095;
defparam Ur10_n_11_pp.CE = 13'd 0;
defparam Ur10_n_11_pp.CF = 13'd 4095;
assign lut_val_10_n_11_pp[13] = lut_val_10_n_11_pp[12];
wire [13:0] lut_val_10_n_12_pp;
rom_lut_r_cen Ur10_n_12_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[12] } ), .data_out( lut_val_10_n_12_pp[12:0]) ) ;
defparam Ur10_n_12_pp.DATA_WIDTH = 13;
defparam Ur10_n_12_pp.C0 = 13'd 0;
defparam Ur10_n_12_pp.C1 = 13'd 4095;
defparam Ur10_n_12_pp.C2 = 13'd 0;
defparam Ur10_n_12_pp.C3 = 13'd 4095;
defparam Ur10_n_12_pp.C4 = 13'd 0;
defparam Ur10_n_12_pp.C5 = 13'd 4095;
defparam Ur10_n_12_pp.C6 = 13'd 0;
defparam Ur10_n_12_pp.C7 = 13'd 4095;
defparam Ur10_n_12_pp.C8 = 13'd 0;
defparam Ur10_n_12_pp.C9 = 13'd 4095;
defparam Ur10_n_12_pp.CA = 13'd 0;
defparam Ur10_n_12_pp.CB = 13'd 4095;
defparam Ur10_n_12_pp.CC = 13'd 0;
defparam Ur10_n_12_pp.CD = 13'd 4095;
defparam Ur10_n_12_pp.CE = 13'd 0;
defparam Ur10_n_12_pp.CF = 13'd 4095;
assign lut_val_10_n_12_pp[13] = lut_val_10_n_12_pp[12];
wire [13:0] lut_val_10_n_13_pp;
rom_lut_r_cen Ur10_n_13_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[13] } ), .data_out( lut_val_10_n_13_pp[12:0]) ) ;
defparam Ur10_n_13_pp.DATA_WIDTH = 13;
defparam Ur10_n_13_pp.C0 = 13'd 0;
defparam Ur10_n_13_pp.C1 = 13'd 4095;
defparam Ur10_n_13_pp.C2 = 13'd 0;
defparam Ur10_n_13_pp.C3 = 13'd 4095;
defparam Ur10_n_13_pp.C4 = 13'd 0;
defparam Ur10_n_13_pp.C5 = 13'd 4095;
defparam Ur10_n_13_pp.C6 = 13'd 0;
defparam Ur10_n_13_pp.C7 = 13'd 4095;
defparam Ur10_n_13_pp.C8 = 13'd 0;
defparam Ur10_n_13_pp.C9 = 13'd 4095;
defparam Ur10_n_13_pp.CA = 13'd 0;
defparam Ur10_n_13_pp.CB = 13'd 4095;
defparam Ur10_n_13_pp.CC = 13'd 0;
defparam Ur10_n_13_pp.CD = 13'd 4095;
defparam Ur10_n_13_pp.CE = 13'd 0;
defparam Ur10_n_13_pp.CF = 13'd 4095;
assign lut_val_10_n_13_pp[13] = lut_val_10_n_13_pp[12];
wire [13:0] lut_val_10_n_14_pp;
rom_lut_r_cen Ur10_n_14_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[14] } ), .data_out( lut_val_10_n_14_pp[12:0]) ) ;
defparam Ur10_n_14_pp.DATA_WIDTH = 13;
defparam Ur10_n_14_pp.C0 = 13'd 0;
defparam Ur10_n_14_pp.C1 = 13'd 4095;
defparam Ur10_n_14_pp.C2 = 13'd 0;
defparam Ur10_n_14_pp.C3 = 13'd 4095;
defparam Ur10_n_14_pp.C4 = 13'd 0;
defparam Ur10_n_14_pp.C5 = 13'd 4095;
defparam Ur10_n_14_pp.C6 = 13'd 0;
defparam Ur10_n_14_pp.C7 = 13'd 4095;
defparam Ur10_n_14_pp.C8 = 13'd 0;
defparam Ur10_n_14_pp.C9 = 13'd 4095;
defparam Ur10_n_14_pp.CA = 13'd 0;
defparam Ur10_n_14_pp.CB = 13'd 4095;
defparam Ur10_n_14_pp.CC = 13'd 0;
defparam Ur10_n_14_pp.CD = 13'd 4095;
defparam Ur10_n_14_pp.CE = 13'd 0;
defparam Ur10_n_14_pp.CF = 13'd 4095;
assign lut_val_10_n_14_pp[13] = lut_val_10_n_14_pp[12];
wire [13:0] lut_val_10_n_15_pp;
rom_lut_r_cen Ur10_n_15_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {addr_low,addr_low,addr_low,sym_res_40_n[15] } ), .data_out( lut_val_10_n_15_pp[12:0]) ) ;
defparam Ur10_n_15_pp.DATA_WIDTH = 13;
defparam Ur10_n_15_pp.C0 = 13'd 0;
defparam Ur10_n_15_pp.C1 = 13'd 4095;
defparam Ur10_n_15_pp.C2 = 13'd 0;
defparam Ur10_n_15_pp.C3 = 13'd 4095;
defparam Ur10_n_15_pp.C4 = 13'd 0;
defparam Ur10_n_15_pp.C5 = 13'd 4095;
defparam Ur10_n_15_pp.C6 = 13'd 0;
defparam Ur10_n_15_pp.C7 = 13'd 4095;
defparam Ur10_n_15_pp.C8 = 13'd 0;
defparam Ur10_n_15_pp.C9 = 13'd 4095;
defparam Ur10_n_15_pp.CA = 13'd 0;
defparam Ur10_n_15_pp.CB = 13'd 4095;
defparam Ur10_n_15_pp.CC = 13'd 0;
defparam Ur10_n_15_pp.CD = 13'd 4095;
defparam Ur10_n_15_pp.CE = 13'd 0;
defparam Ur10_n_15_pp.CF = 13'd 4095;
assign lut_val_10_n_15_pp[13] = lut_val_10_n_15_pp[12];
// ---- partial product adder tree ----
wire [28:0] lut_0_bit_0_fill;
wire [28:0] lut_0_bit_1_fill;
wire [28:0] lut_0_bit_2_fill;
wire [28:0] lut_0_bit_3_fill;
wire [28:0] lut_0_bit_4_fill;
wire [28:0] lut_0_bit_5_fill;
wire [28:0] lut_0_bit_6_fill;
wire [28:0] lut_0_bit_7_fill;
wire [28:0] lut_0_bit_8_fill;
wire [28:0] lut_0_bit_9_fill;
wire [28:0] lut_0_bit_10_fill;
wire [28:0] lut_0_bit_11_fill;
wire [28:0] lut_0_bit_12_fill;
wire [28:0] lut_0_bit_13_fill;
wire [28:0] lut_0_bit_14_fill;
wire [28:0] lut_0_bit_15_fill;
assign lut_0_bit_0_fill = {lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp[13], lut_val_0_n_0_pp };
assign lut_0_bit_1_fill = {lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp[13], lut_val_0_n_1_pp, 1'd0 };
assign lut_0_bit_2_fill = {lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp[13], lut_val_0_n_2_pp, 2'd0 };
assign lut_0_bit_3_fill = {lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp[13], lut_val_0_n_3_pp, 3'd0 };
assign lut_0_bit_4_fill = {lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp[13], lut_val_0_n_4_pp, 4'd0 };
assign lut_0_bit_5_fill = {lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp[13], lut_val_0_n_5_pp, 5'd0 };
assign lut_0_bit_6_fill = {lut_val_0_n_6_pp[13], lut_val_0_n_6_pp[13], lut_val_0_n_6_pp[13], lut_val_0_n_6_pp[13], lut_val_0_n_6_pp[13], lut_val_0_n_6_pp[13], lut_val_0_n_6_pp[13], lut_val_0_n_6_pp[13], lut_val_0_n_6_pp[13], lut_val_0_n_6_pp, 6'd0 };
assign lut_0_bit_7_fill = {lut_val_0_n_7_pp[13], lut_val_0_n_7_pp[13], lut_val_0_n_7_pp[13], lut_val_0_n_7_pp[13], lut_val_0_n_7_pp[13], lut_val_0_n_7_pp[13], lut_val_0_n_7_pp[13], lut_val_0_n_7_pp[13], lut_val_0_n_7_pp, 7'd0 };
assign lut_0_bit_8_fill = {lut_val_0_n_8_pp[13], lut_val_0_n_8_pp[13], lut_val_0_n_8_pp[13], lut_val_0_n_8_pp[13], lut_val_0_n_8_pp[13], lut_val_0_n_8_pp[13], lut_val_0_n_8_pp[13], lut_val_0_n_8_pp, 8'd0 };
assign lut_0_bit_9_fill = {lut_val_0_n_9_pp[13], lut_val_0_n_9_pp[13], lut_val_0_n_9_pp[13], lut_val_0_n_9_pp[13], lut_val_0_n_9_pp[13], lut_val_0_n_9_pp[13], lut_val_0_n_9_pp, 9'd0 };
assign lut_0_bit_10_fill = {lut_val_0_n_10_pp[13], lut_val_0_n_10_pp[13], lut_val_0_n_10_pp[13], lut_val_0_n_10_pp[13], lut_val_0_n_10_pp[13], lut_val_0_n_10_pp, 10'd0 };
assign lut_0_bit_11_fill = {lut_val_0_n_11_pp[13], lut_val_0_n_11_pp[13], lut_val_0_n_11_pp[13], lut_val_0_n_11_pp[13], lut_val_0_n_11_pp, 11'd0 };
assign lut_0_bit_12_fill = {lut_val_0_n_12_pp[13], lut_val_0_n_12_pp[13], lut_val_0_n_12_pp[13], lut_val_0_n_12_pp, 12'd0 };
assign lut_0_bit_13_fill = {lut_val_0_n_13_pp[13], lut_val_0_n_13_pp[13], lut_val_0_n_13_pp, 13'd0 };
assign lut_0_bit_14_fill = {lut_val_0_n_14_pp[13], lut_val_0_n_14_pp, 14'd0 };
assign lut_0_bit_15_fill = { lut_val_0_n_15_pp, 15'd0 };
wire [29:0] tree_0_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_0_fill), .bin(lut_0_bit_1_fill), .res(tree_0_pp_l_0_n_0_n) );
defparam Uadd_0_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_0_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_0_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_2_fill), .bin(lut_0_bit_3_fill), .res(tree_0_pp_l_0_n_1_n) );
defparam Uadd_0_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_0_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_0_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_4_fill), .bin(lut_0_bit_5_fill), .res(tree_0_pp_l_0_n_2_n) );
defparam Uadd_0_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_0_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_0_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_6_fill), .bin(lut_0_bit_7_fill), .res(tree_0_pp_l_0_n_3_n) );
defparam Uadd_0_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_0_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_0_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_8_fill), .bin(lut_0_bit_9_fill), .res(tree_0_pp_l_0_n_4_n) );
defparam Uadd_0_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_0_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_0_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_10_fill), .bin(lut_0_bit_11_fill), .res(tree_0_pp_l_0_n_5_n) );
defparam Uadd_0_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_0_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_0_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_12_fill), .bin(lut_0_bit_13_fill), .res(tree_0_pp_l_0_n_6_n) );
defparam Uadd_0_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_0_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_0_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_0_bit_14_fill), .bin(lut_0_bit_15_fill), .res(tree_0_pp_l_0_n_7_n) );
defparam Uadd_0_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_0_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_0_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_0_n), .bin(tree_0_pp_l_0_n_1_n), .res(tree_0_pp_l_1_n_0_n) );
defparam Uadd_0_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_0_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_0_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_2_n), .bin(tree_0_pp_l_0_n_3_n), .res(tree_0_pp_l_1_n_1_n) );
defparam Uadd_0_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_0_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_0_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_4_n), .bin(tree_0_pp_l_0_n_5_n), .res(tree_0_pp_l_1_n_2_n) );
defparam Uadd_0_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_0_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_0_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_6_n), .bin(tree_0_pp_l_0_n_7_n), .res(tree_0_pp_l_1_n_3_n) );
defparam Uadd_0_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_0_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_0_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_1_n_0_n), .bin(tree_0_pp_l_1_n_1_n), .res(tree_0_pp_l_2_n_0_n) );
defparam Uadd_0_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_0_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_0_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_1_n_2_n), .bin(tree_0_pp_l_1_n_3_n), .res(tree_0_pp_l_2_n_1_n) );
defparam Uadd_0_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_0_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_0_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_0_pp_l_2_n_0_n), .bin(tree_0_pp_l_2_n_1_n), .res(tree_0_pp_l_3_n_0_n) );
defparam Uadd_0_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_0_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_0_n;
assign lut_val_0_n=tree_0_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_1_bit_0_fill;
wire [28:0] lut_1_bit_1_fill;
wire [28:0] lut_1_bit_2_fill;
wire [28:0] lut_1_bit_3_fill;
wire [28:0] lut_1_bit_4_fill;
wire [28:0] lut_1_bit_5_fill;
wire [28:0] lut_1_bit_6_fill;
wire [28:0] lut_1_bit_7_fill;
wire [28:0] lut_1_bit_8_fill;
wire [28:0] lut_1_bit_9_fill;
wire [28:0] lut_1_bit_10_fill;
wire [28:0] lut_1_bit_11_fill;
wire [28:0] lut_1_bit_12_fill;
wire [28:0] lut_1_bit_13_fill;
wire [28:0] lut_1_bit_14_fill;
wire [28:0] lut_1_bit_15_fill;
assign lut_1_bit_0_fill = {lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp[13], lut_val_1_n_0_pp };
assign lut_1_bit_1_fill = {lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp[13], lut_val_1_n_1_pp, 1'd0 };
assign lut_1_bit_2_fill = {lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp[13], lut_val_1_n_2_pp, 2'd0 };
assign lut_1_bit_3_fill = {lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp[13], lut_val_1_n_3_pp, 3'd0 };
assign lut_1_bit_4_fill = {lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp[13], lut_val_1_n_4_pp, 4'd0 };
assign lut_1_bit_5_fill = {lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp[13], lut_val_1_n_5_pp, 5'd0 };
assign lut_1_bit_6_fill = {lut_val_1_n_6_pp[13], lut_val_1_n_6_pp[13], lut_val_1_n_6_pp[13], lut_val_1_n_6_pp[13], lut_val_1_n_6_pp[13], lut_val_1_n_6_pp[13], lut_val_1_n_6_pp[13], lut_val_1_n_6_pp[13], lut_val_1_n_6_pp[13], lut_val_1_n_6_pp, 6'd0 };
assign lut_1_bit_7_fill = {lut_val_1_n_7_pp[13], lut_val_1_n_7_pp[13], lut_val_1_n_7_pp[13], lut_val_1_n_7_pp[13], lut_val_1_n_7_pp[13], lut_val_1_n_7_pp[13], lut_val_1_n_7_pp[13], lut_val_1_n_7_pp[13], lut_val_1_n_7_pp, 7'd0 };
assign lut_1_bit_8_fill = {lut_val_1_n_8_pp[13], lut_val_1_n_8_pp[13], lut_val_1_n_8_pp[13], lut_val_1_n_8_pp[13], lut_val_1_n_8_pp[13], lut_val_1_n_8_pp[13], lut_val_1_n_8_pp[13], lut_val_1_n_8_pp, 8'd0 };
assign lut_1_bit_9_fill = {lut_val_1_n_9_pp[13], lut_val_1_n_9_pp[13], lut_val_1_n_9_pp[13], lut_val_1_n_9_pp[13], lut_val_1_n_9_pp[13], lut_val_1_n_9_pp[13], lut_val_1_n_9_pp, 9'd0 };
assign lut_1_bit_10_fill = {lut_val_1_n_10_pp[13], lut_val_1_n_10_pp[13], lut_val_1_n_10_pp[13], lut_val_1_n_10_pp[13], lut_val_1_n_10_pp[13], lut_val_1_n_10_pp, 10'd0 };
assign lut_1_bit_11_fill = {lut_val_1_n_11_pp[13], lut_val_1_n_11_pp[13], lut_val_1_n_11_pp[13], lut_val_1_n_11_pp[13], lut_val_1_n_11_pp, 11'd0 };
assign lut_1_bit_12_fill = {lut_val_1_n_12_pp[13], lut_val_1_n_12_pp[13], lut_val_1_n_12_pp[13], lut_val_1_n_12_pp, 12'd0 };
assign lut_1_bit_13_fill = {lut_val_1_n_13_pp[13], lut_val_1_n_13_pp[13], lut_val_1_n_13_pp, 13'd0 };
assign lut_1_bit_14_fill = {lut_val_1_n_14_pp[13], lut_val_1_n_14_pp, 14'd0 };
assign lut_1_bit_15_fill = { lut_val_1_n_15_pp, 15'd0 };
wire [29:0] tree_1_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_0_fill), .bin(lut_1_bit_1_fill), .res(tree_1_pp_l_0_n_0_n) );
defparam Uadd_1_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_1_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_1_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_2_fill), .bin(lut_1_bit_3_fill), .res(tree_1_pp_l_0_n_1_n) );
defparam Uadd_1_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_1_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_1_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_4_fill), .bin(lut_1_bit_5_fill), .res(tree_1_pp_l_0_n_2_n) );
defparam Uadd_1_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_1_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_1_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_6_fill), .bin(lut_1_bit_7_fill), .res(tree_1_pp_l_0_n_3_n) );
defparam Uadd_1_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_1_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_1_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_8_fill), .bin(lut_1_bit_9_fill), .res(tree_1_pp_l_0_n_4_n) );
defparam Uadd_1_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_1_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_1_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_10_fill), .bin(lut_1_bit_11_fill), .res(tree_1_pp_l_0_n_5_n) );
defparam Uadd_1_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_1_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_1_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_12_fill), .bin(lut_1_bit_13_fill), .res(tree_1_pp_l_0_n_6_n) );
defparam Uadd_1_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_1_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_1_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_1_bit_14_fill), .bin(lut_1_bit_15_fill), .res(tree_1_pp_l_0_n_7_n) );
defparam Uadd_1_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_1_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_1_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_0_n), .bin(tree_1_pp_l_0_n_1_n), .res(tree_1_pp_l_1_n_0_n) );
defparam Uadd_1_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_1_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_1_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_2_n), .bin(tree_1_pp_l_0_n_3_n), .res(tree_1_pp_l_1_n_1_n) );
defparam Uadd_1_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_1_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_1_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_4_n), .bin(tree_1_pp_l_0_n_5_n), .res(tree_1_pp_l_1_n_2_n) );
defparam Uadd_1_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_1_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_1_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_6_n), .bin(tree_1_pp_l_0_n_7_n), .res(tree_1_pp_l_1_n_3_n) );
defparam Uadd_1_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_1_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_1_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_1_n_0_n), .bin(tree_1_pp_l_1_n_1_n), .res(tree_1_pp_l_2_n_0_n) );
defparam Uadd_1_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_1_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_1_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_1_n_2_n), .bin(tree_1_pp_l_1_n_3_n), .res(tree_1_pp_l_2_n_1_n) );
defparam Uadd_1_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_1_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_1_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_1_pp_l_2_n_0_n), .bin(tree_1_pp_l_2_n_1_n), .res(tree_1_pp_l_3_n_0_n) );
defparam Uadd_1_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_1_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_1_n;
assign lut_val_1_n=tree_1_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_2_bit_0_fill;
wire [28:0] lut_2_bit_1_fill;
wire [28:0] lut_2_bit_2_fill;
wire [28:0] lut_2_bit_3_fill;
wire [28:0] lut_2_bit_4_fill;
wire [28:0] lut_2_bit_5_fill;
wire [28:0] lut_2_bit_6_fill;
wire [28:0] lut_2_bit_7_fill;
wire [28:0] lut_2_bit_8_fill;
wire [28:0] lut_2_bit_9_fill;
wire [28:0] lut_2_bit_10_fill;
wire [28:0] lut_2_bit_11_fill;
wire [28:0] lut_2_bit_12_fill;
wire [28:0] lut_2_bit_13_fill;
wire [28:0] lut_2_bit_14_fill;
wire [28:0] lut_2_bit_15_fill;
assign lut_2_bit_0_fill = {lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp[13], lut_val_2_n_0_pp };
assign lut_2_bit_1_fill = {lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp[13], lut_val_2_n_1_pp, 1'd0 };
assign lut_2_bit_2_fill = {lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp[13], lut_val_2_n_2_pp, 2'd0 };
assign lut_2_bit_3_fill = {lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp[13], lut_val_2_n_3_pp, 3'd0 };
assign lut_2_bit_4_fill = {lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp[13], lut_val_2_n_4_pp, 4'd0 };
assign lut_2_bit_5_fill = {lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp[13], lut_val_2_n_5_pp, 5'd0 };
assign lut_2_bit_6_fill = {lut_val_2_n_6_pp[13], lut_val_2_n_6_pp[13], lut_val_2_n_6_pp[13], lut_val_2_n_6_pp[13], lut_val_2_n_6_pp[13], lut_val_2_n_6_pp[13], lut_val_2_n_6_pp[13], lut_val_2_n_6_pp[13], lut_val_2_n_6_pp[13], lut_val_2_n_6_pp, 6'd0 };
assign lut_2_bit_7_fill = {lut_val_2_n_7_pp[13], lut_val_2_n_7_pp[13], lut_val_2_n_7_pp[13], lut_val_2_n_7_pp[13], lut_val_2_n_7_pp[13], lut_val_2_n_7_pp[13], lut_val_2_n_7_pp[13], lut_val_2_n_7_pp[13], lut_val_2_n_7_pp, 7'd0 };
assign lut_2_bit_8_fill = {lut_val_2_n_8_pp[13], lut_val_2_n_8_pp[13], lut_val_2_n_8_pp[13], lut_val_2_n_8_pp[13], lut_val_2_n_8_pp[13], lut_val_2_n_8_pp[13], lut_val_2_n_8_pp[13], lut_val_2_n_8_pp, 8'd0 };
assign lut_2_bit_9_fill = {lut_val_2_n_9_pp[13], lut_val_2_n_9_pp[13], lut_val_2_n_9_pp[13], lut_val_2_n_9_pp[13], lut_val_2_n_9_pp[13], lut_val_2_n_9_pp[13], lut_val_2_n_9_pp, 9'd0 };
assign lut_2_bit_10_fill = {lut_val_2_n_10_pp[13], lut_val_2_n_10_pp[13], lut_val_2_n_10_pp[13], lut_val_2_n_10_pp[13], lut_val_2_n_10_pp[13], lut_val_2_n_10_pp, 10'd0 };
assign lut_2_bit_11_fill = {lut_val_2_n_11_pp[13], lut_val_2_n_11_pp[13], lut_val_2_n_11_pp[13], lut_val_2_n_11_pp[13], lut_val_2_n_11_pp, 11'd0 };
assign lut_2_bit_12_fill = {lut_val_2_n_12_pp[13], lut_val_2_n_12_pp[13], lut_val_2_n_12_pp[13], lut_val_2_n_12_pp, 12'd0 };
assign lut_2_bit_13_fill = {lut_val_2_n_13_pp[13], lut_val_2_n_13_pp[13], lut_val_2_n_13_pp, 13'd0 };
assign lut_2_bit_14_fill = {lut_val_2_n_14_pp[13], lut_val_2_n_14_pp, 14'd0 };
assign lut_2_bit_15_fill = { lut_val_2_n_15_pp, 15'd0 };
wire [29:0] tree_2_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_0_fill), .bin(lut_2_bit_1_fill), .res(tree_2_pp_l_0_n_0_n) );
defparam Uadd_2_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_2_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_2_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_2_fill), .bin(lut_2_bit_3_fill), .res(tree_2_pp_l_0_n_1_n) );
defparam Uadd_2_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_2_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_2_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_4_fill), .bin(lut_2_bit_5_fill), .res(tree_2_pp_l_0_n_2_n) );
defparam Uadd_2_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_2_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_2_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_6_fill), .bin(lut_2_bit_7_fill), .res(tree_2_pp_l_0_n_3_n) );
defparam Uadd_2_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_2_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_2_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_8_fill), .bin(lut_2_bit_9_fill), .res(tree_2_pp_l_0_n_4_n) );
defparam Uadd_2_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_2_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_2_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_10_fill), .bin(lut_2_bit_11_fill), .res(tree_2_pp_l_0_n_5_n) );
defparam Uadd_2_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_2_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_2_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_12_fill), .bin(lut_2_bit_13_fill), .res(tree_2_pp_l_0_n_6_n) );
defparam Uadd_2_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_2_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_2_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_2_bit_14_fill), .bin(lut_2_bit_15_fill), .res(tree_2_pp_l_0_n_7_n) );
defparam Uadd_2_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_2_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_2_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_0_n_0_n), .bin(tree_2_pp_l_0_n_1_n), .res(tree_2_pp_l_1_n_0_n) );
defparam Uadd_2_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_2_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_2_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_2_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_0_n_2_n), .bin(tree_2_pp_l_0_n_3_n), .res(tree_2_pp_l_1_n_1_n) );
defparam Uadd_2_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_2_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_2_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_2_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_0_n_4_n), .bin(tree_2_pp_l_0_n_5_n), .res(tree_2_pp_l_1_n_2_n) );
defparam Uadd_2_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_2_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_2_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_2_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_0_n_6_n), .bin(tree_2_pp_l_0_n_7_n), .res(tree_2_pp_l_1_n_3_n) );
defparam Uadd_2_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_2_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_2_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_1_n_0_n), .bin(tree_2_pp_l_1_n_1_n), .res(tree_2_pp_l_2_n_0_n) );
defparam Uadd_2_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_2_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_2_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_2_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_1_n_2_n), .bin(tree_2_pp_l_1_n_3_n), .res(tree_2_pp_l_2_n_1_n) );
defparam Uadd_2_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_2_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_2_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_2_pp_l_2_n_0_n), .bin(tree_2_pp_l_2_n_1_n), .res(tree_2_pp_l_3_n_0_n) );
defparam Uadd_2_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_2_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_2_n;
assign lut_val_2_n=tree_2_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_3_bit_0_fill;
wire [28:0] lut_3_bit_1_fill;
wire [28:0] lut_3_bit_2_fill;
wire [28:0] lut_3_bit_3_fill;
wire [28:0] lut_3_bit_4_fill;
wire [28:0] lut_3_bit_5_fill;
wire [28:0] lut_3_bit_6_fill;
wire [28:0] lut_3_bit_7_fill;
wire [28:0] lut_3_bit_8_fill;
wire [28:0] lut_3_bit_9_fill;
wire [28:0] lut_3_bit_10_fill;
wire [28:0] lut_3_bit_11_fill;
wire [28:0] lut_3_bit_12_fill;
wire [28:0] lut_3_bit_13_fill;
wire [28:0] lut_3_bit_14_fill;
wire [28:0] lut_3_bit_15_fill;
assign lut_3_bit_0_fill = {lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp[13], lut_val_3_n_0_pp };
assign lut_3_bit_1_fill = {lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp[13], lut_val_3_n_1_pp, 1'd0 };
assign lut_3_bit_2_fill = {lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp[13], lut_val_3_n_2_pp, 2'd0 };
assign lut_3_bit_3_fill = {lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp[13], lut_val_3_n_3_pp, 3'd0 };
assign lut_3_bit_4_fill = {lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp[13], lut_val_3_n_4_pp, 4'd0 };
assign lut_3_bit_5_fill = {lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp[13], lut_val_3_n_5_pp, 5'd0 };
assign lut_3_bit_6_fill = {lut_val_3_n_6_pp[13], lut_val_3_n_6_pp[13], lut_val_3_n_6_pp[13], lut_val_3_n_6_pp[13], lut_val_3_n_6_pp[13], lut_val_3_n_6_pp[13], lut_val_3_n_6_pp[13], lut_val_3_n_6_pp[13], lut_val_3_n_6_pp[13], lut_val_3_n_6_pp, 6'd0 };
assign lut_3_bit_7_fill = {lut_val_3_n_7_pp[13], lut_val_3_n_7_pp[13], lut_val_3_n_7_pp[13], lut_val_3_n_7_pp[13], lut_val_3_n_7_pp[13], lut_val_3_n_7_pp[13], lut_val_3_n_7_pp[13], lut_val_3_n_7_pp[13], lut_val_3_n_7_pp, 7'd0 };
assign lut_3_bit_8_fill = {lut_val_3_n_8_pp[13], lut_val_3_n_8_pp[13], lut_val_3_n_8_pp[13], lut_val_3_n_8_pp[13], lut_val_3_n_8_pp[13], lut_val_3_n_8_pp[13], lut_val_3_n_8_pp[13], lut_val_3_n_8_pp, 8'd0 };
assign lut_3_bit_9_fill = {lut_val_3_n_9_pp[13], lut_val_3_n_9_pp[13], lut_val_3_n_9_pp[13], lut_val_3_n_9_pp[13], lut_val_3_n_9_pp[13], lut_val_3_n_9_pp[13], lut_val_3_n_9_pp, 9'd0 };
assign lut_3_bit_10_fill = {lut_val_3_n_10_pp[13], lut_val_3_n_10_pp[13], lut_val_3_n_10_pp[13], lut_val_3_n_10_pp[13], lut_val_3_n_10_pp[13], lut_val_3_n_10_pp, 10'd0 };
assign lut_3_bit_11_fill = {lut_val_3_n_11_pp[13], lut_val_3_n_11_pp[13], lut_val_3_n_11_pp[13], lut_val_3_n_11_pp[13], lut_val_3_n_11_pp, 11'd0 };
assign lut_3_bit_12_fill = {lut_val_3_n_12_pp[13], lut_val_3_n_12_pp[13], lut_val_3_n_12_pp[13], lut_val_3_n_12_pp, 12'd0 };
assign lut_3_bit_13_fill = {lut_val_3_n_13_pp[13], lut_val_3_n_13_pp[13], lut_val_3_n_13_pp, 13'd0 };
assign lut_3_bit_14_fill = {lut_val_3_n_14_pp[13], lut_val_3_n_14_pp, 14'd0 };
assign lut_3_bit_15_fill = { lut_val_3_n_15_pp, 15'd0 };
wire [29:0] tree_3_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_0_fill), .bin(lut_3_bit_1_fill), .res(tree_3_pp_l_0_n_0_n) );
defparam Uadd_3_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_3_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_3_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_2_fill), .bin(lut_3_bit_3_fill), .res(tree_3_pp_l_0_n_1_n) );
defparam Uadd_3_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_3_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_3_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_4_fill), .bin(lut_3_bit_5_fill), .res(tree_3_pp_l_0_n_2_n) );
defparam Uadd_3_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_3_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_3_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_6_fill), .bin(lut_3_bit_7_fill), .res(tree_3_pp_l_0_n_3_n) );
defparam Uadd_3_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_3_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_3_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_8_fill), .bin(lut_3_bit_9_fill), .res(tree_3_pp_l_0_n_4_n) );
defparam Uadd_3_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_3_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_3_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_10_fill), .bin(lut_3_bit_11_fill), .res(tree_3_pp_l_0_n_5_n) );
defparam Uadd_3_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_3_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_3_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_12_fill), .bin(lut_3_bit_13_fill), .res(tree_3_pp_l_0_n_6_n) );
defparam Uadd_3_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_3_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_3_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_3_bit_14_fill), .bin(lut_3_bit_15_fill), .res(tree_3_pp_l_0_n_7_n) );
defparam Uadd_3_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_3_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_3_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_0_n_0_n), .bin(tree_3_pp_l_0_n_1_n), .res(tree_3_pp_l_1_n_0_n) );
defparam Uadd_3_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_3_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_3_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_3_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_0_n_2_n), .bin(tree_3_pp_l_0_n_3_n), .res(tree_3_pp_l_1_n_1_n) );
defparam Uadd_3_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_3_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_3_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_3_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_0_n_4_n), .bin(tree_3_pp_l_0_n_5_n), .res(tree_3_pp_l_1_n_2_n) );
defparam Uadd_3_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_3_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_3_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_3_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_0_n_6_n), .bin(tree_3_pp_l_0_n_7_n), .res(tree_3_pp_l_1_n_3_n) );
defparam Uadd_3_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_3_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_3_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_1_n_0_n), .bin(tree_3_pp_l_1_n_1_n), .res(tree_3_pp_l_2_n_0_n) );
defparam Uadd_3_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_3_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_3_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_3_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_1_n_2_n), .bin(tree_3_pp_l_1_n_3_n), .res(tree_3_pp_l_2_n_1_n) );
defparam Uadd_3_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_3_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_3_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_3_pp_l_2_n_0_n), .bin(tree_3_pp_l_2_n_1_n), .res(tree_3_pp_l_3_n_0_n) );
defparam Uadd_3_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_3_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_3_n;
assign lut_val_3_n=tree_3_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_4_bit_0_fill;
wire [28:0] lut_4_bit_1_fill;
wire [28:0] lut_4_bit_2_fill;
wire [28:0] lut_4_bit_3_fill;
wire [28:0] lut_4_bit_4_fill;
wire [28:0] lut_4_bit_5_fill;
wire [28:0] lut_4_bit_6_fill;
wire [28:0] lut_4_bit_7_fill;
wire [28:0] lut_4_bit_8_fill;
wire [28:0] lut_4_bit_9_fill;
wire [28:0] lut_4_bit_10_fill;
wire [28:0] lut_4_bit_11_fill;
wire [28:0] lut_4_bit_12_fill;
wire [28:0] lut_4_bit_13_fill;
wire [28:0] lut_4_bit_14_fill;
wire [28:0] lut_4_bit_15_fill;
assign lut_4_bit_0_fill = {lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp[13], lut_val_4_n_0_pp };
assign lut_4_bit_1_fill = {lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp[13], lut_val_4_n_1_pp, 1'd0 };
assign lut_4_bit_2_fill = {lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp[13], lut_val_4_n_2_pp, 2'd0 };
assign lut_4_bit_3_fill = {lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp[13], lut_val_4_n_3_pp, 3'd0 };
assign lut_4_bit_4_fill = {lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp[13], lut_val_4_n_4_pp, 4'd0 };
assign lut_4_bit_5_fill = {lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp[13], lut_val_4_n_5_pp, 5'd0 };
assign lut_4_bit_6_fill = {lut_val_4_n_6_pp[13], lut_val_4_n_6_pp[13], lut_val_4_n_6_pp[13], lut_val_4_n_6_pp[13], lut_val_4_n_6_pp[13], lut_val_4_n_6_pp[13], lut_val_4_n_6_pp[13], lut_val_4_n_6_pp[13], lut_val_4_n_6_pp[13], lut_val_4_n_6_pp, 6'd0 };
assign lut_4_bit_7_fill = {lut_val_4_n_7_pp[13], lut_val_4_n_7_pp[13], lut_val_4_n_7_pp[13], lut_val_4_n_7_pp[13], lut_val_4_n_7_pp[13], lut_val_4_n_7_pp[13], lut_val_4_n_7_pp[13], lut_val_4_n_7_pp[13], lut_val_4_n_7_pp, 7'd0 };
assign lut_4_bit_8_fill = {lut_val_4_n_8_pp[13], lut_val_4_n_8_pp[13], lut_val_4_n_8_pp[13], lut_val_4_n_8_pp[13], lut_val_4_n_8_pp[13], lut_val_4_n_8_pp[13], lut_val_4_n_8_pp[13], lut_val_4_n_8_pp, 8'd0 };
assign lut_4_bit_9_fill = {lut_val_4_n_9_pp[13], lut_val_4_n_9_pp[13], lut_val_4_n_9_pp[13], lut_val_4_n_9_pp[13], lut_val_4_n_9_pp[13], lut_val_4_n_9_pp[13], lut_val_4_n_9_pp, 9'd0 };
assign lut_4_bit_10_fill = {lut_val_4_n_10_pp[13], lut_val_4_n_10_pp[13], lut_val_4_n_10_pp[13], lut_val_4_n_10_pp[13], lut_val_4_n_10_pp[13], lut_val_4_n_10_pp, 10'd0 };
assign lut_4_bit_11_fill = {lut_val_4_n_11_pp[13], lut_val_4_n_11_pp[13], lut_val_4_n_11_pp[13], lut_val_4_n_11_pp[13], lut_val_4_n_11_pp, 11'd0 };
assign lut_4_bit_12_fill = {lut_val_4_n_12_pp[13], lut_val_4_n_12_pp[13], lut_val_4_n_12_pp[13], lut_val_4_n_12_pp, 12'd0 };
assign lut_4_bit_13_fill = {lut_val_4_n_13_pp[13], lut_val_4_n_13_pp[13], lut_val_4_n_13_pp, 13'd0 };
assign lut_4_bit_14_fill = {lut_val_4_n_14_pp[13], lut_val_4_n_14_pp, 14'd0 };
assign lut_4_bit_15_fill = { lut_val_4_n_15_pp, 15'd0 };
wire [29:0] tree_4_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_4_bit_0_fill), .bin(lut_4_bit_1_fill), .res(tree_4_pp_l_0_n_0_n) );
defparam Uadd_4_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_4_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_4_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_4_bit_2_fill), .bin(lut_4_bit_3_fill), .res(tree_4_pp_l_0_n_1_n) );
defparam Uadd_4_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_4_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_4_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_4_bit_4_fill), .bin(lut_4_bit_5_fill), .res(tree_4_pp_l_0_n_2_n) );
defparam Uadd_4_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_4_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_4_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_4_bit_6_fill), .bin(lut_4_bit_7_fill), .res(tree_4_pp_l_0_n_3_n) );
defparam Uadd_4_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_4_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_4_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_4_bit_8_fill), .bin(lut_4_bit_9_fill), .res(tree_4_pp_l_0_n_4_n) );
defparam Uadd_4_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_4_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_4_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_4_bit_10_fill), .bin(lut_4_bit_11_fill), .res(tree_4_pp_l_0_n_5_n) );
defparam Uadd_4_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_4_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_4_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_4_bit_12_fill), .bin(lut_4_bit_13_fill), .res(tree_4_pp_l_0_n_6_n) );
defparam Uadd_4_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_4_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_4_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_4_bit_14_fill), .bin(lut_4_bit_15_fill), .res(tree_4_pp_l_0_n_7_n) );
defparam Uadd_4_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_4_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_4_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_4_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_4_pp_l_0_n_0_n), .bin(tree_4_pp_l_0_n_1_n), .res(tree_4_pp_l_1_n_0_n) );
defparam Uadd_4_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_4_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_4_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_4_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_4_pp_l_0_n_2_n), .bin(tree_4_pp_l_0_n_3_n), .res(tree_4_pp_l_1_n_1_n) );
defparam Uadd_4_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_4_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_4_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_4_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_4_pp_l_0_n_4_n), .bin(tree_4_pp_l_0_n_5_n), .res(tree_4_pp_l_1_n_2_n) );
defparam Uadd_4_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_4_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_4_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_4_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_4_pp_l_0_n_6_n), .bin(tree_4_pp_l_0_n_7_n), .res(tree_4_pp_l_1_n_3_n) );
defparam Uadd_4_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_4_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_4_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_4_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_4_pp_l_1_n_0_n), .bin(tree_4_pp_l_1_n_1_n), .res(tree_4_pp_l_2_n_0_n) );
defparam Uadd_4_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_4_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_4_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_4_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_4_pp_l_1_n_2_n), .bin(tree_4_pp_l_1_n_3_n), .res(tree_4_pp_l_2_n_1_n) );
defparam Uadd_4_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_4_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_4_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_4_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_4_pp_l_2_n_0_n), .bin(tree_4_pp_l_2_n_1_n), .res(tree_4_pp_l_3_n_0_n) );
defparam Uadd_4_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_4_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_4_n;
assign lut_val_4_n=tree_4_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_5_bit_0_fill;
wire [28:0] lut_5_bit_1_fill;
wire [28:0] lut_5_bit_2_fill;
wire [28:0] lut_5_bit_3_fill;
wire [28:0] lut_5_bit_4_fill;
wire [28:0] lut_5_bit_5_fill;
wire [28:0] lut_5_bit_6_fill;
wire [28:0] lut_5_bit_7_fill;
wire [28:0] lut_5_bit_8_fill;
wire [28:0] lut_5_bit_9_fill;
wire [28:0] lut_5_bit_10_fill;
wire [28:0] lut_5_bit_11_fill;
wire [28:0] lut_5_bit_12_fill;
wire [28:0] lut_5_bit_13_fill;
wire [28:0] lut_5_bit_14_fill;
wire [28:0] lut_5_bit_15_fill;
assign lut_5_bit_0_fill = {lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp[13], lut_val_5_n_0_pp };
assign lut_5_bit_1_fill = {lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp[13], lut_val_5_n_1_pp, 1'd0 };
assign lut_5_bit_2_fill = {lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp[13], lut_val_5_n_2_pp, 2'd0 };
assign lut_5_bit_3_fill = {lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp[13], lut_val_5_n_3_pp, 3'd0 };
assign lut_5_bit_4_fill = {lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp[13], lut_val_5_n_4_pp, 4'd0 };
assign lut_5_bit_5_fill = {lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp[13], lut_val_5_n_5_pp, 5'd0 };
assign lut_5_bit_6_fill = {lut_val_5_n_6_pp[13], lut_val_5_n_6_pp[13], lut_val_5_n_6_pp[13], lut_val_5_n_6_pp[13], lut_val_5_n_6_pp[13], lut_val_5_n_6_pp[13], lut_val_5_n_6_pp[13], lut_val_5_n_6_pp[13], lut_val_5_n_6_pp[13], lut_val_5_n_6_pp, 6'd0 };
assign lut_5_bit_7_fill = {lut_val_5_n_7_pp[13], lut_val_5_n_7_pp[13], lut_val_5_n_7_pp[13], lut_val_5_n_7_pp[13], lut_val_5_n_7_pp[13], lut_val_5_n_7_pp[13], lut_val_5_n_7_pp[13], lut_val_5_n_7_pp[13], lut_val_5_n_7_pp, 7'd0 };
assign lut_5_bit_8_fill = {lut_val_5_n_8_pp[13], lut_val_5_n_8_pp[13], lut_val_5_n_8_pp[13], lut_val_5_n_8_pp[13], lut_val_5_n_8_pp[13], lut_val_5_n_8_pp[13], lut_val_5_n_8_pp[13], lut_val_5_n_8_pp, 8'd0 };
assign lut_5_bit_9_fill = {lut_val_5_n_9_pp[13], lut_val_5_n_9_pp[13], lut_val_5_n_9_pp[13], lut_val_5_n_9_pp[13], lut_val_5_n_9_pp[13], lut_val_5_n_9_pp[13], lut_val_5_n_9_pp, 9'd0 };
assign lut_5_bit_10_fill = {lut_val_5_n_10_pp[13], lut_val_5_n_10_pp[13], lut_val_5_n_10_pp[13], lut_val_5_n_10_pp[13], lut_val_5_n_10_pp[13], lut_val_5_n_10_pp, 10'd0 };
assign lut_5_bit_11_fill = {lut_val_5_n_11_pp[13], lut_val_5_n_11_pp[13], lut_val_5_n_11_pp[13], lut_val_5_n_11_pp[13], lut_val_5_n_11_pp, 11'd0 };
assign lut_5_bit_12_fill = {lut_val_5_n_12_pp[13], lut_val_5_n_12_pp[13], lut_val_5_n_12_pp[13], lut_val_5_n_12_pp, 12'd0 };
assign lut_5_bit_13_fill = {lut_val_5_n_13_pp[13], lut_val_5_n_13_pp[13], lut_val_5_n_13_pp, 13'd0 };
assign lut_5_bit_14_fill = {lut_val_5_n_14_pp[13], lut_val_5_n_14_pp, 14'd0 };
assign lut_5_bit_15_fill = { lut_val_5_n_15_pp, 15'd0 };
wire [29:0] tree_5_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_5_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_5_bit_0_fill), .bin(lut_5_bit_1_fill), .res(tree_5_pp_l_0_n_0_n) );
defparam Uadd_5_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_5_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_5_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_5_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_5_bit_2_fill), .bin(lut_5_bit_3_fill), .res(tree_5_pp_l_0_n_1_n) );
defparam Uadd_5_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_5_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_5_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_5_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_5_bit_4_fill), .bin(lut_5_bit_5_fill), .res(tree_5_pp_l_0_n_2_n) );
defparam Uadd_5_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_5_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_5_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_5_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_5_bit_6_fill), .bin(lut_5_bit_7_fill), .res(tree_5_pp_l_0_n_3_n) );
defparam Uadd_5_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_5_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_5_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_5_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_5_bit_8_fill), .bin(lut_5_bit_9_fill), .res(tree_5_pp_l_0_n_4_n) );
defparam Uadd_5_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_5_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_5_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_5_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_5_bit_10_fill), .bin(lut_5_bit_11_fill), .res(tree_5_pp_l_0_n_5_n) );
defparam Uadd_5_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_5_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_5_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_5_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_5_bit_12_fill), .bin(lut_5_bit_13_fill), .res(tree_5_pp_l_0_n_6_n) );
defparam Uadd_5_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_5_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_5_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_5_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_5_bit_14_fill), .bin(lut_5_bit_15_fill), .res(tree_5_pp_l_0_n_7_n) );
defparam Uadd_5_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_5_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_5_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_5_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_5_pp_l_0_n_0_n), .bin(tree_5_pp_l_0_n_1_n), .res(tree_5_pp_l_1_n_0_n) );
defparam Uadd_5_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_5_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_5_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_5_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_5_pp_l_0_n_2_n), .bin(tree_5_pp_l_0_n_3_n), .res(tree_5_pp_l_1_n_1_n) );
defparam Uadd_5_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_5_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_5_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_5_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_5_pp_l_0_n_4_n), .bin(tree_5_pp_l_0_n_5_n), .res(tree_5_pp_l_1_n_2_n) );
defparam Uadd_5_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_5_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_5_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_5_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_5_pp_l_0_n_6_n), .bin(tree_5_pp_l_0_n_7_n), .res(tree_5_pp_l_1_n_3_n) );
defparam Uadd_5_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_5_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_5_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_5_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_5_pp_l_1_n_0_n), .bin(tree_5_pp_l_1_n_1_n), .res(tree_5_pp_l_2_n_0_n) );
defparam Uadd_5_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_5_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_5_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_5_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_5_pp_l_1_n_2_n), .bin(tree_5_pp_l_1_n_3_n), .res(tree_5_pp_l_2_n_1_n) );
defparam Uadd_5_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_5_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_5_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_5_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_5_pp_l_2_n_0_n), .bin(tree_5_pp_l_2_n_1_n), .res(tree_5_pp_l_3_n_0_n) );
defparam Uadd_5_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_5_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_5_n;
assign lut_val_5_n=tree_5_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_6_bit_0_fill;
wire [28:0] lut_6_bit_1_fill;
wire [28:0] lut_6_bit_2_fill;
wire [28:0] lut_6_bit_3_fill;
wire [28:0] lut_6_bit_4_fill;
wire [28:0] lut_6_bit_5_fill;
wire [28:0] lut_6_bit_6_fill;
wire [28:0] lut_6_bit_7_fill;
wire [28:0] lut_6_bit_8_fill;
wire [28:0] lut_6_bit_9_fill;
wire [28:0] lut_6_bit_10_fill;
wire [28:0] lut_6_bit_11_fill;
wire [28:0] lut_6_bit_12_fill;
wire [28:0] lut_6_bit_13_fill;
wire [28:0] lut_6_bit_14_fill;
wire [28:0] lut_6_bit_15_fill;
assign lut_6_bit_0_fill = {lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp[13], lut_val_6_n_0_pp };
assign lut_6_bit_1_fill = {lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp[13], lut_val_6_n_1_pp, 1'd0 };
assign lut_6_bit_2_fill = {lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp[13], lut_val_6_n_2_pp, 2'd0 };
assign lut_6_bit_3_fill = {lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp[13], lut_val_6_n_3_pp, 3'd0 };
assign lut_6_bit_4_fill = {lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp[13], lut_val_6_n_4_pp, 4'd0 };
assign lut_6_bit_5_fill = {lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp[13], lut_val_6_n_5_pp, 5'd0 };
assign lut_6_bit_6_fill = {lut_val_6_n_6_pp[13], lut_val_6_n_6_pp[13], lut_val_6_n_6_pp[13], lut_val_6_n_6_pp[13], lut_val_6_n_6_pp[13], lut_val_6_n_6_pp[13], lut_val_6_n_6_pp[13], lut_val_6_n_6_pp[13], lut_val_6_n_6_pp[13], lut_val_6_n_6_pp, 6'd0 };
assign lut_6_bit_7_fill = {lut_val_6_n_7_pp[13], lut_val_6_n_7_pp[13], lut_val_6_n_7_pp[13], lut_val_6_n_7_pp[13], lut_val_6_n_7_pp[13], lut_val_6_n_7_pp[13], lut_val_6_n_7_pp[13], lut_val_6_n_7_pp[13], lut_val_6_n_7_pp, 7'd0 };
assign lut_6_bit_8_fill = {lut_val_6_n_8_pp[13], lut_val_6_n_8_pp[13], lut_val_6_n_8_pp[13], lut_val_6_n_8_pp[13], lut_val_6_n_8_pp[13], lut_val_6_n_8_pp[13], lut_val_6_n_8_pp[13], lut_val_6_n_8_pp, 8'd0 };
assign lut_6_bit_9_fill = {lut_val_6_n_9_pp[13], lut_val_6_n_9_pp[13], lut_val_6_n_9_pp[13], lut_val_6_n_9_pp[13], lut_val_6_n_9_pp[13], lut_val_6_n_9_pp[13], lut_val_6_n_9_pp, 9'd0 };
assign lut_6_bit_10_fill = {lut_val_6_n_10_pp[13], lut_val_6_n_10_pp[13], lut_val_6_n_10_pp[13], lut_val_6_n_10_pp[13], lut_val_6_n_10_pp[13], lut_val_6_n_10_pp, 10'd0 };
assign lut_6_bit_11_fill = {lut_val_6_n_11_pp[13], lut_val_6_n_11_pp[13], lut_val_6_n_11_pp[13], lut_val_6_n_11_pp[13], lut_val_6_n_11_pp, 11'd0 };
assign lut_6_bit_12_fill = {lut_val_6_n_12_pp[13], lut_val_6_n_12_pp[13], lut_val_6_n_12_pp[13], lut_val_6_n_12_pp, 12'd0 };
assign lut_6_bit_13_fill = {lut_val_6_n_13_pp[13], lut_val_6_n_13_pp[13], lut_val_6_n_13_pp, 13'd0 };
assign lut_6_bit_14_fill = {lut_val_6_n_14_pp[13], lut_val_6_n_14_pp, 14'd0 };
assign lut_6_bit_15_fill = { lut_val_6_n_15_pp, 15'd0 };
wire [29:0] tree_6_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_6_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_6_bit_0_fill), .bin(lut_6_bit_1_fill), .res(tree_6_pp_l_0_n_0_n) );
defparam Uadd_6_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_6_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_6_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_6_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_6_bit_2_fill), .bin(lut_6_bit_3_fill), .res(tree_6_pp_l_0_n_1_n) );
defparam Uadd_6_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_6_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_6_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_6_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_6_bit_4_fill), .bin(lut_6_bit_5_fill), .res(tree_6_pp_l_0_n_2_n) );
defparam Uadd_6_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_6_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_6_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_6_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_6_bit_6_fill), .bin(lut_6_bit_7_fill), .res(tree_6_pp_l_0_n_3_n) );
defparam Uadd_6_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_6_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_6_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_6_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_6_bit_8_fill), .bin(lut_6_bit_9_fill), .res(tree_6_pp_l_0_n_4_n) );
defparam Uadd_6_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_6_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_6_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_6_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_6_bit_10_fill), .bin(lut_6_bit_11_fill), .res(tree_6_pp_l_0_n_5_n) );
defparam Uadd_6_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_6_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_6_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_6_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_6_bit_12_fill), .bin(lut_6_bit_13_fill), .res(tree_6_pp_l_0_n_6_n) );
defparam Uadd_6_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_6_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_6_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_6_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_6_bit_14_fill), .bin(lut_6_bit_15_fill), .res(tree_6_pp_l_0_n_7_n) );
defparam Uadd_6_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_6_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_6_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_6_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_6_pp_l_0_n_0_n), .bin(tree_6_pp_l_0_n_1_n), .res(tree_6_pp_l_1_n_0_n) );
defparam Uadd_6_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_6_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_6_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_6_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_6_pp_l_0_n_2_n), .bin(tree_6_pp_l_0_n_3_n), .res(tree_6_pp_l_1_n_1_n) );
defparam Uadd_6_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_6_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_6_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_6_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_6_pp_l_0_n_4_n), .bin(tree_6_pp_l_0_n_5_n), .res(tree_6_pp_l_1_n_2_n) );
defparam Uadd_6_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_6_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_6_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_6_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_6_pp_l_0_n_6_n), .bin(tree_6_pp_l_0_n_7_n), .res(tree_6_pp_l_1_n_3_n) );
defparam Uadd_6_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_6_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_6_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_6_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_6_pp_l_1_n_0_n), .bin(tree_6_pp_l_1_n_1_n), .res(tree_6_pp_l_2_n_0_n) );
defparam Uadd_6_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_6_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_6_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_6_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_6_pp_l_1_n_2_n), .bin(tree_6_pp_l_1_n_3_n), .res(tree_6_pp_l_2_n_1_n) );
defparam Uadd_6_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_6_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_6_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_6_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_6_pp_l_2_n_0_n), .bin(tree_6_pp_l_2_n_1_n), .res(tree_6_pp_l_3_n_0_n) );
defparam Uadd_6_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_6_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_6_n;
assign lut_val_6_n=tree_6_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_7_bit_0_fill;
wire [28:0] lut_7_bit_1_fill;
wire [28:0] lut_7_bit_2_fill;
wire [28:0] lut_7_bit_3_fill;
wire [28:0] lut_7_bit_4_fill;
wire [28:0] lut_7_bit_5_fill;
wire [28:0] lut_7_bit_6_fill;
wire [28:0] lut_7_bit_7_fill;
wire [28:0] lut_7_bit_8_fill;
wire [28:0] lut_7_bit_9_fill;
wire [28:0] lut_7_bit_10_fill;
wire [28:0] lut_7_bit_11_fill;
wire [28:0] lut_7_bit_12_fill;
wire [28:0] lut_7_bit_13_fill;
wire [28:0] lut_7_bit_14_fill;
wire [28:0] lut_7_bit_15_fill;
assign lut_7_bit_0_fill = {lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp[13], lut_val_7_n_0_pp };
assign lut_7_bit_1_fill = {lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp[13], lut_val_7_n_1_pp, 1'd0 };
assign lut_7_bit_2_fill = {lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp[13], lut_val_7_n_2_pp, 2'd0 };
assign lut_7_bit_3_fill = {lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp[13], lut_val_7_n_3_pp, 3'd0 };
assign lut_7_bit_4_fill = {lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp[13], lut_val_7_n_4_pp, 4'd0 };
assign lut_7_bit_5_fill = {lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp[13], lut_val_7_n_5_pp, 5'd0 };
assign lut_7_bit_6_fill = {lut_val_7_n_6_pp[13], lut_val_7_n_6_pp[13], lut_val_7_n_6_pp[13], lut_val_7_n_6_pp[13], lut_val_7_n_6_pp[13], lut_val_7_n_6_pp[13], lut_val_7_n_6_pp[13], lut_val_7_n_6_pp[13], lut_val_7_n_6_pp[13], lut_val_7_n_6_pp, 6'd0 };
assign lut_7_bit_7_fill = {lut_val_7_n_7_pp[13], lut_val_7_n_7_pp[13], lut_val_7_n_7_pp[13], lut_val_7_n_7_pp[13], lut_val_7_n_7_pp[13], lut_val_7_n_7_pp[13], lut_val_7_n_7_pp[13], lut_val_7_n_7_pp[13], lut_val_7_n_7_pp, 7'd0 };
assign lut_7_bit_8_fill = {lut_val_7_n_8_pp[13], lut_val_7_n_8_pp[13], lut_val_7_n_8_pp[13], lut_val_7_n_8_pp[13], lut_val_7_n_8_pp[13], lut_val_7_n_8_pp[13], lut_val_7_n_8_pp[13], lut_val_7_n_8_pp, 8'd0 };
assign lut_7_bit_9_fill = {lut_val_7_n_9_pp[13], lut_val_7_n_9_pp[13], lut_val_7_n_9_pp[13], lut_val_7_n_9_pp[13], lut_val_7_n_9_pp[13], lut_val_7_n_9_pp[13], lut_val_7_n_9_pp, 9'd0 };
assign lut_7_bit_10_fill = {lut_val_7_n_10_pp[13], lut_val_7_n_10_pp[13], lut_val_7_n_10_pp[13], lut_val_7_n_10_pp[13], lut_val_7_n_10_pp[13], lut_val_7_n_10_pp, 10'd0 };
assign lut_7_bit_11_fill = {lut_val_7_n_11_pp[13], lut_val_7_n_11_pp[13], lut_val_7_n_11_pp[13], lut_val_7_n_11_pp[13], lut_val_7_n_11_pp, 11'd0 };
assign lut_7_bit_12_fill = {lut_val_7_n_12_pp[13], lut_val_7_n_12_pp[13], lut_val_7_n_12_pp[13], lut_val_7_n_12_pp, 12'd0 };
assign lut_7_bit_13_fill = {lut_val_7_n_13_pp[13], lut_val_7_n_13_pp[13], lut_val_7_n_13_pp, 13'd0 };
assign lut_7_bit_14_fill = {lut_val_7_n_14_pp[13], lut_val_7_n_14_pp, 14'd0 };
assign lut_7_bit_15_fill = { lut_val_7_n_15_pp, 15'd0 };
wire [29:0] tree_7_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_7_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_7_bit_0_fill), .bin(lut_7_bit_1_fill), .res(tree_7_pp_l_0_n_0_n) );
defparam Uadd_7_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_7_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_7_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_7_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_7_bit_2_fill), .bin(lut_7_bit_3_fill), .res(tree_7_pp_l_0_n_1_n) );
defparam Uadd_7_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_7_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_7_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_7_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_7_bit_4_fill), .bin(lut_7_bit_5_fill), .res(tree_7_pp_l_0_n_2_n) );
defparam Uadd_7_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_7_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_7_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_7_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_7_bit_6_fill), .bin(lut_7_bit_7_fill), .res(tree_7_pp_l_0_n_3_n) );
defparam Uadd_7_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_7_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_7_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_7_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_7_bit_8_fill), .bin(lut_7_bit_9_fill), .res(tree_7_pp_l_0_n_4_n) );
defparam Uadd_7_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_7_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_7_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_7_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_7_bit_10_fill), .bin(lut_7_bit_11_fill), .res(tree_7_pp_l_0_n_5_n) );
defparam Uadd_7_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_7_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_7_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_7_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_7_bit_12_fill), .bin(lut_7_bit_13_fill), .res(tree_7_pp_l_0_n_6_n) );
defparam Uadd_7_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_7_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_7_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_7_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_7_bit_14_fill), .bin(lut_7_bit_15_fill), .res(tree_7_pp_l_0_n_7_n) );
defparam Uadd_7_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_7_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_7_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_7_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_7_pp_l_0_n_0_n), .bin(tree_7_pp_l_0_n_1_n), .res(tree_7_pp_l_1_n_0_n) );
defparam Uadd_7_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_7_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_7_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_7_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_7_pp_l_0_n_2_n), .bin(tree_7_pp_l_0_n_3_n), .res(tree_7_pp_l_1_n_1_n) );
defparam Uadd_7_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_7_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_7_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_7_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_7_pp_l_0_n_4_n), .bin(tree_7_pp_l_0_n_5_n), .res(tree_7_pp_l_1_n_2_n) );
defparam Uadd_7_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_7_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_7_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_7_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_7_pp_l_0_n_6_n), .bin(tree_7_pp_l_0_n_7_n), .res(tree_7_pp_l_1_n_3_n) );
defparam Uadd_7_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_7_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_7_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_7_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_7_pp_l_1_n_0_n), .bin(tree_7_pp_l_1_n_1_n), .res(tree_7_pp_l_2_n_0_n) );
defparam Uadd_7_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_7_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_7_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_7_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_7_pp_l_1_n_2_n), .bin(tree_7_pp_l_1_n_3_n), .res(tree_7_pp_l_2_n_1_n) );
defparam Uadd_7_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_7_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_7_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_7_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_7_pp_l_2_n_0_n), .bin(tree_7_pp_l_2_n_1_n), .res(tree_7_pp_l_3_n_0_n) );
defparam Uadd_7_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_7_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_7_n;
assign lut_val_7_n=tree_7_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_8_bit_0_fill;
wire [28:0] lut_8_bit_1_fill;
wire [28:0] lut_8_bit_2_fill;
wire [28:0] lut_8_bit_3_fill;
wire [28:0] lut_8_bit_4_fill;
wire [28:0] lut_8_bit_5_fill;
wire [28:0] lut_8_bit_6_fill;
wire [28:0] lut_8_bit_7_fill;
wire [28:0] lut_8_bit_8_fill;
wire [28:0] lut_8_bit_9_fill;
wire [28:0] lut_8_bit_10_fill;
wire [28:0] lut_8_bit_11_fill;
wire [28:0] lut_8_bit_12_fill;
wire [28:0] lut_8_bit_13_fill;
wire [28:0] lut_8_bit_14_fill;
wire [28:0] lut_8_bit_15_fill;
assign lut_8_bit_0_fill = {lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp[13], lut_val_8_n_0_pp };
assign lut_8_bit_1_fill = {lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp[13], lut_val_8_n_1_pp, 1'd0 };
assign lut_8_bit_2_fill = {lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp[13], lut_val_8_n_2_pp, 2'd0 };
assign lut_8_bit_3_fill = {lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp[13], lut_val_8_n_3_pp, 3'd0 };
assign lut_8_bit_4_fill = {lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp[13], lut_val_8_n_4_pp, 4'd0 };
assign lut_8_bit_5_fill = {lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp[13], lut_val_8_n_5_pp, 5'd0 };
assign lut_8_bit_6_fill = {lut_val_8_n_6_pp[13], lut_val_8_n_6_pp[13], lut_val_8_n_6_pp[13], lut_val_8_n_6_pp[13], lut_val_8_n_6_pp[13], lut_val_8_n_6_pp[13], lut_val_8_n_6_pp[13], lut_val_8_n_6_pp[13], lut_val_8_n_6_pp[13], lut_val_8_n_6_pp, 6'd0 };
assign lut_8_bit_7_fill = {lut_val_8_n_7_pp[13], lut_val_8_n_7_pp[13], lut_val_8_n_7_pp[13], lut_val_8_n_7_pp[13], lut_val_8_n_7_pp[13], lut_val_8_n_7_pp[13], lut_val_8_n_7_pp[13], lut_val_8_n_7_pp[13], lut_val_8_n_7_pp, 7'd0 };
assign lut_8_bit_8_fill = {lut_val_8_n_8_pp[13], lut_val_8_n_8_pp[13], lut_val_8_n_8_pp[13], lut_val_8_n_8_pp[13], lut_val_8_n_8_pp[13], lut_val_8_n_8_pp[13], lut_val_8_n_8_pp[13], lut_val_8_n_8_pp, 8'd0 };
assign lut_8_bit_9_fill = {lut_val_8_n_9_pp[13], lut_val_8_n_9_pp[13], lut_val_8_n_9_pp[13], lut_val_8_n_9_pp[13], lut_val_8_n_9_pp[13], lut_val_8_n_9_pp[13], lut_val_8_n_9_pp, 9'd0 };
assign lut_8_bit_10_fill = {lut_val_8_n_10_pp[13], lut_val_8_n_10_pp[13], lut_val_8_n_10_pp[13], lut_val_8_n_10_pp[13], lut_val_8_n_10_pp[13], lut_val_8_n_10_pp, 10'd0 };
assign lut_8_bit_11_fill = {lut_val_8_n_11_pp[13], lut_val_8_n_11_pp[13], lut_val_8_n_11_pp[13], lut_val_8_n_11_pp[13], lut_val_8_n_11_pp, 11'd0 };
assign lut_8_bit_12_fill = {lut_val_8_n_12_pp[13], lut_val_8_n_12_pp[13], lut_val_8_n_12_pp[13], lut_val_8_n_12_pp, 12'd0 };
assign lut_8_bit_13_fill = {lut_val_8_n_13_pp[13], lut_val_8_n_13_pp[13], lut_val_8_n_13_pp, 13'd0 };
assign lut_8_bit_14_fill = {lut_val_8_n_14_pp[13], lut_val_8_n_14_pp, 14'd0 };
assign lut_8_bit_15_fill = { lut_val_8_n_15_pp, 15'd0 };
wire [29:0] tree_8_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_8_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_8_bit_0_fill), .bin(lut_8_bit_1_fill), .res(tree_8_pp_l_0_n_0_n) );
defparam Uadd_8_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_8_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_8_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_8_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_8_bit_2_fill), .bin(lut_8_bit_3_fill), .res(tree_8_pp_l_0_n_1_n) );
defparam Uadd_8_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_8_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_8_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_8_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_8_bit_4_fill), .bin(lut_8_bit_5_fill), .res(tree_8_pp_l_0_n_2_n) );
defparam Uadd_8_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_8_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_8_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_8_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_8_bit_6_fill), .bin(lut_8_bit_7_fill), .res(tree_8_pp_l_0_n_3_n) );
defparam Uadd_8_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_8_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_8_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_8_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_8_bit_8_fill), .bin(lut_8_bit_9_fill), .res(tree_8_pp_l_0_n_4_n) );
defparam Uadd_8_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_8_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_8_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_8_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_8_bit_10_fill), .bin(lut_8_bit_11_fill), .res(tree_8_pp_l_0_n_5_n) );
defparam Uadd_8_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_8_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_8_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_8_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_8_bit_12_fill), .bin(lut_8_bit_13_fill), .res(tree_8_pp_l_0_n_6_n) );
defparam Uadd_8_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_8_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_8_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_8_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_8_bit_14_fill), .bin(lut_8_bit_15_fill), .res(tree_8_pp_l_0_n_7_n) );
defparam Uadd_8_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_8_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_8_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_8_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_8_pp_l_0_n_0_n), .bin(tree_8_pp_l_0_n_1_n), .res(tree_8_pp_l_1_n_0_n) );
defparam Uadd_8_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_8_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_8_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_8_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_8_pp_l_0_n_2_n), .bin(tree_8_pp_l_0_n_3_n), .res(tree_8_pp_l_1_n_1_n) );
defparam Uadd_8_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_8_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_8_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_8_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_8_pp_l_0_n_4_n), .bin(tree_8_pp_l_0_n_5_n), .res(tree_8_pp_l_1_n_2_n) );
defparam Uadd_8_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_8_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_8_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_8_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_8_pp_l_0_n_6_n), .bin(tree_8_pp_l_0_n_7_n), .res(tree_8_pp_l_1_n_3_n) );
defparam Uadd_8_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_8_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_8_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_8_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_8_pp_l_1_n_0_n), .bin(tree_8_pp_l_1_n_1_n), .res(tree_8_pp_l_2_n_0_n) );
defparam Uadd_8_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_8_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_8_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_8_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_8_pp_l_1_n_2_n), .bin(tree_8_pp_l_1_n_3_n), .res(tree_8_pp_l_2_n_1_n) );
defparam Uadd_8_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_8_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_8_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_8_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_8_pp_l_2_n_0_n), .bin(tree_8_pp_l_2_n_1_n), .res(tree_8_pp_l_3_n_0_n) );
defparam Uadd_8_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_8_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_8_n;
assign lut_val_8_n=tree_8_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_9_bit_0_fill;
wire [28:0] lut_9_bit_1_fill;
wire [28:0] lut_9_bit_2_fill;
wire [28:0] lut_9_bit_3_fill;
wire [28:0] lut_9_bit_4_fill;
wire [28:0] lut_9_bit_5_fill;
wire [28:0] lut_9_bit_6_fill;
wire [28:0] lut_9_bit_7_fill;
wire [28:0] lut_9_bit_8_fill;
wire [28:0] lut_9_bit_9_fill;
wire [28:0] lut_9_bit_10_fill;
wire [28:0] lut_9_bit_11_fill;
wire [28:0] lut_9_bit_12_fill;
wire [28:0] lut_9_bit_13_fill;
wire [28:0] lut_9_bit_14_fill;
wire [28:0] lut_9_bit_15_fill;
assign lut_9_bit_0_fill = {lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp[13], lut_val_9_n_0_pp };
assign lut_9_bit_1_fill = {lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp[13], lut_val_9_n_1_pp, 1'd0 };
assign lut_9_bit_2_fill = {lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp[13], lut_val_9_n_2_pp, 2'd0 };
assign lut_9_bit_3_fill = {lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp[13], lut_val_9_n_3_pp, 3'd0 };
assign lut_9_bit_4_fill = {lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp[13], lut_val_9_n_4_pp, 4'd0 };
assign lut_9_bit_5_fill = {lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp[13], lut_val_9_n_5_pp, 5'd0 };
assign lut_9_bit_6_fill = {lut_val_9_n_6_pp[13], lut_val_9_n_6_pp[13], lut_val_9_n_6_pp[13], lut_val_9_n_6_pp[13], lut_val_9_n_6_pp[13], lut_val_9_n_6_pp[13], lut_val_9_n_6_pp[13], lut_val_9_n_6_pp[13], lut_val_9_n_6_pp[13], lut_val_9_n_6_pp, 6'd0 };
assign lut_9_bit_7_fill = {lut_val_9_n_7_pp[13], lut_val_9_n_7_pp[13], lut_val_9_n_7_pp[13], lut_val_9_n_7_pp[13], lut_val_9_n_7_pp[13], lut_val_9_n_7_pp[13], lut_val_9_n_7_pp[13], lut_val_9_n_7_pp[13], lut_val_9_n_7_pp, 7'd0 };
assign lut_9_bit_8_fill = {lut_val_9_n_8_pp[13], lut_val_9_n_8_pp[13], lut_val_9_n_8_pp[13], lut_val_9_n_8_pp[13], lut_val_9_n_8_pp[13], lut_val_9_n_8_pp[13], lut_val_9_n_8_pp[13], lut_val_9_n_8_pp, 8'd0 };
assign lut_9_bit_9_fill = {lut_val_9_n_9_pp[13], lut_val_9_n_9_pp[13], lut_val_9_n_9_pp[13], lut_val_9_n_9_pp[13], lut_val_9_n_9_pp[13], lut_val_9_n_9_pp[13], lut_val_9_n_9_pp, 9'd0 };
assign lut_9_bit_10_fill = {lut_val_9_n_10_pp[13], lut_val_9_n_10_pp[13], lut_val_9_n_10_pp[13], lut_val_9_n_10_pp[13], lut_val_9_n_10_pp[13], lut_val_9_n_10_pp, 10'd0 };
assign lut_9_bit_11_fill = {lut_val_9_n_11_pp[13], lut_val_9_n_11_pp[13], lut_val_9_n_11_pp[13], lut_val_9_n_11_pp[13], lut_val_9_n_11_pp, 11'd0 };
assign lut_9_bit_12_fill = {lut_val_9_n_12_pp[13], lut_val_9_n_12_pp[13], lut_val_9_n_12_pp[13], lut_val_9_n_12_pp, 12'd0 };
assign lut_9_bit_13_fill = {lut_val_9_n_13_pp[13], lut_val_9_n_13_pp[13], lut_val_9_n_13_pp, 13'd0 };
assign lut_9_bit_14_fill = {lut_val_9_n_14_pp[13], lut_val_9_n_14_pp, 14'd0 };
assign lut_9_bit_15_fill = { lut_val_9_n_15_pp, 15'd0 };
wire [29:0] tree_9_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_9_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_9_bit_0_fill), .bin(lut_9_bit_1_fill), .res(tree_9_pp_l_0_n_0_n) );
defparam Uadd_9_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_9_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_9_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_9_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_9_bit_2_fill), .bin(lut_9_bit_3_fill), .res(tree_9_pp_l_0_n_1_n) );
defparam Uadd_9_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_9_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_9_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_9_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_9_bit_4_fill), .bin(lut_9_bit_5_fill), .res(tree_9_pp_l_0_n_2_n) );
defparam Uadd_9_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_9_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_9_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_9_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_9_bit_6_fill), .bin(lut_9_bit_7_fill), .res(tree_9_pp_l_0_n_3_n) );
defparam Uadd_9_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_9_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_9_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_9_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_9_bit_8_fill), .bin(lut_9_bit_9_fill), .res(tree_9_pp_l_0_n_4_n) );
defparam Uadd_9_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_9_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_9_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_9_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_9_bit_10_fill), .bin(lut_9_bit_11_fill), .res(tree_9_pp_l_0_n_5_n) );
defparam Uadd_9_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_9_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_9_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_9_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_9_bit_12_fill), .bin(lut_9_bit_13_fill), .res(tree_9_pp_l_0_n_6_n) );
defparam Uadd_9_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_9_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_9_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_9_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_9_bit_14_fill), .bin(lut_9_bit_15_fill), .res(tree_9_pp_l_0_n_7_n) );
defparam Uadd_9_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_9_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_9_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_9_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_9_pp_l_0_n_0_n), .bin(tree_9_pp_l_0_n_1_n), .res(tree_9_pp_l_1_n_0_n) );
defparam Uadd_9_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_9_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_9_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_9_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_9_pp_l_0_n_2_n), .bin(tree_9_pp_l_0_n_3_n), .res(tree_9_pp_l_1_n_1_n) );
defparam Uadd_9_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_9_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_9_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_9_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_9_pp_l_0_n_4_n), .bin(tree_9_pp_l_0_n_5_n), .res(tree_9_pp_l_1_n_2_n) );
defparam Uadd_9_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_9_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_9_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_9_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_9_pp_l_0_n_6_n), .bin(tree_9_pp_l_0_n_7_n), .res(tree_9_pp_l_1_n_3_n) );
defparam Uadd_9_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_9_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_9_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_9_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_9_pp_l_1_n_0_n), .bin(tree_9_pp_l_1_n_1_n), .res(tree_9_pp_l_2_n_0_n) );
defparam Uadd_9_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_9_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_9_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_9_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_9_pp_l_1_n_2_n), .bin(tree_9_pp_l_1_n_3_n), .res(tree_9_pp_l_2_n_1_n) );
defparam Uadd_9_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_9_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_9_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_9_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_9_pp_l_2_n_0_n), .bin(tree_9_pp_l_2_n_1_n), .res(tree_9_pp_l_3_n_0_n) );
defparam Uadd_9_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_9_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_9_n;
assign lut_val_9_n=tree_9_pp_l_3_n_0_n;
// ---- partial product adder tree ----
wire [28:0] lut_10_bit_0_fill;
wire [28:0] lut_10_bit_1_fill;
wire [28:0] lut_10_bit_2_fill;
wire [28:0] lut_10_bit_3_fill;
wire [28:0] lut_10_bit_4_fill;
wire [28:0] lut_10_bit_5_fill;
wire [28:0] lut_10_bit_6_fill;
wire [28:0] lut_10_bit_7_fill;
wire [28:0] lut_10_bit_8_fill;
wire [28:0] lut_10_bit_9_fill;
wire [28:0] lut_10_bit_10_fill;
wire [28:0] lut_10_bit_11_fill;
wire [28:0] lut_10_bit_12_fill;
wire [28:0] lut_10_bit_13_fill;
wire [28:0] lut_10_bit_14_fill;
wire [28:0] lut_10_bit_15_fill;
assign lut_10_bit_0_fill = {lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp[13], lut_val_10_n_0_pp };
assign lut_10_bit_1_fill = {lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp[13], lut_val_10_n_1_pp, 1'd0 };
assign lut_10_bit_2_fill = {lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp[13], lut_val_10_n_2_pp, 2'd0 };
assign lut_10_bit_3_fill = {lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp[13], lut_val_10_n_3_pp, 3'd0 };
assign lut_10_bit_4_fill = {lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp[13], lut_val_10_n_4_pp, 4'd0 };
assign lut_10_bit_5_fill = {lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp[13], lut_val_10_n_5_pp, 5'd0 };
assign lut_10_bit_6_fill = {lut_val_10_n_6_pp[13], lut_val_10_n_6_pp[13], lut_val_10_n_6_pp[13], lut_val_10_n_6_pp[13], lut_val_10_n_6_pp[13], lut_val_10_n_6_pp[13], lut_val_10_n_6_pp[13], lut_val_10_n_6_pp[13], lut_val_10_n_6_pp[13], lut_val_10_n_6_pp, 6'd0 };
assign lut_10_bit_7_fill = {lut_val_10_n_7_pp[13], lut_val_10_n_7_pp[13], lut_val_10_n_7_pp[13], lut_val_10_n_7_pp[13], lut_val_10_n_7_pp[13], lut_val_10_n_7_pp[13], lut_val_10_n_7_pp[13], lut_val_10_n_7_pp[13], lut_val_10_n_7_pp, 7'd0 };
assign lut_10_bit_8_fill = {lut_val_10_n_8_pp[13], lut_val_10_n_8_pp[13], lut_val_10_n_8_pp[13], lut_val_10_n_8_pp[13], lut_val_10_n_8_pp[13], lut_val_10_n_8_pp[13], lut_val_10_n_8_pp[13], lut_val_10_n_8_pp, 8'd0 };
assign lut_10_bit_9_fill = {lut_val_10_n_9_pp[13], lut_val_10_n_9_pp[13], lut_val_10_n_9_pp[13], lut_val_10_n_9_pp[13], lut_val_10_n_9_pp[13], lut_val_10_n_9_pp[13], lut_val_10_n_9_pp, 9'd0 };
assign lut_10_bit_10_fill = {lut_val_10_n_10_pp[13], lut_val_10_n_10_pp[13], lut_val_10_n_10_pp[13], lut_val_10_n_10_pp[13], lut_val_10_n_10_pp[13], lut_val_10_n_10_pp, 10'd0 };
assign lut_10_bit_11_fill = {lut_val_10_n_11_pp[13], lut_val_10_n_11_pp[13], lut_val_10_n_11_pp[13], lut_val_10_n_11_pp[13], lut_val_10_n_11_pp, 11'd0 };
assign lut_10_bit_12_fill = {lut_val_10_n_12_pp[13], lut_val_10_n_12_pp[13], lut_val_10_n_12_pp[13], lut_val_10_n_12_pp, 12'd0 };
assign lut_10_bit_13_fill = {lut_val_10_n_13_pp[13], lut_val_10_n_13_pp[13], lut_val_10_n_13_pp, 13'd0 };
assign lut_10_bit_14_fill = {lut_val_10_n_14_pp[13], lut_val_10_n_14_pp, 14'd0 };
assign lut_10_bit_15_fill = { lut_val_10_n_15_pp, 15'd0 };
wire [29:0] tree_10_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_10_lut_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_10_bit_0_fill), .bin(lut_10_bit_1_fill), .res(tree_10_pp_l_0_n_0_n) );
defparam Uadd_10_lut_l_0_n_0_n.IN_WIDTH = 29;
defparam Uadd_10_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [29:0] tree_10_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_10_lut_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_10_bit_2_fill), .bin(lut_10_bit_3_fill), .res(tree_10_pp_l_0_n_1_n) );
defparam Uadd_10_lut_l_0_n_1_n.IN_WIDTH = 29;
defparam Uadd_10_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [29:0] tree_10_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_10_lut_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_10_bit_4_fill), .bin(lut_10_bit_5_fill), .res(tree_10_pp_l_0_n_2_n) );
defparam Uadd_10_lut_l_0_n_2_n.IN_WIDTH = 29;
defparam Uadd_10_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [29:0] tree_10_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_10_lut_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_10_bit_6_fill), .bin(lut_10_bit_7_fill), .res(tree_10_pp_l_0_n_3_n) );
defparam Uadd_10_lut_l_0_n_3_n.IN_WIDTH = 29;
defparam Uadd_10_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [29:0] tree_10_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_10_lut_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_10_bit_8_fill), .bin(lut_10_bit_9_fill), .res(tree_10_pp_l_0_n_4_n) );
defparam Uadd_10_lut_l_0_n_4_n.IN_WIDTH = 29;
defparam Uadd_10_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [29:0] tree_10_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_10_lut_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_10_bit_10_fill), .bin(lut_10_bit_11_fill), .res(tree_10_pp_l_0_n_5_n) );
defparam Uadd_10_lut_l_0_n_5_n.IN_WIDTH = 29;
defparam Uadd_10_lut_l_0_n_5_n.PIPE_DEPTH = 1;
wire [29:0] tree_10_pp_l_0_n_6_n;
sadd_lpm_cen Uadd_10_lut_l_0_n_6_n (.clk(clk), .gclk_en(clk_en), .ain(lut_10_bit_12_fill), .bin(lut_10_bit_13_fill), .res(tree_10_pp_l_0_n_6_n) );
defparam Uadd_10_lut_l_0_n_6_n.IN_WIDTH = 29;
defparam Uadd_10_lut_l_0_n_6_n.PIPE_DEPTH = 1;
wire [29:0] tree_10_pp_l_0_n_7_n;
sadd_lpm_cen Uadd_10_lut_l_0_n_7_n (.clk(clk), .gclk_en(clk_en), .ain(lut_10_bit_14_fill), .bin(lut_10_bit_15_fill), .res(tree_10_pp_l_0_n_7_n) );
defparam Uadd_10_lut_l_0_n_7_n.IN_WIDTH = 29;
defparam Uadd_10_lut_l_0_n_7_n.PIPE_DEPTH = 1;
wire [30:0] tree_10_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_10_lut_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_10_pp_l_0_n_0_n), .bin(tree_10_pp_l_0_n_1_n), .res(tree_10_pp_l_1_n_0_n) );
defparam Uadd_10_lut_l_1_n_0_n.IN_WIDTH = 30;
defparam Uadd_10_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [30:0] tree_10_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_10_lut_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_10_pp_l_0_n_2_n), .bin(tree_10_pp_l_0_n_3_n), .res(tree_10_pp_l_1_n_1_n) );
defparam Uadd_10_lut_l_1_n_1_n.IN_WIDTH = 30;
defparam Uadd_10_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [30:0] tree_10_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_10_lut_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(tree_10_pp_l_0_n_4_n), .bin(tree_10_pp_l_0_n_5_n), .res(tree_10_pp_l_1_n_2_n) );
defparam Uadd_10_lut_l_1_n_2_n.IN_WIDTH = 30;
defparam Uadd_10_lut_l_1_n_2_n.PIPE_DEPTH = 1;
wire [30:0] tree_10_pp_l_1_n_3_n;
sadd_lpm_cen Uadd_10_lut_l_1_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(tree_10_pp_l_0_n_6_n), .bin(tree_10_pp_l_0_n_7_n), .res(tree_10_pp_l_1_n_3_n) );
defparam Uadd_10_lut_l_1_n_3_n.IN_WIDTH = 30;
defparam Uadd_10_lut_l_1_n_3_n.PIPE_DEPTH = 1;
wire [31:0] tree_10_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_10_lut_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_10_pp_l_1_n_0_n), .bin(tree_10_pp_l_1_n_1_n), .res(tree_10_pp_l_2_n_0_n) );
defparam Uadd_10_lut_l_2_n_0_n.IN_WIDTH = 31;
defparam Uadd_10_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [31:0] tree_10_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_10_lut_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(tree_10_pp_l_1_n_2_n), .bin(tree_10_pp_l_1_n_3_n), .res(tree_10_pp_l_2_n_1_n) );
defparam Uadd_10_lut_l_2_n_1_n.IN_WIDTH = 31;
defparam Uadd_10_lut_l_2_n_1_n.PIPE_DEPTH = 1;
wire [32:0] tree_10_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_10_lut_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(tree_10_pp_l_2_n_0_n), .bin(tree_10_pp_l_2_n_1_n), .res(tree_10_pp_l_3_n_0_n) );
defparam Uadd_10_lut_l_3_n_0_n.IN_WIDTH = 32;
defparam Uadd_10_lut_l_3_n_0_n.PIPE_DEPTH = 1;
wire [32:0] lut_val_10_n;
assign lut_val_10_n=tree_10_pp_l_3_n_0_n;
// ---- final adder tree ----
wire [33:0] fin_atree_l_0_n_0_n;
sadd_lpm_cen Uadd_cen_l_0_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(lut_val_0_n), .bin(lut_val_1_n), .res(fin_atree_l_0_n_0_n) );
defparam Uadd_cen_l_0_n_0_n.IN_WIDTH = 33;
defparam Uadd_cen_l_0_n_0_n.PIPE_DEPTH = 1;
wire [33:0] fin_atree_l_0_n_1_n;
sadd_lpm_cen Uadd_cen_l_0_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(lut_val_2_n), .bin(lut_val_3_n), .res(fin_atree_l_0_n_1_n) );
defparam Uadd_cen_l_0_n_1_n.IN_WIDTH = 33;
defparam Uadd_cen_l_0_n_1_n.PIPE_DEPTH = 1;
wire [33:0] fin_atree_l_0_n_2_n;
sadd_lpm_cen Uadd_cen_l_0_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(lut_val_4_n), .bin(lut_val_5_n), .res(fin_atree_l_0_n_2_n) );
defparam Uadd_cen_l_0_n_2_n.IN_WIDTH = 33;
defparam Uadd_cen_l_0_n_2_n.PIPE_DEPTH = 1;
wire [33:0] fin_atree_l_0_n_3_n;
sadd_lpm_cen Uadd_cen_l_0_n_3_n (.clk(clk), .gclk_en(clk_en), .ain(lut_val_6_n), .bin(lut_val_7_n), .res(fin_atree_l_0_n_3_n) );
defparam Uadd_cen_l_0_n_3_n.IN_WIDTH = 33;
defparam Uadd_cen_l_0_n_3_n.PIPE_DEPTH = 1;
wire [33:0] fin_atree_l_0_n_4_n;
sadd_lpm_cen Uadd_cen_l_0_n_4_n (.clk(clk), .gclk_en(clk_en), .ain(lut_val_8_n), .bin(lut_val_9_n), .res(fin_atree_l_0_n_4_n) );
defparam Uadd_cen_l_0_n_4_n.IN_WIDTH = 33;
defparam Uadd_cen_l_0_n_4_n.PIPE_DEPTH = 1;
wire [33:0] fin_atree_l_0_n_5_n;
sadd_lpm_cen Uadd_cen_l_0_n_5_n (.clk(clk), .gclk_en(clk_en), .ain(lut_val_10_n), .bin(33'd0), .res(fin_atree_l_0_n_5_n) );
defparam Uadd_cen_l_0_n_5_n.IN_WIDTH = 33;
defparam Uadd_cen_l_0_n_5_n.PIPE_DEPTH = 1;
wire [34:0] fin_atree_l_1_n_0_n;
sadd_lpm_cen Uadd_cen_l_1_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(fin_atree_l_0_n_0_n), .bin(fin_atree_l_0_n_1_n), .res(fin_atree_l_1_n_0_n) );
defparam Uadd_cen_l_1_n_0_n.IN_WIDTH = 34;
defparam Uadd_cen_l_1_n_0_n.PIPE_DEPTH = 1;
wire [34:0] fin_atree_l_1_n_1_n;
sadd_lpm_cen Uadd_cen_l_1_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(fin_atree_l_0_n_2_n), .bin(fin_atree_l_0_n_3_n), .res(fin_atree_l_1_n_1_n) );
defparam Uadd_cen_l_1_n_1_n.IN_WIDTH = 34;
defparam Uadd_cen_l_1_n_1_n.PIPE_DEPTH = 1;
wire [34:0] fin_atree_l_1_n_2_n;
sadd_lpm_cen Uadd_cen_l_1_n_2_n (.clk(clk), .gclk_en(clk_en), .ain(fin_atree_l_0_n_4_n), .bin(fin_atree_l_0_n_5_n), .res(fin_atree_l_1_n_2_n) );
defparam Uadd_cen_l_1_n_2_n.IN_WIDTH = 34;
defparam Uadd_cen_l_1_n_2_n.PIPE_DEPTH = 1;
wire [35:0] fin_atree_l_2_n_0_n;
sadd_lpm_cen Uadd_cen_l_2_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(fin_atree_l_1_n_0_n), .bin(fin_atree_l_1_n_1_n), .res(fin_atree_l_2_n_0_n) );
defparam Uadd_cen_l_2_n_0_n.IN_WIDTH = 35;
defparam Uadd_cen_l_2_n_0_n.PIPE_DEPTH = 1;
wire [35:0] fin_atree_l_2_n_1_n;
sadd_lpm_cen Uadd_cen_l_2_n_1_n (.clk(clk), .gclk_en(clk_en), .ain(fin_atree_l_1_n_2_n), .bin(35'd0), .res(fin_atree_l_2_n_1_n) );
defparam Uadd_cen_l_2_n_1_n.IN_WIDTH = 35;
defparam Uadd_cen_l_2_n_1_n.PIPE_DEPTH = 1;
wire [36:0] fin_atree_l_3_n_0_n;
sadd_lpm_cen Uadd_cen_l_3_n_0_n (.clk(clk), .gclk_en(clk_en), .ain(fin_atree_l_2_n_0_n), .bin(fin_atree_l_2_n_1_n), .res(fin_atree_l_3_n_0_n) );
defparam Uadd_cen_l_3_n_0_n.IN_WIDTH = 36;
defparam Uadd_cen_l_3_n_0_n.PIPE_DEPTH = 1;
wire [36:0] mac_res;
assign mac_res=fin_atree_l_3_n_0_n;
wire [36:0] atree_res;
mac_tl Umtl (.clk(clk),
.data_in(mac_res),
.data_out(atree_res));
defparam Umtl.DATA_WIDTH = 37;
// ---- Adder Tree Complete ----
wire [30:0] fir_int_res;
assign fir_int_res = atree_res [30:0];
// ---- Limiting Precision ----
wire [30:0]fir_int_res_fill;
assign fir_int_res_fill = fir_int_res[30 :0];
parameter TOT_WIDTH = ACCUM_WIDTH;
assign fir_result = fir_int_res_fill[TOT_WIDTH-MSB_RM-1:LSB_RM];
wire pre_rdy;
assign rdy_to_ld = pre_rdy;
assign done = done_int;
par_ctrl Uctrl(.rst(rst),
.clk(clk),
.clk_en(clk_en),
.done(done_int),
.rdy_int(rdy_int),
.rdy_to_ld(pre_rdy));
defparam Uctrl.REG_LEN = 11;
defparam Uctrl.REG_BIT = 4;
defparam Uctrl.CH_WIDTH =0;
defparam Uctrl.NUM_CH =1;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:41:46 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474,
n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
DP_OP_15J51_123_3372_n8, DP_OP_15J51_123_3372_n7,
DP_OP_15J51_123_3372_n6, DP_OP_15J51_123_3372_n5,
DP_OP_15J51_123_3372_n4, intadd_57_B_12_, intadd_57_B_11_,
intadd_57_B_10_, intadd_57_B_9_, intadd_57_B_8_, intadd_57_B_7_,
intadd_57_B_6_, intadd_57_B_5_, intadd_57_B_4_, intadd_57_B_3_,
intadd_57_B_2_, intadd_57_B_1_, intadd_57_B_0_, intadd_57_CI,
intadd_57_SUM_12_, intadd_57_SUM_11_, intadd_57_SUM_10_,
intadd_57_SUM_9_, intadd_57_SUM_8_, intadd_57_SUM_7_,
intadd_57_SUM_6_, intadd_57_SUM_5_, intadd_57_SUM_4_,
intadd_57_SUM_3_, intadd_57_SUM_2_, intadd_57_SUM_1_,
intadd_57_SUM_0_, intadd_57_n13, intadd_57_n12, intadd_57_n11,
intadd_57_n10, intadd_57_n9, intadd_57_n8, intadd_57_n7, intadd_57_n6,
intadd_57_n5, intadd_57_n4, intadd_57_n3, intadd_57_n2, intadd_57_n1,
intadd_58_A_2_, intadd_58_A_1_, intadd_58_B_2_, intadd_58_B_1_,
intadd_58_B_0_, intadd_58_CI, intadd_58_SUM_2_, intadd_58_SUM_1_,
intadd_58_SUM_0_, intadd_58_n3, intadd_58_n2, intadd_58_n1,
intadd_59_A_2_, intadd_59_A_1_, intadd_59_B_1_, intadd_59_B_0_,
intadd_59_CI, intadd_59_SUM_2_, intadd_59_SUM_1_, intadd_59_SUM_0_,
intadd_59_n3, intadd_59_n2, intadd_59_n1, n873, n874, n875, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1323, n1324, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1351, n1352, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1576, n1577, n1578, n1579, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1605, n1606, n1607;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:1] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [24:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1578), .QN(
n889) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1579),
.QN(n879) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1581),
.QN(n880) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1577),
.QN(n881) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1576), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1579), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1581),
.Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n875), .QN(n885) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1592),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n875), .Q(
Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1579),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1582),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n874), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1584), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1601), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1588), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1589), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1592), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1585), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n874), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n922), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n875), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n875), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1582), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n922), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n875), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n875), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1579), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1581), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1577), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1579), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1581), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1577), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n874), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1585), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1592), .QN(n890)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1589), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n874), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1601), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1588), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1588), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1584), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n874), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1585), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1584), .Q(
DMP_SFG[2]), .QN(n1559) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1585), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n874), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1597), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1587), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1597), .Q(
DMP_SFG[6]), .QN(n1560) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1587), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1587), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1587), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1587), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1587), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1586), .Q(
DMP_SFG[10]), .QN(n1517) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1585), .Q(
DMP_SFG[11]), .QN(n1516) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1588), .Q(
DMP_SFG[12]), .QN(n1522) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1584), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n874), .Q(
DMP_SFG[13]), .QN(n1521) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1585), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1592), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1589), .Q(
DMP_SFG[14]), .QN(n1525) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n874), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1584), .Q(
DMP_SFG[15]), .QN(n1544) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1585), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1592), .Q(
DMP_SFG[16]), .QN(n1543) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1589), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n874), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1601), .Q(
DMP_SFG[17]), .QN(n1555) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1584), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n874), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1585), .Q(
DMP_SFG[18]), .QN(n1554) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1586), .Q(
DMP_SFG[19]), .QN(n1563) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n874), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1602), .Q(
DMP_SFG[20]), .QN(n1562) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1602), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1597), .Q(
DMP_SFG[21]), .QN(n1573) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1587), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n874), .Q(
DMP_SFG[22]), .QN(n1572) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1587), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1587), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1602), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1586), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n874), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1590), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n874), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1590), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1586), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1594), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1595), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1598), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1591), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n921), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n921), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1594), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1598), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1591), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n921), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1579), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1588), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1601), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1584), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1588), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1585), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1592), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1589), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n874), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1601), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1592), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1585), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1589), .QN(
n892) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1601), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1579), .QN(
n891) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1577), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n874), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1584), .QN(
n887) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1599), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1596), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1600),
.QN(n888) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1593), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1599), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1596), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1591), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n921), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1594),
.QN(n886) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1589), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1591), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1595), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1601), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1578), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1583), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1596), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1600), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1593), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1599), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1596), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1600), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1593), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1576), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1599), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1596), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1600), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1584), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n874), .Q(
LZD_output_NRM2_EW[3]), .QN(n1526) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1586), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1597), .Q(
LZD_output_NRM2_EW[2]), .QN(n1523) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1586), .Q(
LZD_output_NRM2_EW[1]), .QN(n1518) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1597), .Q(
LZD_output_NRM2_EW[4]), .QN(n1527) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n921), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1598), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1591), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1576), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n921), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1594), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1595), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1598), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1591), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1585), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1593), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1601), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1589), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1599), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1596), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1600), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1593), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1585), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1599), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1596), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1600), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1593), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1600), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[0]), .QN(n911) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[1]), .QN(n912) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[2]), .QN(n913) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[3]), .QN(n917) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[4]), .QN(n918) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[6]), .QN(n915) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[7]), .QN(n914) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[8]), .QN(n907) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1601), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1584), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n874), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[22]), .QN(n908) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[23]), .QN(n909) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[24]), .QN(n910) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n874), .Q(
DmP_mant_SFG_SWR[25]) );
CMPR32X2TS intadd_57_U14 ( .A(n1517), .B(intadd_57_B_0_), .C(intadd_57_CI),
.CO(intadd_57_n13), .S(intadd_57_SUM_0_) );
CMPR32X2TS intadd_57_U13 ( .A(n1516), .B(intadd_57_B_1_), .C(intadd_57_n13),
.CO(intadd_57_n12), .S(intadd_57_SUM_1_) );
CMPR32X2TS intadd_57_U12 ( .A(n1522), .B(intadd_57_B_2_), .C(intadd_57_n12),
.CO(intadd_57_n11), .S(intadd_57_SUM_2_) );
CMPR32X2TS intadd_57_U11 ( .A(n1521), .B(intadd_57_B_3_), .C(intadd_57_n11),
.CO(intadd_57_n10), .S(intadd_57_SUM_3_) );
CMPR32X2TS intadd_57_U10 ( .A(n1525), .B(intadd_57_B_4_), .C(intadd_57_n10),
.CO(intadd_57_n9), .S(intadd_57_SUM_4_) );
CMPR32X2TS intadd_57_U9 ( .A(n1544), .B(intadd_57_B_5_), .C(intadd_57_n9),
.CO(intadd_57_n8), .S(intadd_57_SUM_5_) );
CMPR32X2TS intadd_57_U8 ( .A(n1543), .B(intadd_57_B_6_), .C(intadd_57_n8),
.CO(intadd_57_n7), .S(intadd_57_SUM_6_) );
CMPR32X2TS intadd_57_U7 ( .A(n1555), .B(intadd_57_B_7_), .C(intadd_57_n7),
.CO(intadd_57_n6), .S(intadd_57_SUM_7_) );
CMPR32X2TS intadd_57_U6 ( .A(n1554), .B(intadd_57_B_8_), .C(intadd_57_n6),
.CO(intadd_57_n5), .S(intadd_57_SUM_8_) );
CMPR32X2TS intadd_57_U5 ( .A(n1563), .B(intadd_57_B_9_), .C(intadd_57_n5),
.CO(intadd_57_n4), .S(intadd_57_SUM_9_) );
CMPR32X2TS intadd_57_U4 ( .A(n1562), .B(intadd_57_B_10_), .C(intadd_57_n4),
.CO(intadd_57_n3), .S(intadd_57_SUM_10_) );
CMPR32X2TS intadd_57_U3 ( .A(n1573), .B(intadd_57_B_11_), .C(intadd_57_n3),
.CO(intadd_57_n2), .S(intadd_57_SUM_11_) );
CMPR32X2TS intadd_57_U2 ( .A(n1572), .B(intadd_57_B_12_), .C(intadd_57_n2),
.CO(intadd_57_n1), .S(intadd_57_SUM_12_) );
CMPR32X2TS intadd_58_U4 ( .A(n1560), .B(intadd_58_B_0_), .C(intadd_58_CI),
.CO(intadd_58_n3), .S(intadd_58_SUM_0_) );
CMPR32X2TS intadd_58_U3 ( .A(intadd_58_A_1_), .B(intadd_58_B_1_), .C(
intadd_58_n3), .CO(intadd_58_n2), .S(intadd_58_SUM_1_) );
CMPR32X2TS intadd_58_U2 ( .A(intadd_58_A_2_), .B(intadd_58_B_2_), .C(
intadd_58_n2), .CO(intadd_58_n1), .S(intadd_58_SUM_2_) );
CMPR32X2TS intadd_59_U4 ( .A(n1559), .B(intadd_59_B_0_), .C(intadd_59_CI),
.CO(intadd_59_n3), .S(intadd_59_SUM_0_) );
CMPR32X2TS intadd_59_U3 ( .A(intadd_59_A_1_), .B(intadd_59_B_1_), .C(
intadd_59_n3), .CO(intadd_59_n2), .S(intadd_59_SUM_1_) );
CMPR32X2TS intadd_59_U2 ( .A(intadd_59_A_2_), .B(n895), .C(intadd_59_n2),
.CO(intadd_59_n1), .S(intadd_59_SUM_2_) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1593), .Q(
OP_FLAG_SFG), .QN(n1493) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1597), .Q(
Data_array_SWR[10]), .QN(n1570) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1591), .Q(
DmP_EXP_EWSW[25]), .QN(n1569) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1585), .Q(
DMP_EXP_EWSW[26]), .QN(n1568) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1577),
.Q(intDX_EWSW[24]), .QN(n1567) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n874), .Q(
Data_array_SWR[13]), .QN(n1566) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1601), .Q(
Data_array_SWR[11]), .QN(n1565) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[26]), .QN(n1564) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n921), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1561) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1576), .Q(
Data_array_SWR[22]), .QN(n1558) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1588), .Q(
DMP_EXP_EWSW[25]), .QN(n1557) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1556) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1553) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1585),
.Q(intDY_EWSW[18]), .QN(n1552) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1581),
.Q(intDY_EWSW[30]), .QN(n1551) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[26]), .QN(n1550) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1587), .Q(
intDY_EWSW[8]), .QN(n1549) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1578), .Q(
intDY_EWSW[1]), .QN(n1548) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n875), .Q(
intDY_EWSW[17]), .QN(n1547) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1577), .Q(
intDY_EWSW[0]), .QN(n1546) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[25]), .QN(n1545) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1597), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1542) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n874), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1541) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1583),
.Q(intDY_EWSW[27]), .QN(n1540) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n922), .Q(
intDY_EWSW[23]), .QN(n1539) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1578),
.Q(intDY_EWSW[28]), .QN(n1538) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n875), .Q(
intDY_EWSW[7]), .QN(n1537) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n875), .Q(
intDY_EWSW[14]), .QN(n1535) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n874), .Q(
intDY_EWSW[12]), .QN(n1534) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n875), .Q(
intDY_EWSW[4]), .QN(n1533) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1583), .Q(
intDY_EWSW[2]), .QN(n1532) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[13]), .QN(n1530) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1582), .Q(
intDY_EWSW[9]), .QN(n1529) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1581), .Q(
intDY_EWSW[6]), .QN(n1528) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1578), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1524) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[28]), .QN(n1520) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[16]), .QN(n1519) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1602), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1515) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1579), .Q(
intDX_EWSW[6]), .QN(n1514) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1513) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1576), .Q(
shift_value_SHT2_EWR[3]), .QN(n1512) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1586), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1511) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n922), .Q(
shift_value_SHT2_EWR[4]), .QN(n1510) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1576), .Q(
intDX_EWSW[5]), .QN(n1509) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1508) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1598), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1507) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1594), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1506) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1576), .Q(
n1488), .QN(n1571) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[26]), .QN(n1505) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[25]), .QN(n1504) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1503) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1584), .Q(
DMP_EXP_EWSW[24]), .QN(n1502) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[24]), .QN(n1501) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1579),
.Q(intDY_EWSW[29]), .QN(n1500) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[19]), .QN(n1499) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n875), .Q(
intDY_EWSW[22]), .QN(n1498) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1587),
.Q(intDY_EWSW[16]), .QN(n1497) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n922), .Q(
intDY_EWSW[5]), .QN(n1496) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1579), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1495) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1581), .Q(
intDX_EWSW[7]), .QN(n1494) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1578), .Q(
intDX_EWSW[4]), .QN(n1492) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n921), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1491) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n921), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1490) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1598), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1489) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n875), .Q(
intDY_EWSW[24]), .QN(n1487) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1486) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n874), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1485) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1484) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1483) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1591), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1482) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1591), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1481) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1480) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1479) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n874), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1478) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1477) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1576),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1583), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1577), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1576), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1579), .Q(
Data_array_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1594), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1578), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1581), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1576), .Q(
intDX_EWSW[9]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1581), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n875), .Q(
Data_array_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1578), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1577),
.Q(intDX_EWSW[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[27]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1577), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1597), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n922), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1589), .Q(
Data_array_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n921), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n875), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n922), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n875), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1586), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1597), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1588), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1577),
.Q(intDX_EWSW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1594), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1595), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1598), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1583), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1599), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1595), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1596), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n875), .Q(
intDY_EWSW[10]), .QN(n878) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1593), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1581), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1591), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1599), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1596), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n921), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1600), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1585), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1592), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1589), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1601), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1585), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1601), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n875), .Q(
Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n875), .Q(
intDY_EWSW[15]), .QN(n1607) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[20]), .QN(n1536) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n1581),
.Q(intDY_EWSW[21]), .QN(n1531) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1592), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1586), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1586), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1587), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1579),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1576),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n922), .Q(
intDY_EWSW[3]), .QN(n1605) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n875), .Q(
intDY_EWSW[11]), .QN(n1606) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n875), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1583), .Q(
Data_array_SWR[20]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n875), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n922), .Q(
Data_array_SWR[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n921), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[5]), .QN(n916) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[9]), .QN(n877) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1602), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n875), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n922), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n875), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[27]) );
ADDFX1TS DP_OP_15J51_123_3372_U8 ( .A(n1518), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J51_123_3372_n8), .CO(DP_OP_15J51_123_3372_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J51_123_3372_U7 ( .A(n1523), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J51_123_3372_n7), .CO(DP_OP_15J51_123_3372_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J51_123_3372_U6 ( .A(n1526), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J51_123_3372_n6), .CO(DP_OP_15J51_123_3372_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J51_123_3372_U5 ( .A(n1527), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J51_123_3372_n5), .CO(DP_OP_15J51_123_3372_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1577), .Q(
Shift_reg_FLAGS_7[1]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1583), .Q(
busy), .QN(n1574) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1583), .Q(
Shift_reg_FLAGS_7_6), .QN(n919) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1576), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1583), .Q(
n873), .QN(n1603) );
BUFX4TS U897 ( .A(n921), .Y(n922) );
NAND2X4TS U898 ( .A(n1150), .B(n1280), .Y(n1135) );
CLKINVX6TS U899 ( .A(rst), .Y(n921) );
AOI222X4TS U900 ( .A0(Data_array_SWR[23]), .A1(n1386), .B0(
Data_array_SWR[19]), .B1(n1401), .C0(Data_array_SWR[15]), .C1(n1400),
.Y(n1431) );
AOI211X2TS U901 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1116), .B0(n1254), .C0(
n1115), .Y(n1131) );
OAI222X1TS U902 ( .A0(n1565), .A1(n1297), .B0(n1288), .B1(n1286), .C0(n1147),
.C1(n1285), .Y(n783) );
OAI222X1TS U903 ( .A0(n1297), .A1(n1566), .B0(n1288), .B1(n1285), .C0(n1147),
.C1(n1278), .Y(n785) );
OAI222X1TS U904 ( .A0(n1558), .A1(n1297), .B0(n1288), .B1(n1275), .C0(n1147),
.C1(n1274), .Y(n794) );
CLKINVX6TS U905 ( .A(n1291), .Y(n1147) );
NOR2XLTS U906 ( .A(n1150), .B(n1192), .Y(n1151) );
CLKINVX6TS U907 ( .A(n1282), .Y(n1117) );
NAND3XLTS U908 ( .A(n1123), .B(n1108), .C(n1243), .Y(n1254) );
BUFX4TS U909 ( .A(n996), .Y(n1012) );
NOR2X4TS U910 ( .A(n995), .B(n919), .Y(n996) );
AND2X4TS U911 ( .A(Shift_reg_FLAGS_7_6), .B(n995), .Y(n1087) );
CLKINVX3TS U912 ( .A(n1269), .Y(n1266) );
CLKINVX3TS U913 ( .A(n1267), .Y(n1272) );
BUFX6TS U914 ( .A(n1321), .Y(n1454) );
NOR2X6TS U915 ( .A(n1473), .B(n1411), .Y(n1364) );
BUFX6TS U916 ( .A(n1581), .Y(n874) );
INVX6TS U917 ( .A(Shift_reg_FLAGS_7_6), .Y(n997) );
NOR2X6TS U918 ( .A(shift_value_SHT2_EWR[4]), .B(n1380), .Y(n1363) );
NAND3XLTS U919 ( .A(n1507), .B(n1490), .C(n1482), .Y(n1240) );
BUFX6TS U920 ( .A(n922), .Y(n875) );
NAND2BXLTS U921 ( .AN(n906), .B(intDY_EWSW[2]), .Y(n945) );
NAND2BXLTS U922 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n979) );
NAND2BXLTS U923 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n933) );
NAND2BXLTS U924 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n958) );
OAI2BB2XLTS U925 ( .B0(intDY_EWSW[14]), .B1(n964), .A0N(intDX_EWSW[15]),
.A1N(n1607), .Y(n965) );
NAND2BXLTS U926 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n954) );
NAND2BXLTS U927 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n973) );
INVX2TS U928 ( .A(n882), .Y(n895) );
AO22XLTS U929 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n1354), .B0(n1351), .B1(n915),
.Y(n882) );
AOI222X4TS U930 ( .A0(Data_array_SWR[13]), .A1(n1363), .B0(
Data_array_SWR[21]), .B1(n1427), .C0(Data_array_SWR[17]), .C1(n1426),
.Y(n1376) );
AOI222X4TS U931 ( .A0(Data_array_SWR[22]), .A1(n1427), .B0(
Data_array_SWR[18]), .B1(n1426), .C0(Data_array_SWR[14]), .C1(n1363),
.Y(n1372) );
AOI222X4TS U932 ( .A0(Data_array_SWR[23]), .A1(n1427), .B0(
Data_array_SWR[19]), .B1(n1426), .C0(Data_array_SWR[15]), .C1(n1363),
.Y(n1368) );
AOI222X4TS U933 ( .A0(Data_array_SWR[20]), .A1(n1426), .B0(
Data_array_SWR[16]), .B1(n1363), .C0(Data_array_SWR[24]), .C1(n1427),
.Y(n1369) );
NAND2BXLTS U934 ( .AN(n1256), .B(n928), .Y(n931) );
AOI222X1TS U935 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1279), .C1(n897), .Y(n1161) );
AOI222X1TS U936 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1279), .C1(DmP_mant_SHT1_SW[3]), .Y(n1154)
);
AOI222X1TS U937 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1279), .C1(DmP_mant_SHT1_SW[8]), .Y(n1168)
);
AOI222X1TS U938 ( .A0(n1216), .A1(DMP_SFG[1]), .B0(n1216), .B1(n893), .C0(
DMP_SFG[1]), .C1(n893), .Y(intadd_59_CI) );
AOI222X4TS U939 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1279), .C1(DmP_mant_SHT1_SW[17]), .Y(n1184) );
AOI222X1TS U940 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1117), .B0(n1284), .B1(n900), .C0(n1279), .C1(DmP_mant_SHT1_SW[20]), .Y(n1211) );
AOI222X1TS U941 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1279), .C1(DmP_mant_SHT1_SW[18]), .Y(n1215) );
AOI222X1TS U942 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1279), .C1(DmP_mant_SHT1_SW[7]), .Y(n1179)
);
AOI222X1TS U943 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1117), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1279), .C0(n1284), .C1(
DmP_mant_SHT1_SW[13]), .Y(n1209) );
AOI222X1TS U944 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1279), .C1(DmP_mant_SHT1_SW[16]), .Y(n1206) );
AOI211X1TS U945 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n1336), .B0(n1279), .C0(
n1193), .Y(n1273) );
AOI222X4TS U946 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1187), .C1(DmP_mant_SHT1_SW[21]), .Y(n1194) );
AO22XLTS U947 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n1351), .B0(n1354), .B1(n914),
.Y(n883) );
AO22XLTS U948 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n1351), .B0(n1354), .B1(n917),
.Y(n884) );
INVX4TS U949 ( .A(n1469), .Y(n1476) );
AOI222X1TS U950 ( .A0(n1388), .A1(n1473), .B0(Data_array_SWR[8]), .B1(n1435),
.C0(n1387), .C1(n1408), .Y(n1458) );
AOI222X1TS U951 ( .A0(n1388), .A1(n1434), .B0(Data_array_SWR[8]), .B1(n1364),
.C0(n1387), .C1(n1407), .Y(n1443) );
AOI222X1TS U952 ( .A0(n1383), .A1(n1473), .B0(Data_array_SWR[9]), .B1(n1435),
.C0(n1382), .C1(n1408), .Y(n1456) );
AOI222X1TS U953 ( .A0(n1383), .A1(n1434), .B0(Data_array_SWR[9]), .B1(n1364),
.C0(n1382), .C1(n1407), .Y(n1444) );
AOI222X1TS U954 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1117), .B0(n1284), .B1(
n899), .C0(n1279), .C1(DmP_mant_SHT1_SW[10]), .Y(n1205) );
AOI222X1TS U955 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1117), .B0(n1284), .B1(
n898), .C0(n1279), .C1(DmP_mant_SHT1_SW[12]), .Y(n1202) );
AO22XLTS U956 ( .A0(n1267), .A1(Data_X[19]), .B0(n1266), .B1(intDX_EWSW[19]),
.Y(n843) );
AO22XLTS U957 ( .A0(n1451), .A1(DMP_SHT2_EWSW[0]), .B0(n1321), .B1(
DMP_SFG[0]), .Y(n717) );
AO22XLTS U958 ( .A0(n1329), .A1(DmP_EXP_EWSW[0]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U959 ( .A0(n1329), .A1(DmP_EXP_EWSW[1]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AO22XLTS U960 ( .A0(n1329), .A1(DmP_EXP_EWSW[2]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U961 ( .A0(n1329), .A1(DmP_EXP_EWSW[6]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U962 ( .A0(n1334), .A1(DmP_EXP_EWSW[15]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U963 ( .A0(n1329), .A1(DmP_EXP_EWSW[10]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U964 ( .A0(n1329), .A1(DmP_EXP_EWSW[12]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
AO22XLTS U965 ( .A0(n1329), .A1(DmP_EXP_EWSW[18]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U966 ( .A0(n1334), .A1(DmP_EXP_EWSW[13]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U967 ( .A0(n1329), .A1(DmP_EXP_EWSW[8]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U968 ( .A0(n1334), .A1(DmP_EXP_EWSW[21]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U969 ( .A0(n1329), .A1(DmP_EXP_EWSW[3]), .B0(n1571), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
AO22XLTS U970 ( .A0(n1329), .A1(DmP_EXP_EWSW[7]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AO22XLTS U971 ( .A0(n1329), .A1(DmP_EXP_EWSW[16]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U972 ( .A0(n1334), .A1(DmP_EXP_EWSW[20]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U973 ( .A0(n1263), .A1(n1359), .B0(n1264), .B1(n896), .Y(n865) );
AO22XLTS U974 ( .A0(n1270), .A1(Data_X[31]), .B0(n1268), .B1(intDX_EWSW[31]),
.Y(n831) );
AO22XLTS U975 ( .A0(n1451), .A1(DMP_SHT2_EWSW[1]), .B0(n1469), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U976 ( .A0(n1329), .A1(DmP_EXP_EWSW[11]), .B0(n1571), .B1(n898),
.Y(n587) );
AO22XLTS U977 ( .A0(n1329), .A1(DmP_EXP_EWSW[9]), .B0(n1323), .B1(n899), .Y(
n591) );
AO22XLTS U978 ( .A0(n1329), .A1(DmP_EXP_EWSW[5]), .B0(n1333), .B1(n901), .Y(
n599) );
AO22XLTS U979 ( .A0(n1329), .A1(DmP_EXP_EWSW[4]), .B0(n1331), .B1(n897), .Y(
n601) );
AO22XLTS U980 ( .A0(n1264), .A1(busy), .B0(n1263), .B1(n896), .Y(n866) );
OAI222X1TS U981 ( .A0(n1570), .A1(n1297), .B0(n1288), .B1(n1287), .C0(n1147),
.C1(n1286), .Y(n781) );
AOI221X1TS U982 ( .A0(n1550), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]), .B1(
n1540), .C0(n1033), .Y(n1037) );
OAI21X2TS U983 ( .A0(intDX_EWSW[26]), .A1(n1550), .B0(n933), .Y(n1033) );
NOR2BX2TS U984 ( .AN(n1252), .B(n1251), .Y(n1112) );
NAND4XLTS U985 ( .A(n1489), .B(n1481), .C(n1477), .D(n1506), .Y(n1251) );
BUFX4TS U986 ( .A(n1594), .Y(n1589) );
OAI211XLTS U987 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1107), .B0(n1247), .C0(
n1513), .Y(n1108) );
NOR2X2TS U988 ( .A(Raw_mant_NRM_SWR[6]), .B(n1106), .Y(n1247) );
BUFX4TS U989 ( .A(n1595), .Y(n1592) );
BUFX4TS U990 ( .A(n1598), .Y(n1585) );
BUFX4TS U991 ( .A(n1591), .Y(n1601) );
BUFX4TS U992 ( .A(n1590), .Y(n1588) );
BUFX6TS U993 ( .A(n1321), .Y(n1469) );
CLKINVX6TS U994 ( .A(n1323), .Y(n1332) );
BUFX6TS U995 ( .A(n1571), .Y(n1331) );
BUFX4TS U996 ( .A(n1583), .Y(n1590) );
BUFX4TS U997 ( .A(n1576), .Y(n1586) );
BUFX4TS U998 ( .A(n1579), .Y(n1587) );
BUFX4TS U999 ( .A(n1592), .Y(n1597) );
BUFX4TS U1000 ( .A(n875), .Y(n1583) );
INVX2TS U1001 ( .A(n884), .Y(n893) );
INVX2TS U1002 ( .A(n883), .Y(n894) );
NOR2X2TS U1003 ( .A(Raw_mant_NRM_SWR[13]), .B(n1241), .Y(n1122) );
BUFX6TS U1004 ( .A(n920), .Y(n1270) );
BUFX4TS U1005 ( .A(n920), .Y(n1267) );
BUFX4TS U1006 ( .A(n920), .Y(n1269) );
BUFX4TS U1007 ( .A(n1582), .Y(n1581) );
BUFX4TS U1008 ( .A(n875), .Y(n1579) );
BUFX4TS U1009 ( .A(n922), .Y(n1576) );
BUFX4TS U1010 ( .A(n1588), .Y(n1578) );
NOR2X4TS U1011 ( .A(shift_value_SHT2_EWR[4]), .B(n1473), .Y(n1408) );
BUFX6TS U1012 ( .A(left_right_SHT2), .Y(n1473) );
CLKINVX6TS U1013 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1336) );
INVX2TS U1014 ( .A(n889), .Y(n896) );
INVX2TS U1015 ( .A(n892), .Y(n897) );
INVX2TS U1016 ( .A(n888), .Y(n898) );
INVX2TS U1017 ( .A(n887), .Y(n899) );
INVX2TS U1018 ( .A(n886), .Y(n900) );
INVX2TS U1019 ( .A(n891), .Y(n901) );
INVX2TS U1020 ( .A(n890), .Y(n902) );
NOR4BX2TS U1021 ( .AN(n1128), .B(n1127), .C(n1126), .D(n1125), .Y(n1150) );
BUFX4TS U1022 ( .A(n1087), .Y(n1093) );
BUFX6TS U1023 ( .A(n1129), .Y(n1288) );
BUFX4TS U1024 ( .A(n1365), .Y(n1435) );
BUFX4TS U1025 ( .A(n1362), .Y(n1426) );
INVX6TS U1026 ( .A(n1603), .Y(n1359) );
BUFX6TS U1027 ( .A(n1132), .Y(n1284) );
BUFX6TS U1028 ( .A(n1187), .Y(n1279) );
CLKINVX6TS U1029 ( .A(n1270), .Y(n1268) );
INVX3TS U1030 ( .A(n1355), .Y(n1354) );
CLKINVX3TS U1031 ( .A(n1469), .Y(n1471) );
AOI222X4TS U1032 ( .A0(Data_array_SWR[20]), .A1(n1401), .B0(
Data_array_SWR[16]), .B1(n1400), .C0(Data_array_SWR[24]), .C1(n1386),
.Y(n1423) );
INVX2TS U1033 ( .A(n885), .Y(n903) );
AOI32X1TS U1034 ( .A0(n1552), .A1(n979), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1499), .Y(n980) );
AOI221X1TS U1035 ( .A0(n1552), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1499), .C0(n1040), .Y(n1045) );
AOI221X1TS U1036 ( .A0(n878), .A1(n905), .B0(intDX_EWSW[11]), .B1(n1606),
.C0(n1048), .Y(n1053) );
AOI221X1TS U1037 ( .A0(n1551), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1547), .C0(n1039), .Y(n1046) );
AOI221X4TS U1038 ( .A0(intDX_EWSW[30]), .A1(n1551), .B0(intDX_EWSW[29]),
.B1(n1500), .C0(n938), .Y(n940) );
INVX2TS U1039 ( .A(n879), .Y(n904) );
INVX2TS U1040 ( .A(n881), .Y(n905) );
AOI221X1TS U1041 ( .A0(n1532), .A1(n906), .B0(intDX_EWSW[3]), .B1(n1605),
.C0(n1056), .Y(n1061) );
INVX2TS U1042 ( .A(n880), .Y(n906) );
AOI221X1TS U1043 ( .A0(n1498), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1539), .C0(n1042), .Y(n1043) );
AOI221X1TS U1044 ( .A0(n1535), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1607), .C0(n1050), .Y(n1051) );
OAI211X2TS U1045 ( .A0(intDX_EWSW[20]), .A1(n1536), .B0(n987), .C0(n973),
.Y(n982) );
AOI221X1TS U1046 ( .A0(n1536), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1531), .C0(n1041), .Y(n1044) );
OAI211X2TS U1047 ( .A0(intDX_EWSW[12]), .A1(n1534), .B0(n968), .C0(n954),
.Y(n970) );
AOI221X1TS U1048 ( .A0(n1534), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1530), .C0(n1049), .Y(n1052) );
INVX1TS U1049 ( .A(DMP_SFG[3]), .Y(intadd_59_A_1_) );
INVX1TS U1050 ( .A(DMP_SFG[4]), .Y(intadd_59_A_2_) );
INVX1TS U1051 ( .A(DMP_SFG[7]), .Y(intadd_58_A_1_) );
INVX1TS U1052 ( .A(DMP_SFG[8]), .Y(intadd_58_A_2_) );
OAI31XLTS U1053 ( .A0(n1320), .A1(n1070), .A2(n1326), .B0(n1069), .Y(n720)
);
NOR2X2TS U1054 ( .A(n1300), .B(DMP_EXP_EWSW[23]), .Y(n1305) );
XNOR2X2TS U1055 ( .A(DMP_exp_NRM2_EW[6]), .B(n929), .Y(n1256) );
XNOR2X2TS U1056 ( .A(DMP_exp_NRM2_EW[0]), .B(n1236), .Y(n1218) );
INVX1TS U1057 ( .A(LZD_output_NRM2_EW[0]), .Y(n1236) );
XNOR2X2TS U1058 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J51_123_3372_n4), .Y(
n1220) );
CLKINVX6TS U1059 ( .A(n996), .Y(n1092) );
NOR2X4TS U1060 ( .A(shift_value_SHT2_EWR[4]), .B(n1434), .Y(n1407) );
CLKINVX6TS U1061 ( .A(n1473), .Y(n1434) );
AOI2BB2X2TS U1062 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1354), .A0N(n1354),
.A1N(DmP_mant_SFG_SWR[10]), .Y(intadd_58_B_2_) );
AOI2BB2X2TS U1063 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1351), .A0N(n1355),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1347) );
BUFX6TS U1064 ( .A(n1603), .Y(n1357) );
NOR2X4TS U1065 ( .A(n1361), .B(n1360), .Y(n1381) );
OAI2BB1X2TS U1066 ( .A0N(n1226), .A1N(n1225), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1360) );
AOI222X4TS U1067 ( .A0(DMP_SFG[5]), .A1(n894), .B0(DMP_SFG[5]), .B1(n1232),
.C0(n894), .C1(n1232), .Y(intadd_58_CI) );
AOI222X4TS U1068 ( .A0(DMP_SFG[9]), .A1(n1347), .B0(DMP_SFG[9]), .B1(n1235),
.C0(n1347), .C1(n1235), .Y(intadd_57_B_0_) );
AOI222X1TS U1069 ( .A0(n1402), .A1(n1434), .B0(n1364), .B1(Data_array_SWR[5]), .C0(n1403), .C1(n1407), .Y(n1440) );
AOI222X1TS U1070 ( .A0(n1402), .A1(n1473), .B0(Data_array_SWR[5]), .B1(n1435), .C0(n1403), .C1(n1408), .Y(n1464) );
AOI222X1TS U1071 ( .A0(n1410), .A1(n1434), .B0(n1364), .B1(Data_array_SWR[4]), .C0(n1409), .C1(n1407), .Y(n1439) );
AOI222X1TS U1072 ( .A0(n1410), .A1(n1473), .B0(Data_array_SWR[4]), .B1(n1435), .C0(n1409), .C1(n1408), .Y(n1466) );
AOI222X1TS U1073 ( .A0(n1392), .A1(n1434), .B0(Data_array_SWR[7]), .B1(n1364), .C0(n1391), .C1(n1407), .Y(n1442) );
AOI222X1TS U1074 ( .A0(n1392), .A1(n1473), .B0(Data_array_SWR[7]), .B1(n1435), .C0(n1391), .C1(n1408), .Y(n1460) );
AOI222X1TS U1075 ( .A0(n1397), .A1(n1434), .B0(Data_array_SWR[6]), .B1(n1364), .C0(n1396), .C1(n1407), .Y(n1441) );
AOI222X1TS U1076 ( .A0(n1397), .A1(n1473), .B0(Data_array_SWR[6]), .B1(n1435), .C0(n1396), .C1(n1408), .Y(n1462) );
AOI22X2TS U1077 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n1352), .B0(n1351), .B1(n877), .Y(intadd_58_B_1_) );
AOI22X2TS U1078 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1352), .B0(n1351), .B1(n916), .Y(intadd_59_B_1_) );
INVX4TS U1079 ( .A(n1355), .Y(n1352) );
INVX3TS U1080 ( .A(n1327), .Y(n1420) );
CLKINVX6TS U1081 ( .A(n1574), .Y(n1335) );
NOR2X2TS U1082 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1524), .Y(n1261) );
OAI21X2TS U1083 ( .A0(intDX_EWSW[18]), .A1(n1552), .B0(n979), .Y(n1040) );
NOR3X1TS U1084 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1252) );
NOR2X2TS U1085 ( .A(Raw_mant_NRM_SWR[12]), .B(n1114), .Y(n1246) );
AOI32X1TS U1086 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1297), .A2(n1336),
.B0(shift_value_SHT2_EWR[2]), .B1(n1294), .Y(n1296) );
NOR3X1TS U1087 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1512), .Y(n1362) );
NOR2X4TS U1088 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1400) );
AND2X2TS U1089 ( .A(beg_OP), .B(n1265), .Y(n920) );
NOR2XLTS U1090 ( .A(n1606), .B(intDX_EWSW[11]), .Y(n956) );
OAI21XLTS U1091 ( .A0(intDX_EWSW[15]), .A1(n1607), .B0(intDX_EWSW[14]), .Y(
n964) );
NOR2XLTS U1092 ( .A(n977), .B(intDY_EWSW[16]), .Y(n978) );
OAI21XLTS U1093 ( .A0(intDX_EWSW[23]), .A1(n1539), .B0(intDX_EWSW[22]), .Y(
n983) );
OAI21XLTS U1094 ( .A0(intDX_EWSW[21]), .A1(n1531), .B0(intDX_EWSW[20]), .Y(
n976) );
NOR2XLTS U1095 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1118) );
OR2X1TS U1096 ( .A(n931), .B(n1217), .Y(n1228) );
OAI21XLTS U1097 ( .A0(n1556), .A1(n1192), .B0(n1169), .Y(n1170) );
OAI21XLTS U1098 ( .A0(n1540), .A1(n1067), .B0(n1021), .Y(n560) );
OAI21XLTS U1099 ( .A0(n1605), .A1(n1324), .B0(n1020), .Y(n604) );
OAI21XLTS U1100 ( .A0(n1547), .A1(n1092), .B0(n1072), .Y(n736) );
OAI21XLTS U1101 ( .A0(n1605), .A1(n1326), .B0(n1029), .Y(n750) );
OAI211XLTS U1102 ( .A0(n1168), .A1(n1288), .B0(n1167), .C0(n1166), .Y(n780)
);
BUFX3TS U1103 ( .A(n921), .Y(n1591) );
BUFX3TS U1104 ( .A(n922), .Y(n1593) );
BUFX3TS U1105 ( .A(n922), .Y(n1594) );
BUFX3TS U1106 ( .A(n921), .Y(n1600) );
BUFX3TS U1107 ( .A(n921), .Y(n1596) );
BUFX3TS U1108 ( .A(n921), .Y(n1582) );
BUFX3TS U1109 ( .A(n922), .Y(n1599) );
BUFX3TS U1110 ( .A(n922), .Y(n1595) );
BUFX3TS U1111 ( .A(n1592), .Y(n1602) );
BUFX3TS U1112 ( .A(n1586), .Y(n1584) );
BUFX3TS U1113 ( .A(n1601), .Y(n1577) );
BUFX3TS U1114 ( .A(n921), .Y(n1598) );
INVX2TS U1115 ( .A(DP_OP_15J51_123_3372_n4), .Y(n923) );
NAND2X1TS U1116 ( .A(n1542), .B(n923), .Y(n929) );
NOR2XLTS U1117 ( .A(n1218), .B(exp_rslt_NRM2_EW1[1]), .Y(n926) );
INVX2TS U1118 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n925) );
INVX2TS U1119 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n924) );
NAND4BXLTS U1120 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n926), .C(n925), .D(n924),
.Y(n927) );
NOR2XLTS U1121 ( .A(n927), .B(n1220), .Y(n928) );
INVX2TS U1122 ( .A(n929), .Y(n930) );
NAND2X1TS U1123 ( .A(n1541), .B(n930), .Y(n1223) );
XNOR2X1TS U1124 ( .A(DMP_exp_NRM2_EW[7]), .B(n1223), .Y(n1217) );
CLKBUFX2TS U1125 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1327) );
NAND2X2TS U1126 ( .A(n1228), .B(n1327), .Y(n1257) );
OA22X1TS U1127 ( .A0(n1257), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n757) );
OA22X1TS U1128 ( .A0(n1257), .A1(n1220), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n756) );
OA22X1TS U1129 ( .A0(n1257), .A1(n1218), .B0(final_result_ieee[23]), .B1(
Shift_reg_FLAGS_7[0]), .Y(n761) );
OA22X1TS U1130 ( .A0(n1257), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n758) );
OA22X1TS U1131 ( .A0(n1257), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n760) );
OA22X1TS U1132 ( .A0(n1257), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n759) );
OAI21XLTS U1133 ( .A0(n1335), .A1(n1434), .B0(n1336), .Y(n829) );
NOR2X1TS U1134 ( .A(n1545), .B(intDX_EWSW[25]), .Y(n990) );
NOR2XLTS U1135 ( .A(n990), .B(intDY_EWSW[24]), .Y(n932) );
AOI22X1TS U1136 ( .A0(intDX_EWSW[25]), .A1(n1545), .B0(intDX_EWSW[24]), .B1(
n932), .Y(n936) );
NAND3XLTS U1137 ( .A(n1550), .B(n933), .C(intDX_EWSW[26]), .Y(n935) );
NAND2BXLTS U1138 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n934) );
OAI211XLTS U1139 ( .A0(n936), .A1(n1033), .B0(n935), .C0(n934), .Y(n941) );
NOR2X1TS U1140 ( .A(n1551), .B(intDX_EWSW[30]), .Y(n939) );
NOR2X1TS U1141 ( .A(n1500), .B(intDX_EWSW[29]), .Y(n937) );
AOI211X1TS U1142 ( .A0(intDY_EWSW[28]), .A1(n1520), .B0(n939), .C0(n937),
.Y(n989) );
NOR3XLTS U1143 ( .A(n1520), .B(n937), .C(intDY_EWSW[28]), .Y(n938) );
AOI2BB2X1TS U1144 ( .B0(n941), .B1(n989), .A0N(n940), .A1N(n939), .Y(n994)
);
NOR2X1TS U1145 ( .A(n1547), .B(intDX_EWSW[17]), .Y(n977) );
OAI22X1TS U1146 ( .A0(n878), .A1(n905), .B0(n1606), .B1(intDX_EWSW[11]), .Y(
n1048) );
INVX2TS U1147 ( .A(n1048), .Y(n961) );
OAI211XLTS U1148 ( .A0(intDX_EWSW[8]), .A1(n1549), .B0(n958), .C0(n961), .Y(
n972) );
OAI2BB1X1TS U1149 ( .A0N(n1509), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n942) );
OAI22X1TS U1150 ( .A0(intDY_EWSW[4]), .A1(n942), .B0(n1509), .B1(
intDY_EWSW[5]), .Y(n953) );
OAI2BB1X1TS U1151 ( .A0N(n1494), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n943) );
OAI22X1TS U1152 ( .A0(intDY_EWSW[6]), .A1(n943), .B0(n1494), .B1(
intDY_EWSW[7]), .Y(n952) );
OAI21XLTS U1153 ( .A0(intDX_EWSW[1]), .A1(n1548), .B0(n904), .Y(n944) );
OAI2BB2XLTS U1154 ( .B0(intDY_EWSW[0]), .B1(n944), .A0N(intDX_EWSW[1]),
.A1N(n1548), .Y(n946) );
OAI211XLTS U1155 ( .A0(n1605), .A1(intDX_EWSW[3]), .B0(n946), .C0(n945), .Y(
n949) );
OAI21XLTS U1156 ( .A0(intDX_EWSW[3]), .A1(n1605), .B0(n906), .Y(n947) );
AOI2BB2XLTS U1157 ( .B0(intDX_EWSW[3]), .B1(n1605), .A0N(intDY_EWSW[2]),
.A1N(n947), .Y(n948) );
AOI222X1TS U1158 ( .A0(intDY_EWSW[4]), .A1(n1492), .B0(n949), .B1(n948),
.C0(intDY_EWSW[5]), .C1(n1509), .Y(n951) );
AOI22X1TS U1159 ( .A0(intDY_EWSW[7]), .A1(n1494), .B0(intDY_EWSW[6]), .B1(
n1514), .Y(n950) );
OAI32X1TS U1160 ( .A0(n953), .A1(n952), .A2(n951), .B0(n950), .B1(n952), .Y(
n971) );
OA22X1TS U1161 ( .A0(n1535), .A1(intDX_EWSW[14]), .B0(n1607), .B1(
intDX_EWSW[15]), .Y(n968) );
OAI21XLTS U1162 ( .A0(intDX_EWSW[13]), .A1(n1530), .B0(intDX_EWSW[12]), .Y(
n955) );
OAI2BB2XLTS U1163 ( .B0(intDY_EWSW[12]), .B1(n955), .A0N(intDX_EWSW[13]),
.A1N(n1530), .Y(n967) );
NOR2XLTS U1164 ( .A(n956), .B(intDY_EWSW[10]), .Y(n957) );
AOI22X1TS U1165 ( .A0(intDX_EWSW[11]), .A1(n1606), .B0(n905), .B1(n957), .Y(
n963) );
NAND2BXLTS U1166 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n960) );
NAND3XLTS U1167 ( .A(n1549), .B(n958), .C(intDX_EWSW[8]), .Y(n959) );
AOI21X1TS U1168 ( .A0(n960), .A1(n959), .B0(n970), .Y(n962) );
OAI2BB2XLTS U1169 ( .B0(n963), .B1(n970), .A0N(n962), .A1N(n961), .Y(n966)
);
AOI211X1TS U1170 ( .A0(n968), .A1(n967), .B0(n966), .C0(n965), .Y(n969) );
OAI31X1TS U1171 ( .A0(n972), .A1(n971), .A2(n970), .B0(n969), .Y(n975) );
OA22X1TS U1172 ( .A0(n1498), .A1(intDX_EWSW[22]), .B0(n1539), .B1(
intDX_EWSW[23]), .Y(n987) );
AOI211XLTS U1173 ( .A0(intDY_EWSW[16]), .A1(n1519), .B0(n982), .C0(n1040),
.Y(n974) );
NAND3BXLTS U1174 ( .AN(n977), .B(n975), .C(n974), .Y(n993) );
OAI2BB2XLTS U1175 ( .B0(intDY_EWSW[20]), .B1(n976), .A0N(intDX_EWSW[21]),
.A1N(n1531), .Y(n986) );
AOI22X1TS U1176 ( .A0(intDX_EWSW[17]), .A1(n1547), .B0(intDX_EWSW[16]), .B1(
n978), .Y(n981) );
OAI32X1TS U1177 ( .A0(n1040), .A1(n982), .A2(n981), .B0(n980), .B1(n982),
.Y(n985) );
OAI2BB2XLTS U1178 ( .B0(intDY_EWSW[22]), .B1(n983), .A0N(intDX_EWSW[23]),
.A1N(n1539), .Y(n984) );
AOI211X1TS U1179 ( .A0(n987), .A1(n986), .B0(n985), .C0(n984), .Y(n992) );
NAND2BXLTS U1180 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n988) );
NAND4BBX1TS U1181 ( .AN(n1033), .BN(n990), .C(n989), .D(n988), .Y(n991) );
AOI32X1TS U1182 ( .A0(n994), .A1(n993), .A2(n992), .B0(n991), .B1(n994), .Y(
n995) );
INVX3TS U1183 ( .A(n1087), .Y(n1067) );
BUFX4TS U1184 ( .A(n997), .Y(n1090) );
AOI22X1TS U1185 ( .A0(intDX_EWSW[14]), .A1(n996), .B0(DmP_EXP_EWSW[14]),
.B1(n1090), .Y(n998) );
OAI21XLTS U1186 ( .A0(n1535), .A1(n1067), .B0(n998), .Y(n582) );
INVX4TS U1187 ( .A(n1087), .Y(n1324) );
BUFX4TS U1188 ( .A(n997), .Y(n1262) );
AOI22X1TS U1189 ( .A0(intDX_EWSW[19]), .A1(n996), .B0(DmP_EXP_EWSW[19]),
.B1(n1262), .Y(n999) );
OAI21XLTS U1190 ( .A0(n1499), .A1(n1324), .B0(n999), .Y(n572) );
AOI22X1TS U1191 ( .A0(n904), .A1(n996), .B0(DmP_EXP_EWSW[0]), .B1(n1090),
.Y(n1000) );
OAI21XLTS U1192 ( .A0(n1546), .A1(n1324), .B0(n1000), .Y(n610) );
AOI22X1TS U1193 ( .A0(intDX_EWSW[22]), .A1(n996), .B0(DmP_EXP_EWSW[22]),
.B1(n1262), .Y(n1001) );
OAI21XLTS U1194 ( .A0(n1498), .A1(n1324), .B0(n1001), .Y(n566) );
AOI22X1TS U1195 ( .A0(intDX_EWSW[16]), .A1(n996), .B0(DmP_EXP_EWSW[16]),
.B1(n1262), .Y(n1002) );
OAI21XLTS U1196 ( .A0(n1497), .A1(n1324), .B0(n1002), .Y(n578) );
AOI22X1TS U1197 ( .A0(intDX_EWSW[5]), .A1(n1012), .B0(DmP_EXP_EWSW[5]), .B1(
n1090), .Y(n1003) );
OAI21XLTS U1198 ( .A0(n1496), .A1(n1067), .B0(n1003), .Y(n600) );
AOI22X1TS U1199 ( .A0(intDX_EWSW[6]), .A1(n1012), .B0(DmP_EXP_EWSW[6]), .B1(
n1262), .Y(n1004) );
OAI21XLTS U1200 ( .A0(n1528), .A1(n1067), .B0(n1004), .Y(n598) );
AOI22X1TS U1201 ( .A0(intDX_EWSW[4]), .A1(n1012), .B0(DmP_EXP_EWSW[4]), .B1(
n997), .Y(n1005) );
OAI21XLTS U1202 ( .A0(n1533), .A1(n1067), .B0(n1005), .Y(n602) );
AOI22X1TS U1203 ( .A0(intDX_EWSW[17]), .A1(n996), .B0(DmP_EXP_EWSW[17]),
.B1(n1262), .Y(n1006) );
OAI21XLTS U1204 ( .A0(n1547), .A1(n1324), .B0(n1006), .Y(n576) );
AOI22X1TS U1205 ( .A0(n905), .A1(n1012), .B0(DmP_EXP_EWSW[10]), .B1(n1090),
.Y(n1007) );
OAI21XLTS U1206 ( .A0(n878), .A1(n1067), .B0(n1007), .Y(n590) );
AOI22X1TS U1207 ( .A0(intDX_EWSW[13]), .A1(n996), .B0(DmP_EXP_EWSW[13]),
.B1(n1262), .Y(n1008) );
OAI21XLTS U1208 ( .A0(n1530), .A1(n1067), .B0(n1008), .Y(n584) );
AOI22X1TS U1209 ( .A0(intDX_EWSW[20]), .A1(n1012), .B0(DmP_EXP_EWSW[20]),
.B1(n1262), .Y(n1009) );
OAI21XLTS U1210 ( .A0(n1536), .A1(n1324), .B0(n1009), .Y(n570) );
AOI22X1TS U1211 ( .A0(intDX_EWSW[9]), .A1(n1012), .B0(DmP_EXP_EWSW[9]), .B1(
n1090), .Y(n1010) );
OAI21XLTS U1212 ( .A0(n1529), .A1(n1067), .B0(n1010), .Y(n592) );
AOI22X1TS U1213 ( .A0(intDX_EWSW[21]), .A1(n1012), .B0(DmP_EXP_EWSW[21]),
.B1(n1262), .Y(n1011) );
OAI21XLTS U1214 ( .A0(n1531), .A1(n1324), .B0(n1011), .Y(n568) );
AOI22X1TS U1215 ( .A0(intDX_EWSW[7]), .A1(n1012), .B0(DmP_EXP_EWSW[7]), .B1(
n1090), .Y(n1013) );
OAI21XLTS U1216 ( .A0(n1537), .A1(n1067), .B0(n1013), .Y(n596) );
AOI22X1TS U1217 ( .A0(intDX_EWSW[18]), .A1(n1012), .B0(DmP_EXP_EWSW[18]),
.B1(n1262), .Y(n1014) );
OAI21XLTS U1218 ( .A0(n1552), .A1(n1324), .B0(n1014), .Y(n574) );
AOI22X1TS U1219 ( .A0(intDX_EWSW[1]), .A1(n1012), .B0(DmP_EXP_EWSW[1]), .B1(
n1262), .Y(n1015) );
OAI21XLTS U1220 ( .A0(n1548), .A1(n1324), .B0(n1015), .Y(n608) );
AOI22X1TS U1221 ( .A0(n906), .A1(n1012), .B0(DmP_EXP_EWSW[2]), .B1(n1262),
.Y(n1016) );
OAI21XLTS U1222 ( .A0(n1532), .A1(n1324), .B0(n1016), .Y(n606) );
AOI22X1TS U1223 ( .A0(intDX_EWSW[12]), .A1(n1012), .B0(DmP_EXP_EWSW[12]),
.B1(n997), .Y(n1017) );
OAI21XLTS U1224 ( .A0(n1534), .A1(n1067), .B0(n1017), .Y(n586) );
AOI22X1TS U1225 ( .A0(intDX_EWSW[8]), .A1(n1012), .B0(DmP_EXP_EWSW[8]), .B1(
n997), .Y(n1018) );
OAI21XLTS U1226 ( .A0(n1549), .A1(n1067), .B0(n1018), .Y(n594) );
AOI22X1TS U1227 ( .A0(intDX_EWSW[11]), .A1(n1012), .B0(DmP_EXP_EWSW[11]),
.B1(n1262), .Y(n1019) );
OAI21XLTS U1228 ( .A0(n1606), .A1(n1067), .B0(n1019), .Y(n588) );
AOI22X1TS U1229 ( .A0(intDX_EWSW[3]), .A1(n1012), .B0(DmP_EXP_EWSW[3]), .B1(
n1090), .Y(n1020) );
AOI22X1TS U1230 ( .A0(DmP_EXP_EWSW[27]), .A1(n1262), .B0(intDX_EWSW[27]),
.B1(n1012), .Y(n1021) );
AOI22X1TS U1231 ( .A0(intDX_EWSW[15]), .A1(n1012), .B0(DmP_EXP_EWSW[15]),
.B1(n1262), .Y(n1022) );
OAI21XLTS U1232 ( .A0(n1607), .A1(n1067), .B0(n1022), .Y(n580) );
INVX4TS U1233 ( .A(n996), .Y(n1326) );
AOI22X1TS U1234 ( .A0(intDX_EWSW[30]), .A1(n1087), .B0(DMP_EXP_EWSW[30]),
.B1(n1090), .Y(n1023) );
OAI21XLTS U1235 ( .A0(n1551), .A1(n1326), .B0(n1023), .Y(n723) );
AOI22X1TS U1236 ( .A0(intDX_EWSW[28]), .A1(n1087), .B0(DMP_EXP_EWSW[28]),
.B1(n1090), .Y(n1024) );
OAI21XLTS U1237 ( .A0(n1538), .A1(n1326), .B0(n1024), .Y(n725) );
AOI22X1TS U1238 ( .A0(n902), .A1(n1262), .B0(intDX_EWSW[27]), .B1(n1087),
.Y(n1025) );
OAI21XLTS U1239 ( .A0(n1540), .A1(n1326), .B0(n1025), .Y(n726) );
AOI22X1TS U1240 ( .A0(DMP_EXP_EWSW[23]), .A1(n1262), .B0(intDX_EWSW[23]),
.B1(n1093), .Y(n1026) );
OAI21XLTS U1241 ( .A0(n1539), .A1(n1326), .B0(n1026), .Y(n730) );
AOI22X1TS U1242 ( .A0(intDX_EWSW[29]), .A1(n1087), .B0(DMP_EXP_EWSW[29]),
.B1(n1090), .Y(n1027) );
OAI21XLTS U1243 ( .A0(n1500), .A1(n1326), .B0(n1027), .Y(n724) );
AOI22X1TS U1244 ( .A0(intDX_EWSW[1]), .A1(n1093), .B0(DMP_EXP_EWSW[1]), .B1(
n997), .Y(n1028) );
OAI21XLTS U1245 ( .A0(n1548), .A1(n1326), .B0(n1028), .Y(n752) );
AOI22X1TS U1246 ( .A0(intDX_EWSW[3]), .A1(n1093), .B0(DMP_EXP_EWSW[3]), .B1(
n997), .Y(n1029) );
AOI22X1TS U1247 ( .A0(intDX_EWSW[4]), .A1(n1093), .B0(DMP_EXP_EWSW[4]), .B1(
n997), .Y(n1030) );
OAI21XLTS U1248 ( .A0(n1533), .A1(n1326), .B0(n1030), .Y(n749) );
AOI22X1TS U1249 ( .A0(intDX_EWSW[9]), .A1(n1093), .B0(DMP_EXP_EWSW[9]), .B1(
n997), .Y(n1031) );
OAI21XLTS U1250 ( .A0(n1529), .A1(n1326), .B0(n1031), .Y(n744) );
OAI22X1TS U1251 ( .A0(n1548), .A1(intDX_EWSW[1]), .B0(n1545), .B1(
intDX_EWSW[25]), .Y(n1032) );
AOI221X1TS U1252 ( .A0(n1548), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1545), .C0(n1032), .Y(n1038) );
OAI22X1TS U1253 ( .A0(n1538), .A1(intDX_EWSW[28]), .B0(n1500), .B1(
intDX_EWSW[29]), .Y(n1034) );
AOI221X1TS U1254 ( .A0(n1538), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1500), .C0(n1034), .Y(n1036) );
AOI2BB2XLTS U1255 ( .B0(intDX_EWSW[7]), .B1(n1537), .A0N(n1537), .A1N(
intDX_EWSW[7]), .Y(n1035) );
NAND4XLTS U1256 ( .A(n1038), .B(n1037), .C(n1036), .D(n1035), .Y(n1066) );
OAI22X1TS U1257 ( .A0(n1551), .A1(intDX_EWSW[30]), .B0(n1547), .B1(
intDX_EWSW[17]), .Y(n1039) );
OAI22X1TS U1258 ( .A0(n1536), .A1(intDX_EWSW[20]), .B0(n1531), .B1(
intDX_EWSW[21]), .Y(n1041) );
OAI22X1TS U1259 ( .A0(n1498), .A1(intDX_EWSW[22]), .B0(n1539), .B1(
intDX_EWSW[23]), .Y(n1042) );
NAND4XLTS U1260 ( .A(n1046), .B(n1045), .C(n1044), .D(n1043), .Y(n1065) );
OAI22X1TS U1261 ( .A0(n1487), .A1(intDX_EWSW[24]), .B0(n1529), .B1(
intDX_EWSW[9]), .Y(n1047) );
AOI221X1TS U1262 ( .A0(n1487), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1529), .C0(n1047), .Y(n1054) );
OAI22X1TS U1263 ( .A0(n1534), .A1(intDX_EWSW[12]), .B0(n1530), .B1(
intDX_EWSW[13]), .Y(n1049) );
OAI22X1TS U1264 ( .A0(n1535), .A1(intDX_EWSW[14]), .B0(n1607), .B1(
intDX_EWSW[15]), .Y(n1050) );
NAND4XLTS U1265 ( .A(n1054), .B(n1053), .C(n1052), .D(n1051), .Y(n1064) );
OAI22X1TS U1266 ( .A0(n1497), .A1(intDX_EWSW[16]), .B0(n1546), .B1(n904),
.Y(n1055) );
AOI221X1TS U1267 ( .A0(n1497), .A1(intDX_EWSW[16]), .B0(n904), .B1(n1546),
.C0(n1055), .Y(n1062) );
OAI22X1TS U1268 ( .A0(n1532), .A1(n906), .B0(n1605), .B1(intDX_EWSW[3]), .Y(
n1056) );
OAI22X1TS U1269 ( .A0(n1533), .A1(intDX_EWSW[4]), .B0(n1496), .B1(
intDX_EWSW[5]), .Y(n1057) );
AOI221X1TS U1270 ( .A0(n1533), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1496), .C0(n1057), .Y(n1060) );
OAI22X1TS U1271 ( .A0(n1549), .A1(intDX_EWSW[8]), .B0(n1528), .B1(
intDX_EWSW[6]), .Y(n1058) );
AOI221X1TS U1272 ( .A0(n1549), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1528), .C0(n1058), .Y(n1059) );
NAND4XLTS U1273 ( .A(n1062), .B(n1061), .C(n1060), .D(n1059), .Y(n1063) );
NOR4X1TS U1274 ( .A(n1066), .B(n1065), .C(n1064), .D(n1063), .Y(n1320) );
CLKXOR2X2TS U1275 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1318) );
INVX2TS U1276 ( .A(n1318), .Y(n1070) );
OAI21XLTS U1277 ( .A0(n1070), .A1(n997), .B0(n1067), .Y(n1068) );
AOI22X1TS U1278 ( .A0(intDX_EWSW[31]), .A1(n1068), .B0(SIGN_FLAG_EXP), .B1(
n1262), .Y(n1069) );
AOI22X1TS U1279 ( .A0(intDX_EWSW[15]), .A1(n1093), .B0(DMP_EXP_EWSW[15]),
.B1(n997), .Y(n1071) );
OAI21XLTS U1280 ( .A0(n1607), .A1(n1092), .B0(n1071), .Y(n738) );
AOI22X1TS U1281 ( .A0(intDX_EWSW[17]), .A1(n1087), .B0(DMP_EXP_EWSW[17]),
.B1(n1090), .Y(n1072) );
AOI22X1TS U1282 ( .A0(intDX_EWSW[14]), .A1(n1093), .B0(DMP_EXP_EWSW[14]),
.B1(n997), .Y(n1073) );
OAI21XLTS U1283 ( .A0(n1535), .A1(n1092), .B0(n1073), .Y(n739) );
AOI22X1TS U1284 ( .A0(intDX_EWSW[8]), .A1(n1087), .B0(DMP_EXP_EWSW[8]), .B1(
n997), .Y(n1074) );
OAI21XLTS U1285 ( .A0(n1549), .A1(n1092), .B0(n1074), .Y(n745) );
AOI22X1TS U1286 ( .A0(intDX_EWSW[12]), .A1(n1087), .B0(DMP_EXP_EWSW[12]),
.B1(n997), .Y(n1075) );
OAI21XLTS U1287 ( .A0(n1534), .A1(n1092), .B0(n1075), .Y(n741) );
AOI22X1TS U1288 ( .A0(intDX_EWSW[22]), .A1(n1087), .B0(DMP_EXP_EWSW[22]),
.B1(n1090), .Y(n1076) );
OAI21XLTS U1289 ( .A0(n1498), .A1(n1092), .B0(n1076), .Y(n731) );
AOI22X1TS U1290 ( .A0(intDX_EWSW[13]), .A1(n1087), .B0(DMP_EXP_EWSW[13]),
.B1(n997), .Y(n1077) );
OAI21XLTS U1291 ( .A0(n1530), .A1(n1092), .B0(n1077), .Y(n740) );
AOI22X1TS U1292 ( .A0(intDX_EWSW[18]), .A1(n1093), .B0(DMP_EXP_EWSW[18]),
.B1(n1090), .Y(n1078) );
OAI21XLTS U1293 ( .A0(n1552), .A1(n1092), .B0(n1078), .Y(n735) );
AOI22X1TS U1294 ( .A0(intDX_EWSW[7]), .A1(n1093), .B0(DMP_EXP_EWSW[7]), .B1(
n997), .Y(n1079) );
OAI21XLTS U1295 ( .A0(n1537), .A1(n1092), .B0(n1079), .Y(n746) );
AOI22X1TS U1296 ( .A0(intDX_EWSW[19]), .A1(n1087), .B0(DMP_EXP_EWSW[19]),
.B1(n1090), .Y(n1080) );
OAI21XLTS U1297 ( .A0(n1499), .A1(n1092), .B0(n1080), .Y(n734) );
AOI22X1TS U1298 ( .A0(intDX_EWSW[6]), .A1(n1093), .B0(DMP_EXP_EWSW[6]), .B1(
n997), .Y(n1081) );
OAI21XLTS U1299 ( .A0(n1528), .A1(n1092), .B0(n1081), .Y(n747) );
AOI22X1TS U1300 ( .A0(intDX_EWSW[5]), .A1(n1087), .B0(DMP_EXP_EWSW[5]), .B1(
n997), .Y(n1082) );
OAI21XLTS U1301 ( .A0(n1496), .A1(n1092), .B0(n1082), .Y(n748) );
AOI22X1TS U1302 ( .A0(intDX_EWSW[16]), .A1(n1087), .B0(DMP_EXP_EWSW[16]),
.B1(n1090), .Y(n1083) );
OAI21XLTS U1303 ( .A0(n1497), .A1(n1092), .B0(n1083), .Y(n737) );
AOI22X1TS U1304 ( .A0(n906), .A1(n1093), .B0(DMP_EXP_EWSW[2]), .B1(n997),
.Y(n1084) );
OAI21XLTS U1305 ( .A0(n1532), .A1(n1092), .B0(n1084), .Y(n751) );
AOI22X1TS U1306 ( .A0(n904), .A1(n1087), .B0(DMP_EXP_EWSW[0]), .B1(n997),
.Y(n1085) );
OAI21XLTS U1307 ( .A0(n1546), .A1(n1092), .B0(n1085), .Y(n753) );
AOI22X1TS U1308 ( .A0(intDX_EWSW[11]), .A1(n1087), .B0(DMP_EXP_EWSW[11]),
.B1(n1090), .Y(n1086) );
OAI21XLTS U1309 ( .A0(n1606), .A1(n1092), .B0(n1086), .Y(n742) );
AOI22X1TS U1310 ( .A0(n905), .A1(n1087), .B0(DMP_EXP_EWSW[10]), .B1(n997),
.Y(n1088) );
OAI21XLTS U1311 ( .A0(n878), .A1(n1092), .B0(n1088), .Y(n743) );
AOI22X1TS U1312 ( .A0(intDX_EWSW[20]), .A1(n1093), .B0(DMP_EXP_EWSW[20]),
.B1(n1090), .Y(n1089) );
OAI21XLTS U1313 ( .A0(n1536), .A1(n1092), .B0(n1089), .Y(n733) );
AOI22X1TS U1314 ( .A0(intDX_EWSW[21]), .A1(n1093), .B0(DMP_EXP_EWSW[21]),
.B1(n1090), .Y(n1091) );
OAI21XLTS U1315 ( .A0(n1531), .A1(n1092), .B0(n1091), .Y(n732) );
AOI222X1TS U1316 ( .A0(n1012), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n997), .C0(intDY_EWSW[23]), .C1(n1093), .Y(n1094) );
INVX2TS U1317 ( .A(n1094), .Y(n564) );
AOI2BB2XLTS U1318 ( .B0(beg_OP), .B1(n1495), .A0N(n1495), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1095) );
NAND3XLTS U1319 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1495), .C(
n1524), .Y(n1258) );
OAI21XLTS U1320 ( .A0(n1261), .A1(n1095), .B0(n1258), .Y(n870) );
NAND2X2TS U1321 ( .A(n1336), .B(n1574), .Y(n1297) );
NOR2XLTS U1322 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1097)
);
NOR2BX1TS U1323 ( .AN(n1112), .B(Raw_mant_NRM_SWR[18]), .Y(n1239) );
NOR2BX1TS U1324 ( .AN(n1239), .B(n1240), .Y(n1109) );
NAND2X1TS U1325 ( .A(n1109), .B(n1491), .Y(n1241) );
NAND2X1TS U1326 ( .A(n1122), .B(n1483), .Y(n1114) );
NAND2X1TS U1327 ( .A(n1246), .B(n1484), .Y(n1096) );
NOR2X1TS U1328 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1098)
);
NOR3X1TS U1329 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1096),
.Y(n1099) );
NAND2X1TS U1330 ( .A(n1099), .B(n1485), .Y(n1106) );
OAI22X1TS U1331 ( .A0(n1097), .A1(n1096), .B0(n1098), .B1(n1106), .Y(n1104)
);
NOR2X1TS U1332 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1101)
);
NAND2X1TS U1333 ( .A(n1247), .B(n1098), .Y(n1102) );
OAI21XLTS U1334 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1099), .Y(n1100) );
OAI21X1TS U1335 ( .A0(n1101), .A1(n1102), .B0(n1100), .Y(n1126) );
INVX2TS U1336 ( .A(n1102), .Y(n1248) );
NAND3XLTS U1337 ( .A(n1101), .B(n1248), .C(Raw_mant_NRM_SWR[1]), .Y(n1242)
);
OAI21XLTS U1338 ( .A0(n1486), .A1(n1102), .B0(n1242), .Y(n1103) );
OAI31X1TS U1339 ( .A0(n1104), .A1(n1126), .A2(n1103), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1238) );
NAND3XLTS U1340 ( .A(n1335), .B(Shift_amount_SHT1_EWR[4]), .C(n1336), .Y(
n1105) );
OAI211XLTS U1341 ( .A0(n1297), .A1(n1510), .B0(n1238), .C0(n1105), .Y(n767)
);
INVX2TS U1342 ( .A(n1106), .Y(n1116) );
AOI22X1TS U1343 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1112), .B0(n1246), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1123) );
OAI32X1TS U1344 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1486), .B0(n1511), .B1(Raw_mant_NRM_SWR[3]), .Y(n1107) );
NAND2X1TS U1345 ( .A(Raw_mant_NRM_SWR[12]), .B(n1122), .Y(n1243) );
NAND2X1TS U1346 ( .A(Raw_mant_NRM_SWR[14]), .B(n1109), .Y(n1128) );
AOI32X1TS U1347 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1477), .A2(n1508), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1477), .Y(n1110) );
AOI32X1TS U1348 ( .A0(n1481), .A1(n1128), .A2(n1110), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1128), .Y(n1111) );
AOI31XLTS U1349 ( .A0(n1112), .A1(Raw_mant_NRM_SWR[16]), .A2(n1507), .B0(
n1111), .Y(n1113) );
OAI31X1TS U1350 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1114), .A2(n1478), .B0(
n1113), .Y(n1115) );
NAND2X2TS U1351 ( .A(Shift_reg_FLAGS_7[1]), .B(n1131), .Y(n1282) );
NOR2BX1TS U1352 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1187) );
AOI22X1TS U1353 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1117), .B0(n1279), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1138) );
NOR2XLTS U1354 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1121) );
NOR2X1TS U1355 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1119) );
AOI32X1TS U1356 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1119), .A2(n1118), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1119), .Y(n1120) );
AOI211X1TS U1357 ( .A0(n1121), .A1(n1120), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1127) );
INVX2TS U1358 ( .A(n1122), .Y(n1124) );
OAI31X1TS U1359 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1483), .A2(n1124), .B0(
n1123), .Y(n1125) );
NOR2X1TS U1360 ( .A(n1150), .B(n1336), .Y(n1255) );
AOI21X1TS U1361 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n1336), .B0(n1255), .Y(
n1130) );
NAND2X1TS U1362 ( .A(n1130), .B(n1297), .Y(n1129) );
INVX2TS U1363 ( .A(n1297), .Y(n1201) );
BUFX4TS U1364 ( .A(n1201), .Y(n1294) );
NOR2X2TS U1365 ( .A(n1294), .B(n1130), .Y(n1291) );
NOR2X4TS U1366 ( .A(n1131), .B(n1336), .Y(n1280) );
AOI22X1TS U1367 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1280), .B0(n1279), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1134) );
NOR2XLTS U1368 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n1132) );
AOI22X1TS U1369 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1133) );
NAND2X1TS U1370 ( .A(n1134), .B(n1133), .Y(n1158) );
AOI22X1TS U1371 ( .A0(n1201), .A1(Data_array_SWR[1]), .B0(n1291), .B1(n1158),
.Y(n1137) );
INVX2TS U1372 ( .A(n1135), .Y(n1289) );
NAND2X1TS U1373 ( .A(Raw_mant_NRM_SWR[23]), .B(n1289), .Y(n1136) );
OAI211XLTS U1374 ( .A0(n1138), .A1(n1288), .B0(n1137), .C0(n1136), .Y(n772)
);
AOI22X1TS U1375 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1280), .B0(n1279), .B1(
n901), .Y(n1140) );
AOI22X1TS U1376 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1117), .B0(n1284), .B1(
n897), .Y(n1139) );
NAND2X1TS U1377 ( .A(n1140), .B(n1139), .Y(n1155) );
AOI22X1TS U1378 ( .A0(n1201), .A1(Data_array_SWR[4]), .B0(n1291), .B1(n1155),
.Y(n1142) );
NAND2X1TS U1379 ( .A(Raw_mant_NRM_SWR[20]), .B(n1289), .Y(n1141) );
OAI211XLTS U1380 ( .A0(n1154), .A1(n1288), .B0(n1142), .C0(n1141), .Y(n775)
);
AOI22X1TS U1381 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1280), .B0(n1279), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1144) );
AOI22X1TS U1382 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1117), .B0(n1284), .B1(
n901), .Y(n1143) );
NAND2X1TS U1383 ( .A(n1144), .B(n1143), .Y(n1162) );
AOI22X1TS U1384 ( .A0(n1294), .A1(Data_array_SWR[5]), .B0(n1291), .B1(n1162),
.Y(n1146) );
NAND2X1TS U1385 ( .A(Raw_mant_NRM_SWR[19]), .B(n1289), .Y(n1145) );
OAI211XLTS U1386 ( .A0(n1161), .A1(n1288), .B0(n1146), .C0(n1145), .Y(n776)
);
INVX2TS U1387 ( .A(n1288), .Y(n1163) );
AOI22X1TS U1388 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1280), .B0(n1279), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1149) );
AOI22X1TS U1389 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1148) );
NAND2X1TS U1390 ( .A(n1149), .B(n1148), .Y(n1290) );
AOI22X1TS U1391 ( .A0(n1294), .A1(Data_array_SWR[2]), .B0(n1163), .B1(n1290),
.Y(n1153) );
INVX2TS U1392 ( .A(n1280), .Y(n1192) );
BUFX3TS U1393 ( .A(n1151), .Y(n1210) );
NAND2X1TS U1394 ( .A(Raw_mant_NRM_SWR[20]), .B(n1210), .Y(n1152) );
OAI211XLTS U1395 ( .A0(n1154), .A1(n1147), .B0(n1153), .C0(n1152), .Y(n773)
);
AOI22X1TS U1396 ( .A0(n1201), .A1(Data_array_SWR[6]), .B0(n1163), .B1(n1155),
.Y(n1157) );
NAND2X1TS U1397 ( .A(Raw_mant_NRM_SWR[16]), .B(n1210), .Y(n1156) );
OAI211XLTS U1398 ( .A0(n1179), .A1(n1147), .B0(n1157), .C0(n1156), .Y(n777)
);
AOI22X1TS U1399 ( .A0(n1201), .A1(Data_array_SWR[3]), .B0(n1163), .B1(n1158),
.Y(n1160) );
NAND2X1TS U1400 ( .A(Raw_mant_NRM_SWR[19]), .B(n1210), .Y(n1159) );
OAI211XLTS U1401 ( .A0(n1161), .A1(n1147), .B0(n1160), .C0(n1159), .Y(n774)
);
AOI22X1TS U1402 ( .A0(n1201), .A1(Data_array_SWR[7]), .B0(n1163), .B1(n1162),
.Y(n1165) );
NAND2X1TS U1403 ( .A(Raw_mant_NRM_SWR[15]), .B(n1210), .Y(n1164) );
OAI211XLTS U1404 ( .A0(n1168), .A1(n1147), .B0(n1165), .C0(n1164), .Y(n778)
);
AOI22X1TS U1405 ( .A0(n1201), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1210), .Y(n1167) );
AOI2BB2XLTS U1406 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1289), .A0N(n1205),
.A1N(n1147), .Y(n1166) );
AOI22X1TS U1407 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[21]), .B0(n1279), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1169) );
AOI21X1TS U1408 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1117), .B0(n1170), .Y(n1275) );
OAI22X1TS U1409 ( .A0(n1211), .A1(n1288), .B0(n1553), .B1(n1135), .Y(n1171)
);
AOI21X1TS U1410 ( .A0(n1294), .A1(Data_array_SWR[20]), .B0(n1171), .Y(n1172)
);
OAI21XLTS U1411 ( .A0(n1275), .A1(n1147), .B0(n1172), .Y(n792) );
AOI22X1TS U1412 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1280), .B0(n1279), .B1(n900), .Y(n1173) );
OAI21XLTS U1413 ( .A0(n1513), .A1(n1282), .B0(n1173), .Y(n1174) );
AOI21X1TS U1414 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[18]), .B0(n1174), .Y(
n1191) );
OAI22X1TS U1415 ( .A0(n1184), .A1(n1288), .B0(n1479), .B1(n1135), .Y(n1175)
);
AOI21X1TS U1416 ( .A0(n1294), .A1(Data_array_SWR[17]), .B0(n1175), .Y(n1176)
);
OAI21XLTS U1417 ( .A0(n1191), .A1(n1147), .B0(n1176), .Y(n789) );
AOI22X1TS U1418 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[8]), .B0(n1279), .B1(n899), .Y(n1177) );
OAI21XLTS U1419 ( .A0(n1491), .A1(n1192), .B0(n1177), .Y(n1178) );
AOI21X1TS U1420 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1117), .B0(n1178), .Y(
n1287) );
OAI22X1TS U1421 ( .A0(n1179), .A1(n1288), .B0(n1482), .B1(n1135), .Y(n1180)
);
AOI21X1TS U1422 ( .A0(n1294), .A1(Data_array_SWR[8]), .B0(n1180), .Y(n1181)
);
OAI21XLTS U1423 ( .A0(n1287), .A1(n1147), .B0(n1181), .Y(n779) );
AOI22X1TS U1424 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1280), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1279), .Y(n1182) );
OAI21XLTS U1425 ( .A0(n1480), .A1(n1282), .B0(n1182), .Y(n1183) );
AOI21X1TS U1426 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n1284), .B0(n1183), .Y(
n1278) );
INVX2TS U1427 ( .A(n1210), .Y(n1188) );
OAI22X1TS U1428 ( .A0(n1184), .A1(n1147), .B0(n1479), .B1(n1188), .Y(n1185)
);
AOI21X1TS U1429 ( .A0(n1294), .A1(Data_array_SWR[15]), .B0(n1185), .Y(n1186)
);
OAI21XLTS U1430 ( .A0(n1278), .A1(n1288), .B0(n1186), .Y(n787) );
OAI22X1TS U1431 ( .A0(n1194), .A1(n1147), .B0(n1511), .B1(n1188), .Y(n1189)
);
AOI21X1TS U1432 ( .A0(n1294), .A1(Data_array_SWR[19]), .B0(n1189), .Y(n1190)
);
OAI21XLTS U1433 ( .A0(n1191), .A1(n1288), .B0(n1190), .Y(n791) );
OAI22X1TS U1434 ( .A0(n1556), .A1(n1282), .B0(n1486), .B1(n1192), .Y(n1193)
);
OAI22X1TS U1435 ( .A0(n1273), .A1(n1147), .B0(n1194), .B1(n1288), .Y(n1195)
);
AOI21X1TS U1436 ( .A0(n1294), .A1(Data_array_SWR[21]), .B0(n1195), .Y(n1196)
);
OAI21XLTS U1437 ( .A0(n1511), .A1(n1135), .B0(n1196), .Y(n793) );
AOI22X1TS U1438 ( .A0(n1294), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1210), .Y(n1198) );
OA22X1TS U1439 ( .A0(n1485), .A1(n1135), .B0(n1215), .B1(n1147), .Y(n1197)
);
OAI211XLTS U1440 ( .A0(n1206), .A1(n1288), .B0(n1198), .C0(n1197), .Y(n788)
);
AOI22X1TS U1441 ( .A0(n1294), .A1(Data_array_SWR[12]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1210), .Y(n1200) );
OA22X1TS U1442 ( .A0(n1483), .A1(n1135), .B0(n1209), .B1(n1147), .Y(n1199)
);
OAI211XLTS U1443 ( .A0(n1202), .A1(n1288), .B0(n1200), .C0(n1199), .Y(n784)
);
AOI22X1TS U1444 ( .A0(n1201), .A1(n903), .B0(Raw_mant_NRM_SWR[11]), .B1(
n1210), .Y(n1204) );
OA22X1TS U1445 ( .A0(n1503), .A1(n1135), .B0(n1202), .B1(n1147), .Y(n1203)
);
OAI211XLTS U1446 ( .A0(n1205), .A1(n1288), .B0(n1204), .C0(n1203), .Y(n782)
);
AOI22X1TS U1447 ( .A0(n1294), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1210), .Y(n1208) );
OA22X1TS U1448 ( .A0(n1480), .A1(n1135), .B0(n1206), .B1(n1147), .Y(n1207)
);
OAI211XLTS U1449 ( .A0(n1209), .A1(n1288), .B0(n1208), .C0(n1207), .Y(n786)
);
AOI22X1TS U1450 ( .A0(n1294), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1210), .Y(n1214) );
OA22X1TS U1451 ( .A0(n1513), .A1(n1135), .B0(n1211), .B1(n1147), .Y(n1213)
);
OAI211XLTS U1452 ( .A0(n1215), .A1(n1288), .B0(n1214), .C0(n1213), .Y(n790)
);
BUFX4TS U1453 ( .A(OP_FLAG_SFG), .Y(n1351) );
CLKBUFX2TS U1454 ( .A(OP_FLAG_SFG), .Y(n1355) );
AOI22X1TS U1455 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n1351), .B0(n1354), .B1(n913), .Y(n1340) );
NAND2X1TS U1456 ( .A(n1340), .B(DMP_SFG[0]), .Y(n1342) );
INVX2TS U1457 ( .A(n1342), .Y(n1216) );
INVX2TS U1458 ( .A(n1217), .Y(n1227) );
AND4X1TS U1459 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1218), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1219) );
NAND3XLTS U1460 ( .A(n1220), .B(exp_rslt_NRM2_EW1[4]), .C(n1219), .Y(n1221)
);
NAND2BXLTS U1461 ( .AN(n1221), .B(n1256), .Y(n1222) );
NOR2XLTS U1462 ( .A(n1227), .B(n1222), .Y(n1226) );
INVX2TS U1463 ( .A(n1223), .Y(n1224) );
CLKAND2X2TS U1464 ( .A(n1561), .B(n1224), .Y(n1225) );
OAI2BB2XLTS U1465 ( .B0(n1360), .B1(n1227), .A0N(final_result_ieee[30]),
.A1N(n1420), .Y(n754) );
INVX2TS U1466 ( .A(n1228), .Y(n1361) );
NOR2XLTS U1467 ( .A(n1361), .B(SIGN_FLAG_SHT1SHT2), .Y(n1229) );
OAI2BB2XLTS U1468 ( .B0(n1229), .B1(n1360), .A0N(n1420), .A1N(
final_result_ieee[31]), .Y(n543) );
AOI22X1TS U1469 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1354), .B0(n1351), .B1(n918), .Y(intadd_59_B_0_) );
AOI21X1TS U1470 ( .A0(intadd_59_A_1_), .A1(intadd_59_B_1_), .B0(
intadd_59_B_0_), .Y(n1230) );
AOI2BB2X1TS U1471 ( .B0(DMP_SFG[2]), .B1(n1230), .A0N(intadd_59_A_1_), .A1N(
intadd_59_B_1_), .Y(n1231) );
AOI222X1TS U1472 ( .A0(n1231), .A1(intadd_59_A_2_), .B0(n1231), .B1(n895),
.C0(intadd_59_A_2_), .C1(n895), .Y(n1232) );
AOI22X1TS U1473 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1352), .B0(n1351), .B1(n907), .Y(intadd_58_B_0_) );
AOI21X1TS U1474 ( .A0(intadd_58_A_1_), .A1(intadd_58_B_1_), .B0(
intadd_58_B_0_), .Y(n1233) );
AOI2BB2X1TS U1475 ( .B0(DMP_SFG[6]), .B1(n1233), .A0N(intadd_58_A_1_), .A1N(
intadd_58_B_1_), .Y(n1234) );
AOI222X1TS U1476 ( .A0(n1234), .A1(intadd_58_A_2_), .B0(n1234), .B1(
intadd_58_B_2_), .C0(intadd_58_A_2_), .C1(intadd_58_B_2_), .Y(n1235)
);
INVX2TS U1477 ( .A(n1236), .Y(n1237) );
NAND2X1TS U1478 ( .A(n1515), .B(n1237), .Y(DP_OP_15J51_123_3372_n8) );
MX2X1TS U1479 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
MX2X1TS U1480 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n616) );
MX2X1TS U1481 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1482 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
MX2X1TS U1483 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1484 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1485 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1486 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n646) );
OAI2BB1X1TS U1487 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1336), .B0(n1238),
.Y(n512) );
OAI32X1TS U1488 ( .A0(n1336), .A1(Raw_mant_NRM_SWR[14]), .A2(n1240), .B0(
n1239), .B1(n1336), .Y(n1244) );
AO21XLTS U1489 ( .A0(n1483), .A1(n1503), .B0(n1241), .Y(n1249) );
NAND4XLTS U1490 ( .A(n1244), .B(n1243), .C(n1242), .D(n1249), .Y(n1245) );
AOI21X1TS U1491 ( .A0(n1246), .A1(Raw_mant_NRM_SWR[10]), .B0(n1245), .Y(
n1299) );
AOI2BB1XLTS U1492 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1299), .Y(n516) );
AOI22X1TS U1493 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1248), .B0(n1247), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1250) );
OAI211XLTS U1494 ( .A0(n1252), .A1(n1251), .B0(n1250), .C0(n1249), .Y(n1253)
);
OAI21X1TS U1495 ( .A0(n1254), .A1(n1253), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1295) );
OAI2BB1X1TS U1496 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1336), .B0(n1295),
.Y(n514) );
AO21XLTS U1497 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1336), .B0(n1255), .Y(n513) );
AO21XLTS U1498 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1336), .B0(n1280), .Y(n515) );
OA22X1TS U1499 ( .A0(n1257), .A1(n1256), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n755) );
OA21XLTS U1500 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1360),
.Y(n558) );
INVX2TS U1501 ( .A(n1261), .Y(n1259) );
AOI22X1TS U1502 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1259), .B1(n1495), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1503 ( .A(n1259), .B(n1258), .Y(n871) );
NOR2XLTS U1504 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1260) );
AOI32X4TS U1505 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1260), .B1(n1524), .Y(n1264)
);
INVX2TS U1506 ( .A(n1264), .Y(n1263) );
AOI22X1TS U1507 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1261), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1495), .Y(n1265) );
AO22XLTS U1508 ( .A0(n1263), .A1(Shift_reg_FLAGS_7_6), .B0(n1264), .B1(n1265), .Y(n869) );
AOI22X1TS U1509 ( .A0(n1264), .A1(n1262), .B0(n1333), .B1(n1263), .Y(n868)
);
AOI22X1TS U1510 ( .A0(n1264), .A1(n1331), .B0(n1574), .B1(n1263), .Y(n867)
);
AOI22X1TS U1511 ( .A0(n1264), .A1(n1603), .B0(n1336), .B1(n1263), .Y(n864)
);
AOI22X1TS U1512 ( .A0(n1264), .A1(n1336), .B0(n1420), .B1(n1263), .Y(n863)
);
AO22XLTS U1513 ( .A0(n1267), .A1(Data_X[0]), .B0(n1266), .B1(n904), .Y(n862)
);
AO22XLTS U1514 ( .A0(n1270), .A1(Data_X[1]), .B0(n1272), .B1(intDX_EWSW[1]),
.Y(n861) );
AO22XLTS U1515 ( .A0(n1270), .A1(Data_X[2]), .B0(n1268), .B1(n906), .Y(n860)
);
AO22XLTS U1516 ( .A0(n1267), .A1(Data_X[3]), .B0(n1272), .B1(intDX_EWSW[3]),
.Y(n859) );
AO22XLTS U1517 ( .A0(n1267), .A1(Data_X[4]), .B0(n1266), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1518 ( .A0(n1267), .A1(Data_X[5]), .B0(n1268), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1519 ( .A0(n1269), .A1(Data_X[6]), .B0(n1268), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1520 ( .A0(n1269), .A1(Data_X[7]), .B0(n1266), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1521 ( .A0(n1270), .A1(Data_X[8]), .B0(n1268), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1522 ( .A0(n1267), .A1(Data_X[9]), .B0(n1268), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1523 ( .A0(n1269), .A1(Data_X[10]), .B0(n1268), .B1(n905), .Y(n852) );
AO22XLTS U1524 ( .A0(n1267), .A1(Data_X[11]), .B0(n1268), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1525 ( .A0(n1269), .A1(Data_X[12]), .B0(n1266), .B1(intDX_EWSW[12]), .Y(n850) );
AO22XLTS U1526 ( .A0(n1270), .A1(Data_X[13]), .B0(n1268), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1527 ( .A0(n1270), .A1(Data_X[14]), .B0(n1266), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1528 ( .A0(n1267), .A1(Data_X[15]), .B0(n1272), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1529 ( .A0(n1270), .A1(Data_X[16]), .B0(n1272), .B1(intDX_EWSW[16]), .Y(n846) );
AO22XLTS U1530 ( .A0(n1269), .A1(Data_X[17]), .B0(n1272), .B1(intDX_EWSW[17]), .Y(n845) );
AO22XLTS U1531 ( .A0(n1269), .A1(Data_X[18]), .B0(n1272), .B1(intDX_EWSW[18]), .Y(n844) );
AO22XLTS U1532 ( .A0(n1269), .A1(Data_X[20]), .B0(n1272), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1533 ( .A0(n1270), .A1(Data_X[21]), .B0(n1272), .B1(intDX_EWSW[21]), .Y(n841) );
AO22XLTS U1534 ( .A0(n1267), .A1(Data_X[22]), .B0(n1272), .B1(intDX_EWSW[22]), .Y(n840) );
AO22XLTS U1535 ( .A0(n1269), .A1(Data_X[23]), .B0(n1272), .B1(intDX_EWSW[23]), .Y(n839) );
AO22XLTS U1536 ( .A0(n1268), .A1(intDX_EWSW[24]), .B0(n1269), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1537 ( .A0(n1268), .A1(intDX_EWSW[25]), .B0(n920), .B1(Data_X[25]),
.Y(n837) );
AO22XLTS U1538 ( .A0(n1266), .A1(intDX_EWSW[26]), .B0(n1269), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1539 ( .A0(n1270), .A1(Data_X[27]), .B0(n1272), .B1(intDX_EWSW[27]), .Y(n835) );
AO22XLTS U1540 ( .A0(n1270), .A1(Data_X[28]), .B0(n1268), .B1(intDX_EWSW[28]), .Y(n834) );
AO22XLTS U1541 ( .A0(n1270), .A1(Data_X[29]), .B0(n1272), .B1(intDX_EWSW[29]), .Y(n833) );
AO22XLTS U1542 ( .A0(n1270), .A1(Data_X[30]), .B0(n1268), .B1(intDX_EWSW[30]), .Y(n832) );
AO22XLTS U1543 ( .A0(n1269), .A1(add_subt), .B0(n1266), .B1(intAS), .Y(n830)
);
AO22XLTS U1544 ( .A0(n1268), .A1(intDY_EWSW[0]), .B0(n1269), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1545 ( .A0(n1266), .A1(intDY_EWSW[1]), .B0(n1269), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1546 ( .A0(n1268), .A1(intDY_EWSW[2]), .B0(n1267), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1547 ( .A0(n1268), .A1(intDY_EWSW[3]), .B0(n1267), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1548 ( .A0(n1266), .A1(intDY_EWSW[4]), .B0(n1269), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1549 ( .A0(n1268), .A1(intDY_EWSW[5]), .B0(n1270), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1550 ( .A0(n1268), .A1(intDY_EWSW[6]), .B0(n1270), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1551 ( .A0(n1266), .A1(intDY_EWSW[7]), .B0(n1267), .B1(Data_Y[7]),
.Y(n821) );
INVX4TS U1552 ( .A(n920), .Y(n1271) );
AO22XLTS U1553 ( .A0(n1271), .A1(intDY_EWSW[8]), .B0(n1267), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1554 ( .A0(n1268), .A1(intDY_EWSW[9]), .B0(n1270), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1555 ( .A0(n1268), .A1(intDY_EWSW[10]), .B0(n1270), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1556 ( .A0(n1268), .A1(intDY_EWSW[11]), .B0(n1270), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1557 ( .A0(n1271), .A1(intDY_EWSW[12]), .B0(n1270), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1558 ( .A0(n1271), .A1(intDY_EWSW[13]), .B0(n1270), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1559 ( .A0(n1271), .A1(intDY_EWSW[14]), .B0(n1270), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1560 ( .A0(n1268), .A1(intDY_EWSW[15]), .B0(n1270), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1561 ( .A0(n1266), .A1(intDY_EWSW[16]), .B0(n920), .B1(Data_Y[16]),
.Y(n812) );
AO22XLTS U1562 ( .A0(n1271), .A1(intDY_EWSW[17]), .B0(n1267), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1563 ( .A0(n1271), .A1(intDY_EWSW[18]), .B0(n1269), .B1(Data_Y[18]), .Y(n810) );
AO22XLTS U1564 ( .A0(n1271), .A1(intDY_EWSW[19]), .B0(n920), .B1(Data_Y[19]),
.Y(n809) );
AO22XLTS U1565 ( .A0(n1271), .A1(intDY_EWSW[20]), .B0(n920), .B1(Data_Y[20]),
.Y(n808) );
AO22XLTS U1566 ( .A0(n1271), .A1(intDY_EWSW[21]), .B0(n920), .B1(Data_Y[21]),
.Y(n807) );
AO22XLTS U1567 ( .A0(n1271), .A1(intDY_EWSW[22]), .B0(n1267), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1568 ( .A0(n1271), .A1(intDY_EWSW[23]), .B0(n1269), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1569 ( .A0(n1271), .A1(intDY_EWSW[24]), .B0(n1270), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1570 ( .A0(n1271), .A1(intDY_EWSW[25]), .B0(n1267), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1571 ( .A0(n1271), .A1(intDY_EWSW[26]), .B0(n1269), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1572 ( .A0(n1271), .A1(intDY_EWSW[27]), .B0(n1267), .B1(Data_Y[27]), .Y(n801) );
AO22XLTS U1573 ( .A0(n1271), .A1(intDY_EWSW[28]), .B0(n1269), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1574 ( .A0(n1271), .A1(intDY_EWSW[29]), .B0(n1270), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1575 ( .A0(n1271), .A1(intDY_EWSW[30]), .B0(n1267), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1576 ( .A0(n1270), .A1(Data_Y[31]), .B0(n1268), .B1(intDY_EWSW[31]), .Y(n797) );
AOI21X1TS U1577 ( .A0(n1117), .A1(Raw_mant_NRM_SWR[0]), .B0(n1284), .Y(n1274) );
OAI2BB2XLTS U1578 ( .B0(n1274), .B1(n1288), .A0N(n1294), .A1N(
Data_array_SWR[24]), .Y(n796) );
OAI2BB2XLTS U1579 ( .B0(n1273), .B1(n1288), .A0N(n1294), .A1N(
Data_array_SWR[23]), .Y(n795) );
AOI22X1TS U1580 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1280), .B0(n1279), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1276) );
OAI21XLTS U1581 ( .A0(n1483), .A1(n1282), .B0(n1276), .Y(n1277) );
AOI21X1TS U1582 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[12]), .B0(n1277), .Y(
n1285) );
AOI22X1TS U1583 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1280), .B0(n1279), .B1(
n898), .Y(n1281) );
OAI21XLTS U1584 ( .A0(n1503), .A1(n1282), .B0(n1281), .Y(n1283) );
AOI21X1TS U1585 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[10]), .B0(n1283), .Y(
n1286) );
AOI22X1TS U1586 ( .A0(n1294), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1289), .Y(n1293) );
AOI22X1TS U1587 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1117), .B0(n1291), .B1(
n1290), .Y(n1292) );
NAND2X1TS U1588 ( .A(n1293), .B(n1292), .Y(n771) );
NAND2X1TS U1589 ( .A(n1296), .B(n1295), .Y(n770) );
AOI21X1TS U1590 ( .A0(n1335), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1298) );
OAI22X1TS U1591 ( .A0(n1299), .A1(n1298), .B0(n1297), .B1(n1512), .Y(n769)
);
INVX4TS U1592 ( .A(n1323), .Y(n1329) );
CLKINVX1TS U1593 ( .A(DmP_EXP_EWSW[23]), .Y(n1300) );
AOI21X1TS U1594 ( .A0(DMP_EXP_EWSW[23]), .A1(n1300), .B0(n1305), .Y(n1301)
);
AOI2BB2XLTS U1595 ( .B0(n1329), .B1(n1301), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1488), .Y(n766) );
NOR2X1TS U1596 ( .A(n1501), .B(DMP_EXP_EWSW[24]), .Y(n1304) );
AOI21X1TS U1597 ( .A0(DMP_EXP_EWSW[24]), .A1(n1501), .B0(n1304), .Y(n1302)
);
XNOR2X1TS U1598 ( .A(n1305), .B(n1302), .Y(n1303) );
AO22XLTS U1599 ( .A0(n1488), .A1(n1303), .B0(n1331), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
OAI22X1TS U1600 ( .A0(n1305), .A1(n1304), .B0(DmP_EXP_EWSW[24]), .B1(n1502),
.Y(n1308) );
NAND2X1TS U1601 ( .A(DmP_EXP_EWSW[25]), .B(n1557), .Y(n1309) );
OAI21XLTS U1602 ( .A0(DmP_EXP_EWSW[25]), .A1(n1557), .B0(n1309), .Y(n1306)
);
XNOR2X1TS U1603 ( .A(n1308), .B(n1306), .Y(n1307) );
AO22XLTS U1604 ( .A0(n1488), .A1(n1307), .B0(n1333), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AOI22X1TS U1605 ( .A0(DMP_EXP_EWSW[25]), .A1(n1569), .B0(n1309), .B1(n1308),
.Y(n1312) );
NOR2X1TS U1606 ( .A(n1564), .B(DMP_EXP_EWSW[26]), .Y(n1313) );
AOI21X1TS U1607 ( .A0(DMP_EXP_EWSW[26]), .A1(n1564), .B0(n1313), .Y(n1310)
);
XNOR2X1TS U1608 ( .A(n1312), .B(n1310), .Y(n1311) );
AO22XLTS U1609 ( .A0(n1488), .A1(n1311), .B0(n1323), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
OAI22X1TS U1610 ( .A0(n1313), .A1(n1312), .B0(DmP_EXP_EWSW[26]), .B1(n1568),
.Y(n1315) );
XNOR2X1TS U1611 ( .A(DmP_EXP_EWSW[27]), .B(n902), .Y(n1314) );
XOR2XLTS U1612 ( .A(n1315), .B(n1314), .Y(n1316) );
AO22XLTS U1613 ( .A0(n1488), .A1(n1316), .B0(n1333), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
OAI222X1TS U1614 ( .A0(n1324), .A1(n1567), .B0(n1502), .B1(
Shift_reg_FLAGS_7_6), .C0(n1487), .C1(n1326), .Y(n729) );
OAI222X1TS U1615 ( .A0(n1324), .A1(n1504), .B0(n1557), .B1(
Shift_reg_FLAGS_7_6), .C0(n1545), .C1(n1326), .Y(n728) );
OAI222X1TS U1616 ( .A0(n1324), .A1(n1505), .B0(n1568), .B1(
Shift_reg_FLAGS_7_6), .C0(n1550), .C1(n1326), .Y(n727) );
OAI21XLTS U1617 ( .A0(n1318), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1317) );
AOI21X1TS U1618 ( .A0(n1318), .A1(intDX_EWSW[31]), .B0(n1317), .Y(n1319) );
AO21XLTS U1619 ( .A0(OP_FLAG_EXP), .A1(n997), .B0(n1319), .Y(n722) );
AO22XLTS U1620 ( .A0(n1320), .A1(n1319), .B0(ZERO_FLAG_EXP), .B1(n997), .Y(
n721) );
AO22XLTS U1621 ( .A0(n1488), .A1(DMP_EXP_EWSW[0]), .B0(n1333), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1622 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1574), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
NAND2X1TS U1623 ( .A(n896), .B(n1420), .Y(n1321) );
INVX4TS U1624 ( .A(n1454), .Y(n1451) );
AO22XLTS U1625 ( .A0(n1488), .A1(DMP_EXP_EWSW[1]), .B0(n1331), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1626 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1574), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1627 ( .A0(n1488), .A1(DMP_EXP_EWSW[2]), .B0(n1323), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1628 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1574), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
INVX4TS U1629 ( .A(n1454), .Y(n1453) );
AO22XLTS U1630 ( .A0(n1454), .A1(DMP_SFG[2]), .B0(n1453), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1631 ( .A0(n1332), .A1(DMP_EXP_EWSW[3]), .B0(n1331), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1632 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1574), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1633 ( .A0(n1454), .A1(DMP_SFG[3]), .B0(n1453), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1634 ( .A0(n1332), .A1(DMP_EXP_EWSW[4]), .B0(n1333), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1635 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1574), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1636 ( .A0(n1454), .A1(DMP_SFG[4]), .B0(n1453), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1637 ( .A0(n1332), .A1(DMP_EXP_EWSW[5]), .B0(n1331), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1638 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1574), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1639 ( .A0(n1471), .A1(DMP_SHT2_EWSW[5]), .B0(n1469), .B1(
DMP_SFG[5]), .Y(n702) );
AO22XLTS U1640 ( .A0(n1332), .A1(DMP_EXP_EWSW[6]), .B0(n1323), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1641 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1574), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
BUFX3TS U1642 ( .A(n1454), .Y(n1447) );
AO22XLTS U1643 ( .A0(n1447), .A1(DMP_SFG[6]), .B0(n1453), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
AO22XLTS U1644 ( .A0(n1332), .A1(DMP_EXP_EWSW[7]), .B0(n1333), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1645 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1574), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1646 ( .A0(n1454), .A1(DMP_SFG[7]), .B0(n1453), .B1(
DMP_SHT2_EWSW[7]), .Y(n696) );
AO22XLTS U1647 ( .A0(n1332), .A1(DMP_EXP_EWSW[8]), .B0(n1331), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1648 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1574), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1649 ( .A0(n1454), .A1(DMP_SFG[8]), .B0(n1453), .B1(
DMP_SHT2_EWSW[8]), .Y(n693) );
AO22XLTS U1650 ( .A0(n1332), .A1(DMP_EXP_EWSW[9]), .B0(n1331), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1651 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1574), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1652 ( .A0(n1471), .A1(DMP_SHT2_EWSW[9]), .B0(n1469), .B1(
DMP_SFG[9]), .Y(n690) );
AO22XLTS U1653 ( .A0(n1332), .A1(DMP_EXP_EWSW[10]), .B0(n1333), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
BUFX4TS U1654 ( .A(n1574), .Y(n1330) );
AO22XLTS U1655 ( .A0(n1335), .A1(DMP_SHT1_EWSW[10]), .B0(n1330), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1656 ( .A0(n1454), .A1(DMP_SFG[10]), .B0(n1451), .B1(
DMP_SHT2_EWSW[10]), .Y(n687) );
BUFX4TS U1657 ( .A(n1571), .Y(n1333) );
AO22XLTS U1658 ( .A0(n1332), .A1(DMP_EXP_EWSW[11]), .B0(n1571), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1659 ( .A0(n1335), .A1(DMP_SHT1_EWSW[11]), .B0(n1330), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1660 ( .A0(n1447), .A1(DMP_SFG[11]), .B0(n1453), .B1(
DMP_SHT2_EWSW[11]), .Y(n684) );
AO22XLTS U1661 ( .A0(n1332), .A1(DMP_EXP_EWSW[12]), .B0(n1331), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1662 ( .A0(n1335), .A1(DMP_SHT1_EWSW[12]), .B0(n1330), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1663 ( .A0(n1454), .A1(DMP_SFG[12]), .B0(n1453), .B1(
DMP_SHT2_EWSW[12]), .Y(n681) );
AO22XLTS U1664 ( .A0(n1332), .A1(DMP_EXP_EWSW[13]), .B0(n1333), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1665 ( .A0(n1335), .A1(DMP_SHT1_EWSW[13]), .B0(n1330), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1666 ( .A0(n1447), .A1(DMP_SFG[13]), .B0(n1453), .B1(
DMP_SHT2_EWSW[13]), .Y(n678) );
AO22XLTS U1667 ( .A0(n1332), .A1(DMP_EXP_EWSW[14]), .B0(n1331), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1668 ( .A0(n1335), .A1(DMP_SHT1_EWSW[14]), .B0(n1330), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1669 ( .A0(n1454), .A1(DMP_SFG[14]), .B0(n1453), .B1(
DMP_SHT2_EWSW[14]), .Y(n675) );
AO22XLTS U1670 ( .A0(n1332), .A1(DMP_EXP_EWSW[15]), .B0(n1571), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1671 ( .A0(n1335), .A1(DMP_SHT1_EWSW[15]), .B0(n1330), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1672 ( .A0(n1447), .A1(DMP_SFG[15]), .B0(n1453), .B1(
DMP_SHT2_EWSW[15]), .Y(n672) );
AO22XLTS U1673 ( .A0(n1332), .A1(DMP_EXP_EWSW[16]), .B0(n1331), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1674 ( .A0(n1335), .A1(DMP_SHT1_EWSW[16]), .B0(n1330), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1675 ( .A0(n1454), .A1(DMP_SFG[16]), .B0(n1451), .B1(
DMP_SHT2_EWSW[16]), .Y(n669) );
INVX4TS U1676 ( .A(n1323), .Y(n1334) );
AO22XLTS U1677 ( .A0(n1334), .A1(DMP_EXP_EWSW[17]), .B0(n1333), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1678 ( .A0(n1335), .A1(DMP_SHT1_EWSW[17]), .B0(n1330), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1679 ( .A0(n1447), .A1(DMP_SFG[17]), .B0(n1453), .B1(
DMP_SHT2_EWSW[17]), .Y(n666) );
AO22XLTS U1680 ( .A0(n1334), .A1(DMP_EXP_EWSW[18]), .B0(n1331), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1681 ( .A0(n1335), .A1(DMP_SHT1_EWSW[18]), .B0(n1330), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1682 ( .A0(n1454), .A1(DMP_SFG[18]), .B0(n1451), .B1(
DMP_SHT2_EWSW[18]), .Y(n663) );
BUFX4TS U1683 ( .A(n1571), .Y(n1323) );
AO22XLTS U1684 ( .A0(n1334), .A1(DMP_EXP_EWSW[19]), .B0(n1333), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1685 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1330), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1686 ( .A0(n1447), .A1(DMP_SFG[19]), .B0(n1453), .B1(
DMP_SHT2_EWSW[19]), .Y(n660) );
AO22XLTS U1687 ( .A0(n1334), .A1(DMP_EXP_EWSW[20]), .B0(n1323), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1688 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1330), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1689 ( .A0(n1447), .A1(DMP_SFG[20]), .B0(n1451), .B1(
DMP_SHT2_EWSW[20]), .Y(n657) );
AO22XLTS U1690 ( .A0(n1334), .A1(DMP_EXP_EWSW[21]), .B0(n1333), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1691 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1330), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1692 ( .A0(n1447), .A1(DMP_SFG[21]), .B0(n1451), .B1(
DMP_SHT2_EWSW[21]), .Y(n654) );
AO22XLTS U1693 ( .A0(n1334), .A1(DMP_EXP_EWSW[22]), .B0(n1333), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1694 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n1574), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1695 ( .A0(n1447), .A1(DMP_SFG[22]), .B0(n1451), .B1(
DMP_SHT2_EWSW[22]), .Y(n651) );
AO22XLTS U1696 ( .A0(n1334), .A1(DMP_EXP_EWSW[23]), .B0(n1331), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1697 ( .A0(n1335), .A1(DMP_SHT1_EWSW[23]), .B0(n1574), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1698 ( .A0(n1471), .A1(DMP_SHT2_EWSW[23]), .B0(n1447), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1699 ( .A0(n873), .A1(DMP_SFG[23]), .B0(n1603), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1700 ( .A0(n1334), .A1(DMP_EXP_EWSW[24]), .B0(n1323), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1701 ( .A0(n1335), .A1(DMP_SHT1_EWSW[24]), .B0(n1330), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1702 ( .A0(n1451), .A1(DMP_SHT2_EWSW[24]), .B0(n1469), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1703 ( .A0(n873), .A1(DMP_SFG[24]), .B0(n1603), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1704 ( .A0(n1334), .A1(DMP_EXP_EWSW[25]), .B0(n1331), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1705 ( .A0(n1335), .A1(DMP_SHT1_EWSW[25]), .B0(n1330), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1706 ( .A0(n1471), .A1(DMP_SHT2_EWSW[25]), .B0(n1469), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1707 ( .A0(n873), .A1(DMP_SFG[25]), .B0(n1603), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1708 ( .A0(n1334), .A1(DMP_EXP_EWSW[26]), .B0(n1333), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1709 ( .A0(n1335), .A1(DMP_SHT1_EWSW[26]), .B0(n1330), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1710 ( .A0(n1471), .A1(DMP_SHT2_EWSW[26]), .B0(n1454), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1711 ( .A0(n873), .A1(DMP_SFG[26]), .B0(n1603), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1712 ( .A0(n1334), .A1(n902), .B0(n1331), .B1(DMP_SHT1_EWSW[27]),
.Y(n630) );
AO22XLTS U1713 ( .A0(n1335), .A1(DMP_SHT1_EWSW[27]), .B0(n1330), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1714 ( .A0(n1451), .A1(DMP_SHT2_EWSW[27]), .B0(n1469), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1715 ( .A0(n873), .A1(DMP_SFG[27]), .B0(n1357), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1716 ( .A0(n1334), .A1(DMP_EXP_EWSW[28]), .B0(n1571), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1717 ( .A0(n1335), .A1(DMP_SHT1_EWSW[28]), .B0(n1330), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1718 ( .A0(n1451), .A1(DMP_SHT2_EWSW[28]), .B0(n1454), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1719 ( .A0(n873), .A1(DMP_SFG[28]), .B0(n1357), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1720 ( .A0(n1334), .A1(DMP_EXP_EWSW[29]), .B0(n1333), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1721 ( .A0(n1335), .A1(DMP_SHT1_EWSW[29]), .B0(n1330), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1722 ( .A0(n1471), .A1(DMP_SHT2_EWSW[29]), .B0(n1469), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1723 ( .A0(n1359), .A1(DMP_SFG[29]), .B0(n1357), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1724 ( .A0(n1329), .A1(DMP_EXP_EWSW[30]), .B0(n1331), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1725 ( .A0(n1335), .A1(DMP_SHT1_EWSW[30]), .B0(n1330), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1726 ( .A0(n1451), .A1(DMP_SHT2_EWSW[30]), .B0(n1469), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1727 ( .A0(n1359), .A1(DMP_SFG[30]), .B0(n1357), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1728 ( .A0(n1332), .A1(DmP_EXP_EWSW[14]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U1729 ( .A0(n1332), .A1(DmP_EXP_EWSW[17]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U1730 ( .A0(n1332), .A1(DmP_EXP_EWSW[19]), .B0(n1571), .B1(n900),
.Y(n571) );
AO22XLTS U1731 ( .A0(n1332), .A1(DmP_EXP_EWSW[22]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
OAI222X1TS U1732 ( .A0(n1326), .A1(n1567), .B0(n1501), .B1(
Shift_reg_FLAGS_7_6), .C0(n1487), .C1(n1324), .Y(n563) );
OAI222X1TS U1733 ( .A0(n1326), .A1(n1504), .B0(n1569), .B1(
Shift_reg_FLAGS_7_6), .C0(n1545), .C1(n1324), .Y(n562) );
OAI222X1TS U1734 ( .A0(n1326), .A1(n1505), .B0(n1564), .B1(
Shift_reg_FLAGS_7_6), .C0(n1550), .C1(n1324), .Y(n561) );
INVX4TS U1735 ( .A(n1327), .Y(n1424) );
NAND2X1TS U1736 ( .A(n1361), .B(Shift_reg_FLAGS_7[0]), .Y(n1328) );
OAI2BB1X1TS U1737 ( .A0N(underflow_flag), .A1N(n1424), .B0(n1328), .Y(n559)
);
AO22XLTS U1738 ( .A0(n1329), .A1(ZERO_FLAG_EXP), .B0(n1323), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
AO22XLTS U1739 ( .A0(n1335), .A1(ZERO_FLAG_SHT1), .B0(n1330), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1740 ( .A0(n1451), .A1(ZERO_FLAG_SHT2), .B0(n1469), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1741 ( .A0(n873), .A1(ZERO_FLAG_SFG), .B0(n1357), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1742 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n1336),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1743 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1424), .B1(zero_flag), .Y(n552) );
AO22XLTS U1744 ( .A0(n1332), .A1(OP_FLAG_EXP), .B0(n1331), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1745 ( .A0(n1335), .A1(OP_FLAG_SHT1), .B0(n1574), .B1(OP_FLAG_SHT2), .Y(n550) );
AO22XLTS U1746 ( .A0(n1447), .A1(OP_FLAG_SFG), .B0(n1451), .B1(OP_FLAG_SHT2),
.Y(n549) );
AO22XLTS U1747 ( .A0(n1334), .A1(SIGN_FLAG_EXP), .B0(n1331), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1748 ( .A0(n1335), .A1(SIGN_FLAG_SHT1), .B0(n1574), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1749 ( .A0(n1451), .A1(SIGN_FLAG_SHT2), .B0(n1454), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1750 ( .A0(n873), .A1(SIGN_FLAG_SFG), .B0(n1357), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1751 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n1336),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n544) );
AOI22X1TS U1752 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1352), .B0(n1355), .B1(n911), .Y(n1338) );
AOI22X1TS U1753 ( .A0(n1359), .A1(n1338), .B0(n1486), .B1(n1357), .Y(n542)
);
AOI22X1TS U1754 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1354), .B0(n1351), .B1(n912), .Y(n1339) );
AOI22X1TS U1755 ( .A0(n1359), .A1(n1339), .B0(n1556), .B1(n1357), .Y(n541)
);
OAI21XLTS U1756 ( .A0(n1340), .A1(DMP_SFG[0]), .B0(n1342), .Y(n1341) );
AOI22X1TS U1757 ( .A0(n1359), .A1(n1341), .B0(n1511), .B1(n1357), .Y(n540)
);
XNOR2X1TS U1758 ( .A(DMP_SFG[1]), .B(n1342), .Y(n1343) );
XNOR2X1TS U1759 ( .A(n1343), .B(n893), .Y(n1344) );
AOI22X1TS U1760 ( .A0(n1359), .A1(n1344), .B0(n1553), .B1(n1603), .Y(n539)
);
AOI2BB2XLTS U1761 ( .B0(n873), .B1(intadd_59_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n873), .Y(n538) );
AOI22X1TS U1762 ( .A0(n1359), .A1(intadd_59_SUM_1_), .B0(n1513), .B1(n1357),
.Y(n537) );
AOI22X1TS U1763 ( .A0(n1359), .A1(intadd_59_SUM_2_), .B0(n1479), .B1(n1357),
.Y(n536) );
XNOR2X1TS U1764 ( .A(DMP_SFG[5]), .B(n894), .Y(n1345) );
XNOR2X1TS U1765 ( .A(intadd_59_n1), .B(n1345), .Y(n1346) );
AOI22X1TS U1766 ( .A0(n1359), .A1(n1346), .B0(n1485), .B1(n1357), .Y(n535)
);
AOI22X1TS U1767 ( .A0(n1359), .A1(intadd_58_SUM_0_), .B0(n1478), .B1(n1357),
.Y(n534) );
AOI22X1TS U1768 ( .A0(n1359), .A1(intadd_58_SUM_1_), .B0(n1480), .B1(n1357),
.Y(n533) );
AOI22X1TS U1769 ( .A0(n1359), .A1(intadd_58_SUM_2_), .B0(n1484), .B1(n1357),
.Y(n532) );
XNOR2X1TS U1770 ( .A(DMP_SFG[9]), .B(n1347), .Y(n1348) );
XNOR2X1TS U1771 ( .A(intadd_58_n1), .B(n1348), .Y(n1349) );
AOI22X1TS U1772 ( .A0(n1359), .A1(n1349), .B0(n1483), .B1(n1357), .Y(n531)
);
AOI2BB2XLTS U1773 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1354), .A0N(n1493),
.A1N(DmP_mant_SFG_SWR[12]), .Y(intadd_57_CI) );
AOI2BB2XLTS U1774 ( .B0(n873), .B1(intadd_57_SUM_0_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n873), .Y(n530) );
AOI2BB2XLTS U1775 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1354), .A0N(n1493),
.A1N(DmP_mant_SFG_SWR[13]), .Y(intadd_57_B_1_) );
AOI22X1TS U1776 ( .A0(n1359), .A1(intadd_57_SUM_1_), .B0(n1503), .B1(n1357),
.Y(n529) );
AOI2BB2XLTS U1777 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n1354), .A0N(n1493),
.A1N(DmP_mant_SFG_SWR[14]), .Y(intadd_57_B_2_) );
AOI22X1TS U1778 ( .A0(n1359), .A1(intadd_57_SUM_2_), .B0(n1491), .B1(n1357),
.Y(n528) );
AOI2BB2XLTS U1779 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n1354), .A0N(n1493),
.A1N(DmP_mant_SFG_SWR[15]), .Y(intadd_57_B_3_) );
AOI22X1TS U1780 ( .A0(n1359), .A1(intadd_57_SUM_3_), .B0(n1490), .B1(n1357),
.Y(n527) );
INVX1TS U1781 ( .A(DmP_mant_SFG_SWR[16]), .Y(n1455) );
AOI22X1TS U1782 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1352), .B0(n1351), .B1(
n1455), .Y(intadd_57_B_4_) );
AOI22X1TS U1783 ( .A0(n1359), .A1(intadd_57_SUM_4_), .B0(n1482), .B1(n1603),
.Y(n526) );
INVX1TS U1784 ( .A(DmP_mant_SFG_SWR[17]), .Y(n1457) );
AOI22X1TS U1785 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1352), .B0(n1351), .B1(
n1457), .Y(intadd_57_B_5_) );
AOI22X1TS U1786 ( .A0(n1359), .A1(intadd_57_SUM_5_), .B0(n1507), .B1(n1603),
.Y(n525) );
INVX1TS U1787 ( .A(DmP_mant_SFG_SWR[18]), .Y(n1459) );
AOI22X1TS U1788 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n1352), .B0(n1351), .B1(
n1459), .Y(intadd_57_B_6_) );
AOI2BB2XLTS U1789 ( .B0(n873), .B1(intadd_57_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n873), .Y(n524) );
INVX1TS U1790 ( .A(DmP_mant_SFG_SWR[19]), .Y(n1461) );
AOI22X1TS U1791 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1352), .B0(n1351), .B1(
n1461), .Y(intadd_57_B_7_) );
AOI2BB2XLTS U1792 ( .B0(n873), .B1(intadd_57_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n873), .Y(n523) );
INVX1TS U1793 ( .A(DmP_mant_SFG_SWR[20]), .Y(n1463) );
AOI22X1TS U1794 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1352), .B0(n1351), .B1(
n1463), .Y(intadd_57_B_8_) );
AOI2BB2XLTS U1795 ( .B0(n873), .B1(intadd_57_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n873), .Y(n522) );
INVX1TS U1796 ( .A(DmP_mant_SFG_SWR[21]), .Y(n1465) );
AOI22X1TS U1797 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1352), .B0(n1351), .B1(
n1465), .Y(intadd_57_B_9_) );
AOI22X1TS U1798 ( .A0(n1359), .A1(intadd_57_SUM_9_), .B0(n1508), .B1(n1603),
.Y(n521) );
AOI22X1TS U1799 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1352), .B0(n1351), .B1(
n908), .Y(intadd_57_B_10_) );
AOI22X1TS U1800 ( .A0(n1359), .A1(intadd_57_SUM_10_), .B0(n1506), .B1(n1603),
.Y(n520) );
AOI22X1TS U1801 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n1352), .B0(n1355), .B1(
n909), .Y(intadd_57_B_11_) );
AOI22X1TS U1802 ( .A0(n1359), .A1(intadd_57_SUM_11_), .B0(n1477), .B1(n1603),
.Y(n519) );
AOI22X1TS U1803 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1352), .B0(n1351), .B1(
n910), .Y(intadd_57_B_12_) );
AOI22X1TS U1804 ( .A0(n1359), .A1(intadd_57_SUM_12_), .B0(n1481), .B1(n1603),
.Y(n518) );
INVX1TS U1805 ( .A(DmP_mant_SFG_SWR[25]), .Y(n1474) );
AOI22X1TS U1806 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1355), .B0(n1354), .B1(
n1474), .Y(n1356) );
XNOR2X1TS U1807 ( .A(intadd_57_n1), .B(n1356), .Y(n1358) );
AOI22X1TS U1808 ( .A0(n1359), .A1(n1358), .B0(n1489), .B1(n1357), .Y(n517)
);
AND3X4TS U1809 ( .A(shift_value_SHT2_EWR[2]), .B(n1510), .C(
shift_value_SHT2_EWR[3]), .Y(n1427) );
NAND2X1TS U1810 ( .A(shift_value_SHT2_EWR[2]), .B(n1512), .Y(n1380) );
NAND2X1TS U1811 ( .A(n1400), .B(n1510), .Y(n1411) );
NOR2XLTS U1812 ( .A(n1434), .B(n1411), .Y(n1365) );
AOI22X1TS U1813 ( .A0(Data_array_SWR[11]), .A1(n1364), .B0(
Data_array_SWR[12]), .B1(n1435), .Y(n1366) );
OAI221X1TS U1814 ( .A0(n1473), .A1(n1368), .B0(n1434), .B1(n1369), .C0(n1366), .Y(n1448) );
AO22XLTS U1815 ( .A0(final_result_ieee[10]), .A1(n1424), .B0(n1381), .B1(
n1448), .Y(n511) );
AOI22X1TS U1816 ( .A0(Data_array_SWR[11]), .A1(n1435), .B0(
Data_array_SWR[12]), .B1(n1364), .Y(n1367) );
OAI221X1TS U1817 ( .A0(n1473), .A1(n1369), .B0(n1434), .B1(n1368), .C0(n1367), .Y(n1449) );
AO22XLTS U1818 ( .A0(n1381), .A1(n1449), .B0(final_result_ieee[11]), .B1(
n1424), .Y(n510) );
AOI22X1TS U1819 ( .A0(Data_array_SWR[21]), .A1(n1426), .B0(
Data_array_SWR[17]), .B1(n1363), .Y(n1373) );
AOI22X1TS U1820 ( .A0(Data_array_SWR[13]), .A1(n1435), .B0(n903), .B1(n1364),
.Y(n1370) );
OAI221X1TS U1821 ( .A0(n1473), .A1(n1372), .B0(n1434), .B1(n1373), .C0(n1370), .Y(n1446) );
AO22XLTS U1822 ( .A0(n1381), .A1(n1446), .B0(final_result_ieee[9]), .B1(
n1424), .Y(n509) );
AOI22X1TS U1823 ( .A0(Data_array_SWR[13]), .A1(n1364), .B0(n903), .B1(n1435),
.Y(n1371) );
OAI221X1TS U1824 ( .A0(n1473), .A1(n1373), .B0(n1434), .B1(n1372), .C0(n1371), .Y(n1450) );
AO22XLTS U1825 ( .A0(n1381), .A1(n1450), .B0(final_result_ieee[12]), .B1(
n1424), .Y(n508) );
AOI22X1TS U1826 ( .A0(Data_array_SWR[22]), .A1(n1426), .B0(
Data_array_SWR[18]), .B1(n1363), .Y(n1377) );
AOI22X1TS U1827 ( .A0(Data_array_SWR[10]), .A1(n1364), .B0(
Data_array_SWR[14]), .B1(n1435), .Y(n1374) );
OAI221X1TS U1828 ( .A0(n1473), .A1(n1376), .B0(n1434), .B1(n1377), .C0(n1374), .Y(n1445) );
AO22XLTS U1829 ( .A0(n1381), .A1(n1445), .B0(final_result_ieee[8]), .B1(
n1424), .Y(n507) );
AOI22X1TS U1830 ( .A0(Data_array_SWR[10]), .A1(n1435), .B0(
Data_array_SWR[14]), .B1(n1364), .Y(n1375) );
OAI221X1TS U1831 ( .A0(n1473), .A1(n1377), .B0(n1434), .B1(n1376), .C0(n1375), .Y(n1452) );
AO22XLTS U1832 ( .A0(n1381), .A1(n1452), .B0(final_result_ieee[13]), .B1(
n1424), .Y(n506) );
AOI22X1TS U1833 ( .A0(Data_array_SWR[16]), .A1(n1426), .B0(
Data_array_SWR[12]), .B1(n1363), .Y(n1379) );
CLKAND2X2TS U1834 ( .A(n1400), .B(shift_value_SHT2_EWR[4]), .Y(n1393) );
AOI22X1TS U1835 ( .A0(Data_array_SWR[20]), .A1(n1427), .B0(
Data_array_SWR[24]), .B1(n1393), .Y(n1378) );
NAND2X1TS U1836 ( .A(n1379), .B(n1378), .Y(n1383) );
NOR2X1TS U1837 ( .A(shift_value_SHT2_EWR[2]), .B(n1512), .Y(n1386) );
INVX2TS U1838 ( .A(n1380), .Y(n1401) );
INVX2TS U1839 ( .A(n1431), .Y(n1382) );
INVX4TS U1840 ( .A(n1381), .Y(n1425) );
OAI2BB2XLTS U1841 ( .B0(n1444), .B1(n1425), .A0N(final_result_ieee[7]),
.A1N(n1424), .Y(n505) );
OAI2BB2XLTS U1842 ( .B0(n1456), .B1(n1425), .A0N(final_result_ieee[14]),
.A1N(n1424), .Y(n504) );
AOI22X1TS U1843 ( .A0(Data_array_SWR[11]), .A1(n1363), .B0(
Data_array_SWR[15]), .B1(n1426), .Y(n1385) );
AOI22X1TS U1844 ( .A0(Data_array_SWR[23]), .A1(n1393), .B0(
Data_array_SWR[19]), .B1(n1427), .Y(n1384) );
NAND2X1TS U1845 ( .A(n1385), .B(n1384), .Y(n1388) );
INVX2TS U1846 ( .A(n1423), .Y(n1387) );
OAI2BB2XLTS U1847 ( .B0(n1443), .B1(n1425), .A0N(final_result_ieee[6]),
.A1N(n1424), .Y(n503) );
OAI2BB2XLTS U1848 ( .B0(n1458), .B1(n1425), .A0N(final_result_ieee[15]),
.A1N(n1424), .Y(n502) );
AOI22X1TS U1849 ( .A0(Data_array_SWR[14]), .A1(n1426), .B0(n903), .B1(n1363),
.Y(n1390) );
AOI22X1TS U1850 ( .A0(Data_array_SWR[22]), .A1(n1393), .B0(
Data_array_SWR[18]), .B1(n1427), .Y(n1389) );
NAND2X1TS U1851 ( .A(n1390), .B(n1389), .Y(n1392) );
AOI22X1TS U1852 ( .A0(Data_array_SWR[21]), .A1(n1401), .B0(
Data_array_SWR[17]), .B1(n1400), .Y(n1417) );
INVX2TS U1853 ( .A(n1417), .Y(n1391) );
OAI2BB2XLTS U1854 ( .B0(n1442), .B1(n1425), .A0N(final_result_ieee[5]),
.A1N(n1424), .Y(n501) );
OAI2BB2XLTS U1855 ( .B0(n1460), .B1(n1425), .A0N(final_result_ieee[16]),
.A1N(n1424), .Y(n500) );
AOI22X1TS U1856 ( .A0(Data_array_SWR[13]), .A1(n1426), .B0(
Data_array_SWR[10]), .B1(n1363), .Y(n1395) );
AOI22X1TS U1857 ( .A0(Data_array_SWR[21]), .A1(n1393), .B0(
Data_array_SWR[17]), .B1(n1427), .Y(n1394) );
NAND2X1TS U1858 ( .A(n1395), .B(n1394), .Y(n1397) );
AOI22X1TS U1859 ( .A0(Data_array_SWR[22]), .A1(n1401), .B0(
Data_array_SWR[18]), .B1(n1400), .Y(n1414) );
INVX2TS U1860 ( .A(n1414), .Y(n1396) );
OAI2BB2XLTS U1861 ( .B0(n1441), .B1(n1425), .A0N(final_result_ieee[4]),
.A1N(n1420), .Y(n499) );
OAI2BB2XLTS U1862 ( .B0(n1462), .B1(n1425), .A0N(final_result_ieee[17]),
.A1N(n1420), .Y(n498) );
AOI22X1TS U1863 ( .A0(Data_array_SWR[20]), .A1(n1400), .B0(
Data_array_SWR[24]), .B1(n1401), .Y(n1406) );
AOI22X1TS U1864 ( .A0(Data_array_SWR[12]), .A1(n1426), .B0(Data_array_SWR[9]), .B1(n1363), .Y(n1399) );
NAND2X1TS U1865 ( .A(Data_array_SWR[16]), .B(n1427), .Y(n1398) );
OAI211X1TS U1866 ( .A0(n1406), .A1(n1510), .B0(n1399), .C0(n1398), .Y(n1402)
);
AO22X1TS U1867 ( .A0(Data_array_SWR[23]), .A1(n1401), .B0(Data_array_SWR[19]), .B1(n1400), .Y(n1403) );
OAI2BB2XLTS U1868 ( .B0(n1440), .B1(n1425), .A0N(final_result_ieee[3]),
.A1N(n1420), .Y(n497) );
OAI2BB2XLTS U1869 ( .B0(n1464), .B1(n1425), .A0N(final_result_ieee[18]),
.A1N(n1420), .Y(n496) );
AOI22X1TS U1870 ( .A0(Data_array_SWR[11]), .A1(n1426), .B0(Data_array_SWR[8]), .B1(n1363), .Y(n1405) );
AOI22X1TS U1871 ( .A0(Data_array_SWR[15]), .A1(n1427), .B0(
shift_value_SHT2_EWR[4]), .B1(n1403), .Y(n1404) );
NAND2X1TS U1872 ( .A(n1405), .B(n1404), .Y(n1410) );
INVX2TS U1873 ( .A(n1406), .Y(n1409) );
OAI2BB2XLTS U1874 ( .B0(n1439), .B1(n1425), .A0N(final_result_ieee[2]),
.A1N(n1420), .Y(n495) );
OAI2BB2XLTS U1875 ( .B0(n1466), .B1(n1425), .A0N(final_result_ieee[19]),
.A1N(n1420), .Y(n494) );
AOI22X1TS U1876 ( .A0(Data_array_SWR[14]), .A1(n1427), .B0(n903), .B1(n1426),
.Y(n1413) );
INVX2TS U1877 ( .A(n1411), .Y(n1428) );
AOI22X1TS U1878 ( .A0(Data_array_SWR[7]), .A1(n1363), .B0(Data_array_SWR[3]),
.B1(n1428), .Y(n1412) );
OAI211X1TS U1879 ( .A0(n1414), .A1(n1510), .B0(n1413), .C0(n1412), .Y(n1418)
);
AOI22X1TS U1880 ( .A0(Data_array_SWR[21]), .A1(n1435), .B0(n1434), .B1(n1418), .Y(n1438) );
OAI2BB2XLTS U1881 ( .B0(n1438), .B1(n1425), .A0N(final_result_ieee[1]),
.A1N(n1420), .Y(n493) );
AOI22X1TS U1882 ( .A0(Data_array_SWR[13]), .A1(n1427), .B0(
Data_array_SWR[10]), .B1(n1426), .Y(n1416) );
AOI22X1TS U1883 ( .A0(Data_array_SWR[6]), .A1(n1363), .B0(Data_array_SWR[2]),
.B1(n1428), .Y(n1415) );
OAI211X1TS U1884 ( .A0(n1417), .A1(n1510), .B0(n1416), .C0(n1415), .Y(n1419)
);
AOI22X1TS U1885 ( .A0(Data_array_SWR[22]), .A1(n1435), .B0(n1434), .B1(n1419), .Y(n1437) );
OAI2BB2XLTS U1886 ( .B0(n1437), .B1(n1425), .A0N(final_result_ieee[0]),
.A1N(n1420), .Y(n492) );
AOI22X1TS U1887 ( .A0(Data_array_SWR[21]), .A1(n1364), .B0(n1473), .B1(n1418), .Y(n1467) );
OAI2BB2XLTS U1888 ( .B0(n1467), .B1(n1425), .A0N(final_result_ieee[20]),
.A1N(n1420), .Y(n491) );
AOI22X1TS U1889 ( .A0(Data_array_SWR[22]), .A1(n1364), .B0(n1473), .B1(n1419), .Y(n1468) );
OAI2BB2XLTS U1890 ( .B0(n1468), .B1(n1425), .A0N(final_result_ieee[21]),
.A1N(n1420), .Y(n490) );
AOI22X1TS U1891 ( .A0(Data_array_SWR[12]), .A1(n1427), .B0(Data_array_SWR[9]), .B1(n1426), .Y(n1422) );
AOI22X1TS U1892 ( .A0(Data_array_SWR[5]), .A1(n1363), .B0(Data_array_SWR[1]),
.B1(n1428), .Y(n1421) );
OAI211X1TS U1893 ( .A0(n1423), .A1(n1510), .B0(n1422), .C0(n1421), .Y(n1433)
);
AOI22X1TS U1894 ( .A0(Data_array_SWR[23]), .A1(n1364), .B0(n1473), .B1(n1433), .Y(n1470) );
OAI2BB2XLTS U1895 ( .B0(n1470), .B1(n1425), .A0N(final_result_ieee[22]),
.A1N(n1424), .Y(n489) );
AOI22X1TS U1896 ( .A0(Data_array_SWR[11]), .A1(n1427), .B0(Data_array_SWR[8]), .B1(n1426), .Y(n1430) );
AOI22X1TS U1897 ( .A0(Data_array_SWR[4]), .A1(n1363), .B0(Data_array_SWR[0]),
.B1(n1428), .Y(n1429) );
OAI211X1TS U1898 ( .A0(n1431), .A1(n1510), .B0(n1430), .C0(n1429), .Y(n1472)
);
AOI22X1TS U1899 ( .A0(Data_array_SWR[24]), .A1(n1435), .B0(n1434), .B1(n1472), .Y(n1432) );
AOI22X1TS U1900 ( .A0(n1476), .A1(n1432), .B0(n1447), .B1(n911), .Y(n488) );
AOI22X1TS U1901 ( .A0(Data_array_SWR[23]), .A1(n1435), .B0(n1434), .B1(n1433), .Y(n1436) );
AOI22X1TS U1902 ( .A0(n1476), .A1(n1436), .B0(n1447), .B1(n912), .Y(n487) );
AOI22X1TS U1903 ( .A0(n1476), .A1(n1437), .B0(n1454), .B1(n913), .Y(n486) );
AOI22X1TS U1904 ( .A0(n1476), .A1(n1438), .B0(n1469), .B1(n917), .Y(n485) );
AOI22X1TS U1905 ( .A0(n1471), .A1(n1439), .B0(n1454), .B1(n918), .Y(n484) );
AOI22X1TS U1906 ( .A0(n1476), .A1(n1440), .B0(n916), .B1(n1469), .Y(n483) );
AOI22X1TS U1907 ( .A0(n1476), .A1(n1441), .B0(n1454), .B1(n915), .Y(n482) );
AOI22X1TS U1908 ( .A0(n1471), .A1(n1442), .B0(n1469), .B1(n914), .Y(n481) );
AOI22X1TS U1909 ( .A0(n1471), .A1(n1443), .B0(n1454), .B1(n907), .Y(n480) );
AOI22X1TS U1910 ( .A0(n1471), .A1(n1444), .B0(n877), .B1(n1469), .Y(n479) );
AO22XLTS U1911 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[10]), .B0(n1453), .B1(
n1445), .Y(n478) );
AO22XLTS U1912 ( .A0(n1447), .A1(DmP_mant_SFG_SWR[11]), .B0(n1453), .B1(
n1446), .Y(n477) );
AO22XLTS U1913 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[12]), .B0(n1453), .B1(
n1448), .Y(n476) );
AO22XLTS U1914 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[13]), .B0(n1451), .B1(
n1449), .Y(n475) );
AO22XLTS U1915 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[14]), .B0(n1451), .B1(
n1450), .Y(n474) );
AO22XLTS U1916 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[15]), .B0(n1453), .B1(
n1452), .Y(n473) );
AOI22X1TS U1917 ( .A0(n1471), .A1(n1456), .B0(n1455), .B1(n1469), .Y(n472)
);
AOI22X1TS U1918 ( .A0(n1476), .A1(n1458), .B0(n1457), .B1(n1469), .Y(n471)
);
AOI22X1TS U1919 ( .A0(n1476), .A1(n1460), .B0(n1459), .B1(n1469), .Y(n470)
);
AOI22X1TS U1920 ( .A0(n1476), .A1(n1462), .B0(n1461), .B1(n1469), .Y(n469)
);
AOI22X1TS U1921 ( .A0(n1476), .A1(n1464), .B0(n1463), .B1(n1469), .Y(n468)
);
AOI22X1TS U1922 ( .A0(n1476), .A1(n1466), .B0(n1465), .B1(n1469), .Y(n467)
);
AOI22X1TS U1923 ( .A0(n1476), .A1(n1467), .B0(n1469), .B1(n908), .Y(n466) );
AOI22X1TS U1924 ( .A0(n1476), .A1(n1468), .B0(n1469), .B1(n909), .Y(n465) );
AOI22X1TS U1925 ( .A0(n1476), .A1(n1470), .B0(n1469), .B1(n910), .Y(n464) );
AOI22X1TS U1926 ( .A0(Data_array_SWR[24]), .A1(n1364), .B0(n1473), .B1(n1472), .Y(n1475) );
AOI22X1TS U1927 ( .A0(n1476), .A1(n1475), .B0(n1474), .B1(n1469), .Y(n463)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_GeArN16R4P4_syn.sdf");
endmodule
|
module IPE_IF(
clk,
ammc_clk,
card0_clk,
card1_clk,
card0_refclk,
card1_refclk,
reconfig_clk,
ue1_clk,
reset,
//XAUI
line0_xaui_rxdat,
line0_xaui_txdat,
line1_xaui_rxdat,
line1_xaui_txdat,
//gmii
slot0_gm_tx_clk,
slot0_gm_rx_clk,
slot0_gm_tx_d,
slot0_gm_tx_en,
slot0_gm_tx_err,
slot0_gm_rx_d,
slot0_gm_rx_dv,
slot0_gm_rx_err,
slot1_gm_tx_clk,
slot1_gm_rx_clk,
slot1_gm_tx_d,
slot1_gm_tx_en,
slot1_gm_tx_err,
slot1_gm_rx_d,
slot1_gm_rx_dv,
slot1_gm_rx_err,
//egress
in_egress_pkt_wr,
in_egress_pkt,
out_egress_pkt_almostfull,
in_egress_pkt_valid_wr,
in_egress_pkt_valid,
//ingress
out_ingress_pkt_wr,
out_ingress_pkt,
in_ingress_pkt_almostfull,
out_ingress_valid_wr,
out_ingress_valid,
slot0_port0_address,
slot0_port0_write,
slot0_port0_read,
slot0_port0_writedata,
slot0_port0_readdata,
slot0_port0_waitrequest,
slot0_port1_address,
slot0_port1_write,
slot0_port1_read,
slot0_port1_writedata,
slot0_port1_readdata,
slot0_port1_waitrequest,
slot0_port2_address,
slot0_port2_write,
slot0_port2_read,
slot0_port2_writedata,
slot0_port2_readdata,
slot0_port2_waitrequest,
slot0_port3_address,
slot0_port3_write,
slot0_port3_read,
slot0_port3_writedata,
slot0_port3_readdata,
slot0_port3_waitrequest,
slot0_port4_address,
slot0_port4_write,
slot0_port4_read,
slot0_port4_writedata,
slot0_port4_readdata,
slot0_port4_waitrequest,
slot1_port0_address,
slot1_port0_write,
slot1_port0_read,
slot1_port0_writedata,
slot1_port0_readdata,
slot1_port0_waitrequest,
slot1_port1_address,
slot1_port1_write,
slot1_port1_read,
slot1_port1_writedata,
slot1_port1_readdata,
slot1_port1_waitrequest,
slot1_port2_address,
slot1_port2_write,
slot1_port2_read,
slot1_port2_writedata,
slot1_port2_readdata,
slot1_port2_waitrequest,
slot1_port3_address,
slot1_port3_write,
slot1_port3_read,
slot1_port3_writedata,
slot1_port3_readdata,
slot1_port3_waitrequest,
slot1_port4_address,
slot1_port4_write,
slot1_port4_read,
slot1_port4_writedata,
slot1_port4_readdata,
slot1_port4_waitrequest,
//port count
slot0_port0_pkt_receive_add,
slot0_port0_pkt_discard_add,
slot0_port0_pkt_send_add,
slot0_port1_pkt_receive_add,
slot0_port1_pkt_discard_add,
slot0_port1_pkt_send_add,
slot0_port2_pkt_receive_add,
slot0_port2_pkt_discard_add,
slot0_port2_pkt_send_add,
slot0_port3_pkt_receive_add,
slot0_port3_pkt_discard_add,
slot0_port3_pkt_send_add,
slot0_port4_pkt_receive_add,
slot0_port4_pkt_discard_add,
slot0_port4_pkt_send_add,
slot1_port0_pkt_receive_add,
slot1_port0_pkt_discard_add,
slot1_port0_pkt_send_add,
slot1_port1_pkt_receive_add,
slot1_port1_pkt_discard_add,
slot1_port1_pkt_send_add,
slot1_port2_pkt_receive_add,
slot1_port2_pkt_discard_add,
slot1_port2_pkt_send_add,
slot1_port3_pkt_receive_add,
slot1_port3_pkt_discard_add,
slot1_port3_pkt_send_add,
slot1_port4_pkt_receive_add,
slot1_port4_pkt_discard_add,
slot1_port4_pkt_send_add,
//mux count
mux0_receive_pkt_add,
mux0_discard_error_pkt_add,
mux1_receive_pkt_add,
mux1_discard_error_pkt_add,
//dmux count
dmux0_receive_pkt_add,
dmux0_discard_error_pkt_add,
dmux0_send_port0_pkt_add,
dmux0_send_port1_pkt_add,
dmux0_send_port2_pkt_add,
dmux0_send_port3_pkt_add,
dmux0_send_port4_pkt_add,
dmux1_receive_pkt_add,
dmux1_discard_error_pkt_add,
dmux1_send_port0_pkt_add,
dmux1_send_port1_pkt_add,
dmux1_send_port2_pkt_add,
dmux1_send_port3_pkt_add,
dmux1_send_port4_pkt_add,
//input ctl count
inputctl_receive_pkt_add,
output_receive_pkt_add,
output_discard_error_pkt_add,
output_send_slot0_pkt_add,
output_send_slot1_pkt_add);
input clk;
input ammc_clk;
input card0_refclk;
input card1_refclk;
input reconfig_clk;
input card0_clk;
input card1_clk;
input ue1_clk;
input reset;
//XAUI
input [3:0] line0_xaui_rxdat;
output [3:0] line0_xaui_txdat;
input [3:0] line1_xaui_rxdat;
output [3:0] line1_xaui_txdat;
//gmii
input slot0_gm_tx_clk;
input slot0_gm_rx_clk;
output [7:0] slot0_gm_tx_d;
output slot0_gm_tx_en;
output slot0_gm_tx_err;
input [7:0] slot0_gm_rx_d;
input slot0_gm_rx_dv;
input slot0_gm_rx_err;
input slot1_gm_tx_clk;
input slot1_gm_rx_clk;
output [7:0] slot1_gm_tx_d;
output slot1_gm_tx_en;
output slot1_gm_tx_err;
input [7:0] slot1_gm_rx_d;
input slot1_gm_rx_dv;
input slot1_gm_rx_err;
//egress
input in_egress_pkt_wr;
input [133:0] in_egress_pkt;
output out_egress_pkt_almostfull;
input in_egress_pkt_valid_wr;
input in_egress_pkt_valid;
//ingress
output out_ingress_pkt_wr;
output [133:0] out_ingress_pkt;
input in_ingress_pkt_almostfull;
output out_ingress_valid_wr;
output out_ingress_valid;
input [7:0] slot0_port0_address;
input slot0_port0_write;
input slot0_port0_read;
input [31:0] slot0_port0_writedata;
output [31:0] slot0_port0_readdata;
output slot0_port0_waitrequest;
input [7:0] slot0_port1_address;
input slot0_port1_write;
input slot0_port1_read;
input [31:0] slot0_port1_writedata;
output [31:0] slot0_port1_readdata;
output slot0_port1_waitrequest;
input [7:0] slot0_port2_address;
input slot0_port2_write;
input slot0_port2_read;
input [31:0] slot0_port2_writedata;
output [31:0] slot0_port2_readdata;
output slot0_port2_waitrequest;
input [7:0] slot0_port3_address;
input slot0_port3_write;
input slot0_port3_read;
input [31:0] slot0_port3_writedata;
output [31:0] slot0_port3_readdata;
output slot0_port3_waitrequest;
input [7:0] slot0_port4_address;
input slot0_port4_write;
input slot0_port4_read;
input [31:0] slot0_port4_writedata;
output [31:0] slot0_port4_readdata;
output slot0_port4_waitrequest;
input [7:0] slot1_port0_address;
input slot1_port0_write;
input slot1_port0_read;
input [31:0] slot1_port0_writedata;
output [31:0] slot1_port0_readdata;
output slot1_port0_waitrequest;
input [7:0] slot1_port1_address;
input slot1_port1_write;
input slot1_port1_read;
input [31:0] slot1_port1_writedata;
output [31:0] slot1_port1_readdata;
output slot1_port1_waitrequest;
input [7:0] slot1_port2_address;
input slot1_port2_write;
input slot1_port2_read;
input [31:0] slot1_port2_writedata;
output [31:0] slot1_port2_readdata;
output slot1_port2_waitrequest;
input [7:0] slot1_port3_address;
input slot1_port3_write;
input slot1_port3_read;
input [31:0] slot1_port3_writedata;
output [31:0] slot1_port3_readdata;
output slot1_port3_waitrequest;
input [7:0] slot1_port4_address;
input slot1_port4_write;
input slot1_port4_read;
input [31:0] slot1_port4_writedata;
output [31:0] slot1_port4_readdata;
output slot1_port4_waitrequest;
//MAC
output slot0_port0_pkt_receive_add;
output slot0_port0_pkt_discard_add;
output slot0_port0_pkt_send_add;
output slot0_port1_pkt_receive_add;
output slot0_port1_pkt_discard_add;
output slot0_port1_pkt_send_add;
output slot0_port2_pkt_receive_add;
output slot0_port2_pkt_discard_add;
output slot0_port2_pkt_send_add;
output slot0_port3_pkt_receive_add;
output slot0_port3_pkt_discard_add;
output slot0_port3_pkt_send_add;
output slot0_port4_pkt_receive_add;
output slot0_port4_pkt_discard_add;
output slot0_port4_pkt_send_add;
output slot1_port0_pkt_receive_add;
output slot1_port0_pkt_discard_add;
output slot1_port0_pkt_send_add;
output slot1_port1_pkt_receive_add;
output slot1_port1_pkt_discard_add;
output slot1_port1_pkt_send_add;
output slot1_port2_pkt_receive_add;
output slot1_port2_pkt_discard_add;
output slot1_port2_pkt_send_add;
output slot1_port3_pkt_receive_add;
output slot1_port3_pkt_discard_add;
output slot1_port3_pkt_send_add;
output slot1_port4_pkt_receive_add;
output slot1_port4_pkt_discard_add;
output slot1_port4_pkt_send_add;
output mux0_receive_pkt_add;
output mux0_discard_error_pkt_add;
output mux1_receive_pkt_add;
output mux1_discard_error_pkt_add;
output dmux0_receive_pkt_add;
output dmux0_discard_error_pkt_add;
output dmux0_send_port0_pkt_add;
output dmux0_send_port1_pkt_add;
output dmux0_send_port2_pkt_add;
output dmux0_send_port3_pkt_add;
output dmux0_send_port4_pkt_add;
output dmux1_receive_pkt_add;
output dmux1_discard_error_pkt_add;
output dmux1_send_port0_pkt_add;
output dmux1_send_port1_pkt_add;
output dmux1_send_port2_pkt_add;
output dmux1_send_port3_pkt_add;
output dmux1_send_port4_pkt_add;
output inputctl_receive_pkt_add;
output output_receive_pkt_add;
output output_discard_error_pkt_add;
output output_send_slot0_pkt_add;
output output_send_slot1_pkt_add;
wire slot0_port0_out_mux_pkt_wr;
wire [133:0] slot0_port0_out_mux_pkt;
wire slot0_port0_in_mux_pkt_almostfull;
wire slot0_port0_out_mux_pkt_valid_wr;
wire slot0_port0_out_mux_pkt_valid;
wire slot0_port0_in_dmux_pkt_wr;
wire [133:0] slot0_port0_in_dmux_pkt;
wire slot0_port0_out_dmux_pkt_almostfull;
wire slot0_port0_in_dmux_pkt_valid_wr;
wire slot0_port0_in_dmux_pkt_valid;
SGMII_PORT SLOT0_SGMII_PORT0(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (card0_clk),
.reset (reset),
.out_pkt_wrreq (slot0_port0_out_mux_pkt_wr),
.out_pkt (slot0_port0_out_mux_pkt),
.out_pkt_almostfull (slot0_port0_in_mux_pkt_almostfull),
.out_valid_wrreq (slot0_port0_out_mux_pkt_valid_wr),
.out_valid (slot0_port0_out_mux_pkt_valid),
.out2_pkt_wrreq (slot0_port0_in_dmux_pkt_wr),
.out2_pkt (slot0_port0_in_dmux_pkt),
.out2_pkt_almost_full (slot0_port0_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot0_port0_in_dmux_pkt_valid_wr),
.out2_valid (slot0_port0_in_dmux_pkt_valid),
.pkt_receive_add (slot0_port0_pkt_receive_add),
.pkt_discard_add (slot0_port0_pkt_discard_add),
.pkt_send_add (slot0_port0_pkt_send_add),
.ref_clk (card0_refclk),
.txp (line0_xaui_txdat[0]),
.rxp (line0_xaui_rxdat[0]),
.address (slot0_port0_address),
.write (slot0_port0_write),
.read (slot0_port0_read),
.writedata (slot0_port0_writedata),
.readdata (slot0_port0_readdata),
.waitrequest (slot0_port0_waitrequest),
.reconfig_clk (reconfig_clk));//37.5Mhz ----50Mhz
wire slot0_port1_out_mux_pkt_wr;
wire [133:0] slot0_port1_out_mux_pkt;
wire slot0_port1_in_mux_pkt_almostfull;
wire slot0_port1_out_mux_pkt_valid_wr;
wire slot0_port1_out_mux_pkt_valid;
wire slot0_port1_in_dmux_pkt_wr;
wire [133:0] slot0_port1_in_dmux_pkt;
wire slot0_port1_out_dmux_pkt_almostfull;
wire slot0_port1_in_dmux_pkt_valid_wr;
wire slot0_port1_in_dmux_pkt_valid;
SGMII_PORT SLOT0_SGMII_PORT1(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (card0_clk),
.reset (reset),
.out_pkt_wrreq (slot0_port1_out_mux_pkt_wr),
.out_pkt (slot0_port1_out_mux_pkt),
.out_pkt_almostfull (slot0_port1_in_mux_pkt_almostfull),
.out_valid_wrreq (slot0_port1_out_mux_pkt_valid_wr),
.out_valid (slot0_port1_out_mux_pkt_valid),
.out2_pkt_wrreq (slot0_port1_in_dmux_pkt_wr),
.out2_pkt (slot0_port1_in_dmux_pkt),
.out2_pkt_almost_full (slot0_port1_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot0_port1_in_dmux_pkt_valid_wr),
.out2_valid (slot0_port1_in_dmux_pkt_valid),
.pkt_receive_add (slot0_port1_pkt_receive_add),
.pkt_discard_add (slot0_port1_pkt_discard_add),
.pkt_send_add (slot0_port1_pkt_send_add),
.ref_clk (card0_refclk),
.txp (line0_xaui_txdat[1]),
.rxp (line0_xaui_rxdat[1]),
.address (slot0_port1_address),
.write (slot0_port1_write),
.read (slot0_port1_read),
.writedata (slot0_port1_writedata),
.readdata (slot0_port1_readdata),
.waitrequest (slot0_port1_waitrequest),
.reconfig_clk (reconfig_clk));//37.5Mhz ----50Mhz
wire slot0_port2_out_mux_pkt_wr;
wire [133:0] slot0_port2_out_mux_pkt;
wire slot0_port2_in_mux_pkt_almostfull;
wire slot0_port2_out_mux_pkt_valid_wr;
wire slot0_port2_out_mux_pkt_valid;
wire slot0_port2_in_dmux_pkt_wr;
wire [133:0] slot0_port2_in_dmux_pkt;
wire slot0_port2_out_dmux_pkt_almostfull;
wire slot0_port2_in_dmux_pkt_valid_wr;
wire slot0_port2_in_dmux_pkt_valid;
SGMII_PORT SLOT0_SGMII_PORT2(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (card0_clk),
.reset (reset),
.out_pkt_wrreq (slot0_port2_out_mux_pkt_wr),
.out_pkt (slot0_port2_out_mux_pkt),
.out_pkt_almostfull (slot0_port2_in_mux_pkt_almostfull),
.out_valid_wrreq (slot0_port2_out_mux_pkt_valid_wr),
.out_valid (slot0_port2_out_mux_pkt_valid),
.out2_pkt_wrreq (slot0_port2_in_dmux_pkt_wr),
.out2_pkt (slot0_port2_in_dmux_pkt),
.out2_pkt_almost_full (slot0_port2_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot0_port2_in_dmux_pkt_valid_wr),
.out2_valid (slot0_port2_in_dmux_pkt_valid),
.pkt_receive_add (slot0_port2_pkt_receive_add),
.pkt_discard_add (slot0_port2_pkt_discard_add),
.pkt_send_add (slot0_port2_pkt_send_add),
.ref_clk (card0_refclk),
.txp (line0_xaui_txdat[2]),
.rxp (line0_xaui_rxdat[2]),
.address (slot0_port2_address),
.write (slot0_port2_write),
.read (slot0_port2_read),
.writedata (slot0_port2_writedata),
.readdata (slot0_port2_readdata),
.waitrequest (slot0_port2_waitrequest),
.reconfig_clk (reconfig_clk));//37.5Mhz ----50Mhz
wire slot0_port3_out_mux_pkt_wr;
wire [133:0] slot0_port3_out_mux_pkt;
wire slot0_port3_in_mux_pkt_almostfull;
wire slot0_port3_out_mux_pkt_valid_wr;
wire slot0_port3_out_mux_pkt_valid;
wire slot0_port3_in_dmux_pkt_wr;
wire [133:0] slot0_port3_in_dmux_pkt;
wire slot0_port3_out_dmux_pkt_almostfull;
wire slot0_port3_in_dmux_pkt_valid_wr;
wire slot0_port3_in_dmux_pkt_valid;
SGMII_PORT SLOT0_SGMII_PORT3(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (card0_clk),
.reset (reset),
.out_pkt_wrreq (slot0_port3_out_mux_pkt_wr),
.out_pkt (slot0_port3_out_mux_pkt),
.out_pkt_almostfull (slot0_port3_in_mux_pkt_almostfull),
.out_valid_wrreq (slot0_port3_out_mux_pkt_valid_wr),
.out_valid (slot0_port3_out_mux_pkt_valid),
.out2_pkt_wrreq (slot0_port3_in_dmux_pkt_wr),
.out2_pkt (slot0_port3_in_dmux_pkt),
.out2_pkt_almost_full (slot0_port3_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot0_port3_in_dmux_pkt_valid_wr),
.out2_valid (slot0_port3_in_dmux_pkt_valid),
.pkt_receive_add (slot0_port3_pkt_receive_add),
.pkt_discard_add (slot0_port3_pkt_discard_add),
.pkt_send_add (slot0_port3_pkt_send_add),
.ref_clk (card0_refclk),
.txp (line0_xaui_txdat[3]),
.rxp (line0_xaui_rxdat[3]),
.address (slot0_port3_address),
.write (slot0_port3_write),
.read (slot0_port3_read),
.writedata (slot0_port3_writedata),
.readdata (slot0_port3_readdata),
.waitrequest (slot0_port3_waitrequest),
.reconfig_clk (reconfig_clk));//37.5Mhz ----50Mhz
wire slot1_port0_out_mux_pkt_wr;
wire [133:0] slot1_port0_out_mux_pkt;
wire slot1_port0_in_mux_pkt_almostfull;
wire slot1_port0_out_mux_pkt_valid_wr;
wire slot1_port0_out_mux_pkt_valid;
wire slot1_port0_in_dmux_pkt_wr;
wire [133:0] slot1_port0_in_dmux_pkt;
wire slot1_port0_out_dmux_pkt_almostfull;
wire slot1_port0_in_dmux_pkt_valid_wr;
wire slot1_port0_in_dmux_pkt_valid;
SGMII_PORT SLOT1_SGMII_PORT0(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (card1_clk),
.reset (reset),
.out_pkt_wrreq (slot1_port0_out_mux_pkt_wr),
.out_pkt (slot1_port0_out_mux_pkt),
.out_pkt_almostfull (slot1_port0_in_mux_pkt_almostfull),
.out_valid_wrreq (slot1_port0_out_mux_pkt_valid_wr),
.out_valid (slot1_port0_out_mux_pkt_valid),
.out2_pkt_wrreq (slot1_port0_in_dmux_pkt_wr),
.out2_pkt (slot1_port0_in_dmux_pkt),
.out2_pkt_almost_full (slot1_port0_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot1_port0_in_dmux_pkt_valid_wr),
.out2_valid (slot1_port0_in_dmux_pkt_valid),
.pkt_receive_add (slot1_port0_pkt_receive_add),
.pkt_discard_add (slot1_port0_pkt_discard_add),
.pkt_send_add (slot1_port0_pkt_send_add),
.ref_clk (card1_refclk),
.txp (line1_xaui_txdat[0]),
.rxp (line1_xaui_rxdat[0]),
.address (slot1_port0_address),
.write (slot1_port0_write),
.read (slot1_port0_read),
.writedata (slot1_port0_writedata),
.readdata (slot1_port0_readdata),
.waitrequest (slot1_port0_waitrequest),
.reconfig_clk (reconfig_clk));//37.5Mhz ----50Mhz
wire slot1_port1_out_mux_pkt_wr;
wire [133:0] slot1_port1_out_mux_pkt;
wire slot1_port1_in_mux_pkt_almostfull;
wire slot1_port1_out_mux_pkt_valid_wr;
wire slot1_port1_out_mux_pkt_valid;
wire slot1_port1_in_dmux_pkt_wr;
wire [133:0] slot1_port1_in_dmux_pkt;
wire slot1_port1_out_dmux_pkt_almostfull;
wire slot1_port1_in_dmux_pkt_valid_wr;
wire slot1_port1_in_dmux_pkt_valid;
SGMII_PORT SLOT1_SGMII_PORT1(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (card1_clk),
.reset (reset),
.out_pkt_wrreq (slot1_port1_out_mux_pkt_wr),
.out_pkt (slot1_port1_out_mux_pkt),
.out_pkt_almostfull (slot1_port1_in_mux_pkt_almostfull),
.out_valid_wrreq (slot1_port1_out_mux_pkt_valid_wr),
.out_valid (slot1_port1_out_mux_pkt_valid),
.out2_pkt_wrreq (slot1_port1_in_dmux_pkt_wr),
.out2_pkt (slot1_port1_in_dmux_pkt),
.out2_pkt_almost_full (slot1_port1_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot1_port1_in_dmux_pkt_valid_wr),
.out2_valid (slot1_port1_in_dmux_pkt_valid),
.pkt_receive_add (slot1_port1_pkt_receive_add),
.pkt_discard_add (slot1_port1_pkt_discard_add),
.pkt_send_add (slot1_port1_pkt_send_add),
.ref_clk (card1_refclk),
.txp (line1_xaui_txdat[1]),
.rxp (line1_xaui_rxdat[1]),
.address (slot1_port1_address),
.write (slot1_port1_write),
.read (slot1_port1_read),
.writedata (slot1_port1_writedata),
.readdata (slot1_port1_readdata),
.waitrequest (slot1_port1_waitrequest),
.reconfig_clk (reconfig_clk));//37.5Mhz ----50Mhz
wire slot1_port2_out_mux_pkt_wr;
wire [133:0] slot1_port2_out_mux_pkt;
wire slot1_port2_in_mux_pkt_almostfull;
wire slot1_port2_out_mux_pkt_valid_wr;
wire slot1_port2_out_mux_pkt_valid;
wire slot1_port2_in_dmux_pkt_wr;
wire [133:0] slot1_port2_in_dmux_pkt;
wire slot1_port2_out_dmux_pkt_almostfull;
wire slot1_port2_in_dmux_pkt_valid_wr;
wire slot1_port2_in_dmux_pkt_valid;
SGMII_PORT SLOT1_SGMII_PORT2(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (card1_clk),
.reset (reset),
.out_pkt_wrreq (slot1_port2_out_mux_pkt_wr),
.out_pkt (slot1_port2_out_mux_pkt),
.out_pkt_almostfull (slot1_port2_in_mux_pkt_almostfull),
.out_valid_wrreq (slot1_port2_out_mux_pkt_valid_wr),
.out_valid (slot1_port2_out_mux_pkt_valid),
.out2_pkt_wrreq (slot1_port2_in_dmux_pkt_wr),
.out2_pkt (slot1_port2_in_dmux_pkt),
.out2_pkt_almost_full (slot1_port2_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot1_port2_in_dmux_pkt_valid_wr),
.out2_valid (slot1_port2_in_dmux_pkt_valid),
.pkt_receive_add (slot1_port2_pkt_receive_add),
.pkt_discard_add (slot1_port2_pkt_discard_add),
.pkt_send_add (slot1_port2_pkt_send_add),
.ref_clk (card1_refclk),
.txp (line1_xaui_txdat[2]),
.rxp (line1_xaui_rxdat[2]),
.address (slot1_port2_address),
.write (slot1_port2_write),
.read (slot1_port2_read),
.writedata (slot1_port2_writedata),
.readdata (slot1_port2_readdata),
.waitrequest (slot1_port2_waitrequest),
.reconfig_clk (reconfig_clk));
wire slot1_port3_out_mux_pkt_wr;
wire [133:0] slot1_port3_out_mux_pkt;
wire slot1_port3_in_mux_pkt_almostfull;
wire slot1_port3_out_mux_pkt_valid_wr;
wire slot1_port3_out_mux_pkt_valid;
wire slot1_port3_in_dmux_pkt_wr;
wire [133:0] slot1_port3_in_dmux_pkt;
wire slot1_port3_out_dmux_pkt_almostfull;
wire slot1_port3_in_dmux_pkt_valid_wr;
wire slot1_port3_in_dmux_pkt_valid;
SGMII_PORT SLOT1_SGMII_PORT3(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (card1_clk),
.reset (reset),
.out_pkt_wrreq (slot1_port3_out_mux_pkt_wr),
.out_pkt (slot1_port3_out_mux_pkt),
.out_pkt_almostfull (slot1_port3_in_mux_pkt_almostfull),
.out_valid_wrreq (slot1_port3_out_mux_pkt_valid_wr),
.out_valid (slot1_port3_out_mux_pkt_valid),
.out2_pkt_wrreq (slot1_port3_in_dmux_pkt_wr),
.out2_pkt (slot1_port3_in_dmux_pkt),
.out2_pkt_almost_full (slot1_port3_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot1_port3_in_dmux_pkt_valid_wr),
.out2_valid (slot1_port3_in_dmux_pkt_valid),
.pkt_receive_add (slot1_port3_pkt_receive_add),
.pkt_discard_add (slot1_port3_pkt_discard_add),
.pkt_send_add (slot1_port3_pkt_send_add),
.ref_clk (card1_refclk),
.txp (line1_xaui_txdat[3]),
.rxp (line1_xaui_rxdat[3]),
.address (slot1_port3_address),
.write (slot1_port3_write),
.read (slot1_port3_read),
.writedata (slot1_port3_writedata),
.readdata (slot1_port3_readdata),
.waitrequest (slot1_port3_waitrequest),
.reconfig_clk (reconfig_clk));//37.5Mhz ----50Mhz
wire slot0_port4_out_mux_pkt_wr;
wire [133:0] slot0_port4_out_mux_pkt;
wire slot0_port4_in_mux_pkt_almostfull;
wire slot0_port4_out_mux_pkt_valid_wr;
wire slot0_port4_out_mux_pkt_valid;
wire slot0_port4_in_dmux_pkt_wr;
wire [133:0] slot0_port4_in_dmux_pkt;
wire slot0_port4_out_dmux_pkt_almostfull;
wire slot0_port4_in_dmux_pkt_valid_wr;
wire slot0_port4_in_dmux_pkt_valid;
UE1_PORT UE1_SLOT0_PORT(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (ue1_clk),
.reset (reset),
.out_pkt_wrreq (slot0_port4_out_mux_pkt_wr),
.out_pkt (slot0_port4_out_mux_pkt),
.out_pkt_almostfull (slot0_port4_in_mux_pkt_almostfull),
.out_valid_wrreq (slot0_port4_out_mux_pkt_valid_wr),
.out_valid (slot0_port4_out_mux_pkt_valid),
.out2_pkt_wrreq (slot0_port4_in_dmux_pkt_wr),
.out2_pkt (slot0_port4_in_dmux_pkt),
.out2_pkt_almost_full (slot0_port4_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot0_port4_in_dmux_pkt_valid_wr),
.out2_valid (slot0_port4_in_dmux_pkt_valid),
.pkt_receive_add (slot0_port4_pkt_receive_add),
.pkt_discard_add (slot0_port4_pkt_discard_add),
.pkt_send_add (slot0_port4_pkt_send_add),
//gmii
.tx_clk (slot0_gm_tx_clk),
.rx_clk (slot0_gm_rx_clk),
.gm_tx_d (slot0_gm_tx_d),
.gm_tx_en (slot0_gm_tx_en),
.gm_tx_err (slot0_gm_tx_err),
.gm_rx_d (slot0_gm_rx_d),
.gm_rx_dv (slot0_gm_rx_dv),
.gm_rx_err (slot0_gm_rx_err),
.address (slot0_port4_address),
.write (slot0_port4_write),
.read (slot0_port4_read),
.writedata (slot0_port4_writedata),
.readdata (slot0_port4_readdata),
.waitrequest (slot0_port4_waitrequest));
UE1_PORT UE1_SLOT1_PORT(
.clk (clk),
.ammc_clk (ammc_clk),
.sgmii_clk (ue1_clk),
.reset (reset),
.out_pkt_wrreq (slot1_port4_out_mux_pkt_wr),
.out_pkt (slot1_port4_out_mux_pkt),
.out_pkt_almostfull (slot1_port4_in_mux_pkt_almostfull),
.out_valid_wrreq (slot1_port4_out_mux_pkt_valid_wr),
.out_valid (slot1_port4_out_mux_pkt_valid),
.out2_pkt_wrreq (slot1_port4_in_dmux_pkt_wr),
.out2_pkt (slot1_port4_in_dmux_pkt),
.out2_pkt_almost_full (slot1_port4_out_dmux_pkt_almostfull),
.out2_valid_wrreq (slot1_port4_in_dmux_pkt_valid_wr),
.out2_valid (slot1_port4_in_dmux_pkt_valid),
.pkt_receive_add (slot1_port4_pkt_receive_add),
.pkt_discard_add (slot1_port4_pkt_discard_add),
.pkt_send_add (slot1_port4_pkt_send_add),
//gmii
.tx_clk (slot1_gm_tx_clk),
.rx_clk (slot1_gm_rx_clk),
.gm_tx_d (slot1_gm_tx_d),
.gm_tx_en (slot1_gm_tx_en),
.gm_tx_err (slot1_gm_tx_err),
.gm_rx_d (slot1_gm_rx_d),
.gm_rx_dv (slot1_gm_rx_dv),
.gm_rx_err (slot1_gm_rx_err),
.address (slot1_port4_address),
.write (slot1_port4_write),
.read (slot1_port4_read),
.writedata (slot1_port4_writedata),
.readdata (slot1_port4_readdata),
.waitrequest (slot1_port4_waitrequest));
SGMII_DMUX Slot0_DMUX(
.clk (clk),
.reset (reset),
//xaul0
.out_xaui0_pkt_wr (slot0_port0_in_dmux_pkt_wr),
.out_xaui0_pkt (slot0_port0_in_dmux_pkt),
.in_xaui0_pkt_almostfull (slot0_port0_out_dmux_pkt_almostfull),
.out_xaui0_pkt_valid_wr (slot0_port0_in_dmux_pkt_valid_wr),
.out_xaui0_pkt_valid (slot0_port0_in_dmux_pkt_valid),
//xaui1
.out_xaui1_pkt_wr (slot0_port1_in_dmux_pkt_wr),
.out_xaui1_pkt (slot0_port1_in_dmux_pkt),
.in_xaui1_pkt_almostfull (slot0_port1_out_dmux_pkt_almostfull),
.out_xaui1_pkt_valid_wr (slot0_port1_in_dmux_pkt_valid_wr),
.out_xaui1_pkt_valid (slot0_port1_in_dmux_pkt_valid),
//xaui2
.out_xaui2_pkt_wr (slot0_port2_in_dmux_pkt_wr),
.out_xaui2_pkt (slot0_port2_in_dmux_pkt),
.in_xaui2_pkt_almostfull (slot0_port2_out_dmux_pkt_almostfull),
.out_xaui2_pkt_valid_wr (slot0_port2_in_dmux_pkt_valid_wr),
.out_xaui2_pkt_valid (slot0_port2_in_dmux_pkt_valid),
//xaui3
.out_xaui3_pkt_wr (slot0_port3_in_dmux_pkt_wr),
.out_xaui3_pkt (slot0_port3_in_dmux_pkt),
.in_xaui3_pkt_almostfull (slot0_port3_out_dmux_pkt_almostfull),
.out_xaui3_pkt_valid_wr (slot0_port3_in_dmux_pkt_valid_wr),
.out_xaui3_pkt_valid (slot0_port3_in_dmux_pkt_valid),
//xaul4
.out_xaui4_pkt_wr (slot0_port4_in_dmux_pkt_wr),
.out_xaui4_pkt (slot0_port4_in_dmux_pkt),
.in_xaui4_pkt_almostfull (slot0_port4_out_dmux_pkt_almostfull),
.out_xaui4_pkt_valid_wr (slot0_port4_in_dmux_pkt_valid_wr),
.out_xaui4_pkt_valid (slot0_port4_in_dmux_pkt_valid),
//to NA
.in_egress_pkt_wr (out_slot0_pkt_wr),
.in_egress_pkt (out_slot0_pkt),
.out_egress_pkt_almostfull (in_slot0_pkt_almostfull),
.in_egress_pkt_valid_wr (out_slot0_pkt_valid_wr),
.in_egress_pkt_valid (out_slot0_pkt_valid),
.dmux_receive_pkt_add (dmux0_receive_pkt_add),
.dmux_discard_error_pkt_add (dmux0_discard_error_pkt_add),
.dmux_send_port0_pkt_add (dmux0_send_port0_pkt_add),
.dmux_send_port1_pkt_add (dmux0_send_port1_pkt_add),
.dmux_send_port2_pkt_add (dmux0_send_port2_pkt_add),
.dmux_send_port3_pkt_add (dmux0_send_port3_pkt_add),
.dmux_send_port4_pkt_add (dmux0_send_port4_pkt_add));
wire slot1_port4_in_dmux_pkt_wr;
wire [133:0] slot1_port4_in_dmux_pkt;
wire slot1_port4_out_dmux_pkt_almostfull;
wire slot1_port4_in_dmux_pkt_valid_wr;
wire slot1_port4_in_dmux_pkt_valid;
SGMII_DMUX Slot1_DMUX(
.clk (clk),
.reset (reset),
//xaul0
.out_xaui0_pkt_wr (slot1_port0_in_dmux_pkt_wr),
.out_xaui0_pkt (slot1_port0_in_dmux_pkt),
.in_xaui0_pkt_almostfull (slot1_port0_out_dmux_pkt_almostfull),
.out_xaui0_pkt_valid_wr (slot1_port0_in_dmux_pkt_valid_wr),
.out_xaui0_pkt_valid (slot1_port0_in_dmux_pkt_valid),
//xaui1
.out_xaui1_pkt_wr (slot1_port1_in_dmux_pkt_wr),
.out_xaui1_pkt (slot1_port1_in_dmux_pkt),
.in_xaui1_pkt_almostfull (slot1_port1_out_dmux_pkt_almostfull),
.out_xaui1_pkt_valid_wr (slot1_port1_in_dmux_pkt_valid_wr),
.out_xaui1_pkt_valid (slot1_port1_in_dmux_pkt_valid),
//xaui2
.out_xaui2_pkt_wr (slot1_port2_in_dmux_pkt_wr),
.out_xaui2_pkt (slot1_port2_in_dmux_pkt),
.in_xaui2_pkt_almostfull (slot1_port2_out_dmux_pkt_almostfull),
.out_xaui2_pkt_valid_wr (slot1_port2_in_dmux_pkt_valid_wr),
.out_xaui2_pkt_valid (slot1_port2_in_dmux_pkt_valid),
//xaui3
.out_xaui3_pkt_wr (slot1_port3_in_dmux_pkt_wr),
.out_xaui3_pkt (slot1_port3_in_dmux_pkt),
.in_xaui3_pkt_almostfull (slot1_port3_out_dmux_pkt_almostfull),
.out_xaui3_pkt_valid_wr (slot1_port3_in_dmux_pkt_valid_wr),
.out_xaui3_pkt_valid (slot1_port3_in_dmux_pkt_valid),
//xaul4
.out_xaui4_pkt_wr (slot1_port4_in_dmux_pkt_wr),
.out_xaui4_pkt (slot1_port4_in_dmux_pkt),
.in_xaui4_pkt_almostfull (slot1_port4_out_dmux_pkt_almostfull),
.out_xaui4_pkt_valid_wr (slot1_port4_in_dmux_pkt_valid_wr),
.out_xaui4_pkt_valid (slot1_port4_in_dmux_pkt_valid),
//to NA
.in_egress_pkt_wr (out_slot1_pkt_wr),
.in_egress_pkt (out_slot1_pkt),
.out_egress_pkt_almostfull (in_slot1_pkt_almostfull),
.in_egress_pkt_valid_wr (out_slot1_pkt_valid_wr),
.in_egress_pkt_valid (out_slot1_pkt_valid),
.dmux_receive_pkt_add (dmux1_receive_pkt_add),
.dmux_discard_error_pkt_add (dmux1_discard_error_pkt_add),
.dmux_send_port0_pkt_add (dmux1_send_port0_pkt_add),
.dmux_send_port1_pkt_add (dmux1_send_port1_pkt_add),
.dmux_send_port2_pkt_add (dmux1_send_port2_pkt_add),
.dmux_send_port3_pkt_add (dmux1_send_port3_pkt_add),
.dmux_send_port4_pkt_add (dmux1_send_port4_pkt_add));
wire slot0_out_input_pkt_wr;
wire [133:0] slot0_out_input_pkt;
wire slot0_in_input_pkt_almostfull;
wire slot0_out_input_pkt_valid_wr;
wire [11:0] slot0_out_input_pkt_valid;
SGMII_MUX slot0(
.clk (clk),
.wrclk0 (card0_clk),
.wrclk1 (card0_clk),
.wrclk2 (card0_clk),
.wrclk3 (card0_clk),
.wrclk4 (ue1_clk),
.reset (reset),
//xaul0
.in_xaui0_pkt_wrreq (slot0_port0_out_mux_pkt_wr),
.in_xaui0_pkt (slot0_port0_out_mux_pkt),
.out_xaui0_pkt_almostfull (slot0_port0_in_mux_pkt_almostfull),
.in_xaui0_pkt_valid_wrreq (slot0_port0_out_mux_pkt_valid_wr),
.in_xaui0_pkt_valid (slot0_port0_out_mux_pkt_valid),
//xaui1
.in_xaui1_pkt_wrreq (slot0_port1_out_mux_pkt_wr),
.in_xaui1_pkt (slot0_port1_out_mux_pkt),
.out_xaui1_pkt_almostfull (slot0_port1_in_mux_pkt_almostfull),
.in_xaui1_pkt_valid_wrreq (slot0_port1_out_mux_pkt_valid_wr),
.in_xaui1_pkt_valid (slot0_port1_out_mux_pkt_valid),
//xaul2
.in_xaui2_pkt_wrreq (slot0_port2_out_mux_pkt_wr),
.in_xaui2_pkt (slot0_port2_out_mux_pkt),
.out_xaui2_pkt_almostfull (slot0_port2_in_mux_pkt_almostfull),
.in_xaui2_pkt_valid_wrreq (slot0_port2_out_mux_pkt_valid_wr),
.in_xaui2_pkt_valid (slot0_port2_out_mux_pkt_valid),
//xaui3
.in_xaui3_pkt_wrreq (slot0_port3_out_mux_pkt_wr),
.in_xaui3_pkt (slot0_port3_out_mux_pkt),
.out_xaui3_pkt_almostfull (slot0_port3_in_mux_pkt_almostfull),
.in_xaui3_pkt_valid_wrreq (slot0_port3_out_mux_pkt_valid_wr),
.in_xaui3_pkt_valid (slot0_port3_out_mux_pkt_valid),
//xaui4
.in_xaui4_pkt_wrreq (slot0_port4_out_mux_pkt_wr),
.in_xaui4_pkt (slot0_port4_out_mux_pkt),
.out_xaui4_pkt_almostfull (slot0_port4_in_mux_pkt_almostfull),
.in_xaui4_pkt_valid_wrreq (slot0_port4_out_mux_pkt_valid_wr),
.in_xaui4_pkt_valid (slot0_port4_out_mux_pkt_valid),
//to NA
.out_xaui_pkt_wrreq (slot0_out_input_pkt_wr),
.out_xaui_pkt (slot0_out_input_pkt),
.in_xaui_pkt_almostfull (slot0_in_input_pkt_almostfull),
.out_xaui_pkt_valid_wrreq (slot0_out_input_pkt_valid_wr),
.out_xaui_pkt_valid (slot0_out_input_pkt_valid),
.pkt_inport0 (5'd0),
.pkt_inport1 (5'd1),
.pkt_inport2 (5'd2),
.pkt_inport3 (5'd3),
.pkt_inport4 (5'd4),
.slot_ID (3'b000),
.card_ID (),
.receive_pkt_add (mux0_receive_pkt_add),
.discard_error_pkt_add (mux0_discard_error_pkt_add));
wire slot1_port4_out_mux_pkt_wr;
wire [133:0] slot1_port4_out_mux_pkt;
wire slot1_port4_in_mux_pkt_almostfull;
wire slot1_port4_out_mux_pkt_valid_wr;
wire slot1_port4_out_mux_pkt_valid;
wire slot1_out_input_pkt_wr;
wire [133:0] slot1_out_input_pkt;
wire slot1_in_input_pkt_almostfull;
wire slot1_out_input_pkt_valid_wr;
wire [11:0] slot1_out_input_pkt_valid;
SGMII_MUX slot1(
.clk (clk),
.wrclk0 (card1_clk),
.wrclk1 (card1_clk),
.wrclk2 (card1_clk),
.wrclk3 (card1_clk),
.wrclk4 (ue1_clk),
.reset (reset),
//xaul0
.in_xaui0_pkt_wrreq (slot1_port0_out_mux_pkt_wr),
.in_xaui0_pkt (slot1_port0_out_mux_pkt),
.out_xaui0_pkt_almostfull (slot1_port0_in_mux_pkt_almostfull),
.in_xaui0_pkt_valid_wrreq (slot1_port0_out_mux_pkt_valid_wr),
.in_xaui0_pkt_valid (slot1_port0_out_mux_pkt_valid),
//xaui1
.in_xaui1_pkt_wrreq (slot1_port1_out_mux_pkt_wr),
.in_xaui1_pkt (slot1_port1_out_mux_pkt),
.out_xaui1_pkt_almostfull (slot1_port1_in_mux_pkt_almostfull),
.in_xaui1_pkt_valid_wrreq (slot1_port1_out_mux_pkt_valid_wr),
.in_xaui1_pkt_valid (slot1_port1_out_mux_pkt_valid),
//xaul2
.in_xaui2_pkt_wrreq (slot1_port2_out_mux_pkt_wr),
.in_xaui2_pkt (slot1_port2_out_mux_pkt),
.out_xaui2_pkt_almostfull (slot1_port2_in_mux_pkt_almostfull),
.in_xaui2_pkt_valid_wrreq (slot1_port2_out_mux_pkt_valid_wr),
.in_xaui2_pkt_valid (slot1_port2_out_mux_pkt_valid),
//xaui3
.in_xaui3_pkt_wrreq (slot1_port3_out_mux_pkt_wr),
.in_xaui3_pkt (slot1_port3_out_mux_pkt),
.out_xaui3_pkt_almostfull (slot1_port3_in_mux_pkt_almostfull),
.in_xaui3_pkt_valid_wrreq (slot1_port3_out_mux_pkt_valid_wr),
.in_xaui3_pkt_valid (slot1_port3_out_mux_pkt_valid),
//xaui4
.in_xaui4_pkt_wrreq (slot1_port4_out_mux_pkt_wr),
.in_xaui4_pkt (slot1_port4_out_mux_pkt),
.out_xaui4_pkt_almostfull (slot1_port4_in_mux_pkt_almostfull),
.in_xaui4_pkt_valid_wrreq (slot1_port4_out_mux_pkt_valid_wr),
.in_xaui4_pkt_valid (slot1_port4_out_mux_pkt_valid),
//to NA
.out_xaui_pkt_wrreq (slot1_out_input_pkt_wr),
.out_xaui_pkt (slot1_out_input_pkt),
.in_xaui_pkt_almostfull (slot1_in_input_pkt_almostfull),
.out_xaui_pkt_valid_wrreq (slot1_out_input_pkt_valid_wr),
.out_xaui_pkt_valid (slot1_out_input_pkt_valid),
.pkt_inport0 (5'd0),
.pkt_inport1 (5'd1),
.pkt_inport2 (5'd2),
.pkt_inport3 (5'd3),
.pkt_inport4 (5'd4),
.slot_ID (3'b001),
.card_ID (),
.receive_pkt_add (mux1_receive_pkt_add),
.discard_error_pkt_add (mux1_discard_error_pkt_add));
INPUT_CTL INPUT_CTL(
.clk (clk),
.reset (reset),
//xaul0
.in_xaui0_pkt_wr (slot0_out_input_pkt_wr),
.in_xaui0_pkt (slot0_out_input_pkt),
.out_xaui0_pkt_almostfull (slot0_in_input_pkt_almostfull),
.in_xaui0_pkt_valid_wr (slot0_out_input_pkt_valid_wr),
.in_xaui0_pkt_valid (slot0_out_input_pkt_valid),
//xaui1
.in_xaui1_pkt_wr (slot1_out_input_pkt_wr),
.in_xaui1_pkt (slot1_out_input_pkt),
.out_xaui1_pkt_almostfull (slot1_in_input_pkt_almostfull),
.in_xaui1_pkt_valid_wr (slot1_out_input_pkt_valid_wr),
.in_xaui1_pkt_valid (slot1_out_input_pkt_valid),
//to NA
.out_xaui_pkt_wr (out_ingress_pkt_wr),
.out_xaui_pkt (out_ingress_pkt),
.in_xaui_pkt_almostfull (in_ingress_pkt_almostfull),
.out_xaui_valid_wr (out_ingress_valid_wr),
.out_xaui_valid (out_ingress_valid),
.inputctl_receive_pkt_add (inputctl_receive_pkt_add));
wire out_slot0_pkt_wr;
wire [133:0] out_slot0_pkt;
wire out_slot0_pkt_valid;
wire out_slot0_pkt_valid_wr;
wire in_slot0_pkt_almostfull;
wire out_slot1_pkt_wr;
wire [133:0] out_slot1_pkt;
wire out_slot1_pkt_valid;
wire out_slot1_pkt_valid_wr;
wire in_slot1_pkt_almostfull;
OUTPUT_CTL OUTPUT_CTL(
.clk (clk),
.reset (reset),
.in_egress_pkt_wr (in_egress_pkt_wr),
.in_egress_pkt (in_egress_pkt),
.in_egress_pkt_valid_wr (in_egress_pkt_valid_wr),
.in_egress_pkt_valid (in_egress_pkt_valid),
.out_egress_pkt_almostfull (out_egress_pkt_almostfull),
.out_slot0_pkt (out_slot0_pkt),
.out_slot0_pkt_wr (out_slot0_pkt_wr),
.out_slot0_pkt_valid (out_slot0_pkt_valid),
.out_slot0_pkt_valid_wr (out_slot0_pkt_valid_wr),
.in_slot0_pkt_almostfull (in_slot0_pkt_almostfull),
.out_slot1_pkt (out_slot1_pkt),
.out_slot1_pkt_wr (out_slot1_pkt_wr),
.out_slot1_pkt_valid (out_slot1_pkt_valid),
.out_slot1_pkt_valid_wr (out_slot1_pkt_valid_wr),
.in_slot1_pkt_almostfull (in_slot1_pkt_almostfull),
.output_receive_pkt_add (output_receive_pkt_add),
.output_discard_error_pkt_add (output_discard_error_pkt_add),
.output_send_slot0_pkt_add (output_send_slot0_pkt_add),
.output_send_slot1_pkt_add (output_send_slot1_pkt_add));
endmodule |
module NCenterMaze(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0] CurrentX;
input [8:0] CurrentY;
input [7:0] wall;
output [7:0] mapData;
reg [7:0] mColor;
//Screen is divided into 20 intervals of 32 pixels each in the x direction
always @(posedge clk_vga) begin
//From x == 0 to 63, inclusive
if((CurrentX >= 0 && CurrentX <=63) && (
(CurrentY <= 39) ||
(CurrentY >= 120 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 64 to 95, inclusive
else if( (CurrentX >= 64 && CurrentX <= 95) && (
(CurrentY <= 39) ||
(CurrentY >= 280 && CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 96 to 127, inclusive
else if( (CurrentX >= 96 && CurrentX <= 127) && (
(CurrentY <= 39) ||
(CurrentY >= 280) ) )
mColor[7:0] <= wall;
//From x == 128 to 159, inclusive
else if( (CurrentX >= 128 && CurrentX <= 159) && (
(CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 160 to 224, inclusive
else if( (CurrentX >= 160 && CurrentX <= 224) && (
(CurrentY <= 39) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 224 to 255, inclusive
else if( (CurrentX >= 224 && CurrentX <= 255) && (
(CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From X == 256 to 287, inclusive
else if( (CurrentX >= 256 && CurrentX <= 287) && (
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 280) ) )
mColor[7:0] <= wall;
//From x == 352 to 383, inclusive
else if( (CurrentX >= 352 && CurrentX <= 383) && (
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 280) ) )
mColor[7:0] <= wall;
//From x == 384 to 415, inclusive
else if( (CurrentX >= 384 && CurrentX <= 415) && (
(CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 416 to 479, inclusive
else if( (CurrentX >= 416 && CurrentX <= 479) && (
(CurrentY <= 39) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 480 to 511, inclusive
else if( (CurrentX >= 480 && CurrentX <= 511) && (
(CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 512 to 543, inclusive
else if( (CurrentX >= 512 && CurrentX <= 543) && (
(CurrentY <= 39) ||
(CurrentY >= 280) ) )
mColor[7:0] <= wall;
//From x == 544 to 575, inclusive
else if( (CurrentX >= 544 && CurrentX <= 575) && (
(CurrentY <= 39) ||
(CurrentY >= 280 && CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 576 to 640, inclusive
else if((CurrentX >= 576 && CurrentX <= 640) && (
(CurrentY <= 39) ||
(CurrentY >= 120 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//floor area - grey
else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
//======================================================================
//
// sha512_k_constants.v
// --------------------
// The table K with constants in the SHA-512 hash function.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha512_k_constants(
input wire [6 : 0] addr,
output wire [63 : 0] K
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] tmp_K;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign K = tmp_K;
//----------------------------------------------------------------
// addr_mux
//----------------------------------------------------------------
always @*
begin : addr_mux
case(addr)
0: tmp_K = 64'h428a2f98d728ae22;
1: tmp_K = 64'h7137449123ef65cd;
2: tmp_K = 64'hb5c0fbcfec4d3b2f;
3: tmp_K = 64'he9b5dba58189dbbc;
4: tmp_K = 64'h3956c25bf348b538;
5: tmp_K = 64'h59f111f1b605d019;
6: tmp_K = 64'h923f82a4af194f9b;
7: tmp_K = 64'hab1c5ed5da6d8118;
8: tmp_K = 64'hd807aa98a3030242;
9: tmp_K = 64'h12835b0145706fbe;
10: tmp_K = 64'h243185be4ee4b28c;
11: tmp_K = 64'h550c7dc3d5ffb4e2;
12: tmp_K = 64'h72be5d74f27b896f;
13: tmp_K = 64'h80deb1fe3b1696b1;
14: tmp_K = 64'h9bdc06a725c71235;
15: tmp_K = 64'hc19bf174cf692694;
16: tmp_K = 64'he49b69c19ef14ad2;
17: tmp_K = 64'hefbe4786384f25e3;
18: tmp_K = 64'h0fc19dc68b8cd5b5;
19: tmp_K = 64'h240ca1cc77ac9c65;
20: tmp_K = 64'h2de92c6f592b0275;
21: tmp_K = 64'h4a7484aa6ea6e483;
22: tmp_K = 64'h5cb0a9dcbd41fbd4;
23: tmp_K = 64'h76f988da831153b5;
24: tmp_K = 64'h983e5152ee66dfab;
25: tmp_K = 64'ha831c66d2db43210;
26: tmp_K = 64'hb00327c898fb213f;
27: tmp_K = 64'hbf597fc7beef0ee4;
28: tmp_K = 64'hc6e00bf33da88fc2;
29: tmp_K = 64'hd5a79147930aa725;
30: tmp_K = 64'h06ca6351e003826f;
31: tmp_K = 64'h142929670a0e6e70;
32: tmp_K = 64'h27b70a8546d22ffc;
33: tmp_K = 64'h2e1b21385c26c926;
34: tmp_K = 64'h4d2c6dfc5ac42aed;
35: tmp_K = 64'h53380d139d95b3df;
36: tmp_K = 64'h650a73548baf63de;
37: tmp_K = 64'h766a0abb3c77b2a8;
38: tmp_K = 64'h81c2c92e47edaee6;
39: tmp_K = 64'h92722c851482353b;
40: tmp_K = 64'ha2bfe8a14cf10364;
41: tmp_K = 64'ha81a664bbc423001;
42: tmp_K = 64'hc24b8b70d0f89791;
43: tmp_K = 64'hc76c51a30654be30;
44: tmp_K = 64'hd192e819d6ef5218;
45: tmp_K = 64'hd69906245565a910;
46: tmp_K = 64'hf40e35855771202a;
47: tmp_K = 64'h106aa07032bbd1b8;
48: tmp_K = 64'h19a4c116b8d2d0c8;
49: tmp_K = 64'h1e376c085141ab53;
50: tmp_K = 64'h2748774cdf8eeb99;
51: tmp_K = 64'h34b0bcb5e19b48a8;
52: tmp_K = 64'h391c0cb3c5c95a63;
53: tmp_K = 64'h4ed8aa4ae3418acb;
54: tmp_K = 64'h5b9cca4f7763e373;
55: tmp_K = 64'h682e6ff3d6b2b8a3;
56: tmp_K = 64'h748f82ee5defb2fc;
57: tmp_K = 64'h78a5636f43172f60;
58: tmp_K = 64'h84c87814a1f0ab72;
59: tmp_K = 64'h8cc702081a6439ec;
60: tmp_K = 64'h90befffa23631e28;
61: tmp_K = 64'ha4506cebde82bde9;
62: tmp_K = 64'hbef9a3f7b2c67915;
63: tmp_K = 64'hc67178f2e372532b;
64: tmp_K = 64'hca273eceea26619c;
65: tmp_K = 64'hd186b8c721c0c207;
66: tmp_K = 64'heada7dd6cde0eb1e;
67: tmp_K = 64'hf57d4f7fee6ed178;
68: tmp_K = 64'h06f067aa72176fba;
69: tmp_K = 64'h0a637dc5a2c898a6;
70: tmp_K = 64'h113f9804bef90dae;
71: tmp_K = 64'h1b710b35131c471b;
72: tmp_K = 64'h28db77f523047d84;
73: tmp_K = 64'h32caab7b40c72493;
74: tmp_K = 64'h3c9ebe0a15c9bebc;
75: tmp_K = 64'h431d67c49c100d4c;
76: tmp_K = 64'h4cc5d4becb3e42b6;
77: tmp_K = 64'h597f299cfc657e2a;
78: tmp_K = 64'h5fcb6fab3ad6faec;
79: tmp_K = 64'h6c44198c4a475817;
default:
tmp_K = 64'h0;
endcase // case (addr)
end // block: addr_mux
endmodule // sha512_k_constants
//======================================================================
// sha512_k_constants.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O31A_FUNCTIONAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O21AI_PP_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_PP_BLACKBOX_V
|
`include "riscv_defs.v"
module tb_core;
//--------------------------------------------------------------
parameter C_IRQV_SZ = 32;
reg clk = 1'b1;
reg resetb = 1'b0;
// response
wire request;
reg ireqready;
reg irspvalid;
wire irsprerr;
reg [`RV_XLEN-1:0] irspdata;
// verification fifo
wire [`RV_XLEN-1:0] fifo_dout;
// id stage
wire ids_ack;
reg ids_ack_rand;
// hvec
wire hvec_wr;
reg [`RV_XLEN-1:0] hvec_pc;
reg hvec_rand;
// pfu
wire ireqvalid;
wire [`RV_XLEN-1:0] ireqaddr;
wire irspready;
wire ids_dav;
wire [`RV_XLEN-1:0] ids_ins;
wire [`RV_XLEN-1:0] ids_pc;
wire hvec_pc_ready;
//
//--------------------------------------------------------------
// general setup
//
initial
begin
$dumpfile("wave.lxt");
$dumpvars(0, tb_core);
#(200_000);
$finish();
end
// generate a clock
//
always
begin
#50;
clk = ~clk;
end
// generate a reset
//
always @ (posedge clk)
begin
resetb <= 1'b1;
end
// response
//
assign irsprerr = 1'b0; // TODO
assign request = ireqvalid & ireqready;
//
always @ (posedge clk or negedge resetb)
begin
if (~resetb) begin
end else begin
if (ireqvalid) begin
ireqready <= $random();
end
end
//
if (request) begin
if (ireqaddr[1:0] === 2'b0); else $error("Misaligned address."); // TODO assert
irspvalid <= 1'b1;
irspdata <= ireqaddr;
end else begin
irspvalid <= 1'b0;
end
end
// verification fifo
//
fifo
#(
.C_FIFO_WIDTH (`RV_XLEN),
.C_FIFO_DEPTH_X (4)
) i_fifo (
// global
.clk_i (clk),
.clk_en_i (1'b1),
.resetb_i (resetb),
// control and status
.flush_i (1'b0),
.empty_o (),
.full_o (),
// write port
.wr_i (request),
.din_i (ireqaddr),
// read port
.rd_i (ids_ack),
.dout_o (fifo_dout)
);
// id stage
//
assign ids_ack = (ids_dav ? ids_ack_rand : 1'b0);
//
always @ (posedge clk)
begin
if (ids_ack) begin // new ins this cycle
if (fifo_dout === ids_ins && fifo_dout === ids_pc) begin
end else begin
$error("Incorrect data returned by PFU");
$fatal();
end
end
//
ids_ack_rand <= $random();
end
// hvec
//
assign hvec_wr = hvec_rand & hvec_pc_ready;
always @ (posedge clk or negedge resetb)
begin
if (~resetb) begin
hvec_rand <= 1'b0;
end else begin
hvec_pc <= { $random(), 2'b0 };
if (hvec_pc_ready) begin
if ($random() % 10 == 0) begin
hvec_rand <= 1'b1;
end else begin
hvec_rand <= 1'b0;
end
end
end
end
// prefetch unit
//
pfu
#(
.C_BUS_SZX (5), // bus width base 2 exponent
.C_FIFO_DEPTH_X (2), // pfu fifo depth base 2 exponent
.C_RESET_VECTOR (32'h00000000)
) i_pfu (
// global
.clk_i (clk),
.clk_en_i (1'b1),
.resetb_i (resetb),
// instruction cache interface
.ireqready_i (ireqready),
.ireqvalid_o (ireqvalid),
.ireqhpl_o (),
.ireqaddr_o (ireqaddr),
.irspready_o (irspready),
.irspvalid_i (irspvalid),
.irsprerr_i (irsprerr),
.irspdata_i (irspdata),
// decoder interface
.ids_dav_o (ids_dav), // new fetch available
.ids_ack_i (ids_ack),//ids_ack), // ack this fetch
.ids_sofid_o (), // first fetch since vectoring
.ids_ins_o (ids_ins), // instruction fetched
.ids_ferr_o (), // this instruction fetch resulted in error
.ids_pc_o (ids_pc), // address of this instruction
// vectoring and exception controller interface
.hvec_pc_ready_o (hvec_pc_ready),
.hvec_pc_wr_i (hvec_wr),
.hvec_pc_din_i (hvec_pc),
// pfu stage interface
.exs_hpl_i (2'b0)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_1_V
`define SKY130_FD_SC_HS__NAND4BB_1_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23.09.2016 08:48:06
// Design Name:
// Module Name: linescanner_image_capture_unit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module linescanner_image_capture_unit(
input wire enable,
input wire[7:0] data,
output reg rst_cvc,
output reg rst_cds,
output reg sample,
input wire end_adc,
input wire lval,
input wire pixel_clock,
input wire main_clock_source,
output wire main_clock,
input wire n_reset,
output reg load_pulse,
output wire[7:0] pixel_data,
output wire pixel_captured);
assign main_clock = main_clock_source;
assign pixel_captured = lval ? pixel_clock : 0;
assign pixel_data = data;
localparam
SM1_SEND_FE_OF_RST_CVC = 0,
SM1_SEND_FE_OF_RST_CDS = 1,
SM1_SEND_RE_OF_SAMPLE = 2,
SM1_SEND_FE_OF_SAMPLE = 3,
SM1_SEND_RE_OF_RST_CVC_AND_RST_CDS = 4,
SM1_WAIT_NUM_CLOCKS = 5;
reg[2:0] sm1_state, sm1_state_to_go_to_after_waiting;
reg[5:0] sm1_num_clocks_to_wait, sm1_clock_count;
always @ (posedge pixel_clock or negedge n_reset) begin
if(!n_reset) begin
rst_cvc <= 1'b1;
rst_cds <= 1'b1;
sample <= 1'b0;
sm1_state <= SM1_SEND_FE_OF_RST_CVC;
sm1_state_to_go_to_after_waiting <= 0;
sm1_num_clocks_to_wait <= 0;
sm1_clock_count <= 0;
end
else
case (sm1_state)
SM1_SEND_FE_OF_RST_CVC:
if(enable) begin
rst_cvc <= 1'b0;
sm1_state <= SM1_WAIT_NUM_CLOCKS;
sm1_state_to_go_to_after_waiting <= SM1_SEND_FE_OF_RST_CDS;
sm1_num_clocks_to_wait <= 48;
end
SM1_SEND_FE_OF_RST_CDS:
begin
rst_cds <= 1'b0;
sm1_state <= SM1_WAIT_NUM_CLOCKS;
sm1_state_to_go_to_after_waiting <= SM1_SEND_RE_OF_SAMPLE;
sm1_num_clocks_to_wait <= 7;
end
SM1_SEND_RE_OF_SAMPLE:
begin
if(end_adc) begin
sample <= 1'b1;
sm1_state <= SM1_WAIT_NUM_CLOCKS;
sm1_state_to_go_to_after_waiting <= SM1_SEND_FE_OF_SAMPLE;
sm1_num_clocks_to_wait <= 48;
end
end
SM1_SEND_FE_OF_SAMPLE:
begin
sample <= 1'b0;
sm1_state <= SM1_WAIT_NUM_CLOCKS;
sm1_state_to_go_to_after_waiting <= SM1_SEND_RE_OF_RST_CVC_AND_RST_CDS;
sm1_num_clocks_to_wait <= 6;
end
SM1_SEND_RE_OF_RST_CVC_AND_RST_CDS:
begin
rst_cvc <= 1'b1;
rst_cds <= 1'b1;
sm1_state <= SM1_SEND_FE_OF_RST_CVC;
end
SM1_WAIT_NUM_CLOCKS:
if(sm1_clock_count < sm1_num_clocks_to_wait)
sm1_clock_count <= sm1_clock_count + 1;
else begin
sm1_clock_count <= 0;
sm1_state <= sm1_state_to_go_to_after_waiting;
end
endcase
end
localparam
SM2_WAIT_FOR_RE_OF_END_ADC = 0,
SM2_WAIT_FOR_FE_OF_LVAL = 1,
SM2_SEND_RE_OF_LOAD_PULSE = 2,
SM2_SEND_FE_OF_LOAD_PULSE = 3,
SM2_WAIT_FOR_FE_OF_END_ADC = 4,
SM2_WAIT_NUM_CLOCKS = 5;
reg[2:0] sm2_state, sm2_state_to_go_to_after_waiting;
reg[1:0] sm2_clock_count;
always @ (posedge pixel_clock or negedge n_reset) begin
if(!n_reset) begin
load_pulse <= 1'b0;
sm2_state <= 0;
sm2_state_to_go_to_after_waiting <= 0;
sm2_clock_count <= 0;
end
else
case(sm2_state)
SM2_WAIT_FOR_RE_OF_END_ADC:
if(end_adc) begin
if(!lval) begin
sm2_state <= SM2_WAIT_NUM_CLOCKS;
sm2_state_to_go_to_after_waiting <= SM2_SEND_RE_OF_LOAD_PULSE;
end
else
sm2_state <= SM2_WAIT_FOR_FE_OF_LVAL;
end
SM2_WAIT_FOR_FE_OF_LVAL:
if(!lval) begin
sm2_state <= SM2_WAIT_NUM_CLOCKS;
sm2_state_to_go_to_after_waiting <= SM2_SEND_RE_OF_LOAD_PULSE;
end
SM2_SEND_RE_OF_LOAD_PULSE:
begin
load_pulse <= 1'b1;
sm2_state <= SM2_SEND_FE_OF_LOAD_PULSE;
end
SM2_SEND_FE_OF_LOAD_PULSE:
begin
load_pulse <= 1'b0;
sm2_state <= SM2_WAIT_FOR_FE_OF_END_ADC;
end
SM2_WAIT_FOR_FE_OF_END_ADC:
if(!end_adc)
sm2_state <= SM2_WAIT_FOR_RE_OF_END_ADC;
SM2_WAIT_NUM_CLOCKS:
if(sm2_clock_count < 3)
sm2_clock_count <= sm2_clock_count + 1;
else begin
sm2_clock_count <= 0;
sm2_state <= sm2_state_to_go_to_after_waiting;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_TB_V
`define SKY130_FD_SC_LP__O32A_TB_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o32a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_TB_V
|
`include "ShiftRegister.v"
`include "memory.v"
`include "finiteStateMachine.v"
`include "programCounter.v"
`include "serialClock.v"
`include "mosiFF.v"
`include "delayCounter.v"
module toplevel(led, gpioBank1, gpioBank2, clk, sw, btn); // possible inputs from fpga
output [7:0] led;
output [3:0] gpioBank1;
output [3:0] gpioBank2;
input clk;
input[7:0] sw;
input[3:0] btn;
parameter memBits = 10;
parameter memAddrWidth = 16;
parameter dataBits = 8;
// serialClock
wire sclk, sclkPosEdge, sclkNegEdge;
wire sclk8PosEdge;
// memory
wire writeEnable;
wire[memAddrWidth-1:0] addr;
wire[memBits-1:0] dataIn, dataOut;
// programCounter
wire[memAddrWidth-1:0] memAddr;
wire reset;
assign addr = memAddr;
// shiftRegister
wire parallelLoad, serialDataIn; //not used
wire[dataBits-1:0] parallelDataOut; // also not used
wire[dataBits-1:0] parallelDataIn;
wire serialDataOut;
assign parallelLoad = sclk8PosEdge;
assign parallelDataIn = dataOut;
// finiteStateMachine
wire[memBits-1:0] instr; // probably change this to reflect envelope diagram
wire cs, dc;
wire[dataBits-1:0] parallelData;
assign instr = dataOut;
// FFs
wire md, mq;
assign md = serialDataOut;
wire cd, cq;
assign cd = cs;
wire dd, dq;
assign dd = dc;
// delayCounter
wire delayEn, pcEn;
// OUTPUTS
assign gpioBank1[0] = mq; // mosi
assign gpioBank1[1] = cq; // chip select
assign gpioBank1[2] = dq; // data/command select
assign gpioBank1[3] = sclkPosEdge; // serialClock (positive edge)
assign led = parallelDataOut[7:0];
assign reset = btn[0];
assign gpioBank2[0] = !btn[1];
// Magic
serialClock #(3) sc(clk, sclk, sclkPosEdge, sclkNegEdge, sclk8PosEdge);
memory m(clk, writeEnable, addr, dataIn, dataOut);
programCounter pc(clk, sclkPosEdge, pcEn, memAddr, sclk8PosEdge, reset);
shiftRegister sr(clk, sclkPosEdge, parallelLoad, parallelDataIn, serialDataIn, parallelDataOut, serialDataOut, sclk8PosEdge);
finiteStateMachine fsm(clk, sclkPosEdge, instr, cs, dc, delayEn, parallelData);
mosiFF mff(clk, sclkNegEdge, md, mq);
mosiFF csff(clk, sclkNegEdge, cd, cq);
mosiFF dcff(clk, sclkNegEdge, dd, dq);
delayCounter delC(clk, delayEn, pcEn);
endmodule
module testTopLevel;
wire [7:0] led;
wire [3:0] gpioBank1;
wire[3:0] gpioBank2;
reg clk;
reg[7:0] sw;
reg[3:0] btn;
toplevel tl(led, gpioBank1, gpioBank2, clk, sw, btn);
initial clk=0;
always #10 clk=!clk;
//initial begin
//#7850 btn[0]=1;
//#10 btn[0]=0;
//end
endmodule
|
/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
output wire [1:0] user_led_g,
output wire user_led_r,
output wire [1:0] front_led,
input wire [1:0] user_sw,
/*
* Ethernet: QSFP28
*/
input wire qsfp_0_tx_clk_0,
input wire qsfp_0_tx_rst_0,
output wire [63:0] qsfp_0_txd_0,
output wire [7:0] qsfp_0_txc_0,
input wire qsfp_0_rx_clk_0,
input wire qsfp_0_rx_rst_0,
input wire [63:0] qsfp_0_rxd_0,
input wire [7:0] qsfp_0_rxc_0,
input wire qsfp_0_tx_clk_1,
input wire qsfp_0_tx_rst_1,
output wire [63:0] qsfp_0_txd_1,
output wire [7:0] qsfp_0_txc_1,
input wire qsfp_0_rx_clk_1,
input wire qsfp_0_rx_rst_1,
input wire [63:0] qsfp_0_rxd_1,
input wire [7:0] qsfp_0_rxc_1,
input wire qsfp_0_tx_clk_2,
input wire qsfp_0_tx_rst_2,
output wire [63:0] qsfp_0_txd_2,
output wire [7:0] qsfp_0_txc_2,
input wire qsfp_0_rx_clk_2,
input wire qsfp_0_rx_rst_2,
input wire [63:0] qsfp_0_rxd_2,
input wire [7:0] qsfp_0_rxc_2,
input wire qsfp_0_tx_clk_3,
input wire qsfp_0_tx_rst_3,
output wire [63:0] qsfp_0_txd_3,
output wire [7:0] qsfp_0_txc_3,
input wire qsfp_0_rx_clk_3,
input wire qsfp_0_rx_rst_3,
input wire [63:0] qsfp_0_rxd_3,
input wire [7:0] qsfp_0_rxc_3,
input wire qsfp_1_tx_clk_0,
input wire qsfp_1_tx_rst_0,
output wire [63:0] qsfp_1_txd_0,
output wire [7:0] qsfp_1_txc_0,
input wire qsfp_1_rx_clk_0,
input wire qsfp_1_rx_rst_0,
input wire [63:0] qsfp_1_rxd_0,
input wire [7:0] qsfp_1_rxc_0,
input wire qsfp_1_tx_clk_1,
input wire qsfp_1_tx_rst_1,
output wire [63:0] qsfp_1_txd_1,
output wire [7:0] qsfp_1_txc_1,
input wire qsfp_1_rx_clk_1,
input wire qsfp_1_rx_rst_1,
input wire [63:0] qsfp_1_rxd_1,
input wire [7:0] qsfp_1_rxc_1,
input wire qsfp_1_tx_clk_2,
input wire qsfp_1_tx_rst_2,
output wire [63:0] qsfp_1_txd_2,
output wire [7:0] qsfp_1_txc_2,
input wire qsfp_1_rx_clk_2,
input wire qsfp_1_rx_rst_2,
input wire [63:0] qsfp_1_rxd_2,
input wire [7:0] qsfp_1_rxc_2,
input wire qsfp_1_tx_clk_3,
input wire qsfp_1_tx_rst_3,
output wire [63:0] qsfp_1_txd_3,
output wire [7:0] qsfp_1_txc_3,
input wire qsfp_1_rx_clk_3,
input wire qsfp_1_rx_rst_3,
input wire [63:0] qsfp_1_rxd_3,
input wire [7:0] qsfp_1_rxc_3
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign user_led_g = ~led_reg[1:0];
assign user_led_r = 1'b1;
assign front_led = 2'b00;
assign qsfp_0_txd_1 = 64'h0707070707070707;
assign qsfp_0_txc_1 = 8'hff;
assign qsfp_0_txd_2 = 64'h0707070707070707;
assign qsfp_0_txc_2 = 8'hff;
assign qsfp_0_txd_3 = 64'h0707070707070707;
assign qsfp_0_txc_3 = 8'hff;
assign qsfp_1_txd_0 = 64'h0707070707070707;
assign qsfp_1_txc_0 = 8'hff;
assign qsfp_1_txd_1 = 64'h0707070707070707;
assign qsfp_1_txc_1 = 8'hff;
assign qsfp_1_txd_2 = 64'h0707070707070707;
assign qsfp_1_txc_2 = 8'hff;
assign qsfp_1_txd_3 = 64'h0707070707070707;
assign qsfp_1_txc_3 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp_0_rx_clk_0),
.rx_rst(qsfp_0_rx_rst_0),
.tx_clk(qsfp_0_tx_clk_0),
.tx_rst(qsfp_0_tx_rst_0),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(qsfp_0_rxd_0),
.xgmii_rxc(qsfp_0_rxc_0),
.xgmii_txd(qsfp_0_txd_0),
.xgmii_txc(qsfp_0_txc_0),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes data to the Audio chip on Altera's DE2 *
* Development and Education Board. The audio chip must be in master mode *
* and the digital format must be left justified. *
* *
******************************************************************************/
module nios_system_audio_0 (
// Inputs
clk,
reset,
address,
chipselect,
read,
write,
writedata,
AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
// Outputs
irq,
readdata,
AUD_DACDAT
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] address;
input chipselect;
input read;
input write;
input [31: 0] writedata;
input AUD_ADCDAT;
input AUD_ADCLRCK;
input AUD_BCLK;
input AUD_DACLRCK;
// Bidirectionals
// Outputs
output reg irq;
output reg [31: 0] readdata;
output AUD_DACDAT;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam DW = 15;
localparam BIT_COUNTER_INIT = 5'd15;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire bclk_rising_edge;
wire bclk_falling_edge;
wire adc_lrclk_rising_edge;
wire adc_lrclk_falling_edge;
wire [DW: 0] new_left_channel_audio;
wire [DW: 0] new_right_channel_audio;
wire [ 7: 0] left_channel_read_available;
wire [ 7: 0] right_channel_read_available;
wire dac_lrclk_rising_edge;
wire dac_lrclk_falling_edge;
wire [ 7: 0] left_channel_write_space;
wire [ 7: 0] right_channel_write_space;
// Internal Registers
reg done_adc_channel_sync;
reg read_interrupt_en;
reg clear_read_fifos;
reg read_interrupt;
reg done_dac_channel_sync;
reg write_interrupt_en;
reg clear_write_fifos;
reg write_interrupt;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
irq <= 1'b0;
else
irq <=
write_interrupt |
read_interrupt;
end
always @(posedge clk)
begin
if (reset == 1'b1)
readdata <= 32'h00000000;
else if (chipselect == 1'b1)
begin
if (address == 2'h0)
readdata <=
{22'h000000,
write_interrupt,
read_interrupt,
4'h0,
clear_write_fifos,
clear_read_fifos,
write_interrupt_en,
read_interrupt_en};
else if (address == 2'h1)
begin
readdata[31:24] <= left_channel_write_space;
readdata[23:16] <= right_channel_write_space;
readdata[15: 8] <= left_channel_read_available;
readdata[ 7: 0] <= right_channel_read_available;
end
else if (address == 2'h2)
readdata <= 32'h00000000 |
new_left_channel_audio;
else
readdata <= 32'h00000000 |
new_right_channel_audio;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
read_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 2'h0))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
clear_read_fifos <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 2'h0))
clear_read_fifos <= writedata[2];
end
always @(posedge clk)
begin
if (reset == 1'b1)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <=
(&(left_channel_read_available[6:5]) | left_channel_read_available[7]) |
(&(right_channel_read_available[6:5]) | right_channel_read_available[7]);
end
always @(posedge clk)
begin
if (reset == 1'b1)
done_adc_channel_sync <= 1'b0;
else if (adc_lrclk_rising_edge == 1'b1)
done_adc_channel_sync <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 2'h0))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset == 1'b1)
clear_write_fifos <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 2'h0))
clear_write_fifos <= writedata[3];
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <=
(&(left_channel_write_space[6:5]) | left_channel_write_space[7]) |
(&(right_channel_write_space[6:5]) | right_channel_write_space[7]);
end
always @(posedge clk)
begin
if (reset == 1'b1)
done_dac_channel_sync <= 1'b0;
else if (dac_lrclk_falling_edge == 1'b1)
done_dac_channel_sync <= 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_clock_edge Bit_Clock_Edges (
// Inputs
.clk (clk),
.reset (reset),
.test_clk (AUD_BCLK),
// Bidirectionals
// Outputs
.rising_edge (bclk_rising_edge),
.falling_edge (bclk_falling_edge)
);
altera_up_clock_edge ADC_Left_Right_Clock_Edges (
// Inputs
.clk (clk),
.reset (reset),
.test_clk (AUD_ADCLRCK),
// Bidirectionals
// Outputs
.rising_edge (adc_lrclk_rising_edge),
.falling_edge (adc_lrclk_falling_edge)
);
altera_up_clock_edge DAC_Left_Right_Clock_Edges (
// Inputs
.clk (clk),
.reset (reset),
.test_clk (AUD_DACLRCK),
// Bidirectionals
// Outputs
.rising_edge (dac_lrclk_rising_edge),
.falling_edge (dac_lrclk_falling_edge)
);
altera_up_audio_in_deserializer Audio_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset | clear_read_fifos),
.bit_clk_rising_edge (bclk_rising_edge),
.bit_clk_falling_edge (bclk_falling_edge),
.left_right_clk_rising_edge (adc_lrclk_rising_edge),
.left_right_clk_falling_edge (adc_lrclk_falling_edge),
.done_channel_sync (done_adc_channel_sync),
.serial_audio_in_data (AUD_ADCDAT),
.read_left_audio_data_en ((address == 2'h2) & chipselect & read),
.read_right_audio_data_en ((address == 2'h3) & chipselect & read),
// Bidirectionals
// Outputs
.left_audio_fifo_read_space (left_channel_read_available),
.right_audio_fifo_read_space (right_channel_read_available),
.left_channel_data (new_left_channel_audio),
.right_channel_data (new_right_channel_audio)
);
defparam
Audio_In_Deserializer.DW = DW,
Audio_In_Deserializer.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
altera_up_audio_out_serializer Audio_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset | clear_write_fifos),
.bit_clk_rising_edge (bclk_rising_edge),
.bit_clk_falling_edge (bclk_falling_edge),
.left_right_clk_rising_edge (done_dac_channel_sync & dac_lrclk_rising_edge),
.left_right_clk_falling_edge (done_dac_channel_sync & dac_lrclk_falling_edge),
.left_channel_data (writedata[DW:0]),
.left_channel_data_en ((address == 2'h2) & chipselect & write),
.right_channel_data (writedata[DW:0]),
.right_channel_data_en ((address == 2'h3) & chipselect & write),
// Bidirectionals
// Outputs
.left_channel_fifo_write_space (left_channel_write_space),
.right_channel_fifo_write_space (right_channel_write_space),
.serial_audio_out_data (AUD_DACDAT)
);
defparam
Audio_Out_Serializer.DW = DW;
endmodule
|
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_burst_gen #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_TCCD = 4,
CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1,
CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1,
CFG_ENABLE_BURST_GEN_OUTPUT_REG = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_type,
cfg_burst_length,
cfg_tccd,
cfg_enable_burst_interrupt,
cfg_enable_burst_terminate,
// Arbiter Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size,
// AFI Interface
bg_do_write_combi,
bg_do_read_combi,
bg_do_burst_chop_combi,
bg_do_burst_terminate_combi,
bg_do_activate_combi,
bg_do_precharge_combi,
bg_to_chip_combi,
bg_effective_size_combi,
bg_interrupt_ready_combi,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_zq_cal,
bg_do_lmr,
bg_to_chipsel,
bg_to_chip,
bg_to_bank,
bg_to_row,
bg_to_col,
bg_doing_write,
bg_doing_read,
bg_rdwr_data_valid,
bg_interrupt_ready,
bg_localid,
bg_dataid,
bg_size,
bg_effective_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT - 1 : 0] cfg_enable_burst_interrupt;
input [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE - 1 : 0] cfg_enable_burst_terminate;
// Arbiter Interface
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
input [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
input [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// AFI Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
output bg_interrupt_ready_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
output bg_doing_write;
output bg_doing_read;
output bg_rdwr_data_valid;
output bg_interrupt_ready;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// AFI Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
reg bg_doing_write;
reg bg_doing_read;
reg bg_rdwr_data_valid;
reg bg_interrupt_ready;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
// Burst generation logic
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] int_to_col;
reg [2 : 0] int_col_address;
reg [2 : 0] int_address_left;
reg int_do_row_req;
reg int_do_col_req;
reg int_do_rd_req;
reg int_do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_partial;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] to_col;
reg [2 : 0] col_address;
reg [2 : 0] address_left;
reg do_row_req;
reg do_col_req;
reg do_rd_req;
reg do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_partial;
reg [3 : 0] max_local_burst_size;
reg [3 : 0] max_local_burst_size_divide_2;
reg [3 : 0] max_local_burst_size_minus_2;
reg [3 : 0] max_local_burst_size_divide_2_and_minus_2;
reg [3 : 0] burst_left;
reg current_valid;
reg delayed_valid;
reg combined_valid;
reg [3 : 0] max_burst_left;
reg delayed_doing;
reg last_is_write;
reg last_is_read;
// Burst interrupt logic
reg [CFG_PORT_WIDTH_TCCD - 2 : 0] n_prefetch;
reg int_allow_interrupt;
reg int_interrupt_enable_ready;
reg int_interrupt_disable_ready;
reg int_interrupt_gate;
// Burst terminate logic
reg int_allow_terminate;
reg int_do_burst_terminate;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_do_req;
reg doing_burst_terminate;
reg terminate_doing;
// RMW Info
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_partial;
// Data ID
reg [CFG_DATA_ID_WIDTH - 1 : 0] delayed_dataid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] combined_dataid;
// Column address
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] modified_to_col;
// Common
wire zero = 1'b0;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
reg bg_interrupt_ready_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_terminate;
reg doing_write;
reg doing_read;
reg rdwr_data_valid;
reg interrupt_ready;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
// Do signals
generate
if (CFG_ENABLE_BURST_GEN_OUTPUT_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (! ctl_reset_n)
begin
bg_do_write <= 0;
bg_do_read <= 0;
bg_do_auto_precharge <= 0;
bg_do_rmw_correct <= 0;
bg_do_rmw_partial <= 0;
bg_do_activate <= 0;
bg_do_precharge <= 0;
bg_do_precharge_all <= 0;
bg_do_refresh <= 0;
bg_do_self_refresh <= 0;
bg_do_power_down <= 0;
bg_do_deep_pdown <= 0;
bg_do_zq_cal <= 0;
bg_do_lmr <= 0;
bg_to_chip <= 0;
bg_to_chipsel <= 0;
bg_to_bank <= 0;
bg_to_row <= 0;
bg_localid <= 0;
bg_size <= 0;
bg_to_col <= 0;
bg_dataid <= 0;
bg_do_burst_chop <= 0;
bg_do_burst_terminate <= 0;
bg_doing_write <= 0;
bg_doing_read <= 0;
bg_rdwr_data_valid <= 0;
bg_interrupt_ready <= 0;
bg_effective_size <= 0;
end
else
begin
bg_do_write <= arb_do_write;
bg_do_read <= arb_do_read;
bg_do_auto_precharge <= arb_do_auto_precharge;
bg_do_rmw_correct <= combined_do_rmw_correct;
bg_do_rmw_partial <= combined_do_rmw_partial;
bg_do_activate <= arb_do_activate;
bg_do_precharge <= arb_do_precharge;
bg_do_precharge_all <= arb_do_precharge_all;
bg_do_refresh <= arb_do_refresh;
bg_do_self_refresh <= arb_do_self_refresh;
bg_do_power_down <= arb_do_power_down;
bg_do_deep_pdown <= arb_do_deep_pdown;
bg_do_zq_cal <= arb_do_zq_cal;
bg_do_lmr <= arb_do_lmr;
bg_to_chip <= arb_to_chip;
bg_to_chipsel <= arb_to_chipsel;
bg_to_bank <= arb_to_bank;
bg_to_row <= arb_to_row;
bg_localid <= arb_localid;
bg_size <= arb_size;
bg_to_col <= modified_to_col;
bg_dataid <= combined_dataid;
bg_do_burst_chop <= do_burst_chop;
bg_do_burst_terminate <= do_burst_terminate;
bg_doing_write <= doing_write;
bg_doing_read <= doing_read;
bg_rdwr_data_valid <= rdwr_data_valid;
bg_interrupt_ready <= interrupt_ready;
bg_effective_size <= effective_size;
end
end
end
else
begin
always @ (*)
begin
bg_do_write = arb_do_write;
bg_do_read = arb_do_read;
bg_do_auto_precharge = arb_do_auto_precharge;
bg_do_activate = arb_do_activate;
bg_do_precharge = arb_do_precharge;
bg_do_precharge_all = arb_do_precharge_all;
bg_do_refresh = arb_do_refresh;
bg_do_self_refresh = arb_do_self_refresh;
bg_do_power_down = arb_do_power_down;
bg_do_deep_pdown = arb_do_deep_pdown;
bg_do_zq_cal = arb_do_zq_cal;
bg_do_lmr = arb_do_lmr;
bg_to_chip = arb_to_chip;
bg_to_chipsel = arb_to_chipsel;
bg_to_bank = arb_to_bank;
bg_to_row = arb_to_row;
bg_localid = arb_localid;
bg_size = arb_size;
bg_do_burst_chop = do_burst_chop;
bg_do_burst_terminate = do_burst_terminate;
bg_doing_write = doing_write;
bg_doing_read = doing_read;
bg_rdwr_data_valid = rdwr_data_valid;
bg_interrupt_ready = interrupt_ready;
bg_effective_size = effective_size;
end
// To column
always @ (*)
begin
bg_to_col = modified_to_col;
end
// RMW info
always @ (*)
begin
bg_do_rmw_correct = combined_do_rmw_correct;
bg_do_rmw_partial = combined_do_rmw_partial;
end
// Data ID
always @ (*)
begin
bg_dataid = combined_dataid;
end
end
endgenerate
// Regardless whether CFG_ENABLE_BURST_GEN_OUTPUT_REG is 1/0
// following signals (inputs to rank_timer) need to be combi
always @ (*)
begin
bg_do_write_combi = arb_do_write;
bg_do_read_combi = arb_do_read;
bg_do_burst_chop_combi = do_burst_chop;
bg_do_burst_terminate_combi = do_burst_terminate;
bg_do_activate_combi = arb_do_activate;
bg_do_precharge_combi = arb_do_precharge;
bg_to_chip_combi = arb_to_chip;
bg_effective_size_combi = effective_size;
bg_interrupt_ready_combi = interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Generation Logic
//
// Doing read/write signal will indicate the "FULL" burst duration of a request
// Data Valid signal will indicate "VALID" burst duration of a request
//
// Example: Without address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Input Size ----X 1 X-----------------X 2 X-----------------X 3 X-----------------X 4 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal ____/ 1 \_________________/ 1 X 2 \___________/ 1 X 2 X 3 \_____/ 1 X 2 X 3 X 4 \_____
//
// Example: With address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 1 X-----------------X 2 X-----------------X 2 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 2 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal __________/ 1 \_______________________/ 1 \_________________/ 1 X 2 \_____
// <-----> <-----------> <----------->
// Offset Offset Offset
//
// Example: Burst chop for DDR3 only (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 1 X-----------------X 2 X-----------------X 3 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 1 X-----------------X 1 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 2 X-----------------X 2 X-----------------------
// Output Burst Chop Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Output Doing Signal ____/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \_________________
// Output Valid Signal ____/ 1 \_______________________/ 1 \___________/ 1 \_______________________/ 1 \_________________
// <-----> <----->
// Offset Offset
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Maximum local burst size
//----------------------------------------------------------------------------------------------------
// Calculate maximum local burst size
// based on burst length and controller rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size_divide_2 <= 0;
max_local_burst_size_minus_2 <= 0;
max_local_burst_size_divide_2_and_minus_2 <= 0;
end
else
begin
max_local_burst_size_divide_2 <= max_local_burst_size / 2;
max_local_burst_size_minus_2 <= max_local_burst_size - 2'd2;
max_local_burst_size_divide_2_and_minus_2 <= (max_local_burst_size / 2) - 2'd2;
end
end
//----------------------------------------------------------------------------------------------------
// Address shifting
//----------------------------------------------------------------------------------------------------
// Column address
// we only require address [2 - 0] because the maximum supported
// local burst count is 8 which is BL of 16 in full rate
// we only take low phase of arb_to_col address because high and low phase is identical
always @ (*)
begin
int_col_address = 0;
if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop) // DDR3 and burst chop, we don't want address shifting during burst chop
begin
if (max_local_burst_size [2]) // max local burst of 4
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else
// max local burst of 1, 2 - address shifting in burst chop is not possible
// max local burst of 8 - not supported in DDR3, there is no BL 16 support in DDR3
int_col_address = 0;
end
else if (max_local_burst_size [0]) // max local burst of 1
int_col_address = 0;
else if (max_local_burst_size [1]) // max local burst of 2
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [2]) // max local burst of 4
int_col_address [1 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 1 : (CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [3]) // max local burst of 8
int_col_address [2 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 2 : (CFG_DWIDTH_RATIO / 2)];
end
always @ (*)
begin
col_address = int_col_address;
end
//----------------------------------------------------------------------------------------------------
// Command Info
//----------------------------------------------------------------------------------------------------
// To col address
always @ (*)
begin
int_to_col = arb_to_col;
end
// Row request
always @ (*)
begin
int_do_row_req = (|arb_do_activate) | (|arb_do_precharge);
end
// Column request
always @ (*)
begin
int_do_col_req = (|arb_do_write) | (|arb_do_read);
end
// Read and write request
always @ (*)
begin
int_do_rd_req = |arb_do_read;
int_do_wr_req = |arb_do_write;
end
// Burst chop
always @ (*)
begin
int_do_burst_chop = arb_do_burst_chop;
end
// RMW info
always @ (*)
begin
int_do_rmw_correct = arb_do_rmw_correct;
int_do_rmw_partial = arb_do_rmw_partial;
end
// Other Info: size, dataid
always @ (*)
begin
int_size = arb_size;
int_dataid = arb_dataid;
end
always @ (*)
begin
size = int_size;
dataid = int_dataid;
to_col = int_to_col;
do_row_req = int_do_row_req;
do_col_req = int_do_col_req;
do_rd_req = int_do_rd_req;
do_wr_req = int_do_wr_req;
do_burst_chop = int_do_burst_chop;
do_rmw_correct = int_do_rmw_correct;
do_rmw_partial = int_do_rmw_partial;
end
//----------------------------------------------------------------------------------------------------
// Address Count
//----------------------------------------------------------------------------------------------------
// Address counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
address_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address > 1'b1)
address_left <= col_address - 2'd2;
else
address_left <= 0;
end
else if (address_left != 0)
address_left <= address_left - 1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Valid Signal
//----------------------------------------------------------------------------------------------------
// Burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address == 0) // no shifting required
begin
if (size > 1'b1)
burst_left <= size - 2'd2;
else
burst_left <= 0;
end
else if (col_address == 1'b1) // require shifting
begin
burst_left <= size - 1'b1;
end
else // require shifting
begin
burst_left <= size;
end
end
else if (address_left == 0 && burst_left != 0) // start decreasing only after addres shifting is completed
burst_left <= burst_left - 1'b1;
end
end
// Current valid signal
// when there is a column request and column address is "0"
// valid signal must be asserted along with column request
always @ (*)
begin
if (do_col_req && col_address == 0)
current_valid = 1'b1;
else
current_valid = 1'b0;
end
// Delayed valid signal
// when there is a column request with size larger than "1"
// valid signal will be asserted according to the request size
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_valid <= 0;
end
else
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address == 1'b1))
delayed_valid <= 1'b1;
else if (address_left == 0 && burst_left > 0)
delayed_valid <= 1'b1;
else
delayed_valid <= 1'b0;
end
end
// Combined valid signal
always @ (*)
begin
combined_valid = current_valid | delayed_valid;
end
// Read write valid signal
always @ (*)
begin
rdwr_data_valid = combined_valid;
end
//----------------------------------------------------------------------------------------------------
// Doing Signal
//----------------------------------------------------------------------------------------------------
// Maximum burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (do_burst_chop)
begin
if (max_local_burst_size_divide_2 <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_divide_2_and_minus_2;
end
else
begin
if (max_local_burst_size <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_minus_2;
end
end
else if (max_burst_left != 0)
max_burst_left <= max_burst_left - 1'b1;
end
end
// Delayed doing signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_doing <= 0;
end
else
begin
if (do_col_req)
begin
if (max_local_burst_size <= 1'b1) //do not generate delayed_doing if max burst count is 1
delayed_doing <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
delayed_doing <= 1'b0;
else
delayed_doing <= 1'b1;
end
else if (max_burst_left > 0)
delayed_doing <= 1'b1;
else
delayed_doing <= 1'b0;
end
end
// Keep track of last commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b0;
end
else
begin
if (do_wr_req)
begin
last_is_write <= 1'b1;
last_is_read <= 1'b0;
end
else if (do_rd_req)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b1;
end
end
end
// Doing write signal
always @ (*)
begin
if (do_rd_req)
doing_write = 1'b0;
else if (do_wr_req)
doing_write = ~terminate_doing;
else if (last_is_write)
doing_write = delayed_doing & ~terminate_doing;
else
doing_write = 1'b0;
end
// Doing read signal
always @ (*)
begin
if (do_wr_req)
doing_read = 1'b0;
else if (do_rd_req)
doing_read = ~terminate_doing;
else if (last_is_read)
doing_read = delayed_doing & ~terminate_doing;
else
doing_read = 1'b0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Generation Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
// Registered arb_do_rmw_* signal when there is a coumn request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_do_rmw_correct <= 0;
delayed_do_rmw_partial <= 0;
end
else
begin
if (do_col_req)
begin
delayed_do_rmw_correct <= do_rmw_correct;
delayed_do_rmw_partial <= do_rmw_partial;
end
end
end
// Prolong RMW information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
begin
combined_do_rmw_correct = do_rmw_correct;
combined_do_rmw_partial = do_rmw_partial;
end
else if (delayed_doing)
begin
combined_do_rmw_correct = delayed_do_rmw_correct;
combined_do_rmw_partial = delayed_do_rmw_partial;
end
else
begin
combined_do_rmw_correct = 0;
combined_do_rmw_partial = 0;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Data ID
//
//--------------------------------------------------------------------------------------------------------
// Register data ID when there is a column request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_dataid <= 0;
end
else
begin
if (do_col_req)
delayed_dataid <= dataid;
end
end
// Prolong data ID information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
combined_dataid = dataid;
else if (delayed_doing)
combined_dataid = delayed_dataid;
else
combined_dataid = 0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Data ID
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Column Address
//
//--------------------------------------------------------------------------------------------------------
// Change column address bit [2 : 0]
// see waveform examples in burst generation logic portion
always @ (*)
begin
modified_to_col = to_col;
// During burst chop in DDR3 only, retain original column address
// maximum local burst in DDR3 is 4 which is BL8 in full rate
if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)
begin
if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
else
begin
if (max_local_burst_size [0]) // max local burst of 1
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 2 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 2 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [3]) // max local burst of 8
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 3 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 3 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Column Address
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Interrupt
//
// DDR, DDR2, LPDDR and LPDDR2 specific
//
// This logic re-use most of the existing logic in burst generation section (valid signal)
// This signal will be used in rank timer block to gate can_read and can_write signals
//
// Example: (DDR2 full rate, burst length of 8, this will result in maximum local burst of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Do Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Valid Signal ____/ 1 \_______________________/ 1 \_______________________/ 1 \_______________________/ 1 \_____
//
// Interrupt Ready (tCCD = 1) / HIGH \_____/ HIGH \___________/ HIGH \_________________/
// Interrupt Ready (tCCD = 2) / HIGH \_____/ HIGH \_____/ HIGH \_________________/ \_________________/
//
//--------------------------------------------------------------------------------------------------------
// n-prefetch architecture, related tCCD value (only support 1, 2 and 4)
// if tCCD is set to 1, command can be interrupted / terminated at every 2 memory burst boundary (1 memory clock cycle)
// if tCCD is set to 2, command can be interrupted / terminated at every 4 memory burst boundary (2 memory clock cycle)
// if tCCD is set to 4, command can be interrupted / terminated at every 8 memory burst boundary (4 memory clock cycle)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
n_prefetch <= 0;
end
else
begin
n_prefetch <= cfg_tccd / (CFG_DWIDTH_RATIO / 2);
end
end
// For n_prefetch of 0 and 1, we will allow interrupt at any controller clock cycles
// for n_prefetch of n, we will allow interrupt at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_interrupt <= 1'b1;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR3) // DDR3 specific, interrupt masking is handled by setting read-to-read and write-to-write to BL/2
int_allow_interrupt <= 1'b1;
else
begin
if (n_prefetch <= 1) // allow interrupt at any clock cycle
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address != 0))
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 2)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [0] == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 4)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [1 : 0] == 0)
int_allow_interrupt <= 1'b1;
end
end
end
end
// Interrupt info when interrupt feature is enabled
always @ (*)
begin
int_interrupt_enable_ready = int_allow_interrupt;
end
// Interrupt info when interrupt feature is disabled
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_interrupt_disable_ready <= 0;
end
else
begin
if (do_col_req)
begin
if (CFG_REG_GRANT)
begin
if (max_local_burst_size <= 2'd2) //do not generate int_interrupt_ready
int_interrupt_disable_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 3'd4)
int_interrupt_disable_ready <= 1'b0;
else
int_interrupt_disable_ready <= 1'b1;
end
else
begin
if (max_local_burst_size <= 1'b1) //do not generate int_interrupt_ready if max burst count is 1
int_interrupt_disable_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
int_interrupt_disable_ready <= 1'b0;
else
int_interrupt_disable_ready <= 1'b1;
end
end
else if (!CFG_REG_GRANT && max_burst_left > 0)
int_interrupt_disable_ready <= 1'b1;
else if ( CFG_REG_GRANT && max_burst_left > 1'b1)
int_interrupt_disable_ready <= 1'b1;
else
int_interrupt_disable_ready <= 1'b0;
end
end
// Assign to output ports
always @ (*)
begin
if (cfg_enable_burst_interrupt)
begin
interrupt_ready = ~int_interrupt_enable_ready;
end
else
begin
interrupt_ready = ~int_interrupt_disable_ready;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Interrupt
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Terminate
//
// LPDDR1 and LPDDR2 specific only
//
//--------------------------------------------------------------------------------------------------------
// For n_prefetch of 0 and 1, we will allow terminate at any controller clock cycles
// for n_prefetch of n, we will allow terminate at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else
begin
if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2) // LPDDR1 and LPDDR2 only
begin
if (n_prefetch <= 1) // allow terminate at any clock cycle
begin
if (do_col_req && col_address != 0)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (do_col_req && col_address == 0 && size == 1'b1)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 2)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 4)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [1 : 0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
end
else
begin
int_allow_terminate <= 1'b0;
end
end
end
// Effective size, actual issued size migh be smaller that maximum local burst size
// we need to inform rank timer about this information for efficient DQ bus turnaround operation
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_effective_size <= 0;
end
else
begin
if (do_col_req)
int_effective_size <= 1'b1;
else if (int_effective_size != {CFG_INT_SIZE_WIDTH{1'b1}})
int_effective_size <= int_effective_size + 1'b1;
end
end
// Terminate doing signal, this signal will be used to mask off doing_read or doing_write signal
// when we issue a burst terminate signal, we should also terminate doing_read and doing_write signal
// to prevent unwanted DQS toggle on the memory interface
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && ((|do_burst_terminate) == 1'b1 || doing_burst_terminate == 1'b1))
doing_burst_terminate <= 1'b1;
else
doing_burst_terminate <= 1'b0;
end
end
always @ (*)
begin
if (cfg_enable_burst_terminate)
begin
terminate_doing = (|do_burst_terminate) | doing_burst_terminate;
end
else
begin
terminate_doing = zero;
end
end
// Burst terminate output ports
// set burst terminate signal to '0' when there is a do_col_req (in half and quarter rate)
// or both do_col_req and do_row_req (full rate) because this indicate there is a incoming command
// any command from arbiter is have higher priority compared to burst terminate command
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
int_do_req = do_col_req | do_row_req;
else
int_do_req = do_col_req;
end
generate
begin
if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (cfg_enable_burst_terminate)
begin
if (int_do_req)
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
end
else
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = int_do_burst_terminate;
end
end
else
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
end
end
end
else if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (cfg_enable_burst_terminate)
begin
if (int_do_req)
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
end
else
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = int_do_burst_terminate;
end
end
else
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
end
end
end
end
endgenerate
// Effective size output ports
always @ (*)
begin
if (cfg_enable_burst_terminate)
begin
effective_size = int_effective_size;
end
else
begin
effective_size = {CFG_INT_SIZE_WIDTH{zero}};
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Terminate
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Chop
//
// DDR3 specific only
//
//--------------------------------------------------------------------------------------------------------
// yyong generate
// yyong begin
// yyong if (CFG_DWIDTH_RATIO == 2)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size <= 2 && arb_to_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 4)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = 0;
// yyong
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 8)
// yyong begin
// yyong // Burst chop is not available in quarter rate
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{zero}};
// yyong end
// yyong end
// yyong end
// yyong endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Chop
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
`timescale 1 ps / 1 ps
module zynq_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
zynq_1 zynq_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_1_V
`define SKY130_FD_SC_LP__AND3B_1_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_1 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_1_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram1 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [9:0] rdaddress;
input rdclock;
input [10:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (wrclock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.clock1 (rdclock),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({16{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram1_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram1_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_TB_V
`define SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_TB_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 RESET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 RESET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 RESET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 RESET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_TB_V
|
//--------------------------------------------------------------------------------
//-- Filename: INT_MANAGER.v
//--
//-- Description: INTERRUPT MANAGER Module
//--
//-- The module receives done signals from CPM module and then gener-
//-- ates interrupt singals to notify HOST a request has done.
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module INT_MANAGER(
clk,
rst_n,
en,
int_en,
rd_int_msk_i,
wr_int_msk_i,
rd_req_done_i,
wr_req_done_i,
int_cnt_o,
msi_on,
cfg_interrupt_assert_n_o,
cfg_interrupt_rdy_n_i,
cfg_interrupt_n_o,
cfg_interrupt_legacyclr
);
parameter INT_RST = 2'b01;
parameter INT_PENDING = 2'b10;
input clk;
input rst_n;
input en;
input int_en;
input rd_int_msk_i , wr_int_msk_i;
input rd_req_done_i , wr_req_done_i;
output [31:0] int_cnt_o;
input msi_on;
output cfg_interrupt_assert_n_o;
input cfg_interrupt_rdy_n_i;
output cfg_interrupt_n_o;
input cfg_interrupt_legacyclr;
reg [31:0] int_cnt_o;
reg cfg_interrupt_n_o;
reg rd_int , wr_int;
reg rd_req_done_prev , wr_req_done_prev;
reg int_clr;
reg [1:0] intr_state;
// capture read and write request done signals , some interrupts
// will be lost but the HOST driver should take this into cons-
// ideration.
always @ ( posedge clk ) begin
if( !rst_n || !en ) begin
rd_int <= 1'b0;
wr_int <= 1'b0;
rd_req_done_prev <= 1'b0;
wr_req_done_prev <= 1'b0;
end
else begin
rd_req_done_prev <= rd_req_done_i;
wr_req_done_prev <= wr_req_done_i;
if( int_clr || !int_en ) begin
rd_int <= 1'b0;
wr_int <= 1'b0;
end
else begin
if( !rd_req_done_prev && rd_req_done_i && !rd_int_msk_i)
rd_int <= 1'b1;
if( !wr_req_done_prev && wr_req_done_i && !wr_int_msk_i )
wr_int <= 1'b1;
end //if( int_clr || !int_en )
end //if( rst_n || !en )
end
// assert the interrupt signal to the core causes the core sends
// a MSI INT message to HOST.
//
always @ ( posedge clk ) begin
if( !rst_n || !en ) begin
int_clr <= 1'b0;
cfg_interrupt_n_o <= 1'b1;
int_cnt_o <= 32'b0;
intr_state <= INT_RST;
end
else begin
case ( intr_state )
INT_RST: begin
if( rd_int | wr_int ) begin
int_clr <= 1'b1;
cfg_interrupt_n_o <= 1'b0;
int_cnt_o <= int_cnt_o + 1'b1;
intr_state <= INT_PENDING;
end
end
INT_PENDING: begin
int_clr <= 1'b0;
if( !cfg_interrupt_rdy_n_i ) begin
cfg_interrupt_n_o <= 1'b1;
intr_state <= INT_RST;
end
end
default: intr_state <= INT_RST;
endcase
end //if( !rst_n || !en )
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_1_V
`define SKY130_FD_SC_MS__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_PR_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_PR_BLACKBOX_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dlatch$PR (
Q ,
D ,
GATE ,
RESET
);
output Q ;
input D ;
input GATE ;
input RESET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_PR_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_2_V
`define SKY130_FD_SC_HD__EINVN_2_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_2_V
|
/*
* include/linux/ion.h
*
* Copyright (C) 2011 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _LINUX_ION_H
#define _LINUX_ION_H
#include "config.h"
#include <linux/types.h>
#ifdef CONFIG_COMPAT
#include "hacked/compat.h"
#endif
typedef int ion_user_handle_t;
/**
* enum ion_heap_types - list of all possible types of heaps
* @ION_HEAP_TYPE_SYSTEM: memory allocated via vmalloc
* @ION_HEAP_TYPE_SYSTEM_CONTIG: memory allocated via kmalloc
* @ION_HEAP_TYPE_CARVEOUT: memory allocated from a prereserved
* carveout heap, allocations are physically
* contiguous
* @ION_HEAP_TYPE_DMA: memory allocated via DMA API
* @ION_NUM_HEAPS: helper for iterating over heaps, a bit mask
* is used to identify the heaps, so only 32
* total heap types are supported
*/
enum ion_heap_type {
ION_HEAP_TYPE_SYSTEM,
ION_HEAP_TYPE_SYSTEM_CONTIG,
ION_HEAP_TYPE_CARVEOUT,
ION_HEAP_TYPE_CHUNK,
ION_HEAP_TYPE_DMA,
ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always
are at the end of this enum */
ION_NUM_HEAPS = 16,
};
#define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG)
#define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT)
#define ION_HEAP_TYPE_DMA_MASK (1 << ION_HEAP_TYPE_DMA)
#define ION_NUM_HEAP_IDS sizeof(unsigned int) * 8
/**
* allocation flags - the lower 16 bits are used by core ion, the upper 16
* bits are reserved for use by the heaps themselves.
*/
#define ION_FLAG_CACHED 1 /* mappings of this buffer should be
cached, ion will do cache
maintenance when the buffer is
mapped for dma */
#define ION_FLAG_CACHED_NEEDS_SYNC 2 /* mappings of this buffer will created
at mmap time, if this is set
caches must be managed manually */
#define ION_FLAG_PRESERVE_KMAP 4 /* deprecated. ignored. */
#define ION_FLAG_NOZEROED 8 /* Allocated buffer is not initialized
with zero value and userspace is not
able to access the buffer
*/
/**
* DOC: Ion Userspace API
*
* create a client by opening /dev/ion
* most operations handled via following ioctls
*
*/
/**
* struct ion_allocation_data - metadata passed from userspace for allocations
* @len: size of the allocation
* @align: required alignment of the allocation
* @heap_id_mask: mask of heap ids to allocate from
* @flags: flags passed to heap
* @handle: pointer that will be populated with a cookie to use to
* refer to this allocation
*
* Provided by userspace as an argument to the ioctl
*/
struct ion_allocation_data {
size_t len;
size_t align;
unsigned int heap_id_mask;
unsigned int flags;
ion_user_handle_t handle;
};
/**
* struct ion_fd_data - metadata passed to/from userspace for a handle/fd pair
* @handle: a handle
* @fd: a file descriptor representing that handle
*
* For ION_IOC_SHARE or ION_IOC_MAP userspace populates the handle field with
* the handle returned from ion alloc, and the kernel returns the file
* descriptor to share or map in the fd field. For ION_IOC_IMPORT, userspace
* provides the file descriptor and the kernel returns the handle.
*/
struct ion_fd_data {
ion_user_handle_t handle;
int fd;
};
/**
* struct ion_handle_data - a handle passed to/from the kernel
* @handle: a handle
*/
struct ion_handle_data {
ion_user_handle_t handle;
};
/**
* struct ion_custom_data - metadata passed to/from userspace for a custom ioctl
* @cmd: the custom ioctl function to call
* @arg: additional data to pass to the custom ioctl, typically a user
* pointer to a predefined structure
*
* This works just like the regular cmd and arg fields of an ioctl.
*/
struct ion_custom_data {
unsigned int cmd;
unsigned long arg;
};
/**
* struct ion_preload_data - metadata for preload buffers
* @heap_id_mask: mask of heap ids to allocate from
* @len: size of the allocation
* @flags: flags passed to heap
* @count: number of buffers of the allocation
*
* Provided by userspace as an argument to the ioctl
*/
struct ion_preload_object {
size_t len;
unsigned int count;
};
struct ion_preload_data {
unsigned int heap_id_mask;
unsigned int flags;
unsigned int count;
struct ion_preload_object *obj;
};
#define ION_IOC_MAGIC 'I'
/**
* DOC: ION_IOC_ALLOC - allocate memory
*
* Takes an ion_allocation_data struct and returns it with the handle field
* populated with the opaque handle for the allocation.
*/
#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, \
struct ion_allocation_data)
/**
* DOC: ION_IOC_FREE - free memory
*
* Takes an ion_handle_data struct and frees the handle.
*/
#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data)
/**
* DOC: ION_IOC_MAP - get a file descriptor to mmap
*
* Takes an ion_fd_data struct with the handle field populated with a valid
* opaque handle. Returns the struct with the fd field set to a file
* descriptor open in the current address space. This file descriptor
* can then be used as an argument to mmap.
*/
#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data)
/**
* DOC: ION_IOC_SHARE - creates a file descriptor to use to share an allocation
*
* Takes an ion_fd_data struct with the handle field populated with a valid
* opaque handle. Returns the struct with the fd field set to a file
* descriptor open in the current address space. This file descriptor
* can then be passed to another process. The corresponding opaque handle can
* be retrieved via ION_IOC_IMPORT.
*/
#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data)
/**
* DOC: ION_IOC_IMPORT - imports a shared file descriptor
*
* Takes an ion_fd_data struct with the fd field populated with a valid file
* descriptor obtained from ION_IOC_SHARE and returns the struct with the handle
* filed set to the corresponding opaque handle.
*/
#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data)
/**
* DOC: ION_IOC_SYNC - syncs a shared file descriptors to memory
*
* Deprecated in favor of using the dma_buf api's correctly (syncing
* will happend automatically when the buffer is mapped to a device).
* If necessary should be used after touching a cached buffer from the cpu,
* this will make the buffer in memory coherent.
*/
#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data)
/**
* DOC: ION_IOC_PRELOAD_ALLOC - prefetches pages to page pool
*/
#define ION_IOC_PRELOAD_ALLOC _IOW(ION_IOC_MAGIC, 8, struct ion_preload_data)
/**
* DOC: ION_IOC_CUSTOM - call architecture specific ion ioctl
*
* Takes the argument of the architecture specific ioctl to call and
* passes appropriate userdata for that ioctl
*/
#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data)
//support for compat
#ifdef CONFIG_COMPAT
struct compat_ion_allocation_data {
compat_size_t len;
compat_size_t align;
compat_uint_t heap_id_mask;
compat_uint_t flags;
compat_int_t handle;
};
struct compat_ion_custom_data {
compat_uint_t cmd;
compat_ulong_t arg;
};
struct compat_ion_handle_data {
compat_int_t handle;
};
#define COMPAT_ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, \
struct compat_ion_allocation_data)
#define COMPAT_ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, \
struct compat_ion_handle_data)
#define COMPAT_ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, \
struct compat_ion_custom_data)
#endif
#endif /* _LINUX_ION_H */
|
//======================================================================
//
// tb_trng.v
// -----------
// Testbench for the trng module in the trng.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_trng();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// The DUT address map.
parameter TRNG_PREFIX = 4'h0;
parameter ENTROPY1_PREFIX = 4'h5;
parameter ENTROPY2_PREFIX = 4'h6;
parameter MIXER_PREFIX = 4'ha;
parameter CSPRNG_PREFIX = 4'hb;
parameter ADDR_TRNG_CTRL = 8'h10;
parameter TRNG_CTRL_ENABLE_BIT = 0;
parameter TRNG_CTRL_ENT0_ENABLE_BIT = 1;
parameter TRNG_CTRL_ENT1_ENABLE_BIT = 2;
parameter TRNG_CTRL_ENT2_ENABLE_BIT = 3;
parameter TRNG_CTRL_SEED_BIT = 8;
parameter ADDR_TRNG_STATUS = 8'h11;
parameter ADDR_TRNG_RND_DATA = 8'h20;
parameter ADDR_TRNG_RND_DATA_VALID = 8'h21;
parameter TRNG_RND_VALID_BIT = 0;
parameter ADDR_CSPRNG_CTRL = 8'h10;
parameter CSPRNG_CTRL_ENABLE_BIT = 0;
parameter CSPRNG_CTRL_SEED_BIT = 1;
parameter ADDR_CSPRNG_STATUS = 8'h11;
parameter CSPRNG_STATUS_RND_VALID_BIT = 0;
parameter ADDR_CSPRNG_NUM_ROUNDS = 8'h40;
parameter ADDR_CSPRNG_NUM_BLOCKS_LOW = 8'h41;
parameter ADDR_CSPRNG_NUM_BLOCKS_HIGH = 8'h42;
parameter ADDR_ENTROPY0_RAW = 8'h40;
parameter ADDR_ENTROPY0_STATS = 8'h41;
parameter ADDR_ENTROPY1_RAW = 8'h50;
parameter ADDR_ENTROPY1_STATS = 8'h51;
parameter ADDR_ENTROPY2_RAW = 8'h60;
parameter ADDR_ENTROPY2_STATS = 8'h61;
parameter ADDR_MIXER_CTRL = 8'h10;
parameter MIXER_CTRL_ENABLE_BIT = 0;
parameter MIXER_CTRL_RESTART_BIT = 1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [31 : 0] read_data;
reg tb_clk;
reg tb_reset_n;
reg tb_avalanche_noise;
reg tb_cs;
reg tb_we;
reg [11 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire [7 : 0] tb_debug;
reg tb_debug_update;
wire tb_error;
wire tb_security_error;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
trng dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.avalanche_noise(tb_avalanche_noise),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data),
.error(tb_error),
.debug(tb_debug),
.debug_update(tb_debug_update),
.security_error(tb_security_error)
);
//----------------------------------------------------------------
// Concurrent assignments.
//----------------------------------------------------------------
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(2 * CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_avalanche_noise = 0;
tb_cs = 0;
tb_we = 0;
tb_address = 12'h000;
tb_write_data = 32'h00000000;
tb_debug_update = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// tc1_gen_rnd()
//
// A simple first testcase that tries to make the DUT generate
// a number of random values.
//----------------------------------------------------------------
task tc1_gen_rnd;
reg [31 : 0] i;
begin
$display("*** Starting TC1: Generating random values from entropy.");
tb_debug_update = 1;
#(10 * CLK_PERIOD);
tb_debug_update = 0;
// Enable the csprng and the mixer
write_word({CSPRNG_PREFIX, ADDR_CSPRNG_CTRL}, 32'h00000001);
write_word({MIXER_PREFIX, ADDR_MIXER_CTRL}, 32'h00000001);
// We try to change number of blocks to a low value to force reseeding.
write_word({CSPRNG_PREFIX, ADDR_CSPRNG_NUM_BLOCKS_LOW}, 32'h00000002);
write_word({CSPRNG_PREFIX, ADDR_CSPRNG_NUM_BLOCKS_HIGH}, 32'h00000000);
#(100 * CLK_PERIOD);
i = 0;
while (i < 10000)
begin
$display("Reading rnd word %08x.", i);
i = i + 1;
read_word({CSPRNG_PREFIX, ADDR_TRNG_RND_DATA});
#(2 * CLK_PERIOD);
end
$display("*** TC1 done.");
end
endtask // tc1_gen_seeds
//----------------------------------------------------------------
// trng_test
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : trng_test
$display(" -= Testbench for TRNG started =-");
$display(" ===============================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
tc1_gen_rnd();
display_test_results();
$display("");
$display("*** TRNG simulation done. ***");
$finish;
end // trng_test
endmodule // tb_trng
//======================================================================
// EOF tb_trng.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_SYMBOL_V
`define SKY130_FD_SC_LP__BUF_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__buf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_SYMBOL_V
|
// UC Berkeley CS250
// Authors: Ryan Thornton ([email protected])
// Arya Reais-Parsi ([email protected])
//
// Based on the description in: Wenyi Feng, Jonathan Greene, and Alan
// Mishchenko. 2018. Improving FPGA Performance with a S44 LUT Structure. In
// Proceedings of the 2018 ACM/SIGDA International Symposium on
// Field-Programmable Gate Arrays (FPGA '18). Association for Computing
// Machinery, New York, NY, USA, 61–66.
// DOI:https://doi.org/10.1145/3174243.3174272
///////// HARD S44 LUT /////////
module lut_s44 #(
parameter CONFIG_WIDTH=8
) (
input [6:0] addr,
output out,
// Stream Style Configuration
input config_clk,
input config_en,
input [CONFIG_WIDTH-1:0] config_in,
output [CONFIG_WIDTH-1:0] config_out
);
wire intermediate;
wire [CONFIG_WIDTH-1:0] config_in2;
lut #(.INPUTS(4)) first_lut (
.addr(addr[6:3]),
.out(intermediate),
.config_clk(config_clk),
.config_en(config_en),
.config_in(config_in),
.config_out(config_in2)
);
lut #(.INPUTS(4)) second_lut (
.addr({intermediate, addr[2:0]}),
.out(out),
.config_clk(config_clk),
.config_en(config_en),
.config_in(config_in2),
.config_out(config_out)
);
endmodule
|
// STD 10-30-16
//
// Synchronous 1-port ram with byte masking
// Only one read or one write may be done per cycle.
//
module bsg_mem_1rw_sync_mask_write_byte
#(parameter `BSG_INV_PARAM(els_p )
,parameter `BSG_INV_PARAM(data_width_p )
,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
,parameter write_mask_width_lp = data_width_p>>3
)
(input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [data_width_p-1:0] data_i
,input [write_mask_width_lp-1:0] write_mask_i
,output [data_width_p-1:0] data_o
);
// TSMC 180 1024x32 Byte Mask
if ((els_p == 1024) & (data_width_p == 32))
begin : macro
wire [3:0] wen = {~(w_i & write_mask_i[3])
,~(w_i & write_mask_i[2])
,~(w_i & write_mask_i[1])
,~(w_i & write_mask_i[0])};
tsmc180_1rw_lg10_w32_m8_byte mem
(.Q (data_o)
,.CLK (clk_i)
,.CEN (~v_i)
,.WEN (wen)
,.A (addr_i)
,.D (data_i)
// 1=tristate output
,.OEN (1'b0)
);
end
// no hardened version found
else
begin : notmacro
bsg_mem_1rw_sync_mask_write_byte_synth
#(.els_p(els_p), .data_width_p(data_width_p))
synth (.*);
end
// synopsys translate_off
always_comb
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O221AI_FUNCTIONAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_FUNCTIONAL_V |
module brush_motor_driver(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [2:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input rsi_PWMRST_reset,
input csi_PWMCLK_clk,
//brush_moter_interface
output HX,
output HY
);
//Qsys controller
reg forward_back;
reg on_off;
reg [31:0] PWM_width;
reg [31:0] PWM_frequent;
reg [31:0] read_data;
assign avs_ctrl_readdata = read_data;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else if(avs_ctrl_write)
begin
case(avs_ctrl_address)
1: begin
if(avs_ctrl_byteenable[3]) PWM_frequent[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_frequent[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_frequent[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_frequent[7:0] <= avs_ctrl_writedata[7:0];
end
2: begin
if(avs_ctrl_byteenable[3]) PWM_width[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_width[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_width[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_width[7:0] <= avs_ctrl_writedata[7:0];
end
3: on_off <= avs_ctrl_writedata[0];
4: forward_back <= avs_ctrl_writedata[0];
default:;
endcase
end
else begin
case(avs_ctrl_address)
0: read_data <= 32'hEA680003;
1: read_data <= PWM_frequent;
2: read_data <= PWM_width;
3: read_data <= {31'b0,on_off};
4: read_data <= {31'b0,forward_back};
default: read_data <= 32'b0;
endcase
end
end
//PWM controller
reg [31:0] PWM;
reg PWM_out;
always @ (posedge csi_PWMCLK_clk or posedge rsi_PWMRST_reset)
begin
if(rsi_PWMRST_reset)
PWM <= 32'b0;
else
begin
PWM <= PWM + PWM_frequent;
PWM_out <=(PWM > PWM_width) ? 1'b0:1'b1;
end
end
//Output
wire X, Y;
assign X = forward_back?PWM_out:0;
assign Y = forward_back?0:PWM_out;
assign HX = on_off?X:0;
assign HY = on_off?Y:0;
endmodule |
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Main graphics rendering pipeline.
`include "collision.vh"
`include "memory_map.vh"
`include "registers.vh"
`include "sprite_registers.vh"
`include "tile_registers.vh"
`define LINE_BUF_ADDR_WIDTH 10
`define BYTE_WIDTH 8
`define SCREEN_WIDTH 640
`define SCREEN_HEIGHT 480
`define SCREEN_IMAGE_WIDTH (`SCREEN_WIDTH / 2)
`define SCREEN_IMAGE_HEIGHT (`SCREEN_HEIGHT / 2)
`define WORLD_WIDTH 512
`define WORLD_HEIGHT 512
// These are data bus widths for the the internal sprite and collision region
// buffers. They are not based on the external collision table definitions.
`define SPRITE_BUF_DATA_WIDTH (`BYTE_WIDTH + 1)
`define COLLISION_BUF_DATA_WIDTH (`BYTE_WIDTH + 1)
//`define TEST_COLLISION_BUFFER
//`define TEST_COLLISION_REGIONS_ONLY
//`define SPRITE_LAYER_LEVEL 3 // TODO: use registers to specify level.
//`define SPRITE_LAYER_LEVEL reg_array[`SPRITE_Z]
module Renderer(clk, reset, reg_values, tile_reg_values,
h_pos, v_pos, h_sync, v_sync,
pal_clk, pal_addr, pal_data,
map_clk, map_addr, map_data,
spr_clk, spr_addr, spr_data,
vram_en, vram_rd, vram_wr, vram_be,
vram_clk, vram_addr, vram_data,
coll_wr, coll_addr, coll_data,
rgb_out);
parameter RGB_COLOR_DEPTH=18;
localparam SCREEN_X_WIDTH=10;
localparam SCREEN_Y_WIDTH=10;
input clk; // System clock
input reset; // Reset
// Main register values
input [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values;
input [`NUM_TOTAL_TILE_REG_BITS-1:0] tile_reg_values;
input [SCREEN_X_WIDTH-1:0] h_pos; // Current screen refresh coordinates
input [SCREEN_Y_WIDTH-1:0] v_pos;
output h_sync, v_sync; // Sync signals
// Decode video scanout position.
wire h_blank, v_blank;
wire h_sync_in, v_sync_in;
wire [SCREEN_X_WIDTH-1:0] h_visible;
wire [SCREEN_X_WIDTH-1:0] v_visible;
DisplayTiming timing(.h_pos(h_pos), .v_pos(v_pos),
.h_sync(h_sync_in), .v_sync(v_sync_in),
.h_blank(h_blank), .v_blank(v_blank),
.h_visible_pos(h_visible), .v_visible_pos(v_visible));
wire h_blank_delayed;
wire v_blank_delayed;
// Delay the vertical sync output by two horizontal lines to match the delayed
// line buffer scanout.
DisplayTiming v_delay(.h_pos(h_pos),
.v_pos(v_pos - 2),
.v_sync(v_sync),
.v_blank(v_blank_delayed));
// Delay horizontal sync and blank by two clocks. This is to to match the
// scanout from the line buffer plus the registered RGB output.
CC_Delay #(.WIDTH(2), .DELAY(2)) h_delay(.clk(clk),
.reset(reset),
.d({h_sync_in, h_blank}),
.q({h_sync, h_blank_delayed}));
// Palette interface
output pal_clk;
output [`PAL_ADDR_WIDTH-1:0] pal_addr;
input [`PAL_DATA_WIDTH-1:0] pal_data;
// Palette interface
output map_clk;
output [`TILEMAP_ADDR_WIDTH-1:0] map_addr;
input [`TILEMAP_DATA_WIDTH-1:0] map_data;
// Sprite memory interface.
output spr_clk;
output [`SPRITE_ADDR_WIDTH-1:0] spr_addr;
input [`SPRITE_DATA_WIDTH-1:0] spr_data;
// Collision table interface.
output coll_wr;
output [`COLL_ADDR_WIDTH-1:0] coll_addr;
output [`COLL_DATA_WIDTH-1:0] coll_data;
// VRAM interface
output wire vram_en; // Chip enable (active low)
output wire vram_rd; // Read enable (active low)
output wire vram_wr; // Write enable (active low)
output wire [1:0] vram_be; // Byte enable (active low)
output vram_clk;
output [`VRAM_ADDR_WIDTH-1:0] vram_addr; // Address bus
input [`VRAM_DATA_WIDTH-1:0] vram_data; // Data bus
output [RGB_COLOR_DEPTH-1:0] rgb_out; // Color output.
assign vram_wr = 1'b0;
assign vram_rd = 1'b1; // TODO: switch these off when not rendering.
assign vram_en = 1'b1;
assign vram_be = 2'b11;
// Main register values.
wire [`REG_DATA_WIDTH-1:0] reg_array [`NUM_MAIN_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : REGS
assign reg_array[i] = reg_values[`REG_DATA_WIDTH * (i + 1) - 1:
`REG_DATA_WIDTH * i];
end
endgenerate
// Tile register logic.
wire [`REG_DATA_WIDTH-1:0] tile_ctrl0;
wire [`REG_DATA_WIDTH-1:0] tile_ctrl1;
wire [`REG_DATA_WIDTH-1:0] tile_nop_value;
wire [`REG_DATA_WIDTH-1:0] tile_color_key;
wire [`VRAM_DATA_WIDTH:0] tile_data_offset;
wire [`REG_DATA_WIDTH-1:0] tile_offset_x;
wire [`REG_DATA_WIDTH-1:0] tile_offset_y;
wire tile_enable_flip;
wire tile_enable_8_bit;
TileRegDecoder tile_reg_decoder(
.current_layer(current_tile_layer),
.reg_values(tile_reg_values),
.ctrl0(tile_ctrl0),
.enable_8bit(tile_enable_8_bit),
.enable_flip(tile_enable_flip),
.ctrl1(tile_ctrl1),
.data_offset(tile_data_offset),
.nop_value(tile_nop_value),
.color_key(tile_color_key),
.offset_x(tile_offset_x),
.offset_y(tile_offset_y));
// Sprite register decoding.
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl0;
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl1;
wire [`VRAM_ADDR_WIDTH:0] sprite_data_offset;
wire [`REG_DATA_WIDTH-1:0] sprite_color_key;
wire [`REG_DATA_WIDTH-1:0] sprite_offset_x;
wire [`REG_DATA_WIDTH-1:0] sprite_offset_y;
wire sprite_enabled;
wire sprite_enable_scroll;
wire sprite_enable_transp;
wire sprite_enable_alpha;
wire sprite_enable_color;
wire sprite_flip_x;
wire sprite_flip_y;
wire sprite_flip_xy;
wire [8:0] sprite_pal_index;
wire [8:0] sprite_width;
wire [8:0] sprite_height;
SpriteRegDecoder sprite_reg_decoder(
.reg_values(sprite_reg_values),
.enabled(sprite_enabled),
.enable_scroll(sprite_enable_scroll),
.enable_transp(sprite_enable_transp),
.enable_alpha(sprite_enable_alpha),
.enable_color(sprite_enable_color),
.flip_x(sprite_flip_x),
.flip_y(sprite_flip_y),
.flip_xy(sprite_flip_xy),
.palette(sprite_pal_index),
.width(sprite_width),
.height(sprite_height),
.ctrl0(sprite_ctrl0),
.ctrl1(sprite_ctrl1),
.data_offset(sprite_data_offset),
.color_key(sprite_color_key),
.offset_x(sprite_offset_x),
.offset_y(sprite_offset_y));
// The dimensions of the sprite as it is shown on the screen. Takes diagonal
// flipping into account.
wire [8:0] sprite_render_width = sprite_flip_xy ? sprite_height
: sprite_width;
wire [8:0] sprite_render_height = sprite_flip_xy ? sprite_width
: sprite_height;
// Compute the offset of the sprite on the screen.
// If sprite scrolling is enabled, then the world scroll offset is taken into
// account; the sprite's offset is considered to be in world coordinates.
// if sprite scrolling is disabled, then the sprite's offset is considered to
// be in screen coordinates.
wire [SCREEN_X_WIDTH-1:0] sprite_screen_offset_x =
sprite_enable_scroll ? sprite_offset_x - reg_array[`SCROLL_X]
: sprite_offset_x;
wire [SCREEN_Y_WIDTH-1:0] sprite_screen_offset_y =
sprite_enable_scroll ? sprite_offset_y - reg_array[`SCROLL_Y]
: sprite_offset_y;
wire [SCREEN_Y_WIDTH-2:0] sprite_top = sprite_screen_offset_y;
wire [SCREEN_Y_WIDTH-2:0] sprite_bottom =
sprite_screen_offset_y + sprite_render_height;
// TODO: complete the rendering pipeline.
// For now, this setup uses contents of the tilemap RAM to look up palette
// colors. The palette color goes straight to the output.
// TODO: create global functions or tasks for computing screen coordinates
// from VGA counter values.
wire [SCREEN_X_WIDTH-2:0] screen_x = h_visible / 2;
wire [SCREEN_Y_WIDTH-2:0] screen_y = v_visible / 2;
// The y-coordinate in world space of the line currently being rendered.
wire [SCREEN_Y_WIDTH-2:0] world_y = screen_y + reg_array[`SCROLL_Y];
assign pal_clk = clk;
assign map_clk = clk;
assign vram_clk = clk;
assign spr_clk = ~clk;
// The logic for drawing to the line buffer.
`define STATE_IDLE 0
`define STATE_DECIDE 1
`define STATE_DRAW_LAYER 2
`define STATE_READ_SPRITE 3
`define STATE_DRAW_SPRITE 4
reg [3:0] render_state;
reg [`LINE_BUF_ADDR_WIDTH-2:0] render_x;
// For keeping track of what's been rendered.
reg [4:0] num_layers_drawn;
reg [8:0] num_sprites_drawn;
reg [15:0] num_texels_drawn;
reg [8:0] num_sprite_words_read;
wire [4:0] current_tile_layer = num_layers_drawn;
wire [`BYTE_WIDTH-1:0] current_sprite = num_sprites_drawn[`BYTE_WIDTH-1:0];
assign spr_addr = {current_sprite, num_sprite_words_read[0]};
reg [`NUM_SPRITE_REGS * `REG_DATA_WIDTH - 1 : 0] sprite_reg_values;
always @ (posedge clk or posedge reset) begin
if (reset) begin
render_state <= `STATE_IDLE;
sprite_reg_values <= 0;
end else begin
case (render_state)
`STATE_IDLE:
begin
// Start drawing at the start of an even numbered on-screen scanline.
if (h_pos == 0 && v_blank == 0 && v_visible[0] == 0) begin
render_state <= `STATE_DECIDE;
num_layers_drawn <= 0;
num_sprites_drawn <= 0;
num_texels_drawn <= 0;
num_sprite_words_read <= 0;
end
end
`STATE_DECIDE:
begin
// TODO: eventually this state will need to be removed for maximum
// efficiency. Deciding what to draw next should be immediate,
// without having to go through an intermediate step.
// Draw all layers. The sprite layer's order relative to the tile
// layers is hardcoded.
// TODO: Make sprite layer more dynamic.
//if (num_layers_drawn < `SPRITE_LAYER_LEVEL ||
if (num_layers_drawn < reg_array[`SPRITE_Z] ||
(num_layers_drawn < `NUM_TILE_LAYERS && num_sprites_drawn > 0))
begin
if (tile_ctrl0[`TILE_LAYER_ENABLED]) begin
render_state <= `STATE_DRAW_LAYER;
render_x <= 0;
end
// Skip to the next layer if the current one is disabled.
else
num_layers_drawn <= num_layers_drawn + 1;
end
// Draw sprites if all layers below it.
//else if ((num_layers_drawn == `SPRITE_LAYER_LEVEL ||
else if ((num_layers_drawn == reg_array[`SPRITE_Z] ||
num_layers_drawn == `NUM_TILE_LAYERS) &&
num_sprites_drawn < `NUM_SPRITES)
begin
render_state <= `STATE_READ_SPRITE;
num_sprite_words_read <= 0;
end
// All done.
else
render_state <= `STATE_IDLE;
end
`STATE_DRAW_LAYER:
begin
// Stop drawing at the end of an odd numbered on-screen scanline.
// TODO: create define for '800', the max 640x480 horizontal count.
if (h_pos + 1 == 800 && v_visible[0] == 1) begin
render_state <= `STATE_IDLE;
end else if (render_x + 1 >= `SCREEN_IMAGE_WIDTH) begin
// Stop drawing if the screen has been drawn.
// TODO: direct drawing based on tile coordinates rather than screen
// coordinates.
render_state <= `STATE_DECIDE;
num_layers_drawn <= num_layers_drawn + 1;
end else begin
render_x <= render_x + 1;
end
end
`STATE_READ_SPRITE:
begin
if (num_sprites_drawn >= `NUM_SPRITES) begin
render_state <= `STATE_DECIDE;
end else if (num_sprite_words_read < 2) begin
// Sequentially read in all the sprite regs over two clock cycles.
if (num_sprite_words_read == 0)
sprite_reg_values[`SPRITE_DATA_WIDTH-1:0] <= spr_data;
else if (num_sprite_words_read == 1)
sprite_reg_values[`SPRITE_DATA_WIDTH*2-1:`SPRITE_DATA_WIDTH] <=
spr_data;
num_sprite_words_read <= num_sprite_words_read + 1;
end else begin
// Skip sprite if it is:
// 1. not enabled
// 2. not on the current line (two cases):
// a. sprite does not cross y-boundary of the world
// b. sprite wraps around y-boundary of the world
if (!sprite_enabled || // Condition #1
(sprite_top <= sprite_bottom && // Condition #2a
(screen_y < sprite_top || screen_y >= sprite_bottom)) ||
(sprite_top >= sprite_bottom && // Condition #2b
(screen_y >= sprite_bottom && screen_y < sprite_top))
// TODO: Handle horizontal boundary checking as well.
) begin
num_sprite_words_read <= 0;
num_sprites_drawn <= num_sprites_drawn + 1;
end else begin
// TODO: do not render parts of sprite that are not visible
// (either to the left or to the right of the visible area).
render_state <= `STATE_DRAW_SPRITE;
render_x <= 0;
end
end
end
`STATE_DRAW_SPRITE:
begin
if (render_x + 1 >= sprite_render_width) begin
render_state <= `STATE_READ_SPRITE;
num_sprites_drawn <= num_sprites_drawn + 1;
num_sprite_words_read <= 0;
end else begin
render_x <= render_x + 1;
end
end
endcase
end
end
wire render_tiles = (render_state == `STATE_DRAW_LAYER);
wire render_sprite = (render_state == `STATE_DRAW_SPRITE);
reg render_tiles_delayed;
reg render_sprite_delayed;
always @ (posedge clk) begin
render_tiles_delayed <= render_tiles;
render_sprite_delayed <= render_sprite;
end
wire [`LINE_BUF_ADDR_WIDTH-2:0] tile_render_x = render_x;
wire [`LINE_BUF_ADDR_WIDTH-2:0] tile_render_y =
screen_y + reg_array[`SCROLL_Y] - tile_offset_y;
wire [`LINE_BUF_ADDR_WIDTH-2:0] sprite_render_x =
(render_x + sprite_screen_offset_x) % `WORLD_WIDTH;
// Sprite rendering pipeline.
// Location within the sprite to render from.
reg [15:0] sprite_x;
reg [15:0] sprite_y;
// Location within the on-screen sprite currently being drawn.
// Be sure to handle wraparound when |screen_y| < |sprite_screen_offset_y|.
wire [15:0] sprite_render_y =
(screen_y - sprite_screen_offset_y) % `WORLD_HEIGHT;
wire [15:0] sprite_flipped_x = sprite_render_width - render_x - 1;
wire [15:0] sprite_flipped_y = sprite_render_height - sprite_render_y - 1;
// Start location of sprite data in VRAM.
reg [`VRAM_ADDR_WIDTH-1:0] sprite_vram_offset;
// Delay by one clock to match the timing of the tile pipeline. There is
// no tilemap to read.
always @ (posedge clk) begin
if (~sprite_flip_xy) begin
sprite_x <= sprite_flip_x ? sprite_flipped_x : render_x;
sprite_y <= sprite_flip_y ? sprite_flipped_y : sprite_render_y;
end else begin
sprite_x <= sprite_flip_x ? sprite_flipped_y : sprite_render_y;
sprite_y <= sprite_flip_y ? sprite_flipped_x : render_x;
end
sprite_vram_offset <= sprite_data_offset / 2;
end
// This assumes that the sprite data is not aligned to any power of two.
wire [15:0] sprite_pixel_offset = sprite_y * sprite_width + sprite_x;
// Tile rendering pipeline.
// Handle x-scrolling.
wire [`LINE_BUF_ADDR_WIDTH-2:0] render_x_world =
tile_render_x + reg_array[`SCROLL_X] - tile_offset_x;
wire tile_enable_8x8 = tile_ctrl0[`TILE_ENABLE_8x8];
reg [4:0] map_x;
reg [5:0] map_y;
reg [3:0] tile_x;
reg [3:0] tile_y;
always @ (*) begin
if (tile_enable_8x8) begin
if (tile_enable_8_bit) begin
// If reading tile map as 8-bits, the tile map is twice as wide.
map_x <= render_x_world[7:3];
map_y <= {tile_render_y[8:3], render_x_world[8]};
end else begin
map_x <= render_x_world[8:3];
map_y <= tile_render_y[8:3];
end
tile_x <= render_x_world[2:0];
tile_y <= tile_render_y[2:0];
end else begin
map_x <= render_x_world[8:4];
map_y <= tile_render_y[8:4];
tile_x <= render_x_world[3:0];
tile_y <= tile_render_y[3:0];
end
end
// Screen location -> map address
assign map_addr =
tile_enable_8_bit ? {current_tile_layer, map_y[5:0], map_x[4:1]}
: {current_tile_layer, map_y[4:0], map_x[4:0]};
reg map_data_byte_select;
always @ (posedge clk)
map_data_byte_select <= map_x[0];
// Handle tile flip bits, if flipping is enabled.
// If not, all bits of the tile map data are used for the tile value.
wire tile_flip_x = tile_enable_flip & map_data[`TILE_FLIP_X_BIT];
wire tile_flip_y = tile_enable_flip & map_data[`TILE_FLIP_Y_BIT];
wire tile_flip_xy = tile_enable_flip & map_data[`TILE_FLIP_XY_BIT];
wire [`TILEMAP_DATA_WIDTH-1:0] tile_value =
tile_enable_8_bit
? (map_data_byte_select
? map_data[`TILEMAP_DATA_WIDTH-1:`TILEMAP_DATA_WIDTH/2]
: map_data[`TILEMAP_DATA_WIDTH/2-1:0])
: (tile_enable_flip ? (~`TILE_FLIP_BITS_MASK & map_data)
: map_data);
reg [3:0] tile_x_reg;
reg [3:0] tile_y_reg;
always @ (posedge clk) begin
tile_x_reg <= tile_x;
tile_y_reg <= tile_y;
end
reg [3:0] tile_x_flipped;
reg [3:0] tile_y_flipped;
always @ (*)
begin
if (tile_flip_xy) begin
tile_x_flipped <= tile_flip_y ? ~tile_y_reg : tile_y_reg;
tile_y_flipped <= tile_flip_x ? ~tile_x_reg : tile_x_reg;
end else begin
tile_x_flipped <= tile_flip_x ? ~tile_x_reg : tile_x_reg;
tile_y_flipped <= tile_flip_y ? ~tile_y_reg : tile_y_reg;
end
end
// Map data -> VRAM address
reg [`VRAM_ADDR_WIDTH-1:0] tile_vram_offset;
always @ (posedge clk)
tile_vram_offset <= tile_data_offset / 2;
wire [`VRAM_ADDR_WIDTH-1:0] tile_vram_addr =
tile_enable_8x8 ? {tile_value, tile_y_flipped[2:0], tile_x_flipped[2:1]}
: {tile_value, tile_y_flipped[3:0], tile_x_flipped[3:1]} +
tile_vram_offset;
wire [`VRAM_ADDR_WIDTH-1:0] sprite_vram_addr =
sprite_pixel_offset[15:1] + sprite_vram_offset;
assign vram_addr = render_tiles_delayed ? tile_vram_addr : sprite_vram_addr;
wire vram_byte_select;
CC_Delay #(.WIDTH(1), .DELAY(2))
vram_byte_select_delay(
.clk(clk),
.reset(reset),
.d(render_tiles_delayed ? tile_x_flipped[0] : sprite_pixel_offset[0]),
.q(vram_byte_select));
// Delay the line buffer write address by five cycles due to the need for data
// to pass through the rendering pipeline.
// The five-clock delay is broken down as follows:
// - Tile map RAM access
// - Registered VRAM address
// - Registered VRAM data
// TODO: In my current setup, VRAM requires its ports to be registered.
// My setup has 10cm wires between the FPGA and VRAM. In a production
// system, there should be board traces instead of wires, and the traces
// should be shorter. That might eliminate the need for VRAM ports to be
// registered.
// - Palette access.
// - Something else in the pipeline that I can't account for. But it works if
// I use an extra delay.
`define RENDER_DELAY 5
// VRAM data -> palette address
wire [`TILE_PALETTE_WIDTH-1:0] tile_pal_index =
tile_ctrl0[`TILE_PALETTE_END:`TILE_PALETTE_START];
wire [`TILE_PALETTE_WIDTH-1:0] pal_index_delayed;
CC_Delay #(.WIDTH(`TILE_PALETTE_WIDTH), .DELAY(`RENDER_DELAY-2))
pal_index_delay(.clk(clk),
.reset(reset),
.d(render_tiles ? tile_pal_index : sprite_pal_index),
.q(pal_index_delayed));
// Prepend the palette index to the palette address.
assign pal_addr =
{ pal_index_delayed,
(vram_byte_select == 0) ? vram_data[7:0] : vram_data[15:8] };
reg [RGB_COLOR_DEPTH-1:0] rgb_out;
// Palette data -> Line buffer
// Interface A: writing to the line buffer.
wire [`LINE_BUF_ADDR_WIDTH-1:0] buf_addr;
CC_Delay #(.WIDTH(`LINE_BUF_ADDR_WIDTH), .DELAY(`RENDER_DELAY))
buf_addr_delay(
.clk(clk),
.reset(reset),
.d({screen_y[0],
render_tiles_delayed ? tile_render_x : sprite_render_x}),
.q(buf_addr));
wire [3:0] render_state_delayed;
CC_Delay #(.WIDTH(3), .DELAY(`RENDER_DELAY))
render_state_delay(.clk(clk),
.reset(reset),
.d(render_state),
.q(render_state_delayed));
// Delayed sprite values.
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl0_delayed;
wire [`REG_DATA_WIDTH-1:0] sprite_color_key_delayed;
wire [`BYTE_WIDTH-1:0] current_sprite_delayed;
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
sprite_ctrl0_delay(.clk(clk),
.reset(reset),
.d(sprite_ctrl0),
.q(sprite_ctrl0_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
sprite_color_key_delay(.clk(clk),
.reset(reset),
.d(sprite_color_key),
.q(sprite_color_key_delayed));
CC_Delay #(.WIDTH(`BYTE_WIDTH), .DELAY(`RENDER_DELAY))
current_sprite_delay(.clk(clk),
.reset(reset),
.d(current_sprite),
.q(current_sprite_delayed));
// Delayed tile values.
wire [`TILEMAP_DATA_WIDTH-1:0] tile_value_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_ctrl0_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_nop_value_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_color_key_delayed;
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_enable_nop_delay(.clk(clk),
.reset(reset),
.d(tile_ctrl0),
.q(tile_ctrl0_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_nop_value_delay(.clk(clk),
.reset(reset),
.d(tile_nop_value[`TILEMAP_DATA_WIDTH-1:0]),
.q(tile_nop_value_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_color_key_delay(.clk(clk),
.reset(reset),
.d(tile_color_key),
.q(tile_color_key_delayed));
CC_Delay #(.WIDTH(`TILEMAP_DATA_WIDTH), .DELAY(`RENDER_DELAY-1))
tile_value_delay(.clk(clk),
.reset(reset),
.d(map_data),
.q(tile_value_delayed));
// Delayed VRAM output.
wire [7:0] pixel_value_delayed;
CC_Delay #(.WIDTH(8), .DELAY(2))
pixel_value_delay(.clk(clk),
.reset(reset),
.d(pal_addr[7:0]),
.q(pixel_value_delayed));
wire tile_buf_wr = (render_state_delayed == `STATE_DRAW_LAYER) &&
!(tile_value_delayed == tile_nop_value_delayed &&
tile_ctrl0_delayed[`TILE_ENABLE_NOP]) &&
!(pixel_value_delayed == tile_color_key_delayed &&
tile_ctrl0_delayed[`TILE_ENABLE_TRANSP]);
wire sprite_buf_wr = (render_state_delayed == `STATE_DRAW_SPRITE) &&
!(pixel_value_delayed == sprite_color_key_delayed &&
sprite_ctrl0_delayed[`SPRITE_ENABLE_TRANSP]);
// The Palette memory module happens to be good for a line drawing buffer,
// since its contents are of the same color format.
Palette #(.NUM_CHANNELS(`NUM_PAL_CHANNELS)) line_buffer(
.clk_a(clk),
.wr_a(tile_buf_wr | sprite_buf_wr),
.rd_a(0),
.addr_a(buf_addr),
.data_in_a(pal_data),
.byte_en_a(3'b111),
.clk_b(clk),
.wr_b(h_visible[0] & v_visible[0]), // Clear the old data for a new line.
.rd_b(~(h_blank | v_blank_delayed)),
.addr_b(buf_scanout_addr),
.data_in_b(0),
.data_out_b(buf_scanout_data)
);
// Sprite index buffer, for detecting collisions between sprites.
// Writing sprite data to it parallels drawing sprites to the line buffer.
wire [`SPRITE_BUF_DATA_WIDTH-1:0] sprite_buffer_out;
collision_buffer_1Kx9 sprite_buffer(
.clock(clk),
// Interface A.
.wren_a(sprite_buf_wr),
.address_a(buf_addr),
// The uppermost bit indicates a valid sprite pixel.
.data_a({1'b1, current_sprite_delayed}),
// Break down the output into separate fields.
.q_a({existing_sprite_pixel_valid, existing_sprite_index}),
// Interface B.
.wren_b(h_visible[0] & v_visible[0]), // Clear old data for a new line.
.address_b(buf_scanout_addr),
.data_b(0),
.q_b(sprite_buffer_out),
);
// The read value is valid one clock after the write value. Use a delayed
// write value to compare the two.
reg sprite_buf_wr_delayed;
reg [`BYTE_WIDTH-1:0] new_sprite_index;
reg [`LINE_BUF_ADDR_WIDTH-1:0] buf_addr_delayed;
always @ (posedge clk) begin
sprite_buf_wr_delayed <= sprite_buf_wr;
new_sprite_index <= current_sprite_delayed;
buf_addr_delayed <= buf_addr;
end
wire existing_sprite_pixel_valid;
wire [`BYTE_WIDTH-1:0] existing_sprite_index;
// A collision is detected if there's an existing sprite pixel and it doesn't
// come from the same sprite as the new one.
// TODO: The screen goes black if the logic for comparing old vs new sprite
// is used. Figure out why.
// TODO: Implement actual collision table.
wire sprite_collision = sprite_buf_wr_delayed & existing_sprite_pixel_valid;
assign coll_wr = sprite_collision;
assign coll_addr = new_sprite_index;
assign coll_data = existing_sprite_index;
// This buffer stores the pixels where collision happened. It is used only
// for testing. The output is only used when TEST_COLLISION_REGIONS_ONLY is
// defined.
wire [`COLLISION_BUF_DATA_WIDTH-1:0] collision_buffer_out;
collision_buffer_1Kx9 collision_test_buffer(
.clock(clk),
// Write to the collision buffer only when there's a collision.
.wren_a(sprite_collision),
// Interface A.
// Write to the buffer position that corresponds to the current pixel
// being drawn. Thus the collision buffer contains an image of where the
// collisions are.
.address_a(buf_addr_delayed),
// The uppermost bit indicates a valid sprite pixel.
.data_a({`COLLISION_BUF_DATA_WIDTH{1'b1}}),
// Interface B.
.wren_b(h_visible[0] & v_visible[0]), // Clear old data for a new line.
.address_b(buf_scanout_addr),
.data_b(0),
.q_b(collision_buffer_out),
);
// Line buffer -> VGA output
// Interface B: reading from the line buffer
wire [`LINE_BUF_ADDR_WIDTH-1:0] buf_scanout_addr;
// Make sure to scan out from the part of the buffer that was rendered to
// the previous line.
assign buf_scanout_addr = {~screen_y[0], screen_x};
wire [`PAL_DATA_WIDTH-1:0] buf_scanout_data;
reg [7:0] buf_scanout_red;
reg [7:0] buf_scanout_green;
reg [7:0] buf_scanout_blue;
// Latch the line buffer output. This is needed to preserve the line buffer
// output after it gets cleared for a new line.
// TODO: I got this to work properly after a bit of trial and error. In the
// future, this may need to be revisited to get a better understanding of how
// it works.
always @ (negedge clk) begin
`ifndef TEST_COLLISION_BUFFER
buf_scanout_red = buf_scanout_data[7:0];
buf_scanout_green = buf_scanout_data[15:8];
buf_scanout_blue = buf_scanout_data[23:16];
`else
`ifndef TEST_COLLISION_REGIONS_ONLY
// Test the sprite buffer.
`define BUFFER_TEST_BIT sprite_buffer_out[`SPRITE_BUF_DATA_WIDTH-1]
`else
// Test the collision buffer.
`define BUFFER_TEST_BIT collision_buffer_out[`COLL_DATA_WIDTH-1]
`endif // defined(TEST_COLLISION_REGIONS_ONLY)
// For testing the collision buffer, show the buffer contents as part of the
// scanout. Regions with sprite pixels are shown as grey.
{buf_scanout_red, buf_scanout_green, buf_scanout_blue} =
`BUFFER_TEST_BIT ? 'h7f7f7f : {buf_scanout_data[7:0],
buf_scanout_data[15:8],
buf_scanout_data[23:16]};
`endif // defined(TEST_COLLISION_BUFFER)
end
always @ (negedge clk) begin
if (h_blank_delayed | v_blank_delayed) begin
rgb_out <= {RGB_COLOR_DEPTH {1'b0}};
end else if (~h_visible[0]) begin
rgb_out <= {buf_scanout_blue[7:2],
buf_scanout_green[7:2],
buf_scanout_red[7:2]};
end
end
endmodule
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100 MHz
* Reset: Push button, active low
*/
input wire clk_sys_100m_p,
input wire cpu_resetn,
/*
* GPIO
*/
output wire [3:0] user_led,
/*
* Ethernet: QSFP28
*/
output wire [3:0] qsfp0_tx_p,
input wire [3:0] qsfp0_rx_p,
input wire refclk_qsfp0_p,
output wire qsfp0_modsel_l,
output wire qsfp0_reset_l,
input wire qsfp0_modprs_l,
output wire qsfp0_lpmode,
input wire qsfp0_int_l,
output wire [3:0] qsfp1_tx_p,
input wire [3:0] qsfp1_rx_p,
input wire refclk_qsfp1_p,
output wire qsfp1_modsel_l,
output wire qsfp1_reset_l,
input wire qsfp1_modprs_l,
output wire qsfp1_lpmode,
input wire qsfp1_int_l
);
// Clock and reset
wire ninit_done;
reset_release reset_release_inst (
.ninit_done (ninit_done)
);
wire clk_125mhz_int;
wire rst_125mhz_int;
wire iopll_locked;
iopll iopll_inst (
.rst(~cpu_resetn || ninit_done),
.refclk(clk_sys_100m_p),
.locked(iopll_locked),
.outclk_0(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~iopll_locked),
.out(rst_125mhz_int)
);
// XGMII 10G PHY
assign qsfp0_modsel_l = 1'b0;
assign qsfp0_reset_l = 1'b1;
assign qsfp0_lpmode = 1'b0;
wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [63:0] qsfp0_txd_1_int;
wire [7:0] qsfp0_txc_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [63:0] qsfp0_rxd_1_int;
wire [7:0] qsfp0_rxc_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [63:0] qsfp0_txd_2_int;
wire [7:0] qsfp0_txc_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [63:0] qsfp0_rxd_2_int;
wire [7:0] qsfp0_rxc_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [63:0] qsfp0_txd_3_int;
wire [7:0] qsfp0_txc_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [63:0] qsfp0_rxd_3_int;
wire [7:0] qsfp0_rxc_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [63:0] qsfp0_txd_4_int;
wire [7:0] qsfp0_txc_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [63:0] qsfp0_rxd_4_int;
wire [7:0] qsfp0_rxc_4_int;
assign qsfp1_modsel_l = 1'b0;
assign qsfp1_reset_l = 1'b1;
assign qsfp1_lpmode = 1'b0;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [63:0] qsfp1_txd_1_int;
wire [7:0] qsfp1_txc_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [63:0] qsfp1_rxd_1_int;
wire [7:0] qsfp1_rxc_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [63:0] qsfp1_txd_2_int;
wire [7:0] qsfp1_txc_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [63:0] qsfp1_rxd_2_int;
wire [7:0] qsfp1_rxc_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [63:0] qsfp1_txd_3_int;
wire [7:0] qsfp1_txc_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [63:0] qsfp1_rxd_3_int;
wire [7:0] qsfp1_rxc_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [63:0] qsfp1_txd_4_int;
wire [7:0] qsfp1_txc_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [63:0] qsfp1_rxd_4_int;
wire [7:0] qsfp1_rxc_4_int;
assign clk_156mhz_int = qsfp0_tx_clk_1_int;
assign rst_156mhz_int = qsfp0_tx_rst_1_int;
wire qsfp0_rx_block_lock_1;
wire qsfp0_rx_block_lock_2;
wire qsfp0_rx_block_lock_3;
wire qsfp0_rx_block_lock_4;
wire qsfp1_rx_block_lock_1;
wire qsfp1_rx_block_lock_2;
wire qsfp1_rx_block_lock_3;
wire qsfp1_rx_block_lock_4;
eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
.xcvr_ref_clk(refclk_qsfp0_p),
.xcvr_tx_serial_data(qsfp0_tx_p),
.xcvr_rx_serial_data(qsfp0_rx_p),
.phy_1_tx_clk(qsfp0_tx_clk_1_int),
.phy_1_tx_rst(qsfp0_tx_rst_1_int),
.phy_1_xgmii_txd(qsfp0_txd_1_int),
.phy_1_xgmii_txc(qsfp0_txc_1_int),
.phy_1_rx_clk(qsfp0_rx_clk_1_int),
.phy_1_rx_rst(qsfp0_rx_rst_1_int),
.phy_1_xgmii_rxd(qsfp0_rxd_1_int),
.phy_1_xgmii_rxc(qsfp0_rxc_1_int),
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
.phy_2_xgmii_txd(qsfp0_txd_2_int),
.phy_2_xgmii_txc(qsfp0_txc_2_int),
.phy_2_rx_clk(qsfp0_rx_clk_2_int),
.phy_2_rx_rst(qsfp0_rx_rst_2_int),
.phy_2_xgmii_rxd(qsfp0_rxd_2_int),
.phy_2_xgmii_rxc(qsfp0_rxc_2_int),
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
.phy_3_xgmii_txd(qsfp0_txd_3_int),
.phy_3_xgmii_txc(qsfp0_txc_3_int),
.phy_3_rx_clk(qsfp0_rx_clk_3_int),
.phy_3_rx_rst(qsfp0_rx_rst_3_int),
.phy_3_xgmii_rxd(qsfp0_rxd_3_int),
.phy_3_xgmii_rxc(qsfp0_rxc_3_int),
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
.phy_4_xgmii_txd(qsfp0_txd_4_int),
.phy_4_xgmii_txc(qsfp0_txc_4_int),
.phy_4_rx_clk(qsfp0_rx_clk_4_int),
.phy_4_rx_rst(qsfp0_rx_rst_4_int),
.phy_4_xgmii_rxd(qsfp0_rxd_4_int),
.phy_4_xgmii_rxc(qsfp0_rxc_4_int),
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber()
);
eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
.xcvr_ref_clk(refclk_qsfp1_p),
.xcvr_tx_serial_data(qsfp1_tx_p),
.xcvr_rx_serial_data(qsfp1_rx_p),
.phy_1_tx_clk(qsfp1_tx_clk_1_int),
.phy_1_tx_rst(qsfp1_tx_rst_1_int),
.phy_1_xgmii_txd(qsfp1_txd_1_int),
.phy_1_xgmii_txc(qsfp1_txc_1_int),
.phy_1_rx_clk(qsfp1_rx_clk_1_int),
.phy_1_rx_rst(qsfp1_rx_rst_1_int),
.phy_1_xgmii_rxd(qsfp1_rxd_1_int),
.phy_1_xgmii_rxc(qsfp1_rxc_1_int),
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
.phy_2_xgmii_txd(qsfp1_txd_2_int),
.phy_2_xgmii_txc(qsfp1_txc_2_int),
.phy_2_rx_clk(qsfp1_rx_clk_2_int),
.phy_2_rx_rst(qsfp1_rx_rst_2_int),
.phy_2_xgmii_rxd(qsfp1_rxd_2_int),
.phy_2_xgmii_rxc(qsfp1_rxc_2_int),
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
.phy_3_xgmii_txd(qsfp1_txd_3_int),
.phy_3_xgmii_txc(qsfp1_txc_3_int),
.phy_3_rx_clk(qsfp1_rx_clk_3_int),
.phy_3_rx_rst(qsfp1_rx_rst_3_int),
.phy_3_xgmii_rxd(qsfp1_rxd_3_int),
.phy_3_xgmii_rxc(qsfp1_rxc_3_int),
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
.phy_4_xgmii_txd(qsfp1_txd_4_int),
.phy_4_xgmii_txc(qsfp1_txc_4_int),
.phy_4_rx_clk(qsfp1_rx_clk_4_int),
.phy_4_rx_rst(qsfp1_rx_rst_4_int),
.phy_4_xgmii_rxd(qsfp1_rxd_4_int),
.phy_4_xgmii_rxc(qsfp1_rxc_4_int),
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber()
);
fpga_core
core_inst (
/*
* Clock: 125 MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.user_led(user_led),
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_4_V
`define SKY130_FD_SC_HD__SEDFXTP_4_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxtp_4 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxtp_4 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCIN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__FAHCIN_PP_BLACKBOX_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCIN_PP_BLACKBOX_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module norflash32 #(
parameter adr_width = 21 /* in 32-bit words */
) (
input sys_clk,
input sys_rst,
input [31:0] wb_adr_i,
output reg [31:0] wb_dat_o,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
/* 32-bit granularity */
output reg [adr_width-1:0] flash_adr,
input [31:0] flash_d
);
always @(posedge sys_clk) begin
/* Use IOB registers to prevent glitches on address lines */
if(wb_cyc_i & wb_stb_i) /* register only when needed to reduce EMI */
flash_adr <= wb_adr_i[adr_width+1:2];
wb_dat_o <= flash_d;
end
/*
* Timing of the ML401 flash chips is 110ns.
* By using 16 cycles at 100MHz and counting
* the I/O registers delay we have some margins
* and simple hardware for generating WB ack.
*/
reg [3:0] counter;
always @(posedge sys_clk) begin
if(sys_rst)
counter <= 4'd1;
else begin
if(wb_cyc_i & wb_stb_i)
counter <= counter + 4'd1;
wb_ack_o <= &counter;
end
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: upd77c25_pgmrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module upd77c25_pgmrom (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [23:0] data;
input [10:0] rdaddress;
input [10:0] wraddress;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "49152"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "framework_defines.vh"
module pipeline_agent
(
input wire clk,
input wire rst_n,
// Pipelining request
input wire find_pipeline_schedule,
input wire direct_pipeline_schedule,
input wire [0:`NUMBER_OF_FTHREADS-1] fthreads_state,
input wire [0:`NUMBER_OF_FTHREADS-1] src_job_fthread_mapping,
input wire [0:`NUMBER_OF_FTHREADS-1] dst_job_fthread_mapping,
// Pipeline Schedule decision
output reg [0:`NUMBER_OF_FTHREADS-1] src_fthread_select,
output reg [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select,
output reg dst_fthread_reserve,
output reg pipeline_schedule_valid
);
wire [0:`NUMBER_OF_FTHREADS-1] dst_job_mapping_shifted;
wire [0:`NUMBER_OF_FTHREADS-1] pipeline_src_job_mapping;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_src;
wire [0:`NUMBER_OF_FTHREADS-1] src_job_mapping_shifted;
wire [0:`NUMBER_OF_FTHREADS-1] pipeline_dst_job_mapping;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_dst;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_both;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_b;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_b;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_s;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_s;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_a;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_a;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_r;
wire [0:`NUMBER_OF_FTHREADS-1] valid_mapping_src;
wire [0:`NUMBER_OF_FTHREADS-1] valid_mapping_dst;
genvar k;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////
/////////////////////////////// Memory Pipeline Schedule Decision /////////////////////////////
////////////////////////////////// ///////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
generate if(`NUMBER_OF_FTHREADS > 1) begin
// any valid mapping
assign valid_mapping_src = src_job_fthread_mapping & ~fthreads_state;
assign valid_mapping_dst = dst_job_fthread_mapping & ~fthreads_state;
// src schedule decision
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_a
assign src_fthread_select_a[k] = valid_mapping_src[k] & ~(|(valid_mapping_src[0:k-1]));
end
//endgenerate
assign src_fthread_select_a[1] = valid_mapping_src[1] & ~valid_mapping_src[0];
assign src_fthread_select_a[0] = valid_mapping_src[0];
// dst schedule decision
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_dst_a
assign dst_fthread_select_a[k] = valid_mapping_dst[k] & ~(|(valid_mapping_dst[0:k-1]));
end
//endgenerate
assign dst_fthread_select_a[1] = valid_mapping_dst[1] & ~valid_mapping_dst[0];
assign dst_fthread_select_a[0] = valid_mapping_dst[0];
// dst schedule reserve
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_dst_r
assign dst_fthread_select_r[k] = dst_job_fthread_mapping[k] & ~(|(dst_job_fthread_mapping[0:k-1]));
end
//endgenerate
assign dst_fthread_select_r[1] = dst_job_fthread_mapping[1] & ~dst_job_fthread_mapping[0];
assign dst_fthread_select_r[0] = dst_job_fthread_mapping[0];
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////
/////////////////////////////// Direct Pipeline Schedule Decision /////////////////////////////
////////////////////////////////// ///////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// Check if at least the src can be mapped
assign dst_job_mapping_shifted = {dst_job_fthread_mapping[1:`NUMBER_OF_FTHREADS-1], 1'b0};
assign pipeline_src_job_mapping = dst_job_mapping_shifted & src_job_fthread_mapping;
assign valid_pipeline_mapping_src = pipeline_src_job_mapping & ~fthreads_state;
// check if at least dst can be mapped
assign src_job_mapping_shifted = {1'b0, src_job_fthread_mapping[0:`NUMBER_OF_FTHREADS-2]};
assign pipeline_dst_job_mapping = src_job_mapping_shifted & dst_job_fthread_mapping;
assign valid_pipeline_mapping_dst = pipeline_dst_job_mapping & ~fthreads_state;
// Check if both src and dst can be mapped
assign valid_pipeline_mapping_both = {valid_pipeline_mapping_dst[1:`NUMBER_OF_FTHREADS-1], 1'b0} &
valid_pipeline_mapping_src;
//---------------------------------------------------------------------------------------------------//
// src schedule decision based on valid mapping for both src & dst
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_b
assign src_fthread_select_b[k] = valid_pipeline_mapping_both[k] & ~(|(valid_pipeline_mapping_both[0:k-1]));
end
//endgenerate
assign src_fthread_select_b[1] = valid_pipeline_mapping_both[1] & ~valid_pipeline_mapping_both[0];
assign src_fthread_select_b[0] = valid_pipeline_mapping_both[0];
//---------------------------------------------------------------------------------------------------//
// dst schedule decision based on valid mapping for both src & dst
assign dst_fthread_select_b = {1'b0, src_fthread_select_b[0:`NUMBER_OF_FTHREADS-2]};
//---------------------------------------------------------------------------------------------------//
// src schedule decision based on valid mapping at least for src
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_s
assign src_fthread_select_s[k] = valid_pipeline_mapping_src[k] & ~(|(valid_pipeline_mapping_src[0:k-1]));
end
//endgenerate
assign src_fthread_select_s[1] = valid_pipeline_mapping_src[1] & ~valid_pipeline_mapping_src[0];
assign src_fthread_select_s[0] = valid_pipeline_mapping_src[0];
//---------------------------------------------------------------------------------------------------//
// dst reserved
assign dst_fthread_select_s = {1'b0, src_fthread_select_s[0:`NUMBER_OF_FTHREADS-2]};
//---------------------------------------------------------------------------------------------------//
always @(posedge clk) begin
if (~rst_n) begin
src_fthread_select <= 0;
dst_fthread_select <= 0;
dst_fthread_reserve <= 0;
pipeline_schedule_valid <= 0;
end
else begin
if(direct_pipeline_schedule) begin
if (|src_fthread_select_b) begin
src_fthread_select <= src_fthread_select_b;
dst_fthread_select <= dst_fthread_select_b;
dst_fthread_reserve <= 1'b0;
end
else begin
src_fthread_select <= src_fthread_select_s;
dst_fthread_select <= dst_fthread_select_s;
dst_fthread_reserve <= 1'b1;
end
end
else begin
src_fthread_select <= src_fthread_select_a;
dst_fthread_select <= 0;
dst_fthread_reserve <= 1'b0;
if(|src_fthread_select_a) begin
if(|dst_fthread_select_a) begin
dst_fthread_select <= dst_fthread_select_a;
end
else begin
dst_fthread_select <= dst_fthread_select_r;
dst_fthread_reserve <= 1'b1;
end
end
end
pipeline_schedule_valid <= find_pipeline_schedule;
end
end
end
else begin
always @(posedge clk) begin
src_fthread_select <= 0;
dst_fthread_select <= 0;
dst_fthread_reserve <= 0;
pipeline_schedule_valid <= 0;
end
end
endgenerate
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_SYMBOL_V
`define SKY130_FD_SC_LS__O31AI_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o31ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_SYMBOL_V
|
`ifndef ALU_V
`define ALU_V
`include "adder.v"
`include "multiplier.v"
`include "divider.v"
`include "shifter.v"
`define OP_NOP 4'b0000
`define OP_ADD 4'b0001
`define OP_SUB 4'b0010
`define OP_MUL 4'b0011
`define OP_DIV 4'b0100
`define OP_LEFT_SHIFTL 4'b0101
`define OP_LEFT_SHIFTA 4'b0110
`define OP_RIGHT_SHIFTL 4'b0111
`define OP_RIGHT_SHIFTA 4'b1000
// Simple single cycle adder
module alu(
input clk,
input reset,
input [31:0] i_a, // 1st operand
input [31:0] i_b, // 2nd operand
input [3:0] i_cmd, // command
output [31:0] o_result,
output o_valid, // result is valid
output o_ready // ready to take input
);
reg [31:0] reg_result;
reg reg_valid = 1'b0;
// ALU state machine macros
`define ST_RESET 2'h0
`define ST_READY 2'h1
`define ST_BUSY 2'h2
// begin in reset state
reg [1:0] reg_status = `ST_RESET;
// Synchronous reset
always @(posedge clk && reset) begin
reg_status <= `ST_READY;
end
// Assign outputs
assign o_ready = ((reg_status == `ST_READY) && !reset);
assign o_valid = (reg_valid && (reg_status == `ST_READY));
assign o_result = reg_result; //o_valid ? reg_result : 32'hx; // Ternary operator
// instants of various components of alu
// Adder
reg adder_cin;
wire adder_cout;
wire[31:0] adder_result;
adder alu_adder(.i_a(i_a), .i_b(i_b), .i_cin(adder_cin), .o_result(adder_result), .o_cout(adder_cout));
// Subtractor
reg subtractor_cin;
wire subtractor_cout;
wire[31:0] subtractor_result;
adder alu_subtractor(.i_a(i_a), .i_b(~i_b), .i_cin(subtractor_cin), .o_result(subtractor_result), .o_cout(subtractor_cout));
// Multiplier
reg multiplier_start = 1'b0;
wire[`WIDTH + `WIDTH - 1:0] multiplier_result;
wire multiplier_ready;
multiplier mul(
.start(multiplier_start),
.clk(clk),
.multiplier(i_a),
.multiplicand(i_b),
.product(multiplier_result),
.ready(multiplier_ready));
// Divider
reg divider_start = 1'b0;
wire[`WIDTH-1:0] divider_quotient, divider_remainder;
wire divider_ready;
divider div(
.start(divider_start),
.clk(clk),
.dividend(i_b),
.divisor(i_a),
.quotient(divider_quotient),
.remainder(divider_remainder),
.ready(divider_ready));
// Shifter
reg[`OPS-1:0] shifter_ops;
wire[`WIDTH-1:0] shifter_result;
reg shifter_start = 1'b0;
shifter shift(
.i_data(i_a),
.i_shift(i_b[`SHIFT_WIDTH-1:0]),
.i_op(shifter_ops),
.i_start(shifter_start),
.o_result(shifter_result));
// Main processing loop
always @(posedge clk && !reset) begin
case (reg_status)
`ST_READY: begin
reg_status <= `ST_BUSY;
case (i_cmd)
`OP_ADD: begin
adder_cin = 1'b0;
reg_result = adder_result;
end
`OP_SUB: begin
subtractor_cin = 1'b1;
reg_result = subtractor_result;
end
`OP_MUL: begin
multiplier_start = 1'b1;
reg_result = multiplier_result[`WIDTH-1:0];
end
`OP_DIV: begin
divider_start = 1'b1;
reg_result = divider_quotient;
end
`OP_LEFT_SHIFTL: begin
shifter_ops = `LEFT_SHIFTL;
shifter_start = 1'b1;
reg_result = shifter_result;
end
`OP_LEFT_SHIFTA: begin
shifter_ops = `LEFT_SHIFTA;
shifter_start = 1'b1;
reg_result = shifter_result;
end
`OP_RIGHT_SHIFTL: begin
shifter_ops = `RIGHT_SHIFTL;
shifter_start = 1'b1;
reg_result = shifter_result;
end
`OP_RIGHT_SHIFTA: begin
shifter_ops = `RIGHT_SHIFTA;
shifter_start = 1'b1;
reg_result = shifter_result;
end
endcase
end
`ST_BUSY: begin
if (divider_ready == 1'b1 && multiplier_ready == 1'b1) begin
reg_valid <= 1'b1;
reg_status <= `ST_READY;
end
shifter_start = 1'b0;
if (divider_ready == 1'b0)
divider_start = 1'b0;
if (multiplier_ready == 1'b0)
multiplier_start = 1'b0;
end
default: begin
$display("should not happen");
$finish;
end
endcase
end
endmodule
`endif
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=100, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
//(* HW_HANDOFF = "triangle_intersect_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
//wire ENET0_GMII_TX_EN_i;
//wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
begin
assign ENET0_GMII_TX_EN_i = 1'b0;
assign ENET0_GMII_TX_ER_i = 1'b0;
assign ENET0_GMII_TXD_i = 1'b0;
always@*
begin
ENET0_GMII_TXD <= 0;
ENET0_GMII_TX_EN <= 0;
ENET0_GMII_TX_ER <= 0;
ENET0_GMII_COL_i <= 0;
ENET0_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
assign ENET1_GMII_TX_EN_i = 1'b0;
assign ENET1_GMII_TX_ER_i = 1'b0;
assign ENET1_GMII_TXD_i = 1'b0;
always@*
begin
ENET1_GMII_TXD <= 0;
ENET1_GMII_TX_EN <= 0;
ENET1_GMII_TX_ER <= 0;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 0;
ENET1_GMII_RX_DV_i <= 0;
ENET1_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
//Start
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// ghrd_10as066n2_mm_bridge_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_mm_bridge_0 #(
parameter DATA_WIDTH = 512,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 32,
parameter BURSTCOUNT_WIDTH = 5,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [63:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [63:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (DATA_WIDTH),
.SYMBOL_WIDTH (SYMBOL_WIDTH),
.HDL_ADDR_WIDTH (HDL_ADDR_WIDTH),
.BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
.PIPELINE_COMMAND (PIPELINE_COMMAND),
.PIPELINE_RESPONSE (PIPELINE_RESPONSE)
) mm_bridge_0 (
.clk (clk), // input, width = 1, clk.clk
.reset (reset), // input, width = 1, reset.reset
.s0_waitrequest (s0_waitrequest), // output, width = 1, s0.waitrequest
.s0_readdata (s0_readdata), // output, width = DATA_WIDTH, .readdata
.s0_readdatavalid (s0_readdatavalid), // output, width = 1, .readdatavalid
.s0_burstcount (s0_burstcount), // input, width = BURSTCOUNT_WIDTH, .burstcount
.s0_writedata (s0_writedata), // input, width = DATA_WIDTH, .writedata
.s0_address (s0_address), // input, width = HDL_ADDR_WIDTH, .address
.s0_write (s0_write), // input, width = 1, .write
.s0_read (s0_read), // input, width = 1, .read
.s0_byteenable (s0_byteenable), // input, width = 64, .byteenable
.s0_debugaccess (s0_debugaccess), // input, width = 1, .debugaccess
.m0_waitrequest (m0_waitrequest), // input, width = 1, m0.waitrequest
.m0_readdata (m0_readdata), // input, width = DATA_WIDTH, .readdata
.m0_readdatavalid (m0_readdatavalid), // input, width = 1, .readdatavalid
.m0_burstcount (m0_burstcount), // output, width = BURSTCOUNT_WIDTH, .burstcount
.m0_writedata (m0_writedata), // output, width = DATA_WIDTH, .writedata
.m0_address (m0_address), // output, width = HDL_ADDR_WIDTH, .address
.m0_write (m0_write), // output, width = 1, .write
.m0_read (m0_read), // output, width = 1, .read
.m0_byteenable (m0_byteenable), // output, width = 64, .byteenable
.m0_debugaccess (m0_debugaccess), // output, width = 1, .debugaccess
.s0_response (), // (terminated),
.m0_response (2'b00) // (terminated),
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:20:05 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n514, n515, n516,
n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527,
n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538,
n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549,
n550, n551, n552, n553, n554, n555, n556, n557, n558, n559, n560,
n561, n562, n563, n564, n565, n566, n567, n568, n569, n570, n571,
n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582,
n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n820, n821, n822, n823, n824, n825,
n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836,
n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847,
n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858,
n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869,
n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880,
n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922,
DP_OP_15J26_123_2314_n8, DP_OP_15J26_123_2314_n7,
DP_OP_15J26_123_2314_n6, DP_OP_15J26_123_2314_n5,
DP_OP_15J26_123_2314_n4, intadd_20_B_10_, intadd_20_B_9_,
intadd_20_B_8_, intadd_20_B_7_, intadd_20_B_6_, intadd_20_B_5_,
intadd_20_B_4_, intadd_20_B_3_, intadd_20_B_2_, intadd_20_B_1_,
intadd_20_B_0_, intadd_20_CI, intadd_20_SUM_10_, intadd_20_SUM_9_,
intadd_20_SUM_8_, intadd_20_SUM_7_, intadd_20_SUM_6_,
intadd_20_SUM_5_, intadd_20_SUM_4_, intadd_20_SUM_3_,
intadd_20_SUM_2_, intadd_20_SUM_1_, intadd_20_SUM_0_, intadd_20_n11,
intadd_20_n10, intadd_20_n9, intadd_20_n8, intadd_20_n7, intadd_20_n6,
intadd_20_n5, intadd_20_n4, intadd_20_n3, intadd_20_n2, intadd_20_n1,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1397, n1398, n1399, n1401, n1402, n1403,
n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664,
n1665, n1666, n1667, n1668, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1699, n1700, n1701;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:1] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [24:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n917), .CK(clk), .RN(n1689), .QN(
n932) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n911), .CK(clk), .RN(n1670),
.QN(n936) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n903), .CK(clk), .RN(n1684),
.QN(n928) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n881), .CK(clk), .RN(n1672), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n880), .CK(clk), .RN(n1670), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1677),
.Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1676), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n824), .CK(clk), .RN(n1673), .Q(
Data_array_SWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n816), .CK(clk), .RN(n927), .Q(
Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n815), .CK(clk), .RN(n1676),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n814), .CK(clk), .RN(n1675),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n813), .CK(clk), .RN(n1673),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n812), .CK(clk), .RN(n1684), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n811), .CK(clk), .RN(n1694), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n810), .CK(clk), .RN(n1694), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n809), .CK(clk), .RN(n1694), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n808), .CK(clk), .RN(n1694), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n807), .CK(clk), .RN(n1694), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n806), .CK(clk), .RN(n1694), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n805), .CK(clk), .RN(n1694), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n804), .CK(clk), .RN(n927), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n803), .CK(clk), .RN(n925), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n802), .CK(clk), .RN(n925), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n801), .CK(clk), .RN(n1676), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n800), .CK(clk), .RN(n1675), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n799), .CK(clk), .RN(n1673), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n798), .CK(clk), .RN(n927), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n797), .CK(clk), .RN(n925), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n796), .CK(clk), .RN(n982), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n795), .CK(clk), .RN(n1672), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n794), .CK(clk), .RN(n1670), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n793), .CK(clk), .RN(n1677), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n792), .CK(clk), .RN(n1671), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n791), .CK(clk), .RN(n1689), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n790), .CK(clk), .RN(n1674), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n789), .CK(clk), .RN(n1672), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n788), .CK(clk), .RN(n1670), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n787), .CK(clk), .RN(n1677), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n786), .CK(clk), .RN(n1671), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n785), .CK(clk), .RN(n1683), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n784), .CK(clk), .RN(n1674), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n783), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n782), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n777), .CK(clk), .RN(n1678), .QN(n949)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n776), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n775), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n774), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n773), .CK(clk), .RN(n1678), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n772), .CK(clk), .RN(n1678), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n771), .CK(clk), .RN(n1679), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n770), .CK(clk), .RN(n1679), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n769), .CK(clk), .RN(n1679), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n767), .CK(clk), .RN(n1679), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n766), .CK(clk), .RN(n1679), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1679), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n763), .CK(clk), .RN(n1679), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n762), .CK(clk), .RN(n1679), .Q(
DMP_SFG[2]), .QN(n1664) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n761), .CK(clk), .RN(n1679), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n760), .CK(clk), .RN(n1679), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n758), .CK(clk), .RN(n1683), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n757), .CK(clk), .RN(n1684), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n756), .CK(clk), .RN(n981), .QN(n944)
);
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n755), .CK(clk), .RN(n1684), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n754), .CK(clk), .RN(n1689), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n752), .CK(clk), .RN(n1684), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n751), .CK(clk), .RN(n925), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n750), .CK(clk), .RN(n1680), .QN(n945)
);
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n749), .CK(clk), .RN(n1683), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n748), .CK(clk), .RN(n1689), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n746), .CK(clk), .RN(n925), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1680), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n743), .CK(clk), .RN(n1680), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n742), .CK(clk), .RN(n1684), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n740), .CK(clk), .RN(n1695), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n739), .CK(clk), .RN(n1683), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n737), .CK(clk), .RN(n1683), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n736), .CK(clk), .RN(n1689), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n735), .CK(clk), .RN(n1686), .QN(n937)
);
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n734), .CK(clk), .RN(n1681), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n733), .CK(clk), .RN(n1686), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n732), .CK(clk), .RN(n1681), .Q(
DMP_SFG[12]), .QN(n1612) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n731), .CK(clk), .RN(n1686), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n730), .CK(clk), .RN(n1681), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n729), .CK(clk), .RN(n1686), .Q(
DMP_SFG[13]), .QN(n1611) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n728), .CK(clk), .RN(n1681), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n727), .CK(clk), .RN(n1686), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n726), .CK(clk), .RN(n1681), .Q(
DMP_SFG[14]), .QN(n1617) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n725), .CK(clk), .RN(n1686), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n724), .CK(clk), .RN(n1681), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n723), .CK(clk), .RN(n1682), .Q(
DMP_SFG[15]), .QN(n1634) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n722), .CK(clk), .RN(n1682), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n721), .CK(clk), .RN(n1682), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n720), .CK(clk), .RN(n1682), .Q(
DMP_SFG[16]), .QN(n1633) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n719), .CK(clk), .RN(n1682), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n718), .CK(clk), .RN(n1682), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n717), .CK(clk), .RN(n1682), .Q(
DMP_SFG[17]), .QN(n1647) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n716), .CK(clk), .RN(n1682), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n715), .CK(clk), .RN(n1682), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n714), .CK(clk), .RN(n1682), .Q(
DMP_SFG[18]), .QN(n1646) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n713), .CK(clk), .RN(n1682), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n712), .CK(clk), .RN(n1682), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n711), .CK(clk), .RN(n1689), .Q(
DMP_SFG[19]), .QN(n1655) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n710), .CK(clk), .RN(n1683), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n709), .CK(clk), .RN(n1680), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n708), .CK(clk), .RN(n1695), .Q(
DMP_SFG[20]), .QN(n1654) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n707), .CK(clk), .RN(n1684), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n706), .CK(clk), .RN(n1689), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n705), .CK(clk), .RN(n1684), .Q(
DMP_SFG[21]), .QN(n1667) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n704), .CK(clk), .RN(n1695), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n703), .CK(clk), .RN(n1683), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n702), .CK(clk), .RN(n925), .Q(
DMP_SFG[22]), .QN(n1666) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n701), .CK(clk), .RN(n1680), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n700), .CK(clk), .RN(n1683), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n699), .CK(clk), .RN(n1680), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n698), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n696), .CK(clk), .RN(n1689), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n695), .CK(clk), .RN(n1683), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n694), .CK(clk), .RN(n1680), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n693), .CK(clk), .RN(n1695), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n691), .CK(clk), .RN(n1695), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n690), .CK(clk), .RN(n1683), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n689), .CK(clk), .RN(n1684), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n688), .CK(clk), .RN(n1689), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n686), .CK(clk), .RN(n1689), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n685), .CK(clk), .RN(n925), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n684), .CK(clk), .RN(n1690), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n683), .CK(clk), .RN(n1685), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n681), .CK(clk), .RN(n1686), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n680), .CK(clk), .RN(n1670), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n679), .CK(clk), .RN(n1695), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n678), .CK(clk), .RN(n1690), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n676), .CK(clk), .RN(n1685), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n675), .CK(clk), .RN(n1674), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n674), .CK(clk), .RN(n1674), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n673), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n671), .CK(clk), .RN(n1690), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n670), .CK(clk), .RN(n1685), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n669), .CK(clk), .RN(n1686), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n668), .CK(clk), .RN(n1681), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n666), .CK(clk), .RN(n1686), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n665), .CK(clk), .RN(n1681), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n664), .CK(clk), .RN(n1686), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n663), .CK(clk), .RN(n1681), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n661), .CK(clk), .RN(n1686), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n660), .CK(clk), .RN(n1681), .QN(
n950) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n659), .CK(clk), .RN(n1686), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n657), .CK(clk), .RN(n1681), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n655), .CK(clk), .RN(n1688), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n653), .CK(clk), .RN(n1688), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n652), .CK(clk), .RN(n1688), .QN(
n954) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n651), .CK(clk), .RN(n1688), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n650), .CK(clk), .RN(n1688), .QN(
n951) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n649), .CK(clk), .RN(n1688), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n647), .CK(clk), .RN(n1688), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n645), .CK(clk), .RN(n1688), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n643), .CK(clk), .RN(n1688), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n642), .CK(clk), .RN(n1688), .QN(
n946) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n641), .CK(clk), .RN(n1687), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n639), .CK(clk), .RN(n1691), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n638), .CK(clk), .RN(n1692),
.QN(n952) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n637), .CK(clk), .RN(n927), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n635), .CK(clk), .RN(n1687), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n634), .CK(clk), .RN(n1691),
.QN(n953) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n633), .CK(clk), .RN(n1692), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n631), .CK(clk), .RN(n1677), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n630), .CK(clk), .RN(n1686),
.QN(n947) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n629), .CK(clk), .RN(n983), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n627), .CK(clk), .RN(n1694), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n625), .CK(clk), .RN(n1690), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n623), .CK(clk), .RN(n1685), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n622), .CK(clk), .RN(n1670),
.QN(n948) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n621), .CK(clk), .RN(n1681), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n619), .CK(clk), .RN(n1681), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n617), .CK(clk), .RN(n1690), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n1685), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n610), .CK(clk), .RN(n1677), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n609), .CK(clk), .RN(n1694), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n608), .CK(clk), .RN(n983), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n607), .CK(clk), .RN(n1680), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n606), .CK(clk), .RN(n927), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n605), .CK(clk), .RN(n1687), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n604), .CK(clk), .RN(n1691), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1692), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n602), .CK(clk), .RN(n927), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n601), .CK(clk), .RN(n1687), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n599), .CK(clk), .RN(n1691), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n598), .CK(clk), .RN(n1692), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n597), .CK(clk), .RN(n927), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n596), .CK(clk), .RN(n1687), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n595), .CK(clk), .RN(n1691), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n594), .CK(clk), .RN(n1694), .Q(
final_result_ieee[31]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n581), .CK(clk), .RN(n1690), .Q(
DmP_mant_SFG_SWR[13]), .QN(n978) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n579), .CK(clk), .RN(n1680), .Q(
LZD_output_NRM2_EW[4]), .QN(n1618) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n1685), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n576), .CK(clk), .RN(n1683), .Q(
LZD_output_NRM2_EW[2]), .QN(n1614) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n575), .CK(clk), .RN(n1671), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n573), .CK(clk), .RN(n1695), .Q(
LZD_output_NRM2_EW[1]), .QN(n1607) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n572), .CK(clk), .RN(n1670), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n571), .CK(clk), .RN(n983), .QN(
n938) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n570), .CK(clk), .RN(n1693), .QN(
n942) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n567), .CK(clk), .RN(n1684), .Q(
LZD_output_NRM2_EW[3]), .QN(n1613) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n564), .CK(clk), .RN(n1672), .Q(
DmP_mant_SFG_SWR[5]), .QN(n924) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n560), .CK(clk), .RN(n1695), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n559), .CK(clk), .RN(n1671), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n557), .CK(clk), .RN(n983), .QN(
n941) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n553), .CK(clk), .RN(n1672), .Q(
DmP_mant_SFG_SWR[11]), .QN(n931) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n551), .CK(clk), .RN(n1687), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n549), .CK(clk), .RN(n1693), .QN(
n935) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n548), .CK(clk), .RN(n1691), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n547), .CK(clk), .RN(n1692), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n546), .CK(clk), .RN(n927), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n545), .CK(clk), .RN(n1687), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n544), .CK(clk), .RN(n1679), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n543), .CK(clk), .RN(n1691), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n542), .CK(clk), .RN(n1692), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n541), .CK(clk), .RN(n927), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n540), .CK(clk), .RN(n1692), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n539), .CK(clk), .RN(n927), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n538), .CK(clk), .RN(n1687), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n537), .CK(clk), .RN(n1691), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n536), .CK(clk), .RN(n1692), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n535), .CK(clk), .RN(n927), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n534), .CK(clk), .RN(n1682), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n533), .CK(clk), .RN(n1687), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n532), .CK(clk), .RN(n1691), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n531), .CK(clk), .RN(n1692), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n530), .CK(clk), .RN(n927), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n529), .CK(clk), .RN(n1679), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n528), .CK(clk), .RN(n1693), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n527), .CK(clk), .RN(n1693), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n526), .CK(clk), .RN(n1693), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n525), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n524), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n522), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n519), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n518), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n515), .CK(clk), .RN(n1694), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n514), .CK(clk), .RN(n1694), .Q(
DmP_mant_SFG_SWR[25]) );
CMPR32X2TS intadd_20_U12 ( .A(n1612), .B(intadd_20_B_0_), .C(intadd_20_CI),
.CO(intadd_20_n11), .S(intadd_20_SUM_0_) );
CMPR32X2TS intadd_20_U11 ( .A(n1611), .B(intadd_20_B_1_), .C(intadd_20_n11),
.CO(intadd_20_n10), .S(intadd_20_SUM_1_) );
CMPR32X2TS intadd_20_U10 ( .A(n1617), .B(intadd_20_B_2_), .C(intadd_20_n10),
.CO(intadd_20_n9), .S(intadd_20_SUM_2_) );
CMPR32X2TS intadd_20_U9 ( .A(n1634), .B(intadd_20_B_3_), .C(intadd_20_n9),
.CO(intadd_20_n8), .S(intadd_20_SUM_3_) );
CMPR32X2TS intadd_20_U8 ( .A(n1633), .B(intadd_20_B_4_), .C(intadd_20_n8),
.CO(intadd_20_n7), .S(intadd_20_SUM_4_) );
CMPR32X2TS intadd_20_U7 ( .A(n1647), .B(intadd_20_B_5_), .C(intadd_20_n7),
.CO(intadd_20_n6), .S(intadd_20_SUM_5_) );
CMPR32X2TS intadd_20_U6 ( .A(n1646), .B(intadd_20_B_6_), .C(intadd_20_n6),
.CO(intadd_20_n5), .S(intadd_20_SUM_6_) );
CMPR32X2TS intadd_20_U5 ( .A(n1655), .B(intadd_20_B_7_), .C(intadd_20_n5),
.CO(intadd_20_n4), .S(intadd_20_SUM_7_) );
CMPR32X2TS intadd_20_U4 ( .A(n1654), .B(intadd_20_B_8_), .C(intadd_20_n4),
.CO(intadd_20_n3), .S(intadd_20_SUM_8_) );
CMPR32X2TS intadd_20_U3 ( .A(n1667), .B(intadd_20_B_9_), .C(intadd_20_n3),
.CO(intadd_20_n2), .S(intadd_20_SUM_9_) );
CMPR32X2TS intadd_20_U2 ( .A(n1666), .B(intadd_20_B_10_), .C(intadd_20_n2),
.CO(intadd_20_n1), .S(intadd_20_SUM_10_) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n927), .Q(
Data_array_SWR[19]), .QN(n1663) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n613), .CK(clk), .RN(n983), .Q(
DmP_EXP_EWSW[25]), .QN(n1662) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n778), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[26]), .QN(n1661) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n831), .CK(clk), .RN(n1675), .Q(
Data_array_SWR[9]), .QN(n1660) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n889), .CK(clk), .RN(n1680),
.Q(intDX_EWSW[24]), .QN(n1659) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n612), .CK(clk), .RN(n1685), .Q(
DmP_EXP_EWSW[26]), .QN(n1658) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n829), .CK(clk), .RN(n981), .Q(
Data_array_SWR[7]), .QN(n1657) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n828), .CK(clk), .RN(n1673), .Q(
Data_array_SWR[6]), .QN(n1656) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n840), .CK(clk), .RN(n981), .Q(
Data_array_SWR[17]), .QN(n1653) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n841), .CK(clk), .RN(n1676), .Q(
Data_array_SWR[18]), .QN(n1652) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n834), .CK(clk), .RN(n982), .Q(
Data_array_SWR[12]), .QN(n1651) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n779), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[25]), .QN(n1650) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n833), .CK(clk), .RN(n1673), .Q(
Data_array_SWR[11]), .QN(n1649) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n832), .CK(clk), .RN(n927), .Q(
Data_array_SWR[10]), .QN(n1648) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n662), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1645) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n759), .CK(clk), .RN(n1683), .Q(
DMP_SFG[3]), .QN(n1644) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n861), .CK(clk), .RN(n1672),
.Q(intDY_EWSW[18]), .QN(n1643) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n885), .CK(clk), .RN(n1672),
.Q(intDX_EWSW[28]), .QN(n1642) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n568), .CK(clk), .RN(n983), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1641) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n871), .CK(clk), .RN(n1671), .Q(
intDY_EWSW[8]), .QN(n1640) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n878), .CK(clk), .RN(n1693), .Q(
intDY_EWSW[1]), .QN(n1639) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n862), .CK(clk), .RN(n982), .Q(
intDY_EWSW[17]), .QN(n1638) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n879), .CK(clk), .RN(n1672), .Q(
intDY_EWSW[0]), .QN(n1637) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n854), .CK(clk), .RN(n1675),
.Q(intDY_EWSW[25]), .QN(n1636) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n853), .CK(clk), .RN(n1673),
.Q(intDY_EWSW[26]), .QN(n1635) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n667), .CK(clk), .RN(n1688), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1632) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n856), .CK(clk), .RN(n1676),
.Q(intDY_EWSW[23]), .QN(n1631) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n884), .CK(clk), .RN(n1677),
.Q(intDX_EWSW[29]), .QN(n1630) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n872), .CK(clk), .RN(n1676), .Q(
intDY_EWSW[7]), .QN(n1629) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n852), .CK(clk), .RN(n1672),
.Q(intDY_EWSW[27]), .QN(n1628) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n865), .CK(clk), .RN(n1675),
.Q(intDY_EWSW[14]), .QN(n1626) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n867), .CK(clk), .RN(n927), .Q(
intDY_EWSW[12]), .QN(n1625) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n875), .CK(clk), .RN(n1675), .Q(
intDY_EWSW[4]), .QN(n1624) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n877), .CK(clk), .RN(n1670), .Q(
intDY_EWSW[2]), .QN(n1623) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n866), .CK(clk), .RN(n1676),
.Q(intDY_EWSW[13]), .QN(n1621) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n870), .CK(clk), .RN(n927), .Q(
intDY_EWSW[9]), .QN(n1620) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n873), .CK(clk), .RN(n981), .Q(
intDY_EWSW[6]), .QN(n1619) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n672), .CK(clk), .RN(n1684), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1616) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n921), .CK(clk), .RN(
n1671), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1615) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n849), .CK(clk), .RN(n1677),
.Q(intDY_EWSW[30]), .QN(n1610) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n897), .CK(clk), .RN(n1671),
.Q(intDX_EWSW[16]), .QN(n1609) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n574), .CK(clk), .RN(n1679), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1608) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n697), .CK(clk), .RN(n1684), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1606) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n907), .CK(clk), .RN(n1674), .Q(
intDX_EWSW[6]), .QN(n1604) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n556), .CK(clk), .RN(n983), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1603) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n908), .CK(clk), .RN(n1671), .Q(
intDX_EWSW[5]), .QN(n1602) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n550), .CK(clk), .RN(n927), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1600) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n558), .CK(clk), .RN(n1690), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1599) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n563), .CK(clk), .RN(n1685), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1598) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n552), .CK(clk), .RN(n1692), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1597) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n554), .CK(clk), .RN(n1685), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1596) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n919), .CK(clk), .RN(n1671), .Q(
n1578), .QN(n1665) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n918), .CK(clk), .RN(n1677), .QN(
n1668) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n887), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[26]), .QN(n1595) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n888), .CK(clk), .RN(n1677),
.Q(intDX_EWSW[25]), .QN(n1594) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n837), .CK(clk), .RN(n1675), .Q(
Data_array_SWR[14]), .QN(n1593) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n844), .CK(clk), .RN(n1674), .Q(
Data_array_SWR[21]), .QN(n1592) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n780), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[24]), .QN(n1591) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n614), .CK(clk), .RN(n983), .Q(
DmP_EXP_EWSW[24]), .QN(n1590) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n860), .CK(clk), .RN(n1675),
.Q(intDY_EWSW[19]), .QN(n1589) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n883), .CK(clk), .RN(n1671),
.Q(intDX_EWSW[30]), .QN(n1588) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n857), .CK(clk), .RN(n1681),
.Q(intDY_EWSW[22]), .QN(n1587) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n863), .CK(clk), .RN(n1676),
.Q(intDY_EWSW[16]), .QN(n1586) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n874), .CK(clk), .RN(n1673), .Q(
intDY_EWSW[5]), .QN(n1585) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1674), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1584) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n850), .CK(clk), .RN(n1682),
.Q(intDY_EWSW[29]), .QN(n1583) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n906), .CK(clk), .RN(n1670), .Q(
intDX_EWSW[7]), .QN(n1581) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n569), .CK(clk), .RN(n1685), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1580) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n909), .CK(clk), .RN(n1677), .Q(
intDX_EWSW[4]), .QN(n1579) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n591), .CK(clk), .RN(n1683), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1577) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n845), .CK(clk), .RN(n1676), .Q(
Data_array_SWR[22]), .QN(n1576) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n836), .CK(clk), .RN(n1673), .QN(
n1575) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n855), .CK(clk), .RN(n981), .Q(
intDY_EWSW[24]), .QN(n1574) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n590), .CK(clk), .RN(n1684), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1573) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n586), .CK(clk), .RN(n927), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1572) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n593), .CK(clk), .RN(n1680), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1571) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n582), .CK(clk), .RN(n1695), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1570) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n585), .CK(clk), .RN(n1689), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1569) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n890), .CK(clk), .RN(n1672),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n900), .CK(clk), .RN(n1672),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n910), .CK(clk), .RN(n1678), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n898), .CK(clk), .RN(n1674),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n892), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n847), .CK(clk), .RN(n1673), .Q(
Data_array_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n587), .CK(clk), .RN(n1683), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n896), .CK(clk), .RN(n1680),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n846), .CK(clk), .RN(n1677), .Q(
Data_array_SWR[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n905), .CK(clk), .RN(n1677), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n902), .CK(clk), .RN(n1671),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n904), .CK(clk), .RN(n1674), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n886), .CK(clk), .RN(n1677),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n835), .CK(clk), .RN(n925), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n588), .CK(clk), .RN(n1684), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n913), .CK(clk), .RN(n1670), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n895), .CK(clk), .RN(n1677),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n561), .CK(clk), .RN(n1690), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n580), .CK(clk), .RN(n1681), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n592), .CK(clk), .RN(n925), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n577), .CK(clk), .RN(n1682), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n565), .CK(clk), .RN(n1695), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n922), .CK(clk), .RN(
n1672), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n830), .CK(clk), .RN(n925), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n838), .CK(clk), .RN(n927), .Q(
Data_array_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n589), .CK(clk), .RN(n1689), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n738), .CK(clk), .RN(n1680), .Q(
DMP_SFG[10]) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n600), .CK(clk), .RN(n1687), .Q(n934),
.QN(n1696) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n826), .CK(clk), .RN(n982), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n827), .CK(clk), .RN(n927), .Q(
Data_array_SWR[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n584), .CK(clk), .RN(n1689), .Q(
Raw_mant_NRM_SWR[23]), .QN(n933) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1679), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n882), .CK(clk), .RN(n1676),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n741), .CK(clk), .RN(n1689), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n747), .CK(clk), .RN(n1684), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n753), .CK(clk), .RN(n1680), .Q(
DMP_SFG[5]) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n818), .CK(clk), .RN(n1672), .Q(
shift_value_SHT2_EWR[4]), .QN(n1582) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n583), .CK(clk), .RN(n927), .Q(
Raw_mant_NRM_SWR[24]), .QN(n977) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n744), .CK(clk), .RN(n1680), .Q(
DMP_SFG[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n616), .CK(clk), .RN(n1690), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n628), .CK(clk), .RN(n1690), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n626), .CK(clk), .RN(n1685), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n646), .CK(clk), .RN(n1687), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n654), .CK(clk), .RN(n1694), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n624), .CK(clk), .RN(n1679), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n636), .CK(clk), .RN(n927), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n640), .CK(clk), .RN(n1694), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n644), .CK(clk), .RN(n1691), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n869), .CK(clk), .RN(n981), .Q(
intDY_EWSW[10]), .QN(n930) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n620), .CK(clk), .RN(n1678), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n632), .CK(clk), .RN(n1691), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n618), .CK(clk), .RN(n1693), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n648), .CK(clk), .RN(n1692), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n656), .CK(clk), .RN(n1686), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n658), .CK(clk), .RN(n1681), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n768), .CK(clk), .RN(n1679), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n516), .CK(clk), .RN(n1694), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n517), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n520), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n521), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n523), .CK(clk), .RN(n1693), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n817), .CK(clk), .RN(n981), .Q(
Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n864), .CK(clk), .RN(n1675),
.Q(intDY_EWSW[15]), .QN(n1701) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n859), .CK(clk), .RN(n1676),
.Q(intDY_EWSW[20]), .QN(n1627) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n858), .CK(clk), .RN(n927), .Q(
intDY_EWSW[21]), .QN(n1622) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n781), .CK(clk), .RN(n1678), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n682), .CK(clk), .RN(n1683), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n687), .CK(clk), .RN(n1695), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n692), .CK(clk), .RN(n1689), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n848), .CK(clk), .RN(n1674),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n901), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n893), .CK(clk), .RN(n1671),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n899), .CK(clk), .RN(n1672),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n891), .CK(clk), .RN(n1674),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n912), .CK(clk), .RN(n1677), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n876), .CK(clk), .RN(n1673), .Q(
intDY_EWSW[3]), .QN(n1699) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n851), .CK(clk), .RN(n1671),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n868), .CK(clk), .RN(n982), .Q(
intDY_EWSW[11]), .QN(n1700) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n894), .CK(clk), .RN(n1670),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n843), .CK(clk), .RN(n982), .Q(
Data_array_SWR[20]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n839), .CK(clk), .RN(n1674), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n820), .CK(clk), .RN(n1670), .Q(
shift_value_SHT2_EWR[3]), .QN(n1605) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n566), .CK(clk), .RN(n1690), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n562), .CK(clk), .RN(n927), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n555), .CK(clk), .RN(n1689), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n821), .CK(clk), .RN(n1671), .Q(
shift_value_SHT2_EWR[2]), .QN(n1601) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n822), .CK(clk), .RN(n1674), .Q(
Data_array_SWR[0]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n677), .CK(clk), .RN(n1680), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n823), .CK(clk), .RN(n1675), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n611), .CK(clk), .RN(n1682), .Q(
DmP_EXP_EWSW[27]) );
ADDFX1TS DP_OP_15J26_123_2314_U8 ( .A(n1607), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J26_123_2314_n8), .CO(DP_OP_15J26_123_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J26_123_2314_U7 ( .A(n1614), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J26_123_2314_n7), .CO(DP_OP_15J26_123_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J26_123_2314_U6 ( .A(n1613), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J26_123_2314_n6), .CO(DP_OP_15J26_123_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J26_123_2314_U5 ( .A(n1618), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J26_123_2314_n5), .CO(DP_OP_15J26_123_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n915), .CK(clk), .RN(n1674), .Q(
Shift_reg_FLAGS_7[1]), .QN(n923) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n920), .CK(clk), .RN(n1671), .Q(
Shift_reg_FLAGS_7_6), .QN(n979) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n914), .CK(clk), .RN(n1672), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n916), .CK(clk), .RN(n1674), .Q(
n943), .QN(n1697) );
NAND2X4TS U930 ( .A(n957), .B(n1547), .Y(n1395) );
CMPR32X2TS U931 ( .A(DMP_SFG[8]), .B(n1494), .C(n1493), .CO(n1496), .S(n985)
);
AOI211X1TS U932 ( .A0(n1438), .A1(Data_array_SWR[3]), .B0(n1002), .C0(n1001),
.Y(n1452) );
AOI211X1TS U933 ( .A0(n1438), .A1(Data_array_SWR[2]), .B0(n999), .C0(n998),
.Y(n1445) );
OR2X1TS U934 ( .A(n923), .B(n1220), .Y(n1346) );
AND2X4TS U935 ( .A(Shift_reg_FLAGS_7_6), .B(n1078), .Y(n1088) );
AOI2BB2X2TS U936 ( .B0(n1449), .B1(n959), .A0N(n959), .A1N(n1449), .Y(n1501)
);
CLKINVX6TS U937 ( .A(Shift_reg_FLAGS_7_6), .Y(n1079) );
BUFX6TS U938 ( .A(n981), .Y(n925) );
INVX6TS U939 ( .A(n1346), .Y(n926) );
CLKINVX6TS U940 ( .A(n1365), .Y(n1215) );
AOI31XLTS U941 ( .A0(n1199), .A1(Raw_mant_NRM_SWR[8]), .A2(n1608), .B0(n1322), .Y(n1200) );
NOR2XLTS U942 ( .A(n1510), .B(n1509), .Y(n1511) );
CLKINVX3TS U943 ( .A(n1336), .Y(n1339) );
CLKINVX3TS U944 ( .A(n1341), .Y(n1340) );
NAND2X4TS U945 ( .A(n1521), .B(n1438), .Y(n1000) );
INVX6TS U946 ( .A(n1371), .Y(n1204) );
NAND2X4TS U947 ( .A(n1563), .B(n1438), .Y(n1003) );
BUFX6TS U948 ( .A(n1395), .Y(n1565) );
CLKINVX3TS U949 ( .A(n1506), .Y(n1005) );
NAND2X2TS U950 ( .A(n1582), .B(n1422), .Y(n997) );
BUFX6TS U951 ( .A(n1696), .Y(n1442) );
BUFX6TS U952 ( .A(n925), .Y(n927) );
NAND2BXLTS U953 ( .AN(n976), .B(intDY_EWSW[2]), .Y(n1027) );
NAND2BXLTS U954 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1061) );
NAND2BXLTS U955 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1015) );
NAND2BXLTS U956 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1040) );
OAI2BB2XLTS U957 ( .B0(intDY_EWSW[14]), .B1(n1046), .A0N(intDX_EWSW[15]),
.A1N(n1701), .Y(n1047) );
NAND2BXLTS U958 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1036) );
NAND2BXLTS U959 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1055) );
AOI222X4TS U960 ( .A0(Data_array_SWR[20]), .A1(n1461), .B0(
Data_array_SWR[16]), .B1(n1462), .C0(Data_array_SWR[24]), .C1(n1422),
.Y(n1431) );
NAND2BXLTS U961 ( .AN(n1325), .B(n993), .Y(n996) );
AO22XLTS U962 ( .A0(n1449), .A1(n924), .B0(DmP_mant_SFG_SWR[5]), .B1(n1442),
.Y(n940) );
AO22XLTS U963 ( .A0(n1449), .A1(DmP_mant_SFG_SWR[13]), .B0(n1442), .B1(n978),
.Y(n929) );
AOI211X1TS U964 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n923), .B0(n1354), .C0(
n1343), .Y(n1348) );
AOI222X1TS U965 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n926), .B0(n1355), .B1(n964), .C0(n1354), .C1(DmP_mant_SHT1_SW[14]), .Y(n1247) );
AOI222X1TS U966 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n926), .B0(n1355), .B1(n963),
.C0(n1354), .C1(DmP_mant_SHT1_SW[16]), .Y(n1244) );
AO22XLTS U967 ( .A0(DmP_mant_SFG_SWR[11]), .A1(n1449), .B0(n1442), .B1(n931),
.Y(n939) );
AOI222X1TS U968 ( .A0(n1455), .A1(DMP_SFG[1]), .B0(n1455), .B1(n1454), .C0(
DMP_SFG[1]), .C1(n1454), .Y(n1483) );
AOI222X1TS U969 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n926), .B0(n1355), .B1(n965), .C0(n1354), .C1(DmP_mant_SHT1_SW[12]), .Y(n1256) );
AOI222X1TS U970 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n926), .B0(n1355), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1354), .C1(DmP_mant_SHT1_SW[18]), .Y(n1255) );
AOI222X1TS U971 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n926), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1354), .C0(n1355), .C1(n962), .Y(n1252) );
AOI222X1TS U972 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n926), .B0(n1355), .B1(n966), .C0(n1354), .C1(DmP_mant_SHT1_SW[10]), .Y(n1260) );
AOI222X1TS U973 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n926), .B0(n1355), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1354), .C1(DmP_mant_SHT1_SW[8]), .Y(n1263)
);
AOI222X1TS U974 ( .A0(n1541), .A1(n1563), .B0(Data_array_SWR[8]), .B1(n1540),
.C0(n1539), .C1(n1538), .Y(n1554) );
AOI222X1TS U975 ( .A0(n1541), .A1(n1521), .B0(n1564), .B1(Data_array_SWR[8]),
.C0(n1539), .C1(n1481), .Y(n1537) );
BUFX4TS U976 ( .A(n1668), .Y(n1397) );
AOI222X1TS U977 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n926), .B0(n1355), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1354), .C1(DmP_mant_SHT1_SW[3]), .Y(n1274)
);
AOI222X1TS U978 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n926), .B0(n1355), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1354), .C1(n961), .Y(n1270) );
AO22XLTS U979 ( .A0(n1555), .A1(DMP_SHT2_EWSW[0]), .B0(n1446), .B1(
DMP_SFG[0]), .Y(n768) );
AO22XLTS U980 ( .A0(n1404), .A1(DmP_EXP_EWSW[1]), .B0(n1398), .B1(
DmP_mant_SHT1_SW[1]), .Y(n658) );
AO22XLTS U981 ( .A0(n1404), .A1(DmP_EXP_EWSW[2]), .B0(n1409), .B1(
DmP_mant_SHT1_SW[2]), .Y(n656) );
AO22XLTS U982 ( .A0(n1404), .A1(DmP_EXP_EWSW[6]), .B0(n1406), .B1(
DmP_mant_SHT1_SW[6]), .Y(n648) );
AO22XLTS U983 ( .A0(n1404), .A1(DmP_EXP_EWSW[21]), .B0(n1398), .B1(
DmP_mant_SHT1_SW[21]), .Y(n618) );
AO22XLTS U984 ( .A0(n1410), .A1(DmP_EXP_EWSW[20]), .B0(n1406), .B1(
DmP_mant_SHT1_SW[20]), .Y(n620) );
AO22XLTS U985 ( .A0(n1404), .A1(DmP_EXP_EWSW[8]), .B0(n1409), .B1(
DmP_mant_SHT1_SW[8]), .Y(n644) );
AO22XLTS U986 ( .A0(n1404), .A1(DmP_EXP_EWSW[10]), .B0(n1406), .B1(
DmP_mant_SHT1_SW[10]), .Y(n640) );
AO22XLTS U987 ( .A0(n1404), .A1(DmP_EXP_EWSW[12]), .B0(n1398), .B1(
DmP_mant_SHT1_SW[12]), .Y(n636) );
AO22XLTS U988 ( .A0(n1404), .A1(DmP_EXP_EWSW[18]), .B0(n1409), .B1(
DmP_mant_SHT1_SW[18]), .Y(n624) );
AO22XLTS U989 ( .A0(n1404), .A1(DmP_EXP_EWSW[3]), .B0(n1665), .B1(
DmP_mant_SHT1_SW[3]), .Y(n654) );
AO22XLTS U990 ( .A0(n1404), .A1(DmP_EXP_EWSW[7]), .B0(n1406), .B1(
DmP_mant_SHT1_SW[7]), .Y(n646) );
AO22XLTS U991 ( .A0(n1410), .A1(DmP_EXP_EWSW[17]), .B0(n1406), .B1(
DmP_mant_SHT1_SW[17]), .Y(n626) );
AO22XLTS U992 ( .A0(n1555), .A1(DMP_SHT2_EWSW[8]), .B0(n1565), .B1(
DMP_SFG[8]), .Y(n744) );
AO22XLTS U993 ( .A0(n1555), .A1(DMP_SHT2_EWSW[5]), .B0(n1565), .B1(
DMP_SFG[5]), .Y(n753) );
AO22XLTS U994 ( .A0(n1408), .A1(DMP_SHT2_EWSW[7]), .B0(n1565), .B1(
DMP_SFG[7]), .Y(n747) );
AO22XLTS U995 ( .A0(n1555), .A1(DMP_SHT2_EWSW[9]), .B0(n1565), .B1(
DMP_SFG[9]), .Y(n741) );
AO22XLTS U996 ( .A0(n1332), .A1(n1475), .B0(n1333), .B1(n957), .Y(n916) );
AO22XLTS U997 ( .A0(n1337), .A1(Data_X[31]), .B0(n1335), .B1(intDX_EWSW[31]),
.Y(n882) );
AO22XLTS U998 ( .A0(n1555), .A1(DMP_SHT2_EWSW[1]), .B0(n1565), .B1(
DMP_SFG[1]), .Y(n765) );
AO22XLTS U999 ( .A0(n1555), .A1(DMP_SHT2_EWSW[10]), .B0(n1565), .B1(
DMP_SFG[10]), .Y(n738) );
AOI222X1TS U1000 ( .A0(n1499), .A1(DMP_SFG[10]), .B0(n1499), .B1(n1501),
.C0(DMP_SFG[10]), .C1(n1501), .Y(n1420) );
AO22XLTS U1001 ( .A0(n1475), .A1(n1474), .B0(n1473), .B1(Raw_mant_NRM_SWR[8]), .Y(n561) );
AO22XLTS U1002 ( .A0(n1555), .A1(n1536), .B0(n1446), .B1(n958), .Y(n570) );
AO22XLTS U1003 ( .A0(n1410), .A1(DmP_EXP_EWSW[15]), .B0(n1398), .B1(n963),
.Y(n630) );
AO22XLTS U1004 ( .A0(n1410), .A1(DmP_EXP_EWSW[13]), .B0(n1409), .B1(n964),
.Y(n634) );
AO22XLTS U1005 ( .A0(n1404), .A1(DmP_EXP_EWSW[11]), .B0(n1665), .B1(n965),
.Y(n638) );
AO22XLTS U1006 ( .A0(n1404), .A1(DmP_EXP_EWSW[9]), .B0(n1406), .B1(n966),
.Y(n642) );
AO22XLTS U1007 ( .A0(n1404), .A1(DmP_EXP_EWSW[5]), .B0(n1406), .B1(n967),
.Y(n650) );
AO22XLTS U1008 ( .A0(n1404), .A1(DmP_EXP_EWSW[4]), .B0(n1409), .B1(n961),
.Y(n652) );
AO22XLTS U1009 ( .A0(n1404), .A1(DmP_EXP_EWSW[0]), .B0(n1406), .B1(n968),
.Y(n660) );
AO22XLTS U1010 ( .A0(n1555), .A1(DMP_SHT2_EWSW[11]), .B0(n1565), .B1(n973),
.Y(n735) );
AO22XLTS U1011 ( .A0(n1555), .A1(DMP_SHT2_EWSW[6]), .B0(n1395), .B1(n970),
.Y(n750) );
AO22XLTS U1012 ( .A0(n1555), .A1(DMP_SHT2_EWSW[4]), .B0(n1446), .B1(n971),
.Y(n756) );
AO22XLTS U1013 ( .A0(n1333), .A1(busy), .B0(n1332), .B1(n957), .Y(n917) );
NOR2BX2TS U1014 ( .AN(n1317), .B(n1316), .Y(n1194) );
NAND4XLTS U1015 ( .A(n1570), .B(n977), .C(n933), .D(n1569), .Y(n1316) );
CLKINVX3TS U1016 ( .A(n1505), .Y(n1476) );
BUFX4TS U1017 ( .A(n1686), .Y(n1694) );
BUFX4TS U1018 ( .A(n983), .Y(n1679) );
BUFX4TS U1019 ( .A(n983), .Y(n1686) );
BUFX4TS U1020 ( .A(n983), .Y(n1681) );
BUFX4TS U1021 ( .A(n1686), .Y(n1693) );
BUFX4TS U1022 ( .A(n983), .Y(n1682) );
BUFX4TS U1023 ( .A(n1674), .Y(n1678) );
INVX2TS U1024 ( .A(n939), .Y(n955) );
INVX2TS U1025 ( .A(n929), .Y(n956) );
CLKINVX6TS U1026 ( .A(n1398), .Y(n1407) );
BUFX6TS U1027 ( .A(n1665), .Y(n1406) );
BUFX3TS U1028 ( .A(n925), .Y(n983) );
BUFX4TS U1029 ( .A(n1684), .Y(n1674) );
BUFX4TS U1030 ( .A(n1672), .Y(n1689) );
BUFX4TS U1031 ( .A(n1671), .Y(n1683) );
BUFX4TS U1032 ( .A(n1670), .Y(n1684) );
BUFX4TS U1033 ( .A(n1677), .Y(n1680) );
NOR2X4TS U1034 ( .A(n1004), .B(shift_value_SHT2_EWR[4]), .Y(n1438) );
BUFX6TS U1035 ( .A(n980), .Y(n1337) );
BUFX4TS U1036 ( .A(n980), .Y(n1341) );
BUFX4TS U1037 ( .A(n980), .Y(n1336) );
NOR2X2TS U1038 ( .A(n1605), .B(shift_value_SHT2_EWR[2]), .Y(n1422) );
BUFX4TS U1039 ( .A(n1675), .Y(n1672) );
BUFX4TS U1040 ( .A(n1673), .Y(n1670) );
BUFX4TS U1041 ( .A(n927), .Y(n1671) );
BUFX4TS U1042 ( .A(n1683), .Y(n1677) );
AOI22X2TS U1043 ( .A0(Data_array_SWR[22]), .A1(n1461), .B0(
Data_array_SWR[18]), .B1(n1462), .Y(n1486) );
OAI211X2TS U1044 ( .A0(n1603), .A1(n1202), .B0(n1201), .C0(n1200), .Y(n1220)
);
INVX2TS U1045 ( .A(n932), .Y(n957) );
INVX2TS U1046 ( .A(n942), .Y(n958) );
INVX2TS U1047 ( .A(n935), .Y(n959) );
AOI2BB2X2TS U1048 ( .B0(n1449), .B1(DmP_mant_SFG_SWR[9]), .A0N(
DmP_mant_SFG_SWR[9]), .A1N(n1449), .Y(n1434) );
INVX2TS U1049 ( .A(n941), .Y(n960) );
AOI2BB2X2TS U1050 ( .B0(n1449), .B1(DmP_mant_SFG_SWR[7]), .A0N(
DmP_mant_SFG_SWR[7]), .A1N(n1449), .Y(n1465) );
AOI2BB2X2TS U1051 ( .B0(n1449), .B1(DmP_mant_SFG_SWR[3]), .A0N(
DmP_mant_SFG_SWR[3]), .A1N(n934), .Y(n1454) );
INVX2TS U1052 ( .A(n954), .Y(n961) );
INVX2TS U1053 ( .A(n948), .Y(n962) );
INVX2TS U1054 ( .A(n947), .Y(n963) );
INVX2TS U1055 ( .A(n953), .Y(n964) );
INVX2TS U1056 ( .A(n952), .Y(n965) );
INVX2TS U1057 ( .A(n946), .Y(n966) );
INVX2TS U1058 ( .A(n951), .Y(n967) );
INVX2TS U1059 ( .A(n950), .Y(n968) );
INVX2TS U1060 ( .A(n949), .Y(n969) );
CLKINVX3TS U1061 ( .A(n1281), .Y(n1259) );
INVX2TS U1062 ( .A(n945), .Y(n970) );
INVX2TS U1063 ( .A(n944), .Y(n971) );
INVX2TS U1064 ( .A(n940), .Y(n972) );
CLKINVX3TS U1065 ( .A(n1545), .Y(n1548) );
NOR2X4TS U1066 ( .A(n1601), .B(shift_value_SHT2_EWR[3]), .Y(n1461) );
CLKINVX6TS U1067 ( .A(n1563), .Y(n1521) );
BUFX6TS U1068 ( .A(left_right_SHT2), .Y(n1563) );
INVX3TS U1069 ( .A(n1287), .Y(n1363) );
BUFX6TS U1070 ( .A(n1217), .Y(n1361) );
CLKINVX6TS U1071 ( .A(n1088), .Y(n1169) );
CLKINVX6TS U1072 ( .A(n1697), .Y(n1504) );
CLKINVX6TS U1073 ( .A(n1697), .Y(n1475) );
BUFX6TS U1074 ( .A(n1231), .Y(n1354) );
BUFX6TS U1075 ( .A(n1203), .Y(n1355) );
CLKINVX6TS U1076 ( .A(n1337), .Y(n1335) );
INVX3TS U1077 ( .A(n1565), .Y(n1555) );
INVX4TS U1078 ( .A(n1565), .Y(n1568) );
INVX2TS U1079 ( .A(n937), .Y(n973) );
INVX2TS U1080 ( .A(n938), .Y(n974) );
AOI222X4TS U1081 ( .A0(Data_array_SWR[20]), .A1(n1477), .B0(
Data_array_SWR[16]), .B1(n1476), .C0(Data_array_SWR[24]), .C1(n1005),
.Y(n1415) );
AOI32X1TS U1082 ( .A0(n1643), .A1(n1061), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1589), .Y(n1062) );
AOI221X1TS U1083 ( .A0(n1643), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1589), .C0(n1142), .Y(n1147) );
AOI221X1TS U1084 ( .A0(n930), .A1(n975), .B0(intDX_EWSW[11]), .B1(n1700),
.C0(n1150), .Y(n1155) );
AOI221X1TS U1085 ( .A0(n1628), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1642), .C0(n1135), .Y(n1139) );
INVX2TS U1086 ( .A(n928), .Y(n975) );
AOI221X1TS U1087 ( .A0(n1623), .A1(n976), .B0(intDX_EWSW[3]), .B1(n1699),
.C0(n1158), .Y(n1163) );
INVX2TS U1088 ( .A(n936), .Y(n976) );
AOI221X1TS U1089 ( .A0(n1639), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1638), .C0(n1141), .Y(n1148) );
AOI221X1TS U1090 ( .A0(n1587), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1631), .C0(n1144), .Y(n1145) );
AOI221X1TS U1091 ( .A0(n1626), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1701), .C0(n1152), .Y(n1153) );
OAI211X2TS U1092 ( .A0(intDX_EWSW[20]), .A1(n1627), .B0(n1069), .C0(n1055),
.Y(n1064) );
AOI221X1TS U1093 ( .A0(n1627), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1622), .C0(n1143), .Y(n1146) );
OAI211X2TS U1094 ( .A0(intDX_EWSW[12]), .A1(n1625), .B0(n1050), .C0(n1036),
.Y(n1052) );
AOI221X1TS U1095 ( .A0(n1625), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1621), .C0(n1151), .Y(n1154) );
AOI211X1TS U1096 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1196), .B0(n1212), .C0(
n1187), .Y(n1189) );
OAI31XLTS U1097 ( .A0(n1394), .A1(n1172), .A2(n1401), .B0(n1171), .Y(n771)
);
NOR2X2TS U1098 ( .A(n1237), .B(n923), .Y(n1324) );
NOR4BBX2TS U1099 ( .AN(n1214), .BN(n1213), .C(n1212), .D(n1211), .Y(n1237)
);
NOR2X2TS U1100 ( .A(n1374), .B(DMP_EXP_EWSW[23]), .Y(n1379) );
AOI22X2TS U1101 ( .A0(Data_array_SWR[21]), .A1(n1461), .B0(
Data_array_SWR[17]), .B1(n1462), .Y(n1469) );
NOR2X4TS U1102 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1462) );
XNOR2X2TS U1103 ( .A(DMP_exp_NRM2_EW[6]), .B(n994), .Y(n1325) );
XNOR2X2TS U1104 ( .A(DMP_exp_NRM2_EW[0]), .B(n1304), .Y(n1292) );
XNOR2X2TS U1105 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J26_123_2314_n4), .Y(
n1294) );
AOI222X1TS U1106 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n926), .B0(n1355), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1231), .C1(DmP_mant_SHT1_SW[7]), .Y(n1288)
);
AOI222X4TS U1107 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n926), .B0(n1355), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1354), .C1(DmP_mant_SHT1_SW[17]), .Y(n1282) );
AOI222X1TS U1108 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n926), .B0(n1355), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1354), .C1(DmP_mant_SHT1_SW[22]), .Y(n1264) );
OAI211XLTS U1109 ( .A0(DMP_SFG[9]), .A1(n955), .B0(n1493), .C0(DMP_SFG[8]),
.Y(n1418) );
NAND3X2TS U1110 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1582), .Y(n1506) );
NAND2X4TS U1111 ( .A(n923), .B(n1397), .Y(n1371) );
INVX3TS U1112 ( .A(n1088), .Y(n1399) );
AOI222X1TS U1113 ( .A0(n1534), .A1(n1521), .B0(n1564), .B1(Data_array_SWR[5]), .C0(n1533), .C1(n1481), .Y(n1532) );
AOI222X1TS U1114 ( .A0(n1534), .A1(n1563), .B0(Data_array_SWR[5]), .B1(n1540), .C0(n1533), .C1(n1538), .Y(n1557) );
AOI222X1TS U1115 ( .A0(n1529), .A1(n1521), .B0(n1564), .B1(Data_array_SWR[4]), .C0(n1528), .C1(n1481), .Y(n1527) );
AOI222X1TS U1116 ( .A0(n1529), .A1(n1563), .B0(Data_array_SWR[4]), .B1(n1540), .C0(n1528), .C1(n1538), .Y(n1559) );
CLKINVX6TS U1117 ( .A(n1696), .Y(n1449) );
INVX3TS U1118 ( .A(n1402), .Y(n1547) );
CLKINVX6TS U1119 ( .A(n1397), .Y(n1411) );
XOR2XLTS U1120 ( .A(n1499), .B(DMP_SFG[10]), .Y(n1500) );
AOI222X4TS U1121 ( .A0(Data_array_SWR[19]), .A1(n1461), .B0(
Data_array_SWR[23]), .B1(n1422), .C0(Data_array_SWR[15]), .C1(n1462),
.Y(n1488) );
AOI222X1TS U1122 ( .A0(Data_array_SWR[19]), .A1(n1477), .B0(
Data_array_SWR[23]), .B1(n1005), .C0(Data_array_SWR[15]), .C1(n1476),
.Y(n1414) );
NOR2X2TS U1123 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1615), .Y(n1330) );
NOR3X2TS U1124 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1202),
.Y(n1196) );
AOI32X1TS U1125 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1208), .A2(n1207), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1208), .Y(n1209) );
NOR2X2TS U1126 ( .A(Raw_mant_NRM_SWR[13]), .B(n1181), .Y(n1206) );
OAI21X2TS U1127 ( .A0(intDX_EWSW[18]), .A1(n1643), .B0(n1061), .Y(n1142) );
NOR3X1TS U1128 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1317) );
AND2X2TS U1129 ( .A(beg_OP), .B(n1334), .Y(n980) );
NOR2XLTS U1130 ( .A(n1700), .B(intDX_EWSW[11]), .Y(n1038) );
OAI21XLTS U1131 ( .A0(intDX_EWSW[15]), .A1(n1701), .B0(intDX_EWSW[14]), .Y(
n1046) );
NOR2XLTS U1132 ( .A(n1059), .B(intDY_EWSW[16]), .Y(n1060) );
OAI21XLTS U1133 ( .A0(intDX_EWSW[21]), .A1(n1622), .B0(intDX_EWSW[20]), .Y(
n1058) );
NOR2XLTS U1134 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1207) );
OAI21XLTS U1135 ( .A0(n973), .A1(n956), .B0(n1124), .Y(intadd_20_B_0_) );
OAI21XLTS U1136 ( .A0(n1172), .A1(n1079), .B0(n1169), .Y(n1170) );
OAI21XLTS U1137 ( .A0(DmP_EXP_EWSW[25]), .A1(n1650), .B0(n1383), .Y(n1380)
);
OAI21XLTS U1138 ( .A0(n1371), .A1(n1582), .B0(n1190), .Y(n818) );
OAI21XLTS U1139 ( .A0(n1330), .A1(n1180), .B0(n1327), .Y(n921) );
OAI211XLTS U1140 ( .A0(n1260), .A1(n1361), .B0(n1258), .C0(n1257), .Y(n833)
);
OAI21XLTS U1141 ( .A0(n1587), .A1(n1399), .B0(n1094), .Y(n617) );
OAI21XLTS U1142 ( .A0(n1588), .A1(n1169), .B0(n1098), .Y(n774) );
OAI21XLTS U1143 ( .A0(n1621), .A1(n1176), .B0(n1174), .Y(n791) );
INVX2TS U1144 ( .A(rst), .Y(n981) );
BUFX3TS U1145 ( .A(n925), .Y(n1685) );
BUFX3TS U1146 ( .A(n925), .Y(n1687) );
BUFX3TS U1147 ( .A(n925), .Y(n1688) );
BUFX3TS U1148 ( .A(n925), .Y(n1676) );
CLKBUFX2TS U1149 ( .A(n925), .Y(n982) );
BUFX3TS U1150 ( .A(n925), .Y(n1692) );
BUFX3TS U1151 ( .A(n925), .Y(n1673) );
BUFX3TS U1152 ( .A(n925), .Y(n1675) );
BUFX3TS U1153 ( .A(n1694), .Y(n1695) );
BUFX3TS U1154 ( .A(n925), .Y(n1690) );
BUFX3TS U1155 ( .A(n925), .Y(n1691) );
AO22XLTS U1156 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n923),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n604) );
AO22XLTS U1157 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n923),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n595) );
INVX1TS U1158 ( .A(DmP_mant_SFG_SWR[8]), .Y(n1432) );
AOI22X1TS U1159 ( .A0(n1449), .A1(DmP_mant_SFG_SWR[8]), .B0(n1432), .B1(
n1442), .Y(n1472) );
OAI211XLTS U1160 ( .A0(DMP_SFG[7]), .A1(n1434), .B0(n970), .C0(n1472), .Y(
n984) );
OAI2BB1X1TS U1161 ( .A0N(n1434), .A1N(DMP_SFG[7]), .B0(n984), .Y(n1494) );
INVX1TS U1162 ( .A(DmP_mant_SFG_SWR[10]), .Y(n1508) );
AOI22X1TS U1163 ( .A0(n1449), .A1(DmP_mant_SFG_SWR[10]), .B0(n1508), .B1(
n1442), .Y(n1493) );
AO22XLTS U1164 ( .A0(n1697), .A1(Raw_mant_NRM_SWR[10]), .B0(n1504), .B1(n985), .Y(n550) );
BUFX4TS U1165 ( .A(n1697), .Y(n1473) );
INVX1TS U1166 ( .A(DmP_mant_SFG_SWR[4]), .Y(n1482) );
AOI22X1TS U1167 ( .A0(n1449), .A1(n1482), .B0(DmP_mant_SFG_SWR[4]), .B1(
n1442), .Y(n1484) );
NAND2BXLTS U1168 ( .AN(n1484), .B(DMP_SFG[2]), .Y(n986) );
AOI222X1TS U1169 ( .A0(n1644), .A1(n972), .B0(n1644), .B1(n986), .C0(n972),
.C1(n986), .Y(n1464) );
AOI2BB2X1TS U1170 ( .B0(n1449), .B1(n960), .A0N(n960), .A1N(n1449), .Y(n1463) );
AO22XLTS U1171 ( .A0(n1473), .A1(Raw_mant_NRM_SWR[6]), .B0(n1504), .B1(n987),
.Y(n556) );
INVX2TS U1172 ( .A(DP_OP_15J26_123_2314_n4), .Y(n988) );
NAND2X1TS U1173 ( .A(n1616), .B(n988), .Y(n994) );
INVX1TS U1174 ( .A(LZD_output_NRM2_EW[0]), .Y(n1304) );
NOR2XLTS U1175 ( .A(n1292), .B(exp_rslt_NRM2_EW1[1]), .Y(n991) );
INVX2TS U1176 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n990) );
INVX2TS U1177 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n989) );
NAND4BXLTS U1178 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n991), .C(n990), .D(n989),
.Y(n992) );
NOR2XLTS U1179 ( .A(n992), .B(n1294), .Y(n993) );
INVX2TS U1180 ( .A(n994), .Y(n995) );
NAND2X1TS U1181 ( .A(n1632), .B(n995), .Y(n1297) );
XNOR2X1TS U1182 ( .A(DMP_exp_NRM2_EW[7]), .B(n1297), .Y(n1291) );
OR2X1TS U1183 ( .A(n996), .B(n1291), .Y(n1302) );
CLKBUFX2TS U1184 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1402) );
NAND2X2TS U1185 ( .A(n1302), .B(n1402), .Y(n1326) );
OA22X1TS U1186 ( .A0(n1326), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n810) );
OA22X1TS U1187 ( .A0(n1326), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n809) );
OA22X1TS U1188 ( .A0(n1326), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n811) );
OA22X1TS U1189 ( .A0(n1326), .A1(n1294), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n807) );
OA22X1TS U1190 ( .A0(n1326), .A1(n1292), .B0(final_result_ieee[23]), .B1(
Shift_reg_FLAGS_7[0]), .Y(n812) );
OA22X1TS U1191 ( .A0(n1326), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n808) );
BUFX3TS U1192 ( .A(n1395), .Y(n1492) );
INVX4TS U1193 ( .A(n1395), .Y(n1491) );
INVX2TS U1194 ( .A(n1462), .Y(n1004) );
OAI22X1TS U1195 ( .A0(n1575), .A1(n1506), .B0(n1648), .B1(n997), .Y(n999) );
NAND2X2TS U1196 ( .A(n1582), .B(n1461), .Y(n1505) );
OAI22X1TS U1197 ( .A0(n1469), .A1(n1582), .B0(n1656), .B1(n1505), .Y(n998)
);
OAI22X1TS U1198 ( .A0(n1445), .A1(n1521), .B0(n1576), .B1(n1000), .Y(n1544)
);
AO22XLTS U1199 ( .A0(n1492), .A1(DmP_mant_SFG_SWR[23]), .B0(n1491), .B1(
n1544), .Y(n516) );
OAI22X1TS U1200 ( .A0(n1593), .A1(n1506), .B0(n1649), .B1(n997), .Y(n1002)
);
OAI22X1TS U1201 ( .A0(n1486), .A1(n1582), .B0(n1657), .B1(n1505), .Y(n1001)
);
OAI22X1TS U1202 ( .A0(n1452), .A1(n1521), .B0(n1592), .B1(n1000), .Y(n1542)
);
AO22XLTS U1203 ( .A0(n1395), .A1(DmP_mant_SFG_SWR[22]), .B0(n1491), .B1(
n1542), .Y(n517) );
NOR2X2TS U1204 ( .A(shift_value_SHT2_EWR[4]), .B(n1563), .Y(n1538) );
INVX2TS U1205 ( .A(n1538), .Y(n1012) );
NOR2X2TS U1206 ( .A(n1582), .B(n1004), .Y(n1428) );
AOI22X1TS U1207 ( .A0(Data_array_SWR[18]), .A1(n1005), .B0(
Data_array_SWR[11]), .B1(n1476), .Y(n1006) );
OAI21XLTS U1208 ( .A0(n1593), .A1(n997), .B0(n1006), .Y(n1007) );
AOI21X1TS U1209 ( .A0(Data_array_SWR[22]), .A1(n1428), .B0(n1007), .Y(n1470)
);
OAI222X1TS U1210 ( .A0(n1003), .A1(n1657), .B0(n1012), .B1(n1469), .C0(n1521), .C1(n1470), .Y(n1531) );
AO22XLTS U1211 ( .A0(n1492), .A1(DmP_mant_SFG_SWR[18]), .B0(n1491), .B1(
n1531), .Y(n521) );
INVX4TS U1212 ( .A(n1395), .Y(n1408) );
AOI22X1TS U1213 ( .A0(Data_array_SWR[10]), .A1(n1476), .B0(
Data_array_SWR[17]), .B1(n1005), .Y(n1008) );
OAI21XLTS U1214 ( .A0(n1575), .A1(n997), .B0(n1008), .Y(n1009) );
AOI21X1TS U1215 ( .A0(Data_array_SWR[21]), .A1(n1428), .B0(n1009), .Y(n1487)
);
OAI222X1TS U1216 ( .A0(n1003), .A1(n1656), .B0(n1012), .B1(n1486), .C0(n1521), .C1(n1487), .Y(n1526) );
AO22XLTS U1217 ( .A0(n1492), .A1(DmP_mant_SFG_SWR[19]), .B0(n1408), .B1(
n1526), .Y(n520) );
INVX2TS U1218 ( .A(n997), .Y(n1477) );
AOI22X1TS U1219 ( .A0(Data_array_SWR[20]), .A1(n1005), .B0(
Data_array_SWR[16]), .B1(n1477), .Y(n1010) );
OAI2BB1X1TS U1220 ( .A0N(Data_array_SWR[13]), .A1N(n1476), .B0(n1010), .Y(
n1011) );
AOI21X1TS U1221 ( .A0(Data_array_SWR[24]), .A1(n1428), .B0(n1011), .Y(n1490)
);
OAI222X1TS U1222 ( .A0(n1003), .A1(n1660), .B0(n1012), .B1(n1488), .C0(n1521), .C1(n1490), .Y(n1524) );
AO22XLTS U1223 ( .A0(n1492), .A1(DmP_mant_SFG_SWR[16]), .B0(n1408), .B1(
n1524), .Y(n523) );
INVX2TS U1224 ( .A(n1000), .Y(n1564) );
INVX2TS U1225 ( .A(n1003), .Y(n1540) );
AOI22X1TS U1226 ( .A0(Data_array_SWR[12]), .A1(n1564), .B0(
Data_array_SWR[13]), .B1(n1540), .Y(n1013) );
OAI221X1TS U1227 ( .A0(n1563), .A1(n1414), .B0(n1521), .B1(n1415), .C0(n1013), .Y(n1512) );
AO22XLTS U1228 ( .A0(n1492), .A1(n959), .B0(n1491), .B1(n1512), .Y(n549) );
INVX4TS U1229 ( .A(n1397), .Y(busy) );
OAI21XLTS U1230 ( .A0(n1411), .A1(n1521), .B0(n923), .Y(n880) );
NOR2X1TS U1231 ( .A(n1636), .B(intDX_EWSW[25]), .Y(n1072) );
NOR2XLTS U1232 ( .A(n1072), .B(intDY_EWSW[24]), .Y(n1014) );
AOI22X1TS U1233 ( .A0(intDX_EWSW[25]), .A1(n1636), .B0(intDX_EWSW[24]), .B1(
n1014), .Y(n1018) );
OAI21X1TS U1234 ( .A0(intDX_EWSW[26]), .A1(n1635), .B0(n1015), .Y(n1073) );
NAND3XLTS U1235 ( .A(n1635), .B(n1015), .C(intDX_EWSW[26]), .Y(n1017) );
NAND2BXLTS U1236 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1016) );
OAI211XLTS U1237 ( .A0(n1018), .A1(n1073), .B0(n1017), .C0(n1016), .Y(n1023)
);
NOR2X1TS U1238 ( .A(n1610), .B(intDX_EWSW[30]), .Y(n1021) );
NOR2X1TS U1239 ( .A(n1583), .B(intDX_EWSW[29]), .Y(n1019) );
AOI211X1TS U1240 ( .A0(intDY_EWSW[28]), .A1(n1642), .B0(n1021), .C0(n1019),
.Y(n1071) );
NOR3X1TS U1241 ( .A(n1642), .B(n1019), .C(intDY_EWSW[28]), .Y(n1020) );
AOI221X1TS U1242 ( .A0(intDX_EWSW[30]), .A1(n1610), .B0(intDX_EWSW[29]),
.B1(n1583), .C0(n1020), .Y(n1022) );
AOI2BB2X1TS U1243 ( .B0(n1023), .B1(n1071), .A0N(n1022), .A1N(n1021), .Y(
n1077) );
NOR2X1TS U1244 ( .A(n1638), .B(intDX_EWSW[17]), .Y(n1059) );
OAI22X1TS U1245 ( .A0(n930), .A1(n975), .B0(n1700), .B1(intDX_EWSW[11]), .Y(
n1150) );
INVX2TS U1246 ( .A(n1150), .Y(n1043) );
OAI211XLTS U1247 ( .A0(intDX_EWSW[8]), .A1(n1640), .B0(n1040), .C0(n1043),
.Y(n1054) );
OAI2BB1X1TS U1248 ( .A0N(n1602), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1024) );
OAI22X1TS U1249 ( .A0(intDY_EWSW[4]), .A1(n1024), .B0(n1602), .B1(
intDY_EWSW[5]), .Y(n1035) );
OAI2BB1X1TS U1250 ( .A0N(n1581), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1025) );
OAI22X1TS U1251 ( .A0(intDY_EWSW[6]), .A1(n1025), .B0(n1581), .B1(
intDY_EWSW[7]), .Y(n1034) );
OAI21XLTS U1252 ( .A0(intDX_EWSW[1]), .A1(n1639), .B0(intDX_EWSW[0]), .Y(
n1026) );
OAI2BB2XLTS U1253 ( .B0(intDY_EWSW[0]), .B1(n1026), .A0N(intDX_EWSW[1]),
.A1N(n1639), .Y(n1028) );
OAI211XLTS U1254 ( .A0(n1699), .A1(intDX_EWSW[3]), .B0(n1028), .C0(n1027),
.Y(n1031) );
OAI21XLTS U1255 ( .A0(intDX_EWSW[3]), .A1(n1699), .B0(n976), .Y(n1029) );
AOI2BB2XLTS U1256 ( .B0(intDX_EWSW[3]), .B1(n1699), .A0N(intDY_EWSW[2]),
.A1N(n1029), .Y(n1030) );
AOI222X1TS U1257 ( .A0(intDY_EWSW[4]), .A1(n1579), .B0(n1031), .B1(n1030),
.C0(intDY_EWSW[5]), .C1(n1602), .Y(n1033) );
AOI22X1TS U1258 ( .A0(intDY_EWSW[7]), .A1(n1581), .B0(intDY_EWSW[6]), .B1(
n1604), .Y(n1032) );
OAI32X1TS U1259 ( .A0(n1035), .A1(n1034), .A2(n1033), .B0(n1032), .B1(n1034),
.Y(n1053) );
OA22X1TS U1260 ( .A0(n1626), .A1(intDX_EWSW[14]), .B0(n1701), .B1(
intDX_EWSW[15]), .Y(n1050) );
OAI21XLTS U1261 ( .A0(intDX_EWSW[13]), .A1(n1621), .B0(intDX_EWSW[12]), .Y(
n1037) );
OAI2BB2XLTS U1262 ( .B0(intDY_EWSW[12]), .B1(n1037), .A0N(intDX_EWSW[13]),
.A1N(n1621), .Y(n1049) );
NOR2XLTS U1263 ( .A(n1038), .B(intDY_EWSW[10]), .Y(n1039) );
AOI22X1TS U1264 ( .A0(intDX_EWSW[11]), .A1(n1700), .B0(n975), .B1(n1039),
.Y(n1045) );
NAND2BXLTS U1265 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1042) );
NAND3XLTS U1266 ( .A(n1640), .B(n1040), .C(intDX_EWSW[8]), .Y(n1041) );
AOI21X1TS U1267 ( .A0(n1042), .A1(n1041), .B0(n1052), .Y(n1044) );
OAI2BB2XLTS U1268 ( .B0(n1045), .B1(n1052), .A0N(n1044), .A1N(n1043), .Y(
n1048) );
AOI211X1TS U1269 ( .A0(n1050), .A1(n1049), .B0(n1048), .C0(n1047), .Y(n1051)
);
OAI31X1TS U1270 ( .A0(n1054), .A1(n1053), .A2(n1052), .B0(n1051), .Y(n1057)
);
OA22X1TS U1271 ( .A0(n1587), .A1(intDX_EWSW[22]), .B0(n1631), .B1(
intDX_EWSW[23]), .Y(n1069) );
AOI211XLTS U1272 ( .A0(intDY_EWSW[16]), .A1(n1609), .B0(n1064), .C0(n1142),
.Y(n1056) );
NAND3BXLTS U1273 ( .AN(n1059), .B(n1057), .C(n1056), .Y(n1076) );
OAI2BB2XLTS U1274 ( .B0(intDY_EWSW[20]), .B1(n1058), .A0N(intDX_EWSW[21]),
.A1N(n1622), .Y(n1068) );
AOI22X1TS U1275 ( .A0(intDX_EWSW[17]), .A1(n1638), .B0(intDX_EWSW[16]), .B1(
n1060), .Y(n1063) );
OAI32X1TS U1276 ( .A0(n1142), .A1(n1064), .A2(n1063), .B0(n1062), .B1(n1064),
.Y(n1067) );
OAI21XLTS U1277 ( .A0(intDX_EWSW[23]), .A1(n1631), .B0(intDX_EWSW[22]), .Y(
n1065) );
OAI2BB2XLTS U1278 ( .B0(intDY_EWSW[22]), .B1(n1065), .A0N(intDX_EWSW[23]),
.A1N(n1631), .Y(n1066) );
AOI211X1TS U1279 ( .A0(n1069), .A1(n1068), .B0(n1067), .C0(n1066), .Y(n1075)
);
NAND2BXLTS U1280 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1070) );
NAND4BBX1TS U1281 ( .AN(n1073), .BN(n1072), .C(n1071), .D(n1070), .Y(n1074)
);
AOI32X1TS U1282 ( .A0(n1077), .A1(n1076), .A2(n1075), .B0(n1074), .B1(n1077),
.Y(n1078) );
NOR2X1TS U1283 ( .A(n1078), .B(n979), .Y(n1089) );
INVX4TS U1284 ( .A(n1089), .Y(n1401) );
BUFX4TS U1285 ( .A(n1079), .Y(n1177) );
AOI22X1TS U1286 ( .A0(intDX_EWSW[22]), .A1(n1088), .B0(DMP_EXP_EWSW[22]),
.B1(n1177), .Y(n1080) );
OAI21XLTS U1287 ( .A0(n1587), .A1(n1401), .B0(n1080), .Y(n782) );
BUFX4TS U1288 ( .A(n1079), .Y(n1331) );
AOI22X1TS U1289 ( .A0(n969), .A1(n1331), .B0(intDX_EWSW[27]), .B1(n1088),
.Y(n1081) );
OAI21XLTS U1290 ( .A0(n1628), .A1(n1401), .B0(n1081), .Y(n777) );
AOI22X1TS U1291 ( .A0(intDX_EWSW[20]), .A1(n1088), .B0(DMP_EXP_EWSW[20]),
.B1(n1177), .Y(n1082) );
OAI21XLTS U1292 ( .A0(n1627), .A1(n1401), .B0(n1082), .Y(n784) );
INVX4TS U1293 ( .A(n1129), .Y(n1176) );
AOI22X1TS U1294 ( .A0(DMP_EXP_EWSW[23]), .A1(n1331), .B0(intDX_EWSW[23]),
.B1(n1088), .Y(n1083) );
OAI21XLTS U1295 ( .A0(n1631), .A1(n1176), .B0(n1083), .Y(n781) );
AOI22X1TS U1296 ( .A0(intDX_EWSW[4]), .A1(n1088), .B0(DMP_EXP_EWSW[4]), .B1(
n1079), .Y(n1084) );
OAI21XLTS U1297 ( .A0(n1624), .A1(n1401), .B0(n1084), .Y(n800) );
AOI22X1TS U1298 ( .A0(intDX_EWSW[5]), .A1(n1088), .B0(DMP_EXP_EWSW[5]), .B1(
n1079), .Y(n1085) );
OAI21XLTS U1299 ( .A0(n1585), .A1(n1176), .B0(n1085), .Y(n799) );
AOI22X1TS U1300 ( .A0(intDX_EWSW[6]), .A1(n1088), .B0(DMP_EXP_EWSW[6]), .B1(
n1079), .Y(n1086) );
OAI21XLTS U1301 ( .A0(n1619), .A1(n1176), .B0(n1086), .Y(n798) );
AOI22X1TS U1302 ( .A0(intDX_EWSW[7]), .A1(n1088), .B0(DMP_EXP_EWSW[7]), .B1(
n1079), .Y(n1087) );
OAI21XLTS U1303 ( .A0(n1629), .A1(n1176), .B0(n1087), .Y(n797) );
BUFX3TS U1304 ( .A(n1089), .Y(n1129) );
BUFX4TS U1305 ( .A(n1129), .Y(n1116) );
AOI22X1TS U1306 ( .A0(intDX_EWSW[18]), .A1(n1116), .B0(DmP_EXP_EWSW[18]),
.B1(n1331), .Y(n1090) );
OAI21XLTS U1307 ( .A0(n1643), .A1(n1399), .B0(n1090), .Y(n625) );
AOI22X1TS U1308 ( .A0(intDY_EWSW[28]), .A1(n1116), .B0(DMP_EXP_EWSW[28]),
.B1(n1177), .Y(n1091) );
OAI21XLTS U1309 ( .A0(n1642), .A1(n1399), .B0(n1091), .Y(n776) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[19]), .A1(n1116), .B0(DmP_EXP_EWSW[19]),
.B1(n1331), .Y(n1092) );
OAI21XLTS U1311 ( .A0(n1589), .A1(n1399), .B0(n1092), .Y(n623) );
AOI22X1TS U1312 ( .A0(intDX_EWSW[17]), .A1(n1116), .B0(DmP_EXP_EWSW[17]),
.B1(n1331), .Y(n1093) );
OAI21XLTS U1313 ( .A0(n1638), .A1(n1399), .B0(n1093), .Y(n627) );
AOI22X1TS U1314 ( .A0(intDX_EWSW[22]), .A1(n1116), .B0(DmP_EXP_EWSW[22]),
.B1(n1331), .Y(n1094) );
AOI22X1TS U1315 ( .A0(intDX_EWSW[20]), .A1(n1116), .B0(DmP_EXP_EWSW[20]),
.B1(n1331), .Y(n1095) );
OAI21XLTS U1316 ( .A0(n1627), .A1(n1399), .B0(n1095), .Y(n621) );
AOI22X1TS U1317 ( .A0(intDY_EWSW[29]), .A1(n1129), .B0(DMP_EXP_EWSW[29]),
.B1(n1177), .Y(n1096) );
OAI21XLTS U1318 ( .A0(n1630), .A1(n1169), .B0(n1096), .Y(n775) );
AOI22X1TS U1319 ( .A0(intDX_EWSW[12]), .A1(n1116), .B0(DmP_EXP_EWSW[12]),
.B1(n1079), .Y(n1097) );
OAI21XLTS U1320 ( .A0(n1625), .A1(n1169), .B0(n1097), .Y(n637) );
AOI22X1TS U1321 ( .A0(intDY_EWSW[30]), .A1(n1129), .B0(DMP_EXP_EWSW[30]),
.B1(n1177), .Y(n1098) );
AOI22X1TS U1322 ( .A0(intDX_EWSW[7]), .A1(n1129), .B0(DmP_EXP_EWSW[7]), .B1(
n1177), .Y(n1099) );
OAI21XLTS U1323 ( .A0(n1629), .A1(n1169), .B0(n1099), .Y(n647) );
AOI22X1TS U1324 ( .A0(intDX_EWSW[8]), .A1(n1116), .B0(DmP_EXP_EWSW[8]), .B1(
n1079), .Y(n1100) );
OAI21XLTS U1325 ( .A0(n1640), .A1(n1169), .B0(n1100), .Y(n645) );
AOI22X1TS U1326 ( .A0(intDX_EWSW[16]), .A1(n1116), .B0(DmP_EXP_EWSW[16]),
.B1(n1331), .Y(n1101) );
OAI21XLTS U1327 ( .A0(n1586), .A1(n1169), .B0(n1101), .Y(n629) );
AOI22X1TS U1328 ( .A0(intDX_EWSW[13]), .A1(n1116), .B0(DmP_EXP_EWSW[13]),
.B1(n1331), .Y(n1102) );
OAI21XLTS U1329 ( .A0(n1621), .A1(n1169), .B0(n1102), .Y(n635) );
AOI22X1TS U1330 ( .A0(intDX_EWSW[15]), .A1(n1116), .B0(DmP_EXP_EWSW[15]),
.B1(n1331), .Y(n1103) );
OAI21XLTS U1331 ( .A0(n1701), .A1(n1169), .B0(n1103), .Y(n631) );
AOI22X1TS U1332 ( .A0(intDX_EWSW[5]), .A1(n1116), .B0(DmP_EXP_EWSW[5]), .B1(
n1177), .Y(n1104) );
OAI21XLTS U1333 ( .A0(n1585), .A1(n1169), .B0(n1104), .Y(n651) );
AOI22X1TS U1334 ( .A0(intDX_EWSW[3]), .A1(n1129), .B0(DmP_EXP_EWSW[3]), .B1(
n1177), .Y(n1105) );
OAI21XLTS U1335 ( .A0(n1699), .A1(n1169), .B0(n1105), .Y(n655) );
AOI22X1TS U1336 ( .A0(n976), .A1(n1129), .B0(DmP_EXP_EWSW[2]), .B1(n1331),
.Y(n1106) );
OAI21XLTS U1337 ( .A0(n1623), .A1(n1169), .B0(n1106), .Y(n657) );
AOI22X1TS U1338 ( .A0(intDX_EWSW[14]), .A1(n1116), .B0(DmP_EXP_EWSW[14]),
.B1(n1177), .Y(n1107) );
OAI21XLTS U1339 ( .A0(n1626), .A1(n1169), .B0(n1107), .Y(n633) );
AOI22X1TS U1340 ( .A0(intDX_EWSW[9]), .A1(n1116), .B0(DmP_EXP_EWSW[9]), .B1(
n1177), .Y(n1108) );
OAI21XLTS U1341 ( .A0(n1620), .A1(n1169), .B0(n1108), .Y(n643) );
AOI22X1TS U1342 ( .A0(intDX_EWSW[1]), .A1(n1129), .B0(DmP_EXP_EWSW[1]), .B1(
n1331), .Y(n1109) );
OAI21XLTS U1343 ( .A0(n1639), .A1(n1169), .B0(n1109), .Y(n659) );
AOI22X1TS U1344 ( .A0(DmP_EXP_EWSW[27]), .A1(n1331), .B0(intDX_EWSW[27]),
.B1(n1129), .Y(n1110) );
OAI21XLTS U1345 ( .A0(n1628), .A1(n1169), .B0(n1110), .Y(n611) );
AOI22X1TS U1346 ( .A0(intDX_EWSW[6]), .A1(n1116), .B0(DmP_EXP_EWSW[6]), .B1(
n1331), .Y(n1111) );
OAI21XLTS U1347 ( .A0(n1619), .A1(n1169), .B0(n1111), .Y(n649) );
AOI22X1TS U1348 ( .A0(intDX_EWSW[4]), .A1(n1129), .B0(DmP_EXP_EWSW[4]), .B1(
n1079), .Y(n1112) );
OAI21XLTS U1349 ( .A0(n1624), .A1(n1169), .B0(n1112), .Y(n653) );
AOI22X1TS U1350 ( .A0(intDX_EWSW[0]), .A1(n1129), .B0(DmP_EXP_EWSW[0]), .B1(
n1177), .Y(n1113) );
OAI21XLTS U1351 ( .A0(n1637), .A1(n1169), .B0(n1113), .Y(n661) );
AOI22X1TS U1352 ( .A0(intDX_EWSW[11]), .A1(n1116), .B0(DmP_EXP_EWSW[11]),
.B1(n1331), .Y(n1114) );
OAI21XLTS U1353 ( .A0(n1700), .A1(n1169), .B0(n1114), .Y(n639) );
AOI22X1TS U1354 ( .A0(n975), .A1(n1116), .B0(DmP_EXP_EWSW[10]), .B1(n1177),
.Y(n1115) );
OAI21XLTS U1355 ( .A0(n930), .A1(n1169), .B0(n1115), .Y(n641) );
AOI22X1TS U1356 ( .A0(intDX_EWSW[21]), .A1(n1116), .B0(DmP_EXP_EWSW[21]),
.B1(n1331), .Y(n1117) );
OAI21XLTS U1357 ( .A0(n1622), .A1(n1399), .B0(n1117), .Y(n619) );
AOI22X1TS U1358 ( .A0(intDX_EWSW[0]), .A1(n1088), .B0(DMP_EXP_EWSW[0]), .B1(
n1079), .Y(n1118) );
OAI21XLTS U1359 ( .A0(n1637), .A1(n1401), .B0(n1118), .Y(n804) );
AOI22X1TS U1360 ( .A0(intDX_EWSW[9]), .A1(n1178), .B0(DMP_EXP_EWSW[9]), .B1(
n1079), .Y(n1119) );
OAI21XLTS U1361 ( .A0(n1620), .A1(n1176), .B0(n1119), .Y(n795) );
AOI22X1TS U1362 ( .A0(n976), .A1(n1088), .B0(DMP_EXP_EWSW[2]), .B1(n1079),
.Y(n1120) );
OAI21XLTS U1363 ( .A0(n1623), .A1(n1176), .B0(n1120), .Y(n802) );
AOI22X1TS U1364 ( .A0(intDX_EWSW[1]), .A1(n1088), .B0(DMP_EXP_EWSW[1]), .B1(
n1177), .Y(n1121) );
OAI21XLTS U1365 ( .A0(n1639), .A1(n1176), .B0(n1121), .Y(n803) );
AOI22X1TS U1366 ( .A0(intDX_EWSW[8]), .A1(n1088), .B0(DMP_EXP_EWSW[8]), .B1(
n1079), .Y(n1122) );
OAI21XLTS U1367 ( .A0(n1640), .A1(n1176), .B0(n1122), .Y(n796) );
AOI22X1TS U1368 ( .A0(intDX_EWSW[3]), .A1(n1088), .B0(DMP_EXP_EWSW[3]), .B1(
n1079), .Y(n1123) );
OAI21XLTS U1369 ( .A0(n1699), .A1(n1401), .B0(n1123), .Y(n801) );
AO22XLTS U1370 ( .A0(n973), .A1(n956), .B0(DMP_SFG[10]), .B1(n1501), .Y(
n1124) );
BUFX3TS U1371 ( .A(n1088), .Y(n1178) );
AOI22X1TS U1372 ( .A0(intDX_EWSW[16]), .A1(n1178), .B0(DMP_EXP_EWSW[16]),
.B1(n1177), .Y(n1125) );
OAI21XLTS U1373 ( .A0(n1586), .A1(n1176), .B0(n1125), .Y(n788) );
AOI22X1TS U1374 ( .A0(intDX_EWSW[19]), .A1(n1178), .B0(DMP_EXP_EWSW[19]),
.B1(n1177), .Y(n1126) );
OAI21XLTS U1375 ( .A0(n1589), .A1(n1401), .B0(n1126), .Y(n785) );
AOI22X1TS U1376 ( .A0(intDX_EWSW[18]), .A1(n1178), .B0(DMP_EXP_EWSW[18]),
.B1(n1177), .Y(n1127) );
OAI21XLTS U1377 ( .A0(n1643), .A1(n1176), .B0(n1127), .Y(n786) );
AOI22X1TS U1378 ( .A0(n975), .A1(n1178), .B0(DMP_EXP_EWSW[10]), .B1(n1079),
.Y(n1128) );
OAI21XLTS U1379 ( .A0(n930), .A1(n1176), .B0(n1128), .Y(n794) );
AOI222X1TS U1380 ( .A0(n1129), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1079), .C0(intDY_EWSW[23]), .C1(n1178), .Y(n1130) );
INVX2TS U1381 ( .A(n1130), .Y(n615) );
AOI22X1TS U1382 ( .A0(intDX_EWSW[14]), .A1(n1178), .B0(DMP_EXP_EWSW[14]),
.B1(n1079), .Y(n1131) );
OAI21XLTS U1383 ( .A0(n1626), .A1(n1176), .B0(n1131), .Y(n790) );
AOI22X1TS U1384 ( .A0(intDX_EWSW[17]), .A1(n1178), .B0(DMP_EXP_EWSW[17]),
.B1(n1177), .Y(n1132) );
OAI21XLTS U1385 ( .A0(n1638), .A1(n1176), .B0(n1132), .Y(n787) );
AOI22X1TS U1386 ( .A0(intDX_EWSW[12]), .A1(n1178), .B0(DMP_EXP_EWSW[12]),
.B1(n1079), .Y(n1133) );
OAI21XLTS U1387 ( .A0(n1625), .A1(n1176), .B0(n1133), .Y(n792) );
OAI22X1TS U1388 ( .A0(n1636), .A1(intDX_EWSW[25]), .B0(n1635), .B1(
intDX_EWSW[26]), .Y(n1134) );
AOI221X1TS U1389 ( .A0(n1636), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1635), .C0(n1134), .Y(n1140) );
OAI22X1TS U1390 ( .A0(n1628), .A1(intDX_EWSW[27]), .B0(n1642), .B1(
intDY_EWSW[28]), .Y(n1135) );
OAI22X1TS U1391 ( .A0(n1630), .A1(intDY_EWSW[29]), .B0(n1588), .B1(
intDY_EWSW[30]), .Y(n1136) );
AOI221X1TS U1392 ( .A0(n1630), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1588), .C0(n1136), .Y(n1138) );
AOI2BB2XLTS U1393 ( .B0(intDX_EWSW[7]), .B1(n1629), .A0N(n1629), .A1N(
intDX_EWSW[7]), .Y(n1137) );
NAND4XLTS U1394 ( .A(n1140), .B(n1139), .C(n1138), .D(n1137), .Y(n1168) );
OAI22X1TS U1395 ( .A0(n1639), .A1(intDX_EWSW[1]), .B0(n1638), .B1(
intDX_EWSW[17]), .Y(n1141) );
OAI22X1TS U1396 ( .A0(n1627), .A1(intDX_EWSW[20]), .B0(n1622), .B1(
intDX_EWSW[21]), .Y(n1143) );
OAI22X1TS U1397 ( .A0(n1587), .A1(intDX_EWSW[22]), .B0(n1631), .B1(
intDX_EWSW[23]), .Y(n1144) );
NAND4XLTS U1398 ( .A(n1148), .B(n1147), .C(n1146), .D(n1145), .Y(n1167) );
OAI22X1TS U1399 ( .A0(n1574), .A1(intDX_EWSW[24]), .B0(n1620), .B1(
intDX_EWSW[9]), .Y(n1149) );
AOI221X1TS U1400 ( .A0(n1574), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1620), .C0(n1149), .Y(n1156) );
OAI22X1TS U1401 ( .A0(n1625), .A1(intDX_EWSW[12]), .B0(n1621), .B1(
intDX_EWSW[13]), .Y(n1151) );
OAI22X1TS U1402 ( .A0(n1626), .A1(intDX_EWSW[14]), .B0(n1701), .B1(
intDX_EWSW[15]), .Y(n1152) );
NAND4XLTS U1403 ( .A(n1156), .B(n1155), .C(n1154), .D(n1153), .Y(n1166) );
OAI22X1TS U1404 ( .A0(n1586), .A1(intDX_EWSW[16]), .B0(n1637), .B1(
intDX_EWSW[0]), .Y(n1157) );
AOI221X1TS U1405 ( .A0(n1586), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1637), .C0(n1157), .Y(n1164) );
OAI22X1TS U1406 ( .A0(n1623), .A1(n976), .B0(n1699), .B1(intDX_EWSW[3]), .Y(
n1158) );
OAI22X1TS U1407 ( .A0(n1624), .A1(intDX_EWSW[4]), .B0(n1585), .B1(
intDX_EWSW[5]), .Y(n1159) );
AOI221X1TS U1408 ( .A0(n1624), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1585), .C0(n1159), .Y(n1162) );
OAI22X1TS U1409 ( .A0(n1640), .A1(intDX_EWSW[8]), .B0(n1619), .B1(
intDX_EWSW[6]), .Y(n1160) );
AOI221X1TS U1410 ( .A0(n1640), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1619), .C0(n1160), .Y(n1161) );
NAND4XLTS U1411 ( .A(n1164), .B(n1163), .C(n1162), .D(n1161), .Y(n1165) );
NOR4X1TS U1412 ( .A(n1168), .B(n1167), .C(n1166), .D(n1165), .Y(n1394) );
CLKXOR2X2TS U1413 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1392) );
INVX2TS U1414 ( .A(n1392), .Y(n1172) );
AOI22X1TS U1415 ( .A0(intDX_EWSW[31]), .A1(n1170), .B0(SIGN_FLAG_EXP), .B1(
n1331), .Y(n1171) );
AOI22X1TS U1416 ( .A0(intDX_EWSW[11]), .A1(n1178), .B0(DMP_EXP_EWSW[11]),
.B1(n1177), .Y(n1173) );
OAI21XLTS U1417 ( .A0(n1700), .A1(n1176), .B0(n1173), .Y(n793) );
AOI22X1TS U1418 ( .A0(intDX_EWSW[13]), .A1(n1178), .B0(DMP_EXP_EWSW[13]),
.B1(n1079), .Y(n1174) );
AOI22X1TS U1419 ( .A0(intDX_EWSW[15]), .A1(n1178), .B0(DMP_EXP_EWSW[15]),
.B1(n1079), .Y(n1175) );
OAI21XLTS U1420 ( .A0(n1701), .A1(n1176), .B0(n1175), .Y(n789) );
AOI22X1TS U1421 ( .A0(intDX_EWSW[21]), .A1(n1178), .B0(DMP_EXP_EWSW[21]),
.B1(n1177), .Y(n1179) );
OAI21XLTS U1422 ( .A0(n1622), .A1(n1401), .B0(n1179), .Y(n783) );
AOI2BB2XLTS U1423 ( .B0(beg_OP), .B1(n1584), .A0N(n1584), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1180) );
NAND3XLTS U1424 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1584), .C(
n1615), .Y(n1327) );
NOR2BX1TS U1425 ( .AN(n1194), .B(Raw_mant_NRM_SWR[18]), .Y(n1308) );
NOR3X1TS U1426 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1309) );
CLKAND2X2TS U1427 ( .A(n1308), .B(n1309), .Y(n1307) );
NAND2X1TS U1428 ( .A(n1307), .B(n1571), .Y(n1181) );
NAND2X1TS U1429 ( .A(n1206), .B(n1596), .Y(n1193) );
NOR2X1TS U1430 ( .A(Raw_mant_NRM_SWR[10]), .B(n1193), .Y(n1199) );
NAND2X1TS U1431 ( .A(n1199), .B(n1597), .Y(n1185) );
NOR3X1TS U1432 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1185),
.Y(n1182) );
NAND2X1TS U1433 ( .A(n1182), .B(n1598), .Y(n1202) );
NOR2XLTS U1434 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1184)
);
NAND2X1TS U1435 ( .A(n1196), .B(n1599), .Y(n1318) );
OAI21XLTS U1436 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1182), .Y(n1183) );
OAI21X1TS U1437 ( .A0(n1184), .A1(n1318), .B0(n1183), .Y(n1212) );
NOR2XLTS U1438 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1186)
);
NAND2BXLTS U1439 ( .AN(n1202), .B(Raw_mant_NRM_SWR[5]), .Y(n1319) );
OAI21XLTS U1440 ( .A0(n1186), .A1(n1185), .B0(n1319), .Y(n1187) );
NOR3X1TS U1441 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .C(n1318),
.Y(n1188) );
NAND2X1TS U1442 ( .A(n1188), .B(n974), .Y(n1198) );
NAND2X1TS U1443 ( .A(Raw_mant_NRM_SWR[1]), .B(n1188), .Y(n1311) );
AOI31X1TS U1444 ( .A0(n1189), .A1(n1198), .A2(n1311), .B0(n923), .Y(n1306)
);
AOI31XLTS U1445 ( .A0(n1411), .A1(Shift_amount_SHT1_EWR[4]), .A2(n923), .B0(
n1306), .Y(n1190) );
NAND2X1TS U1446 ( .A(Raw_mant_NRM_SWR[14]), .B(n1307), .Y(n1214) );
AOI32X1TS U1447 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n933), .A2(n1572), .B0(
Raw_mant_NRM_SWR[22]), .B1(n933), .Y(n1191) );
AOI32X1TS U1448 ( .A0(n977), .A1(n1214), .A2(n1191), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1214), .Y(n1192) );
AOI31XLTS U1449 ( .A0(n1194), .A1(Raw_mant_NRM_SWR[16]), .A2(n1573), .B0(
n1192), .Y(n1201) );
OAI21XLTS U1450 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1580), .B0(n1599), .Y(n1195) );
NOR3X1TS U1451 ( .A(Raw_mant_NRM_SWR[12]), .B(n1600), .C(n1193), .Y(n1314)
);
AO21XLTS U1452 ( .A0(n1194), .A1(Raw_mant_NRM_SWR[18]), .B0(n1314), .Y(n1205) );
AOI21X1TS U1453 ( .A0(n1196), .A1(n1195), .B0(n1205), .Y(n1197) );
NAND2X1TS U1454 ( .A(Raw_mant_NRM_SWR[12]), .B(n1206), .Y(n1312) );
OAI211X1TS U1455 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1198), .B0(n1197), .C0(
n1312), .Y(n1322) );
NOR2XLTS U1456 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n1203) );
NOR2BX1TS U1457 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1231) );
AOI31XLTS U1458 ( .A0(n1597), .A1(Raw_mant_NRM_SWR[11]), .A2(n1206), .B0(
n1205), .Y(n1213) );
NOR2XLTS U1459 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1210) );
NOR2X1TS U1460 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1208) );
AOI211X1TS U1461 ( .A0(n1210), .A1(n1209), .B0(Raw_mant_NRM_SWR[24]), .C0(
Raw_mant_NRM_SWR[25]), .Y(n1211) );
AOI21X1TS U1462 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n923), .B0(n1324), .Y(
n1216) );
NOR2X2TS U1463 ( .A(n1204), .B(n1216), .Y(n1365) );
NAND2X1TS U1464 ( .A(n1216), .B(n1371), .Y(n1217) );
INVX2TS U1465 ( .A(n1361), .Y(n1234) );
NAND2X2TS U1466 ( .A(n1220), .B(Shift_reg_FLAGS_7[1]), .Y(n1357) );
INVX2TS U1467 ( .A(n1357), .Y(n1344) );
AOI22X1TS U1468 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1344), .B0(n1354), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1219) );
AOI22X1TS U1469 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n926), .B0(n1355), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1218) );
NAND2X1TS U1470 ( .A(n1219), .B(n1218), .Y(n1248) );
AOI22X1TS U1471 ( .A0(n1204), .A1(Data_array_SWR[3]), .B0(n1234), .B1(n1248),
.Y(n1222) );
NAND2X1TS U1472 ( .A(n1324), .B(n1220), .Y(n1281) );
NAND2X1TS U1473 ( .A(Raw_mant_NRM_SWR[19]), .B(n1259), .Y(n1221) );
OAI211XLTS U1474 ( .A0(n1270), .A1(n1215), .B0(n1222), .C0(n1221), .Y(n825)
);
AOI22X1TS U1475 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1344), .B0(n1354), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1224) );
AOI22X1TS U1476 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n926), .B0(n1355), .B1(n967), .Y(n1223) );
NAND2X1TS U1477 ( .A(n1224), .B(n1223), .Y(n1267) );
AOI22X1TS U1478 ( .A0(n1204), .A1(Data_array_SWR[7]), .B0(n1234), .B1(n1267),
.Y(n1226) );
NAND2X1TS U1479 ( .A(Raw_mant_NRM_SWR[15]), .B(n1259), .Y(n1225) );
OAI211XLTS U1480 ( .A0(n1263), .A1(n1215), .B0(n1226), .C0(n1225), .Y(n829)
);
AOI22X1TS U1481 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1344), .B0(n1354), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1228) );
AOI22X1TS U1482 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n926), .B0(n1355), .B1(n968), .Y(n1227) );
NAND2X1TS U1483 ( .A(n1228), .B(n1227), .Y(n1364) );
AOI22X1TS U1484 ( .A0(n1204), .A1(Data_array_SWR[2]), .B0(n1234), .B1(n1364),
.Y(n1230) );
NAND2X1TS U1485 ( .A(Raw_mant_NRM_SWR[20]), .B(n1259), .Y(n1229) );
OAI211XLTS U1486 ( .A0(n1274), .A1(n1215), .B0(n1230), .C0(n1229), .Y(n824)
);
AOI22X1TS U1487 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1344), .B0(n1354), .B1(
n967), .Y(n1233) );
AOI22X1TS U1488 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n926), .B0(n1355), .B1(n961), .Y(n1232) );
NAND2X1TS U1489 ( .A(n1233), .B(n1232), .Y(n1271) );
AOI22X1TS U1490 ( .A0(n1204), .A1(Data_array_SWR[6]), .B0(n1234), .B1(n1271),
.Y(n1236) );
NAND2X1TS U1491 ( .A(Raw_mant_NRM_SWR[16]), .B(n1259), .Y(n1235) );
OAI211XLTS U1492 ( .A0(n1288), .A1(n1215), .B0(n1236), .C0(n1235), .Y(n828)
);
AOI22X1TS U1493 ( .A0(n1204), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1259), .Y(n1239) );
NAND2X1TS U1494 ( .A(n1237), .B(n1344), .Y(n1287) );
AOI2BB2XLTS U1495 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1363), .A0N(n1247),
.A1N(n1215), .Y(n1238) );
OAI211XLTS U1496 ( .A0(n1256), .A1(n1361), .B0(n1239), .C0(n1238), .Y(n835)
);
AOI22X1TS U1497 ( .A0(n1204), .A1(Data_array_SWR[20]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1259), .Y(n1241) );
AOI2BB2XLTS U1498 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1363), .A0N(n1264), .A1N(
n1215), .Y(n1240) );
OAI211XLTS U1499 ( .A0(n1252), .A1(n1361), .B0(n1241), .C0(n1240), .Y(n843)
);
AOI22X1TS U1500 ( .A0(n1204), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1259), .Y(n1243) );
AOI2BB2XLTS U1501 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1363), .A0N(n1255), .A1N(
n1215), .Y(n1242) );
OAI211XLTS U1502 ( .A0(n1244), .A1(n1361), .B0(n1243), .C0(n1242), .Y(n839)
);
AOI22X1TS U1503 ( .A0(n1204), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1259), .Y(n1246) );
AOI2BB2XLTS U1504 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1363), .A0N(n1244), .A1N(
n1215), .Y(n1245) );
OAI211XLTS U1505 ( .A0(n1247), .A1(n1361), .B0(n1246), .C0(n1245), .Y(n837)
);
AOI22X1TS U1506 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n926), .B0(n1354), .B1(n968), .Y(n1251) );
AOI22X1TS U1507 ( .A0(n1204), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1363), .Y(n1250) );
NAND2X1TS U1508 ( .A(n1365), .B(n1248), .Y(n1249) );
OAI211XLTS U1509 ( .A0(n1251), .A1(n1361), .B0(n1250), .C0(n1249), .Y(n823)
);
AOI22X1TS U1510 ( .A0(n1204), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1259), .Y(n1254) );
AOI2BB2XLTS U1511 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1363), .A0N(n1252), .A1N(
n1215), .Y(n1253) );
OAI211XLTS U1512 ( .A0(n1255), .A1(n1361), .B0(n1254), .C0(n1253), .Y(n841)
);
AOI22X1TS U1513 ( .A0(n1204), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1259), .Y(n1258) );
AOI2BB2XLTS U1514 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1363), .A0N(n1256),
.A1N(n1215), .Y(n1257) );
AOI22X1TS U1515 ( .A0(n1204), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1259), .Y(n1262) );
AOI2BB2XLTS U1516 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1363), .A0N(n1260),
.A1N(n1215), .Y(n1261) );
OAI211XLTS U1517 ( .A0(n1263), .A1(n1361), .B0(n1262), .C0(n1261), .Y(n831)
);
AOI21X1TS U1518 ( .A0(n926), .A1(n974), .B0(n1355), .Y(n1342) );
OAI22X1TS U1519 ( .A0(n1264), .A1(n1361), .B0(n1371), .B1(n1576), .Y(n1265)
);
AOI21X1TS U1520 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1363), .B0(n1265), .Y(n1266) );
OAI21XLTS U1521 ( .A0(n1342), .A1(n1215), .B0(n1266), .Y(n845) );
AOI22X1TS U1522 ( .A0(n1204), .A1(Data_array_SWR[5]), .B0(n1365), .B1(n1267),
.Y(n1269) );
NAND2X1TS U1523 ( .A(Raw_mant_NRM_SWR[19]), .B(n1363), .Y(n1268) );
OAI211XLTS U1524 ( .A0(n1270), .A1(n1361), .B0(n1269), .C0(n1268), .Y(n827)
);
AOI22X1TS U1525 ( .A0(n1204), .A1(Data_array_SWR[4]), .B0(n1365), .B1(n1271),
.Y(n1273) );
NAND2X1TS U1526 ( .A(Raw_mant_NRM_SWR[20]), .B(n1363), .Y(n1272) );
OAI211XLTS U1527 ( .A0(n1274), .A1(n1361), .B0(n1273), .C0(n1272), .Y(n826)
);
AOI22X1TS U1528 ( .A0(n1355), .A1(DmP_mant_SHT1_SW[18]), .B0(n1354), .B1(
n962), .Y(n1275) );
OAI21XLTS U1529 ( .A0(n1599), .A1(n1357), .B0(n1275), .Y(n1276) );
AOI21X1TS U1530 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n926), .B0(n1276), .Y(n1349)
);
OAI22X1TS U1531 ( .A0(n1282), .A1(n1361), .B0(n1603), .B1(n1287), .Y(n1277)
);
AOI21X1TS U1532 ( .A0(n1204), .A1(Data_array_SWR[17]), .B0(n1277), .Y(n1278)
);
OAI21XLTS U1533 ( .A0(n1349), .A1(n1215), .B0(n1278), .Y(n840) );
AOI22X1TS U1534 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1344), .B0(n1354), .B1(n963), .Y(n1279) );
OAI21XLTS U1535 ( .A0(n1608), .A1(n1346), .B0(n1279), .Y(n1280) );
AOI21X1TS U1536 ( .A0(n1355), .A1(DmP_mant_SHT1_SW[14]), .B0(n1280), .Y(
n1353) );
OAI22X1TS U1537 ( .A0(n1282), .A1(n1215), .B0(n1603), .B1(n1281), .Y(n1283)
);
AOI21X1TS U1538 ( .A0(n1204), .A1(Data_array_SWR[15]), .B0(n1283), .Y(n1284)
);
OAI21XLTS U1539 ( .A0(n1353), .A1(n1361), .B0(n1284), .Y(n838) );
AOI22X1TS U1540 ( .A0(n1355), .A1(DmP_mant_SHT1_SW[8]), .B0(n1354), .B1(n966), .Y(n1285) );
OAI21XLTS U1541 ( .A0(n1571), .A1(n1357), .B0(n1285), .Y(n1286) );
AOI21X1TS U1542 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n926), .B0(n1286), .Y(n1360) );
OAI22X1TS U1543 ( .A0(n1288), .A1(n1361), .B0(n1577), .B1(n1287), .Y(n1289)
);
AOI21X1TS U1544 ( .A0(n1204), .A1(Data_array_SWR[8]), .B0(n1289), .Y(n1290)
);
OAI21XLTS U1545 ( .A0(n1360), .A1(n1215), .B0(n1290), .Y(n830) );
INVX2TS U1546 ( .A(n1291), .Y(n1301) );
AND4X1TS U1547 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1292), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1293) );
NAND3XLTS U1548 ( .A(n1294), .B(exp_rslt_NRM2_EW1[4]), .C(n1293), .Y(n1295)
);
NAND2BXLTS U1549 ( .AN(n1295), .B(n1325), .Y(n1296) );
NOR2XLTS U1550 ( .A(n1301), .B(n1296), .Y(n1300) );
INVX2TS U1551 ( .A(n1297), .Y(n1298) );
CLKAND2X2TS U1552 ( .A(n1645), .B(n1298), .Y(n1299) );
OAI2BB1X1TS U1553 ( .A0N(n1300), .A1N(n1299), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1509) );
OAI2BB2XLTS U1554 ( .B0(n1509), .B1(n1301), .A0N(final_result_ieee[30]),
.A1N(n1547), .Y(n805) );
INVX2TS U1555 ( .A(n1302), .Y(n1510) );
NOR2XLTS U1556 ( .A(n1510), .B(SIGN_FLAG_SHT1SHT2), .Y(n1303) );
OAI2BB2XLTS U1557 ( .B0(n1303), .B1(n1509), .A0N(n1547), .A1N(
final_result_ieee[31]), .Y(n594) );
INVX2TS U1558 ( .A(n1304), .Y(n1305) );
NAND2X1TS U1559 ( .A(n1606), .B(n1305), .Y(DP_OP_15J26_123_2314_n8) );
MX2X1TS U1560 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n662) );
MX2X1TS U1561 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n667) );
MX2X1TS U1562 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n672) );
MX2X1TS U1563 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n677) );
MX2X1TS U1564 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n682) );
MX2X1TS U1565 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n687) );
MX2X1TS U1566 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n692) );
MX2X1TS U1567 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n697) );
AO21XLTS U1568 ( .A0(LZD_output_NRM2_EW[4]), .A1(n923), .B0(n1306), .Y(n579)
);
OAI211X1TS U1569 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1307), .C0(n1571), .Y(n1315) );
OAI2BB1X1TS U1570 ( .A0N(n1309), .A1N(n1571), .B0(n1308), .Y(n1310) );
NAND4XLTS U1571 ( .A(n1312), .B(n1315), .C(n1311), .D(n1310), .Y(n1313) );
OAI21X1TS U1572 ( .A0(n1314), .A1(n1313), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1372) );
OAI2BB1X1TS U1573 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n923), .B0(n1372), .Y(
n567) );
OAI21XLTS U1574 ( .A0(n1317), .A1(n1316), .B0(n1315), .Y(n1323) );
OAI22X1TS U1575 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1319), .B0(n1318), .B1(
n1641), .Y(n1321) );
OAI31X1TS U1576 ( .A0(n1323), .A1(n1322), .A2(n1321), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1368) );
OAI2BB1X1TS U1577 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n923), .B0(n1368), .Y(
n576) );
AO21XLTS U1578 ( .A0(LZD_output_NRM2_EW[1]), .A1(n923), .B0(n1324), .Y(n573)
);
OAI2BB1X1TS U1579 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n923), .B0(n1357), .Y(
n560) );
OA22X1TS U1580 ( .A0(n1326), .A1(n1325), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n806) );
OA21XLTS U1581 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1509),
.Y(n609) );
INVX2TS U1582 ( .A(n1330), .Y(n1328) );
AOI22X1TS U1583 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1328), .B1(n1584), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1584 ( .A(n1328), .B(n1327), .Y(n922) );
NOR2XLTS U1585 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1329) );
AOI32X4TS U1586 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1329), .B1(n1615), .Y(n1333)
);
INVX2TS U1587 ( .A(n1333), .Y(n1332) );
AOI22X1TS U1588 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1330), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1584), .Y(n1334) );
AO22XLTS U1589 ( .A0(n1332), .A1(Shift_reg_FLAGS_7_6), .B0(n1333), .B1(n1334), .Y(n920) );
AOI22X1TS U1590 ( .A0(n1333), .A1(n1331), .B0(n1409), .B1(n1332), .Y(n919)
);
AOI22X1TS U1591 ( .A0(n1333), .A1(n1406), .B0(n1397), .B1(n1332), .Y(n918)
);
AOI22X1TS U1592 ( .A0(n1333), .A1(n1697), .B0(n923), .B1(n1332), .Y(n915) );
AOI22X1TS U1593 ( .A0(n1333), .A1(n923), .B0(n1547), .B1(n1332), .Y(n914) );
AO22XLTS U1594 ( .A0(n1337), .A1(Data_X[0]), .B0(n1339), .B1(intDX_EWSW[0]),
.Y(n913) );
AO22XLTS U1595 ( .A0(n1336), .A1(Data_X[1]), .B0(n1335), .B1(intDX_EWSW[1]),
.Y(n912) );
AO22XLTS U1596 ( .A0(n1336), .A1(Data_X[2]), .B0(n1335), .B1(n976), .Y(n911)
);
AO22XLTS U1597 ( .A0(n1341), .A1(Data_X[3]), .B0(n1335), .B1(intDX_EWSW[3]),
.Y(n910) );
AO22XLTS U1598 ( .A0(n1341), .A1(Data_X[4]), .B0(n1339), .B1(intDX_EWSW[4]),
.Y(n909) );
AO22XLTS U1599 ( .A0(n1336), .A1(Data_X[5]), .B0(n1335), .B1(intDX_EWSW[5]),
.Y(n908) );
AO22XLTS U1600 ( .A0(n1337), .A1(Data_X[6]), .B0(n1335), .B1(intDX_EWSW[6]),
.Y(n907) );
AO22XLTS U1601 ( .A0(n1337), .A1(Data_X[7]), .B0(n1335), .B1(intDX_EWSW[7]),
.Y(n906) );
AO22XLTS U1602 ( .A0(n1341), .A1(Data_X[8]), .B0(n1339), .B1(intDX_EWSW[8]),
.Y(n905) );
AO22XLTS U1603 ( .A0(n1336), .A1(Data_X[9]), .B0(n1335), .B1(intDX_EWSW[9]),
.Y(n904) );
AO22XLTS U1604 ( .A0(n1337), .A1(Data_X[10]), .B0(n1339), .B1(n975), .Y(n903) );
AO22XLTS U1605 ( .A0(n1336), .A1(Data_X[11]), .B0(n1339), .B1(intDX_EWSW[11]), .Y(n902) );
AO22XLTS U1606 ( .A0(n1337), .A1(Data_X[12]), .B0(n1340), .B1(intDX_EWSW[12]), .Y(n901) );
AO22XLTS U1607 ( .A0(n1336), .A1(Data_X[13]), .B0(n1340), .B1(intDX_EWSW[13]), .Y(n900) );
AO22XLTS U1608 ( .A0(n1336), .A1(Data_X[14]), .B0(n1340), .B1(intDX_EWSW[14]), .Y(n899) );
AO22XLTS U1609 ( .A0(n1341), .A1(Data_X[15]), .B0(n1340), .B1(intDX_EWSW[15]), .Y(n898) );
AO22XLTS U1610 ( .A0(n1336), .A1(Data_X[16]), .B0(n1340), .B1(intDX_EWSW[16]), .Y(n897) );
AO22XLTS U1611 ( .A0(n1337), .A1(Data_X[17]), .B0(n1340), .B1(intDX_EWSW[17]), .Y(n896) );
AO22XLTS U1612 ( .A0(n1337), .A1(Data_X[18]), .B0(n1340), .B1(intDX_EWSW[18]), .Y(n895) );
AO22XLTS U1613 ( .A0(n1337), .A1(Data_X[19]), .B0(n1340), .B1(intDX_EWSW[19]), .Y(n894) );
AO22XLTS U1614 ( .A0(n1337), .A1(Data_X[20]), .B0(n1340), .B1(intDX_EWSW[20]), .Y(n893) );
AO22XLTS U1615 ( .A0(n1341), .A1(Data_X[21]), .B0(n1340), .B1(intDX_EWSW[21]), .Y(n892) );
AO22XLTS U1616 ( .A0(n1341), .A1(Data_X[22]), .B0(n1340), .B1(intDX_EWSW[22]), .Y(n891) );
AO22XLTS U1617 ( .A0(n1337), .A1(Data_X[23]), .B0(n1340), .B1(intDX_EWSW[23]), .Y(n890) );
AO22XLTS U1618 ( .A0(n1335), .A1(intDX_EWSW[24]), .B0(n980), .B1(Data_X[24]),
.Y(n889) );
AO22XLTS U1619 ( .A0(n1335), .A1(intDX_EWSW[25]), .B0(n1337), .B1(Data_X[25]), .Y(n888) );
AO22XLTS U1620 ( .A0(n1339), .A1(intDX_EWSW[26]), .B0(n1341), .B1(Data_X[26]), .Y(n887) );
AO22XLTS U1621 ( .A0(n1341), .A1(Data_X[27]), .B0(n1335), .B1(intDX_EWSW[27]), .Y(n886) );
AO22XLTS U1622 ( .A0(n1335), .A1(intDX_EWSW[28]), .B0(n1341), .B1(Data_X[28]), .Y(n885) );
AO22XLTS U1623 ( .A0(n1335), .A1(intDX_EWSW[29]), .B0(n1341), .B1(Data_X[29]), .Y(n884) );
AO22XLTS U1624 ( .A0(n1339), .A1(intDX_EWSW[30]), .B0(n1336), .B1(Data_X[30]), .Y(n883) );
AO22XLTS U1625 ( .A0(n1341), .A1(add_subt), .B0(n1339), .B1(intAS), .Y(n881)
);
AO22XLTS U1626 ( .A0(n1335), .A1(intDY_EWSW[0]), .B0(n1337), .B1(Data_Y[0]),
.Y(n879) );
AO22XLTS U1627 ( .A0(n1335), .A1(intDY_EWSW[1]), .B0(n1336), .B1(Data_Y[1]),
.Y(n878) );
AO22XLTS U1628 ( .A0(n1335), .A1(intDY_EWSW[2]), .B0(n1337), .B1(Data_Y[2]),
.Y(n877) );
AO22XLTS U1629 ( .A0(n1339), .A1(intDY_EWSW[3]), .B0(n1337), .B1(Data_Y[3]),
.Y(n876) );
INVX4TS U1630 ( .A(n980), .Y(n1338) );
AO22XLTS U1631 ( .A0(n1338), .A1(intDY_EWSW[4]), .B0(n1341), .B1(Data_Y[4]),
.Y(n875) );
AO22XLTS U1632 ( .A0(n1338), .A1(intDY_EWSW[5]), .B0(n1336), .B1(Data_Y[5]),
.Y(n874) );
AO22XLTS U1633 ( .A0(n1339), .A1(intDY_EWSW[6]), .B0(n1337), .B1(Data_Y[6]),
.Y(n873) );
AO22XLTS U1634 ( .A0(n1335), .A1(intDY_EWSW[7]), .B0(n980), .B1(Data_Y[7]),
.Y(n872) );
AO22XLTS U1635 ( .A0(n1338), .A1(intDY_EWSW[8]), .B0(n1336), .B1(Data_Y[8]),
.Y(n871) );
AO22XLTS U1636 ( .A0(n1335), .A1(intDY_EWSW[9]), .B0(n1336), .B1(Data_Y[9]),
.Y(n870) );
AO22XLTS U1637 ( .A0(n1339), .A1(intDY_EWSW[10]), .B0(n980), .B1(Data_Y[10]),
.Y(n869) );
AO22XLTS U1638 ( .A0(n1335), .A1(intDY_EWSW[11]), .B0(n1336), .B1(Data_Y[11]), .Y(n868) );
AO22XLTS U1639 ( .A0(n1338), .A1(intDY_EWSW[12]), .B0(n1337), .B1(Data_Y[12]), .Y(n867) );
AO22XLTS U1640 ( .A0(n1338), .A1(intDY_EWSW[13]), .B0(n1336), .B1(Data_Y[13]), .Y(n866) );
AO22XLTS U1641 ( .A0(n1338), .A1(intDY_EWSW[14]), .B0(n1341), .B1(Data_Y[14]), .Y(n865) );
AO22XLTS U1642 ( .A0(n1335), .A1(intDY_EWSW[15]), .B0(n1337), .B1(Data_Y[15]), .Y(n864) );
AO22XLTS U1643 ( .A0(n1338), .A1(intDY_EWSW[16]), .B0(n980), .B1(Data_Y[16]),
.Y(n863) );
AO22XLTS U1644 ( .A0(n1338), .A1(intDY_EWSW[17]), .B0(n1337), .B1(Data_Y[17]), .Y(n862) );
AO22XLTS U1645 ( .A0(n1338), .A1(intDY_EWSW[18]), .B0(n1341), .B1(Data_Y[18]), .Y(n861) );
AO22XLTS U1646 ( .A0(n1338), .A1(intDY_EWSW[19]), .B0(n980), .B1(Data_Y[19]),
.Y(n860) );
AO22XLTS U1647 ( .A0(n1338), .A1(intDY_EWSW[20]), .B0(n1337), .B1(Data_Y[20]), .Y(n859) );
AO22XLTS U1648 ( .A0(n1338), .A1(intDY_EWSW[21]), .B0(n1341), .B1(Data_Y[21]), .Y(n858) );
AO22XLTS U1649 ( .A0(n1338), .A1(intDY_EWSW[22]), .B0(n1336), .B1(Data_Y[22]), .Y(n857) );
AO22XLTS U1650 ( .A0(n1338), .A1(intDY_EWSW[23]), .B0(n1337), .B1(Data_Y[23]), .Y(n856) );
AO22XLTS U1651 ( .A0(n1338), .A1(intDY_EWSW[24]), .B0(n1341), .B1(Data_Y[24]), .Y(n855) );
AO22XLTS U1652 ( .A0(n1338), .A1(intDY_EWSW[25]), .B0(n1341), .B1(Data_Y[25]), .Y(n854) );
AO22XLTS U1653 ( .A0(n1338), .A1(intDY_EWSW[26]), .B0(n1336), .B1(Data_Y[26]), .Y(n853) );
AO22XLTS U1654 ( .A0(n1338), .A1(intDY_EWSW[27]), .B0(n1337), .B1(Data_Y[27]), .Y(n852) );
AO22XLTS U1655 ( .A0(n1337), .A1(Data_Y[28]), .B0(n1335), .B1(intDY_EWSW[28]), .Y(n851) );
AO22XLTS U1656 ( .A0(n1337), .A1(Data_Y[29]), .B0(n1335), .B1(intDY_EWSW[29]), .Y(n850) );
AO22XLTS U1657 ( .A0(n1336), .A1(Data_Y[30]), .B0(n1335), .B1(intDY_EWSW[30]), .Y(n849) );
AO22XLTS U1658 ( .A0(n1341), .A1(Data_Y[31]), .B0(n1339), .B1(intDY_EWSW[31]), .Y(n848) );
OAI2BB2XLTS U1659 ( .B0(n1342), .B1(n1361), .A0N(n1204), .A1N(
Data_array_SWR[24]), .Y(n847) );
AO22XLTS U1660 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n926), .B0(n974), .B1(n1344),
.Y(n1343) );
OAI2BB2XLTS U1661 ( .B0(n1348), .B1(n1361), .A0N(n1204), .A1N(
Data_array_SWR[23]), .Y(n846) );
AOI22X1TS U1662 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1344), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1354), .Y(n1345) );
OAI21XLTS U1663 ( .A0(n1641), .A1(n1346), .B0(n1345), .Y(n1347) );
AOI21X1TS U1664 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n1355), .B0(n1347), .Y(
n1350) );
OAI222X1TS U1665 ( .A0(n1371), .A1(n1592), .B0(n1215), .B1(n1348), .C0(n1361), .C1(n1350), .Y(n844) );
OAI222X1TS U1666 ( .A0(n1663), .A1(n1371), .B0(n1215), .B1(n1350), .C0(n1361), .C1(n1349), .Y(n842) );
AOI22X1TS U1667 ( .A0(n1355), .A1(DmP_mant_SHT1_SW[12]), .B0(n1354), .B1(
n964), .Y(n1351) );
OAI21XLTS U1668 ( .A0(n1600), .A1(n1357), .B0(n1351), .Y(n1352) );
AOI21X1TS U1669 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n926), .B0(n1352), .Y(n1359) );
OAI222X1TS U1670 ( .A0(n1575), .A1(n1371), .B0(n1215), .B1(n1353), .C0(n1361), .C1(n1359), .Y(n836) );
AOI22X1TS U1671 ( .A0(n1355), .A1(DmP_mant_SHT1_SW[10]), .B0(n1354), .B1(
n965), .Y(n1356) );
OAI21XLTS U1672 ( .A0(n1597), .A1(n1357), .B0(n1356), .Y(n1358) );
AOI21X1TS U1673 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n926), .B0(n1358), .Y(n1362) );
OAI222X1TS U1674 ( .A0(n1651), .A1(n1371), .B0(n1215), .B1(n1359), .C0(n1361), .C1(n1362), .Y(n834) );
OAI222X1TS U1675 ( .A0(n1648), .A1(n1371), .B0(n1215), .B1(n1362), .C0(n1361), .C1(n1360), .Y(n832) );
AOI22X1TS U1676 ( .A0(n1204), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1363), .Y(n1367) );
AOI22X1TS U1677 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n926), .B0(n1365), .B1(
n1364), .Y(n1366) );
NAND2X1TS U1678 ( .A(n1367), .B(n1366), .Y(n822) );
AOI32X1TS U1679 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1371), .A2(n923), .B0(
shift_value_SHT2_EWR[2]), .B1(n1204), .Y(n1369) );
NAND2X1TS U1680 ( .A(n1369), .B(n1368), .Y(n821) );
AOI32X1TS U1681 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1371), .A2(n923), .B0(
shift_value_SHT2_EWR[3]), .B1(n1204), .Y(n1373) );
NAND2X1TS U1682 ( .A(n1373), .B(n1372), .Y(n820) );
INVX4TS U1683 ( .A(n1398), .Y(n1404) );
CLKINVX1TS U1684 ( .A(DmP_EXP_EWSW[23]), .Y(n1374) );
AOI21X1TS U1685 ( .A0(DMP_EXP_EWSW[23]), .A1(n1374), .B0(n1379), .Y(n1375)
);
AOI2BB2XLTS U1686 ( .B0(n1404), .B1(n1375), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1578), .Y(n817) );
NOR2X1TS U1687 ( .A(n1590), .B(DMP_EXP_EWSW[24]), .Y(n1378) );
AOI21X1TS U1688 ( .A0(DMP_EXP_EWSW[24]), .A1(n1590), .B0(n1378), .Y(n1376)
);
XNOR2X1TS U1689 ( .A(n1379), .B(n1376), .Y(n1377) );
AO22XLTS U1690 ( .A0(n1578), .A1(n1377), .B0(n1406), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n816) );
OAI22X1TS U1691 ( .A0(n1379), .A1(n1378), .B0(DmP_EXP_EWSW[24]), .B1(n1591),
.Y(n1382) );
NAND2X1TS U1692 ( .A(DmP_EXP_EWSW[25]), .B(n1650), .Y(n1383) );
XNOR2X1TS U1693 ( .A(n1382), .B(n1380), .Y(n1381) );
AO22XLTS U1694 ( .A0(n1578), .A1(n1381), .B0(n1409), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n815) );
AOI22X1TS U1695 ( .A0(DMP_EXP_EWSW[25]), .A1(n1662), .B0(n1383), .B1(n1382),
.Y(n1386) );
NOR2X1TS U1696 ( .A(n1658), .B(DMP_EXP_EWSW[26]), .Y(n1387) );
AOI21X1TS U1697 ( .A0(DMP_EXP_EWSW[26]), .A1(n1658), .B0(n1387), .Y(n1384)
);
XNOR2X1TS U1698 ( .A(n1386), .B(n1384), .Y(n1385) );
AO22XLTS U1699 ( .A0(n1578), .A1(n1385), .B0(n1398), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n814) );
OAI22X1TS U1700 ( .A0(n1387), .A1(n1386), .B0(DmP_EXP_EWSW[26]), .B1(n1661),
.Y(n1389) );
XNOR2X1TS U1701 ( .A(DmP_EXP_EWSW[27]), .B(n969), .Y(n1388) );
XOR2XLTS U1702 ( .A(n1389), .B(n1388), .Y(n1390) );
AO22XLTS U1703 ( .A0(n1578), .A1(n1390), .B0(n1409), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n813) );
OAI222X1TS U1704 ( .A0(n1399), .A1(n1659), .B0(n1591), .B1(
Shift_reg_FLAGS_7_6), .C0(n1574), .C1(n1401), .Y(n780) );
OAI222X1TS U1705 ( .A0(n1399), .A1(n1594), .B0(n1650), .B1(
Shift_reg_FLAGS_7_6), .C0(n1636), .C1(n1401), .Y(n779) );
OAI222X1TS U1706 ( .A0(n1399), .A1(n1595), .B0(n1661), .B1(
Shift_reg_FLAGS_7_6), .C0(n1635), .C1(n1401), .Y(n778) );
OAI21XLTS U1707 ( .A0(n1392), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1391) );
AOI21X1TS U1708 ( .A0(n1392), .A1(intDX_EWSW[31]), .B0(n1391), .Y(n1393) );
AO21XLTS U1709 ( .A0(OP_FLAG_EXP), .A1(n979), .B0(n1393), .Y(n773) );
AO22XLTS U1710 ( .A0(n1394), .A1(n1393), .B0(ZERO_FLAG_EXP), .B1(n1079), .Y(
n772) );
AO22XLTS U1711 ( .A0(n1578), .A1(DMP_EXP_EWSW[0]), .B0(n1409), .B1(
DMP_SHT1_EWSW[0]), .Y(n770) );
AO22XLTS U1712 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1397), .B1(
DMP_SHT2_EWSW[0]), .Y(n769) );
AO22XLTS U1713 ( .A0(n1578), .A1(DMP_EXP_EWSW[1]), .B0(n1406), .B1(
DMP_SHT1_EWSW[1]), .Y(n767) );
AO22XLTS U1714 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1397), .B1(
DMP_SHT2_EWSW[1]), .Y(n766) );
AO22XLTS U1715 ( .A0(n1578), .A1(DMP_EXP_EWSW[2]), .B0(n1398), .B1(
DMP_SHT1_EWSW[2]), .Y(n764) );
AO22XLTS U1716 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1397), .B1(
DMP_SHT2_EWSW[2]), .Y(n763) );
BUFX3TS U1717 ( .A(n1395), .Y(n1446) );
AO22XLTS U1718 ( .A0(n1446), .A1(DMP_SFG[2]), .B0(n1491), .B1(
DMP_SHT2_EWSW[2]), .Y(n762) );
AO22XLTS U1719 ( .A0(n1407), .A1(DMP_EXP_EWSW[3]), .B0(n1406), .B1(
DMP_SHT1_EWSW[3]), .Y(n761) );
AO22XLTS U1720 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1397), .B1(
DMP_SHT2_EWSW[3]), .Y(n760) );
AO22XLTS U1721 ( .A0(n1492), .A1(DMP_SFG[3]), .B0(n1491), .B1(
DMP_SHT2_EWSW[3]), .Y(n759) );
AO22XLTS U1722 ( .A0(n1407), .A1(DMP_EXP_EWSW[4]), .B0(n1409), .B1(
DMP_SHT1_EWSW[4]), .Y(n758) );
AO22XLTS U1723 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1397), .B1(
DMP_SHT2_EWSW[4]), .Y(n757) );
AO22XLTS U1724 ( .A0(n1407), .A1(DMP_EXP_EWSW[5]), .B0(n1406), .B1(
DMP_SHT1_EWSW[5]), .Y(n755) );
AO22XLTS U1725 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1397), .B1(
DMP_SHT2_EWSW[5]), .Y(n754) );
AO22XLTS U1726 ( .A0(n1407), .A1(DMP_EXP_EWSW[6]), .B0(n1398), .B1(
DMP_SHT1_EWSW[6]), .Y(n752) );
AO22XLTS U1727 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1397), .B1(
DMP_SHT2_EWSW[6]), .Y(n751) );
AO22XLTS U1728 ( .A0(n1407), .A1(DMP_EXP_EWSW[7]), .B0(n1409), .B1(
DMP_SHT1_EWSW[7]), .Y(n749) );
AO22XLTS U1729 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1397), .B1(
DMP_SHT2_EWSW[7]), .Y(n748) );
AO22XLTS U1730 ( .A0(n1407), .A1(DMP_EXP_EWSW[8]), .B0(n1406), .B1(
DMP_SHT1_EWSW[8]), .Y(n746) );
AO22XLTS U1731 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1397), .B1(
DMP_SHT2_EWSW[8]), .Y(n745) );
AO22XLTS U1732 ( .A0(n1407), .A1(DMP_EXP_EWSW[9]), .B0(n1406), .B1(
DMP_SHT1_EWSW[9]), .Y(n743) );
AO22XLTS U1733 ( .A0(n1411), .A1(DMP_SHT1_EWSW[9]), .B0(n1397), .B1(
DMP_SHT2_EWSW[9]), .Y(n742) );
AO22XLTS U1734 ( .A0(n1407), .A1(DMP_EXP_EWSW[10]), .B0(n1409), .B1(
DMP_SHT1_EWSW[10]), .Y(n740) );
BUFX4TS U1735 ( .A(n1397), .Y(n1405) );
AO22XLTS U1736 ( .A0(n1411), .A1(DMP_SHT1_EWSW[10]), .B0(n1405), .B1(
DMP_SHT2_EWSW[10]), .Y(n739) );
BUFX4TS U1737 ( .A(n1665), .Y(n1409) );
AO22XLTS U1738 ( .A0(n1407), .A1(DMP_EXP_EWSW[11]), .B0(n1665), .B1(
DMP_SHT1_EWSW[11]), .Y(n737) );
AO22XLTS U1739 ( .A0(n1411), .A1(DMP_SHT1_EWSW[11]), .B0(n1405), .B1(
DMP_SHT2_EWSW[11]), .Y(n736) );
AO22XLTS U1740 ( .A0(n1407), .A1(DMP_EXP_EWSW[12]), .B0(n1406), .B1(
DMP_SHT1_EWSW[12]), .Y(n734) );
AO22XLTS U1741 ( .A0(n1411), .A1(DMP_SHT1_EWSW[12]), .B0(n1405), .B1(
DMP_SHT2_EWSW[12]), .Y(n733) );
AO22XLTS U1742 ( .A0(n1446), .A1(DMP_SFG[12]), .B0(n1491), .B1(
DMP_SHT2_EWSW[12]), .Y(n732) );
AO22XLTS U1743 ( .A0(n1407), .A1(DMP_EXP_EWSW[13]), .B0(n1409), .B1(
DMP_SHT1_EWSW[13]), .Y(n731) );
AO22XLTS U1744 ( .A0(n1411), .A1(DMP_SHT1_EWSW[13]), .B0(n1405), .B1(
DMP_SHT2_EWSW[13]), .Y(n730) );
AO22XLTS U1745 ( .A0(n1395), .A1(DMP_SFG[13]), .B0(n1491), .B1(
DMP_SHT2_EWSW[13]), .Y(n729) );
AO22XLTS U1746 ( .A0(n1407), .A1(DMP_EXP_EWSW[14]), .B0(n1406), .B1(
DMP_SHT1_EWSW[14]), .Y(n728) );
AO22XLTS U1747 ( .A0(n1411), .A1(DMP_SHT1_EWSW[14]), .B0(n1405), .B1(
DMP_SHT2_EWSW[14]), .Y(n727) );
AO22XLTS U1748 ( .A0(n1446), .A1(DMP_SFG[14]), .B0(n1491), .B1(
DMP_SHT2_EWSW[14]), .Y(n726) );
AO22XLTS U1749 ( .A0(n1407), .A1(DMP_EXP_EWSW[15]), .B0(n1665), .B1(
DMP_SHT1_EWSW[15]), .Y(n725) );
AO22XLTS U1750 ( .A0(n1411), .A1(DMP_SHT1_EWSW[15]), .B0(n1405), .B1(
DMP_SHT2_EWSW[15]), .Y(n724) );
AO22XLTS U1751 ( .A0(n1395), .A1(DMP_SFG[15]), .B0(n1408), .B1(
DMP_SHT2_EWSW[15]), .Y(n723) );
AO22XLTS U1752 ( .A0(n1407), .A1(DMP_EXP_EWSW[16]), .B0(n1406), .B1(
DMP_SHT1_EWSW[16]), .Y(n722) );
AO22XLTS U1753 ( .A0(n1411), .A1(DMP_SHT1_EWSW[16]), .B0(n1405), .B1(
DMP_SHT2_EWSW[16]), .Y(n721) );
AO22XLTS U1754 ( .A0(n1492), .A1(DMP_SFG[16]), .B0(n1491), .B1(
DMP_SHT2_EWSW[16]), .Y(n720) );
INVX4TS U1755 ( .A(n1398), .Y(n1410) );
AO22XLTS U1756 ( .A0(n1410), .A1(DMP_EXP_EWSW[17]), .B0(n1409), .B1(
DMP_SHT1_EWSW[17]), .Y(n719) );
AO22XLTS U1757 ( .A0(n1411), .A1(DMP_SHT1_EWSW[17]), .B0(n1405), .B1(
DMP_SHT2_EWSW[17]), .Y(n718) );
AO22XLTS U1758 ( .A0(n1395), .A1(DMP_SFG[17]), .B0(n1408), .B1(
DMP_SHT2_EWSW[17]), .Y(n717) );
AO22XLTS U1759 ( .A0(n1410), .A1(DMP_EXP_EWSW[18]), .B0(n1406), .B1(
DMP_SHT1_EWSW[18]), .Y(n716) );
AO22XLTS U1760 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1405), .B1(
DMP_SHT2_EWSW[18]), .Y(n715) );
AO22XLTS U1761 ( .A0(n1492), .A1(DMP_SFG[18]), .B0(n1491), .B1(
DMP_SHT2_EWSW[18]), .Y(n714) );
BUFX4TS U1762 ( .A(n1665), .Y(n1398) );
AO22XLTS U1763 ( .A0(n1410), .A1(DMP_EXP_EWSW[19]), .B0(n1409), .B1(
DMP_SHT1_EWSW[19]), .Y(n713) );
AO22XLTS U1764 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1405), .B1(
DMP_SHT2_EWSW[19]), .Y(n712) );
AO22XLTS U1765 ( .A0(n1395), .A1(DMP_SFG[19]), .B0(n1491), .B1(
DMP_SHT2_EWSW[19]), .Y(n711) );
AO22XLTS U1766 ( .A0(n1410), .A1(DMP_EXP_EWSW[20]), .B0(n1398), .B1(
DMP_SHT1_EWSW[20]), .Y(n710) );
AO22XLTS U1767 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1405), .B1(
DMP_SHT2_EWSW[20]), .Y(n709) );
AO22XLTS U1768 ( .A0(n1395), .A1(DMP_SFG[20]), .B0(n1408), .B1(
DMP_SHT2_EWSW[20]), .Y(n708) );
AO22XLTS U1769 ( .A0(n1410), .A1(DMP_EXP_EWSW[21]), .B0(n1409), .B1(
DMP_SHT1_EWSW[21]), .Y(n707) );
AO22XLTS U1770 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1405), .B1(
DMP_SHT2_EWSW[21]), .Y(n706) );
AO22XLTS U1771 ( .A0(n1395), .A1(DMP_SFG[21]), .B0(n1491), .B1(
DMP_SHT2_EWSW[21]), .Y(n705) );
AO22XLTS U1772 ( .A0(n1410), .A1(DMP_EXP_EWSW[22]), .B0(n1409), .B1(
DMP_SHT1_EWSW[22]), .Y(n704) );
AO22XLTS U1773 ( .A0(n1411), .A1(DMP_SHT1_EWSW[22]), .B0(n1668), .B1(
DMP_SHT2_EWSW[22]), .Y(n703) );
AO22XLTS U1774 ( .A0(n1395), .A1(DMP_SFG[22]), .B0(n1408), .B1(
DMP_SHT2_EWSW[22]), .Y(n702) );
AO22XLTS U1775 ( .A0(n1410), .A1(DMP_EXP_EWSW[23]), .B0(n1406), .B1(
DMP_SHT1_EWSW[23]), .Y(n701) );
AO22XLTS U1776 ( .A0(n1411), .A1(DMP_SHT1_EWSW[23]), .B0(n1397), .B1(
DMP_SHT2_EWSW[23]), .Y(n700) );
AO22XLTS U1777 ( .A0(n1555), .A1(DMP_SHT2_EWSW[23]), .B0(n1446), .B1(
DMP_SFG[23]), .Y(n699) );
AO22XLTS U1778 ( .A0(n1475), .A1(DMP_SFG[23]), .B0(n1473), .B1(
DMP_exp_NRM_EW[0]), .Y(n698) );
AO22XLTS U1779 ( .A0(n1410), .A1(DMP_EXP_EWSW[24]), .B0(n1398), .B1(
DMP_SHT1_EWSW[24]), .Y(n696) );
AO22XLTS U1780 ( .A0(n1411), .A1(DMP_SHT1_EWSW[24]), .B0(n1405), .B1(
DMP_SHT2_EWSW[24]), .Y(n695) );
AO22XLTS U1781 ( .A0(n1408), .A1(DMP_SHT2_EWSW[24]), .B0(n1565), .B1(
DMP_SFG[24]), .Y(n694) );
AO22XLTS U1782 ( .A0(n943), .A1(DMP_SFG[24]), .B0(n1473), .B1(
DMP_exp_NRM_EW[1]), .Y(n693) );
AO22XLTS U1783 ( .A0(n1410), .A1(DMP_EXP_EWSW[25]), .B0(n1406), .B1(
DMP_SHT1_EWSW[25]), .Y(n691) );
AO22XLTS U1784 ( .A0(n1411), .A1(DMP_SHT1_EWSW[25]), .B0(n1405), .B1(
DMP_SHT2_EWSW[25]), .Y(n690) );
AO22XLTS U1785 ( .A0(n1408), .A1(DMP_SHT2_EWSW[25]), .B0(n1446), .B1(
DMP_SFG[25]), .Y(n689) );
AO22XLTS U1786 ( .A0(n1475), .A1(DMP_SFG[25]), .B0(n1473), .B1(
DMP_exp_NRM_EW[2]), .Y(n688) );
AO22XLTS U1787 ( .A0(n1410), .A1(DMP_EXP_EWSW[26]), .B0(n1409), .B1(
DMP_SHT1_EWSW[26]), .Y(n686) );
AO22XLTS U1788 ( .A0(n1411), .A1(DMP_SHT1_EWSW[26]), .B0(n1405), .B1(
DMP_SHT2_EWSW[26]), .Y(n685) );
AO22XLTS U1789 ( .A0(n1408), .A1(DMP_SHT2_EWSW[26]), .B0(n1446), .B1(
DMP_SFG[26]), .Y(n684) );
AO22XLTS U1790 ( .A0(n1475), .A1(DMP_SFG[26]), .B0(n1473), .B1(
DMP_exp_NRM_EW[3]), .Y(n683) );
AO22XLTS U1791 ( .A0(n1410), .A1(n969), .B0(n1406), .B1(DMP_SHT1_EWSW[27]),
.Y(n681) );
AO22XLTS U1792 ( .A0(n1411), .A1(DMP_SHT1_EWSW[27]), .B0(n1405), .B1(
DMP_SHT2_EWSW[27]), .Y(n680) );
AO22XLTS U1793 ( .A0(n1408), .A1(DMP_SHT2_EWSW[27]), .B0(n1446), .B1(
DMP_SFG[27]), .Y(n679) );
AO22XLTS U1794 ( .A0(n943), .A1(DMP_SFG[27]), .B0(n1473), .B1(
DMP_exp_NRM_EW[4]), .Y(n678) );
AO22XLTS U1795 ( .A0(n1410), .A1(DMP_EXP_EWSW[28]), .B0(n1665), .B1(
DMP_SHT1_EWSW[28]), .Y(n676) );
AO22XLTS U1796 ( .A0(n1411), .A1(DMP_SHT1_EWSW[28]), .B0(n1405), .B1(
DMP_SHT2_EWSW[28]), .Y(n675) );
AO22XLTS U1797 ( .A0(n1408), .A1(DMP_SHT2_EWSW[28]), .B0(n1446), .B1(
DMP_SFG[28]), .Y(n674) );
AO22XLTS U1798 ( .A0(n1475), .A1(DMP_SFG[28]), .B0(n1697), .B1(
DMP_exp_NRM_EW[5]), .Y(n673) );
AO22XLTS U1799 ( .A0(n1410), .A1(DMP_EXP_EWSW[29]), .B0(n1409), .B1(
DMP_SHT1_EWSW[29]), .Y(n671) );
AO22XLTS U1800 ( .A0(n1411), .A1(DMP_SHT1_EWSW[29]), .B0(n1405), .B1(
DMP_SHT2_EWSW[29]), .Y(n670) );
AO22XLTS U1801 ( .A0(n1408), .A1(DMP_SHT2_EWSW[29]), .B0(n1446), .B1(
DMP_SFG[29]), .Y(n669) );
AO22XLTS U1802 ( .A0(n943), .A1(DMP_SFG[29]), .B0(n1697), .B1(
DMP_exp_NRM_EW[6]), .Y(n668) );
AO22XLTS U1803 ( .A0(n1404), .A1(DMP_EXP_EWSW[30]), .B0(n1406), .B1(
DMP_SHT1_EWSW[30]), .Y(n666) );
AO22XLTS U1804 ( .A0(n1411), .A1(DMP_SHT1_EWSW[30]), .B0(n1405), .B1(
DMP_SHT2_EWSW[30]), .Y(n665) );
AO22XLTS U1805 ( .A0(n1408), .A1(DMP_SHT2_EWSW[30]), .B0(n1446), .B1(
DMP_SFG[30]), .Y(n664) );
AO22XLTS U1806 ( .A0(n1475), .A1(DMP_SFG[30]), .B0(n1697), .B1(
DMP_exp_NRM_EW[7]), .Y(n663) );
AO22XLTS U1807 ( .A0(n1407), .A1(DmP_EXP_EWSW[14]), .B0(n1398), .B1(
DmP_mant_SHT1_SW[14]), .Y(n632) );
AO22XLTS U1808 ( .A0(n1407), .A1(DmP_EXP_EWSW[16]), .B0(n1398), .B1(
DmP_mant_SHT1_SW[16]), .Y(n628) );
AO22XLTS U1809 ( .A0(n1407), .A1(DmP_EXP_EWSW[19]), .B0(n1665), .B1(n962),
.Y(n622) );
AO22XLTS U1810 ( .A0(n1407), .A1(DmP_EXP_EWSW[22]), .B0(n1409), .B1(
DmP_mant_SHT1_SW[22]), .Y(n616) );
OAI222X1TS U1811 ( .A0(n1401), .A1(n1659), .B0(n1590), .B1(
Shift_reg_FLAGS_7_6), .C0(n1574), .C1(n1399), .Y(n614) );
OAI222X1TS U1812 ( .A0(n1401), .A1(n1594), .B0(n1662), .B1(
Shift_reg_FLAGS_7_6), .C0(n1636), .C1(n1399), .Y(n613) );
OAI222X1TS U1813 ( .A0(n1401), .A1(n1595), .B0(n1658), .B1(
Shift_reg_FLAGS_7_6), .C0(n1635), .C1(n1399), .Y(n612) );
INVX4TS U1814 ( .A(n1402), .Y(n1543) );
NAND2X1TS U1815 ( .A(n1510), .B(Shift_reg_FLAGS_7[0]), .Y(n1403) );
OAI2BB1X1TS U1816 ( .A0N(underflow_flag), .A1N(n1543), .B0(n1403), .Y(n610)
);
AO22XLTS U1817 ( .A0(n1404), .A1(ZERO_FLAG_EXP), .B0(n1398), .B1(
ZERO_FLAG_SHT1), .Y(n608) );
AO22XLTS U1818 ( .A0(n1411), .A1(ZERO_FLAG_SHT1), .B0(n1405), .B1(
ZERO_FLAG_SHT2), .Y(n607) );
AO22XLTS U1819 ( .A0(n1408), .A1(ZERO_FLAG_SHT2), .B0(n1446), .B1(
ZERO_FLAG_SFG), .Y(n606) );
AO22XLTS U1820 ( .A0(n1475), .A1(ZERO_FLAG_SFG), .B0(n1473), .B1(
ZERO_FLAG_NRM), .Y(n605) );
AO22XLTS U1821 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1543), .B1(zero_flag), .Y(n603) );
AO22XLTS U1822 ( .A0(n1407), .A1(OP_FLAG_EXP), .B0(n1406), .B1(OP_FLAG_SHT1),
.Y(n602) );
AO22XLTS U1823 ( .A0(n1411), .A1(OP_FLAG_SHT1), .B0(n1668), .B1(OP_FLAG_SHT2), .Y(n601) );
AO22XLTS U1824 ( .A0(n1492), .A1(n934), .B0(n1408), .B1(OP_FLAG_SHT2), .Y(
n600) );
AO22XLTS U1825 ( .A0(n1410), .A1(SIGN_FLAG_EXP), .B0(n1406), .B1(
SIGN_FLAG_SHT1), .Y(n599) );
AO22XLTS U1826 ( .A0(n1411), .A1(SIGN_FLAG_SHT1), .B0(n1668), .B1(
SIGN_FLAG_SHT2), .Y(n598) );
AO22XLTS U1827 ( .A0(n1555), .A1(SIGN_FLAG_SHT2), .B0(n1565), .B1(
SIGN_FLAG_SFG), .Y(n597) );
AO22XLTS U1828 ( .A0(n943), .A1(SIGN_FLAG_SFG), .B0(n1473), .B1(
SIGN_FLAG_NRM), .Y(n596) );
INVX1TS U1829 ( .A(DmP_mant_SFG_SWR[14]), .Y(n1549) );
AOI22X1TS U1830 ( .A0(n934), .A1(n1549), .B0(DmP_mant_SFG_SWR[14]), .B1(
n1442), .Y(intadd_20_CI) );
AOI22X1TS U1831 ( .A0(n1475), .A1(intadd_20_SUM_0_), .B0(n1571), .B1(n1473),
.Y(n593) );
INVX1TS U1832 ( .A(DmP_mant_SFG_SWR[15]), .Y(n1551) );
AOI22X1TS U1833 ( .A0(n934), .A1(n1551), .B0(DmP_mant_SFG_SWR[15]), .B1(
n1442), .Y(intadd_20_B_1_) );
AOI2BB2XLTS U1834 ( .B0(n1504), .B1(intadd_20_SUM_1_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1504), .Y(n592) );
AOI2BB2XLTS U1835 ( .B0(DmP_mant_SFG_SWR[16]), .B1(n1442), .A0N(n1696),
.A1N(DmP_mant_SFG_SWR[16]), .Y(intadd_20_B_2_) );
AOI22X1TS U1836 ( .A0(n1475), .A1(intadd_20_SUM_2_), .B0(n1577), .B1(n1473),
.Y(n591) );
INVX1TS U1837 ( .A(DmP_mant_SFG_SWR[17]), .Y(n1553) );
AOI22X1TS U1838 ( .A0(n1449), .A1(n1553), .B0(DmP_mant_SFG_SWR[17]), .B1(
n1442), .Y(intadd_20_B_3_) );
AOI22X1TS U1839 ( .A0(n1504), .A1(intadd_20_SUM_3_), .B0(n1573), .B1(n1473),
.Y(n590) );
AOI2BB2XLTS U1840 ( .B0(DmP_mant_SFG_SWR[18]), .B1(n1442), .A0N(n1696),
.A1N(DmP_mant_SFG_SWR[18]), .Y(intadd_20_B_4_) );
AOI2BB2XLTS U1841 ( .B0(n1504), .B1(intadd_20_SUM_4_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1504), .Y(n589) );
AOI2BB2XLTS U1842 ( .B0(DmP_mant_SFG_SWR[19]), .B1(n1442), .A0N(n1442),
.A1N(DmP_mant_SFG_SWR[19]), .Y(intadd_20_B_5_) );
AOI2BB2XLTS U1843 ( .B0(n1504), .B1(intadd_20_SUM_5_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1504), .Y(n588) );
INVX1TS U1844 ( .A(DmP_mant_SFG_SWR[20]), .Y(n1556) );
AOI22X1TS U1845 ( .A0(n1449), .A1(n1556), .B0(DmP_mant_SFG_SWR[20]), .B1(
n1442), .Y(intadd_20_B_6_) );
AOI2BB2XLTS U1846 ( .B0(n1504), .B1(intadd_20_SUM_6_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1504), .Y(n587) );
INVX1TS U1847 ( .A(DmP_mant_SFG_SWR[21]), .Y(n1558) );
AOI22X1TS U1848 ( .A0(n1449), .A1(n1558), .B0(DmP_mant_SFG_SWR[21]), .B1(
n1442), .Y(intadd_20_B_7_) );
AOI22X1TS U1849 ( .A0(n1475), .A1(intadd_20_SUM_7_), .B0(n1572), .B1(n1473),
.Y(n586) );
AOI2BB2XLTS U1850 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1442), .A0N(n1442),
.A1N(DmP_mant_SFG_SWR[22]), .Y(intadd_20_B_8_) );
AOI22X1TS U1851 ( .A0(n1475), .A1(intadd_20_SUM_8_), .B0(n1569), .B1(n1473),
.Y(n585) );
AOI2BB2XLTS U1852 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n1442), .A0N(n1442),
.A1N(DmP_mant_SFG_SWR[23]), .Y(intadd_20_B_9_) );
AOI22X1TS U1853 ( .A0(n1475), .A1(intadd_20_SUM_9_), .B0(n933), .B1(n1473),
.Y(n584) );
INVX1TS U1854 ( .A(DmP_mant_SFG_SWR[24]), .Y(n1560) );
AOI22X1TS U1855 ( .A0(n1449), .A1(n1560), .B0(DmP_mant_SFG_SWR[24]), .B1(
n1442), .Y(intadd_20_B_10_) );
AOI22X1TS U1856 ( .A0(n1475), .A1(intadd_20_SUM_10_), .B0(n977), .B1(n1473),
.Y(n583) );
INVX1TS U1857 ( .A(DmP_mant_SFG_SWR[25]), .Y(n1566) );
AOI22X1TS U1858 ( .A0(n934), .A1(DmP_mant_SFG_SWR[25]), .B0(n1566), .B1(
n1442), .Y(n1412) );
XNOR2X1TS U1859 ( .A(intadd_20_n1), .B(n1412), .Y(n1413) );
AOI22X1TS U1860 ( .A0(n1475), .A1(n1413), .B0(n1570), .B1(n1473), .Y(n582)
);
NOR2XLTS U1861 ( .A(n1414), .B(n1521), .Y(n1417) );
OAI22X1TS U1862 ( .A0(n1563), .A1(n1415), .B0(n1651), .B1(n1003), .Y(n1416)
);
AOI211X1TS U1863 ( .A0(Data_array_SWR[13]), .A1(n1564), .B0(n1417), .C0(
n1416), .Y(n1513) );
AOI22X1TS U1864 ( .A0(n1555), .A1(n1513), .B0(n1492), .B1(n978), .Y(n581) );
OAI2BB1X1TS U1865 ( .A0N(n955), .A1N(DMP_SFG[9]), .B0(n1418), .Y(n1499) );
XNOR2X1TS U1866 ( .A(n973), .B(n956), .Y(n1419) );
XNOR2X1TS U1867 ( .A(n1420), .B(n1419), .Y(n1421) );
AOI2BB2XLTS U1868 ( .B0(n1504), .B1(n1421), .A0N(Raw_mant_NRM_SWR[13]),
.A1N(n1504), .Y(n580) );
AOI22X1TS U1869 ( .A0(Data_array_SWR[13]), .A1(n1005), .B0(Data_array_SWR[9]), .B1(n1477), .Y(n1424) );
AOI22X1TS U1870 ( .A0(Data_array_SWR[5]), .A1(n1476), .B0(Data_array_SWR[1]),
.B1(n1438), .Y(n1423) );
OAI211X1TS U1871 ( .A0(n1431), .A1(n1582), .B0(n1424), .C0(n1423), .Y(n1546)
);
AOI22X1TS U1872 ( .A0(Data_array_SWR[23]), .A1(n1540), .B0(n1521), .B1(n1546), .Y(n1425) );
INVX1TS U1873 ( .A(DmP_mant_SFG_SWR[1]), .Y(n1426) );
AOI22X1TS U1874 ( .A0(n1568), .A1(n1425), .B0(n1426), .B1(n1565), .Y(n578)
);
AOI22X1TS U1875 ( .A0(n934), .A1(n1426), .B0(DmP_mant_SFG_SWR[1]), .B1(n1442), .Y(n1427) );
AOI2BB2XLTS U1876 ( .B0(n1504), .B1(n1427), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1504), .Y(n577) );
AOI22X1TS U1877 ( .A0(Data_array_SWR[12]), .A1(n1476), .B0(
Data_array_SWR[15]), .B1(n1477), .Y(n1430) );
AOI22X1TS U1878 ( .A0(Data_array_SWR[19]), .A1(n1005), .B0(
Data_array_SWR[23]), .B1(n1428), .Y(n1429) );
NAND2X1TS U1879 ( .A(n1430), .B(n1429), .Y(n1541) );
INVX2TS U1880 ( .A(n1431), .Y(n1539) );
NOR2X2TS U1881 ( .A(shift_value_SHT2_EWR[4]), .B(n1521), .Y(n1481) );
AOI22X1TS U1882 ( .A0(n1568), .A1(n1537), .B0(n1432), .B1(n1565), .Y(n575)
);
OAI211XLTS U1883 ( .A0(DMP_SFG[5]), .A1(n1465), .B0(n971), .C0(n1463), .Y(
n1433) );
OAI2BB1X1TS U1884 ( .A0N(n1465), .A1N(DMP_SFG[5]), .B0(n1433), .Y(n1471) );
XNOR2X1TS U1885 ( .A(DMP_SFG[7]), .B(n1434), .Y(n1435) );
XOR2X1TS U1886 ( .A(n1436), .B(n1435), .Y(n1437) );
AOI22X1TS U1887 ( .A0(n1475), .A1(n1437), .B0(n1608), .B1(n1697), .Y(n574)
);
AOI22X1TS U1888 ( .A0(Data_array_SWR[12]), .A1(n1005), .B0(Data_array_SWR[8]), .B1(n1477), .Y(n1440) );
AOI22X1TS U1889 ( .A0(Data_array_SWR[4]), .A1(n1476), .B0(Data_array_SWR[0]),
.B1(n1438), .Y(n1439) );
OAI211X1TS U1890 ( .A0(n1488), .A1(n1582), .B0(n1440), .C0(n1439), .Y(n1562)
);
AOI22X1TS U1891 ( .A0(Data_array_SWR[24]), .A1(n1540), .B0(n1521), .B1(n1562), .Y(n1441) );
INVX1TS U1892 ( .A(DmP_mant_SFG_SWR[0]), .Y(n1443) );
AOI22X1TS U1893 ( .A0(n1568), .A1(n1441), .B0(n1443), .B1(n1565), .Y(n572)
);
AOI22X1TS U1894 ( .A0(n934), .A1(n1443), .B0(DmP_mant_SFG_SWR[0]), .B1(n1442), .Y(n1444) );
AOI2BB2XLTS U1895 ( .B0(n1504), .B1(n1444), .A0N(n974), .A1N(n1504), .Y(n571) );
OAI22X1TS U1896 ( .A0(n1563), .A1(n1445), .B0(n1576), .B1(n1003), .Y(n1536)
);
AOI2BB2X1TS U1897 ( .B0(n1449), .B1(n958), .A0N(n958), .A1N(n1449), .Y(n1447) );
NAND2X1TS U1898 ( .A(n1447), .B(DMP_SFG[0]), .Y(n1453) );
OAI21XLTS U1899 ( .A0(n1447), .A1(DMP_SFG[0]), .B0(n1453), .Y(n1448) );
AOI22X1TS U1900 ( .A0(n1475), .A1(n1448), .B0(n1580), .B1(n1473), .Y(n569)
);
XNOR2X1TS U1901 ( .A(DMP_SFG[1]), .B(n1453), .Y(n1450) );
XNOR2X1TS U1902 ( .A(n1450), .B(n1454), .Y(n1451) );
AOI22X1TS U1903 ( .A0(n1475), .A1(n1451), .B0(n1641), .B1(n1697), .Y(n568)
);
OAI22X1TS U1904 ( .A0(n1563), .A1(n1452), .B0(n1592), .B1(n1003), .Y(n1535)
);
AO22XLTS U1905 ( .A0(n1492), .A1(DmP_mant_SFG_SWR[3]), .B0(n1491), .B1(n1535), .Y(n566) );
INVX2TS U1906 ( .A(n1453), .Y(n1455) );
AOI2BB2XLTS U1907 ( .B0(DMP_SFG[3]), .B1(n972), .A0N(n972), .A1N(DMP_SFG[3]),
.Y(n1456) );
XNOR2X1TS U1908 ( .A(n1457), .B(n1456), .Y(n1458) );
AOI2BB2XLTS U1909 ( .B0(n1504), .B1(n1458), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n1504), .Y(n565) );
AOI22X1TS U1910 ( .A0(Data_array_SWR[20]), .A1(n1462), .B0(
Data_array_SWR[24]), .B1(n1461), .Y(n1480) );
AOI22X1TS U1911 ( .A0(Data_array_SWR[13]), .A1(n1477), .B0(Data_array_SWR[9]), .B1(n1476), .Y(n1460) );
NAND2X1TS U1912 ( .A(Data_array_SWR[16]), .B(n1005), .Y(n1459) );
OAI211X1TS U1913 ( .A0(n1480), .A1(n1582), .B0(n1460), .C0(n1459), .Y(n1534)
);
AO22X1TS U1914 ( .A0(Data_array_SWR[19]), .A1(n1462), .B0(Data_array_SWR[23]), .B1(n1461), .Y(n1533) );
AOI22X1TS U1915 ( .A0(n1568), .A1(n1532), .B0(n924), .B1(n1565), .Y(n564) );
CMPR32X2TS U1916 ( .A(n971), .B(n1464), .C(n1463), .CO(n1467), .S(n987) );
XNOR2X1TS U1917 ( .A(DMP_SFG[5]), .B(n1465), .Y(n1466) );
XOR2X1TS U1918 ( .A(n1467), .B(n1466), .Y(n1468) );
AOI22X1TS U1919 ( .A0(n1475), .A1(n1468), .B0(n1598), .B1(n1697), .Y(n563)
);
INVX2TS U1920 ( .A(n1481), .Y(n1489) );
OAI222X1TS U1921 ( .A0(n1000), .A1(n1657), .B0(n1563), .B1(n1470), .C0(n1489), .C1(n1469), .Y(n1530) );
AO22XLTS U1922 ( .A0(n1492), .A1(DmP_mant_SFG_SWR[7]), .B0(n1491), .B1(n1530), .Y(n562) );
CMPR32X2TS U1923 ( .A(n970), .B(n1472), .C(n1471), .CO(n1436), .S(n1474) );
AOI22X1TS U1924 ( .A0(Data_array_SWR[12]), .A1(n1477), .B0(Data_array_SWR[8]), .B1(n1476), .Y(n1479) );
AOI22X1TS U1925 ( .A0(Data_array_SWR[15]), .A1(n1005), .B0(
shift_value_SHT2_EWR[4]), .B1(n1533), .Y(n1478) );
NAND2X1TS U1926 ( .A(n1479), .B(n1478), .Y(n1529) );
INVX2TS U1927 ( .A(n1480), .Y(n1528) );
AOI22X1TS U1928 ( .A0(n1568), .A1(n1527), .B0(n1482), .B1(n1565), .Y(n559)
);
CMPR32X2TS U1929 ( .A(n1664), .B(n1484), .C(n1483), .CO(n1457), .S(n1485) );
AOI22X1TS U1930 ( .A0(n1475), .A1(n1485), .B0(n1599), .B1(n1697), .Y(n558)
);
OAI222X1TS U1931 ( .A0(n1000), .A1(n1656), .B0(n1563), .B1(n1487), .C0(n1489), .C1(n1486), .Y(n1525) );
AO22XLTS U1932 ( .A0(n1492), .A1(n960), .B0(n1491), .B1(n1525), .Y(n557) );
OAI222X1TS U1933 ( .A0(n1000), .A1(n1660), .B0(n1563), .B1(n1490), .C0(n1489), .C1(n1488), .Y(n1523) );
AO22XLTS U1934 ( .A0(n1492), .A1(DmP_mant_SFG_SWR[9]), .B0(n1491), .B1(n1523), .Y(n555) );
XNOR2X1TS U1935 ( .A(DMP_SFG[9]), .B(n955), .Y(n1495) );
XOR2X1TS U1936 ( .A(n1496), .B(n1495), .Y(n1497) );
AOI22X1TS U1937 ( .A0(n1475), .A1(n1497), .B0(n1596), .B1(n1697), .Y(n554)
);
OAI22X1TS U1938 ( .A0(n1592), .A1(n997), .B0(n1653), .B1(n1505), .Y(n1520)
);
OAI222X1TS U1939 ( .A0(n1505), .A1(n1593), .B0(n1506), .B1(n1576), .C0(n1652), .C1(n997), .Y(n1522) );
OAI22X1TS U1940 ( .A0(n1575), .A1(n1003), .B0(n1649), .B1(n1000), .Y(n1498)
);
AOI221X1TS U1941 ( .A0(n1563), .A1(n1520), .B0(n1521), .B1(n1522), .C0(n1498), .Y(n1518) );
AOI22X1TS U1942 ( .A0(n1568), .A1(n1518), .B0(n931), .B1(n1565), .Y(n553) );
XNOR2X1TS U1943 ( .A(n1501), .B(n1500), .Y(n1503) );
AOI22X1TS U1944 ( .A0(n1475), .A1(n1503), .B0(n1597), .B1(n1697), .Y(n552)
);
OAI22X1TS U1945 ( .A0(n1576), .A1(n997), .B0(n1652), .B1(n1505), .Y(n1516)
);
OAI222X1TS U1946 ( .A0(n997), .A1(n1653), .B0(n1506), .B1(n1592), .C0(n1575),
.C1(n1505), .Y(n1517) );
OAI22X1TS U1947 ( .A0(n1648), .A1(n1000), .B0(n1593), .B1(n1003), .Y(n1507)
);
AOI221X1TS U1948 ( .A0(n1563), .A1(n1516), .B0(n1521), .B1(n1517), .C0(n1507), .Y(n1514) );
AOI22X1TS U1949 ( .A0(n1568), .A1(n1514), .B0(n1508), .B1(n1565), .Y(n551)
);
BUFX3TS U1950 ( .A(n1511), .Y(n1545) );
AO22XLTS U1951 ( .A0(n1545), .A1(n1512), .B0(final_result_ieee[10]), .B1(
n1543), .Y(n548) );
OAI2BB2XLTS U1952 ( .B0(n1513), .B1(n1548), .A0N(final_result_ieee[11]),
.A1N(n1547), .Y(n547) );
OAI2BB2XLTS U1953 ( .B0(n1514), .B1(n1548), .A0N(final_result_ieee[8]),
.A1N(n1543), .Y(n546) );
OAI22X1TS U1954 ( .A0(n1648), .A1(n1003), .B0(n1593), .B1(n1000), .Y(n1515)
);
AOI221X1TS U1955 ( .A0(n1563), .A1(n1517), .B0(n1521), .B1(n1516), .C0(n1515), .Y(n1552) );
OAI2BB2XLTS U1956 ( .B0(n1552), .B1(n1548), .A0N(final_result_ieee[13]),
.A1N(n1543), .Y(n545) );
OAI2BB2XLTS U1957 ( .B0(n1518), .B1(n1548), .A0N(final_result_ieee[9]),
.A1N(n1547), .Y(n544) );
OAI22X1TS U1958 ( .A0(n1575), .A1(n1000), .B0(n1649), .B1(n1003), .Y(n1519)
);
AOI221X1TS U1959 ( .A0(n1563), .A1(n1522), .B0(n1521), .B1(n1520), .C0(n1519), .Y(n1550) );
OAI2BB2XLTS U1960 ( .B0(n1550), .B1(n1548), .A0N(final_result_ieee[12]),
.A1N(n1547), .Y(n543) );
AO22XLTS U1961 ( .A0(n1545), .A1(n1523), .B0(final_result_ieee[7]), .B1(
n1543), .Y(n542) );
AO22XLTS U1962 ( .A0(n1545), .A1(n1524), .B0(final_result_ieee[14]), .B1(
n1543), .Y(n541) );
AO22XLTS U1963 ( .A0(n1545), .A1(n1525), .B0(final_result_ieee[4]), .B1(
n1543), .Y(n540) );
AO22XLTS U1964 ( .A0(n1545), .A1(n1526), .B0(final_result_ieee[17]), .B1(
n1543), .Y(n539) );
OAI2BB2XLTS U1965 ( .B0(n1527), .B1(n1548), .A0N(final_result_ieee[2]),
.A1N(n1547), .Y(n538) );
OAI2BB2XLTS U1966 ( .B0(n1559), .B1(n1548), .A0N(final_result_ieee[19]),
.A1N(n1547), .Y(n537) );
AO22XLTS U1967 ( .A0(n1545), .A1(n1530), .B0(final_result_ieee[5]), .B1(
n1543), .Y(n536) );
AO22XLTS U1968 ( .A0(n1545), .A1(n1531), .B0(final_result_ieee[16]), .B1(
n1543), .Y(n535) );
OAI2BB2XLTS U1969 ( .B0(n1532), .B1(n1548), .A0N(final_result_ieee[3]),
.A1N(n1547), .Y(n534) );
OAI2BB2XLTS U1970 ( .B0(n1557), .B1(n1548), .A0N(final_result_ieee[18]),
.A1N(n1547), .Y(n533) );
AO22XLTS U1971 ( .A0(n1545), .A1(n1535), .B0(final_result_ieee[1]), .B1(
n1543), .Y(n532) );
AO22XLTS U1972 ( .A0(n1545), .A1(n1536), .B0(final_result_ieee[0]), .B1(
n1543), .Y(n531) );
OAI2BB2XLTS U1973 ( .B0(n1537), .B1(n1548), .A0N(final_result_ieee[6]),
.A1N(n1547), .Y(n530) );
OAI2BB2XLTS U1974 ( .B0(n1554), .B1(n1548), .A0N(final_result_ieee[15]),
.A1N(n1547), .Y(n529) );
AO22XLTS U1975 ( .A0(n1545), .A1(n1542), .B0(final_result_ieee[20]), .B1(
n1543), .Y(n528) );
AO22XLTS U1976 ( .A0(n1545), .A1(n1544), .B0(final_result_ieee[21]), .B1(
n1543), .Y(n527) );
AOI22X1TS U1977 ( .A0(Data_array_SWR[23]), .A1(n1564), .B0(n1563), .B1(n1546), .Y(n1561) );
OAI2BB2XLTS U1978 ( .B0(n1561), .B1(n1548), .A0N(final_result_ieee[22]),
.A1N(n1547), .Y(n526) );
AOI22X1TS U1979 ( .A0(n1568), .A1(n1550), .B0(n1549), .B1(n1565), .Y(n525)
);
AOI22X1TS U1980 ( .A0(n1568), .A1(n1552), .B0(n1551), .B1(n1565), .Y(n524)
);
AOI22X1TS U1981 ( .A0(n1568), .A1(n1554), .B0(n1553), .B1(n1565), .Y(n522)
);
AOI22X1TS U1982 ( .A0(n1568), .A1(n1557), .B0(n1556), .B1(n1565), .Y(n519)
);
AOI22X1TS U1983 ( .A0(n1568), .A1(n1559), .B0(n1558), .B1(n1565), .Y(n518)
);
AOI22X1TS U1984 ( .A0(n1568), .A1(n1561), .B0(n1560), .B1(n1565), .Y(n515)
);
AOI22X1TS U1985 ( .A0(Data_array_SWR[24]), .A1(n1564), .B0(n1563), .B1(n1562), .Y(n1567) );
AOI22X1TS U1986 ( .A0(n1568), .A1(n1567), .B0(n1566), .B1(n1565), .Y(n514)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_ACAIIN16Q4_syn.sdf");
endmodule
|
//
// Author: Steffen Reith ([email protected])
//
// Creation Date: Mon Nov 20 10:49:12 CET 2017
// Module Name: Board_Nexys4 - Behavioral
// Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
//
//
module IcoBoard (reset,
clk100Mhz,
extInt,
leds,
pwmLeds,
pmodA,
tck,
tms,
tdi,
tdo,
rx,
tx);
// Input ports
input reset;
input clk100Mhz;
input [0:0] extInt;
input rx;
input tck;
input tms;
input tdi;
// Output ports
output [7:0] leds;
output [2:0] pwmLeds;
output tx;
output tdo;
// Bidirectional port
inout [7:0] pmodA;
// Clock generation
wire boardClk;
wire boardClkLocked;
// Internal wiring
wire [7:0] pmodA_read;
wire [7:0] pmodA_write;
wire [7:0] pmodA_writeEnable;
// Instantiate a PLL/MMCM (makes a 25Mhz clock)
PLL makeClk (.clkIn (clk100Mhz),
.clkOut (boardClk),
.isLocked (boardClkLocked));
// Instantiate the J1SoC core generated by Spinal
J1Ico core (.reset (reset),
.boardClk (boardClk),
.boardClkLocked (boardClkLocked),
.extInt (extInt),
.leds (leds),
.pwmLeds (pwmLeds),
.tck (tck),
.tms (tms),
.tdi (tdi),
.tdo (tdo),
.pmodA_read (pmodA_read),
.pmodA_write (pmodA_write),
.pmodA_writeEnable (pmodA_writeEnable),
.rx (rx),
.tx (tx));
// Generate the write port and equip it with tristate functionality
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
// Instantiate the ith tristate buffer
SB_IO #(.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) iobuf (
.PACKAGE_PIN(pmodA[i]),
.OUTPUT_ENABLE(pmodA_writeEnable[i]),
.D_OUT_0(pmodA_write[i]),
.D_IN_0(pmodA_read[i]));
end
endgenerate
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module basys3_demo (
input clk,
output tx,
input rx,
input [15:0] sw,
output [15:0] led
);
// Input 100MHz clock through a BUFG
wire clk100;
BUFG bufg100 (.I(clk), .O(clk100));
// BUFGCE as divide by 2
reg clk50_ce;
always @(posedge clk100)
clk50_ce <= !clk50_ce;
wire clk50;
BUFGCE bufg50 (.I(clk), .CE(clk50_ce), .O(clk50));
// Reset generator
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk50) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[15:0];
// A simple GPIO peripheral connected to LEDs
always @(posedge clk50) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
// The picosoc
picosoc_noflash soc (
.clk (clk50),
.resetn (resetn ),
.ser_tx (tx),
.ser_rx (rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V |
/*
* stack.v
* LIFO Stack
*
* Copyright (C) 2013 James Cowgill
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module stack(top, clk, pushd, push_en, pop_en);
// Width of data values stored on the stack
parameter DATA_WIDTH = 8;
// Width of stack addresses (max stack size = 2^ADDR_WIDTH)
parameter ADDR_WIDTH = 5;
// Inputs and outputs
output [DATA_WIDTH - 1:0] top; // Value on the top of the stack
input clk; // Clock
input [DATA_WIDTH - 1:0] pushd; // Incoming data for push operations
input push_en;// Pushing on next clock
input pop_en; // Pop on next clock
// Stack storage and pointer
// stack_ptr = next location to store data
reg [DATA_WIDTH - 1:0] stack_data[0:(1 << ADDR_WIDTH) - 1];
reg [ADDR_WIDTH - 1:0] stack_ptr;
// Top of the stack
reg [DATA_WIDTH - 1:0] stack_top;
// View of the top of the stack
assign top = stack_top;
// Stack initialization
integer i;
initial
begin
// Registers
stack_ptr = 0;
stack_top = 0;
// Stack data
for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1)
stack_data[i] = 0;
end
// Main pushing and popping code
always @(posedge clk)
begin
if (push_en)
begin
// Copy onto stack and increment pointer
stack_data[stack_ptr] <= stack_top;
stack_ptr <= stack_ptr + 1'b1;
// Update stack top
stack_top <= pushd;
end
else if (pop_en)
begin
// Pop by decrementing pointer
stack_ptr <= stack_ptr - 1'b1;
// Update stack top
stack_top <= stack_data[stack_ptr - 1'b1];
end
end
endmodule
|
`default_nettype none
`timescale 1ns/1ns
module tb_mem();
wire clk, reset;
clock clock(clk, reset);
reg m0_write = 0;
reg m0_read = 0;
reg [35:0] m0_writedata = 0;
reg [17:0] m0_address = 0;
wire [35:0] m0_readdata;
wire m0_waitrequest;
reg m1_write = 0;
reg m1_read = 0;
reg [35:0] m1_writedata = 0;
reg [17:0] m1_address = 0;
wire [35:0] m1_readdata;
wire m1_waitrequest;
wire s_write, s_read, s_waitrequest;
wire [17:0] s_address;
wire [35:0] s_writedata, s_readdata;
arbiter arb0(.clk(clk), .reset(reset),
.s0_address(m0_address),
.s0_write(m0_write),
.s0_read(m0_read),
.s0_writedata(m0_writedata),
.s0_readdata(m0_readdata),
.s0_waitrequest(m0_waitrequest),
.s1_address(m1_address),
.s1_write(m1_write),
.s1_read(m1_read),
.s1_writedata(m1_writedata),
.s1_readdata(m1_readdata),
.s1_waitrequest(m1_waitrequest),
.m_address(s_address),
.m_write(s_write),
.m_read(s_read),
.m_writedata(s_writedata),
.m_readdata(s_readdata),
.m_waitrequest(s_waitrequest));
testmem16k memory(.i_clk(clk), .i_reset_n(reset),
.i_address(s_address), .i_write(s_write), .i_read(s_read),
.i_writedata(s_writedata),
.o_readdata(s_readdata),
.o_waitrequest(s_waitrequest));
initial begin
$dumpfile("dump.vcd");
$dumpvars();
// memory.mem[4] = 'o123;
// memory.mem[5] = 'o321;
// memory.mem[8] = 'o11111;
memory.ram.ram[4] = 'o123;
memory.ram.ram[5] = 'o321;
memory.ram.ram[6] = 'o444444;
memory.ram.ram[8] = 'o11111;
#5;
#200;
m0_address <= 'o4;
// m1_address <= 'o10;
m0_write <= 1;
// m1_write <= 1;
m0_writedata <= 'o1234;
// m1_writedata <= 'o4321;
@(negedge m0_write);
@(posedge clk);
m0_address <= 5;
m0_read <= 1;
@(negedge m0_read);
@(posedge clk);
m0_address <= 6;
m0_read <= 1;
@(negedge m0_read);
@(posedge clk);
m0_address <= 0;
m0_read <= 1;
@(negedge m0_read);
@(posedge clk);
m0_address <= 4;
m0_read <= 1;
end
initial begin
#40000;
$finish;
end
reg [35:0] data0;
reg [35:0] data1;
always @(posedge clk) begin
if(~m0_waitrequest & m0_write)
m0_write <= 0;
if(~m0_waitrequest & m0_read) begin
m0_read <= 0;
data0 <= m0_readdata;
end
if(~m1_waitrequest & m1_write)
m1_write <= 0;
if(~m1_waitrequest & m1_read) begin
m1_read <= 0;
data1 <= m1_readdata;
end
end
endmodule
|
`timescale 1 ns/1 ps
module aws_vgg_testbench;
wire [47:0] airplane4_image [1023:0] = { 48'h1100120014, 48'h1100130014, 48'h1200130015, 48'h1200130015, 48'h1300140015, 48'h1200130015, 48'h1200130015, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1400150016, 48'h1400150016, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1200130015, 48'h1200130015, 48'h1100120014, 48'h1100120014, 48'h1100120014, 48'h1100110014, 48'h1000110014, 48'h1000100013, 48'hf000f0012, 48'he000f0011, 48'he000e0011, 48'hd000e0011, 48'he000f0011, 48'h1100120014, 48'h1100130014, 48'h1200130015, 48'h1300130015, 48'h1300140015, 48'hf00100011, 48'hd000e000f, 48'h1200130015, 48'h1400150016, 48'h1300140015, 48'h1300140016, 48'h1300140015, 48'h1300140015, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1300140016, 48'h1300140015, 48'h1200130015, 48'h1200130015, 48'h1100120014, 48'h1100120014, 48'h1100110014, 48'h1000110014, 48'h1000100013, 48'hf00100013, 48'hf00100013, 48'he000f0012, 48'he000f0011, 48'hd000e0011, 48'he000f0011, 48'h1100120014, 48'h1100130014, 48'h1100130014, 48'h1300140016, 48'h9000b000f, 48'h600090009, 48'h500050008, 48'h600060009, 48'h1000120013, 48'h1400150016, 48'h1300140015, 48'h1300140015, 48'h1200140015, 48'h1300150015, 48'h1300140015, 48'h1300140015, 48'h1300140015, 48'h1300140015, 48'h1200130015, 48'h1200130015, 48'h1100130015, 48'h1100120014, 48'h1100120014, 48'h1100110014, 48'h1000110014, 48'hf00100013, 48'hf00100013, 48'hf00100013, 48'he000e0012, 48'hd000e0011, 48'hd000e0010, 48'he000f0012, 48'h1100120014, 48'h1100130014, 48'h1100120014, 48'h1200140015, 48'hfffe00020008, 48'hfff7fff90001, 48'h400040008, 48'h100020004, 48'h200040004, 48'hf000f0010, 48'h1400140015, 48'h1200140015, 48'h1100140014, 48'h1200150015, 48'h1000120013, 48'hf00100011, 48'h1200130015, 48'h1200130015, 48'h1100130014, 48'h1100120015, 48'h1100120015, 48'h1100120015, 48'h1100110014, 48'h1000110014, 48'h1000100013, 48'h1000100013, 48'hf00100013, 48'hf00100013, 48'he000e0013, 48'he000e0011, 48'hd000f0010, 48'he000f0011, 48'h1100120014, 48'h1100130014, 48'h1100120014, 48'h1100130014, 48'hc000d0013, 48'hfff5fff60005, 48'hfff4fff80000, 48'h60004, 48'hffff00020001, 48'hffff00000000, 48'hc000d000d, 48'h1300150015, 48'h1100130015, 48'h1200140016, 48'h1100120014, 48'h9000a000b, 48'h1300140016, 48'h1300140015, 48'h1200130015, 48'h1100120015, 48'h1100120015, 48'h1100110014, 48'h1000110014, 48'h1000100013, 48'hf00100013, 48'hf00100013, 48'hf00100013, 48'hf00100013, 48'he000f0012, 48'he000f0010, 48'hd000f000f, 48'he000f0011, 48'h1100120014, 48'h1100120014, 48'h1100120014, 48'h1100120014, 48'h1300130016, 48'h8000c0012, 48'hffedfff30000, 48'hfff4fffa0000, 48'h100030007, 48'h3, 48'hfffcfffdfffd, 48'h8000a000a, 48'h1400150017, 48'h1100110015, 48'h200030005, 48'hfff5fff7fff9, 48'h300040006, 48'h1000110013, 48'h1100120014, 48'h1100110014, 48'h1100120015, 48'h1100110014, 48'h1000110014, 48'h1000110014, 48'hf00100013, 48'hf00100013, 48'hf00100013, 48'hf00100013, 48'he000f0011, 48'hd000e0010, 48'hd000e0010, 48'he000f0010, 48'h1000110013, 48'h1100120014, 48'h1100120014, 48'h1100120014, 48'h1200120013, 48'h1000140013, 48'h4000a000f, 48'hfff0fff20003, 48'hfff6fff70003, 48'h20006, 48'hfffe00000001, 48'hfffbfffdfffd, 48'h200030004, 48'hfffbfffbffff, 48'hfff3fff3fff7, 48'hffebffebffee, 48'hfff9fff9fffc, 48'h1000100014, 48'hd000e0010, 48'he000f0012, 48'h1200130015, 48'h1100110014, 48'h1000110014, 48'h1000110014, 48'hf00100013, 48'hf00100013, 48'hf00100013, 48'he000f0012, 48'hd000e0010, 48'hd000e0011, 48'he000e0012, 48'hd000e0011, 48'h1000110013, 48'h1000110013, 48'h1000110013, 48'h1100120014, 48'h1200130014, 48'h1200120014, 48'h1100130014, 48'h400060010, 48'hffeefff10000, 48'hfff7fff80002, 48'hfffe00000003, 48'hfffe0000ffff, 48'hfff5fff6fff6, 48'hffedffedffef, 48'hfffafffafffd, 48'hfffafffbfffe, 48'hffffffff0003, 48'h1400140017, 48'hd000d0010, 48'ha000a000d, 48'h1000110013, 48'h1000110014, 48'h1000110014, 48'h1000110014, 48'h1000100013, 48'hf00100013, 48'hf00100013, 48'hf00100013, 48'he000e0011, 48'hb000b0011, 48'h900090010, 48'hc000c0011, 48'hf00110013, 48'h1000110013, 48'h1000110013, 48'h1000110013, 48'h1100110014, 48'h1300110015, 48'h1300110014, 48'h1100150015, 48'h3000c, 48'hfff1fff1fffb, 48'hfffeffff0003, 48'hfffcfffefffd, 48'hfff7fff8fff7, 48'hfff9fff9fffa, 48'hfffbfffcffff, 48'h70008000a, 48'h100020005, 48'hc000c000f, 48'hfff6fff6fffa, 48'hfff2fff2fff7, 48'h60007000a, 48'h1100130014, 48'h1000110013, 48'h1000110013, 48'hf00100013, 48'h1000100013, 48'hf00100013, 48'ha000a000e, 48'hfffefffe0003, 48'hffefffeffff7, 48'hffe7ffe7fff1, 48'h100010009, 48'hf00100011, 48'hf00110011, 48'hf00110012, 48'h1000120013, 48'h1000120013, 48'h1100120013, 48'h1100120013, 48'h1100120013, 48'h1100120014, 48'h300040007, 48'hfffcfffdffff, 48'hfffbfffdfffd, 48'hfffafffcfffb, 48'hfffeffffffff, 48'hfffafffbfffd, 48'hfffcfffdffff, 48'h100020004, 48'hfffafffbfffd, 48'hffeeffeefff3, 48'hffedffedfff2, 48'ha000b000d, 48'h1100120012, 48'h1000110012, 48'h1000110012, 48'hf00100012, 48'hb000c000f, 48'h10005, 48'hfff0fff1fff5, 48'hffe5ffe6ffe9, 48'hffd9ffdbffe1, 48'hffdeffe0ffe9, 48'h30005000b, 48'he000f000f, 48'he000f0010, 48'hf00100010, 48'hf00110011, 48'h1000110011, 48'h1000110011, 48'h1100110012, 48'h1100120012, 48'h1100110012, 48'hf00100011, 48'h10002, 48'hfff8fff9fffa, 48'hfffdfffffffe, 48'hfffeffffffff, 48'hffff00000002, 48'hfffcfffdffff, 48'hfff4fff5fff7, 48'hfff5fff6fff8, 48'h100010004, 48'hfff9fff9fffd, 48'h9000a000b, 48'h1000110012, 48'hf00100013, 48'he000f0011, 48'h200040006, 48'hfff3fff5fff8, 48'hffe9ffebffed, 48'hffe3ffe4ffe7, 48'hffdaffdcffdb, 48'hffd1ffd3ffd4, 48'hffeffff2fff5, 48'hc000e000f, 48'he000e000e, 48'he000e000e, 48'hf000f000f, 48'hf000f000f, 48'hf000f000f, 48'h1000100010, 48'h1100110011, 48'h1100110011, 48'h1000100011, 48'h1000110011, 48'hf00100010, 48'hffff00010000, 48'hfff9fffafffa, 48'hfffeffffffff, 48'h400050006, 48'hffff00000002, 48'hfffcfffdfffe, 48'hfff7fff7fff9, 48'h100020003, 48'h600070008, 48'h80009000b, 48'hf00100013, 48'h90009000e, 48'hfff7fff9fffc, 48'hffe5ffe9ffea, 48'hffe7ffeaffeb, 48'hfff1fff4fff5, 48'hfffcfffeffff, 48'hffeeffefffee, 48'hffedffeeffee, 48'h700070009, 48'ha000b000b, 48'he000d000d, 48'he000d000d, 48'hf000e000e, 48'hf000e000e, 48'hf000e000e, 48'hf000f000e, 48'h10000f000f, 48'h10000f000f, 48'h100010000f, 48'hf0010000f, 48'h100010000f, 48'hb000c000c, 48'hfffdfffefffd, 48'hfffafffbfffc, 48'hffff00000002, 48'hfffcfffdfffe, 48'hfffeffff0001, 48'hfffeffff0000, 48'hfff8fff9fff9, 48'h700080009, 48'ha000a000d, 48'h4, 48'hfff1fff2fff5, 48'hffe9ffecffee, 48'hfff3fff6fff8, 48'h300050006, 48'h9000a000b, 48'h400040004, 48'hfffcfffbfffc, 48'h800050007, 48'hb0008000a, 48'ha0008000a, 48'hd000b000a, 48'hd000b000b, 48'he000c000b, 48'he000c000c, 48'he000d000c, 48'he000d000d, 48'hf000e000d, 48'hf000e000d, 48'he000e000d, 48'he000f000c, 48'he000e000c, 48'he000e000e, 48'h900090009, 48'hfffafffafffc, 48'hfff9fff9fffb, 48'hfffeffff0000, 48'h100020004, 48'h300040006, 48'hfff8fff9fffa, 48'hfff7fff8fff9, 48'hfff2fff2fff6, 48'hffebffebffef, 48'hfff3fff4fff7, 48'h300040006, 48'hb000d000f, 48'h80009000a, 48'hffffffff, 48'hfffefffe, 48'h700050006, 48'hb00070008, 48'hb00060006, 48'hb00070007, 48'hb00090008, 48'hb000a0008, 48'hc000a0009, 48'hc000a000a, 48'hd000b000a, 48'hd000c000a, 48'hd000d000b, 48'hd000d000b, 48'hd000d000b, 48'hd000d000a, 48'hd000d000a, 48'hc000c000a, 48'hd000c000b, 48'h600060006, 48'hfffcfffdffff, 48'h200030004, 48'h100020004, 48'hfff5fff5fff7, 48'hffe9ffebffec, 48'hffe8ffe9ffeb, 48'hffe9ffe9ffed, 48'hfffafffafffe, 48'he00100011, 48'hd000e000e, 48'hffffffff0001, 48'hfffafff9fffa, 48'h500030000, 48'hb00080006, 48'ha00070005, 48'h900060003, 48'ha00050002, 48'ha00060004, 48'ha00080004, 48'hb00090005, 48'hb00090006, 48'hb00090007, 48'hd00090006, 48'hc000a0006, 48'hb000b0008, 48'hc000b0008, 48'hd000b0008, 48'he000a0008, 48'hd000a0008, 48'hc000a0008, 48'hb00090008, 48'h900080008, 48'hfff9fff9fffc, 48'hfff2fff3fff5, 48'hffe9ffebffed, 48'hffe6ffe7ffe9, 48'hffe9ffebffec, 48'hfff9fffafffc, 48'h80007000b, 48'hc000c000f, 48'h200050006, 48'hfffcfffffffd, 48'hfffdfffcffff, 48'hfffbfffcfffe, 48'h40004ffff, 48'h900050002, 48'h800040001, 48'h800040000, 48'h700040000, 48'h800050001, 48'ha00060000, 48'hb00070001, 48'hb00070002, 48'hc00070003, 48'hc00070003, 48'hb00080004, 48'hb00090004, 48'hd00090004, 48'he00090004, 48'he00090004, 48'hc00080004, 48'ha00080005, 48'h900080008, 48'h600060007, 48'hffeffff0fff3, 48'hffdfffe0ffe3, 48'hffe3ffe5ffe8, 48'hfff2fff4fff8, 48'h300060009, 48'hc000e0010, 48'h80007000b, 48'hfffcfffbfffd, 48'hfff6fff8fff7, 48'h100040004, 48'hfff9fffbffff, 48'hffeaffebffed, 48'hfffcfffcfff8, 48'h800040000, 48'h70002fffe, 48'h70003fffd, 48'h60002fffc, 48'h70002fffd, 48'hb0004fffd, 48'ha0005ffff, 48'hb0005ffff, 48'hd0005fffe, 48'hb00050000, 48'hb00050000, 48'hb0006ffff, 48'he00070000, 48'he00060000, 48'hc00060000, 48'hb00070003, 48'h900060005, 48'h1, 48'hfff3fff4fff7, 48'hffe6ffe8ffeb, 48'hffe9ffebffee, 48'hfffe00010004, 48'he00100014, 48'ha000d000f, 48'hfffcfffd0000, 48'hfffafffafffd, 48'hfffefffeffff, 48'hfff8fff9fff7, 48'hfff9fffafffa, 48'hfff8fff8fff9, 48'hfff1ffefffed, 48'hfff9fff6fff1, 48'h70002fffa, 48'h60001fff9, 48'h60001fff9, 48'h60000fff8, 48'h60001fff9, 48'h80001fffb, 48'h70002fffe, 48'h80003fffd, 48'hb0004fffc, 48'hb0004fffd, 48'hb0004fffc, 48'hc0005fffb, 48'hb0005fffd, 48'hb0004ffff, 48'h900050001, 48'h40001fffe, 48'hfff8fff7fff7, 48'hffedffedffef, 48'hffeefff0fff2, 48'hfffbfffdfffe, 48'h9000a000b, 48'hd000d000d, 48'h500040002, 48'hfffafff9fff8, 48'hfffdfffcfffd, 48'h500060008, 48'h600070008, 48'hfffbfffcfffb, 48'hfff9fff8fff6, 48'hfffdfffbfff6, 48'h2fffdfff7, 48'hfff9fff3ffee, 48'h2fffcfff3, 48'h70000fff6, 48'h6fffffff4, 48'h6fffffff4, 48'h70000fff5, 48'h1fffcfff9, 48'h400000000, 48'h40001fffe, 48'h70001fffa, 48'ha0002fff9, 48'hb0003fff8, 48'hb0003fff7, 48'h90003fffb, 48'h40001fffd, 48'hfff8fff7fff7, 48'hffeeffedffee, 48'hffedffeeffef, 48'hfff5fff6fff9, 48'h500070009, 48'hb000d000e, 48'h500050003, 48'h2fffefff9, 48'h3fffefff5, 48'h1fffcfff5, 48'hfffefffbfff9, 48'h10001, 48'hfffe00000001, 48'hfffeffff0000, 48'hfffcfffafffb, 48'hfffcfffafff4, 48'h40000fffa, 48'hfffcfff8fff7, 48'hfff6fff3ffef, 48'h4fffdfff1, 48'h6fffefff1, 48'h5fffdfff0, 48'h6fffefff1, 48'h1fffafff5, 48'hfffffffafffc, 48'h200010004, 48'h40001fffe, 48'h6fffffff7, 48'h80001fff4, 48'ha0003fff7, 48'hfffefffafff4, 48'hffedffedffec, 48'hffe7ffe9ffeb, 48'hfff5fff7fff8, 48'h600080009, 48'hd000e000f, 48'h600060005, 48'hfffefffcfff7, 48'hfffffffbfff3, 48'h5fffefff3, 48'h9fffffff2, 48'h8fffefff2, 48'hfffffff9fff2, 48'hfffafff8fff6, 48'hfffcfffeffff, 48'hffff00010003, 48'hffffffff0002, 48'hfffafffafff9, 48'hfffffffefffb, 48'hfff6fff5fff8, 48'hffeaffebffe9, 48'hfffaffed, 48'h6fffdffee, 48'h4fffcffed, 48'h6fffdffed, 48'h9fffdfff0, 48'hfff8fff4, 48'hfffafffaffff, 48'h100020004, 48'h60002ffff, 48'h50000fff8, 48'hfffcfff8fff2, 48'hffeeffecffed, 48'hfff1fff3fff5, 48'h200030004, 48'ha000b000b, 48'h800080006, 48'h1fffffffa, 48'hfffffffafff2, 48'h5fffdfff0, 48'h8fffffff1, 48'h9ffffffef, 48'h8fffdffed, 48'h9fffeffed, 48'h8fffdfff0, 48'hfffafff2, 48'hfffdfffbfff9, 48'h2, 48'h200030004, 48'hfffdfffdfffe, 48'hfff8fff7fff5, 48'hfff9fff8fff5, 48'hfff6fff3ffeb, 48'hfffffff7ffe8, 48'h5fffbffeb, 48'h4fffaffe9, 48'h6fffaffe9, 48'h9fffcffeb, 48'h5fffcffee, 48'hfffafff7fff3, 48'hfffdfffcfffb, 48'h700040002, 48'hfffffffefffa, 48'hfff4fff4fff4, 48'hfffbfffafffd, 48'hfffffffffffe, 48'hfffffffd, 48'hfffdfff9, 48'hfffafff1, 48'h4fffbffee, 48'h8fffeffee, 48'h8fffeffee, 48'h8fffeffee, 48'h8fffdffed, 48'h8fffdffec, 48'h8fffdffec, 48'h8fffcffed, 48'h6fffbffed, 48'hfffffff8ffef, 48'hfffffffdfffa, 48'hfffe0000ffff, 48'hfff8fffcfff8, 48'hfffafff8fff8, 48'hfffcfff6ffed, 48'h2fff8ffe9, 48'h2fff6ffe6, 48'h5fff9ffe7, 48'h4fff8ffe6, 48'h5fff8ffe6, 48'h9fffaffe7, 48'h6fffcffe6, 48'h1fffaffeb, 48'hfffdfff7fff2, 48'hfffdfffafff9, 48'hfff5fff8fff8, 48'hfff3fff7fffa, 48'hffefffeffff2, 48'hfff4fff0ffeb, 48'hfffffff7ffec, 48'h4fffaffed, 48'h8fffcffec, 48'h9fffcffea, 48'h8fffcffea, 48'h7fffcffeb, 48'h7fffcffea, 48'h8fffbffe9, 48'h8fffbffe8, 48'h6fffaffe9, 48'h8fffaffe9, 48'hafffbffe6, 48'h6fff9ffe8, 48'hfffbfff5ffed, 48'hfff5fff7fff8, 48'hfff7fffcffff, 48'hfff8fff8fffb, 48'hfffcfff7ffec, 48'h4fff8ffe3, 48'h5fff8ffe5, 48'h4fff7ffe4, 48'h4fff6ffe2, 48'h5fff7ffe2, 48'h8fff9ffe5, 48'h6fffbffe1, 48'h6fffbffe4, 48'hfffcfff4ffeb, 48'hffebffe9ffe9, 48'hffe6ffe9ffe9, 48'hffe9ffebffee, 48'hfff2fff2fff4, 48'hfffbfff7fff0, 48'h7fffaffea, 48'hbfffcffe8, 48'hafffbffe6, 48'h6fffaffe7, 48'h5fff9ffe8, 48'h6fffaffe8, 48'h7fffaffe7, 48'h8fffaffe6, 48'h8fffaffe5, 48'h6fff9ffe6, 48'h8fff9ffe5, 48'hafff9ffe2, 48'h8fff9ffe3, 48'h1fff7ffe7, 48'hfff3ffefffed, 48'hfff1fff1fffc, 48'hfff3fff7fffa, 48'hfff8fff7fff2, 48'hfffefff6ffe4, 48'h3fff7ffe1, 48'h3fff5ffe1, 48'h3fff5ffe0, 48'h5fff6ffe0, 48'h5fff7ffe3, 48'h5fff8ffe1, 48'h8fff9ffe1, 48'hfffbfff2ffe5, 48'hffe1ffe1ffe2, 48'hffe0ffe2ffe2, 48'hffeeffedffeb, 48'hfffbfff9fffa, 48'hfffefffcfff8, 48'h1fff8ffeb, 48'h6fff8ffe6, 48'h9fff9ffe3, 48'h8fff9ffe3, 48'h5fff8ffe4, 48'h5fff8ffe4, 48'h6fff8ffe3, 48'h6fff8ffe3, 48'h7fff8ffe2, 48'h6fff8ffe2, 48'h6fff8ffe2, 48'h6fff7ffe1, 48'h6fff7ffe1, 48'h5fff7ffe1, 48'hfffffff3ffe6, 48'hfff3ffeeffee, 48'hffeeffeffff6, 48'hfff3fff4fff8, 48'hfffbfff5ffee, 48'hfffffff4ffdf, 48'h1fff4ffde, 48'h1fff4ffdd, 48'h3fff5ffdd, 48'h3fff5ffe1, 48'h4fff6ffe0, 48'h8fff7ffde, 48'hfff8fff0ffe3, 48'hffe0ffe1ffe3, 48'hffe7ffe7ffe4, 48'hfff7fff1ffe8, 48'hfffafff3ffec, 48'hfffdfff9fff4, 48'hfffbfff4, 48'h1fff6ffe7, 48'h7fff7ffe1, 48'h9fff8ffdf, 48'h7fff7ffe0, 48'h5fff7ffe1, 48'h5fff6ffe0, 48'h6fff6ffe0, 48'h6fff6ffe0, 48'h6fff6ffdf, 48'h5fff6ffdf, 48'h4fff5ffe0, 48'h4fff5ffdf, 48'h6fff5ffdd, 48'h6fff5ffdd, 48'hfffdfff4ffe0, 48'hfff0ffecffed, 48'hfff1ffeffff8, 48'hfffafff7fffa, 48'hfffefff4ffe4, 48'hfffffff2ffdd, 48'h1fff3ffdc, 48'h3fff4ffdb, 48'h3fff4ffdf, 48'h4fff5ffdd, 48'h7fff6ffdb, 48'hfff4ffedffe3, 48'hffdfffe1ffe3, 48'hffedffe9ffe2, 48'h2fff4ffe2, 48'h3fff4ffe0, 48'hfffffff4ffe5, 48'hfff7ffec, 48'h2fff5ffe4, 48'h6fff5ffde, 48'h6fff6ffdd, 48'h5fff5ffde, 48'h6fff5ffde, 48'h6fff5ffde, 48'h5fff5ffdd, 48'h5fff5ffdd, 48'h5fff4ffdd, 48'h5fff4ffdd, 48'h5fff4ffdd, 48'h5fff4ffdd, 48'h5fff4ffdd, 48'h5fff4ffdc, 48'h2fff5ffda, 48'hfffafff1ffe1, 48'hfff3ffecffed, 48'hfff8fff4fff3, 48'hfffefff4ffe7, 48'hfffefff1ffdd, 48'h2fff2ffda, 48'h4fff2ffda, 48'h3fff3ffdd, 48'h3fff3ffdb, 48'h5fff4ffda, 48'hfff4ffecffe0, 48'hffe6ffe4ffe0, 48'hfff4ffedffe1, 48'h4fff4ffdd, 48'h6fff5ffdc, 48'h1fff3ffdf, 48'hfff3ffe1, 48'h4fff4ffde, 48'h6fff4ffdc, 48'h4fff4ffdc, 48'h3fff4ffdd, 48'h5fff4ffdc, 48'h5fff4ffdc, 48'h4fff3ffdb, 48'h4fff3ffdb, 48'h4fff3ffdb, 48'h4fff3ffdc, 48'h4fff3ffdb, 48'h4fff3ffdb, 48'h4fff3ffdb, 48'h6fff2ffdc, 48'h5fff3ffd8, 48'h2fff2ffdb, 48'hfffdffefffe1, 48'hfffcfff1ffdf, 48'hfffefff1ffdd, 48'hfffffff1ffda, 48'h1fff1ffd8, 48'h2fff1ffd8, 48'h3fff2ffdb, 48'h4fff2ffda, 48'h5fff3ffda, 48'hfff9ffedffdd, 48'hfff2ffebffde, 48'hfffdfff2ffdf, 48'h5fff4ffda, 48'h6fff4ffd8, 48'h4fff3ffdb, 48'h4fff3ffdb, 48'h6fff3ffda, 48'h6fff4ffda, 48'h4fff3ffdb, 48'h3fff3ffdc, 48'h4fff3ffdb, 48'h4fff3ffdb, 48'h4fff2ffda, 48'h4fff2ffda, 48'h4fff2ffda, 48'h4fff3ffda, 48'h4fff2ffda, 48'h4fff2ffda, 48'h4fff2ffda, 48'h4fff1ffda, 48'h5fff2ffd7, 48'h4fff2ffd7, 48'h4fff1ffda, 48'h4fff1ffd7, 48'h2fff1ffd8, 48'hfff0ffd7, 48'hfff0ffd6, 48'hfff0ffd7, 48'h3fff1ffda, 48'h4fff1ffda, 48'h4fff1ffda, 48'hfff1ffdc, 48'hfffdfff1ffdd, 48'h1fff2ffdb, 48'h5fff3ffd8, 48'h6fff3ffd8, 48'h5fff3ffd8, 48'h5fff3ffd8, 48'h6fff3ffd8, 48'h5fff3ffd8, 48'h4fff2ffd9, 48'h3fff2ffda, 48'h4fff2ffd9, 48'h4fff2ffd9, 48'h4fff2ffd9, 48'h4fff2ffd9, 48'h4fff2ffd9, 48'h3fff2ffd8, 48'h3fff1ffd8, 48'h3fff1ffd8, 48'h3fff1ffd8, 48'h2fff1ffd7, 48'h1fff1ffd6, 48'h2fff1ffd8, 48'h3ffefffd9, 48'h3ffeeffd9, 48'h2ffefffd6, 48'hffefffd5, 48'hffffffeeffd5, 48'hffffffeeffd6, 48'h3fff0ffd7, 48'h4ffefffd8, 48'h2ffefffda, 48'h2fff1ffd9, 48'h2fff1ffd9, 48'h2fff1ffd9, 48'h4fff1ffd8, 48'h4fff2ffd8, 48'h4fff2ffd8, 48'h4fff2ffd7, 48'h4fff2ffd7, 48'h4fff1ffd8, 48'h4fff1ffd8, 48'h4fff1ffd8, 48'h3fff1ffd8, 48'h3fff1ffd8, 48'h3fff1ffd7, 48'h3fff1ffd7, 48'h3fff1ffd7, 48'h2fff0ffd7, 48'h2fff0ffd7, 48'h2fff0ffd7, 48'h2fff0ffd7, 48'h1fff0ffd6, 48'hffefffd7, 48'hffefffd7, 48'hffeeffd7, 48'hffedffd7, 48'hffedffd6, 48'hffffffedffd5, 48'hfffdffecffd5, 48'hffedffd5};
wire [15:0] airplane4_pred [9:0] = { 16'hff88, 16'hff36, 16'hfd98, 16'hfbf9, 16'hfabc, 16'hfc38, 16'hfbbe, 16'hff4c, 16'hfec5, 16'h8d7 };
reg clock;
reg reset;
wire rdy_in;
reg vld_in;
wire [15:0] bits_in_0;
wire [15:0] bits_in_1;
wire [15:0] bits_in_2;
reg rdy_out;
wire vld_out;
wire [15:0] bits_out [9:0];
reg [9:0] img_cntr;
wire bits_out_0_correct;
wire [47:0] curr_pixel;
assign curr_pixel = airplane4_image[img_cntr];
assign bits_in_0 = curr_pixel[15:0];
assign bits_in_1 = curr_pixel[31:16];
assign bits_in_2 = curr_pixel[47:32];
assign bits_out_0_correct = ( bits_out == airplane4_pred );
/* Instantiation of top level design */
AWSVggWrapper
dut (
.clock( clock ),
.reset( reset ),
.io_dataIn_ready( rdy_in ),
.io_dataIn_valid( vld_in ),
.io_dataIn_bits_0( bits_in_0 ),
.io_dataIn_bits_1( bits_in_1 ),
.io_dataIn_bits_2( bits_in_2 ),
.io_dataOut_ready( rdy_out ),
.io_dataOut_valid( vld_out ),
.io_dataOut_bits_0( bits_out[0] ),
.io_dataOut_bits_1( bits_out[1] ),
.io_dataOut_bits_2( bits_out[2] ),
.io_dataOut_bits_3( bits_out[3] ),
.io_dataOut_bits_4( bits_out[4] ),
.io_dataOut_bits_5( bits_out[5] ),
.io_dataOut_bits_6( bits_out[6] ),
.io_dataOut_bits_7( bits_out[7] ),
.io_dataOut_bits_8( bits_out[8] ),
.io_dataOut_bits_9( bits_out[9] )
);
/* Add stimulus here */
always #2 clock = ~clock;
always @(posedge clock)
begin
if ( vld_in & rdy_in )
begin
img_cntr <= img_cntr + 1'h1;
end
if ( vld_out )
begin
if ( bits_out_0_correct )
begin
$display("ASSERTION PASSED: %h == %h", bits_out[0], airplane4_pred[0]);
end else begin
$display("ASSERTION FAILED: %h == %h", bits_out[0], airplane4_pred[0]);
end
end
end
initial begin
$timeformat(-9,3,"ns",12);
end
initial begin
clock = 0;
reset = 1;
vld_in = 0;
rdy_out = 1;
img_cntr = 0;
#32
reset = 0;
#32
// start sending data
while ( 1 == 1 )
begin
vld_in = 1; // ( $urandom % 5 ) > 0; // use 1 to measure latency
#4;
end
end
endmodule // aws_vgg_testbench
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND3_PP_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_PP_SYMBOL_V
|
// megafunction wizard: %ALTCLKCTRL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclkctrl
// ============================================================
// File Name: PH2_CLK.v
// Megafunction Name(s):
// altclkctrl
//
// Simulation Library Files(s):
// cycloneii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone II" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
//VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module PH2_CLK_altclkctrl_6df
(
clkselect,
ena,
inclk,
outclk) ;
input [1:0] clkselect;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] clkselect;
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_clkctrl1_outclk;
wire [1:0] clkselect_wire;
wire [3:0] inclk_wire;
cycloneii_clkctrl clkctrl1
(
.clkselect(clkselect_wire),
.ena(ena),
.inclk(inclk_wire),
.outclk(wire_clkctrl1_outclk)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "falling edge",
clkctrl1.lpm_type = "cycloneii_clkctrl";
assign
clkselect_wire = {clkselect},
inclk_wire = {inclk},
outclk = wire_clkctrl1_outclk;
endmodule //PH2_CLK_altclkctrl_6df
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PH2_CLK (
inclk,
outclk);
input inclk;
output outclk;
wire sub_wire0;
wire [1:0] sub_wire1 = 2'h0;
wire sub_wire2 = 1'h1;
wire [2:0] sub_wire5 = 3'h0;
wire outclk = sub_wire0;
wire sub_wire3 = inclk;
wire [3:0] sub_wire4 = {sub_wire5, sub_wire3};
PH2_CLK_altclkctrl_6df PH2_CLK_altclkctrl_6df_component (
.clkselect (sub_wire1),
.ena (sub_wire2),
.inclk (sub_wire4),
.outclk (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
// Retrieval info: CONSTANT: clock_type STRING "Global Clock"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK_bb.v TRUE
// Retrieval info: LIB_FILE: cycloneii
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: ps2_keyboard.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ([email protected])
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
// [email protected]
////////////////////////////////////////////////////////////////////////////////
module ps2_keyboard (
CLK,
RESET_N,
PS2_CLK,
PS2_DATA,
RX_PRESSED,
RX_EXTENDED,
RX_SCAN
);
input CLK;
input RESET_N;
input PS2_CLK;
input PS2_DATA;
output RX_PRESSED;
reg RX_PRESSED;
output RX_EXTENDED;
reg RX_EXTENDED;
output [7:0] RX_SCAN;
reg [7:0] RX_SCAN;
reg KB_CLK;
reg KB_DATA;
reg KB_CLK_B;
reg KB_DATA_B;
reg PRESSED_N;
reg EXTENDED;
reg [2:0] BIT;
reg [3:0] STATE;
reg [7:0] SCAN;
wire PARITY;
reg [10:0] TIMER;
reg KILLER;
wire RESET_X;
// Double buffer
always @ (posedge CLK)
begin
KB_CLK_B <= PS2_CLK;
KB_DATA_B <= PS2_DATA;
KB_CLK <= KB_CLK_B;
KB_DATA <= KB_DATA_B;
end
assign PARITY = ~(((SCAN[0]^SCAN[1])
^(SCAN[2]^SCAN[3]))
^((SCAN[4]^SCAN[5])
^(SCAN[6]^SCAN[7])));
assign RESET_X = RESET_N & KILLER;
always @ (negedge CLK or negedge RESET_N)
if(!RESET_N)
begin
KILLER <= 1'b1;
TIMER <= 11'h000;
end
else
case(TIMER)
11'h000:
begin
KILLER <= 1'b1;
if(STATE != 4'h0)
TIMER <= 11'h001;
end
11'h7FD:
begin
KILLER <= 1'b0;
TIMER <= 11'h7FE;
end
default:
if(STATE == 4'h0)
TIMER <= 11'h000;
else
TIMER <= TIMER + 1'b1;
endcase
always @ (posedge CLK or negedge RESET_X)
begin
if(!RESET_X)
begin
STATE <= 4'h0;
SCAN <= 8'h00;
BIT <= 3'b000;
RX_SCAN <= 8'h00;
RX_PRESSED <= 1'b0;
RX_EXTENDED <= 1'b0;
PRESSED_N <= 1'b0;
EXTENDED <= 1'b0;
end
else
begin
case (STATE)
4'h0: // Hunt for start bit
begin
BIT <= 3'b000;
RX_SCAN <= 8'h00;
RX_PRESSED <= 1'b0;
RX_EXTENDED <= 1'b0;
if(~KB_DATA & ~KB_CLK) //look for start bit
STATE <= 4'h1;
end
4'h1: // next bit
begin
if(KB_CLK)
STATE <= 4'h2;
end
4'h2: // Hunt for Bit
begin
if(~KB_CLK)
begin
SCAN[BIT] <= KB_DATA;
BIT <= BIT + 1'b1;
if(BIT == 3'b111)
STATE <= 4'h3;
else
STATE <= 4'h1;
end
end
4'h3: // Hunt for Bit
begin
if(KB_CLK)
STATE <= 4'h4;
end
4'h4: // Test parity
begin
if(~KB_CLK)
begin
if(KB_DATA == PARITY)
STATE <= 4'h5;
else
begin
PRESSED_N <= 1'b0;
EXTENDED <= 1'b0;
SCAN <= 8'h00;
STATE <= 4'hF;
end
end
end
4'h5: // Look for Stop bit
begin
if(KB_CLK)
STATE <= 4'h6;
end
4'h6: // Stop bit
begin
if(~KB_CLK)
STATE <= 4'h7;
end
4'h7:
begin
if(SCAN ==8'hE0)
begin
EXTENDED <= 1'b1;
STATE <= 4'hF;
end
else
if(SCAN == 8'hF0)
begin
PRESSED_N <= 1'b1;
STATE <= 4'hF;
end
else
begin
RX_SCAN <= SCAN;
RX_PRESSED <= ~PRESSED_N;
RX_EXTENDED <= EXTENDED;
PRESSED_N <= 1'b0;
EXTENDED <= 1'b0;
SCAN <= 8'h00;
STATE <= 4'hF;
end
end
4'h8:
begin
STATE <= 4'h9;
end
4'h9:
begin
STATE <= 4'hA;
end
4'hA:
begin
STATE <= 4'hB;
end
4'hB:
begin
STATE <= 4'hC;
end
4'hC:
begin
STATE <= 4'hD;
end
4'hD:
begin
STATE <= 4'hE;
end
4'hE:
begin
STATE <= 4'hF;
end
4'hF:
begin
if(KB_CLK)
STATE <= 4'h0;
end
endcase
end
end
endmodule
|
module IDELAYE2 (/*AUTOARG*/
// Outputs
CNTVALUEOUT, DATAOUT,
// Inputs
C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN,
REGRST
);
parameter CINVCTRL_SEL = "FALSE"; // Enable dynamic clock inversion
parameter DELAY_SRC = "IDATAIN"; // Delay input
parameter HIGH_PERFORMANCE_MODE = "FALSE"; // Reduced jitter
parameter IDELAY_TYPE = "FIXED"; // Type of delay line
parameter integer IDELAY_VALUE = 0; // Input delay tap setting
parameter [0:0] IS_C_INVERTED = 1'b0; //
parameter [0:0] IS_DATAIN_INVERTED = 1'b0; //
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; //
parameter PIPE_SEL = "FALSE"; // Select pipelined mode
parameter real REFCLK_FREQUENCY = 200.0; // Ref clock frequency
parameter SIGNAL_PATTERN = "DATA"; // Input signal type
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT; // count value for monitoring tap value
output DATAOUT; // delayed data
input C; // clock input for variable mode
input CE; // enable increment/decrement function
input CINVCTRL; // dynamically inverts clock polarity
input [4:0] CNTVALUEIN; // counter value for tap delay
input DATAIN; // data input from FGPA logic
input IDATAIN; // data input from IBUF
input INC; // increment tap delay
input LD; // loads the delay primitive
input LDPIPEEN; // enables the pipeline register delay
input REGRST; // reset for pipeline register
assign DATAOUT = IDATAIN;
initial
begin
//$display("Delay %d %m",IDELAY_VALUE);
end
reg [4:0] idelay_reg=5'b0;
always @ (posedge C)
if(LD)
begin
idelay_reg[4:0] <= CNTVALUEIN[4:0];
$display("Delay %d",idelay_reg[4:0]);
end
endmodule // IDELAYE2
|
/* One step in the argmin tree.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`ifndef CENSUS_ARGMIN_STAGE_V_
`define CENSUS_ARGMIN_STAGE_V_
`timescale 1ns/1ps
`include "dff.v"
// This is an individual stage of the argmin tree. It takes in two arguments,
// along with their candidates for the argmin value, and produces a new
// candidate (the minimum of the two inputs), and a new argmin value. The
// argmin value gets a 0 in the stage's bit if the left input is smaller, and
// a 1 if the right input is smaller.
module argmin_stage#(
parameter WIDTH=1,
parameter ADDR_WIDTH=1,
parameter STAGE=1
) (
input wire clk,
input wire rst,
input wire [WIDTH-1:0] left_val,
// One bit of the address input will go unused
/* verilator lint_off UNUSED */
input wire [ADDR_WIDTH-1:0] left_addr,
/* verilator lint_on UNUSED */
input wire [WIDTH-1:0] right_val,
/* verilator lint_off UNUSED */
input wire [ADDR_WIDTH-1:0] right_addr,
/* verilator lint_on UNUSED */
output wire [WIDTH-1:0] outp,
output wire [ADDR_WIDTH-1:0] outp_addr
);
wire left_lte;
wire [WIDTH-1:0] outp_next;
wire [ADDR_WIDTH-1:0] outp_addr_next;
dff#(.WIDTH(WIDTH)) out_ff(clk, rst, outp_next, outp);
dff#(.WIDTH(ADDR_WIDTH)) out_addr_ff(clk, rst, outp_addr_next, outp_addr);
assign left_lte = left_val <= right_val;
assign outp_next = left_lte ? left_val : right_val;
genvar i;
generate
for (i = 0; i < ADDR_WIDTH; i++) begin
if (i == STAGE) begin
assign outp_addr_next[i] = !left_lte;
end else begin
assign outp_addr_next[i] = left_lte ? left_addr[i] : right_addr[i];
end
end
endgenerate
endmodule
`endif // CENSUS_ARGMIN_STAGE_V_
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_BEHAVIORAL_V
`define SKY130_FD_SC_HS__MAJ3_BEHAVIORAL_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire csi_opt_296, and0_out ;
wire csi_opt_296, and1_out ;
wire or0_out ;
wire or1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_BEHAVIORAL_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:09:13 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_rst_ps7_0_100M_0_stub.v
// Design : zqynq_lab_1_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
// bsg_nonsynth_mixin_motherboard_comm_link
//
// This module is a mixin module, because it is parameterize by a module name
// and two submodules that need to be predefined.
//
// This file is a generic motherboard testing module; there are two "sockets"
// for chips. These chips have standard electrical interfaces corresponding
// to the bsg comm link. One socket is for the chipset, and the other is for the
// chip.
//
// To use this module, you must set three defines:
//
// BSG_NONSYNTH_MIXIN_MOTHERBOARD_module_name - the name of the motherboard module
//
// BSG_NONSYNTH_MIXIN_MOTHERBOARD_chipset_sig - partial instantiation of chipset module
// BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig - partial instantiation of the chip module
//
//
//
`include "bsg_defines.v"
`ifndef BSG_NONSYNTH_MIXIN_MOTHERBOARD_module_name
ERROR in bsg_nonsynth_mixin_motherboard.v: BSG_NONSYNTH_MIXIN_MOTHERBOARD_module_name must be defined
`endif
`ifndef BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig
ERROR in bsg_nonsynth_mixin_motherboard.v: BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig must be defined
`endif
`ifndef BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig
ERROR in bsg_nonsynth_mixin_motherboard.v: BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig must be defined
`endif
// note: this module is non-synthesizable
module `BSG_NONSYNTH_MOTHERBOARD_MIXIN_module_name
#( parameter `BSG_INV_PARAM(tile_x_max_p )
, parameter `BSG_INV_PARAM(tile_y_max_p )
, parameter asic_core_period_p = 5ns
, parameter chipset_core_period_p = 6ns
, parameter asic_io_master_period_p = 7ns
, parameter chipset_io_master_period_p = 8ns
, parameter tline_delay_p = 5ns // we could change this to have different delays
// defaults; usually do not change
, parameter num_channels_p = 4
, parameter channel_width_p = 8
)
( output logic asic_core_clock_o
, output logic asic_core_reset_o
);
wire asic_core_clk_i;
wire asic_async_reset_i;
wire asic_io_master_clk_i;
wire chipset_core_clk_i;
wire chipset_async_reset_i;
wire chipset_io_master_clk_i;
assign asic_core_clock_o = asic_core_clk_i;
bsg_nonsynth_clock_gen #(.cycle_time_p(asic_core_period_p)) asic_clk (.o(asic_core_clk_i ));
bsg_nonsynth_clock_gen #(.cycle_time_p(chipset_core_period_p)) chipset_clk (.o(chipset_core_clk_i));
initial
$display("%m creating clocks"
,asic_core_period_p , chipset_core_period_p
,asic_io_master_period_p, chipset_io_master_period_p);
bsg_nonsynth_clock_gen #(.cycle_time_p(asic_io_master_period_p)) i0_clk (.o(asic_io_master_clk_i ));
bsg_nonsynth_clock_gen #(.cycle_time_p(chipset_io_master_period_p)) i1_clk (.o(chipset_io_master_clk_i));
localparam core_reset_cycles_hi_lp = 256;
localparam core_reset_cycles_lo_lp = 16;
bsg_nonsynth_reset_gen
#(.num_clocks_p(4)
,.reset_cycles_lo_p(core_reset_cycles_lo_lp)
,.reset_cycles_hi_p(core_reset_cycles_hi_lp)
) reset_gen
(.clk_i({ asic_core_clk_i, asic_io_master_clk_i, chipset_core_clk_i, chipset_io_master_clk_i })
,.async_reset_o(chipset_async_reset_i)
);
wire [num_channels_p-1:0] asic_io_clk_tline_i;
wire [num_channels_p-1:0] asic_io_valid_tline_i;
wire [channel_width_p-1:0] asic_io_data_tline_i [num_channels_p-1:0];
wire [num_channels_p-1:0] asic_io_token_clk_tline_o;
// out to i/o
wire [num_channels_p-1:0] asic_im_clk_tline_o;
wire [num_channels_p-1:0] asic_im_valid_tline_o;
wire [channel_width_p-1:0] asic_im_data_tline_o [num_channels_p-1:0];
wire [num_channels_p-1:0] asic_token_clk_tline_i;
wire [num_channels_p-1:0] chipset_io_clk_tline_i;
wire [num_channels_p-1:0] chipset_io_valid_tline_i;
wire [channel_width_p-1:0] chipset_io_data_tline_i [num_channels_p-1:0];
wire [num_channels_p-1:0] chipset_io_token_clk_tline_o;
// out to i/o
wire [num_channels_p-1:0] chipset_im_clk_tline_o;
wire [num_channels_p-1:0] chipset_im_valid_tline_o;
wire [channel_width_p-1:0] chipset_im_data_tline_o [num_channels_p-1:0];
wire [num_channels_p-1:0] chipset_token_clk_tline_i;
wire chipset_im_slave_reset_tline_r_o;
wire chipset_core_reset_o;
// **************************
// the FPGA
/*
bsg_nonsynth_raw_chipset_vtile_pli #(.tile_x_max_p(tile_x_max_p)
,.tile_y_max_p(tile_y_max_p)
,.channel_width_p(channel_width_p)
,.num_channels_p(num_channels_p)
,.master_bypass_test_p(5'b11111) // speed up simulation
,.enabled_at_start_vec_p( { (tile_x_max_p+1) {1'b1 } })
) */
`BSG_NONSYNTH_MIXIN_MOTHERBOARD_chipset_sig
chipset
(
.core_clk_i(chipset_core_clk_i)
, .async_reset_i(chipset_async_reset_i)
, .io_master_clk_i(chipset_io_master_clk_i)
// input from i/o
, .io_clk_tline_i (chipset_io_clk_tline_i) // clk
, .io_valid_tline_i(chipset_io_valid_tline_i)
, .io_data_tline_i (chipset_io_data_tline_i)
, .io_token_clk_tline_o(chipset_io_token_clk_tline_o) // clk
// out to i/o
, .im_clk_tline_o (chipset_im_clk_tline_o ) // clk
, .im_valid_tline_o (chipset_im_valid_tline_o )
, .im_data_tline_o (chipset_im_data_tline_o )
, .token_clk_tline_i(chipset_token_clk_tline_i) // clk
// note: generate by the master (FPGA) and sent to the slave (ASIC)
// not used by slave (ASIC).
, .im_slave_reset_tline_r_o(chipset_im_slave_reset_tline_r_o)
// this signal is the post-calibration reset signal
// synchronous to the core clock
, .core_reset_o(chipset_core_reset_o)
);
// **************************
// PC board traces
//
// we introduce delays in the transmission lines that
// go between chips; technically we could use different delays
//
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl0
(.i(asic_im_clk_tline_o), .o(chipset_io_clk_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl1
(.i(chipset_im_clk_tline_o), .o(asic_io_clk_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl2
(.i(asic_im_valid_tline_o), .o(chipset_io_valid_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl3
(.i(chipset_im_valid_tline_o), .o(asic_io_valid_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl4
(.i(asic_io_token_clk_tline_o), .o(chipset_token_clk_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl5
(.i(chipset_io_token_clk_tline_o), .o(asic_token_clk_tline_i));
genvar i;
for (i=0; i < num_channels_p; i++)
begin: rof
bsg_nonsynth_delay_line #(.width_p(channel_width_p), .delay_p(tline_delay_p)) bdl6
(.i(asic_im_data_tline_o[i]), .o(chipset_io_data_tline_i[i]));
bsg_nonsynth_delay_line #(.width_p(channel_width_p), .delay_p(tline_delay_p)) bdl7
(.i(chipset_im_data_tline_o[i]), .o(asic_io_data_tline_i[i]));
end
bsg_nonsynth_delay_line #(.width_p(1), .delay_p(tline_delay_p)) bdl8
(.i(chipset_im_slave_reset_tline_r_o), .o(asic_async_reset_i));
// **************************
// the ASIC
/*
bsg_guts_greendroid_node #(.tile_x_max_p(tile_x_max_p)
,.tile_y_max_p(tile_y_max_p)
,.south_side_only_p(1)
)
*/
`BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig
asic
(.core_clk_i(asic_core_clk_i)
, .async_reset_i(asic_async_reset_i)
, .io_master_clk_i(asic_io_master_clk_i)
// input from i/o
, .io_clk_tline_i (asic_io_clk_tline_i ) // clk
, .io_valid_tline_i(asic_io_valid_tline_i)
, .io_data_tline_i (asic_io_data_tline_i )
, .io_token_clk_tline_o(asic_io_token_clk_tline_o) // clk
// out to i/o
, .im_clk_tline_o (asic_im_clk_tline_o ) // clk
, .im_valid_tline_o (asic_im_valid_tline_o )
, .im_data_tline_o (asic_im_data_tline_o )
, .token_clk_tline_i(asic_token_clk_tline_i) // clk
// note: generate by the master (FPGA) and sent to the slave (ASIC)
// not used by slave (ASIC).
, .im_slave_reset_tline_r_o() // unused; fixme remove?
// this signal is the post-calibration reset signal
// synchronous to the core clock
, .core_reset_o(asic_core_reset_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_mixin_motherboard)
|
module eim_burstcnt(
input wire bclk,
// sync to bclk
input wire [15:0] bus_ad, // raw mux data
input wire [2:0] bus_a, // high address bits
input wire adv, // active high, so connect to !EIM_LBA
input wire rw, // low = write, high = read, so connect to EIM_RW
input wire cs, // active high, so connect to !EIM_CS[1]
output reg [15:0] measured_burst
);
reg activated;
reg [15:0] bus_ad_r;
reg cs_r;
reg [2:0] bus_a_r;
reg rw_r;
reg adv_r;
reg [15:0] burstcnt;
reg [15:0] finalcnt;
reg activated_d;
always @(posedge bclk) begin
bus_ad_r <= bus_ad;
bus_a_r <= bus_a;
cs_r <= cs;
rw_r <= rw;
adv_r <= adv;
if( cs_r && adv_r && ({bus_a_r, bus_ad_r[15:12]} == 7'h4_F) ) begin // 0xc04_fxxx page for bursting
activated <= 1'b1;
end else if( !cs_r ) begin
activated <= 1'b0;
end else begin
activated <= activated;
end // else: !if( !cs )
if( !activated ) begin
finalcnt <= burstcnt;
burstcnt <= 16'h0;
end else begin
burstcnt <= burstcnt + 16'h1;
finalcnt <= finalcnt;
end
activated_d <= activated;
if( activated_d & !activated ) begin // on falling edge of activated...
measured_burst <= finalcnt + 1'b1; // account for 0-offset indexing
end else begin
measured_burst <= measured_burst;
end
end // always @ (posedge clk)
endmodule // eim_burstcnt
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: counter_bus_mux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module counter_bus_mux (
data0x,
data1x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
wire [3:0] sub_wire5;
wire [3:0] sub_wire2 = data1x[3:0];
wire [3:0] sub_wire0 = data0x[3:0];
wire [7:0] sub_wire1 = {sub_wire2, sub_wire0};
wire sub_wire3 = sel;
wire sub_wire4 = sub_wire3;
wire [3:0] result = sub_wire5[3:0];
lpm_mux LPM_MUX_component (
.data (sub_wire1),
.sel (sub_wire4),
.result (sub_wire5)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 2,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 4,
LPM_MUX_component.lpm_widths = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL "data0x[3..0]"
// Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL "data1x[3..0]"
// Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 4 0 data0x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 4 data1x 0 0 4 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
Require Import ssrfun ssrbool.
Require Export ProjectiveGeometry.Dev.fano_matroid_tactics.
(** Pg(2,5). **)
(** To show that our axiom system is consistent we build a finite model. **)
(*****************************************************************************)
Section s_fanoPlaneModelRkPG25.
(* fano_plane_model_rk_pg25_spec.v: #points = 31, #lines = 31 *)
Parameter
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 : Point.
Parameter rk_points :
rk (P0 :: nil) = 1 /\ rk (P1 :: nil) = 1 /\ rk (P2 :: nil) = 1 /\ rk (P3 :: nil) = 1 /\ rk (P4 :: nil) = 1 /\ rk (P5 :: nil) = 1 /\ rk (P6 :: nil) = 1 /\ rk (P7 :: nil) = 1 /\ rk (P8 :: nil) = 1 /\ rk (P9 :: nil) = 1 /\ rk (P10 :: nil) = 1 /\ rk (P11 :: nil) = 1 /\ rk (P12 :: nil) = 1 /\ rk (P13 :: nil) = 1 /\ rk (P14 :: nil) = 1 /\ rk (P15 :: nil) = 1 /\ rk (P16 :: nil) = 1 /\ rk (P17 :: nil) = 1 /\ rk (P18 :: nil) = 1 /\ rk (P19 :: nil) = 1 /\ rk (P20 :: nil) = 1 /\ rk (P21 :: nil) = 1 /\ rk (P22 :: nil) = 1 /\ rk (P23 :: nil) = 1 /\ rk (P24 :: nil) = 1 /\ rk (P25 :: nil) = 1 /\ rk (P26 :: nil) = 1 /\ rk (P27 :: nil) = 1 /\ rk (P28 :: nil) = 1 /\ rk (P29 :: nil) = 1 /\ rk (P30 :: nil) = 1 .
Parameter rk_distinct_points :
rk (P0 :: P1 :: nil) = 2 /\ rk (P0 :: P2 :: nil) = 2 /\ rk (P0 :: P3 :: nil) = 2 /\ rk (P0 :: P4 :: nil) = 2 /\ rk (P0 :: P5 :: nil) = 2 /\ rk (P0 :: P6 :: nil) = 2 /\ rk (P0 :: P7 :: nil) = 2 /\ rk (P0 :: P8 :: nil) = 2 /\ rk (P0 :: P9 :: nil) = 2 /\ rk (P0 :: P10 :: nil) = 2 /\ rk (P0 :: P11 :: nil) = 2 /\ rk (P0 :: P12 :: nil) = 2 /\ rk (P0 :: P13 :: nil) = 2 /\ rk (P0 :: P14 :: nil) = 2 /\ rk (P0 :: P15 :: nil) = 2 /\ rk (P0 :: P16 :: nil) = 2 /\ rk (P0 :: P17 :: nil) = 2 /\ rk (P0 :: P18 :: nil) = 2 /\ rk (P0 :: P19 :: nil) = 2 /\ rk (P0 :: P20 :: nil) = 2 /\ rk (P0 :: P21 :: nil) = 2 /\ rk (P0 :: P22 :: nil) = 2 /\ rk (P0 :: P23 :: nil) = 2 /\ rk (P0 :: P24 :: nil) = 2 /\ rk (P0 :: P25 :: nil) = 2 /\ rk (P0 :: P26 :: nil) = 2 /\ rk (P0 :: P27 :: nil) = 2 /\ rk (P0 :: P28 :: nil) = 2 /\ rk (P0 :: P29 :: nil) = 2 /\ rk (P0 :: P30 :: nil) = 2 /\ rk (P1 :: P2 :: nil) = 2 /\ rk (P1 :: P3 :: nil) = 2 /\ rk (P1 :: P4 :: nil) = 2 /\ rk (P1 :: P5 :: nil) = 2 /\ rk (P1 :: P6 :: nil) = 2 /\ rk (P1 :: P7 :: nil) = 2 /\ rk (P1 :: P8 :: nil) = 2 /\ rk (P1 :: P9 :: nil) = 2 /\ rk (P1 :: P10 :: nil) = 2 /\ rk (P1 :: P11 :: nil) = 2 /\ rk (P1 :: P12 :: nil) = 2 /\ rk (P1 :: P13 :: nil) = 2 /\ rk (P1 :: P14 :: nil) = 2 /\ rk (P1 :: P15 :: nil) = 2 /\ rk (P1 :: P16 :: nil) = 2 /\ rk (P1 :: P17 :: nil) = 2 /\ rk (P1 :: P18 :: nil) = 2 /\ rk (P1 :: P19 :: nil) = 2 /\ rk (P1 :: P20 :: nil) = 2 /\ rk (P1 :: P21 :: nil) = 2 /\ rk (P1 :: P22 :: nil) = 2 /\ rk (P1 :: P23 :: nil) = 2 /\ rk (P1 :: P24 :: nil) = 2 /\ rk (P1 :: P25 :: nil) = 2 /\ rk (P1 :: P26 :: nil) = 2 /\ rk (P1 :: P27 :: nil) = 2 /\ rk (P1 :: P28 :: nil) = 2 /\ rk (P1 :: P29 :: nil) = 2 /\ rk (P1 :: P30 :: nil) = 2 /\ rk (P2 :: P3 :: nil) = 2 /\ rk (P2 :: P4 :: nil) = 2 /\ rk (P2 :: P5 :: nil) = 2 /\ rk (P2 :: P6 :: nil) = 2 /\ rk (P2 :: P7 :: nil) = 2 /\ rk (P2 :: P8 :: nil) = 2 /\ rk (P2 :: P9 :: nil) = 2 /\ rk (P2 :: P10 :: nil) = 2 /\ rk (P2 :: P11 :: nil) = 2 /\ rk (P2 :: P12 :: nil) = 2 /\ rk (P2 :: P13 :: nil) = 2 /\ rk (P2 :: P14 :: nil) = 2 /\ rk (P2 :: P15 :: nil) = 2 /\ rk (P2 :: P16 :: nil) = 2 /\ rk (P2 :: P17 :: nil) = 2 /\ rk (P2 :: P18 :: nil) = 2 /\ rk (P2 :: P19 :: nil) = 2 /\ rk (P2 :: P20 :: nil) = 2 /\ rk (P2 :: P21 :: nil) = 2 /\ rk (P2 :: P22 :: nil) = 2 /\ rk (P2 :: P23 :: nil) = 2 /\ rk (P2 :: P24 :: nil) = 2 /\ rk (P2 :: P25 :: nil) = 2 /\ rk (P2 :: P26 :: nil) = 2 /\ rk (P2 :: P27 :: nil) = 2 /\ rk (P2 :: P28 :: nil) = 2 /\ rk (P2 :: P29 :: nil) = 2 /\ rk (P2 :: P30 :: nil) = 2 /\ rk (P3 :: P4 :: nil) = 2 /\ rk (P3 :: P5 :: nil) = 2 /\ rk (P3 :: P6 :: nil) = 2 /\ rk (P3 :: P7 :: nil) = 2 /\ rk (P3 :: P8 :: nil) = 2 /\ rk (P3 :: P9 :: nil) = 2 /\ rk (P3 :: P10 :: nil) = 2 /\ rk (P3 :: P11 :: nil) = 2 /\ rk (P3 :: P12 :: nil) = 2 /\ rk (P3 :: P13 :: nil) = 2 /\ rk (P3 :: P14 :: nil) = 2 /\ rk (P3 :: P15 :: nil) = 2 /\ rk (P3 :: P16 :: nil) = 2 /\ rk (P3 :: P17 :: nil) = 2 /\ rk (P3 :: P18 :: nil) = 2 /\ rk (P3 :: P19 :: nil) = 2 /\ rk (P3 :: P20 :: nil) = 2 /\ rk (P3 :: P21 :: nil) = 2 /\ rk (P3 :: P22 :: nil) = 2 /\ rk (P3 :: P23 :: nil) = 2 /\ rk (P3 :: P24 :: nil) = 2 /\ rk (P3 :: P25 :: nil) = 2 /\ rk (P3 :: P26 :: nil) = 2 /\ rk (P3 :: P27 :: nil) = 2 /\ rk (P3 :: P28 :: nil) = 2 /\ rk (P3 :: P29 :: nil) = 2 /\ rk (P3 :: P30 :: nil) = 2 /\ rk (P4 :: P5 :: nil) = 2 /\ rk (P4 :: P6 :: nil) = 2 /\ rk (P4 :: P7 :: nil) = 2 /\ rk (P4 :: P8 :: nil) = 2 /\ rk (P4 :: P9 :: nil) = 2 /\ rk (P4 :: P10 :: nil) = 2 /\ rk (P4 :: P11 :: nil) = 2 /\ rk (P4 :: P12 :: nil) = 2 /\ rk (P4 :: P13 :: nil) = 2 /\ rk (P4 :: P14 :: nil) = 2 /\ rk (P4 :: P15 :: nil) = 2 /\ rk (P4 :: P16 :: nil) = 2 /\ rk (P4 :: P17 :: nil) = 2 /\ rk (P4 :: P18 :: nil) = 2 /\ rk (P4 :: P19 :: nil) = 2 /\ rk (P4 :: P20 :: nil) = 2 /\ rk (P4 :: P21 :: nil) = 2 /\ rk (P4 :: P22 :: nil) = 2 /\ rk (P4 :: P23 :: nil) = 2 /\ rk (P4 :: P24 :: nil) = 2 /\ rk (P4 :: P25 :: nil) = 2 /\ rk (P4 :: P26 :: nil) = 2 /\ rk (P4 :: P27 :: nil) = 2 /\ rk (P4 :: P28 :: nil) = 2 /\ rk (P4 :: P29 :: nil) = 2 /\ rk (P4 :: P30 :: nil) = 2 /\ rk (P5 :: P6 :: nil) = 2 /\ rk (P5 :: P7 :: nil) = 2 /\ rk (P5 :: P8 :: nil) = 2 /\ rk (P5 :: P9 :: nil) = 2 /\ rk (P5 :: P10 :: nil) = 2 /\ rk (P5 :: P11 :: nil) = 2 /\ rk (P5 :: P12 :: nil) = 2 /\ rk (P5 :: P13 :: nil) = 2 /\ rk (P5 :: P14 :: nil) = 2 /\ rk (P5 :: P15 :: nil) = 2 /\ rk (P5 :: P16 :: nil) = 2 /\ rk (P5 :: P17 :: nil) = 2 /\ rk (P5 :: P18 :: nil) = 2 /\ rk (P5 :: P19 :: nil) = 2 /\ rk (P5 :: P20 :: nil) = 2 /\ rk (P5 :: P21 :: nil) = 2 /\ rk (P5 :: P22 :: nil) = 2 /\ rk (P5 :: P23 :: nil) = 2 /\ rk (P5 :: P24 :: nil) = 2 /\ rk (P5 :: P25 :: nil) = 2 /\ rk (P5 :: P26 :: nil) = 2 /\ rk (P5 :: P27 :: nil) = 2 /\ rk (P5 :: P28 :: nil) = 2 /\ rk (P5 :: P29 :: nil) = 2 /\ rk (P5 :: P30 :: nil) = 2 /\ rk (P6 :: P7 :: nil) = 2 /\ rk (P6 :: P8 :: nil) = 2 /\ rk (P6 :: P9 :: nil) = 2 /\ rk (P6 :: P10 :: nil) = 2 /\ rk (P6 :: P11 :: nil) = 2 /\ rk (P6 :: P12 :: nil) = 2 /\ rk (P6 :: P13 :: nil) = 2 /\ rk (P6 :: P14 :: nil) = 2 /\ rk (P6 :: P15 :: nil) = 2 /\ rk (P6 :: P16 :: nil) = 2 /\ rk (P6 :: P17 :: nil) = 2 /\ rk (P6 :: P18 :: nil) = 2 /\ rk (P6 :: P19 :: nil) = 2 /\ rk (P6 :: P20 :: nil) = 2 /\ rk (P6 :: P21 :: nil) = 2 /\ rk (P6 :: P22 :: nil) = 2 /\ rk (P6 :: P23 :: nil) = 2 /\ rk (P6 :: P24 :: nil) = 2 /\ rk (P6 :: P25 :: nil) = 2 /\ rk (P6 :: P26 :: nil) = 2 /\ rk (P6 :: P27 :: nil) = 2 /\ rk (P6 :: P28 :: nil) = 2 /\ rk (P6 :: P29 :: nil) = 2 /\ rk (P6 :: P30 :: nil) = 2 /\ rk (P7 :: P8 :: nil) = 2 /\ rk (P7 :: P9 :: nil) = 2 /\ rk (P7 :: P10 :: nil) = 2 /\ rk (P7 :: P11 :: nil) = 2 /\ rk (P7 :: P12 :: nil) = 2 /\ rk (P7 :: P13 :: nil) = 2 /\ rk (P7 :: P14 :: nil) = 2 /\ rk (P7 :: P15 :: nil) = 2 /\ rk (P7 :: P16 :: nil) = 2 /\ rk (P7 :: P17 :: nil) = 2 /\ rk (P7 :: P18 :: nil) = 2 /\ rk (P7 :: P19 :: nil) = 2 /\ rk (P7 :: P20 :: nil) = 2 /\ rk (P7 :: P21 :: nil) = 2 /\ rk (P7 :: P22 :: nil) = 2 /\ rk (P7 :: P23 :: nil) = 2 /\ rk (P7 :: P24 :: nil) = 2 /\ rk (P7 :: P25 :: nil) = 2 /\ rk (P7 :: P26 :: nil) = 2 /\ rk (P7 :: P27 :: nil) = 2 /\ rk (P7 :: P28 :: nil) = 2 /\ rk (P7 :: P29 :: nil) = 2 /\ rk (P7 :: P30 :: nil) = 2 /\ rk (P8 :: P9 :: nil) = 2 /\ rk (P8 :: P10 :: nil) = 2 /\ rk (P8 :: P11 :: nil) = 2 /\ rk (P8 :: P12 :: nil) = 2 /\ rk (P8 :: P13 :: nil) = 2 /\ rk (P8 :: P14 :: nil) = 2 /\ rk (P8 :: P15 :: nil) = 2 /\ rk (P8 :: P16 :: nil) = 2 /\ rk (P8 :: P17 :: nil) = 2 /\ rk (P8 :: P18 :: nil) = 2 /\ rk (P8 :: P19 :: nil) = 2 /\ rk (P8 :: P20 :: nil) = 2 /\ rk (P8 :: P21 :: nil) = 2 /\ rk (P8 :: P22 :: nil) = 2 /\ rk (P8 :: P23 :: nil) = 2 /\ rk (P8 :: P24 :: nil) = 2 /\ rk (P8 :: P25 :: nil) = 2 /\ rk (P8 :: P26 :: nil) = 2 /\ rk (P8 :: P27 :: nil) = 2 /\ rk (P8 :: P28 :: nil) = 2 /\ rk (P8 :: P29 :: nil) = 2 /\ rk (P8 :: P30 :: nil) = 2 /\ rk (P9 :: P10 :: nil) = 2 /\ rk (P9 :: P11 :: nil) = 2 /\ rk (P9 :: P12 :: nil) = 2 /\ rk (P9 :: P13 :: nil) = 2 /\ rk (P9 :: P14 :: nil) = 2 /\ rk (P9 :: P15 :: nil) = 2 /\ rk (P9 :: P16 :: nil) = 2 /\ rk (P9 :: P17 :: nil) = 2 /\ rk (P9 :: P18 :: nil) = 2 /\ rk (P9 :: P19 :: nil) = 2 /\ rk (P9 :: P20 :: nil) = 2 /\ rk (P9 :: P21 :: nil) = 2 /\ rk (P9 :: P22 :: nil) = 2 /\ rk (P9 :: P23 :: nil) = 2 /\ rk (P9 :: P24 :: nil) = 2 /\ rk (P9 :: P25 :: nil) = 2 /\ rk (P9 :: P26 :: nil) = 2 /\ rk (P9 :: P27 :: nil) = 2 /\ rk (P9 :: P28 :: nil) = 2 /\ rk (P9 :: P29 :: nil) = 2 /\ rk (P9 :: P30 :: nil) = 2 /\ rk (P10 :: P11 :: nil) = 2 /\ rk (P10 :: P12 :: nil) = 2 /\ rk (P10 :: P13 :: nil) = 2 /\ rk (P10 :: P14 :: nil) = 2 /\ rk (P10 :: P15 :: nil) = 2 /\ rk (P10 :: P16 :: nil) = 2 /\ rk (P10 :: P17 :: nil) = 2 /\ rk (P10 :: P18 :: nil) = 2 /\ rk (P10 :: P19 :: nil) = 2 /\ rk (P10 :: P20 :: nil) = 2 /\ rk (P10 :: P21 :: nil) = 2 /\ rk (P10 :: P22 :: nil) = 2 /\ rk (P10 :: P23 :: nil) = 2 /\ rk (P10 :: P24 :: nil) = 2 /\ rk (P10 :: P25 :: nil) = 2 /\ rk (P10 :: P26 :: nil) = 2 /\ rk (P10 :: P27 :: nil) = 2 /\ rk (P10 :: P28 :: nil) = 2 /\ rk (P10 :: P29 :: nil) = 2 /\ rk (P10 :: P30 :: nil) = 2 /\ rk (P11 :: P12 :: nil) = 2 /\ rk (P11 :: P13 :: nil) = 2 /\ rk (P11 :: P14 :: nil) = 2 /\ rk (P11 :: P15 :: nil) = 2 /\ rk (P11 :: P16 :: nil) = 2 /\ rk (P11 :: P17 :: nil) = 2 /\ rk (P11 :: P18 :: nil) = 2 /\ rk (P11 :: P19 :: nil) = 2 /\ rk (P11 :: P20 :: nil) = 2 /\ rk (P11 :: P21 :: nil) = 2 /\ rk (P11 :: P22 :: nil) = 2 /\ rk (P11 :: P23 :: nil) = 2 /\ rk (P11 :: P24 :: nil) = 2 /\ rk (P11 :: P25 :: nil) = 2 /\ rk (P11 :: P26 :: nil) = 2 /\ rk (P11 :: P27 :: nil) = 2 /\ rk (P11 :: P28 :: nil) = 2 /\ rk (P11 :: P29 :: nil) = 2 /\ rk (P11 :: P30 :: nil) = 2 /\ rk (P12 :: P13 :: nil) = 2 /\ rk (P12 :: P14 :: nil) = 2 /\ rk (P12 :: P15 :: nil) = 2 /\ rk (P12 :: P16 :: nil) = 2 /\ rk (P12 :: P17 :: nil) = 2 /\ rk (P12 :: P18 :: nil) = 2 /\ rk (P12 :: P19 :: nil) = 2 /\ rk (P12 :: P20 :: nil) = 2 /\ rk (P12 :: P21 :: nil) = 2 /\ rk (P12 :: P22 :: nil) = 2 /\ rk (P12 :: P23 :: nil) = 2 /\ rk (P12 :: P24 :: nil) = 2 /\ rk (P12 :: P25 :: nil) = 2 /\ rk (P12 :: P26 :: nil) = 2 /\ rk (P12 :: P27 :: nil) = 2 /\ rk (P12 :: P28 :: nil) = 2 /\ rk (P12 :: P29 :: nil) = 2 /\ rk (P12 :: P30 :: nil) = 2 /\ rk (P13 :: P14 :: nil) = 2 /\ rk (P13 :: P15 :: nil) = 2 /\ rk (P13 :: P16 :: nil) = 2 /\ rk (P13 :: P17 :: nil) = 2 /\ rk (P13 :: P18 :: nil) = 2 /\ rk (P13 :: P19 :: nil) = 2 /\ rk (P13 :: P20 :: nil) = 2 /\ rk (P13 :: P21 :: nil) = 2 /\ rk (P13 :: P22 :: nil) = 2 /\ rk (P13 :: P23 :: nil) = 2 /\ rk (P13 :: P24 :: nil) = 2 /\ rk (P13 :: P25 :: nil) = 2 /\ rk (P13 :: P26 :: nil) = 2 /\ rk (P13 :: P27 :: nil) = 2 /\ rk (P13 :: P28 :: nil) = 2 /\ rk (P13 :: P29 :: nil) = 2 /\ rk (P13 :: P30 :: nil) = 2 /\ rk (P14 :: P15 :: nil) = 2 /\ rk (P14 :: P16 :: nil) = 2 /\ rk (P14 :: P17 :: nil) = 2 /\ rk (P14 :: P18 :: nil) = 2 /\ rk (P14 :: P19 :: nil) = 2 /\ rk (P14 :: P20 :: nil) = 2 /\ rk (P14 :: P21 :: nil) = 2 /\ rk (P14 :: P22 :: nil) = 2 /\ rk (P14 :: P23 :: nil) = 2 /\ rk (P14 :: P24 :: nil) = 2 /\ rk (P14 :: P25 :: nil) = 2 /\ rk (P14 :: P26 :: nil) = 2 /\ rk (P14 :: P27 :: nil) = 2 /\ rk (P14 :: P28 :: nil) = 2 /\ rk (P14 :: P29 :: nil) = 2 /\ rk (P14 :: P30 :: nil) = 2 /\ rk (P15 :: P16 :: nil) = 2 /\ rk (P15 :: P17 :: nil) = 2 /\ rk (P15 :: P18 :: nil) = 2 /\ rk (P15 :: P19 :: nil) = 2 /\ rk (P15 :: P20 :: nil) = 2 /\ rk (P15 :: P21 :: nil) = 2 /\ rk (P15 :: P22 :: nil) = 2 /\ rk (P15 :: P23 :: nil) = 2 /\ rk (P15 :: P24 :: nil) = 2 /\ rk (P15 :: P25 :: nil) = 2 /\ rk (P15 :: P26 :: nil) = 2 /\ rk (P15 :: P27 :: nil) = 2 /\ rk (P15 :: P28 :: nil) = 2 /\ rk (P15 :: P29 :: nil) = 2 /\ rk (P15 :: P30 :: nil) = 2 /\ rk (P16 :: P17 :: nil) = 2 /\ rk (P16 :: P18 :: nil) = 2 /\ rk (P16 :: P19 :: nil) = 2 /\ rk (P16 :: P20 :: nil) = 2 /\ rk (P16 :: P21 :: nil) = 2 /\ rk (P16 :: P22 :: nil) = 2 /\ rk (P16 :: P23 :: nil) = 2 /\ rk (P16 :: P24 :: nil) = 2 /\ rk (P16 :: P25 :: nil) = 2 /\ rk (P16 :: P26 :: nil) = 2 /\ rk (P16 :: P27 :: nil) = 2 /\ rk (P16 :: P28 :: nil) = 2 /\ rk (P16 :: P29 :: nil) = 2 /\ rk (P16 :: P30 :: nil) = 2 /\ rk (P17 :: P18 :: nil) = 2 /\ rk (P17 :: P19 :: nil) = 2 /\ rk (P17 :: P20 :: nil) = 2 /\ rk (P17 :: P21 :: nil) = 2 /\ rk (P17 :: P22 :: nil) = 2 /\ rk (P17 :: P23 :: nil) = 2 /\ rk (P17 :: P24 :: nil) = 2 /\ rk (P17 :: P25 :: nil) = 2 /\ rk (P17 :: P26 :: nil) = 2 /\ rk (P17 :: P27 :: nil) = 2 /\ rk (P17 :: P28 :: nil) = 2 /\ rk (P17 :: P29 :: nil) = 2 /\ rk (P17 :: P30 :: nil) = 2 /\ rk (P18 :: P19 :: nil) = 2 /\ rk (P18 :: P20 :: nil) = 2 /\ rk (P18 :: P21 :: nil) = 2 /\ rk (P18 :: P22 :: nil) = 2 /\ rk (P18 :: P23 :: nil) = 2 /\ rk (P18 :: P24 :: nil) = 2 /\ rk (P18 :: P25 :: nil) = 2 /\ rk (P18 :: P26 :: nil) = 2 /\ rk (P18 :: P27 :: nil) = 2 /\ rk (P18 :: P28 :: nil) = 2 /\ rk (P18 :: P29 :: nil) = 2 /\ rk (P18 :: P30 :: nil) = 2 /\ rk (P19 :: P20 :: nil) = 2 /\ rk (P19 :: P21 :: nil) = 2 /\ rk (P19 :: P22 :: nil) = 2 /\ rk (P19 :: P23 :: nil) = 2 /\ rk (P19 :: P24 :: nil) = 2 /\ rk (P19 :: P25 :: nil) = 2 /\ rk (P19 :: P26 :: nil) = 2 /\ rk (P19 :: P27 :: nil) = 2 /\ rk (P19 :: P28 :: nil) = 2 /\ rk (P19 :: P29 :: nil) = 2 /\ rk (P19 :: P30 :: nil) = 2 /\ rk (P20 :: P21 :: nil) = 2 /\ rk (P20 :: P22 :: nil) = 2 /\ rk (P20 :: P23 :: nil) = 2 /\ rk (P20 :: P24 :: nil) = 2 /\ rk (P20 :: P25 :: nil) = 2 /\ rk (P20 :: P26 :: nil) = 2 /\ rk (P20 :: P27 :: nil) = 2 /\ rk (P20 :: P28 :: nil) = 2 /\ rk (P20 :: P29 :: nil) = 2 /\ rk (P20 :: P30 :: nil) = 2 /\ rk (P21 :: P22 :: nil) = 2 /\ rk (P21 :: P23 :: nil) = 2 /\ rk (P21 :: P24 :: nil) = 2 /\ rk (P21 :: P25 :: nil) = 2 /\ rk (P21 :: P26 :: nil) = 2 /\ rk (P21 :: P27 :: nil) = 2 /\ rk (P21 :: P28 :: nil) = 2 /\ rk (P21 :: P29 :: nil) = 2 /\ rk (P21 :: P30 :: nil) = 2 /\ rk (P22 :: P23 :: nil) = 2 /\ rk (P22 :: P24 :: nil) = 2 /\ rk (P22 :: P25 :: nil) = 2 /\ rk (P22 :: P26 :: nil) = 2 /\ rk (P22 :: P27 :: nil) = 2 /\ rk (P22 :: P28 :: nil) = 2 /\ rk (P22 :: P29 :: nil) = 2 /\ rk (P22 :: P30 :: nil) = 2 /\ rk (P23 :: P24 :: nil) = 2 /\ rk (P23 :: P25 :: nil) = 2 /\ rk (P23 :: P26 :: nil) = 2 /\ rk (P23 :: P27 :: nil) = 2 /\ rk (P23 :: P28 :: nil) = 2 /\ rk (P23 :: P29 :: nil) = 2 /\ rk (P23 :: P30 :: nil) = 2 /\ rk (P24 :: P25 :: nil) = 2 /\ rk (P24 :: P26 :: nil) = 2 /\ rk (P24 :: P27 :: nil) = 2 /\ rk (P24 :: P28 :: nil) = 2 /\ rk (P24 :: P29 :: nil) = 2 /\ rk (P24 :: P30 :: nil) = 2 /\ rk (P25 :: P26 :: nil) = 2 /\ rk (P25 :: P27 :: nil) = 2 /\ rk (P25 :: P28 :: nil) = 2 /\ rk (P25 :: P29 :: nil) = 2 /\ rk (P25 :: P30 :: nil) = 2 /\ rk (P26 :: P27 :: nil) = 2 /\ rk (P26 :: P28 :: nil) = 2 /\ rk (P26 :: P29 :: nil) = 2 /\ rk (P26 :: P30 :: nil) = 2 /\ rk (P27 :: P28 :: nil) = 2 /\ rk (P27 :: P29 :: nil) = 2 /\ rk (P27 :: P30 :: nil) = 2 /\ rk (P28 :: P29 :: nil) = 2 /\ rk (P28 :: P30 :: nil) = 2 /\ rk (P29 :: P30 :: nil) = 2 .
Parameter rk_lines : rk (P0 :: P1 :: P3 :: P8 :: P12 :: P18 :: nil) = 2 /\ rk (P0 :: P2 :: P7 :: P11 :: P17 :: P30 :: nil) = 2 /\ rk (P1 :: P6 :: P10 :: P16 :: P29 :: P30 :: nil) = 2 /\ rk (P0 :: P5 :: P9 :: P15 :: P28 :: P29 :: nil) = 2 /\ rk (P4 :: P8 :: P14 :: P27 :: P28 :: P30 :: nil) = 2 /\ rk (P3 :: P7 :: P13 :: P26 :: P27 :: P29 :: nil) = 2 /\ rk (P2 :: P6 :: P12 :: P25 :: P26 :: P28 :: nil) = 2 /\ rk (P1 :: P5 :: P11 :: P24 :: P25 :: P27 :: nil) = 2 /\ rk (P0 :: P4 :: P10 :: P23 :: P24 :: P26 :: nil) = 2 /\ rk (P3 :: P9 :: P22 :: P23 :: P25 :: P30 :: nil) = 2 /\ rk (P2 :: P8 :: P21 :: P22 :: P24 :: P29 :: nil) = 2 /\ rk (P1 :: P7 :: P20 :: P21 :: P23 :: P28 :: nil) = 2 /\ rk (P0 :: P6 :: P19 :: P20 :: P22 :: P27 :: nil) = 2 /\ rk (P5 :: P18 :: P19 :: P21 :: P26 :: P30 :: nil) = 2 /\ rk (P4 :: P17 :: P18 :: P20 :: P25 :: P29 :: nil) = 2 /\ rk (P3 :: P16 :: P17 :: P19 :: P24 :: P28 :: nil) = 2 /\ rk (P2 :: P15 :: P16 :: P18 :: P23 :: P27 :: nil) = 2 /\ rk (P1 :: P14 :: P15 :: P17 :: P22 :: P26 :: nil) = 2 /\ rk (P0 :: P13 :: P14 :: P16 :: P21 :: P25 :: nil) = 2 /\ rk (P12 :: P13 :: P15 :: P20 :: P24 :: P30 :: nil) = 2 /\ rk (P11 :: P12 :: P14 :: P19 :: P23 :: P29 :: nil) = 2 /\ rk (P10 :: P11 :: P13 :: P18 :: P22 :: P28 :: nil) = 2 /\ rk (P9 :: P10 :: P12 :: P17 :: P21 :: P27 :: nil) = 2 /\ rk (P8 :: P9 :: P11 :: P16 :: P20 :: P26 :: nil) = 2 /\ rk (P7 :: P8 :: P10 :: P15 :: P19 :: P25 :: nil) = 2 /\ rk (P6 :: P7 :: P9 :: P14 :: P18 :: P24 :: nil) = 2 /\ rk (P5 :: P6 :: P8 :: P13 :: P17 :: P23 :: nil) = 2 /\ rk (P4 :: P5 :: P7 :: P12 :: P16 :: P22 :: nil) = 2 /\ rk (P3 :: P4 :: P6 :: P11 :: P15 :: P21 :: nil) = 2 /\ rk (P2 :: P3 :: P5 :: P10 :: P14 :: P20 :: nil) = 2 /\ rk (P1 :: P2 :: P4 :: P9 :: P13 :: P19 :: nil) = 2.
Parameter rk_lines' : rk(P0 :: P1 :: P3 ::nil) = 2
/\ rk(P0 :: P1 :: P8 ::nil) = 2
/\ rk(P0 :: P1 :: P12 ::nil) = 2
/\ rk(P0 :: P1 :: P18 ::nil) = 2
/\ rk(P0 :: P3 :: P8 ::nil) = 2
/\ rk(P0 :: P3 :: P12 ::nil) = 2
/\ rk(P0 :: P3 :: P18 ::nil) = 2
/\ rk(P0 :: P8 :: P12 ::nil) = 2
/\ rk(P0 :: P8 :: P18 ::nil) = 2
/\ rk(P0 :: P12 :: P18 ::nil) = 2
/\ rk(P1 :: P3 :: P8 ::nil) = 2
/\ rk(P1 :: P3 :: P12 ::nil) = 2
/\ rk(P1 :: P3 :: P18 ::nil) = 2
/\ rk(P1 :: P8 :: P12 ::nil) = 2
/\ rk(P1 :: P8 :: P18 ::nil) = 2
/\ rk(P1 :: P12 :: P18 ::nil) = 2
/\ rk(P3 :: P8 :: P12 ::nil) = 2
/\ rk(P3 :: P8 :: P18 ::nil) = 2
/\ rk(P3 :: P12 :: P18 ::nil) = 2
/\ rk(P8 :: P12 :: P18 ::nil) = 2
/\ rk(P0 :: P2 :: P7 ::nil) = 2
/\ rk(P0 :: P2 :: P11 ::nil) = 2
/\ rk(P0 :: P2 :: P17 ::nil) = 2
/\ rk(P0 :: P2 :: P30 ::nil) = 2
/\ rk(P0 :: P7 :: P11 ::nil) = 2
/\ rk(P0 :: P7 :: P17 ::nil) = 2
/\ rk(P0 :: P7 :: P30 ::nil) = 2
/\ rk(P0 :: P11 :: P17 ::nil) = 2
/\ rk(P0 :: P11 :: P30 ::nil) = 2
/\ rk(P0 :: P17 :: P30 ::nil) = 2
/\ rk(P2 :: P7 :: P11 ::nil) = 2
/\ rk(P2 :: P7 :: P17 ::nil) = 2
/\ rk(P2 :: P7 :: P30 ::nil) = 2
/\ rk(P2 :: P11 :: P17 ::nil) = 2
/\ rk(P2 :: P11 :: P30 ::nil) = 2
/\ rk(P2 :: P17 :: P30 ::nil) = 2
/\ rk(P7 :: P11 :: P17 ::nil) = 2
/\ rk(P7 :: P11 :: P30 ::nil) = 2
/\ rk(P7 :: P17 :: P30 ::nil) = 2
/\ rk(P11 :: P17 :: P30 ::nil) = 2
/\ rk(P1 :: P6 :: P10 ::nil) = 2
/\ rk(P1 :: P6 :: P16 ::nil) = 2
/\ rk(P1 :: P6 :: P29 ::nil) = 2
/\ rk(P1 :: P6 :: P30 ::nil) = 2
/\ rk(P1 :: P10 :: P16 ::nil) = 2
/\ rk(P1 :: P10 :: P29 ::nil) = 2
/\ rk(P1 :: P10 :: P30 ::nil) = 2
/\ rk(P1 :: P16 :: P29 ::nil) = 2
/\ rk(P1 :: P16 :: P30 ::nil) = 2
/\ rk(P1 :: P29 :: P30 ::nil) = 2
/\ rk(P6 :: P10 :: P16 ::nil) = 2
/\ rk(P6 :: P10 :: P29 ::nil) = 2
/\ rk(P6 :: P10 :: P30 ::nil) = 2
/\ rk(P6 :: P16 :: P29 ::nil) = 2
/\ rk(P6 :: P16 :: P30 ::nil) = 2
/\ rk(P6 :: P29 :: P30 ::nil) = 2
/\ rk(P10 :: P16 :: P29 ::nil) = 2
/\ rk(P10 :: P16 :: P30 ::nil) = 2
/\ rk(P10 :: P29 :: P30 ::nil) = 2
/\ rk(P16 :: P29 :: P30 ::nil) = 2
/\ rk(P0 :: P5 :: P9 ::nil) = 2
/\ rk(P0 :: P5 :: P15 ::nil) = 2
/\ rk(P0 :: P5 :: P28 ::nil) = 2
/\ rk(P0 :: P5 :: P29 ::nil) = 2
/\ rk(P0 :: P9 :: P15 ::nil) = 2
/\ rk(P0 :: P9 :: P28 ::nil) = 2
/\ rk(P0 :: P9 :: P29 ::nil) = 2
/\ rk(P0 :: P15 :: P28 ::nil) = 2
/\ rk(P0 :: P15 :: P29 ::nil) = 2
/\ rk(P0 :: P28 :: P29 ::nil) = 2
/\ rk(P5 :: P9 :: P15 ::nil) = 2
/\ rk(P5 :: P9 :: P28 ::nil) = 2
/\ rk(P5 :: P9 :: P29 ::nil) = 2
/\ rk(P5 :: P15 :: P28 ::nil) = 2
/\ rk(P5 :: P15 :: P29 ::nil) = 2
/\ rk(P5 :: P28 :: P29 ::nil) = 2
/\ rk(P9 :: P15 :: P28 ::nil) = 2
/\ rk(P9 :: P15 :: P29 ::nil) = 2
/\ rk(P9 :: P28 :: P29 ::nil) = 2
/\ rk(P15 :: P28 :: P29 ::nil) = 2
/\ rk(P4 :: P8 :: P14 ::nil) = 2
/\ rk(P4 :: P8 :: P27 ::nil) = 2
/\ rk(P4 :: P8 :: P28 ::nil) = 2
/\ rk(P4 :: P8 :: P30 ::nil) = 2
/\ rk(P4 :: P14 :: P27 ::nil) = 2
/\ rk(P4 :: P14 :: P28 ::nil) = 2
/\ rk(P4 :: P14 :: P30 ::nil) = 2
/\ rk(P4 :: P27 :: P28 ::nil) = 2
/\ rk(P4 :: P27 :: P30 ::nil) = 2
/\ rk(P4 :: P28 :: P30 ::nil) = 2
/\ rk(P8 :: P14 :: P27 ::nil) = 2
/\ rk(P8 :: P14 :: P28 ::nil) = 2
/\ rk(P8 :: P14 :: P30 ::nil) = 2
/\ rk(P8 :: P27 :: P28 ::nil) = 2
/\ rk(P8 :: P27 :: P30 ::nil) = 2
/\ rk(P8 :: P28 :: P30 ::nil) = 2
/\ rk(P14 :: P27 :: P28 ::nil) = 2
/\ rk(P14 :: P27 :: P30 ::nil) = 2
/\ rk(P14 :: P28 :: P30 ::nil) = 2
/\ rk(P27 :: P28 :: P30 ::nil) = 2
/\ rk(P3 :: P7 :: P13 ::nil) = 2
/\ rk(P3 :: P7 :: P26 ::nil) = 2
/\ rk(P3 :: P7 :: P27 ::nil) = 2
/\ rk(P3 :: P7 :: P29 ::nil) = 2
/\ rk(P3 :: P13 :: P26 ::nil) = 2
/\ rk(P3 :: P13 :: P27 ::nil) = 2
/\ rk(P3 :: P13 :: P29 ::nil) = 2
/\ rk(P3 :: P26 :: P27 ::nil) = 2
/\ rk(P3 :: P26 :: P29 ::nil) = 2
/\ rk(P3 :: P27 :: P29 ::nil) = 2
/\ rk(P7 :: P13 :: P26 ::nil) = 2
/\ rk(P7 :: P13 :: P27 ::nil) = 2
/\ rk(P7 :: P13 :: P29 ::nil) = 2
/\ rk(P7 :: P26 :: P27 ::nil) = 2
/\ rk(P7 :: P26 :: P29 ::nil) = 2
/\ rk(P7 :: P27 :: P29 ::nil) = 2
/\ rk(P13 :: P26 :: P27 ::nil) = 2
/\ rk(P13 :: P26 :: P29 ::nil) = 2
/\ rk(P13 :: P27 :: P29 ::nil) = 2
/\ rk(P26 :: P27 :: P29 ::nil) = 2
/\ rk(P2 :: P6 :: P12 ::nil) = 2
/\ rk(P2 :: P6 :: P25 ::nil) = 2
/\ rk(P2 :: P6 :: P26 ::nil) = 2
/\ rk(P2 :: P6 :: P28 ::nil) = 2
/\ rk(P2 :: P12 :: P25 ::nil) = 2
/\ rk(P2 :: P12 :: P26 ::nil) = 2
/\ rk(P2 :: P12 :: P28 ::nil) = 2
/\ rk(P2 :: P25 :: P26 ::nil) = 2
/\ rk(P2 :: P25 :: P28 ::nil) = 2
/\ rk(P2 :: P26 :: P28 ::nil) = 2
/\ rk(P6 :: P12 :: P25 ::nil) = 2
/\ rk(P6 :: P12 :: P26 ::nil) = 2
/\ rk(P6 :: P12 :: P28 ::nil) = 2
/\ rk(P6 :: P25 :: P26 ::nil) = 2
/\ rk(P6 :: P25 :: P28 ::nil) = 2
/\ rk(P6 :: P26 :: P28 ::nil) = 2
/\ rk(P12 :: P25 :: P26 ::nil) = 2
/\ rk(P12 :: P25 :: P28 ::nil) = 2
/\ rk(P12 :: P26 :: P28 ::nil) = 2
/\ rk(P25 :: P26 :: P28 ::nil) = 2
/\ rk(P1 :: P5 :: P11 ::nil) = 2
/\ rk(P1 :: P5 :: P24 ::nil) = 2
/\ rk(P1 :: P5 :: P25 ::nil) = 2
/\ rk(P1 :: P5 :: P27 ::nil) = 2
/\ rk(P1 :: P11 :: P24 ::nil) = 2
/\ rk(P1 :: P11 :: P25 ::nil) = 2
/\ rk(P1 :: P11 :: P27 ::nil) = 2
/\ rk(P1 :: P24 :: P25 ::nil) = 2
/\ rk(P1 :: P24 :: P27 ::nil) = 2
/\ rk(P1 :: P25 :: P27 ::nil) = 2
/\ rk(P5 :: P11 :: P24 ::nil) = 2
/\ rk(P5 :: P11 :: P25 ::nil) = 2
/\ rk(P5 :: P11 :: P27 ::nil) = 2
/\ rk(P5 :: P24 :: P25 ::nil) = 2
/\ rk(P5 :: P24 :: P27 ::nil) = 2
/\ rk(P5 :: P25 :: P27 ::nil) = 2
/\ rk(P11 :: P24 :: P25 ::nil) = 2
/\ rk(P11 :: P24 :: P27 ::nil) = 2
/\ rk(P11 :: P25 :: P27 ::nil) = 2
/\ rk(P24 :: P25 :: P27 ::nil) = 2
/\ rk(P0 :: P4 :: P10 ::nil) = 2
/\ rk(P0 :: P4 :: P23 ::nil) = 2
/\ rk(P0 :: P4 :: P24 ::nil) = 2
/\ rk(P0 :: P4 :: P26 ::nil) = 2
/\ rk(P0 :: P10 :: P23 ::nil) = 2
/\ rk(P0 :: P10 :: P24 ::nil) = 2
/\ rk(P0 :: P10 :: P26 ::nil) = 2
/\ rk(P0 :: P23 :: P24 ::nil) = 2
/\ rk(P0 :: P23 :: P26 ::nil) = 2
/\ rk(P0 :: P24 :: P26 ::nil) = 2
/\ rk(P4 :: P10 :: P23 ::nil) = 2
/\ rk(P4 :: P10 :: P24 ::nil) = 2
/\ rk(P4 :: P10 :: P26 ::nil) = 2
/\ rk(P4 :: P23 :: P24 ::nil) = 2
/\ rk(P4 :: P23 :: P26 ::nil) = 2
/\ rk(P4 :: P24 :: P26 ::nil) = 2
/\ rk(P10 :: P23 :: P24 ::nil) = 2
/\ rk(P10 :: P23 :: P26 ::nil) = 2
/\ rk(P10 :: P24 :: P26 ::nil) = 2
/\ rk(P23 :: P24 :: P26 ::nil) = 2
/\ rk(P3 :: P9 :: P22 ::nil) = 2
/\ rk(P3 :: P9 :: P23 ::nil) = 2
/\ rk(P3 :: P9 :: P25 ::nil) = 2
/\ rk(P3 :: P9 :: P30 ::nil) = 2
/\ rk(P3 :: P22 :: P23 ::nil) = 2
/\ rk(P3 :: P22 :: P25 ::nil) = 2
/\ rk(P3 :: P22 :: P30 ::nil) = 2
/\ rk(P3 :: P23 :: P25 ::nil) = 2
/\ rk(P3 :: P23 :: P30 ::nil) = 2
/\ rk(P3 :: P25 :: P30 ::nil) = 2
/\ rk(P9 :: P22 :: P23 ::nil) = 2
/\ rk(P9 :: P22 :: P25 ::nil) = 2
/\ rk(P9 :: P22 :: P30 ::nil) = 2
/\ rk(P9 :: P23 :: P25 ::nil) = 2
/\ rk(P9 :: P23 :: P30 ::nil) = 2
/\ rk(P9 :: P25 :: P30 ::nil) = 2
/\ rk(P22 :: P23 :: P25 ::nil) = 2
/\ rk(P22 :: P23 :: P30 ::nil) = 2
/\ rk(P22 :: P25 :: P30 ::nil) = 2
/\ rk(P23 :: P25 :: P30 ::nil) = 2
/\ rk(P2 :: P8 :: P21 ::nil) = 2
/\ rk(P2 :: P8 :: P22 ::nil) = 2
/\ rk(P2 :: P8 :: P24 ::nil) = 2
/\ rk(P2 :: P8 :: P29 ::nil) = 2
/\ rk(P2 :: P21 :: P22 ::nil) = 2
/\ rk(P2 :: P21 :: P24 ::nil) = 2
/\ rk(P2 :: P21 :: P29 ::nil) = 2
/\ rk(P2 :: P22 :: P24 ::nil) = 2
/\ rk(P2 :: P22 :: P29 ::nil) = 2
/\ rk(P2 :: P24 :: P29 ::nil) = 2
/\ rk(P8 :: P21 :: P22 ::nil) = 2
/\ rk(P8 :: P21 :: P24 ::nil) = 2
/\ rk(P8 :: P21 :: P29 ::nil) = 2
/\ rk(P8 :: P22 :: P24 ::nil) = 2
/\ rk(P8 :: P22 :: P29 ::nil) = 2
/\ rk(P8 :: P24 :: P29 ::nil) = 2
/\ rk(P21 :: P22 :: P24 ::nil) = 2
/\ rk(P21 :: P22 :: P29 ::nil) = 2
/\ rk(P21 :: P24 :: P29 ::nil) = 2
/\ rk(P22 :: P24 :: P29 ::nil) = 2
/\ rk(P1 :: P7 :: P20 ::nil) = 2
/\ rk(P1 :: P7 :: P21 ::nil) = 2
/\ rk(P1 :: P7 :: P23 ::nil) = 2
/\ rk(P1 :: P7 :: P28 ::nil) = 2
/\ rk(P1 :: P20 :: P21 ::nil) = 2
/\ rk(P1 :: P20 :: P23 ::nil) = 2
/\ rk(P1 :: P20 :: P28 ::nil) = 2
/\ rk(P1 :: P21 :: P23 ::nil) = 2
/\ rk(P1 :: P21 :: P28 ::nil) = 2
/\ rk(P1 :: P23 :: P28 ::nil) = 2
/\ rk(P7 :: P20 :: P21 ::nil) = 2
/\ rk(P7 :: P20 :: P23 ::nil) = 2
/\ rk(P7 :: P20 :: P28 ::nil) = 2
/\ rk(P7 :: P21 :: P23 ::nil) = 2
/\ rk(P7 :: P21 :: P28 ::nil) = 2
/\ rk(P7 :: P23 :: P28 ::nil) = 2
/\ rk(P20 :: P21 :: P23 ::nil) = 2
/\ rk(P20 :: P21 :: P28 ::nil) = 2
/\ rk(P20 :: P23 :: P28 ::nil) = 2
/\ rk(P21 :: P23 :: P28 ::nil) = 2
/\ rk(P0 :: P6 :: P19 ::nil) = 2
/\ rk(P0 :: P6 :: P20 ::nil) = 2
/\ rk(P0 :: P6 :: P22 ::nil) = 2
/\ rk(P0 :: P6 :: P27 ::nil) = 2
/\ rk(P0 :: P19 :: P20 ::nil) = 2
/\ rk(P0 :: P19 :: P22 ::nil) = 2
/\ rk(P0 :: P19 :: P27 ::nil) = 2
/\ rk(P0 :: P20 :: P22 ::nil) = 2
/\ rk(P0 :: P20 :: P27 ::nil) = 2
/\ rk(P0 :: P22 :: P27 ::nil) = 2
/\ rk(P6 :: P19 :: P20 ::nil) = 2
/\ rk(P6 :: P19 :: P22 ::nil) = 2
/\ rk(P6 :: P19 :: P27 ::nil) = 2
/\ rk(P6 :: P20 :: P22 ::nil) = 2
/\ rk(P6 :: P20 :: P27 ::nil) = 2
/\ rk(P6 :: P22 :: P27 ::nil) = 2
/\ rk(P19 :: P20 :: P22 ::nil) = 2
/\ rk(P19 :: P20 :: P27 ::nil) = 2
/\ rk(P19 :: P22 :: P27 ::nil) = 2
/\ rk(P20 :: P22 :: P27 ::nil) = 2
/\ rk(P5 :: P18 :: P19 ::nil) = 2
/\ rk(P5 :: P18 :: P21 ::nil) = 2
/\ rk(P5 :: P18 :: P26 ::nil) = 2
/\ rk(P5 :: P18 :: P30 ::nil) = 2
/\ rk(P5 :: P19 :: P21 ::nil) = 2
/\ rk(P5 :: P19 :: P26 ::nil) = 2
/\ rk(P5 :: P19 :: P30 ::nil) = 2
/\ rk(P5 :: P21 :: P26 ::nil) = 2
/\ rk(P5 :: P21 :: P30 ::nil) = 2
/\ rk(P5 :: P26 :: P30 ::nil) = 2
/\ rk(P18 :: P19 :: P21 ::nil) = 2
/\ rk(P18 :: P19 :: P26 ::nil) = 2
/\ rk(P18 :: P19 :: P30 ::nil) = 2
/\ rk(P18 :: P21 :: P26 ::nil) = 2
/\ rk(P18 :: P21 :: P30 ::nil) = 2
/\ rk(P18 :: P26 :: P30 ::nil) = 2
/\ rk(P19 :: P21 :: P26 ::nil) = 2
/\ rk(P19 :: P21 :: P30 ::nil) = 2
/\ rk(P19 :: P26 :: P30 ::nil) = 2
/\ rk(P21 :: P26 :: P30 ::nil) = 2
/\ rk(P4 :: P17 :: P18 ::nil) = 2
/\ rk(P4 :: P17 :: P20 ::nil) = 2
/\ rk(P4 :: P17 :: P25 ::nil) = 2
/\ rk(P4 :: P17 :: P29 ::nil) = 2
/\ rk(P4 :: P18 :: P20 ::nil) = 2
/\ rk(P4 :: P18 :: P25 ::nil) = 2
/\ rk(P4 :: P18 :: P29 ::nil) = 2
/\ rk(P4 :: P20 :: P25 ::nil) = 2
/\ rk(P4 :: P20 :: P29 ::nil) = 2
/\ rk(P4 :: P25 :: P29 ::nil) = 2
/\ rk(P17 :: P18 :: P20 ::nil) = 2
/\ rk(P17 :: P18 :: P25 ::nil) = 2
/\ rk(P17 :: P18 :: P29 ::nil) = 2
/\ rk(P17 :: P20 :: P25 ::nil) = 2
/\ rk(P17 :: P20 :: P29 ::nil) = 2
/\ rk(P17 :: P25 :: P29 ::nil) = 2
/\ rk(P18 :: P20 :: P25 ::nil) = 2
/\ rk(P18 :: P20 :: P29 ::nil) = 2
/\ rk(P18 :: P25 :: P29 ::nil) = 2
/\ rk(P20 :: P25 :: P29 ::nil) = 2
/\ rk(P3 :: P16 :: P17 ::nil) = 2
/\ rk(P3 :: P16 :: P19 ::nil) = 2
/\ rk(P3 :: P16 :: P24 ::nil) = 2
/\ rk(P3 :: P16 :: P28 ::nil) = 2
/\ rk(P3 :: P17 :: P19 ::nil) = 2
/\ rk(P3 :: P17 :: P24 ::nil) = 2
/\ rk(P3 :: P17 :: P28 ::nil) = 2
/\ rk(P3 :: P19 :: P24 ::nil) = 2
/\ rk(P3 :: P19 :: P28 ::nil) = 2
/\ rk(P3 :: P24 :: P28 ::nil) = 2
/\ rk(P16 :: P17 :: P19 ::nil) = 2
/\ rk(P16 :: P17 :: P24 ::nil) = 2
/\ rk(P16 :: P17 :: P28 ::nil) = 2
/\ rk(P16 :: P19 :: P24 ::nil) = 2
/\ rk(P16 :: P19 :: P28 ::nil) = 2
/\ rk(P16 :: P24 :: P28 ::nil) = 2
/\ rk(P17 :: P19 :: P24 ::nil) = 2
/\ rk(P17 :: P19 :: P28 ::nil) = 2
/\ rk(P17 :: P24 :: P28 ::nil) = 2
/\ rk(P19 :: P24 :: P28 ::nil) = 2
/\ rk(P2 :: P15 :: P16 ::nil) = 2
/\ rk(P2 :: P15 :: P18 ::nil) = 2
/\ rk(P2 :: P15 :: P23 ::nil) = 2
/\ rk(P2 :: P15 :: P27 ::nil) = 2
/\ rk(P2 :: P16 :: P18 ::nil) = 2
/\ rk(P2 :: P16 :: P23 ::nil) = 2
/\ rk(P2 :: P16 :: P27 ::nil) = 2
/\ rk(P2 :: P18 :: P23 ::nil) = 2
/\ rk(P2 :: P18 :: P27 ::nil) = 2
/\ rk(P2 :: P23 :: P27 ::nil) = 2
/\ rk(P15 :: P16 :: P18 ::nil) = 2
/\ rk(P15 :: P16 :: P23 ::nil) = 2
/\ rk(P15 :: P16 :: P27 ::nil) = 2
/\ rk(P15 :: P18 :: P23 ::nil) = 2
/\ rk(P15 :: P18 :: P27 ::nil) = 2
/\ rk(P15 :: P23 :: P27 ::nil) = 2
/\ rk(P16 :: P18 :: P23 ::nil) = 2
/\ rk(P16 :: P18 :: P27 ::nil) = 2
/\ rk(P16 :: P23 :: P27 ::nil) = 2
/\ rk(P18 :: P23 :: P27 ::nil) = 2
/\ rk(P1 :: P14 :: P15 ::nil) = 2
/\ rk(P1 :: P14 :: P17 ::nil) = 2
/\ rk(P1 :: P14 :: P22 ::nil) = 2
/\ rk(P1 :: P14 :: P26 ::nil) = 2
/\ rk(P1 :: P15 :: P17 ::nil) = 2
/\ rk(P1 :: P15 :: P22 ::nil) = 2
/\ rk(P1 :: P15 :: P26 ::nil) = 2
/\ rk(P1 :: P17 :: P22 ::nil) = 2
/\ rk(P1 :: P17 :: P26 ::nil) = 2
/\ rk(P1 :: P22 :: P26 ::nil) = 2
/\ rk(P14 :: P15 :: P17 ::nil) = 2
/\ rk(P14 :: P15 :: P22 ::nil) = 2
/\ rk(P14 :: P15 :: P26 ::nil) = 2
/\ rk(P14 :: P17 :: P22 ::nil) = 2
/\ rk(P14 :: P17 :: P26 ::nil) = 2
/\ rk(P14 :: P22 :: P26 ::nil) = 2
/\ rk(P15 :: P17 :: P22 ::nil) = 2
/\ rk(P15 :: P17 :: P26 ::nil) = 2
/\ rk(P15 :: P22 :: P26 ::nil) = 2
/\ rk(P17 :: P22 :: P26 ::nil) = 2
/\ rk(P0 :: P13 :: P14 ::nil) = 2
/\ rk(P0 :: P13 :: P16 ::nil) = 2
/\ rk(P0 :: P13 :: P21 ::nil) = 2
/\ rk(P0 :: P13 :: P25 ::nil) = 2
/\ rk(P0 :: P14 :: P16 ::nil) = 2
/\ rk(P0 :: P14 :: P21 ::nil) = 2
/\ rk(P0 :: P14 :: P25 ::nil) = 2
/\ rk(P0 :: P16 :: P21 ::nil) = 2
/\ rk(P0 :: P16 :: P25 ::nil) = 2
/\ rk(P0 :: P21 :: P25 ::nil) = 2
/\ rk(P13 :: P14 :: P16 ::nil) = 2
/\ rk(P13 :: P14 :: P21 ::nil) = 2
/\ rk(P13 :: P14 :: P25 ::nil) = 2
/\ rk(P13 :: P16 :: P21 ::nil) = 2
/\ rk(P13 :: P16 :: P25 ::nil) = 2
/\ rk(P13 :: P21 :: P25 ::nil) = 2
/\ rk(P14 :: P16 :: P21 ::nil) = 2
/\ rk(P14 :: P16 :: P25 ::nil) = 2
/\ rk(P14 :: P21 :: P25 ::nil) = 2
/\ rk(P16 :: P21 :: P25 ::nil) = 2
/\ rk(P12 :: P13 :: P15 ::nil) = 2
/\ rk(P12 :: P13 :: P20 ::nil) = 2
/\ rk(P12 :: P13 :: P24 ::nil) = 2
/\ rk(P12 :: P13 :: P30 ::nil) = 2
/\ rk(P12 :: P15 :: P20 ::nil) = 2
/\ rk(P12 :: P15 :: P24 ::nil) = 2
/\ rk(P12 :: P15 :: P30 ::nil) = 2
/\ rk(P12 :: P20 :: P24 ::nil) = 2
/\ rk(P12 :: P20 :: P30 ::nil) = 2
/\ rk(P12 :: P24 :: P30 ::nil) = 2
/\ rk(P13 :: P15 :: P20 ::nil) = 2
/\ rk(P13 :: P15 :: P24 ::nil) = 2
/\ rk(P13 :: P15 :: P30 ::nil) = 2
/\ rk(P13 :: P20 :: P24 ::nil) = 2
/\ rk(P13 :: P20 :: P30 ::nil) = 2
/\ rk(P13 :: P24 :: P30 ::nil) = 2
/\ rk(P15 :: P20 :: P24 ::nil) = 2
/\ rk(P15 :: P20 :: P30 ::nil) = 2
/\ rk(P15 :: P24 :: P30 ::nil) = 2
/\ rk(P20 :: P24 :: P30 ::nil) = 2
/\ rk(P11 :: P12 :: P14 ::nil) = 2
/\ rk(P11 :: P12 :: P19 ::nil) = 2
/\ rk(P11 :: P12 :: P23 ::nil) = 2
/\ rk(P11 :: P12 :: P29 ::nil) = 2
/\ rk(P11 :: P14 :: P19 ::nil) = 2
/\ rk(P11 :: P14 :: P23 ::nil) = 2
/\ rk(P11 :: P14 :: P29 ::nil) = 2
/\ rk(P11 :: P19 :: P23 ::nil) = 2
/\ rk(P11 :: P19 :: P29 ::nil) = 2
/\ rk(P11 :: P23 :: P29 ::nil) = 2
/\ rk(P12 :: P14 :: P19 ::nil) = 2
/\ rk(P12 :: P14 :: P23 ::nil) = 2
/\ rk(P12 :: P14 :: P29 ::nil) = 2
/\ rk(P12 :: P19 :: P23 ::nil) = 2
/\ rk(P12 :: P19 :: P29 ::nil) = 2
/\ rk(P12 :: P23 :: P29 ::nil) = 2
/\ rk(P14 :: P19 :: P23 ::nil) = 2
/\ rk(P14 :: P19 :: P29 ::nil) = 2
/\ rk(P14 :: P23 :: P29 ::nil) = 2
/\ rk(P19 :: P23 :: P29 ::nil) = 2
/\ rk(P10 :: P11 :: P13 ::nil) = 2
/\ rk(P10 :: P11 :: P18 ::nil) = 2
/\ rk(P10 :: P11 :: P22 ::nil) = 2
/\ rk(P10 :: P11 :: P28 ::nil) = 2
/\ rk(P10 :: P13 :: P18 ::nil) = 2
/\ rk(P10 :: P13 :: P22 ::nil) = 2
/\ rk(P10 :: P13 :: P28 ::nil) = 2
/\ rk(P10 :: P18 :: P22 ::nil) = 2
/\ rk(P10 :: P18 :: P28 ::nil) = 2
/\ rk(P10 :: P22 :: P28 ::nil) = 2
/\ rk(P11 :: P13 :: P18 ::nil) = 2
/\ rk(P11 :: P13 :: P22 ::nil) = 2
/\ rk(P11 :: P13 :: P28 ::nil) = 2
/\ rk(P11 :: P18 :: P22 ::nil) = 2
/\ rk(P11 :: P18 :: P28 ::nil) = 2
/\ rk(P11 :: P22 :: P28 ::nil) = 2
/\ rk(P13 :: P18 :: P22 ::nil) = 2
/\ rk(P13 :: P18 :: P28 ::nil) = 2
/\ rk(P13 :: P22 :: P28 ::nil) = 2
/\ rk(P18 :: P22 :: P28 ::nil) = 2
/\ rk(P9 :: P10 :: P12 ::nil) = 2
/\ rk(P9 :: P10 :: P17 ::nil) = 2
/\ rk(P9 :: P10 :: P21 ::nil) = 2
/\ rk(P9 :: P10 :: P27 ::nil) = 2
/\ rk(P9 :: P12 :: P17 ::nil) = 2
/\ rk(P9 :: P12 :: P21 ::nil) = 2
/\ rk(P9 :: P12 :: P27 ::nil) = 2
/\ rk(P9 :: P17 :: P21 ::nil) = 2
/\ rk(P9 :: P17 :: P27 ::nil) = 2
/\ rk(P9 :: P21 :: P27 ::nil) = 2
/\ rk(P10 :: P12 :: P17 ::nil) = 2
/\ rk(P10 :: P12 :: P21 ::nil) = 2
/\ rk(P10 :: P12 :: P27 ::nil) = 2
/\ rk(P10 :: P17 :: P21 ::nil) = 2
/\ rk(P10 :: P17 :: P27 ::nil) = 2
/\ rk(P10 :: P21 :: P27 ::nil) = 2
/\ rk(P12 :: P17 :: P21 ::nil) = 2
/\ rk(P12 :: P17 :: P27 ::nil) = 2
/\ rk(P12 :: P21 :: P27 ::nil) = 2
/\ rk(P17 :: P21 :: P27 ::nil) = 2
/\ rk(P8 :: P9 :: P11 ::nil) = 2
/\ rk(P8 :: P9 :: P16 ::nil) = 2
/\ rk(P8 :: P9 :: P20 ::nil) = 2
/\ rk(P8 :: P9 :: P26 ::nil) = 2
/\ rk(P8 :: P11 :: P16 ::nil) = 2
/\ rk(P8 :: P11 :: P20 ::nil) = 2
/\ rk(P8 :: P11 :: P26 ::nil) = 2
/\ rk(P8 :: P16 :: P20 ::nil) = 2
/\ rk(P8 :: P16 :: P26 ::nil) = 2
/\ rk(P8 :: P20 :: P26 ::nil) = 2
/\ rk(P9 :: P11 :: P16 ::nil) = 2
/\ rk(P9 :: P11 :: P20 ::nil) = 2
/\ rk(P9 :: P11 :: P26 ::nil) = 2
/\ rk(P9 :: P16 :: P20 ::nil) = 2
/\ rk(P9 :: P16 :: P26 ::nil) = 2
/\ rk(P9 :: P20 :: P26 ::nil) = 2
/\ rk(P11 :: P16 :: P20 ::nil) = 2
/\ rk(P11 :: P16 :: P26 ::nil) = 2
/\ rk(P11 :: P20 :: P26 ::nil) = 2
/\ rk(P16 :: P20 :: P26 ::nil) = 2
/\ rk(P7 :: P8 :: P10 ::nil) = 2
/\ rk(P7 :: P8 :: P15 ::nil) = 2
/\ rk(P7 :: P8 :: P19 ::nil) = 2
/\ rk(P7 :: P8 :: P25 ::nil) = 2
/\ rk(P7 :: P10 :: P15 ::nil) = 2
/\ rk(P7 :: P10 :: P19 ::nil) = 2
/\ rk(P7 :: P10 :: P25 ::nil) = 2
/\ rk(P7 :: P15 :: P19 ::nil) = 2
/\ rk(P7 :: P15 :: P25 ::nil) = 2
/\ rk(P7 :: P19 :: P25 ::nil) = 2
/\ rk(P8 :: P10 :: P15 ::nil) = 2
/\ rk(P8 :: P10 :: P19 ::nil) = 2
/\ rk(P8 :: P10 :: P25 ::nil) = 2
/\ rk(P8 :: P15 :: P19 ::nil) = 2
/\ rk(P8 :: P15 :: P25 ::nil) = 2
/\ rk(P8 :: P19 :: P25 ::nil) = 2
/\ rk(P10 :: P15 :: P19 ::nil) = 2
/\ rk(P10 :: P15 :: P25 ::nil) = 2
/\ rk(P10 :: P19 :: P25 ::nil) = 2
/\ rk(P15 :: P19 :: P25 ::nil) = 2
/\ rk(P6 :: P7 :: P9 ::nil) = 2
/\ rk(P6 :: P7 :: P14 ::nil) = 2
/\ rk(P6 :: P7 :: P18 ::nil) = 2
/\ rk(P6 :: P7 :: P24 ::nil) = 2
/\ rk(P6 :: P9 :: P14 ::nil) = 2
/\ rk(P6 :: P9 :: P18 ::nil) = 2
/\ rk(P6 :: P9 :: P24 ::nil) = 2
/\ rk(P6 :: P14 :: P18 ::nil) = 2
/\ rk(P6 :: P14 :: P24 ::nil) = 2
/\ rk(P6 :: P18 :: P24 ::nil) = 2
/\ rk(P7 :: P9 :: P14 ::nil) = 2
/\ rk(P7 :: P9 :: P18 ::nil) = 2
/\ rk(P7 :: P9 :: P24 ::nil) = 2
/\ rk(P7 :: P14 :: P18 ::nil) = 2
/\ rk(P7 :: P14 :: P24 ::nil) = 2
/\ rk(P7 :: P18 :: P24 ::nil) = 2
/\ rk(P9 :: P14 :: P18 ::nil) = 2
/\ rk(P9 :: P14 :: P24 ::nil) = 2
/\ rk(P9 :: P18 :: P24 ::nil) = 2
/\ rk(P14 :: P18 :: P24 ::nil) = 2
/\ rk(P5 :: P6 :: P8 ::nil) = 2
/\ rk(P5 :: P6 :: P13 ::nil) = 2
/\ rk(P5 :: P6 :: P17 ::nil) = 2
/\ rk(P5 :: P6 :: P23 ::nil) = 2
/\ rk(P5 :: P8 :: P13 ::nil) = 2
/\ rk(P5 :: P8 :: P17 ::nil) = 2
/\ rk(P5 :: P8 :: P23 ::nil) = 2
/\ rk(P5 :: P13 :: P17 ::nil) = 2
/\ rk(P5 :: P13 :: P23 ::nil) = 2
/\ rk(P5 :: P17 :: P23 ::nil) = 2
/\ rk(P6 :: P8 :: P13 ::nil) = 2
/\ rk(P6 :: P8 :: P17 ::nil) = 2
/\ rk(P6 :: P8 :: P23 ::nil) = 2
/\ rk(P6 :: P13 :: P17 ::nil) = 2
/\ rk(P6 :: P13 :: P23 ::nil) = 2
/\ rk(P6 :: P17 :: P23 ::nil) = 2
/\ rk(P8 :: P13 :: P17 ::nil) = 2
/\ rk(P8 :: P13 :: P23 ::nil) = 2
/\ rk(P8 :: P17 :: P23 ::nil) = 2
/\ rk(P13 :: P17 :: P23 ::nil) = 2
/\ rk(P4 :: P5 :: P7 ::nil) = 2
/\ rk(P4 :: P5 :: P12 ::nil) = 2
/\ rk(P4 :: P5 :: P16 ::nil) = 2
/\ rk(P4 :: P5 :: P22 ::nil) = 2
/\ rk(P4 :: P7 :: P12 ::nil) = 2
/\ rk(P4 :: P7 :: P16 ::nil) = 2
/\ rk(P4 :: P7 :: P22 ::nil) = 2
/\ rk(P4 :: P12 :: P16 ::nil) = 2
/\ rk(P4 :: P12 :: P22 ::nil) = 2
/\ rk(P4 :: P16 :: P22 ::nil) = 2
/\ rk(P5 :: P7 :: P12 ::nil) = 2
/\ rk(P5 :: P7 :: P16 ::nil) = 2
/\ rk(P5 :: P7 :: P22 ::nil) = 2
/\ rk(P5 :: P12 :: P16 ::nil) = 2
/\ rk(P5 :: P12 :: P22 ::nil) = 2
/\ rk(P5 :: P16 :: P22 ::nil) = 2
/\ rk(P7 :: P12 :: P16 ::nil) = 2
/\ rk(P7 :: P12 :: P22 ::nil) = 2
/\ rk(P7 :: P16 :: P22 ::nil) = 2
/\ rk(P12 :: P16 :: P22 ::nil) = 2
/\ rk(P3 :: P4 :: P6 ::nil) = 2
/\ rk(P3 :: P4 :: P11 ::nil) = 2
/\ rk(P3 :: P4 :: P15 ::nil) = 2
/\ rk(P3 :: P4 :: P21 ::nil) = 2
/\ rk(P3 :: P6 :: P11 ::nil) = 2
/\ rk(P3 :: P6 :: P15 ::nil) = 2
/\ rk(P3 :: P6 :: P21 ::nil) = 2
/\ rk(P3 :: P11 :: P15 ::nil) = 2
/\ rk(P3 :: P11 :: P21 ::nil) = 2
/\ rk(P3 :: P15 :: P21 ::nil) = 2
/\ rk(P4 :: P6 :: P11 ::nil) = 2
/\ rk(P4 :: P6 :: P15 ::nil) = 2
/\ rk(P4 :: P6 :: P21 ::nil) = 2
/\ rk(P4 :: P11 :: P15 ::nil) = 2
/\ rk(P4 :: P11 :: P21 ::nil) = 2
/\ rk(P4 :: P15 :: P21 ::nil) = 2
/\ rk(P6 :: P11 :: P15 ::nil) = 2
/\ rk(P6 :: P11 :: P21 ::nil) = 2
/\ rk(P6 :: P15 :: P21 ::nil) = 2
/\ rk(P11 :: P15 :: P21 ::nil) = 2
/\ rk(P2 :: P3 :: P5 ::nil) = 2
/\ rk(P2 :: P3 :: P10 ::nil) = 2
/\ rk(P2 :: P3 :: P14 ::nil) = 2
/\ rk(P2 :: P3 :: P20 ::nil) = 2
/\ rk(P2 :: P5 :: P10 ::nil) = 2
/\ rk(P2 :: P5 :: P14 ::nil) = 2
/\ rk(P2 :: P5 :: P20 ::nil) = 2
/\ rk(P2 :: P10 :: P14 ::nil) = 2
/\ rk(P2 :: P10 :: P20 ::nil) = 2
/\ rk(P2 :: P14 :: P20 ::nil) = 2
/\ rk(P3 :: P5 :: P10 ::nil) = 2
/\ rk(P3 :: P5 :: P14 ::nil) = 2
/\ rk(P3 :: P5 :: P20 ::nil) = 2
/\ rk(P3 :: P10 :: P14 ::nil) = 2
/\ rk(P3 :: P10 :: P20 ::nil) = 2
/\ rk(P3 :: P14 :: P20 ::nil) = 2
/\ rk(P5 :: P10 :: P14 ::nil) = 2
/\ rk(P5 :: P10 :: P20 ::nil) = 2
/\ rk(P5 :: P14 :: P20 ::nil) = 2
/\ rk(P10 :: P14 :: P20 ::nil) = 2
/\ rk(P1 :: P2 :: P4 ::nil) = 2
/\ rk(P1 :: P2 :: P9 ::nil) = 2
/\ rk(P1 :: P2 :: P13 ::nil) = 2
/\ rk(P1 :: P2 :: P19 ::nil) = 2
/\ rk(P1 :: P4 :: P9 ::nil) = 2
/\ rk(P1 :: P4 :: P13 ::nil) = 2
/\ rk(P1 :: P4 :: P19 ::nil) = 2
/\ rk(P1 :: P9 :: P13 ::nil) = 2
/\ rk(P1 :: P9 :: P19 ::nil) = 2
/\ rk(P1 :: P13 :: P19 ::nil) = 2
/\ rk(P2 :: P4 :: P9 ::nil) = 2
/\ rk(P2 :: P4 :: P13 ::nil) = 2
/\ rk(P2 :: P4 :: P19 ::nil) = 2
/\ rk(P2 :: P9 :: P13 ::nil) = 2
/\ rk(P2 :: P9 :: P19 ::nil) = 2
/\ rk(P2 :: P13 :: P19 ::nil) = 2
/\ rk(P4 :: P9 :: P13 ::nil) = 2
/\ rk(P4 :: P9 :: P19 ::nil) = 2
/\ rk(P4 :: P13 :: P19 ::nil) = 2
/\ rk(P9 :: P13 :: P19 ::nil) = 2
.
Parameter rk_planes :
rk ( P0 :: P2 :: P7 ::nil )= 3 /\ rk ( P0 :: P2 :: P11 ::nil )= 3 /\ rk ( P0 :: P2 :: P17 ::nil )= 3 /\ rk ( P0 :: P2 :: P30 ::nil )= 3 /\ rk ( P0 :: P4 :: P10 ::nil )= 3 /\ rk ( P0 :: P4 :: P23 ::nil )= 3 /\ rk ( P0 :: P4 :: P24 ::nil )= 3 /\ rk ( P0 :: P4 :: P26 ::nil )= 3 /\ rk ( P0 :: P5 :: P9 ::nil )= 3 /\ rk ( P0 :: P5 :: P15 ::nil )= 3 /\ rk ( P0 :: P5 :: P28 ::nil )= 3 /\ rk ( P0 :: P5 :: P29 ::nil )= 3 /\ rk ( P0 :: P6 :: P19 ::nil )= 3 /\ rk ( P0 :: P6 :: P20 ::nil )= 3 /\ rk ( P0 :: P6 :: P22 ::nil )= 3 /\ rk ( P0 :: P6 :: P27 ::nil )= 3 /\ rk ( P0 :: P7 :: P11 ::nil )= 3 /\ rk ( P0 :: P7 :: P17 ::nil )= 3 /\ rk ( P0 :: P7 :: P30 ::nil )= 3 /\ rk ( P0 :: P9 :: P15 ::nil )= 3 /\ rk ( P0 :: P9 :: P28 ::nil )= 3 /\ rk ( P0 :: P9 :: P29 ::nil )= 3 /\ rk ( P0 :: P10 :: P23 ::nil )= 3 /\ rk ( P0 :: P10 :: P24 ::nil )= 3 /\ rk ( P0 :: P10 :: P26 ::nil )= 3 /\ rk ( P0 :: P11 :: P17 ::nil )= 3 /\ rk ( P0 :: P11 :: P30 ::nil )= 3 /\ rk ( P0 :: P13 :: P14 ::nil )= 3 /\ rk ( P0 :: P13 :: P16 ::nil )= 3 /\ rk ( P0 :: P13 :: P21 ::nil )= 3 /\ rk ( P0 :: P13 :: P25 ::nil )= 3 /\ rk ( P0 :: P14 :: P16 ::nil )= 3 /\ rk ( P0 :: P14 :: P21 ::nil )= 3 /\ rk ( P0 :: P14 :: P25 ::nil )= 3 /\ rk ( P0 :: P15 :: P28 ::nil )= 3 /\ rk ( P0 :: P15 :: P29 ::nil )= 3 /\ rk ( P0 :: P16 :: P21 ::nil )= 3 /\ rk ( P0 :: P16 :: P25 ::nil )= 3 /\ rk ( P0 :: P17 :: P30 ::nil )= 3 /\ rk ( P0 :: P19 :: P20 ::nil )= 3 /\ rk ( P0 :: P19 :: P22 ::nil )= 3 /\ rk ( P0 :: P19 :: P27 ::nil )= 3 /\ rk ( P0 :: P20 :: P22 ::nil )= 3 /\ rk ( P0 :: P20 :: P27 ::nil )= 3 /\ rk ( P0 :: P21 :: P25 ::nil )= 3 /\ rk ( P0 :: P22 :: P27 ::nil )= 3 /\ rk ( P0 :: P23 :: P24 ::nil )= 3 /\ rk ( P0 :: P23 :: P26 ::nil )= 3 /\ rk ( P0 :: P24 :: P26 ::nil )= 3 /\ rk ( P0 :: P28 :: P29 ::nil )= 3 /\ rk ( P1 :: P2 :: P4 ::nil )= 3 /\ rk ( P1 :: P2 :: P9 ::nil )= 3 /\ rk ( P1 :: P2 :: P13 ::nil )= 3 /\ rk ( P1 :: P2 :: P19 ::nil )= 3 /\ rk ( P1 :: P4 :: P9 ::nil )= 3 /\ rk ( P1 :: P4 :: P13 ::nil )= 3 /\ rk ( P1 :: P4 :: P19 ::nil )= 3 /\ rk ( P1 :: P5 :: P11 ::nil )= 3 /\ rk ( P1 :: P5 :: P24 ::nil )= 3 /\ rk ( P1 :: P5 :: P25 ::nil )= 3 /\ rk ( P1 :: P5 :: P27 ::nil )= 3 /\ rk ( P1 :: P6 :: P10 ::nil )= 3 /\ rk ( P1 :: P6 :: P16 ::nil )= 3 /\ rk ( P1 :: P6 :: P29 ::nil )= 3 /\ rk ( P1 :: P6 :: P30 ::nil )= 3 /\ rk ( P1 :: P7 :: P20 ::nil )= 3 /\ rk ( P1 :: P7 :: P21 ::nil )= 3 /\ rk ( P1 :: P7 :: P23 ::nil )= 3 /\ rk ( P1 :: P7 :: P28 ::nil )= 3 /\ rk ( P1 :: P9 :: P13 ::nil )= 3 /\ rk ( P1 :: P9 :: P19 ::nil )= 3 /\ rk ( P1 :: P10 :: P16 ::nil )= 3 /\ rk ( P1 :: P10 :: P29 ::nil )= 3 /\ rk ( P1 :: P10 :: P30 ::nil )= 3 /\ rk ( P1 :: P11 :: P24 ::nil )= 3 /\ rk ( P1 :: P11 :: P25 ::nil )= 3 /\ rk ( P1 :: P11 :: P27 ::nil )= 3 /\ rk ( P1 :: P13 :: P19 ::nil )= 3 /\ rk ( P1 :: P14 :: P15 ::nil )= 3 /\ rk ( P1 :: P14 :: P17 ::nil )= 3 /\ rk ( P1 :: P14 :: P22 ::nil )= 3 /\ rk ( P1 :: P14 :: P26 ::nil )= 3 /\ rk ( P1 :: P15 :: P17 ::nil )= 3 /\ rk ( P1 :: P15 :: P22 ::nil )= 3 /\ rk ( P1 :: P15 :: P26 ::nil )= 3 /\ rk ( P1 :: P16 :: P29 ::nil )= 3 /\ rk ( P1 :: P16 :: P30 ::nil )= 3 /\ rk ( P1 :: P17 :: P22 ::nil )= 3 /\ rk ( P1 :: P17 :: P26 ::nil )= 3 /\ rk ( P1 :: P20 :: P21 ::nil )= 3 /\ rk ( P1 :: P20 :: P23 ::nil )= 3 /\ rk ( P1 :: P20 :: P28 ::nil )= 3 /\ rk ( P1 :: P21 :: P23 ::nil )= 3 /\ rk ( P1 :: P21 :: P28 ::nil )= 3 /\ rk ( P1 :: P22 :: P26 ::nil )= 3 /\ rk ( P1 :: P23 :: P28 ::nil )= 3 /\ rk ( P1 :: P24 :: P25 ::nil )= 3 /\ rk ( P1 :: P24 :: P27 ::nil )= 3 /\ rk ( P1 :: P25 :: P27 ::nil )= 3 /\ rk ( P1 :: P29 :: P30 ::nil )= 3 /\ rk ( P2 :: P3 :: P5 ::nil )= 3 /\ rk ( P2 :: P3 :: P10 ::nil )= 3 /\ rk ( P2 :: P3 :: P14 ::nil )= 3 /\ rk ( P2 :: P3 :: P20 ::nil )= 3 /\ rk ( P2 :: P4 :: P9 ::nil )= 3 /\ rk ( P2 :: P4 :: P13 ::nil )= 3 /\ rk ( P2 :: P4 :: P19 ::nil )= 3 /\ rk ( P2 :: P5 :: P10 ::nil )= 3 /\ rk ( P2 :: P5 :: P14 ::nil )= 3 /\ rk ( P2 :: P5 :: P20 ::nil )= 3 /\ rk ( P2 :: P6 :: P12 ::nil )= 3 /\ rk ( P2 :: P6 :: P25 ::nil )= 3 /\ rk ( P2 :: P6 :: P26 ::nil )= 3 /\ rk ( P2 :: P6 :: P28 ::nil )= 3 /\ rk ( P2 :: P7 :: P11 ::nil )= 3 /\ rk ( P2 :: P7 :: P17 ::nil )= 3 /\ rk ( P2 :: P7 :: P30 ::nil )= 3 /\ rk ( P2 :: P8 :: P21 ::nil )= 3 /\ rk ( P2 :: P8 :: P22 ::nil )= 3 /\ rk ( P2 :: P8 :: P24 ::nil )= 3 /\ rk ( P2 :: P8 :: P29 ::nil )= 3 /\ rk ( P2 :: P9 :: P13 ::nil )= 3 /\ rk ( P2 :: P9 :: P19 ::nil )= 3 /\ rk ( P2 :: P10 :: P14 ::nil )= 3 /\ rk ( P2 :: P10 :: P20 ::nil )= 3 /\ rk ( P2 :: P11 :: P17 ::nil )= 3 /\ rk ( P2 :: P11 :: P30 ::nil )= 3 /\ rk ( P2 :: P12 :: P25 ::nil )= 3 /\ rk ( P2 :: P12 :: P26 ::nil )= 3 /\ rk ( P2 :: P12 :: P28 ::nil )= 3 /\ rk ( P2 :: P13 :: P19 ::nil )= 3 /\ rk ( P2 :: P14 :: P20 ::nil )= 3 /\ rk ( P2 :: P15 :: P16 ::nil )= 3 /\ rk ( P2 :: P15 :: P18 ::nil )= 3 /\ rk ( P2 :: P15 :: P23 ::nil )= 3 /\ rk ( P2 :: P15 :: P27 ::nil )= 3 /\ rk ( P2 :: P16 :: P18 ::nil )= 3 /\ rk ( P2 :: P16 :: P23 ::nil )= 3 /\ rk ( P2 :: P16 :: P27 ::nil )= 3 /\ rk ( P2 :: P17 :: P30 ::nil )= 3 /\ rk ( P2 :: P18 :: P23 ::nil )= 3 /\ rk ( P2 :: P18 :: P27 ::nil )= 3 /\ rk ( P2 :: P21 :: P22 ::nil )= 3 /\ rk ( P2 :: P21 :: P24 ::nil )= 3 /\ rk ( P2 :: P21 :: P29 ::nil )= 3 /\ rk ( P2 :: P22 :: P24 ::nil )= 3 /\ rk ( P2 :: P22 :: P29 ::nil )= 3 /\ rk ( P2 :: P23 :: P27 ::nil )= 3 /\ rk ( P2 :: P24 :: P29 ::nil )= 3 /\ rk ( P2 :: P25 :: P26 ::nil )= 3 /\ rk ( P2 :: P25 :: P28 ::nil )= 3 /\ rk ( P2 :: P26 :: P28 ::nil )= 3 /\ rk ( P3 :: P4 :: P6 ::nil )= 3 /\ rk ( P3 :: P4 :: P11 ::nil )= 3 /\ rk ( P3 :: P4 :: P15 ::nil )= 3 /\ rk ( P3 :: P4 :: P21 ::nil )= 3 /\ rk ( P3 :: P5 :: P10 ::nil )= 3 /\ rk ( P3 :: P5 :: P14 ::nil )= 3 /\ rk ( P3 :: P5 :: P20 ::nil )= 3 /\ rk ( P3 :: P6 :: P11 ::nil )= 3 /\ rk ( P3 :: P6 :: P15 ::nil )= 3 /\ rk ( P3 :: P6 :: P21 ::nil )= 3 /\ rk ( P3 :: P7 :: P13 ::nil )= 3 /\ rk ( P3 :: P7 :: P26 ::nil )= 3 /\ rk ( P3 :: P7 :: P27 ::nil )= 3 /\ rk ( P3 :: P7 :: P29 ::nil )= 3 /\ rk ( P3 :: P9 :: P22 ::nil )= 3 /\ rk ( P3 :: P9 :: P23 ::nil )= 3 /\ rk ( P3 :: P9 :: P25 ::nil )= 3 /\ rk ( P3 :: P9 :: P30 ::nil )= 3 /\ rk ( P3 :: P10 :: P14 ::nil )= 3 /\ rk ( P3 :: P10 :: P20 ::nil )= 3 /\ rk ( P3 :: P11 :: P15 ::nil )= 3 /\ rk ( P3 :: P11 :: P21 ::nil )= 3 /\ rk ( P3 :: P13 :: P26 ::nil )= 3 /\ rk ( P3 :: P13 :: P27 ::nil )= 3 /\ rk ( P3 :: P13 :: P29 ::nil )= 3 /\ rk ( P3 :: P14 :: P20 ::nil )= 3 /\ rk ( P3 :: P15 :: P21 ::nil )= 3 /\ rk ( P3 :: P16 :: P17 ::nil )= 3 /\ rk ( P3 :: P16 :: P19 ::nil )= 3 /\ rk ( P3 :: P16 :: P24 ::nil )= 3 /\ rk ( P3 :: P16 :: P28 ::nil )= 3 /\ rk ( P3 :: P17 :: P19 ::nil )= 3 /\ rk ( P3 :: P17 :: P24 ::nil )= 3 /\ rk ( P3 :: P17 :: P28 ::nil )= 3 /\ rk ( P3 :: P19 :: P24 ::nil )= 3 /\ rk ( P3 :: P19 :: P28 ::nil )= 3 /\ rk ( P3 :: P22 :: P23 ::nil )= 3 /\ rk ( P3 :: P22 :: P25 ::nil )= 3 /\ rk ( P3 :: P22 :: P30 ::nil )= 3 /\ rk ( P3 :: P23 :: P25 ::nil )= 3 /\ rk ( P3 :: P23 :: P30 ::nil )= 3 /\ rk ( P3 :: P24 :: P28 ::nil )= 3 /\ rk ( P3 :: P25 :: P30 ::nil )= 3 /\ rk ( P3 :: P26 :: P27 ::nil )= 3 /\ rk ( P3 :: P26 :: P29 ::nil )= 3 /\ rk ( P3 :: P27 :: P29 ::nil )= 3 /\ rk ( P4 :: P5 :: P7 ::nil )= 3 /\ rk ( P4 :: P5 :: P12 ::nil )= 3 /\ rk ( P4 :: P5 :: P16 ::nil )= 3 /\ rk ( P4 :: P5 :: P22 ::nil )= 3 /\ rk ( P4 :: P6 :: P11 ::nil )= 3 /\ rk ( P4 :: P6 :: P15 ::nil )= 3 /\ rk ( P4 :: P6 :: P21 ::nil )= 3 /\ rk ( P4 :: P7 :: P12 ::nil )= 3 /\ rk ( P4 :: P7 :: P16 ::nil )= 3 /\ rk ( P4 :: P7 :: P22 ::nil )= 3 /\ rk ( P4 :: P8 :: P14 ::nil )= 3 /\ rk ( P4 :: P8 :: P27 ::nil )= 3 /\ rk ( P4 :: P8 :: P28 ::nil )= 3 /\ rk ( P4 :: P8 :: P30 ::nil )= 3 /\ rk ( P4 :: P9 :: P13 ::nil )= 3 /\ rk ( P4 :: P9 :: P19 ::nil )= 3 /\ rk ( P4 :: P10 :: P23 ::nil )= 3 /\ rk ( P4 :: P10 :: P24 ::nil )= 3 /\ rk ( P4 :: P10 :: P26 ::nil )= 3 /\ rk ( P4 :: P11 :: P15 ::nil )= 3 /\ rk ( P4 :: P11 :: P21 ::nil )= 3 /\ rk ( P4 :: P12 :: P16 ::nil )= 3 /\ rk ( P4 :: P12 :: P22 ::nil )= 3 /\ rk ( P4 :: P13 :: P19 ::nil )= 3 /\ rk ( P4 :: P14 :: P27 ::nil )= 3 /\ rk ( P4 :: P14 :: P28 ::nil )= 3 /\ rk ( P4 :: P14 :: P30 ::nil )= 3 /\ rk ( P4 :: P15 :: P21 ::nil )= 3 /\ rk ( P4 :: P16 :: P22 ::nil )= 3 /\ rk ( P4 :: P17 :: P18 ::nil )= 3 /\ rk ( P4 :: P17 :: P20 ::nil )= 3 /\ rk ( P4 :: P17 :: P25 ::nil )= 3 /\ rk ( P4 :: P17 :: P29 ::nil )= 3 /\ rk ( P4 :: P18 :: P20 ::nil )= 3 /\ rk ( P4 :: P18 :: P25 ::nil )= 3 /\ rk ( P4 :: P18 :: P29 ::nil )= 3 /\ rk ( P4 :: P20 :: P25 ::nil )= 3 /\ rk ( P4 :: P20 :: P29 ::nil )= 3 /\ rk ( P4 :: P23 :: P24 ::nil )= 3 /\ rk ( P4 :: P23 :: P26 ::nil )= 3 /\ rk ( P4 :: P24 :: P26 ::nil )= 3 /\ rk ( P4 :: P25 :: P29 ::nil )= 3 /\ rk ( P4 :: P27 :: P28 ::nil )= 3 /\ rk ( P4 :: P27 :: P30 ::nil )= 3 /\ rk ( P4 :: P28 :: P30 ::nil )= 3 /\ rk ( P5 :: P6 :: P8 ::nil )= 3 /\ rk ( P5 :: P6 :: P13 ::nil )= 3 /\ rk ( P5 :: P6 :: P17 ::nil )= 3 /\ rk ( P5 :: P6 :: P23 ::nil )= 3 /\ rk ( P5 :: P7 :: P12 ::nil )= 3 /\ rk ( P5 :: P7 :: P16 ::nil )= 3 /\ rk ( P5 :: P7 :: P22 ::nil )= 3 /\ rk ( P5 :: P8 :: P13 ::nil )= 3 /\ rk ( P5 :: P8 :: P17 ::nil )= 3 /\ rk ( P5 :: P8 :: P23 ::nil )= 3 /\ rk ( P5 :: P9 :: P15 ::nil )= 3 /\ rk ( P5 :: P9 :: P28 ::nil )= 3 /\ rk ( P5 :: P9 :: P29 ::nil )= 3 /\ rk ( P5 :: P10 :: P14 ::nil )= 3 /\ rk ( P5 :: P10 :: P20 ::nil )= 3 /\ rk ( P5 :: P11 :: P24 ::nil )= 3 /\ rk ( P5 :: P11 :: P25 ::nil )= 3 /\ rk ( P5 :: P11 :: P27 ::nil )= 3 /\ rk ( P5 :: P12 :: P16 ::nil )= 3 /\ rk ( P5 :: P12 :: P22 ::nil )= 3 /\ rk ( P5 :: P13 :: P17 ::nil )= 3 /\ rk ( P5 :: P13 :: P23 ::nil )= 3 /\ rk ( P5 :: P14 :: P20 ::nil )= 3 /\ rk ( P5 :: P15 :: P28 ::nil )= 3 /\ rk ( P5 :: P15 :: P29 ::nil )= 3 /\ rk ( P5 :: P16 :: P22 ::nil )= 3 /\ rk ( P5 :: P17 :: P23 ::nil )= 3 /\ rk ( P5 :: P18 :: P19 ::nil )= 3 /\ rk ( P5 :: P18 :: P21 ::nil )= 3 /\ rk ( P5 :: P18 :: P26 ::nil )= 3 /\ rk ( P5 :: P18 :: P30 ::nil )= 3 /\ rk ( P5 :: P19 :: P21 ::nil )= 3 /\ rk ( P5 :: P19 :: P26 ::nil )= 3 /\ rk ( P5 :: P19 :: P30 ::nil )= 3 /\ rk ( P5 :: P21 :: P26 ::nil )= 3 /\ rk ( P5 :: P21 :: P30 ::nil )= 3 /\ rk ( P5 :: P24 :: P25 ::nil )= 3 /\ rk ( P5 :: P24 :: P27 ::nil )= 3 /\ rk ( P5 :: P25 :: P27 ::nil )= 3 /\ rk ( P5 :: P26 :: P30 ::nil )= 3 /\ rk ( P5 :: P28 :: P29 ::nil )= 3 /\ rk ( P6 :: P7 :: P9 ::nil )= 3 /\ rk ( P6 :: P7 :: P14 ::nil )= 3 /\ rk ( P6 :: P7 :: P18 ::nil )= 3 /\ rk ( P6 :: P7 :: P24 ::nil )= 3 /\ rk ( P6 :: P8 :: P13 ::nil )= 3 /\ rk ( P6 :: P8 :: P17 ::nil )= 3 /\ rk ( P6 :: P8 :: P23 ::nil )= 3 /\ rk ( P6 :: P9 :: P14 ::nil )= 3 /\ rk ( P6 :: P9 :: P18 ::nil )= 3 /\ rk ( P6 :: P9 :: P24 ::nil )= 3 /\ rk ( P6 :: P10 :: P16 ::nil )= 3 /\ rk ( P6 :: P10 :: P29 ::nil )= 3 /\ rk ( P6 :: P10 :: P30 ::nil )= 3 /\ rk ( P6 :: P11 :: P15 ::nil )= 3 /\ rk ( P6 :: P11 :: P21 ::nil )= 3 /\ rk ( P6 :: P12 :: P25 ::nil )= 3 /\ rk ( P6 :: P12 :: P26 ::nil )= 3 /\ rk ( P6 :: P12 :: P28 ::nil )= 3 /\ rk ( P6 :: P13 :: P17 ::nil )= 3 /\ rk ( P6 :: P13 :: P23 ::nil )= 3 /\ rk ( P6 :: P14 :: P18 ::nil )= 3 /\ rk ( P6 :: P14 :: P24 ::nil )= 3 /\ rk ( P6 :: P15 :: P21 ::nil )= 3 /\ rk ( P6 :: P16 :: P29 ::nil )= 3 /\ rk ( P6 :: P16 :: P30 ::nil )= 3 /\ rk ( P6 :: P17 :: P23 ::nil )= 3 /\ rk ( P6 :: P18 :: P24 ::nil )= 3 /\ rk ( P6 :: P19 :: P20 ::nil )= 3 /\ rk ( P6 :: P19 :: P22 ::nil )= 3 /\ rk ( P6 :: P19 :: P27 ::nil )= 3 /\ rk ( P6 :: P20 :: P22 ::nil )= 3 /\ rk ( P6 :: P20 :: P27 ::nil )= 3 /\ rk ( P6 :: P22 :: P27 ::nil )= 3 /\ rk ( P6 :: P25 :: P26 ::nil )= 3 /\ rk ( P6 :: P25 :: P28 ::nil )= 3 /\ rk ( P6 :: P26 :: P28 ::nil )= 3 /\ rk ( P6 :: P29 :: P30 ::nil )= 3 /\ rk ( P7 :: P8 :: P10 ::nil )= 3 /\ rk ( P7 :: P8 :: P15 ::nil )= 3 /\ rk ( P7 :: P8 :: P19 ::nil )= 3 /\ rk ( P7 :: P8 :: P25 ::nil )= 3 /\ rk ( P7 :: P9 :: P14 ::nil )= 3 /\ rk ( P7 :: P9 :: P18 ::nil )= 3 /\ rk ( P7 :: P9 :: P24 ::nil )= 3 /\ rk ( P7 :: P10 :: P15 ::nil )= 3 /\ rk ( P7 :: P10 :: P19 ::nil )= 3 /\ rk ( P7 :: P10 :: P25 ::nil )= 3 /\ rk ( P7 :: P11 :: P17 ::nil )= 3 /\ rk ( P7 :: P11 :: P30 ::nil )= 3 /\ rk ( P7 :: P12 :: P16 ::nil )= 3 /\ rk ( P7 :: P12 :: P22 ::nil )= 3 /\ rk ( P7 :: P13 :: P26 ::nil )= 3 /\ rk ( P7 :: P13 :: P27 ::nil )= 3 /\ rk ( P7 :: P13 :: P29 ::nil )= 3 /\ rk ( P7 :: P14 :: P18 ::nil )= 3 /\ rk ( P7 :: P14 :: P24 ::nil )= 3 /\ rk ( P7 :: P15 :: P19 ::nil )= 3 /\ rk ( P7 :: P15 :: P25 ::nil )= 3 /\ rk ( P7 :: P16 :: P22 ::nil )= 3 /\ rk ( P7 :: P17 :: P30 ::nil )= 3 /\ rk ( P7 :: P18 :: P24 ::nil )= 3 /\ rk ( P7 :: P19 :: P25 ::nil )= 3 /\ rk ( P7 :: P20 :: P21 ::nil )= 3 /\ rk ( P7 :: P20 :: P23 ::nil )= 3 /\ rk ( P7 :: P20 :: P28 ::nil )= 3 /\ rk ( P7 :: P21 :: P23 ::nil )= 3 /\ rk ( P7 :: P21 :: P28 ::nil )= 3 /\ rk ( P7 :: P23 :: P28 ::nil )= 3 /\ rk ( P7 :: P26 :: P27 ::nil )= 3 /\ rk ( P7 :: P26 :: P29 ::nil )= 3 /\ rk ( P7 :: P27 :: P29 ::nil )= 3 /\ rk ( P8 :: P9 :: P11 ::nil )= 3 /\ rk ( P8 :: P9 :: P16 ::nil )= 3 /\ rk ( P8 :: P9 :: P20 ::nil )= 3 /\ rk ( P8 :: P9 :: P26 ::nil )= 3 /\ rk ( P8 :: P10 :: P15 ::nil )= 3 /\ rk ( P8 :: P10 :: P19 ::nil )= 3 /\ rk ( P8 :: P10 :: P25 ::nil )= 3 /\ rk ( P8 :: P11 :: P16 ::nil )= 3 /\ rk ( P8 :: P11 :: P20 ::nil )= 3 /\ rk ( P8 :: P11 :: P26 ::nil )= 3 /\ rk ( P8 :: P13 :: P17 ::nil )= 3 /\ rk ( P8 :: P13 :: P23 ::nil )= 3 /\ rk ( P8 :: P14 :: P27 ::nil )= 3 /\ rk ( P8 :: P14 :: P28 ::nil )= 3 /\ rk ( P8 :: P14 :: P30 ::nil )= 3 /\ rk ( P8 :: P15 :: P19 ::nil )= 3 /\ rk ( P8 :: P15 :: P25 ::nil )= 3 /\ rk ( P8 :: P16 :: P20 ::nil )= 3 /\ rk ( P8 :: P16 :: P26 ::nil )= 3 /\ rk ( P8 :: P17 :: P23 ::nil )= 3 /\ rk ( P8 :: P19 :: P25 ::nil )= 3 /\ rk ( P8 :: P20 :: P26 ::nil )= 3 /\ rk ( P8 :: P21 :: P22 ::nil )= 3 /\ rk ( P8 :: P21 :: P24 ::nil )= 3 /\ rk ( P8 :: P21 :: P29 ::nil )= 3 /\ rk ( P8 :: P22 :: P24 ::nil )= 3 /\ rk ( P8 :: P22 :: P29 ::nil )= 3 /\ rk ( P8 :: P24 :: P29 ::nil )= 3 /\ rk ( P8 :: P27 :: P28 ::nil )= 3 /\ rk ( P8 :: P27 :: P30 ::nil )= 3 /\ rk ( P8 :: P28 :: P30 ::nil )= 3 /\ rk ( P9 :: P10 :: P12 ::nil )= 3 /\ rk ( P9 :: P10 :: P17 ::nil )= 3 /\ rk ( P9 :: P10 :: P21 ::nil )= 3 /\ rk ( P9 :: P10 :: P27 ::nil )= 3 /\ rk ( P9 :: P11 :: P16 ::nil )= 3 /\ rk ( P9 :: P11 :: P20 ::nil )= 3 /\ rk ( P9 :: P11 :: P26 ::nil )= 3 /\ rk ( P9 :: P12 :: P17 ::nil )= 3 /\ rk ( P9 :: P12 :: P21 ::nil )= 3 /\ rk ( P9 :: P12 :: P27 ::nil )= 3 /\ rk ( P9 :: P13 :: P19 ::nil )= 3 /\ rk ( P9 :: P14 :: P18 ::nil )= 3 /\ rk ( P9 :: P14 :: P24 ::nil )= 3 /\ rk ( P9 :: P15 :: P28 ::nil )= 3 /\ rk ( P9 :: P15 :: P29 ::nil )= 3 /\ rk ( P9 :: P16 :: P20 ::nil )= 3 /\ rk ( P9 :: P16 :: P26 ::nil )= 3 /\ rk ( P9 :: P17 :: P21 ::nil )= 3 /\ rk ( P9 :: P17 :: P27 ::nil )= 3 /\ rk ( P9 :: P18 :: P24 ::nil )= 3 /\ rk ( P9 :: P20 :: P26 ::nil )= 3 /\ rk ( P9 :: P21 :: P27 ::nil )= 3 /\ rk ( P9 :: P22 :: P23 ::nil )= 3 /\ rk ( P9 :: P22 :: P25 ::nil )= 3 /\ rk ( P9 :: P22 :: P30 ::nil )= 3 /\ rk ( P9 :: P23 :: P25 ::nil )= 3 /\ rk ( P9 :: P23 :: P30 ::nil )= 3 /\ rk ( P9 :: P25 :: P30 ::nil )= 3 /\ rk ( P9 :: P28 :: P29 ::nil )= 3 /\ rk ( P10 :: P11 :: P13 ::nil )= 3 /\ rk ( P10 :: P11 :: P18 ::nil )= 3 /\ rk ( P10 :: P11 :: P22 ::nil )= 3 /\ rk ( P10 :: P11 :: P28 ::nil )= 3 /\ rk ( P10 :: P12 :: P17 ::nil )= 3 /\ rk ( P10 :: P12 :: P21 ::nil )= 3 /\ rk ( P10 :: P12 :: P27 ::nil )= 3 /\ rk ( P10 :: P13 :: P18 ::nil )= 3 /\ rk ( P10 :: P13 :: P22 ::nil )= 3 /\ rk ( P10 :: P13 :: P28 ::nil )= 3 /\ rk ( P10 :: P14 :: P20 ::nil )= 3 /\ rk ( P10 :: P15 :: P19 ::nil )= 3 /\ rk ( P10 :: P15 :: P25 ::nil )= 3 /\ rk ( P10 :: P16 :: P29 ::nil )= 3 /\ rk ( P10 :: P16 :: P30 ::nil )= 3 /\ rk ( P10 :: P17 :: P21 ::nil )= 3 /\ rk ( P10 :: P17 :: P27 ::nil )= 3 /\ rk ( P10 :: P18 :: P22 ::nil )= 3 /\ rk ( P10 :: P18 :: P28 ::nil )= 3 /\ rk ( P10 :: P19 :: P25 ::nil )= 3 /\ rk ( P10 :: P21 :: P27 ::nil )= 3 /\ rk ( P10 :: P22 :: P28 ::nil )= 3 /\ rk ( P10 :: P23 :: P24 ::nil )= 3 /\ rk ( P10 :: P23 :: P26 ::nil )= 3 /\ rk ( P10 :: P24 :: P26 ::nil )= 3 /\ rk ( P10 :: P29 :: P30 ::nil )= 3 /\ rk ( P11 :: P12 :: P14 ::nil )= 3 /\ rk ( P11 :: P12 :: P19 ::nil )= 3 /\ rk ( P11 :: P12 :: P23 ::nil )= 3 /\ rk ( P11 :: P12 :: P29 ::nil )= 3 /\ rk ( P11 :: P13 :: P18 ::nil )= 3 /\ rk ( P11 :: P13 :: P22 ::nil )= 3 /\ rk ( P11 :: P13 :: P28 ::nil )= 3 /\ rk ( P11 :: P14 :: P19 ::nil )= 3 /\ rk ( P11 :: P14 :: P23 ::nil )= 3 /\ rk ( P11 :: P14 :: P29 ::nil )= 3 /\ rk ( P11 :: P15 :: P21 ::nil )= 3 /\ rk ( P11 :: P16 :: P20 ::nil )= 3 /\ rk ( P11 :: P16 :: P26 ::nil )= 3 /\ rk ( P11 :: P17 :: P30 ::nil )= 3 /\ rk ( P11 :: P18 :: P22 ::nil )= 3 /\ rk ( P11 :: P18 :: P28 ::nil )= 3 /\ rk ( P11 :: P19 :: P23 ::nil )= 3 /\ rk ( P11 :: P19 :: P29 ::nil )= 3 /\ rk ( P11 :: P20 :: P26 ::nil )= 3 /\ rk ( P11 :: P22 :: P28 ::nil )= 3 /\ rk ( P11 :: P23 :: P29 ::nil )= 3 /\ rk ( P11 :: P24 :: P25 ::nil )= 3 /\ rk ( P11 :: P24 :: P27 ::nil )= 3 /\ rk ( P11 :: P25 :: P27 ::nil )= 3 /\ rk ( P12 :: P13 :: P15 ::nil )= 3 /\ rk ( P12 :: P13 :: P20 ::nil )= 3 /\ rk ( P12 :: P13 :: P24 ::nil )= 3 /\ rk ( P12 :: P13 :: P30 ::nil )= 3 /\ rk ( P12 :: P14 :: P19 ::nil )= 3 /\ rk ( P12 :: P14 :: P23 ::nil )= 3 /\ rk ( P12 :: P14 :: P29 ::nil )= 3 /\ rk ( P12 :: P15 :: P20 ::nil )= 3 /\ rk ( P12 :: P15 :: P24 ::nil )= 3 /\ rk ( P12 :: P15 :: P30 ::nil )= 3 /\ rk ( P12 :: P16 :: P22 ::nil )= 3 /\ rk ( P12 :: P17 :: P21 ::nil )= 3 /\ rk ( P12 :: P17 :: P27 ::nil )= 3 /\ rk ( P12 :: P19 :: P23 ::nil )= 3 /\ rk ( P12 :: P19 :: P29 ::nil )= 3 /\ rk ( P12 :: P20 :: P24 ::nil )= 3 /\ rk ( P12 :: P20 :: P30 ::nil )= 3 /\ rk ( P12 :: P21 :: P27 ::nil )= 3 /\ rk ( P12 :: P23 :: P29 ::nil )= 3 /\ rk ( P12 :: P24 :: P30 ::nil )= 3 /\ rk ( P12 :: P25 :: P26 ::nil )= 3 /\ rk ( P12 :: P25 :: P28 ::nil )= 3 /\ rk ( P12 :: P26 :: P28 ::nil )= 3 /\ rk ( P13 :: P14 :: P16 ::nil )= 3 /\ rk ( P13 :: P14 :: P21 ::nil )= 3 /\ rk ( P13 :: P14 :: P25 ::nil )= 3 /\ rk ( P13 :: P15 :: P20 ::nil )= 3 /\ rk ( P13 :: P15 :: P24 ::nil )= 3 /\ rk ( P13 :: P15 :: P30 ::nil )= 3 /\ rk ( P13 :: P16 :: P21 ::nil )= 3 /\ rk ( P13 :: P16 :: P25 ::nil )= 3 /\ rk ( P13 :: P17 :: P23 ::nil )= 3 /\ rk ( P13 :: P18 :: P22 ::nil )= 3 /\ rk ( P13 :: P18 :: P28 ::nil )= 3 /\ rk ( P13 :: P20 :: P24 ::nil )= 3 /\ rk ( P13 :: P20 :: P30 ::nil )= 3 /\ rk ( P13 :: P21 :: P25 ::nil )= 3 /\ rk ( P13 :: P22 :: P28 ::nil )= 3 /\ rk ( P13 :: P24 :: P30 ::nil )= 3 /\ rk ( P13 :: P26 :: P27 ::nil )= 3 /\ rk ( P13 :: P26 :: P29 ::nil )= 3 /\ rk ( P13 :: P27 :: P29 ::nil )= 3 /\ rk ( P14 :: P15 :: P17 ::nil )= 3 /\ rk ( P14 :: P15 :: P22 ::nil )= 3 /\ rk ( P14 :: P15 :: P26 ::nil )= 3 /\ rk ( P14 :: P16 :: P21 ::nil )= 3 /\ rk ( P14 :: P16 :: P25 ::nil )= 3 /\ rk ( P14 :: P17 :: P22 ::nil )= 3 /\ rk ( P14 :: P17 :: P26 ::nil )= 3 /\ rk ( P14 :: P18 :: P24 ::nil )= 3 /\ rk ( P14 :: P19 :: P23 ::nil )= 3 /\ rk ( P14 :: P19 :: P29 ::nil )= 3 /\ rk ( P14 :: P21 :: P25 ::nil )= 3 /\ rk ( P14 :: P22 :: P26 ::nil )= 3 /\ rk ( P14 :: P23 :: P29 ::nil )= 3 /\ rk ( P14 :: P27 :: P28 ::nil )= 3 /\ rk ( P14 :: P27 :: P30 ::nil )= 3 /\ rk ( P14 :: P28 :: P30 ::nil )= 3 /\ rk ( P15 :: P16 :: P18 ::nil )= 3 /\ rk ( P15 :: P16 :: P23 ::nil )= 3 /\ rk ( P15 :: P16 :: P27 ::nil )= 3 /\ rk ( P15 :: P17 :: P22 ::nil )= 3 /\ rk ( P15 :: P17 :: P26 ::nil )= 3 /\ rk ( P15 :: P18 :: P23 ::nil )= 3 /\ rk ( P15 :: P18 :: P27 ::nil )= 3 /\ rk ( P15 :: P19 :: P25 ::nil )= 3 /\ rk ( P15 :: P20 :: P24 ::nil )= 3 /\ rk ( P15 :: P20 :: P30 ::nil )= 3 /\ rk ( P15 :: P22 :: P26 ::nil )= 3 /\ rk ( P15 :: P23 :: P27 ::nil )= 3 /\ rk ( P15 :: P24 :: P30 ::nil )= 3 /\ rk ( P15 :: P28 :: P29 ::nil )= 3 /\ rk ( P16 :: P17 :: P19 ::nil )= 3 /\ rk ( P16 :: P17 :: P24 ::nil )= 3 /\ rk ( P16 :: P17 :: P28 ::nil )= 3 /\ rk ( P16 :: P18 :: P23 ::nil )= 3 /\ rk ( P16 :: P18 :: P27 ::nil )= 3 /\ rk ( P16 :: P19 :: P24 ::nil )= 3 /\ rk ( P16 :: P19 :: P28 ::nil )= 3 /\ rk ( P16 :: P20 :: P26 ::nil )= 3 /\ rk ( P16 :: P21 :: P25 ::nil )= 3 /\ rk ( P16 :: P23 :: P27 ::nil )= 3 /\ rk ( P16 :: P24 :: P28 ::nil )= 3 /\ rk ( P16 :: P29 :: P30 ::nil )= 3 /\ rk ( P17 :: P18 :: P20 ::nil )= 3 /\ rk ( P17 :: P18 :: P25 ::nil )= 3 /\ rk ( P17 :: P18 :: P29 ::nil )= 3 /\ rk ( P17 :: P19 :: P24 ::nil )= 3 /\ rk ( P17 :: P19 :: P28 ::nil )= 3 /\ rk ( P17 :: P20 :: P25 ::nil )= 3 /\ rk ( P17 :: P20 :: P29 ::nil )= 3 /\ rk ( P17 :: P21 :: P27 ::nil )= 3 /\ rk ( P17 :: P22 :: P26 ::nil )= 3 /\ rk ( P17 :: P24 :: P28 ::nil )= 3 /\ rk ( P17 :: P25 :: P29 ::nil )= 3 /\ rk ( P18 :: P19 :: P21 ::nil )= 3 /\ rk ( P18 :: P19 :: P26 ::nil )= 3 /\ rk ( P18 :: P19 :: P30 ::nil )= 3 /\ rk ( P18 :: P20 :: P25 ::nil )= 3 /\ rk ( P18 :: P20 :: P29 ::nil )= 3 /\ rk ( P18 :: P21 :: P26 ::nil )= 3 /\ rk ( P18 :: P21 :: P30 ::nil )= 3 /\ rk ( P18 :: P22 :: P28 ::nil )= 3 /\ rk ( P18 :: P23 :: P27 ::nil )= 3 /\ rk ( P18 :: P25 :: P29 ::nil )= 3 /\ rk ( P18 :: P26 :: P30 ::nil )= 3 /\ rk ( P19 :: P20 :: P22 ::nil )= 3 /\ rk ( P19 :: P20 :: P27 ::nil )= 3 /\ rk ( P19 :: P21 :: P26 ::nil )= 3 /\ rk ( P19 :: P21 :: P30 ::nil )= 3 /\ rk ( P19 :: P22 :: P27 ::nil )= 3 /\ rk ( P19 :: P23 :: P29 ::nil )= 3 /\ rk ( P19 :: P24 :: P28 ::nil )= 3 /\ rk ( P19 :: P26 :: P30 ::nil )= 3 /\ rk ( P20 :: P21 :: P23 ::nil )= 3 /\ rk ( P20 :: P21 :: P28 ::nil )= 3 /\ rk ( P20 :: P22 :: P27 ::nil )= 3 /\ rk ( P20 :: P23 :: P28 ::nil )= 3 /\ rk ( P20 :: P24 :: P30 ::nil )= 3 /\ rk ( P20 :: P25 :: P29 ::nil )= 3 /\ rk ( P21 :: P22 :: P24 ::nil )= 3 /\ rk ( P21 :: P22 :: P29 ::nil )= 3 /\ rk ( P21 :: P23 :: P28 ::nil )= 3 /\ rk ( P21 :: P24 :: P29 ::nil )= 3 /\ rk ( P21 :: P26 :: P30 ::nil )= 3 /\ rk ( P22 :: P23 :: P25 ::nil )= 3 /\ rk ( P22 :: P23 :: P30 ::nil )= 3 /\ rk ( P22 :: P24 :: P29 ::nil )= 3 /\ rk ( P22 :: P25 :: P30 ::nil )= 3 /\ rk ( P23 :: P24 :: P26 ::nil )= 3 /\ rk ( P23 :: P25 :: P30 ::nil )= 3 /\ rk ( P24 :: P25 :: P27 ::nil )= 3 /\ rk ( P25 :: P26 :: P28 ::nil )= 3 /\ rk ( P26 :: P27 :: P29 ::nil )= 3 /\ rk ( P27 :: P28 :: P30 ::nil )= 3.
Parameter is_only_31_pts : forall P,
{P=P0}+{P=P1}+{P=P2}+{P=P3}+{P=P4}+{P=P5}+{P=P6}+{P=P7}+{P=P8}+{P=P9}+{P=P10}+{P=P11}+{P=P12}+{P=P13}+{P=P14}+{P=P15}+{P=P16}+{P=P17}+{P=P18}+{P=P19}+{P=P20}+{P=P21}+{P=P22}+{P=P23}+{P=P24}+{P=P25}+{P=P26}+{P=P27}+{P=P28}+{P=P29}+{P=P30}.
Ltac case_clear_2 P :=
let HP0:=fresh in let HP1:=fresh in let HP2:=fresh in let HP3:=fresh in let HP4:=fresh in let HP5:=fresh in let HP6:=fresh in let HP7:=fresh in let HP8:=fresh in let HP9:=fresh in let HP10:=fresh in let HP11:=fresh in let HP12:=fresh in let HP13:=fresh in let HP14:=fresh in let HP15:=fresh in let HP16:=fresh in let HP17:=fresh in let HP18:=fresh in let HP19:=fresh in let HP20:=fresh in let HP21:=fresh in let HP22:=fresh in let HP23:=fresh in let HP24:=fresh in let HP25:=fresh in let HP26:=fresh in let HP27:=fresh in let HP28:=fresh in let HP29:=fresh in let HP30:=fresh in destruct (is_only_31_pts P) as
[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[P0 | HP1 ]| HP2 ]| HP3 ]| HP4 ]| HP5 ]| HP6 ]| HP7 ]| HP8 ]| HP9 ]| HP10 ]| HP11 ]| HP12 ]| HP13 ]| HP14 ]| HP15 ]| HP16 ]| HP17 ]| HP18 ]| HP19 ]| HP20 ]| HP21 ]| HP22 ]| HP23 ]| HP24 ]| HP25 ]| HP26 ]| HP27 ]| HP28 ]| HP29 ]| HP30 ]; subst P.
Parameter P2nat : Point -> nat.
Parameter P2nat_0 : P2nat P0 = 0.
Parameter P2nat_1 : P2nat P1 = 1.
Parameter P2nat_2 : P2nat P2 = 2.
Parameter P2nat_3 : P2nat P3 = 3.
Parameter P2nat_4 : P2nat P4 = 4.
Parameter P2nat_5 : P2nat P5 = 5.
Parameter P2nat_6 : P2nat P6 = 6.
Parameter P2nat_7 : P2nat P7 = 7.
Parameter P2nat_8 : P2nat P8 = 8.
Parameter P2nat_9 : P2nat P9 = 9.
Parameter P2nat_10 : P2nat P10 = 10.
Parameter P2nat_11 : P2nat P11 = 11.
Parameter P2nat_12 : P2nat P12 = 12.
Parameter P2nat_13 : P2nat P13 = 13.
Parameter P2nat_14 : P2nat P14 = 14.
Parameter P2nat_15 : P2nat P15 = 15.
Parameter P2nat_16 : P2nat P16 = 16.
Parameter P2nat_17 : P2nat P17 = 17.
Parameter P2nat_18 : P2nat P18 = 18.
Parameter P2nat_19 : P2nat P19 = 19.
Parameter P2nat_20 : P2nat P20 = 20.
Parameter P2nat_21 : P2nat P21 = 21.
Parameter P2nat_22 : P2nat P22 = 22.
Parameter P2nat_23 : P2nat P23 = 23.
Parameter P2nat_24 : P2nat P24 = 24.
Parameter P2nat_25 : P2nat P25 = 25.
Parameter P2nat_26 : P2nat P26 = 26.
Parameter P2nat_27 : P2nat P27 = 27.
Parameter P2nat_28 : P2nat P28 = 28.
Parameter P2nat_29 : P2nat P29 = 29.
Parameter P2nat_30 : P2nat P30 = 30.
Definition leP (x y: Point) : bool := leb (P2nat x) (P2nat y).
Hint Rewrite -> P2nat_0 P2nat_1 P2nat_2 P2nat_3 P2nat_4 P2nat_5 P2nat_6 P2nat_7 P2nat_8 P2nat_9 P2nat_10 P2nat_11 P2nat_12 P2nat_13 P2nat_14 P2nat_15 P2nat_16 P2nat_17 P2nat_18 P2nat_19 P2nat_20 P2nat_21 P2nat_22 P2nat_23 P2nat_24 P2nat_25 P2nat_26 P2nat_27 P2nat_28 P2nat_29 P2nat_30 : order.
Lemma leP_total : forall A B, leP A B || leP B A.
Proof.
intros A B; unfold leP; apply Bool.orb_true_iff;
destruct (le_ge_dec (P2nat A) (P2nat B));
[left; apply leb_correct; assumption |
right; apply leb_correct; unfold ge in *; assumption].
Qed.
Ltac solve_ex_p tac := first [
tac P0 | tac P1 | tac P2 | tac P3 | tac P4 | tac P5 | tac P6 | tac P7 | tac P8 | tac P9 | tac P10 | tac P11 | tac P12 | tac P13 | tac P14 | tac P15 | tac P16 | tac P17 | tac P18 | tac P19 | tac P20 | tac P21 | tac P22 | tac P23 | tac P24 | tac P25 | tac P26 | tac P27 | tac P28 | tac P29 | tac P30 ].
(* Local Variables: *)
(* coq-prog-name: "/Users/magaud/.opam/4.06.0/bin/coqtop" *)
(* coq-load-path: (("/Users/magaud/containers/theories" "Containers") ("/Users/magaud/galapagos/dev/trunk/ProjectiveGeometry/Dev" "ProjectiveGeometry.Dev")) *)
(* suffixes: .v *)
(* End: *)
(** rk-singleton : The rank of a point is always greater than one **)
Lemma rk_singleton_ge : forall P, rk (P :: nil) >= 1.
Proof.
intros.
assert(HH := rk_points);use HH.
case_clear_2 P ;solve [intuition].
Qed.
Lemma rk_singleton_1 : forall A, rk(A :: nil) <= 1.
Proof.
intros.
apply matroid1_b_useful.
solve [intuition].
Qed.
Lemma rk_couple_ge_alt : forall P Q, rk(P :: Q :: nil) = 2 -> rk(P :: Q :: nil) >=2.
Proof.
intuition.
Qed.
(** rk-couple : The rank of a two distinct points is always greater than one **)
Lemma rk_couple_ge : forall P Q, ~ P = Q -> rk(P :: Q :: nil) >= 2.
Proof.
intros.
assert(HH := rk_distinct_points);use HH.
apply rk_couple_ge_alt.
case_clear_2 P;case_clear_2 Q;solve [equal_degens | assumption | rewrite couple_equal;assumption].
Qed.
Lemma rk_couple_2 : forall P Q, rk(P :: Q :: nil) <= 2.
Proof.
intros.
apply matroid1_b_useful.
intuition.
Qed.
Lemma rk_couple : forall P Q : Point,~ P = Q -> rk(P :: Q :: nil) = 2.
Proof.
intros.
assert(HH := rk_couple_2 P Q).
assert(HH0 := rk_couple_ge P Q H).
omega.
Qed.
Lemma couple_rk1 : forall P Q, rk(P :: Q :: nil) = 2 -> ~ P = Q.
Proof.
intros.
intro.
rewrite H0 in H.
assert(HH : equivlist (Q :: Q :: nil) (Q :: nil));[my_inO|].
rewrite HH in H.
assert(HH0 := rk_singleton_1 Q).
omega.
Qed.
Lemma triple_rk2_1 : forall P R, rk(P :: R :: nil) = 2 -> rk(P :: P :: R :: nil) = 2.
Proof.
intros.
assert(HH : equivlist (P :: P :: R :: nil) (P :: R :: nil));[my_inO|];rewrite HH;intuition.
Qed.
Lemma triple_rk2_2 : forall P R, rk(P :: R :: nil) = 2 -> rk(P :: R :: P :: nil) = 2.
Proof.
intros.
assert(HH : equivlist (P :: R :: P :: nil) (P :: R :: nil));[my_inO|];rewrite HH;intuition.
Qed.
Lemma triple_rk2_3 : forall P R, rk(P :: R :: nil) = 2 -> rk(R :: P :: P :: nil) = 2.
Proof.
intros.
assert(HH : equivlist (R :: P :: P :: nil) (P :: R :: nil));[my_inO|];rewrite HH;intuition.
Qed.
Ltac rk_couple_triple_bis_bis :=
match goal with
| H : rk(?A :: ?B :: nil) = 2 |- rk(?A :: ?B :: nil) = 2 => assumption
| H : rk(?B :: ?A :: nil) = 2 |- rk(?A :: ?B :: nil) = 2 => rewrite couple_equal in H;assumption
| H : rk(?A :: ?B :: ?C :: nil) = _ |- rk(?A :: ?B :: ?C :: nil) = _ => assumption
| H : rk(?A :: ?C :: ?B :: nil) = _ |- rk(?A :: ?B :: ?C :: nil) = _ => rewrite <-triple_equal_1 in H;assumption
| H : rk(?B :: ?A :: ?C :: nil) = _ |- rk(?A :: ?B :: ?C :: nil) = _ => rewrite <-triple_equal_2 in H;assumption
| H : rk(?B :: ?C :: ?A :: nil) = _ |- rk(?A :: ?B :: ?C :: nil) = _ => rewrite <-triple_equal_3 in H;assumption
| H : rk(?C :: ?A :: ?B :: nil) = _ |- rk(?A :: ?B :: ?C :: nil) = _ => rewrite <-triple_equal_4 in H;assumption
| H : rk(?C :: ?B :: ?A :: nil) = _ |- rk(?A :: ?B :: ?C :: nil) = _ => rewrite <-triple_equal_5 in H;assumption
end.
Ltac degens_rk2' :=
solve[ first [apply triple_rk2_1 | apply triple_rk2_2 | apply triple_rk2_3];rk_couple_triple_bis_bis].
Ltac solve_ex_1 L t := solve [exists L; t ].
(* | exists L; repeat split;solve [ assumption | degens_rk2' | rk_couple_triple_bis_bis ]].*)
Ltac solve_ex_p_1 t := first [
solve_ex_1 P0 t | solve_ex_1 P1 t| solve_ex_1 P2 t| solve_ex_1 P3 t| solve_ex_1 P4 t| solve_ex_1 P5 t| solve_ex_1 P6 t| solve_ex_1 P7 t| solve_ex_1 P8 t| solve_ex_1 P9 t| solve_ex_1 P10 t| solve_ex_1 P11 t| solve_ex_1 P12 t| solve_ex_1 P13 t| solve_ex_1 P14 t| solve_ex_1 P15 t| solve_ex_1 P16 t| solve_ex_1 P17 t| solve_ex_1 P18 t| solve_ex_1 P19 t | solve_ex_1 P20 t| solve_ex_1 P21 t| solve_ex_1 P22 t| solve_ex_1 P23 t| solve_ex_1 P24 t| solve_ex_1 P25 t| solve_ex_1 P26 t| solve_ex_1 P27 t| solve_ex_1 P28 t| solve_ex_1 P29 t| solve_ex_1 P30 t].
Ltac my_inA :=
intuition;unfold incl in *;unfold equivlist in *; simpl;
repeat match goal with
|[H : _ |- _] => progress intros
|[H : _ |- _] => progress intro
|[H : _ |- _] => progress intuition
|[H : _ |- _] => split;intuition
|[H : In _ (?P :: _ ) |- _] => inversion H;clear H
|[H : _ = _ |- _] => rewrite <-H
|[H : In _ nil |- _] => inversion H
end.
Lemma rk_13_12 : forall A B C U, rk(A::C::B::U)=rk(A::B::C::U).
Proof.
intros; apply rk_compat; unfold equivlist; split; my_inA.
Qed.
Lemma rk_23_12 : forall A B C U, rk(C::A::B::U)=rk(A::B::C::U).
Proof.
intros; apply rk_compat; unfold equivlist; split; my_inA.
Qed.
Lemma rk_sym12 : forall A B U, rk(A::B::U)=rk(B::A::U).
Proof.
intros; apply rk_compat; unfold equivlist; split; my_inA.
Qed.
Lemma rk_sym13 : forall A B C U, rk(A::B::C::U)=rk(C::B::A::U).
Proof.
intros; apply rk_compat; unfold equivlist; split; my_inA.
Qed.
Lemma rk_sym23 : forall A B C U, rk(A::B::C::U)=rk(A::C::B::U).
Proof.
intros; apply rk_compat; unfold equivlist; split; my_inA.
Qed.
Ltac split3 := split; [ assumption | split; solve [assumption | rk_couple_triple_bis_bis ]].
Ltac solver := repeat split;solve [ assumption | degens_rk2' | rk_couple_triple_bis_bis ].
Ltac my_rk_three_points_on_lines :=
match goal with
| H : _ |- exists R, rk (?P :: ?P :: _ :: nil) = 2 /\ _ /\ _ => solve_ex_p_1 solver
| H : rk(?P::?Q::?T1::nil)= 2 |- exists R, rk (?P :: ?Q :: R :: nil) = 2 /\ _ /\ _ =>
solve [ exists T1 ; split3 ]
| H : rk(?P::?T1::?Q::nil)= 2 |- exists R, rk (?P :: ?Q :: R :: nil) = 2 /\ _ /\ _ =>
rewrite rk_13_12 in H; solve [ exists T1 ; split3 ]
| H : rk(?T1::?P::?Q::nil)= 2 |- exists R, rk (?P :: ?Q :: R :: nil) = 2 /\ _ /\ _ =>
rewrite rk_23_12 in H; solve [ exists T1 ; split3 ]
| H : rk(?Q::?P::?T1::nil)= 2 |- exists R, rk (?P :: ?Q :: R :: nil) = 2 /\ _ /\ _ =>
rewrite rk_sym12 in H; solve [ exists T1 ; split3 ]
| H : rk(?Q::?T1::?P::nil)= 2 |- exists R, rk (?P :: ?Q :: R :: nil) = 2 /\ _ /\ _ =>
rewrite rk_sym13 in H; rewrite rk_13_12 in H; solve [ exists T1 ; split3 ]
| H : rk(?T1::?Q::?P::nil)= 2 |- exists R, rk (?P :: ?Q :: R :: nil) = 2 /\ _ /\ _ =>
rewrite rk_sym23 in H; rewrite rk_23_12 in H; solve [ exists T1 ; split3 ]
end.
(** rk-three_point_on_lines : Each lines contains at least three points **)
Lemma rk_three_points_on_lines : forall P Q, exists R,
rk (P :: Q :: R :: nil) = 2 /\ rk (Q :: R :: nil) = 2 /\ rk (P :: R :: nil) = 2.
Proof.
Admitted.
(*intros.
assert(HH := rk_distinct_points);assert(HH0 := rk_lines');use HH;use HH0.
time (case_clear_2 P;case_clear_2 Q ; my_rk_three_points_on_lines).
Time Qed.*)
(* proofs are completed up to here *)
Ltac rk_inter_simplify (*P Q R S*) X X' Y Y' :=
match goal with
| H : _ |- exists J, rk (_ :: Y :: _ :: nil) = 2 /\ rk (_ :: _ :: _ :: nil) = 2 => solve_ex_1 Y
| H : _ |- exists J, rk (Y :: _ :: _ :: nil) = 2 /\ rk (_ :: _ :: _ :: nil) = 2 => solve_ex_1 Y
| H : _ |- exists J, rk (_ :: Y' :: _ :: nil) = 2 /\ rk (_ :: _ :: _ :: nil) = 2 => solve_ex_1 Y'
| H : _ |- exists J, rk (Y' :: _ :: _ :: nil) = 2 /\ rk (_ :: _ :: _ :: nil) = 2 => solve_ex_1 Y'
| H : _ |- exists J, rk (_ :: _ :: _ :: nil) = 2 /\ rk (_ :: X :: _ :: nil) = 2 => solve_ex_1 X
| H : _ |- exists J, rk (_ :: _ :: _ :: nil) = 2 /\ rk (X :: _ :: _ :: nil) = 2 => solve_ex_1 X
| H : _ |- exists J, rk (_ :: _ :: _ :: nil) = 2 /\ rk (_ :: X' :: _ :: nil) = 2 => solve_ex_1 X'
| H : _ |- exists J, rk (_ :: _ :: _ :: nil) = 2 /\ rk (X' :: _ :: _ :: nil) = 2 => solve_ex_1 X'
| H : _ |- exists J, rk (_ :: _ :: _ :: nil) = 2 /\ rk (_ :: _ :: _ :: nil) = 2 => solve [solve_ex_1 X | solve_ex_1 X']
end.
Ltac rk_inter_simplify_bis P Q R S X X' :=
match goal with
| H : rk(R :: S :: ?Y :: ?Y' :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(R :: ?Y :: S :: ?Y' :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(R :: ?Y :: ?Y' :: S :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(S :: R :: ?Y :: ?Y' :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(S :: ?Y :: R :: ?Y' :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(S :: ?Y :: ?Y' :: R :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(?Y :: R :: S :: ?Y' :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(?Y :: R :: ?Y' :: S :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(?Y :: S :: R :: ?Y' :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(?Y :: S :: ?Y' :: R :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(?Y :: ?Y' :: R :: S :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
| H : rk(?Y :: ?Y' :: S :: R :: nil) = 2 |- _ => rk_inter_simplify (*P Q R S*) X X' Y Y'
end.
Ltac solver2 := split;solve [ assumption | degens_rk2' | rk_couple_triple_bis_bis ].
Ltac solve_all := solve_ex_p_1 solver2.
(*Ltac rk_inter_simplify_bis_bis_bis :=
match goal with
(*| H : _ |- exists J, rk (?P :: ?P :: _ :: nil) = 2 /\ rk (?P :: ?P :: _ :: nil) = 2 => solve_ex_p_1 *)
| H : _ |- exists J, rk (?P :: ?P :: _ :: nil) = 2 /\ rk (?Q :: ?Q :: _ :: nil) = 2 => solve_all
| H : _ |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?P :: ?P :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?Q :: ?P :: _ :: nil) = 2 /\ rk (?Q :: ?Q :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?Q :: ?Q :: _ :: nil) = 2 /\ rk (?P :: ?Q :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?Q :: ?Q :: _ :: nil) = 2 /\ rk (?Q :: ?P :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?R :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?R :: ?R :: _ :: nil) = 2 /\ rk (?P :: ?Q :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?P :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?P :: ?R :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?Q :: ?P :: _ :: nil) = 2 /\ rk (?R :: ?P :: _ :: nil) = 2 => solve_ex_1 P
| H : _ |- exists J, rk (?Q :: ?P :: _ :: nil) = 2 /\ rk (?P :: ?R :: _ :: nil) = 2 => solve_ex_1 P
(*| H : _ |- exists J, rk(?Q :: _ :: _ :: nil)= 2 /\ rk(?Q::_::_::nil)= 2 => solve_ex_1 Q
| H : _ |- exists J, rk(?Q :: _ :: _ :: nil)= 2 /\ rk(_::?Q::_::nil)= 2 => solve_ex_1 Q
| H : _ |- exists J, rk(?Q :: _ :: _ :: nil)= 2 /\ rk(_::_::?Q::nil)= 2 => solve_ex_1 Q
*)
| H : rk(?P :: ?Q :: ?X :: nil) = 2 |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?S :: _ :: nil) = 2 => solve_ex_1 X (*rk_inter_simplify_bis P Q R S X *)
| H : rk(?Q :: ?P :: ?X :: nil) = 2 |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?S :: _ :: nil) = 2 => rewrite rk_sym12 in H; solve_ex_1 X (*rk_inter_simplify_bis P Q R S X *)
| H : rk(?P :: ?X :: ?Q :: nil) = 2 |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?S :: _ :: nil) = 2 => solve_ex_1 X (*rk_inter_simplify_bis P Q R S X *)
| H : rk(?Q :: ?P :: ?X :: nil) = 2 |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?S :: _ :: nil) = 2 => solve_ex_1 X(*rk_inter_simplify_bis P Q R S X *)
| H : rk(?Q :: ?X :: ?P :: nil) = 2 |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?S :: _ :: nil) = 2 => solve_ex_1 X(*rk_inter_simplify_bis P Q R S X*)
| H : rk(?X :: ?P :: ?Q :: nil) = 2 |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?S :: _ :: nil) = 2 => solve_ex_1 X(*rk_inter_simplify_bis P Q R S X*)
| H : rk(?X :: ?Q :: ?P :: nil) = 2 |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?S :: _ :: nil) = 2 => solve_ex_1 X(*rk_inter_simplify_bis P Q R S X*)
end.
*)
Lemma symL : forall A B C D, (exists J, rk (A::B::J::nil)= 2 /\ rk (C::D::J::nil)= 2) -> exists J, rk (B::A::J::nil)= 2/\rk(C::D::J::nil)= 2.
Proof.
intros A B C D Hex; destruct Hex as [J [HJ1 HJ2]]; exists J; split; [rewrite <- HJ1 | rewrite <- HJ2]; apply rk_compat; split; my_inA.
Qed.
Lemma symR : forall A B C D, (exists J, rk (A::B::J::nil)= 2 /\ rk (C::D::J::nil)= 2) -> exists J, rk (A::B::J::nil)= 2/\rk(D::C::J::nil)= 2.
Proof.
intros A B C D Hex; destruct Hex as [J [HJ1 HJ2]]; exists J; split; [rewrite <- HJ1 | rewrite <- HJ2]; apply rk_compat; split; my_inA.
Qed.
Lemma symLR : forall A B C D, (exists J, rk (A::B::J::nil)= 2 /\ rk (C::D::J::nil)= 2) -> exists J, rk (B::A::J::nil)= 2/\rk(D::C::J::nil)= 2.
Proof.
intros A B C D Hex; destruct Hex as [J [HJ1 HJ2]]; exists J; split; [rewrite <- HJ1 | rewrite <- HJ2]; apply rk_compat; split; my_inA.
Qed.
(*Ltac rk_triple_bis A B C :=
match goal with
| H : rk(A :: B :: C :: nil) = _ |- _ => assumption
| H : rk(A :: C :: B :: nil) = _ |- _ => rewrite <-triple_equal_1 in H;assumption
| H : rk(B :: A :: C :: nil) = _ |- _ => rewrite <-triple_equal_2 in H;assumption
| H : rk(B :: C :: A :: nil) = _ |- _ => rewrite <-triple_equal_3 in H;assumption
| H : rk(C :: A :: B :: nil) = _ |- _ => rewrite <-triple_equal_4 in H;assumption
| H : rk(C :: B :: A :: nil) = _ |- _ => rewrite <-triple_equal_5 in H;assumption
end.
*)
Ltac solve_T T := solve [exists T; split;
solve [
assumption |
(*rewrite triple_equal_1 ;assumption |
rewrite triple_equal_2 ;assumption |
rewrite triple_equal_3 ;assumption |
rewrite triple_equal_4 ;assumption |
rewrite triple_equal_5 ;assumption |*)
degens_rk2'(*|degens_rk2'*) | rk_couple_triple_bis_bis ]].
Lemma a1 : forall C E D, rk(C::E::D::nil)= 2 -> rk(C::D::E::nil)= 2.
Proof.
Admitted.
Lemma a2 : forall C E D, rk(E::C::D::nil)= 2 -> rk(C::D::E::nil)= 2.
Proof.
Admitted.
Lemma a3 : forall A B T, rk(B::T::A::nil)= 2 -> rk(A::B::T::nil)= 2.
Proof.
Admitted.
Lemma sym12 : forall C E D, rk(E::C::D::nil)= 2 -> rk(C::E::D::nil)= 2.
Proof.
Admitted.
Ltac findhyps := match goal with
| H : _ |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?P :: ?P :: _ :: nil) = 2 => solve_T P
| H : _ |- exists J, rk (?Q :: ?P :: _ :: nil) = 2 /\ rk (?Q :: ?Q :: _ :: nil) = 2 => solve_T P
| H : _ |- exists J, rk (?Q :: ?Q :: _ :: nil) = 2 /\ rk (?P :: ?Q :: _ :: nil) = 2 => solve_T P
| H : _ |- exists J, rk (?Q :: ?Q :: _ :: nil) = 2 /\ rk (?Q :: ?P :: _ :: nil) = 2 => solve_T P
| H : _ |- exists J, rk (?P :: ?Q :: _ :: nil) = 2 /\ rk (?R :: ?R :: _ :: nil) = 2 => solve_T P
| H : _ |- exists J, rk (?R :: ?R :: _ :: nil) = 2 /\ rk (?P :: ?Q :: _ :: nil) = 2 => solve_T P
| H:rk(?A::?B::?T::nil)= 2, H':rk(?C::?D::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?B::?T::nil)= 2, H':rk(?C::_::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?B::?T::nil)= 2, H':rk(_::?C::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?A::?T::nil)= 2, H':rk(_::?C::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?A::?T::nil)= 2, H':rk(?C::_::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?A::?T::nil)= 2, H':rk(?C::?D::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?A::?B::nil)= 2, H':rk(?C::?D::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?A::?B::nil)= 2, H':rk(?C::?D::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?A::?B::nil)= 2, H':rk(?C::_::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?B::?A::nil)= 2, H':rk(_::?C::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?B::?A::nil)= 2, H':rk(?C::?D::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?B::?A::nil)= 2, H':rk(?C::_::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?T::?B::nil)= 2, H':rk(?C::?D::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?T::?B::nil)= 2, H':rk(?C::_::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?T::?B::nil)= 2, H':rk(_::?C::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?T::?A::nil)= 2, H':rk(?C::?D::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?T::?A::nil)= 2, H':rk(?C::_::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?T::?A::nil)= 2, H':rk(_::?C::?D::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
(**)
| H:rk(?A::?B::?T::nil)= 2, H':rk(?D::?C::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?B::?T::nil)= 2, H':rk(?D::_::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?B::?T::nil)= 2, H':rk(_::?D::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?A::?T::nil)= 2, H':rk(_::?D::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?A::?T::nil)= 2, H':rk(?D::_::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?A::?T::nil)= 2, H':rk(?D::?C::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?A::?B::nil)= 2, H':rk(_::?D::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?A::?B::nil)= 2, H':rk(?D::?C::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?A::?B::nil)= 2, H':rk(?D::_::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?B::?A::nil)= 2, H':rk(_::?D::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?B::?A::nil)= 2, H':rk(?D::?C::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?T::?B::?A::nil)= 2, H':rk(?D::_::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?T::?B::nil)= 2, H':rk(?D::?C::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?T::?B::nil)= 2, H':rk(?D::_::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?A::?T::?B::nil)= 2, H':rk(_::?D::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?T::?A::nil)= 2, H':rk(?D::?C::_::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?T::?A::nil)= 2, H':rk(?D::_::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H:rk(?B::?T::?A::nil)= 2, H':rk(_::?D::?C::nil)= 2 |- exists J : Point,
rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [solve_T T | solve_T A | solve_T B | solve_T C | solve_T D]
| H : _ |- exists J, rk (?P :: ?P :: _ :: nil) = 2 /\ rk (?Q :: ?Q :: _ :: nil) = 2 => solve_all
end.
Ltac perform A B :=
match goal with
| H:rk(A::B::?T::nil)= 2 |- _ => solve_T T
| H:rk(A::?T::B::nil)= 2 |- _ => solve_T T
| H:rk(?T::A::B::nil)= 2 |- _ => solve_T T
| H:rk(B::A::?T::nil)= 2 |- _ => solve_T T
| H:rk(B::?T::A::nil)= 2 |- _ => solve_T T
| H:rk(?T::B::A::nil)= 2 |- _ => solve_T T
end.
Ltac better_tac :=
match goal with
| H:_ |-
exists J : Point, rk (?A :: ?B :: J :: nil) = 2 /\ rk (?C :: ?D :: J :: nil) = 2 =>
solve [perform A B | solve_T A | solve_T B | solve_T C | solve_T D | perform C D | solve_all]
end.
(** rk-inter : Two lines always intersect in the plane **)
Lemma rk_inter : forall P Q R S, exists J, rk (P :: Q :: J :: nil) = 2 /\ rk (R :: S :: J :: nil) = 2.
Proof.
intros A B C D; intros.
Require Import wlog.
wlog2 A B leP leP_total ltac:(firstorder rk_couple_triple_bis_bis) idtac.
wlog2 C D leP leP_total ltac:(firstorder rk_couple_triple_bis_bis) idtac.
assert(HH := rk_distinct_points);assert(HH0 := rk_lines');use HH;use HH0.
time (unfold leP; intros P Q HPQ; case_clear_2 P;case_clear_2 Q; autorewrite with order in HPQ; try discriminate).
(* 60 s and 496 goals instead on 961 *)
(*par:time (intros R S HRS; case_clear_2 R; case_clear_2 S; autorewrite with order in HRS; try solve [discriminate | better_tac]).*)
Time Qed.
(** rk-lower_dim : There exist three points which are not collinear **)
Lemma rk_lower_dim : exists P0 P1 P2, rk( P0 :: P1 :: P2 :: nil) >=3.
Proof.
intros.
assert(HH := rk_planes);use HH.
exists P0;exists P2;exists P7;intuition.
Qed.
End s_fanoPlaneModelRkPG25.
(* Local Variables: *)
(* coq-prog-name: "/Users/magaud/.opam/4.06.0/bin/coqtop" *)
(* coq-load-path: (("/Users/magaud/containers/theories" "Containers") ("/Users/magaud/galapagos/dev/trunk/ProjectiveGeometry/Dev" "ProjectiveGeometry.Dev")) *)
(* suffixes: .v *)
(* End: *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_P_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DFF_P_SYMBOL_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_P_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_2clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Dual clocks, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module ram_2clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLKA,
input CLKB,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
`include "functions.vh"
//Local parameters
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
module test_ram;
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [197:0] data;
// Outputs
wire [197:0] out;
wire done;
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// write
sel = 1; w = 1;
data = 198'h115a25886512165251569195908560596a6695612620504191;
addr = 0;
#(`P);
data = 198'h1559546442405a181195655549614540592955a15a26984015;
addr = 3;
#(`P);
// not write
w = 0;
data = 198'h12222222222222222222222222222222222222222222222222;
addr = 3;
#(`P);
// read
sel = 1; w = 0;
addr = 0;
#(`P);
if (out !== 198'h115a25886512165251569195908560596a6695612620504191)
$display("E");
addr = 3;
#(`P);
if (out !== 198'h1559546442405a181195655549614540592955a15a26984015)
$display("E");
#(`P);
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_m_w_channel.v
// Version : v1.0
// Description: master write channel: Issue write commands based on the cmd
// ram entries.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_defines.v"
//Specific WARNINGs moved to INFO by Vivado Synthesis Tool
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_m_w_channel #
(
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_ZERO_INVALID = 1 ,
parameter C_M_AXI_AWUSER_WIDTH = 8 ,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_ATG_AXI4LITE = 0
) (
// system
input Clk ,
input rst_l ,
//aw
output [C_M_AXI_THREAD_ID_WIDTH-1:0] awid_m ,
output [31:0] awaddr_m ,
output [7:0] awlen_m ,
output [2:0] awsize_m ,
output [1:0] awburst_m ,
output [0:0] awlock_m ,
output [3:0] awcache_m ,
output [2:0] awprot_m ,
output [3:0] awqos_m ,
output [C_M_AXI_AWUSER_WIDTH-1:0] awuser_m ,
output awvalid_m ,
input awready_m ,
//w
output wlast_m ,
output [C_M_AXI_DATA_WIDTH-1:0] wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_m ,
output wvalid_m ,
input wready_m ,
//b
input [C_M_AXI_THREAD_ID_WIDTH-1:0] bid_m ,
input [1:0] bresp_m ,
input bvalid_m ,
output bready_m ,
//register module
input reg0_m_enable_ff ,
input [9:0] reg0_mw_ptr_ff ,
input reg0_m_enable_cmdram_mrw ,
input reg0_m_enable_cmdram_mrw_ff ,
input reg0_m_enable_3ff ,
input reg0_loop_en_ff ,
output reg mw_done_ff ,
output reg b_resp_unexp_ff ,
output reg b_resp_bad_ff ,
output [9:0] reg0_mw_ptr_update ,
//param ram block
input param_cmdw_delayop_valid ,
input [23:0] param_cmdw_count ,
input param_cmdw_repeatfixedop_valid,
input param_cmdw_disable_submitincr ,
input mrd_done ,
//cmd ram
input [127:0] cmd_out_mw ,
input cmdram_mw_regslice_id_stable ,
//master ram
input [C_M_AXI_DATA_WIDTH-1:0] mram_out ,
output [15:0] maw_agen_addr ,
//masterread
output reg [8:0] mwr_complete_ptr_ff ,
input [8:0] mrd_complete_ptr_ff ,
//debug data
output [15:0] Maw_fifow_dbgout ,
//external modules
output reg [9:0] maw_ptr_new_ff ,
output reg [9:0] maw_ptr_new_2ff ,
output reg maw_fifo_push_ff ,
//axi_traffic_gen_v2_0_debug_capture
output maw_fifow_notfull ,
output reg maw_delay_ok_ff ,
output maw_cnt_do_dec ,
output maw_fifo_notfull ,
output [3:0] mawtrk_free ,
output maw_fifo0_notfull ,
output maw_fifo1_notfull ,
output maw_fifo2_notfull ,
output maw_fifo3_notfull ,
output reg maw_block_push_ff ,
output b_resp_bad ,
output reg b_complete_ff ,
output [9:0] maw_ptr_new ,
output maw_fifow_push ,
output mw_done ,
output maw_fifo0_user_disableincr ,
output maw_disableincr ,
output reg maw_disableincr_ff ,
output maw_fifo1_pop ,
output maw_fifo0_pop ,
output maw_agen_done ,
output mw_fifo_valid ,
output mw_fifo_pop ,
output mw_fifo_notfull ,
output maw_fifow_pop ,
output maw_fifow_valid ,
output maw_done ,
output maw_valid ,
output maw_fifo_push ,
output maw_depend_ok ,
output reg [8:0] maw_complete_depth ,
output [8:0] mwr_complete_ptr ,
output [15:0] maw_complete_next2 ,
output reg [15:0] maw_complete_vec_ff ,
output maw_complete_doinc ,
output [15:0] maw_complete_inc_exp ,
output maw_agen_valid
);
// MASTER WRITE
reg maw_done_ff, maw_fifow_push_ff, maw_fifow_push_block_ff;
reg [23:0] maw_cnt_ff;
reg [C_M_AXI_THREAD_ID_WIDTH-1:0] bid_m_ff;
reg [1:0] bresp_m_ff;
axi_traffic_gen_v2_0_regslice
#(
.DWIDTH (1),
.IDWIDTH (1),
.DATADEPTH(`REGSLICE_FIFOPUSH_DATA)
)
mawfifopush_regslice
(
.din (maw_fifo_push ),
.dout (maw_fifo_push_xff),
.dout_early ( ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
// Push cmd_out_mw into maw_fifo, if rd_depend and wr_depend are met, if
// there's room in maw_fifo and maw_fifow.
// CR#768069: when the loop is enabled, issue & complete pointers
// cannot be directly compared as the issue pointer roll backs to start
// value after the last command is issued.
// So inc/dec_ptr pulses are used to calculate the complete depth.
wire inc_ptr,dec_ptr;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
maw_complete_depth <= 9'h0;
end else if(inc_ptr & dec_ptr) begin
maw_complete_depth <= maw_complete_depth;
end else if(inc_ptr) begin
maw_complete_depth <= maw_complete_depth+1'b1;
end else if(dec_ptr) begin
maw_complete_depth <= maw_complete_depth-1'b1;
end
end
//assign maw_complete_depth = (reg0_mw_ptr_ff[8:0]-mwr_complete_ptr_ff[8:0]);
wire maw_block_push = (maw_complete_depth[8:0] >= 9'h0d);
//wire maw_cnt_reload = ~reg0_m_enable_cmdram_mrw_ff || maw_fifo_push_ff;
wire maw_cnt_reload = ~reg0_m_enable_cmdram_mrw_ff || maw_fifo_push_xff;
//wire [7:0] maw_cnt_expand =
// ((cmd_out_mw[59:56] == 4'h0) ? 8'h00 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h1) ? 8'h00 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h2) ? 8'h01 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h3) ? 8'h02 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h4) ? 8'h06 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h5) ? 8'h09 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h6) ? 8'h0c : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h7) ? 8'h11 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h8) ? 8'h18 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'h9) ? 8'h21 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'ha) ? 8'h32 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'hb) ? 8'h45 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'hc) ? 8'h68 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'hd) ? 8'h81 : 8'h00) |
// ((cmd_out_mw[59:56] == 4'he) ? 8'hbe : 8'h00) |
// ((cmd_out_mw[59:56] == 4'hf) ? 8'hff : 8'h00);
wire maw_cnt_is_not0 = (maw_cnt_ff[23:0] != 24'h0);
wire maw_cnt_ok = ~maw_cnt_reload && ~maw_cnt_is_not0;
//CR#768069: depend ok set to success when loop enabled.
wire [8:0] maw_wr_depend = cmd_out_mw[94:86];
wire [8:0] maw_rd_depend = cmd_out_mw[85:77];
assign maw_depend_ok = (reg0_loop_en_ff | mrd_done) ? 1'b1 :
((maw_rd_depend[7:0] <= mrd_complete_ptr_ff) &
(maw_wr_depend[7:0] <= mwr_complete_ptr_ff));
//wire maw_valid = cmd_out_mw[63] && reg0_m_enable_3ff;
assign maw_valid = (cmd_out_mw[63] && cmdram_mw_regslice_id_stable) && reg0_m_enable_cmdram_mrw && reg0_m_enable_3ff;
//wire maw_delay_ok = (cmd_out_mw[59:56] == 4'h0) || maw_cnt_ok;
assign maw_delay_ok = (cmd_out_mw[59:56] == 4'h0 &&
~( param_cmdw_delayop_valid || param_cmdw_repeatfixedop_valid)) || maw_cnt_ok;
//flop delay_ok for timing improvement
reg maw_fifow_notfull_ff;
always @(posedge Clk) begin
maw_delay_ok_ff <= (rst_l) ? maw_delay_ok : 1'b0;
end
assign maw_cnt_do_dec = maw_fifo_notfull && maw_depend_ok &&
maw_fifow_notfull_ff && (mawtrk_free[3:0] != 4'h0) &&
maw_fifo0_notfull && maw_fifo1_notfull &&
maw_fifo2_notfull && maw_fifo3_notfull &&
~maw_block_push_ff;
//flop maw_cnt_do_dec for timing improvement
reg maw_cnt_do_dec_ff;
always @(posedge Clk) begin
maw_cnt_do_dec_ff <= (rst_l) ? maw_cnt_do_dec : 1'b0;
end
assign maw_fifo_push = maw_valid && maw_cnt_do_dec && maw_delay_ok_ff && ~maw_fifo_push_ff ;
//flop maw_fifo_push for timing improvement
reg maw_fifo_push_1ff;
always @(posedge Clk) begin
maw_fifo_push_1ff <= (rst_l)? maw_fifo_push : 1'b0;
end
assign maw_fifow_push = maw_valid && maw_cnt_do_dec && maw_delay_ok_ff && ~maw_fifow_push_block_ff && ~maw_fifow_push_ff ;
//wire maw_fifow_push = maw_valid && maw_cnt_do_dec && ~maw_fifow_push_block_ff && ~maw_fifow_push_ff ;
//flop maw_fifwo_push for timing improvement
reg maw_fifow_push_1ff;
always @(posedge Clk) begin
maw_fifow_push_1ff <= (rst_l)? maw_fifow_push : 1'b0;
end
wire maw_fifow_push_block = ~maw_fifo_push_1ff && reg0_m_enable_3ff &&
(maw_fifow_push_1ff || maw_fifow_push_block_ff);
wire param_maw_cnt_reload_delayop = param_cmdw_delayop_valid && (~reg0_m_enable_cmdram_mrw_ff || maw_fifo_push_xff );
wire param_maw_cnt_reload_repeatfixedop = param_cmdw_repeatfixedop_valid && (~reg0_m_enable_cmdram_mrw_ff || maw_fifo_push_xff );
reg [23:0] maw_cnt_minus1_ff;
/*
wire [23:0] maw_cnt = (param_maw_cnt_reload_delayop) ? param_cmdw_count_ff[23:0] :
(param_maw_cnt_reload_repeatfixedop) ? {12'h0,param_cmdw_count_ff[19:8]} :
(maw_cnt_reload) ? {16'h0,maw_cnt_expand[7:0]} :
(maw_cnt_do_dec) ? maw_cnt_minus1_ff :
maw_cnt_ff[23:0];
*/
wire [23:0] maw_cnt_minus1 = maw_cnt_ff[23:0] - { 22'h0, maw_cnt_is_not0 };
wire [23:0] maw_cnt = (param_maw_cnt_reload_delayop) ? param_cmdw_count[23:0] :
(param_maw_cnt_reload_repeatfixedop) ? {12'h0,param_cmdw_count[19:8]} :
//(maw_cnt_reload) ? {16'h0,maw_cnt_expand[7:0]} : //Arb delay feature removed.
(maw_cnt_do_dec_ff) ? maw_cnt_minus1 :
maw_cnt_ff[23:0];
//CR#768069:
// a.Get the last disable command index.
// b.Generate a pulse to re-start pointers
// commands issued pointers : reg0_mw_ptr_ff
// commandes completed pointers: mwr_complete_ptr_ff
// Latch reg0_mw_ptr_ff when last command received and use that to
// clear mwr_complete_ptr_ff when it reached reg0_mw_ptr_ff latched value.
// c.Validate all these signals when loop is enabled.
// d.Hold generating the complete signal(maw_done) when loop is enabled.
// e.mask dependency when loop is enabled.
wire cur_itrn_dis_rcvd; //current iteration disable received
reg cur_itrn_dis_rcvd_d1; //current iteration disable received 1clk delayed
assign cur_itrn_dis_rcvd = reg0_m_enable_ff && reg0_m_enable_3ff && reg0_loop_en_ff &&
( (~cmd_out_mw[63] && cmdram_mw_regslice_id_stable) || maw_done_ff);
wire cur_itrn_done;
always @(posedge Clk) begin
cur_itrn_dis_rcvd_d1 <= (rst_l) ? cur_itrn_dis_rcvd : 1'b0;
end
assign cur_itrn_done = cur_itrn_dis_rcvd & ~cur_itrn_dis_rcvd_d1;
assign maw_done = reg0_m_enable_ff && reg0_m_enable_3ff && ~reg0_loop_en_ff &&
( (~cmd_out_mw[63] && cmdram_mw_regslice_id_stable) || maw_done_ff);
// increment unless specialqueue is active disable bit set
assign maw_ptr_new = (cur_itrn_done)? 10'h0:
((maw_fifo_push_ff && ~param_cmdw_disable_submitincr) ? reg0_mw_ptr_ff[9:0] + 10'h1:
reg0_mw_ptr_ff[9:0]);
//CR#768069:Hold the index where the invalid command received in cmdram set.
reg [9:0] last_cmd_index;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
last_cmd_index <= 10'h3FF;
end else if(cur_itrn_done) begin
last_cmd_index <= reg0_mw_ptr_ff;
end else begin
last_cmd_index <= last_cmd_index;
end
end
//inc_ptr: pulse when command issued pointer is incremented.
assign inc_ptr = maw_fifo_push_ff && ~param_cmdw_disable_submitincr;
assign reg0_mw_ptr_update[9:0] = maw_ptr_new[9:0];
// Calculate separate maw_fifow_push to allow wdata to get data even if
// mawaddr is blocked by cnt.
always @(posedge Clk) begin
maw_done_ff <= (rst_l) ? maw_done : 1'b0;
maw_fifo_push_ff <= (rst_l) ? maw_fifo_push : 1'b0;
maw_fifow_push_ff <= (rst_l) ? maw_fifow_push : 1'b0;
maw_block_push_ff <= (rst_l) ? maw_block_push : 1'b0;
maw_fifow_push_block_ff <= (rst_l) ? maw_fifow_push_block : 1'b0;
maw_cnt_ff[23:0] <= (rst_l) ? maw_cnt[23:0] : 24'h0;
maw_cnt_minus1_ff[23:0] <= (rst_l) ? maw_cnt_minus1[23:0] : 24'h0;
maw_ptr_new_ff <= (rst_l) ? maw_ptr_new : 8'h0;
maw_ptr_new_2ff <= (rst_l) ? maw_ptr_new_ff : 8'h0;
end
wire [20:0] maw_fifo0_out, maw_fifo1_out, maw_fifo2_out, maw_fifo3_out;
wire maw_fifo0_valid;
wire maw_fifo1_valid;
wire maw_fifo2_valid, maw_fifo2_pop;
wire maw_fifo3_valid, maw_fifo3_pop;
wire [3:0] mawtrk_clear_pos = { ~maw_fifo3_valid,
~maw_fifo2_valid,
~maw_fifo1_valid,
~maw_fifo0_valid };
wire [3:0] mawtrk_fifo_num, mawtrk_bid_hit;
wire [C_M_AXI_THREAD_ID_WIDTH-1:0] mawtrk_in_push_id = cmd_out_mw[52:47];
wire [C_M_AXI_THREAD_ID_WIDTH-1:0] mawtrk_in_search_id =
bid_m_ff[C_M_AXI_THREAD_ID_WIDTH-1:0];
wire dis_dis_out_of_order;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_M_W_OOO_YES
assign dis_dis_out_of_order = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_M_W_OOO_NO
assign dis_dis_out_of_order = 1'b1;
end
endgenerate
// flop inputs to maw_track by 1 stage
// search should not be flopped, as search_id and search_hit occurs in 1 clock
// cycle.Delaying search, causes to hit a wrong search ID.
reg [C_M_AXI_THREAD_ID_WIDTH-1:0] mawtrk_in_push_id_1ff;
reg [C_M_AXI_THREAD_ID_WIDTH-1:0] mawtrk_in_search_id_1ff;
reg [3:0] mawtrk_clear_pos_1ff;
always @(posedge Clk) begin
mawtrk_in_push_id_1ff <= mawtrk_in_push_id ;
mawtrk_in_search_id_1ff <= mawtrk_in_search_id;
mawtrk_clear_pos_1ff <= mawtrk_clear_pos;
end
axi_traffic_gen_v2_0_id_track #(
.ID_WIDTH(C_M_AXI_THREAD_ID_WIDTH)
) Maw_track (
.Clk (Clk ),
.rst_l (rst_l ),
.in_push_id (mawtrk_in_push_id_1ff[C_M_AXI_THREAD_ID_WIDTH-1:0] ),
.in_push (maw_fifo_push_1ff ),
.in_search_id (mawtrk_in_search_id[C_M_AXI_THREAD_ID_WIDTH-1:0] ),
.in_clear_pos (mawtrk_clear_pos[3:0] ),
.in_only_entry0(dis_dis_out_of_order ),
.out_push_pos (mawtrk_fifo_num[3:0] ),
.out_search_hit(mawtrk_bid_hit[3:0] ),
.out_free (mawtrk_free[3:0] )
);
wire [92:0] maw_fifo_out;
wire maw_fifo_valid, maw_fifo_pop;
//flop maw_fifo_pop for timing improvement
reg [92:0] cmd_out_mw_1ff;
reg [48:0] cmd_out_mw_opt_1ff ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : AXI4_AW_BASIC1_YES
always @(posedge Clk) begin
cmd_out_mw_1ff <= { cmd_out_mw[115:100], cmd_out_mw[76:0] } ;
end
end
endgenerate
// Command Forma:Field: bits: Actual bit location in 128 bit data.
// address 32 31 0
// len 8 39 32
// lock 1 40 40
// reserved 1 41 41
// burst 2 43 42
// size 3 46 44
// id 6 52 47
// prot 3 55 53
// reserved 4 59 56
// last addr 3 62 60
// valid cmd 1 63 63
// mstram index 13 76 64
// other depend 9 85 77
// my depend 9 94 86
// reserved 1 95 95
// expected resp 3 98 96
// reserved 1 99 99
// cache 4 103 100
// user 8 111 104
// qos 4 115 112
// reserved 12 127 116
generate if(C_ATG_BASIC_AXI4 == 1) begin : AXI4_AW_BASIC1_NO
always @(posedge Clk) begin
cmd_out_mw_opt_1ff <= {
cmd_out_mw[52:47], //id
cmd_out_mw[46:44], //size
cmd_out_mw[39:32], //len
cmd_out_mw[31: 0] }; //address
end
end
endgenerate
localparam EX_FIFO_DEPTH = 8; //16 : Original values.
localparam EX_FIFO_DEPTHBITS = 3; // 4
localparam EX_FIFO_FULL_LEVEL = 6; //14
generate if(C_ATG_BASIC_AXI4 == 0) begin : AXI4_AW_BASIC2_NO
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (93 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Maw_fifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (cmd_out_mw_1ff ),
.in_push (maw_fifo_push_1ff ),
.in_pop (maw_fifo_pop ),
.out_data (maw_fifo_out[92:0] ),
.is_full ( ),
.is_notfull (maw_fifo_notfull ),
.is_empty ( ),
.out_valid (maw_fifo_valid ),
.ex_fifo_dbgout ( )
);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : AXI4_AW_BASIC2_YES
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (49 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Maw_fifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (cmd_out_mw_opt_1ff ),
.in_push (maw_fifo_push_1ff ),
.in_pop (maw_fifo_pop ),
.out_data (maw_fifo_out[48:0] ),
.is_full ( ),
.is_notfull (maw_fifo_notfull ),
.is_empty ( ),
.out_valid (maw_fifo_valid ),
.ex_fifo_dbgout ( )
);
end
endgenerate
assign maw_fifo_pop = awvalid_m && awready_m;
generate if(C_ATG_BASIC_AXI4 == 0) begin : AXI4_AW_BASIC_NO
assign awid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] = maw_fifo_out[52:47];
assign awsize_m[2:0] = maw_fifo_out[46:44];
assign awlen_m[7:0] = maw_fifo_out[39:32];
assign awaddr_m[31:0] = maw_fifo_out[31:0];
assign awvalid_m = maw_fifo_valid;
assign awlock_m[0:0] = maw_fifo_out[40:40]; //awlock made 1-bit signal
assign awburst_m[1:0] = maw_fifo_out[43:42];
assign awprot_m[2:0] = maw_fifo_out[55:53];
assign awcache_m[3:0] = maw_fifo_out[80:77];
assign awuser_m[C_M_AXI_AWUSER_WIDTH-1:0] = maw_fifo_out[88:81];
assign awqos_m[3:0] = maw_fifo_out[92:89];
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : AXI4_AW_BASIC_YES
assign awid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] = maw_fifo_out[48:43];
assign awsize_m[2:0] = maw_fifo_out[42:40];
assign awlen_m[7:0] = maw_fifo_out[39:32];
assign awaddr_m[31:0] = maw_fifo_out[31:0];
assign awvalid_m = maw_fifo_valid;
assign awlock_m[0:0] = 1'b0;
assign awburst_m[1:0] = 2'h1;
assign awprot_m[2:0] = 3'b000;
assign awcache_m[3:0] = 4'b0011;
assign awuser_m[C_M_AXI_AWUSER_WIDTH-1:0] = {C_M_AXI_AWUSER_WIDTH{1'b0}};
assign awqos_m[3:0] = 4'h0;
end
endgenerate
wire [76+1:0] maw_fifow_out;
//
//add flopping state for timing improvement
//
reg [76+1:0] maw_fifow_in_ff;
always @(posedge Clk) begin
maw_fifow_in_ff <= (rst_l) ? {param_cmdw_disable_submitincr,cmd_out_mw[76:0]} : 77'h0 ;
end
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (78),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Maw_fifow (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (maw_fifow_in_ff ),
.in_push (maw_fifow_push_1ff ),
.in_pop (maw_fifow_pop ),
.out_data (maw_fifow_out[76+1:0]),
.is_full ( ),
.is_notfull (maw_fifow_notfull ),
.is_empty ( ),
.out_valid (maw_fifow_valid ),
.ex_fifo_dbgout (Maw_fifow_dbgout )
);
wire [15:0] maw_agen_id;
wire [C_M_AXI_DATA_WIDTH/8-1:0] maw_agen_be;
wire maw_agen_pop;
//
//add flopping state for timing improvement
//
reg [77:0] maw_fifow_out_ff;
reg maw_fifow_pop_ff;
reg maw_fifow_valid_ff;
always @(posedge Clk) begin
maw_fifow_out_ff <= (rst_l) ? maw_fifow_out : 78'h0 ;
maw_fifow_pop_ff <= (rst_l) ? maw_fifow_pop : 1'b0 ;
maw_fifow_valid_ff <= (rst_l) ? maw_fifow_valid : 1'b0 ;
maw_fifow_notfull_ff <= (rst_l) ? maw_fifow_notfull: 1'b0 ;
end
axi_traffic_gen_v2_0_addrgen #(
.USE_ADDR_OFFSET (1) ,
.C_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4 (C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Maw_agen (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({ 3'b000, maw_fifow_out[76:64] } ),
.in_addr_offset({1'b0,maw_fifow_out[7:0] } ),
.in_id ({ 10'h0, maw_fifow_out[52:47]} ),
.in_len (maw_fifow_out[39:32] ),
.in_size (maw_fifow_out[46:44] ),
.in_lastaddr ({3'b000,maw_fifow_out[62:60]} ),
.in_burst (maw_fifow_out[43:42] ),
.in_push (maw_fifow_pop ),
.in_pop (maw_agen_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (maw_agen_addr[15:0] ),
.out_id (maw_agen_id[15:0] ),
.out_be (maw_agen_be[C_M_AXI_DATA_WIDTH/8-1:0] ),
.out_done (maw_agen_done ),
.out_valid (maw_agen_valid )
);
assign maw_agen_pop = mw_fifo_notfull && maw_agen_valid;
assign maw_fifow_pop = (~maw_agen_valid || maw_agen_done && maw_agen_pop) &&
maw_fifow_valid_ff && ~maw_fifow_pop_ff;
// Transmit master write data
reg [5:0] mw_id_ff;
reg [C_M_AXI_DATA_WIDTH/8-1:0] maw_agen_be_ff;
reg [15:0] maw_agen_addr_ff;
reg maw_agen_done_ff, maw_agen_pop_ff;
wire [C_M_AXI_DATA_WIDTH*9/8+7-1:0] mw_fifo_out;
wire [5:0] mw_id = maw_agen_id[5:0];
wire [63:0] mw_be32 = maw_agen_be_ff[C_M_AXI_DATA_WIDTH/8-1:0];
wire [C_M_AXI_DATA_WIDTH-1:0] mw_in_mask = {
{ 8 { mw_be32[63] } }, { 8 { mw_be32[62] } },
{ 8 { mw_be32[61] } }, { 8 { mw_be32[60] } },
{ 8 { mw_be32[59] } }, { 8 { mw_be32[58] } },
{ 8 { mw_be32[57] } }, { 8 { mw_be32[56] } },
{ 8 { mw_be32[55] } }, { 8 { mw_be32[54] } },
{ 8 { mw_be32[53] } }, { 8 { mw_be32[52] } },
{ 8 { mw_be32[51] } }, { 8 { mw_be32[50] } },
{ 8 { mw_be32[49] } }, { 8 { mw_be32[48] } },
{ 8 { mw_be32[47] } }, { 8 { mw_be32[46] } },
{ 8 { mw_be32[45] } }, { 8 { mw_be32[44] } },
{ 8 { mw_be32[43] } }, { 8 { mw_be32[42] } },
{ 8 { mw_be32[41] } }, { 8 { mw_be32[40] } },
{ 8 { mw_be32[39] } }, { 8 { mw_be32[38] } },
{ 8 { mw_be32[37] } }, { 8 { mw_be32[36] } },
{ 8 { mw_be32[35] } }, { 8 { mw_be32[34] } },
{ 8 { mw_be32[33] } }, { 8 { mw_be32[32] } },
{ 8 { mw_be32[31] } }, { 8 { mw_be32[30] } },
{ 8 { mw_be32[29] } }, { 8 { mw_be32[28] } },
{ 8 { mw_be32[27] } }, { 8 { mw_be32[26] } },
{ 8 { mw_be32[25] } }, { 8 { mw_be32[24] } },
{ 8 { mw_be32[23] } }, { 8 { mw_be32[22] } },
{ 8 { mw_be32[21] } }, { 8 { mw_be32[20] } },
{ 8 { mw_be32[19] } }, { 8 { mw_be32[18] } },
{ 8 { mw_be32[17] } }, { 8 { mw_be32[16] } },
{ 8 { mw_be32[15] } }, { 8 { mw_be32[14] } },
{ 8 { mw_be32[13] } }, { 8 { mw_be32[12] } },
{ 8 { mw_be32[11] } }, { 8 { mw_be32[10] } },
{ 8 { mw_be32[9] } }, { 8 { mw_be32[8] } },
{ 8 { mw_be32[7] } }, { 8 { mw_be32[6] } },
{ 8 { mw_be32[5] } }, { 8 { mw_be32[4] } },
{ 8 { mw_be32[3] } }, { 8 { mw_be32[2] } },
{ 8 { mw_be32[1] } }, { 8 { mw_be32[0] } } };
wire [C_M_AXI_DATA_WIDTH-1:0] mw_data_masked =
mram_out[C_M_AXI_DATA_WIDTH-1:0] &
mw_in_mask[C_M_AXI_DATA_WIDTH-1:0];
wire [C_M_AXI_DATA_WIDTH*9/8+7-1:0] mw_in_data = {
mw_id_ff[5:0], maw_agen_done_ff, //77:72
maw_agen_be_ff[C_M_AXI_DATA_WIDTH/8-1:0], //71:64
mw_data_masked[C_M_AXI_DATA_WIDTH-1:0] }; //63:0
//63:0
reg [5:0] mw_id_2ff;
reg maw_agen_done_2ff;
always @(posedge Clk) begin
mw_id_ff[5:0] <= (rst_l) ? mw_id[5:0] : 6'h0;
maw_agen_be_ff[C_M_AXI_DATA_WIDTH/8-1:0] <= (rst_l) ?
maw_agen_be[C_M_AXI_DATA_WIDTH/8-1:0] : {(C_M_AXI_DATA_WIDTH/8){1'b0}};
maw_agen_addr_ff[15:0] <= (rst_l) ? maw_agen_addr[15:0] : 16'h0;
maw_agen_done_ff <= (rst_l) ? maw_agen_done : 1'b0;
maw_agen_pop_ff <= (rst_l) ? maw_agen_pop : 1'b0;
//2nd stage
mw_id_2ff <= (rst_l) ? mw_id_ff : 0;
maw_agen_done_2ff <= (rst_l) ? maw_agen_done_ff : 0;
end
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH(C_M_AXI_DATA_WIDTH*9/8+7),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Mw_fifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data(mw_in_data[C_M_AXI_DATA_WIDTH*9/8+7-1:0]),
.in_push (maw_agen_pop_ff ),
.in_pop (mw_fifo_pop ),
.out_data(mw_fifo_out[C_M_AXI_DATA_WIDTH*9/8+7-1:0]),
.is_full ( ),
.is_notfull (mw_fifo_notfull ),
.is_empty ( ),
.out_valid (mw_fifo_valid ),
.ex_fifo_dbgout ( )
);
assign mw_fifo_pop = mw_fifo_valid && wready_m;
assign wvalid_m = mw_fifo_valid;
assign wdata_m[C_M_AXI_DATA_WIDTH-1:0] = mw_fifo_out[C_M_AXI_DATA_WIDTH-1:0];
assign wstrb_m[C_M_AXI_DATA_WIDTH/8-1:0] =
mw_fifo_out[C_M_AXI_DATA_WIDTH*9/8-1:C_M_AXI_DATA_WIDTH];
assign wlast_m = mw_fifo_out[C_M_AXI_DATA_WIDTH*9/8];
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (21),
.DEPTH (EX_FIFO_DEPTH),
.DEPTHBITS (EX_FIFO_DEPTHBITS ),
.HEADREG (1 ),
.FULL_LEVEL(EX_FIFO_FULL_LEVEL)
) Maw_fifo0 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data ({ param_cmdw_disable_submitincr,
reg0_mw_ptr_ff[7:0],
cmd_out_mw[99:96],
cmd_out_mw[62:61],
cmd_out_mw[52:47] } ),
.in_push (mawtrk_fifo_num[0] ),
.in_pop (maw_fifo0_pop ),
.out_data (maw_fifo0_out[20:0] ),
.is_full ( ),
.is_notfull (maw_fifo0_notfull ),
.is_empty ( ),
.out_valid (maw_fifo0_valid ),
.ex_fifo_dbgout ( )
);
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_M_W_OOO_F_NO
assign maw_fifo1_notfull = 1'b1;
assign maw_fifo1_valid = 1'b0;
assign maw_fifo2_notfull = 1'b1;
assign maw_fifo2_valid = 1'b0;
assign maw_fifo3_notfull = 1'b1;
assign maw_fifo3_valid = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_M_W_OOO_F_YES
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (21),
.DEPTH (EX_FIFO_DEPTH),
.DEPTHBITS (EX_FIFO_DEPTHBITS ),
.HEADREG (1 ),
.FULL_LEVEL(EX_FIFO_FULL_LEVEL)
) Maw_fifo1 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data ({ param_cmdw_disable_submitincr,
reg0_mw_ptr_ff[7:0],
cmd_out_mw[99:96],
cmd_out_mw[62:61],
cmd_out_mw[52:47] } ),
.in_push (mawtrk_fifo_num[1] ),
.in_pop (maw_fifo1_pop ),
.out_data (maw_fifo1_out[20:0] ),
.is_full ( ),
.is_notfull (maw_fifo1_notfull ),
.is_empty ( ),
.out_valid (maw_fifo1_valid ),
.ex_fifo_dbgout ( )
);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (21),
.DEPTH (EX_FIFO_DEPTH),
.DEPTHBITS (EX_FIFO_DEPTHBITS ),
.HEADREG (1 ),
.FULL_LEVEL(EX_FIFO_FULL_LEVEL)
) Maw_fifo2 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data ({ param_cmdw_disable_submitincr,
reg0_mw_ptr_ff[7:0],
cmd_out_mw[99:96],
cmd_out_mw[62:61],
cmd_out_mw[52:47] } ),
.in_push (mawtrk_fifo_num[2] ),
.in_pop (maw_fifo2_pop ),
.out_data (maw_fifo2_out[20:0] ),
.is_full ( ),
.is_notfull (maw_fifo2_notfull ),
.is_empty ( ),
.out_valid (maw_fifo2_valid ),
.ex_fifo_dbgout ( )
);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (21),
.DEPTH (EX_FIFO_DEPTH),
.DEPTHBITS (EX_FIFO_DEPTHBITS ),
.HEADREG (1 ),
.FULL_LEVEL(EX_FIFO_FULL_LEVEL)
) Maw_fifo3 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data ({ param_cmdw_disable_submitincr,
reg0_mw_ptr_ff[7:0],
cmd_out_mw[99:96],
cmd_out_mw[62:61],
cmd_out_mw[52:47] } ),
.in_push (mawtrk_fifo_num[3] ),
.in_pop (maw_fifo3_pop ),
.out_data (maw_fifo3_out[20:0] ),
.is_full ( ),
.is_notfull (maw_fifo3_notfull ),
.is_empty ( ),
.out_valid (maw_fifo3_valid ),
.ex_fifo_dbgout ( )
);
end
endgenerate
assign maw_fifo0_pop = b_complete_ff && maw_fifo0_valid && mawtrk_bid_hit[0];
assign maw_fifo1_pop = b_complete_ff && maw_fifo1_valid && mawtrk_bid_hit[1];
assign maw_fifo2_pop = b_complete_ff && maw_fifo2_valid && mawtrk_bid_hit[2];
assign maw_fifo3_pop = b_complete_ff && maw_fifo3_valid && mawtrk_bid_hit[3];
/****
// MASTER BID
reg bready_int_ff = 1'b0;
reg b_resp_unexp_ff;
reg b_resp_bad_ff;
wire b_complete = bready_m && bvalid_m;
wire [2:0] b_resp_exp = ((mawtrk_bid_hit[0]) ? maw_fifo0_out[10:8] : 3'b000) |
((mawtrk_bid_hit[1]) ? maw_fifo1_out[10:8] : 3'b000) |
((mawtrk_bid_hit[2]) ? maw_fifo2_out[10:8] : 3'b000) |
((mawtrk_bid_hit[3]) ? maw_fifo3_out[10:8] : 3'b000);
wire [2:0] b_resp_mask =
((bresp_m_ff[1:0] == 2'b00) ? 3'b001 : 3'b000) |
((bresp_m_ff[1:0] == 2'b01) ? 3'b010 : 3'b000) |
((bresp_m_ff[1] == 1'b1) ? 3'b100 : 3'b000);
wire [2:0] b_resp_allowed = (b_resp_exp[2:0] == 3'b000) ? 3'b001 :
b_resp_exp[2:0];
wire b_resp_ok = ((b_resp_mask[2:0] & b_resp_allowed[2:0]) != 3'b000);
wire b_resp_bad = b_complete_ff && ~b_resp_ok;
wire b_resp_unexp = b_complete_ff & (mawtrk_bid_hit[3:0] == 4'h0);
always @(posedge Clk) begin
bready_int_ff <= (rst_l) ? bready_int : 1'b0;
b_complete_ff <= (rst_l) ? b_complete : 1'b0;
b_resp_unexp_ff <= (rst_l) ? b_resp_unexp : 1'b0;
b_resp_bad_ff <= (rst_l) ? b_resp_bad : 1'b0;
bid_m_ff[C_M_AXI_THREAD_ID_WIDTH-1:0] <= (rst_l) ?
bid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] : 1'b0;
bresp_m_ff[1:0] <= (rst_l) ? bresp_m[1:0] : 2'b00;
end
assign bready_m = bready_int_ff;
****/
/* grahams : new version that does WR completion based on wlast
and NOT on bresp.... several IP does not wait for
resp signal before completing a tranx
*/
// new complete signal based on wlast
//wire b_complete = wlast_m && wready_m;
wire b_complete = bready_m && bvalid_m;
wire [2:0] b_resp_exp ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_M_W1_OOO_F_YES
assign b_resp_exp = ((mawtrk_bid_hit[0]) ? maw_fifo0_out[10:8] : 3'b000) |
((mawtrk_bid_hit[1]) ? maw_fifo1_out[10:8] : 3'b000) |
((mawtrk_bid_hit[2]) ? maw_fifo2_out[10:8] : 3'b000) |
((mawtrk_bid_hit[3]) ? maw_fifo3_out[10:8] : 3'b000);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_M_W1_OOO_F_NO
assign b_resp_exp = ((mawtrk_bid_hit[0]) ? maw_fifo0_out[10:8] : 3'b000) ;
end
endgenerate
wire [2:0] b_resp_mask =
((bresp_m_ff[1:0] == 2'b00) ? 3'b001 : 3'b000) |
((bresp_m_ff[1:0] == 2'b01) ? 3'b010 : 3'b000) |
((bresp_m_ff[1] == 1'b1) ? 3'b100 : 3'b000);
wire [2:0] b_resp_allowed = (b_resp_exp[2:0] == 3'b000) ? 3'b001 : b_resp_exp[2:0];
wire b_resp_ok = ((b_resp_mask[2:0] & b_resp_allowed[2:0]) != 3'b000);
assign b_resp_bad = b_complete_ff && ~b_resp_ok;
wire b_resp_unexp = b_complete_ff & (mawtrk_bid_hit[3:0] == 4'h0);
always @(posedge Clk) begin
b_complete_ff <= (rst_l) ? b_complete : 1'b0;
b_resp_unexp_ff <= (rst_l) ? b_resp_unexp : 1'b0;
b_resp_bad_ff <= (rst_l) ? b_resp_bad : 1'b0;
bid_m_ff[C_M_AXI_THREAD_ID_WIDTH-1:0] <= (rst_l) ?
bid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] : 1'b0;
bresp_m_ff[1:0] <= (rst_l) ? bresp_m[1:0] : 2'b00;
end
assign bready_m = ~(b_complete_ff); //toggle bready for every bvalid match.
//cannot accept
//continuous bvalid
// MASTER complete logic
wire [15:0] maw_fifo0_tag_exp = (maw_fifo0_pop) ?
(16'h1 << maw_fifo0_out[15:12]) : 16'h0;
wire [15:0] maw_fifo1_tag_exp = (maw_fifo1_pop) ?
(16'h1 << maw_fifo1_out[15:12]) : 16'h0;
wire [15:0] maw_fifo2_tag_exp = (maw_fifo2_pop) ?
(16'h1 << maw_fifo2_out[15:12]) : 16'h0;
wire [15:0] maw_fifo3_tag_exp = (maw_fifo3_pop) ?
(16'h1 << maw_fifo3_out[15:12]) : 16'h0;
assign maw_complete_next2 = (16'h1 << mwr_complete_ptr_ff[3:0]);
assign maw_complete_inc_exp = maw_complete_next2[15:0] &
maw_complete_vec_ff[15:0];
assign maw_complete_doinc = (maw_complete_inc_exp[15:0] != 16'h0);
wire [15:0] maw_complete_vec = ~maw_complete_inc_exp[15:0] &
(maw_fifo0_tag_exp[15:0] | maw_fifo1_tag_exp[15:0] |
maw_fifo2_tag_exp[15:0] | maw_fifo3_tag_exp[15:0] |
maw_complete_vec_ff[15:0]);
assign maw_fifo0_user_disableincr = (maw_fifo0_pop) ?
maw_fifo0_out[20] : 1'h0;
wire maw_fifo1_user_disableincr = (maw_fifo1_pop) ?
maw_fifo1_out[20] : 1'h0;
wire maw_fifo2_user_disableincr = (maw_fifo2_pop) ?
maw_fifo2_out[20] : 1'h0;
wire maw_fifo3_user_disableincr = (maw_fifo3_pop) ?
maw_fifo3_out[20] : 1'h0;
assign maw_disableincr = maw_fifo0_user_disableincr |
maw_fifo1_user_disableincr |
maw_fifo2_user_disableincr |
maw_fifo3_user_disableincr;
// using disableincr bit that is tracked for parameterized mode
// CR#768069: Reset complete_ptr when current value equal to latched command
// index.
wire rst_complete_ptr = (last_cmd_index[8:0] == mwr_complete_ptr_ff ) ;//& reg0_loop_en_ff;
assign mwr_complete_ptr = ((~reg0_m_enable_ff)|(rst_complete_ptr)) ? 9'h0 :
((maw_complete_doinc & ~maw_disableincr_ff) ?
mwr_complete_ptr_ff[8:0] + 9'h1 :
mwr_complete_ptr_ff[8:0]);
//dec_ptr: pulse when command command pointer is incremented.
assign dec_ptr = maw_complete_doinc & ~maw_disableincr_ff;
assign mw_done = (reg0_m_enable_ff && maw_done_ff && (mwr_complete_ptr[8:0] == reg0_mw_ptr_ff[8:0]))? 1'b1 :
((~reg0_m_enable_ff)?1'b0:mw_done_ff);
always @(posedge Clk) begin
maw_disableincr_ff <= (rst_l) ? maw_disableincr : 1'h0;
mwr_complete_ptr_ff[8:0] <= (rst_l) ? mwr_complete_ptr[8:0] : 9'h0;
maw_complete_vec_ff[15:0] <= (rst_l) ? maw_complete_vec[15:0] : 16'h0;
mw_done_ff <= (rst_l) ? mw_done : 1'b0;
end
endmodule
|
module compressor2(a,b,s,c);
parameter width = 0;
input [width-1:0] a;
input [width-1:0] b;
output [width-1:0] s;
output [width-1:0] c;
assign s = a ^ b;
assign c = a & b;
endmodule // compressor2
module counter(clk,ld,nb,dn);
parameter width = 0;
input clk;
input ld;
input [width-1:0] nb;
output dn;
reg [width-2:0] sp;
reg [width-1:0] cp;
reg dp;
wire [width-2:0] sq;
wire [width-1:0] cq;
wire dq;
wire [width-2:0] sr;
wire [width-1:0] cr;
compressor2
#(.width (width-1))
advance
(.a (sp),
.b (cp[width-2:0]),
.s (sq),
.c (cq[width-1:1]));
assign cq[0] = ~cp[0];
assign dq = dp | cp[width-1];
assign sr = ld ? nb[width-1:1] : sq;
assign cr[0] = ld ? nb[0] : cq[0];
assign cr[width-1:1] = ld ? {(width-1) {1'b0}} : cq[width-1:1];
assign dn = ld ? 1'b0 : dq;
always @(posedge clk)
begin
sp <= sr;
cp <= cr;
dp <= dn;
end
endmodule // counter
module main;
parameter delay = 10;
parameter width = 5;
reg clk;
reg inp;
reg [width-1:0] nb;
wire out;
counter
#(.width (width))
root
(.clk (clk),
.ld (inp),
.nb (nb),
.dn (out));
initial
begin
$display("+------------------------+");
$display("| Test bench for counter |");
$display("+------------------------+");
$monitor("ld = %b, sr = %d, cr = %d, dn = %b",
root.ld, root.sr, root.cr, root.dn);
clk = 0;
repeat(10) @(posedge clk);
nb = {width {1'b0}} - (delay + 1 - width);
inp = 1;
@(posedge clk);
inp = 0;
repeat(delay-1) @(posedge clk);
if (out)
begin
$display("ERROR: counter finished too soon");
end
@(posedge clk);
if (!out)
begin
$display("ERROR: counter did not finish on time");
end
repeat(5) @(posedge clk);
$monitoroff;
$display("Test complete at time %0t.", $time);
$finish;
end
always
#5 clk = !clk;
endmodule // main
|
/* Problem # 18 */
module Control_Unit(output reg done, Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR,
input reset_b, start, AR_gt_0, AR_lt_0, clk);
always @(posedge clk) begin
if (start) begin
Ld_AR_BR = 1;
Mul_BR_x2_CR = 0;
Div_AR_x2_CR = 0;
Clr_CR = 0;
done = 0;
end else begin
if (AR_gt_0) begin
Ld_AR_BR = 0;
Mul_BR_x2_CR = 1;
Div_AR_x2_CR = 0;
Clr_CR = 0;
done = 1;
end else if (AR_lt_0) begin
Ld_AR_BR = 0;
Mul_BR_x2_CR = 0;
Div_AR_x2_CR = 1;
Clr_CR = 0;
done = 1;
end else begin
Ld_AR_BR = 0;
Mul_BR_x2_CR = 0;
Div_AR_x2_CR = 0;
Clr_CR = 1;
done = 1;
end
end
end
always @(reset_b)
if (reset_b == 0) begin
Ld_AR_BR = 0;
Mul_BR_x2_CR = 0;
Div_AR_x2_CR = 0;
Clr_CR = 0;
done = 0;
end
endmodule
module Datapath_Unit(output reg signed[15:0] CR, output reg AR_gt_0, AR_lt_0,
input [15:0] Data_AR, Data_BR,
input Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR, clk);
reg signed [15:0] AR;
reg signed [15:0] BR;
always @(AR) begin
AR_lt_0 = (AR < 0);
AR_gt_0 = (AR > 0);
end
always @(negedge clk) begin
if (Ld_AR_BR) begin
AR = Data_AR;
BR = Data_BR;
end else if (Div_AR_x2_CR) begin
CR = AR / 2;
end else if (Mul_BR_x2_CR) begin
CR = BR * 2;
end else if (Clr_CR) begin
CR = 0;
end
end
endmodule
module tb();
/* Outputs */
wire [15:0] CR;
wire done;
/* Interconnects */
wire AR_gt_0, AR_lt_0;
wire Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR;
/* Inputs */
reg clk;
reg [15:0] Data_BR, Data_AR;
reg reset_b;
reg start;
Datapath_Unit ddev (CR, AR_gt_0, AR_lt_0, Data_AR, Data_BR,
Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR, clk);
Control_Unit cdev(done, Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR,
reset_b, start, AR_gt_0, AR_lt_0, clk);
reg [35:0] i;
initial begin
$dumpfile("p18.vcd");
$dumpvars(0,tb);
clk = 0;
reset_b = 0;
#2 reset_b = 1;
for(i = 0; i < 2**32-1; i = i + 2**31-1) begin
Data_BR = i[15:0];
Data_AR = i[31:16];
start = 1;
#10 clk = 1;
#5 start = 0;
#5 clk = 0;
while(~done) begin
#10 clk = 1;
#10 clk = 0;
end
end
#20 $finish;
end
endmodule
|
module prometheus_fx3_ZLP(
input rst_n,
input clk_100,
input zlp_mode_selected,
input i_gpif_in_ch0_rdy_d,
input i_gpif_out_ch0_rdy_d,
output o_gpif_we_n_zlp_,
output o_gpif_pkt_end_n_zlp_,
output [31:0] data_out_zlp
);
reg [2:0]current_zlp_state;
reg [2:0]next_zlp_state;
//parameters for ZLP mode state machine
parameter [2:0] zlp_idle = 3'd0;
parameter [2:0] zlp_wait_flagb = 3'd1;
parameter [2:0] zlp_write = 3'd2;
parameter [2:0] zlp_write_wr_delay = 3'd3;
parameter [2:0] zlp_wait = 3'd4;
reg [3:0]strob_cnt;
reg strob;
reg [31:0]data_gen_zlp;
reg o_gpif_pkt_end_n_;
assign o_gpif_we_n_zlp_ = ((current_zlp_state == zlp_write) && (i_gpif_out_ch0_rdy_d == 1'b1)) ? 1'b0 : 1'b1;
//counter to generate the strob for ZLP data pkts
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
strob_cnt <= 4'd0;
end else if(current_zlp_state == zlp_idle)begin
strob_cnt <= 4'd0;
end else if(current_zlp_state == zlp_wait)begin
strob_cnt <= strob_cnt + 1'b1;
end
end
//Strob logic
always@(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
strob <= 1'b0;
end else if((current_zlp_state == zlp_wait) && (strob_cnt == 4'b0111)) begin
strob <= !strob;
end
end
always@(*)begin
if(zlp_mode_selected & (strob_cnt == 4'b0011) & (strob == 1'b1))begin
o_gpif_pkt_end_n_ = 1'b0;
end else begin
o_gpif_pkt_end_n_ = 1'b1;
end
end
assign o_gpif_pkt_end_n_zlp_ = o_gpif_pkt_end_n_;
//ZLP mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_zlp_state <= zlp_idle;
end else begin
current_zlp_state <= next_zlp_state;
end
end
//ZLP mode state machine combo
always@(*)begin
next_zlp_state = current_zlp_state;
case(current_zlp_state)
zlp_idle:begin
if((zlp_mode_selected) & (i_gpif_in_ch0_rdy_d == 1'b1))begin
next_zlp_state = zlp_wait_flagb;
end else begin
next_zlp_state = zlp_idle;
end
end
zlp_wait_flagb :begin
if((strob == 1'b1) & (i_gpif_out_ch0_rdy_d == 1'b1))begin
next_zlp_state = zlp_wait;
end else if ((i_gpif_out_ch0_rdy_d == 1'b1) && (strob == 1'b0))begin
next_zlp_state = zlp_write;
end else begin
next_zlp_state = zlp_wait_flagb;
end
end
zlp_write:begin
if(i_gpif_out_ch0_rdy_d == 1'b0)begin
next_zlp_state = zlp_write_wr_delay;
end else begin
next_zlp_state = zlp_write;
end
end
zlp_write_wr_delay:begin
next_zlp_state = zlp_wait;
end
zlp_wait:begin
if(strob_cnt == 4'b1111)begin
next_zlp_state = zlp_idle;
end else begin
next_zlp_state = zlp_wait;
end
end
endcase
end
//data generator counter for zlp mode
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
data_gen_zlp <= 32'd0;
end else if((o_gpif_we_n_zlp_ == 1'b0) & (zlp_mode_selected)) begin
data_gen_zlp <= data_gen_zlp + 1;
end else if (!zlp_mode_selected) begin
data_gen_zlp <= 32'd0;
end
end
assign data_out_zlp = data_gen_zlp;
endmodule
|
//reads ram and displays on vga monitor
module vga_sram(CLOCK_PX ,rst,VGA_R, VGA_G, VGA_B,VGA_HS, VGA_VS,VGA_SYNC, VGA_BLANK,FB_ADDR,fb_data,we_nIN);
input CLOCK_PX,rst;
//reg [7:0]fb_data_reg;
input we_nIN;
input [7:0] fb_data;
output VGA_BLANK, VGA_SYNC, VGA_HS, VGA_VS;
output [7:0] VGA_R, VGA_G, VGA_B;
output [18:0] FB_ADDR;
reg [7:0] VGA_R, VGA_G, VGA_B;
reg VGA_HS, VGA_VS, h_blank, v_blank, status;
reg [31:0] pixelcount, linecount;
reg red_value;
reg [9:0] rdaddress;
reg [9:0] wraddress;
reg [18:0] FB_ADDR;
reg [7:0] Rdata, Bdata;
reg UBwe, LBwe;
wire CLOCK_PX,we_nIN;
wire VGA_BLANK, VGA_SYNC;
wire [7:0] Rq,Bq, gray;
// VGA parameters 640 x 480
// horizontal
//parameter H_FRONT = 16;
//parameter H_SYNC = 96;
//parameter H_BACK = 48;
//parameter H_ACT = 640;
//parameter H_BLANK = H_FRONT + H_SYNC + H_BACK;
//parameter H_TOTAL = H_FRONT + H_SYNC + H_BACK + H_ACT;
//
//// vertical
//parameter V_FRONT = 10;
//parameter V_SYNC = 2;
//parameter V_BACK = 33;
//parameter V_ACT = 480;
//parameter V_BLANK = V_FRONT + V_SYNC + V_BACK;
//parameter V_TOTAL = V_FRONT + V_SYNC + V_BACK + V_ACT;
// Horizontal Parameter
parameter H_FRONT = 16;
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 11;
parameter V_SYNC = 2;
parameter V_BACK = 31;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
// VGA parameters 1280 x 1024
// horizontal
//parameter H_FRONT = 48;
//parameter H_SYNC = 112;
//parameter H_BACK = 248;
//parameter H_ACT = 1280;
//parameter H_BLANK = H_FRONT + H_SYNC + H_BACK;
//parameter H_TOTAL = H_FRONT + H_SYNC + H_BACK + H_ACT;
//
//// vertical
//parameter V_FRONT = 1;
//parameter V_SYNC = 3;
//parameter V_BACK = 38;
//parameter V_ACT = 1024;
//parameter V_BLANK = V_FRONT + V_SYNC + V_BACK;
//parameter V_TOTAL = V_FRONT + V_SYNC + V_BACK + V_ACT;
parameter FB_SIZE = V_ACT * H_ACT;
`define fb_addr_size 19
// parameters to force a square image
parameter SH_ACT = 0;//V_ACT; // make the horizontal resolution the same as the vertical resolution
parameter S_FILLER = 0;//SH_ACT/2;
//vga pin assigns
assign VGA_SYNC = 1'b1,//VGA_HS || VGA_VS,
VGA_BLANK = h_blank || v_blank;
//sram pin assigns
//assign ce_n=1'b0,//the chip is always selected
// oe_n=1'b0,//dont car in write state, 0 in read state
// ub_n=1'b0,//the upper byte [15:8] will be read/writed each read/write command
// lb_n=1'b0;//the lower byte [7:0] will be read/writed each read/write command
//rgb2gray r2g( Rdata, 8'd0, Bdata,gray);
//linebuffer ram rdclock wrclock
//linebuffer red(gray,rdaddress,CLOCK_PX,wraddress,CLOCK_PX,LBwe,Rq);
//linebuffer blue(gray,rdaddress,CLOCK_PX,wraddress,CLOCK_PX,UBwe,Bq);
linebuffer red(Rdata,rdaddress,CLOCK_PX,wraddress,CLOCK_PX,LBwe,Rq);// only need one channel for grayscale
//linebuffer blue(Bdata,rdaddress,CLOCK_PX,wraddress,CLOCK_PX,UBwe,Bq);
// pixel counter and line counter
always@(posedge CLOCK_PX or negedge rst)
begin
if (rst==1'b0)
begin
pixelcount<=32'd0;
linecount<=32'd0;
end
else
if(we_nIN==1'b1)
if (pixelcount>H_TOTAL)
begin
pixelcount<=32'd0;
if (linecount>V_TOTAL)
linecount<=32'd0;
else
linecount<= linecount+1;
end
else
pixelcount<= pixelcount+1;
else
begin
pixelcount<=32'd0;
linecount<=32'd0;
end
end
//horizontal outputs
always@(posedge CLOCK_PX or negedge rst)
begin
if (rst == 1'b0)
begin
VGA_HS<=1'b0;
h_blank<=1'b1;
VGA_R<=8'h00;
VGA_G<=8'h00;
VGA_B<=8'h00;
rdaddress<=10'b0000000100;
end
else
begin
//HSYNC
if (pixelcount< H_SYNC)
VGA_HS<=1'b0;
else
VGA_HS<=1'b1;
//Back porch and Front porch
// if ((pixelcount>=H_SYNC && pixelcount<(H_SYNC+H_BACK))|| (pixelcount>=(H_SYNC+H_BACK+H_ACT)))
if (pixelcount < H_BLANK)
h_blank<=1'b0;
else
h_blank<=1'b1;
// horizontal visible area
//if (pixelcount>(H_SYNC+H_BACK) && pixelcount<H_SYNC+H_BACK+H_ACT)
//change to make a square 1024x1024 //<=
if (linecount>=(V_BACK+V_SYNC) &&
linecount<(V_BACK+V_SYNC+V_ACT) &&
pixelcount>=(H_BACK+H_SYNC/*+S_FILLER*/) &&
pixelcount<(H_BACK+H_SYNC+H_ACT/*-S_FILLER*/) &&
we_nIN==1'b1)
begin
//read linebuffer
//VGA_R<=8'h00;
VGA_R<=Rq;//Rq and Bq should be equal and grayscale
VGA_G<=Rq;
VGA_B<=Rq;//Bq;
//incriment LB addr
rdaddress<=rdaddress+10'd1;
end
else
begin
//dont read frame buffer
//included to remove infered latch
VGA_R<=8'h00;
VGA_G<=8'h00;
VGA_B<=8'h00;
// rdaddress<=rdaddress;
rdaddress <= 10'd0;
end
end// end else rst
end//always
// vertical outputs
always@(posedge CLOCK_PX or negedge rst)
begin
if (rst ==1'b0)
begin
VGA_VS<=1'b0;
v_blank <= 1'b0;
end
else
begin
//vsync
if (linecount<V_SYNC)
VGA_VS<=1'b0;
else
VGA_VS <= 1'b1;
// Back porch or front porch
//if ((linecount >=V_SYNC && linecount<(V_BACK+V_SYNC))|| linecount>=(V_BACK+V_SYNC+V_ACT))
if (linecount < V_BLANK )
v_blank<=1'b1;
else
v_blank <= 1'b0;
//vertical visible area
// nothing else needs to be done
//linecount >= 32'd29 && linecount< 32'd629
end// end rst else
end
//fill line buffer
always@(posedge CLOCK_PX or negedge rst)
begin
if(rst==1'b0)
begin
wraddress<=10'd0;
FB_ADDR<=`fb_addr_size'd0;
end
else
// fill line buffer in the first 1024 pixels of row (only on visible rows) \/ is this right?
// commented out part that makes screen square
if(linecount>=(V_SYNC+V_BACK)&&linecount<(V_SYNC+V_BACK+V_ACT)&&pixelcount<H_ACT&&we_nIN==1'b1)
begin
Rdata<=fb_data;
//Bdata<=fb_data;// only need one channel for grayscale
//incriment on-chip ram address
wraddress<=wraddress+10'd1;
//incriment sram address
if(FB_ADDR >= FB_SIZE) begin
FB_ADDR <= `fb_addr_size'd0;// FB_ADDR might be less than 20 bits
end else begin
FB_ADDR<=FB_ADDR+`fb_addr_size'd1;
end
//enable writing to on chip rams
UBwe<=1'b1;
LBwe<=1'b1;
end
else
begin
//disable writing to on chip rams
UBwe<=1'b0;
LBwe<=1'b0;
wraddress <= 10'd0;
end
end//always
endmodule |
// DESCRIPTION: Verilator: Check initialisation of cloned clock variables
//
// This tests issue 1327 (Strange initialisation behaviour with
// "VinpClk" cloned clock variables)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Rupert Swarbrick (Argon Design).
// bug1327
// This models some device under test with an asynchronous reset pin
// which counts to 15.
module dut (input wire clk,
input wire rst_n,
output wire done);
reg [3:0] counter;
always @(posedge clk or negedge rst_n) begin
if (rst_n & ! clk) begin
$display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.",
$time, clk, rst_n);
$stop;
end
if (! rst_n) begin
counter <= 4'd0;
end else begin
counter <= counter < 4'd15 ? counter + 4'd1 : counter;
end
end
assign done = rst_n & (counter == 4'd15);
endmodule
module t(input wire clk,
input wire rst_n);
wire dut_done;
// A small FSM for driving the test
//
// This is just designed to be enough to force Verilator to make a
// "VinpClk" variant of dut_rst_n.
// Possible states:
//
// 0: Device in reset
// 1: Device running
// 2: Device finished
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (! rst_n) begin
state <= 0;
end else begin
if (state == 2'd0) begin
// One clock after resetting the device, we switch to running
// it.
state <= 2'd1;
end
else if (state == 2'd1) begin
// If the device is running, we switch to finished when its
// done signal goes high.
state <= dut_done ? 2'd2 : 2'd1;
end
else begin
// If the dut has finished, the test is done.
$write("*-* All Finished *-*\n");
$finish;
end
end
end
wire dut_rst_n = rst_n & (state != 0);
wire done;
dut dut_i (.clk (clk),
.rst_n (dut_rst_n),
.done (dut_done));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_4_V
`define SKY130_FD_SC_HDLL__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_TB_V
`define SKY130_FD_SC_LP__DLXTP_TB_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__dlxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011-2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Receive HDMI, hdmi embedded syncs data in, video dma data out.
module axi_hdmi_rx_core (
// hdmi interface
hdmi_clk,
hdmi_data,
hdmi_hs_count_mismatch, // indicates receive hs mismatch against programmed
hdmi_hs_count_update, // high for one hdmi_clk cycle when count and count_mismatch are update
hdmi_hs_count, // received hs count
hdmi_vs_count_mismatch, // indicates receive vs mismatch against programmed
hdmi_vs_count_update, // high for one hdmi_clk cycle when count and count_mismatch are update
hdmi_vs_count, // received vs count
hdmi_tpm_oos, // test pattern monitor out of sync
hdmi_oos_hs, // horizontal HDMI receive resolution mismatch against programmed
hdmi_oos_vs, // vertical HDMI receive resolution mismatch against programmed
hdmi_wr, // write interface
hdmi_wdata,
// processor interface
hdmi_up_enable,
hdmi_up_edge_sel,
hdmi_up_hs_count,
hdmi_up_vs_count,
hdmi_up_csc_bypass,
hdmi_up_tpg_enable,
hdmi_up_packed,
hdmi_up_bgr,
// debug interface (chipscope)
debug_data,
debug_trigger);
// hdmi interface
input hdmi_clk;
input [15:0] hdmi_data;
output hdmi_hs_count_mismatch;
output hdmi_hs_count_update;
output [15:0] hdmi_hs_count;
output hdmi_vs_count_mismatch;
output hdmi_vs_count_update;
output [15:0] hdmi_vs_count;
output hdmi_tpm_oos;
output hdmi_oos_hs;
output hdmi_oos_vs;
output hdmi_wr;
output [64:0] hdmi_wdata;
// control interface
input hdmi_up_enable;
input hdmi_up_edge_sel;
input [15:0] hdmi_up_hs_count;
input [15:0] hdmi_up_vs_count;
input hdmi_up_csc_bypass;
input hdmi_up_tpg_enable;
input hdmi_up_packed;
input hdmi_up_bgr;
// debug interface (chipscope)
output [61:0] debug_data;
output [ 7:0] debug_trigger;
reg hdmi_wr = 'd0;
reg [64:0] hdmi_wdata = 'd0;
reg [23:0] hdmi_tpm_data = 'd0;
reg hdmi_tpm_oos = 'd0;
reg hdmi_fs_422 = 'd0;
reg hdmi_de_422 = 'd0;
reg [15:0] hdmi_data_422 = 'd0;
reg hdmi_fs_444 = 'd0;
reg hdmi_de_444 = 'd0;
reg [23:0] hdmi_data_444 = 'd0;
reg hdmi_fs_444_d = 'd0;
reg hdmi_de_444_d = 'd0;
reg [23:0] hdmi_data_444_d = 'd0;
reg [23:0] hdmi_data_444_2d = 'd0;
reg [23:0] hdmi_data_444_3d = 'd0;
reg hdmi_oos_hs = 'd0;
reg hdmi_oos_vs = 'd0;
reg hdmi_sof = 'd0;
reg hdmi_hs_de_d = 'd0;
reg hdmi_vs_de_d = 'd0;
reg [15:0] hdmi_hs_run_count = 'd0;
reg [15:0] hdmi_vs_run_count = 'd0;
reg hdmi_hs_count_mismatch = 'd0;
reg hdmi_hs_count_update = 'd0;
reg [15:0] hdmi_hs_count = 'd0;
reg hdmi_vs_count_mismatch = 'd0;
reg hdmi_vs_count_update = 'd0;
reg [15:0] hdmi_vs_count = 'd0;
reg hdmi_enable = 'd0;
reg [15:0] hdmi_data_neg_p = 'd0;
reg [15:0] hdmi_data_pos_p = 'd0;
reg [15:0] hdmi_data_p = 'd0;
reg [15:0] hdmi_data_neg = 'd0;
reg [ 2:0] hdmi_wr_count = 'd0;
wire hdmi_tpm_mismatch_s;
wire [15:0] hdmi_tpm_data_s;
wire hdmi_sof_s;
wire hdmi_oos_hs_s;
wire hdmi_oos_vs_s;
wire hdmi_fs_444_s;
wire hdmi_de_444_s;
wire [23:0] hdmi_data_444_s;
wire ss_fs_s;
wire ss_de_s;
wire [23:0] ss_data_s;
wire [15:0] hdmi_data_de;
wire hdmi_hs_de;
wire hdmi_vs_de;
// debug signals
assign debug_data[61:61] = hdmi_tpm_oos;
assign debug_data[60:60] = hdmi_tpm_mismatch_s;
assign debug_data[59:59] = hdmi_de_422;
assign debug_data[58:43] = hdmi_data_422;
assign debug_data[42:42] = hdmi_oos_hs | hdmi_oos_vs;
assign debug_data[41:41] = hdmi_sof;
assign debug_data[40:40] = hdmi_hs_count_mismatch;
assign debug_data[39:39] = hdmi_vs_count_mismatch;
assign debug_data[38:38] = hdmi_enable;
assign debug_data[37:37] = hdmi_vs_de;
assign debug_data[36:36] = hdmi_hs_de;
assign debug_data[35:20] = hdmi_data_de;
assign debug_data[15: 0] = hdmi_data_p;
assign debug_trigger[7] = hdmi_tpm_mismatch_s;
assign debug_trigger[6] = hdmi_tpm_oos;
assign debug_trigger[5] = hdmi_enable;
assign debug_trigger[4] = hdmi_hs_de;
assign debug_trigger[3] = hdmi_vs_de;
assign debug_trigger[2] = hdmi_sof;
always @(posedge hdmi_clk) begin
if (hdmi_de_444_d == 1'b1)
hdmi_wr_count <= hdmi_wr_count + 1'b1;
else
hdmi_wr_count <= 3'b0;
if (hdmi_up_packed == 1'b0) begin
hdmi_wr <= hdmi_wr_count[0];
hdmi_wdata[63:32] <= {8'hff,hdmi_data_444_d[23:0]};
hdmi_wdata[31:0] <= hdmi_wdata[63:32];
end else begin
if (hdmi_up_csc_bypass) begin
hdmi_wr <= hdmi_wr_count[1] & hdmi_wr_count[0];
hdmi_wdata[63:48] <= hdmi_data_444_d[15:0];
hdmi_wdata[47:0] <= hdmi_wdata[63:16];
end else begin
hdmi_wr <= 1'b0;
case(hdmi_wr_count)
3'h1: begin
hdmi_wdata[23:0] <= hdmi_data_444_2d;
hdmi_wdata[47:24] <= hdmi_data_444_d;
hdmi_wdata[63:48] <= hdmi_data_444[15:0];
end
3'h2: begin
hdmi_wr <= 1'b1;
end
3'h4: begin
hdmi_wdata[7:0] <= hdmi_data_444_3d[23:16];
hdmi_wdata[31:8] <= hdmi_data_444_2d;
hdmi_wdata[55:32] <= hdmi_data_444_d;
hdmi_wdata[63:56] <= hdmi_data_444[7:0];
end
3'h5: begin
hdmi_wr <= 1'b1;
end
3'h6: begin
hdmi_wdata[15:0] <= hdmi_data_444_2d[23:8];
hdmi_wdata[39:16] <= hdmi_data_444_d;
hdmi_wdata[63:40] <= hdmi_data_444;
end
3'h7: begin
hdmi_wr <= 1'b1;
end
endcase
end
end
if (hdmi_fs_444)
hdmi_wdata[64:64] <= 1'b1;
else if (hdmi_wr)
hdmi_wdata[64:64] <= 1'b0;
end
// TPM on 422 data (the data must be passed through the cable as it is transmitted
// by the v2h module. Any csc conversions must be disabled on info frame
assign hdmi_tpm_mismatch_s = (hdmi_data_422 == hdmi_tpm_data_s) ? 1'b0 : hdmi_de_422;
assign hdmi_tpm_data_s = {hdmi_tpm_data[3:2], 6'h20, hdmi_tpm_data[1:0], 6'h20};
always @(posedge hdmi_clk) begin
if (hdmi_fs_422 == 1'b1) begin
hdmi_tpm_data <= 'd0;
end else if (hdmi_de_422 == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
end
hdmi_tpm_oos <= hdmi_tpm_mismatch_s;
end
// fs, enable and data on 422 and 444 domains
always @(posedge hdmi_clk) begin
hdmi_fs_422 <= hdmi_sof & hdmi_enable;
hdmi_de_422 <= hdmi_hs_de & hdmi_vs_de & hdmi_enable;
hdmi_data_422 <= hdmi_data_de;
hdmi_fs_444_d <= hdmi_fs_444;
hdmi_de_444_d <= hdmi_de_444;
hdmi_data_444_d <= hdmi_data_444;
hdmi_data_444_2d <= hdmi_data_444_d;
hdmi_data_444_3d <= hdmi_data_444_2d;
end
// Select output data depending on the control setting
always @(posedge hdmi_clk) begin
if (hdmi_up_csc_bypass == 1'b1) begin
hdmi_fs_444 <= hdmi_fs_422;
hdmi_de_444 <= hdmi_de_422;
end else begin
hdmi_fs_444 <= hdmi_fs_444_s;
hdmi_de_444 <= hdmi_de_444_s;
end
if (hdmi_up_tpg_enable == 1'b1) begin
hdmi_data_444 <= hdmi_tpm_data;
end else if (hdmi_up_csc_bypass == 1'b1) begin
hdmi_data_444 <= {8'd0, hdmi_data_422};
end else if (hdmi_up_bgr == 1'b1) begin
hdmi_data_444 <= {hdmi_data_444_s[7:0], hdmi_data_444_s[15:8], hdmi_data_444_s[23:16]};
end else begin
hdmi_data_444 <= hdmi_data_444_s;
end
end
// start of frame
assign hdmi_sof_s = hdmi_vs_de & ~hdmi_vs_de_d;
assign hdmi_oos_hs_s = hdmi_hs_count == hdmi_up_hs_count ? hdmi_hs_count_mismatch : 1'b1;
assign hdmi_oos_vs_s = hdmi_vs_count == hdmi_up_vs_count ? hdmi_vs_count_mismatch : 1'b1;
// hdmi side of the interface, horizontal and vertical sync counters.
// capture active video size and report mismatch
always @(posedge hdmi_clk) begin
hdmi_oos_hs <= hdmi_oos_hs_s;
hdmi_oos_vs <= hdmi_oos_vs_s;
hdmi_sof <= hdmi_sof_s;
hdmi_hs_de_d <= hdmi_hs_de;
hdmi_vs_de_d <= hdmi_vs_de;
if ((hdmi_hs_de == 1'b1) && (hdmi_hs_de_d == 1'b0)) begin
hdmi_hs_run_count <= 'd1;
end else if (hdmi_hs_de == 1'b1) begin
hdmi_hs_run_count <= hdmi_hs_run_count + 1'b1;
end
if ((hdmi_vs_de == 1'b1) && (hdmi_vs_de_d == 1'b0)) begin
hdmi_vs_run_count <= 'd0;
end else if ((hdmi_vs_de == 1'b1) && (hdmi_hs_de == 1'b1) && (hdmi_hs_de_d == 1'b0)) begin
hdmi_vs_run_count <= hdmi_vs_run_count + 1'b1;
end
if ((hdmi_hs_de == 1'b0) && (hdmi_hs_de_d == 1'b1)) begin
hdmi_hs_count_mismatch <= (hdmi_hs_count == hdmi_hs_run_count) ? 1'b0 : 1'b1;
hdmi_hs_count <= hdmi_hs_run_count;
hdmi_hs_count_update <= 1'b1;
end else begin
hdmi_hs_count_update <= 1'b0;
end
if ((hdmi_vs_de == 1'b0) && (hdmi_vs_de_d == 1'b1)) begin
hdmi_vs_count_mismatch <= (hdmi_vs_count == hdmi_vs_run_count) ? 1'b0 : 1'b1;
hdmi_vs_count <= hdmi_vs_run_count;
hdmi_vs_count_update <= 1'b1;
end else begin
hdmi_vs_count_update <= 1'b0;
end
if (hdmi_sof_s == 1'b1) begin
hdmi_enable <= hdmi_up_enable & ~hdmi_oos_hs_s & ~hdmi_oos_vs_s;
end
end
// hdmi input data registers
always @(posedge hdmi_clk) begin
hdmi_data_neg_p <= hdmi_data_neg;
hdmi_data_pos_p <= hdmi_data;
if (hdmi_up_edge_sel == 1'b1) begin
hdmi_data_p <= hdmi_data_neg_p;
end else begin
hdmi_data_p <= hdmi_data_pos_p;
end
end
always @(negedge hdmi_clk) begin
hdmi_data_neg <= hdmi_data;
end
embedded_sync_decoder es_decoder (
.clk (hdmi_clk),
.data_in (hdmi_data_p),
.hs_de (hdmi_hs_de),
.vs_de (hdmi_vs_de),
.data_out (hdmi_data_de)
);
// super sampling, 422 to 444
ad_ss_422to444 #(
.Cr_Cb_N(0),
.DELAY_DATA_WIDTH(2)
) i_ss (
.clk (hdmi_clk),
.s422_de (hdmi_de_422),
.s422_sync ({hdmi_fs_422,hdmi_de_422}),
.s422_data (hdmi_data_422),
.s444_sync ({ss_fs_s,ss_de_s}),
.s444_data (ss_data_s)
);
// color space conversion, CrYCb to RGB
ad_csc_CrYCb2RGB #(
.DELAY_DATA_WIDTH(2)
) i_csc (
.clk (hdmi_clk),
.CrYCb_sync ({ss_fs_s, ss_de_s}),
.CrYCb_data (ss_data_s),
.RGB_sync ({hdmi_fs_444_s, hdmi_de_444_s}),
.RGB_data (hdmi_data_444_s)
);
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_SYMBOL_V
`define SKY130_FD_SC_LP__O21BA_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_SYMBOL_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Tue Oct 18 17:47:49 2016
// Host : chinook.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
// Command : write_verilog -force -mode funcsim
// /afs/ece.cmu.edu/usr/jacobwei/Public/FPGA/FPGA.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_funcsim.v
// Design : blk_mem_gen_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "blk_mem_gen_0,blk_mem_gen_v8_2,{}" *) (* core_generation_info = "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=4,C_READ_WIDTH_A=4,C_WRITE_DEPTH_A=307200,C_READ_DEPTH_A=307200,C_ADDRA_WIDTH=19,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=4,C_READ_WIDTH_B=4,C_WRITE_DEPTH_B=307200,C_READ_DEPTH_B=307200,C_ADDRB_WIDTH=19,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=36,C_COUNT_18K_BRAM=3,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.198881 mW}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
(* NotValidForBitStream *)
module blk_mem_gen_0
(clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [18:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [3:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [18:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [3:0]doutb;
wire [18:0]addra;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [3:0]dina;
wire [3:0]doutb;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [3:0]NLW_U0_douta_UNCONNECTED;
wire [18:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [18:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "19" *)
(* C_ADDRB_WIDTH = "19" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "3" *)
(* C_COUNT_36K_BRAM = "36" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 16.198881 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "blk_mem_gen_0.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "1" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "307200" *)
(* C_READ_DEPTH_B = "307200" *)
(* C_READ_WIDTH_A = "4" *)
(* C_READ_WIDTH_B = "4" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "307200" *)
(* C_WRITE_DEPTH_B = "307200" *)
(* C_WRITE_MODE_A = "NO_CHANGE" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "4" *)
(* C_WRITE_WIDTH_B = "4" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
blk_mem_gen_0_blk_mem_gen_v8_2 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0}),
.douta(NLW_U0_douta_UNCONNECTED[3:0]),
.doutb(doutb),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[18:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[18:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[3:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module blk_mem_gen_0_blk_mem_gen_generic_cstr
(doutb,
addra,
wea,
addrb,
clka,
clkb,
dina);
output [3:0]doutb;
input [18:0]addra;
input [0:0]wea;
input [18:0]addrb;
input clka;
input clkb;
input [3:0]dina;
wire [18:0]addra;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [3:0]dina;
wire [3:0]doutb;
wire \ramloop[0].ram.r_n_0 ;
wire \ramloop[10].ram.r_n_0 ;
wire \ramloop[11].ram.r_n_0 ;
wire \ramloop[12].ram.r_n_0 ;
wire \ramloop[12].ram.r_n_1 ;
wire \ramloop[12].ram.r_n_2 ;
wire \ramloop[12].ram.r_n_3 ;
wire \ramloop[12].ram.r_n_4 ;
wire \ramloop[13].ram.r_n_0 ;
wire \ramloop[13].ram.r_n_1 ;
wire \ramloop[13].ram.r_n_2 ;
wire \ramloop[14].ram.r_n_0 ;
wire \ramloop[14].ram.r_n_1 ;
wire \ramloop[14].ram.r_n_2 ;
wire \ramloop[15].ram.r_n_0 ;
wire \ramloop[15].ram.r_n_1 ;
wire \ramloop[15].ram.r_n_2 ;
wire \ramloop[15].ram.r_n_3 ;
wire \ramloop[16].ram.r_n_0 ;
wire \ramloop[16].ram.r_n_1 ;
wire \ramloop[16].ram.r_n_2 ;
wire \ramloop[16].ram.r_n_3 ;
wire \ramloop[16].ram.r_n_4 ;
wire \ramloop[17].ram.r_n_0 ;
wire \ramloop[17].ram.r_n_1 ;
wire \ramloop[18].ram.r_n_0 ;
wire \ramloop[19].ram.r_n_0 ;
wire \ramloop[1].ram.r_n_0 ;
wire \ramloop[20].ram.r_n_0 ;
wire \ramloop[21].ram.r_n_0 ;
wire \ramloop[22].ram.r_n_0 ;
wire \ramloop[2].ram.r_n_0 ;
wire \ramloop[3].ram.r_n_0 ;
wire \ramloop[4].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_1 ;
wire \ramloop[5].ram.r_n_2 ;
wire \ramloop[5].ram.r_n_3 ;
wire \ramloop[6].ram.r_n_0 ;
wire \ramloop[6].ram.r_n_1 ;
wire \ramloop[6].ram.r_n_2 ;
wire \ramloop[6].ram.r_n_3 ;
wire \ramloop[7].ram.r_n_0 ;
wire \ramloop[8].ram.r_n_0 ;
wire \ramloop[9].ram.r_n_0 ;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_mux__parameterized0 \has_mux_b.B
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T (\ramloop[1].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 (\ramloop[2].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_1 (\ramloop[3].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_10 (\ramloop[18].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_11 (\ramloop[19].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_12 (\ramloop[20].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_13 (\ramloop[21].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_2 (\ramloop[7].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_3 (\ramloop[8].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_4 (\ramloop[9].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_5 (\ramloop[10].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_6 (\ramloop[12].ram.r_n_4 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_7 (\ramloop[13].ram.r_n_2 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_8 (\ramloop[14].ram.r_n_2 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_9 (\ramloop[15].ram.r_n_3 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ({\ramloop[17].ram.r_n_0 ,\ramloop[17].ram.r_n_1 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\ramloop[4].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\ramloop[11].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\ramloop[16].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\ramloop[22].ram.r_n_0 ),
.DOBDO({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 }),
.DOUTB(\ramloop[0].ram.r_n_0 ),
.addrb(addrb[18:12]),
.clkb(clkb),
.doutb(doutb));
blk_mem_gen_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.DOUTB(\ramloop[0].ram.r_n_0 ),
.ENA(\ramloop[12].ram.r_n_0 ),
.ENB(\ramloop[12].ram.r_n_3 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[0]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r
(.DOUTB(\ramloop[10].ram.r_n_0 ),
.ENA(\ramloop[15].ram.r_n_0 ),
.ENB(\ramloop[15].ram.r_n_2 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[1]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r
(.addra(addra[14:0]),
.\addra_13__s_port_] (\ramloop[16].ram.r_n_1 ),
.addrb(addrb[14:0]),
.\addrb[17] (\ramloop[16].ram.r_n_2 ),
.clka(clka),
.clkb(clkb),
.dina(dina[1]),
.\doutb[1] (\ramloop[11].ram.r_n_0 ));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (\ramloop[12].ram.r_n_1 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 (\ramloop[12].ram.r_n_2 ),
.DOUTB(\ramloop[12].ram.r_n_4 ),
.ENA(\ramloop[12].ram.r_n_0 ),
.ENB(\ramloop[12].ram.r_n_3 ),
.addra(addra),
.addrb({addrb[18],addrb[15:0]}),
.\addrb[17] (\ramloop[16].ram.r_n_3 ),
.clka(clka),
.clkb(clkb),
.dina(dina[2]),
.wea(wea));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r
(.DOUTB(\ramloop[13].ram.r_n_2 ),
.ENA(\ramloop[13].ram.r_n_0 ),
.ENB(\ramloop[13].ram.r_n_1 ),
.addra(addra),
.addra_13__s_port_(\ramloop[15].ram.r_n_1 ),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[2]),
.wea(wea));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r
(.DOUTB(\ramloop[14].ram.r_n_2 ),
.ENA(\ramloop[14].ram.r_n_0 ),
.ENB(\ramloop[14].ram.r_n_1 ),
.addra(addra),
.addra_13__s_port_(\ramloop[15].ram.r_n_1 ),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[2]),
.wea(wea));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized14 \ramloop[15].ram.r
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (\ramloop[15].ram.r_n_1 ),
.DOUTB(\ramloop[15].ram.r_n_3 ),
.ENA(\ramloop[15].ram.r_n_0 ),
.ENB(\ramloop[15].ram.r_n_2 ),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[2]),
.wea(wea));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized15 \ramloop[16].ram.r
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\ramloop[16].ram.r_n_1 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\ramloop[16].ram.r_n_2 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\ramloop[16].ram.r_n_3 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\ramloop[16].ram.r_n_4 ),
.addra({addra[18],addra[14:0]}),
.\addra[17] (\ramloop[12].ram.r_n_1 ),
.\addra[17]_0 (\ramloop[12].ram.r_n_2 ),
.addra_13__s_port_(\ramloop[15].ram.r_n_1 ),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[2]),
.\doutb[2] (\ramloop[16].ram.r_n_0 ),
.wea(wea));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized16 \ramloop[17].ram.r
(.addra(addra[12:0]),
.\addra[17] (\ramloop[5].ram.r_n_2 ),
.addrb(addrb[12:0]),
.\addrb[17] (\ramloop[5].ram.r_n_3 ),
.clka(clka),
.clkb(clkb),
.dina(dina[3:2]),
.\doutb[3] ({\ramloop[17].ram.r_n_0 ,\ramloop[17].ram.r_n_1 }));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized17 \ramloop[18].ram.r
(.DOUTB(\ramloop[18].ram.r_n_0 ),
.ENA(\ramloop[12].ram.r_n_0 ),
.ENB(\ramloop[12].ram.r_n_3 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[3]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized18 \ramloop[19].ram.r
(.DOUTB(\ramloop[19].ram.r_n_0 ),
.ENA(\ramloop[13].ram.r_n_0 ),
.ENB(\ramloop[13].ram.r_n_1 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[3]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.DOUTB(\ramloop[1].ram.r_n_0 ),
.ENA(\ramloop[13].ram.r_n_0 ),
.ENB(\ramloop[13].ram.r_n_1 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[0]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized19 \ramloop[20].ram.r
(.DOUTB(\ramloop[20].ram.r_n_0 ),
.ENA(\ramloop[14].ram.r_n_0 ),
.ENB(\ramloop[14].ram.r_n_1 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[3]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized20 \ramloop[21].ram.r
(.DOUTB(\ramloop[21].ram.r_n_0 ),
.ENA(\ramloop[15].ram.r_n_0 ),
.ENB(\ramloop[15].ram.r_n_2 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[3]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized21 \ramloop[22].ram.r
(.addra(addra[14:0]),
.\addra_13__s_port_] (\ramloop[16].ram.r_n_1 ),
.addrb(addrb[14:0]),
.\addrb[17] (\ramloop[16].ram.r_n_2 ),
.clka(clka),
.clkb(clkb),
.dina(dina[3]),
.\doutb[3] (\ramloop[22].ram.r_n_0 ));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.DOUTB(\ramloop[2].ram.r_n_0 ),
.ENA(\ramloop[14].ram.r_n_0 ),
.ENB(\ramloop[14].ram.r_n_1 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[0]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.DOUTB(\ramloop[3].ram.r_n_0 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.\addrb[18] (\ramloop[15].ram.r_n_2 ),
.clka(clka),
.clkb(clkb),
.dina(dina[0]),
.\wea[0] (\ramloop[15].ram.r_n_0 ));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra[14:0]),
.\addra_13__s_port_] (\ramloop[16].ram.r_n_1 ),
.addrb(addrb[14:0]),
.\addrb[17] (\ramloop[16].ram.r_n_2 ),
.clka(clka),
.clkb(clkb),
.dina(dina[0]),
.\doutb[0] (\ramloop[4].ram.r_n_0 ));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (\ramloop[5].ram.r_n_2 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 (\ramloop[5].ram.r_n_3 ),
.DOBDO({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 }),
.addra({addra[18],addra[14:0]}),
.\addra[17] (\ramloop[12].ram.r_n_1 ),
.\addra[17]_0 (\ramloop[12].ram.r_n_2 ),
.addrb({addrb[18],addrb[14:0]}),
.\addrb[17] (\ramloop[16].ram.r_n_4 ),
.\addrb[17]_0 (\ramloop[16].ram.r_n_3 ),
.clka(clka),
.clkb(clkb),
.dina(dina[1:0]),
.wea(wea));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra({addra[18],addra[14:0]}),
.\addra[17] (\ramloop[12].ram.r_n_2 ),
.\addra[17]_0 (\ramloop[12].ram.r_n_1 ),
.addra_13__s_port_(\ramloop[15].ram.r_n_1 ),
.addrb({addrb[18],addrb[14:0]}),
.\addrb[17] (\ramloop[16].ram.r_n_3 ),
.\addrb[17]_0 (\ramloop[16].ram.r_n_4 ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[3] ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 }),
.wea(wea));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.DOUTB(\ramloop[7].ram.r_n_0 ),
.ENA(\ramloop[12].ram.r_n_0 ),
.ENB(\ramloop[12].ram.r_n_3 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[1]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r
(.DOUTB(\ramloop[8].ram.r_n_0 ),
.ENA(\ramloop[13].ram.r_n_0 ),
.ENB(\ramloop[13].ram.r_n_1 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[1]));
blk_mem_gen_0_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r
(.DOUTB(\ramloop[9].ram.r_n_0 ),
.ENA(\ramloop[14].ram.r_n_0 ),
.ENB(\ramloop[14].ram.r_n_1 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[1]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module blk_mem_gen_0_blk_mem_gen_mux__parameterized0
(doutb,
DOBDO,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ,
addrb,
clkb,
DOUTB,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_4 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_5 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_6 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_7 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_8 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_9 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_10 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_11 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_12 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_13 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 );
output [3:0]doutb;
input [1:0]DOBDO;
input [3:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
input [1:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
input [6:0]addrb;
input clkb;
input [0:0]DOUTB;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_1 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_2 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_3 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_4 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_5 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_6 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_7 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_8 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_9 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_10 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_11 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_12 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_13 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_10 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_11 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_12 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_13 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_3 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_4 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_5 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_6 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_7 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_8 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_9 ;
wire [3:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
wire [1:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
wire [1:0]DOBDO;
wire [0:0]DOUTB;
wire [6:0]addrb;
wire clkb;
wire [3:0]doutb;
wire \doutb[0]_INST_0_i_1_n_0 ;
wire \doutb[0]_INST_0_i_2_n_0 ;
wire \doutb[0]_INST_0_i_3_n_0 ;
wire \doutb[0]_INST_0_i_4_n_0 ;
wire \doutb[1]_INST_0_i_1_n_0 ;
wire \doutb[1]_INST_0_i_2_n_0 ;
wire \doutb[1]_INST_0_i_3_n_0 ;
wire \doutb[1]_INST_0_i_4_n_0 ;
wire \doutb[2]_INST_0_i_1_n_0 ;
wire \doutb[2]_INST_0_i_2_n_0 ;
wire \doutb[2]_INST_0_i_3_n_0 ;
wire \doutb[2]_INST_0_i_4_n_0 ;
wire \doutb[3]_INST_0_i_1_n_0 ;
wire \doutb[3]_INST_0_i_2_n_0 ;
wire \doutb[3]_INST_0_i_3_n_0 ;
wire \doutb[3]_INST_0_i_4_n_0 ;
wire [6:0]sel_pipe;
wire [6:0]sel_pipe_d1;
LUT6 #(
.INIT(64'h0F004F4F0F004040))
\doutb[0]_INST_0
(.I0(sel_pipe_d1[4]),
.I1(\doutb[0]_INST_0_i_1_n_0 ),
.I2(sel_pipe_d1[6]),
.I3(\doutb[0]_INST_0_i_2_n_0 ),
.I4(sel_pipe_d1[5]),
.I5(\doutb[0]_INST_0_i_3_n_0 ),
.O(doutb[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\doutb[0]_INST_0_i_1
(.I0(\doutb[0]_INST_0_i_4_n_0 ),
.I1(sel_pipe_d1[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.O(\doutb[0]_INST_0_i_1_n_0 ));
MUXF7 \doutb[0]_INST_0_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_1 ),
.O(\doutb[0]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[4]));
MUXF7 \doutb[0]_INST_0_i_3
(.I0(DOUTB),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T ),
.O(\doutb[0]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[4]));
LUT5 #(
.INIT(32'h00003A0A))
\doutb[0]_INST_0_i_4
(.I0(DOBDO[0]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [0]),
.I4(sel_pipe_d1[2]),
.O(\doutb[0]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h0F004F4F0F004040))
\doutb[1]_INST_0
(.I0(sel_pipe_d1[4]),
.I1(\doutb[1]_INST_0_i_1_n_0 ),
.I2(sel_pipe_d1[6]),
.I3(\doutb[1]_INST_0_i_2_n_0 ),
.I4(sel_pipe_d1[5]),
.I5(\doutb[1]_INST_0_i_3_n_0 ),
.O(doutb[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\doutb[1]_INST_0_i_1
(.I0(\doutb[1]_INST_0_i_4_n_0 ),
.I1(sel_pipe_d1[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
.O(\doutb[1]_INST_0_i_1_n_0 ));
MUXF7 \doutb[1]_INST_0_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_4 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_5 ),
.O(\doutb[1]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[4]));
MUXF7 \doutb[1]_INST_0_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_2 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_3 ),
.O(\doutb[1]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[4]));
LUT5 #(
.INIT(32'h00003A0A))
\doutb[1]_INST_0_i_4
(.I0(DOBDO[1]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [1]),
.I4(sel_pipe_d1[2]),
.O(\doutb[1]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h0F004F4F0F004040))
\doutb[2]_INST_0
(.I0(sel_pipe_d1[4]),
.I1(\doutb[2]_INST_0_i_1_n_0 ),
.I2(sel_pipe_d1[6]),
.I3(\doutb[2]_INST_0_i_2_n_0 ),
.I4(sel_pipe_d1[5]),
.I5(\doutb[2]_INST_0_i_3_n_0 ),
.O(doutb[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hB8))
\doutb[2]_INST_0_i_1
(.I0(\doutb[2]_INST_0_i_4_n_0 ),
.I1(sel_pipe_d1[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
.O(\doutb[2]_INST_0_i_1_n_0 ));
MUXF7 \doutb[2]_INST_0_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_8 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_9 ),
.O(\doutb[2]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[4]));
MUXF7 \doutb[2]_INST_0_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_6 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_7 ),
.O(\doutb[2]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[4]));
LUT5 #(
.INIT(32'h00003A0A))
\doutb[2]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 [0]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [2]),
.I4(sel_pipe_d1[2]),
.O(\doutb[2]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h0F004F4F0F004040))
\doutb[3]_INST_0
(.I0(sel_pipe_d1[4]),
.I1(\doutb[3]_INST_0_i_1_n_0 ),
.I2(sel_pipe_d1[6]),
.I3(\doutb[3]_INST_0_i_2_n_0 ),
.I4(sel_pipe_d1[5]),
.I5(\doutb[3]_INST_0_i_3_n_0 ),
.O(doutb[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hB8))
\doutb[3]_INST_0_i_1
(.I0(\doutb[3]_INST_0_i_4_n_0 ),
.I1(sel_pipe_d1[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
.O(\doutb[3]_INST_0_i_1_n_0 ));
MUXF7 \doutb[3]_INST_0_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_12 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_13 ),
.O(\doutb[3]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[4]));
MUXF7 \doutb[3]_INST_0_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_10 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_11 ),
.O(\doutb[3]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[4]));
LUT5 #(
.INIT(32'h00003A0A))
\doutb[3]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 [1]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [3]),
.I4(sel_pipe_d1[2]),
.O(\doutb[3]_INST_0_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[2]),
.Q(sel_pipe_d1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[3]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[3]),
.Q(sel_pipe_d1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[4]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[4]),
.Q(sel_pipe_d1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[5]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[5]),
.Q(sel_pipe_d1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[6]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[6]),
.Q(sel_pipe_d1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clkb),
.CE(1'b1),
.D(addrb[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clkb),
.CE(1'b1),
.D(addrb[1]),
.Q(sel_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]
(.C(clkb),
.CE(1'b1),
.D(addrb[2]),
.Q(sel_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]
(.C(clkb),
.CE(1'b1),
.D(addrb[3]),
.Q(sel_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[4]
(.C(clkb),
.CE(1'b1),
.D(addrb[4]),
.Q(sel_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[5]
(.C(clkb),
.CE(1'b1),
.D(addrb[5]),
.Q(sel_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[6]
(.C(clkb),
.CE(1'b1),
.D(addrb[6]),
.Q(sel_pipe[6]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized0
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized1
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized10
(\doutb[1] ,
\addra_13__s_port_] ,
clka,
\addrb[17] ,
clkb,
addra,
addrb,
dina);
output [0:0]\doutb[1] ;
input \addra_13__s_port_] ;
input clka;
input \addrb[17] ;
input clkb;
input [14:0]addra;
input [14:0]addrb;
input [0:0]dina;
wire [14:0]addra;
wire addra_13__s_net_1;
wire [14:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]\doutb[1] ;
assign addra_13__s_net_1 = \addra_13__s_port_] ;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized10 \prim_noinit.ram
(.addra(addra),
.\addra_13__s_port_] (addra_13__s_net_1),
.addrb(addrb),
.\addrb[17] (\addrb[17] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[1] (\doutb[1] ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized11
(ENA,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ,
ENB,
DOUTB,
addra,
wea,
addrb,
\addrb[17] ,
clka,
clkb,
dina);
output ENA;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
output ENB;
output [0:0]DOUTB;
input [18:0]addra;
input [0:0]wea;
input [16:0]addrb;
input \addrb[17] ;
input clka;
input clkb;
input [0:0]dina;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [18:0]addra;
wire [16:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized11 \prim_noinit.ram
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.\addrb[17] (\addrb[17] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized12
(ENA,
ENB,
DOUTB,
addra,
wea,
addra_13__s_port_,
addrb,
clka,
clkb,
dina);
output ENA;
output ENB;
output [0:0]DOUTB;
input [18:0]addra;
input [0:0]wea;
input addra_13__s_port_;
input [18:0]addrb;
input clka;
input clkb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [18:0]addra;
wire addra_13__s_net_1;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
assign addra_13__s_net_1 = addra_13__s_port_;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized12 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addra_13__s_port_(addra_13__s_net_1),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized13
(ENA,
ENB,
DOUTB,
addra,
wea,
addra_13__s_port_,
addrb,
clka,
clkb,
dina);
output ENA;
output ENB;
output [0:0]DOUTB;
input [18:0]addra;
input [0:0]wea;
input addra_13__s_port_;
input [18:0]addrb;
input clka;
input clkb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [18:0]addra;
wire addra_13__s_net_1;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
assign addra_13__s_net_1 = addra_13__s_port_;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized13 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addra_13__s_port_(addra_13__s_net_1),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized14
(ENA,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ,
ENB,
DOUTB,
addra,
wea,
addrb,
clka,
clkb,
dina);
output ENA;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
output ENB;
output [0:0]DOUTB;
input [18:0]addra;
input [0:0]wea;
input [18:0]addrb;
input clka;
input clkb;
input [0:0]dina;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [18:0]addra;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized14 \prim_noinit.ram
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized15
(\doutb[2] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
clka,
clkb,
addra,
addrb,
dina,
\addra[17] ,
wea,
addra_13__s_port_,
\addra[17]_0 );
output [0:0]\doutb[2] ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
input clka;
input clkb;
input [15:0]addra;
input [18:0]addrb;
input [0:0]dina;
input \addra[17] ;
input [0:0]wea;
input addra_13__s_port_;
input \addra[17]_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
wire [15:0]addra;
wire \addra[17] ;
wire \addra[17]_0 ;
wire addra_13__s_net_1;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]\doutb[2] ;
wire [0:0]wea;
assign addra_13__s_net_1 = addra_13__s_port_;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized15 \prim_noinit.ram
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
.addra(addra),
.\addra[17] (\addra[17] ),
.\addra[17]_0 (\addra[17]_0 ),
.addra_13__s_port_(addra_13__s_net_1),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[2] (\doutb[2] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized16
(\doutb[3] ,
clka,
clkb,
\addra[17] ,
\addrb[17] ,
addra,
addrb,
dina);
output [1:0]\doutb[3] ;
input clka;
input clkb;
input \addra[17] ;
input \addrb[17] ;
input [12:0]addra;
input [12:0]addrb;
input [1:0]dina;
wire [12:0]addra;
wire \addra[17] ;
wire [12:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]\doutb[3] ;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized16 \prim_noinit.ram
(.addra(addra),
.\addra[17] (\addra[17] ),
.addrb(addrb),
.\addrb[17] (\addrb[17] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[3] (\doutb[3] ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized17
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized17 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized18
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized18 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized19
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized19 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized2
(DOUTB,
\wea[0] ,
clka,
\addrb[18] ,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input \wea[0] ;
input clka;
input \addrb[18] ;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire [15:0]addra;
wire [15:0]addrb;
wire \addrb[18] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire \wea[0] ;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.DOUTB(DOUTB),
.addra(addra),
.addrb(addrb),
.\addrb[18] (\addrb[18] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\wea[0] (\wea[0] ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized20
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized20 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized21
(\doutb[3] ,
\addra_13__s_port_] ,
clka,
\addrb[17] ,
clkb,
addra,
addrb,
dina);
output [0:0]\doutb[3] ;
input \addra_13__s_port_] ;
input clka;
input \addrb[17] ;
input clkb;
input [14:0]addra;
input [14:0]addrb;
input [0:0]dina;
wire [14:0]addra;
wire addra_13__s_net_1;
wire [14:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]\doutb[3] ;
assign addra_13__s_net_1 = \addra_13__s_port_] ;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized21 \prim_noinit.ram
(.addra(addra),
.\addra_13__s_port_] (addra_13__s_net_1),
.addrb(addrb),
.\addrb[17] (\addrb[17] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[3] (\doutb[3] ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized3
(\doutb[0] ,
\addra_13__s_port_] ,
clka,
\addrb[17] ,
clkb,
addra,
addrb,
dina);
output [0:0]\doutb[0] ;
input \addra_13__s_port_] ;
input clka;
input \addrb[17] ;
input clkb;
input [14:0]addra;
input [14:0]addrb;
input [0:0]dina;
wire [14:0]addra;
wire addra_13__s_net_1;
wire [14:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]\doutb[0] ;
assign addra_13__s_net_1 = \addra_13__s_port_] ;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.addra(addra),
.\addra_13__s_port_] (addra_13__s_net_1),
.addrb(addrb),
.\addrb[17] (\addrb[17] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[0] (\doutb[0] ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized4
(DOBDO,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ,
clka,
clkb,
addra,
addrb,
dina,
wea,
\addra[17] ,
\addra[17]_0 ,
\addrb[17] ,
\addrb[17]_0 );
output [1:0]DOBDO;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
input clka;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [1:0]dina;
input [0:0]wea;
input \addra[17] ;
input \addra[17]_0 ;
input \addrb[17] ;
input \addrb[17]_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
wire [1:0]DOBDO;
wire [15:0]addra;
wire \addra[17] ;
wire \addra[17]_0 ;
wire [15:0]addrb;
wire \addrb[17] ;
wire \addrb[17]_0 ;
wire clka;
wire clkb;
wire [1:0]dina;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.DOBDO(DOBDO),
.addra(addra),
.\addra[17] (\addra[17] ),
.\addra[17]_0 (\addra[17]_0 ),
.addrb(addrb),
.\addrb[17] (\addrb[17] ),
.\addrb[17]_0 (\addrb[17]_0 ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized5
(\doutb[3] ,
clka,
clkb,
addra,
addrb,
dina,
\addra[17] ,
\addra[17]_0 ,
addra_13__s_port_,
wea,
\addrb[17] ,
\addrb[17]_0 );
output [3:0]\doutb[3] ;
input clka;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [3:0]dina;
input \addra[17] ;
input \addra[17]_0 ;
input addra_13__s_port_;
input [0:0]wea;
input \addrb[17] ;
input \addrb[17]_0 ;
wire [15:0]addra;
wire \addra[17] ;
wire \addra[17]_0 ;
wire addra_13__s_net_1;
wire [15:0]addrb;
wire \addrb[17] ;
wire \addrb[17]_0 ;
wire clka;
wire clkb;
wire [3:0]dina;
wire [3:0]\doutb[3] ;
wire [0:0]wea;
assign addra_13__s_net_1 = addra_13__s_port_;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.addra(addra),
.\addra[17] (\addra[17] ),
.\addra[17]_0 (\addra[17]_0 ),
.addra_13__s_port_(addra_13__s_net_1),
.addrb(addrb),
.\addrb[17] (\addrb[17] ),
.\addrb[17]_0 (\addrb[17]_0 ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[3] (\doutb[3] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized6
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized7
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized7 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized8
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized8 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width__parameterized9
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized9 \prim_noinit.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized0
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized1
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized10
(\doutb[1] ,
\addra_13__s_port_] ,
clka,
\addrb[17] ,
clkb,
addra,
addrb,
dina);
output [0:0]\doutb[1] ;
input \addra_13__s_port_] ;
input clka;
input \addrb[17] ;
input clkb;
input [14:0]addra;
input [14:0]addrb;
input [0:0]dina;
wire [14:0]addra;
wire addra_13__s_net_1;
wire [14:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]\doutb[1] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
assign addra_13__s_net_1 = \addra_13__s_port_] ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra}),
.ADDRBWRADDR({1'b1,addrb}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:1],\doutb[1] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(addra_13__s_net_1),
.ENBWREN(\addrb[17] ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized11
(ENA,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ,
ENB,
DOUTB,
addra,
wea,
addrb,
\addrb[17] ,
clka,
clkb,
dina);
output ENA;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
output ENB;
output [0:0]DOUTB;
input [18:0]addra;
input [0:0]wea;
input [16:0]addrb;
input \addrb[17] ;
input clka;
input clkb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [18:0]addra;
wire [16:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5_n_0 ),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6_n_0 ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8_n_0 ),
.O(ENA));
LUT6 #(
.INIT(64'h0000000001000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I2(addra[14]),
.I3(addra[13]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000400000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I1(addra[12]),
.I2(wea),
.I3(addra[14]),
.I4(addra[13]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I1(addra[13]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I3(wea),
.I4(addra[18]),
.I5(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I1(addra[12]),
.I2(wea),
.I3(addra[13]),
.I4(addra[14]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13_n_0 ));
LUT6 #(
.INIT(64'h0000040000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14
(.I0(addra[13]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I3(wea),
.I4(addra[18]),
.I5(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I2(addra[13]),
.I3(addra[12]),
.I4(addra[14]),
.I5(wea),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15_n_0 ));
LUT5 #(
.INIT(32'h00000004))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26_n_0 ),
.I1(addra[15]),
.I2(addra[17]),
.I3(addra[16]),
.I4(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16_n_0 ));
LUT6 #(
.INIT(64'h0000080000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17
(.I0(addra[13]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I3(wea),
.I4(addra[18]),
.I5(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17_n_0 ));
LUT5 #(
.INIT(32'h00000004))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27_n_0 ),
.I1(addra[15]),
.I2(addra[17]),
.I3(addra[16]),
.I4(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18_n_0 ));
LUT6 #(
.INIT(64'h0000000004000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I2(addra[14]),
.I3(addra[13]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19_n_0 ));
LUT2 #(
.INIT(4'h1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2
(.I0(addrb[16]),
.I1(\addrb[17] ),
.O(ENB));
LUT6 #(
.INIT(64'h0000040000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I1(addra[13]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I3(wea),
.I4(addra[18]),
.I5(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20_n_0 ));
LUT6 #(
.INIT(64'h1000000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I2(addra[13]),
.I3(addra[12]),
.I4(addra[14]),
.I5(wea),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000004))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28_n_0 ),
.I1(addra[15]),
.I2(addra[17]),
.I3(addra[16]),
.I4(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22_n_0 ));
LUT6 #(
.INIT(64'h0000000000000400))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23
(.I0(addra[13]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I3(wea),
.I4(addra[18]),
.I5(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00000001))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29_n_0 ),
.I1(addra[15]),
.I2(addra[17]),
.I3(addra[16]),
.I4(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24_n_0 ));
LUT6 #(
.INIT(64'h0000010000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I1(addra[13]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.I3(wea),
.I4(addra[18]),
.I5(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26
(.I0(wea),
.I1(addra[14]),
.I2(addra[12]),
.I3(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hFF7F))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27
(.I0(wea),
.I1(addra[12]),
.I2(addra[13]),
.I3(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFFF7))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28
(.I0(wea),
.I1(addra[12]),
.I2(addra[13]),
.I3(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFF7F))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29
(.I0(wea),
.I1(addra[14]),
.I2(addra[12]),
.I3(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29_n_0 ));
LUT5 #(
.INIT(32'h2AFF2A2A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__2_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3_n_0 ));
LUT5 #(
.INIT(32'h8AFF8A8A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4_n_0 ));
LUT5 #(
.INIT(32'h8AFF8A8A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFAFEFEFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18_n_0 ),
.I3(addra[12]),
.I4(addra[13]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6_n_0 ));
LUT5 #(
.INIT(32'h2AFF2A2A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFAFFFEFEFAFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24_n_0 ),
.I3(addra[12]),
.I4(addra[13]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3
(.I0(addra[16]),
.I1(addra[15]),
.I2(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'hE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4
(.I0(addra[16]),
.I1(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized12
(ENA,
ENB,
DOUTB,
addra,
wea,
addra_13__s_port_,
addrb,
clka,
clkb,
dina);
output ENA;
output ENB;
output [0:0]DOUTB;
input [18:0]addra;
input [0:0]wea;
input addra_13__s_port_;
input [18:0]addrb;
input clka;
input clkb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [18:0]addra;
wire addra_13__s_net_1;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
assign addra_13__s_net_1 = addra_13__s_port_;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hB))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10
(.I0(addra[17]),
.I1(addra[16]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ));
LUT6 #(
.INIT(64'h0000000004000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__2_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(addra[13]),
.I3(addra[12]),
.I4(addra[14]),
.I5(wea),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__2_n_0 ));
LUT6 #(
.INIT(64'h4000000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(addra[13]),
.I3(addra[12]),
.I4(addra[14]),
.I5(wea),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__2_n_0 ));
LUT6 #(
.INIT(64'h0000000070000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__2
(.I0(addra[12]),
.I1(addra[13]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0_n_0 ),
.I3(addra[15]),
.I4(addra[16]),
.I5(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__2_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(addra[14]),
.I3(addra[13]),
.I4(addra[12]),
.I5(wea),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__0_n_0 ));
LUT6 #(
.INIT(64'h0000000070000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__1
(.I0(addra[12]),
.I1(addra[13]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0_n_0 ),
.I3(addra[15]),
.I4(addra[16]),
.I5(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__1_n_0 ));
LUT6 #(
.INIT(64'h0000000010000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__2_n_0 ));
LUT6 #(
.INIT(64'h1000000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(addra[13]),
.I3(addra[12]),
.I4(addra[14]),
.I5(wea),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__2_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(addra[14]),
.I3(addra[13]),
.I4(addra[12]),
.I5(wea),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__2_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__0_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__2_n_0 ),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__1_n_0 ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__2_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__2_n_0 ),
.O(ENA));
LUT6 #(
.INIT(64'h00000000D0000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__0
(.I0(addra[12]),
.I1(addra[13]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0_n_0 ),
.I3(addra[15]),
.I4(addra[16]),
.I5(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__0_n_0 ));
LUT6 #(
.INIT(64'h0100000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(addra[13]),
.I3(addra[12]),
.I4(addra[14]),
.I5(wea),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000D00000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22__0
(.I0(addra[12]),
.I1(addra[13]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0_n_0 ),
.I3(addra[15]),
.I4(addra[16]),
.I5(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h4000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0
(.I0(addra[18]),
.I1(wea),
.I2(addra[14]),
.I3(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0040))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0
(.I0(addra[18]),
.I1(wea),
.I2(addra[13]),
.I3(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0004))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0
(.I0(addra[18]),
.I1(wea),
.I2(addra[14]),
.I3(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0040))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0
(.I0(addra[18]),
.I1(wea),
.I2(addra[14]),
.I3(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2__0
(.I0(addrb[17]),
.I1(addrb[16]),
.I2(addrb[18]),
.O(ENB));
LUT5 #(
.INIT(32'h00000010))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__2
(.I0(addra[18]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I2(wea),
.I3(addra_13__s_net_1),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000010000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__0
(.I0(addra[13]),
.I1(addra[14]),
.I2(addra[18]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ),
.I4(wea),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__0_n_0 ));
LUT5 #(
.INIT(32'h8AFF8A8A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__2_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__2_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__2_n_0 ));
LUT5 #(
.INIT(32'hFFFFCCFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__2_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__2_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__0_n_0 ),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__1_n_0 ));
LUT5 #(
.INIT(32'h2AFF2A2A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__2_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__2_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__2_n_0 ));
LUT5 #(
.INIT(32'hFFFFCCFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__2_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__0_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21__0_n_0 ),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hF8))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1
(.I0(addra[16]),
.I1(addra[15]),
.I2(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized13
(ENA,
ENB,
DOUTB,
addra,
wea,
addra_13__s_port_,
addrb,
clka,
clkb,
dina);
output ENA;
output ENB;
output [0:0]DOUTB;
input [18:0]addra;
input [0:0]wea;
input addra_13__s_port_;
input [18:0]addrb;
input clka;
input clkb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [18:0]addra;
wire addra_13__s_net_1;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
assign addra_13__s_net_1 = addra_13__s_port_;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hB))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0
(.I0(addra[16]),
.I1(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ));
LUT6 #(
.INIT(64'h0000000004000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__0_n_0 ));
LUT6 #(
.INIT(64'h0000000008000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__1
(.I0(addra[12]),
.I1(wea),
.I2(addra[13]),
.I3(addra[14]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__0
(.I0(addra[12]),
.I1(wea),
.I2(addra[13]),
.I3(addra[14]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__0_n_0 ));
LUT6 #(
.INIT(64'h0000000040000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h00000400))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1
(.I0(addra[18]),
.I1(wea),
.I2(addra_13__s_net_1),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1_n_0 ));
LUT6 #(
.INIT(64'h0000000010000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__0_n_0 ));
LUT6 #(
.INIT(64'h0000000040000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I1(addra[12]),
.I2(wea),
.I3(addra[13]),
.I4(addra[14]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000080000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__1
(.I0(addra[12]),
.I1(wea),
.I2(addra[13]),
.I3(addra[14]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000040000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__1_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__1_n_0 ),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__0_n_0 ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__0_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__1_n_0 ),
.O(ENA));
LUT6 #(
.INIT(64'h0000000000040000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__1
(.I0(addra[13]),
.I1(addra[14]),
.I2(addra[18]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I4(wea),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__1_n_0 ));
LUT3 #(
.INIT(8'h04))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2__1
(.I0(addrb[16]),
.I1(addrb[17]),
.I2(addrb[18]),
.O(ENB));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h00000010))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0
(.I0(addra[18]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I2(wea),
.I3(addra_13__s_net_1),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000010000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__1
(.I0(addra[13]),
.I1(addra[14]),
.I2(addra[18]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ),
.I4(wea),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__1_n_0 ));
LUT5 #(
.INIT(32'h8AFF8A8A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__0_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF2FFF2222))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__0_n_0 ),
.I1(addra[18]),
.I2(addra[12]),
.I3(addra[13]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__0_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__0_n_0 ));
LUT5 #(
.INIT(32'h2AFF2A2A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__0_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF2F2222))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__1_n_0 ),
.I1(addra[18]),
.I2(addra[12]),
.I3(addra[13]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__1_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h4F))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9
(.I0(addra[16]),
.I1(addra[15]),
.I2(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized14
(ENA,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ,
ENB,
DOUTB,
addra,
wea,
addrb,
clka,
clkb,
dina);
output ENA;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
output ENB;
output [0:0]DOUTB;
input [18:0]addra;
input [0:0]wea;
input [18:0]addrb;
input clka;
input clkb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__2_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [18:0]addra;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h7))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1
(.I0(addra[16]),
.I1(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ));
LUT6 #(
.INIT(64'h0000000004000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__1_n_0 ));
LUT6 #(
.INIT(64'h0000000008000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__0
(.I0(addra[12]),
.I1(wea),
.I2(addra[13]),
.I3(addra[14]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__0_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__1
(.I0(addra[12]),
.I1(wea),
.I2(addra[13]),
.I3(addra[14]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__1_n_0 ));
LUT6 #(
.INIT(64'h0000000040000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h00000400))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2
(.I0(addra[18]),
.I1(wea),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2_n_0 ));
LUT6 #(
.INIT(64'h0000000010000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__2_n_0 ));
LUT6 #(
.INIT(64'h0000000040000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I1(addra[12]),
.I2(wea),
.I3(addra[13]),
.I4(addra[14]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000080000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__0
(.I0(addra[12]),
.I1(wea),
.I2(addra[13]),
.I3(addra[14]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000040000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I2(addra[13]),
.I3(addra[14]),
.I4(wea),
.I5(addra[18]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__2_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__0_n_0 ),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__2_n_0 ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__1_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__0_n_0 ),
.O(ENA));
LUT6 #(
.INIT(64'h0000000000040000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__2
(.I0(addra[13]),
.I1(addra[14]),
.I2(addra[18]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I4(wea),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__2_n_0 ));
LUT3 #(
.INIT(8'h08))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2__2
(.I0(addrb[16]),
.I1(addrb[17]),
.I2(addrb[18]),
.O(ENB));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h00000010))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1
(.I0(addra[18]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I2(wea),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000010000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__2
(.I0(addra[13]),
.I1(addra[14]),
.I2(addra[18]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ),
.I4(wea),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__2_n_0 ));
LUT5 #(
.INIT(32'h8AFF8A8A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__1_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__0_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF2FFF2222))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__1_n_0 ),
.I1(addra[18]),
.I2(addra[12]),
.I3(addra[13]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__1_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__2_n_0 ));
LUT5 #(
.INIT(32'h2AFF2A2A))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__2_n_0 ),
.I1(addra[13]),
.I2(addra[12]),
.I3(addra[18]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__1_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF2F2222))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__0_n_0 ),
.I1(addra[18]),
.I2(addra[12]),
.I3(addra[13]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__0_n_0 ),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__2_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h8F))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0
(.I0(addra[16]),
.I1(addra[15]),
.I2(addra[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0 ));
LUT2 #(
.INIT(4'hB))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3__0
(.I0(addra[14]),
.I1(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized15
(\doutb[2] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ,
clka,
clkb,
addra,
addrb,
dina,
\addra[17] ,
wea,
addra_13__s_port_,
\addra[17]_0 );
output [0:0]\doutb[2] ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
input clka;
input clkb;
input [15:0]addra;
input [18:0]addrb;
input [0:0]dina;
input \addra[17] ;
input [0:0]wea;
input addra_13__s_port_;
input \addra[17]_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_5_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_6_n_0 ;
wire [15:0]addra;
wire \addra[17] ;
wire \addra[17]_0 ;
wire addra_13__s_net_1;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]\doutb[2] ;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
assign addra_13__s_net_1 = addra_13__s_port_;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'hE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__2
(.I0(addrb[16]),
.I1(addrb[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[14:0]}),
.ADDRBWRADDR({1'b1,addrb[14:0]}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:1],\doutb[2] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
.ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hFFFE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3_n_0 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_5_n_0 ),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_6_n_0 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ));
LUT3 #(
.INIT(8'h02))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(addrb[18]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ));
LUT6 #(
.INIT(64'h0000010000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3
(.I0(addra[13]),
.I1(addra[14]),
.I2(\addra[17] ),
.I3(wea),
.I4(\addra[17]_0 ),
.I5(addra[15]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000080000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4
(.I0(addra[13]),
.I1(addra[14]),
.I2(\addra[17] ),
.I3(wea),
.I4(\addra[17]_0 ),
.I5(addra[15]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0 ));
LUT5 #(
.INIT(32'h00040000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_5
(.I0(\addra[17] ),
.I1(wea),
.I2(addra_13__s_net_1),
.I3(\addra[17]_0 ),
.I4(addra[15]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000040000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_6
(.I0(addra[13]),
.I1(addra[14]),
.I2(\addra[17] ),
.I3(wea),
.I4(\addra[17]_0 ),
.I5(addra[15]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hF4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_7
(.I0(addrb[16]),
.I1(addrb[15]),
.I2(addrb[17]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized16
(\doutb[3] ,
clka,
clkb,
\addra[17] ,
\addrb[17] ,
addra,
addrb,
dina);
output [1:0]\doutb[3] ;
input clka;
input clkb;
input \addra[17] ;
input \addrb[17] ;
input [12:0]addra;
input [12:0]addrb;
input [1:0]dina;
wire [12:0]addra;
wire \addra[17] ;
wire [12:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]\doutb[3] ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0}),
.ADDRBWRADDR({addrb,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:2],\doutb[3] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\addra[17] ),
.ENBWREN(\addrb[17] ),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized17
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized18
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized19
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized2
(DOUTB,
\wea[0] ,
clka,
\addrb[18] ,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input \wea[0] ;
input clka;
input \addrb[18] ;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire [15:0]addra;
wire [15:0]addrb;
wire \addrb[18] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire \wea[0] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\wea[0] ),
.ENBWREN(\addrb[18] ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\wea[0] ),
.ENBWREN(\addrb[18] ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized20
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized21
(\doutb[3] ,
\addra_13__s_port_] ,
clka,
\addrb[17] ,
clkb,
addra,
addrb,
dina);
output [0:0]\doutb[3] ;
input \addra_13__s_port_] ;
input clka;
input \addrb[17] ;
input clkb;
input [14:0]addra;
input [14:0]addrb;
input [0:0]dina;
wire [14:0]addra;
wire addra_13__s_net_1;
wire [14:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]\doutb[3] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
assign addra_13__s_net_1 = \addra_13__s_port_] ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra}),
.ADDRBWRADDR({1'b1,addrb}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:1],\doutb[3] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(addra_13__s_net_1),
.ENBWREN(\addrb[17] ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized3
(\doutb[0] ,
\addra_13__s_port_] ,
clka,
\addrb[17] ,
clkb,
addra,
addrb,
dina);
output [0:0]\doutb[0] ;
input \addra_13__s_port_] ;
input clka;
input \addrb[17] ;
input clkb;
input [14:0]addra;
input [14:0]addrb;
input [0:0]dina;
wire [14:0]addra;
wire addra_13__s_net_1;
wire [14:0]addrb;
wire \addrb[17] ;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]\doutb[0] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
assign addra_13__s_net_1 = \addra_13__s_port_] ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra}),
.ADDRBWRADDR({1'b1,addrb}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:1],\doutb[0] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(addra_13__s_net_1),
.ENBWREN(\addrb[17] ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized4
(DOBDO,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1 ,
clka,
clkb,
addra,
addrb,
dina,
wea,
\addra[17] ,
\addra[17]_0 ,
\addrb[17] ,
\addrb[17]_0 );
output [1:0]DOBDO;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1 ;
input clka;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [1:0]dina;
input [0:0]wea;
input \addra[17] ;
input \addra[17]_0 ;
input \addrb[17] ;
input \addrb[17]_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1 ;
wire [1:0]DOBDO;
wire [15:0]addra;
wire \addra[17] ;
wire \addra[17]_0 ;
wire [15:0]addrb;
wire \addrb[17] ;
wire \addrb[17]_0 ;
wire clka;
wire clkb;
wire [1:0]dina;
wire [0:0]wea;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra[12:0],1'b0}),
.ADDRBWRADDR({addrb[12:0],1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:2],DOBDO}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ),
.ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1 ),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000100000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1__0
(.I0(addra[13]),
.I1(addra[14]),
.I2(wea),
.I3(\addra[17] ),
.I4(\addra[17]_0 ),
.I5(addra[15]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0 ));
LUT5 #(
.INIT(32'h00100000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2
(.I0(addrb[14]),
.I1(addrb[13]),
.I2(\addrb[17] ),
.I3(\addrb[17]_0 ),
.I4(addrb[15]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized5
(\doutb[3] ,
clka,
clkb,
addra,
addrb,
dina,
\addra[17] ,
\addra[17]_0 ,
addra_13__s_port_,
wea,
\addrb[17] ,
\addrb[17]_0 );
output [3:0]\doutb[3] ;
input clka;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [3:0]dina;
input \addra[17] ;
input \addra[17]_0 ;
input addra_13__s_port_;
input [0:0]wea;
input \addrb[17] ;
input \addrb[17]_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4__0_n_0 ;
wire [15:0]addra;
wire \addra[17] ;
wire \addra[17]_0 ;
wire addra_13__s_net_1;
wire [15:0]addrb;
wire \addrb[17] ;
wire \addrb[17]_0 ;
wire clka;
wire clkb;
wire [3:0]dina;
wire [3:0]\doutb[3] ;
wire ram_ena;
wire ram_enb;
wire [0:0]wea;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
assign addra_13__s_net_1 = addra_13__s_port_;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra[11:0],1'b0,1'b0}),
.ADDRBWRADDR({addrb[11:0],1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],\doutb[3] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ram_ena),
.ENBWREN(ram_enb),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000200000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1
(.I0(addra[15]),
.I1(\addra[17] ),
.I2(\addra[17]_0 ),
.I3(addra_13__s_net_1),
.I4(wea),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4__0_n_0 ),
.O(ram_ena));
LUT6 #(
.INIT(64'h0000000000002000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2__0
(.I0(addrb[15]),
.I1(\addrb[17] ),
.I2(\addrb[17]_0 ),
.I3(addrb[13]),
.I4(addrb[12]),
.I5(addrb[14]),
.O(ram_enb));
LUT3 #(
.INIT(8'hF8))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4__0
(.I0(addra[13]),
.I1(addra[12]),
.I2(addra[14]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized6
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized7
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized8
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized9
(DOUTB,
ENA,
clka,
ENB,
clkb,
addra,
addrb,
dina);
output [0:0]DOUTB;
input ENA;
input clka;
input ENB;
input clkb;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module blk_mem_gen_0_blk_mem_gen_top
(doutb,
addra,
wea,
addrb,
clka,
clkb,
dina);
output [3:0]doutb;
input [18:0]addra;
input [0:0]wea;
input [18:0]addrb;
input clka;
input clkb;
input [3:0]dina;
wire [18:0]addra;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [3:0]dina;
wire [3:0]doutb;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "19" *) (* C_ADDRB_WIDTH = "19" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "3" *)
(* C_COUNT_36K_BRAM = "36" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 16.198881 mW" *) (* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *) (* C_INIT_FILE = "blk_mem_gen_0.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *)
(* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "307200" *)
(* C_READ_DEPTH_B = "307200" *) (* C_READ_WIDTH_A = "4" *) (* C_READ_WIDTH_B = "4" *)
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "307200" *)
(* C_WRITE_DEPTH_B = "307200" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "4" *) (* C_WRITE_WIDTH_B = "4" *) (* C_XDEVICEFAMILY = "zynq" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* downgradeipidentifiedwarnings = "yes" *)
module blk_mem_gen_0_blk_mem_gen_v8_2
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [18:0]addra;
input [3:0]dina;
output [3:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [18:0]addrb;
input [3:0]dinb;
output [3:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [18:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [3:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [3:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [18:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [18:0]addra;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [3:0]dina;
wire [3:0]dinb;
wire [3:0]doutb;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [3:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign douta[3] = \<const0> ;
assign douta[2] = \<const0> ;
assign douta[1] = \<const0> ;
assign douta[0] = \<const0> ;
assign rdaddrecc[18] = \<const0> ;
assign rdaddrecc[17] = \<const0> ;
assign rdaddrecc[16] = \<const0> ;
assign rdaddrecc[15] = \<const0> ;
assign rdaddrecc[14] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[18] = \<const0> ;
assign s_axi_rdaddrecc[17] = \<const0> ;
assign s_axi_rdaddrecc[16] = \<const0> ;
assign s_axi_rdaddrecc[15] = \<const0> ;
assign s_axi_rdaddrecc[14] = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
blk_mem_gen_0_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module blk_mem_gen_0_blk_mem_gen_v8_2_synth
(doutb,
addra,
wea,
addrb,
clka,
clkb,
dina);
output [3:0]doutb;
input [18:0]addra;
input [0:0]wea;
input [18:0]addrb;
input clka;
input clkb;
input [3:0]dina;
wire [18:0]addra;
wire [18:0]addrb;
wire clka;
wire clkb;
wire [3:0]dina;
wire [3:0]doutb;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A21BO_BEHAVIORAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_BEHAVIORAL_V |
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module capture(
// -- clock & reset
input core_clk,
input core_rst,
// -- sample configuration
input cons_mode,
input wireless_mode,
input dso_setZero,
input sample_en,
input full_speed,
input [31:0] sample_depth,
input [31:0] sample_last_cnt,
input [31:0] sample_real_start,
input [31:0] trig_set_pos,
input [31:0] trig_set_pos_minus1,
input [31:0] after_trig_depth,
// -- sample data in
input sample_valid,
input [15:0] sample_data,
// -- trigger control in
input trig_en,
input trig_hit,
input [3:0] trig_dly,
// -- capture control output
output reg dso_setZero_done,
output reg [31:0] trig_real_pos,
output reg capture_done,
output reg [31:0] sd_saddr,
output capture_valid,
output [15:0] capture_data
);
// --
// internal singals definition
// --
reg capture_cnt_valid = 1'b0;
wire caputre_cnt_valid_nxt;
reg [31:0] capture_cnt;
wire [31:0] capture_cnt_nxt;
wire trig_hit_pulse;
reg trig_hit_dly;
wire trig_hit_dly_nxt;
wire capture_done_nxt;
reg [32:0] trig_real_start;
wire [32:0] trig_real_start_nxt;
wire [32:0] sd_saddr_nxt;
reg loop0;
wire loop0_nxt;
wire [15:0] capture_data_pre;
reg capture_valid_pre;
wire capture_valid_pre_nxt;
// --
// capture_cnt record the count(mod sample_depth) before trig_hit
// --
assign trig_hit_pulse = trig_hit & capture_valid_pre & ~trig_hit_dly;
assign trig_hit_dly_nxt = capture_done ? 1'b0 :
trig_hit & capture_valid_pre ? 1'b1 : trig_hit_dly;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
trig_hit_dly <= `D 1'b0;
else
trig_hit_dly <= `D trig_hit_dly_nxt;
end
assign capture_cnt_valid_nxt = capture_done ? 1'b0 :
capture_valid_pre_nxt ? 1'b1 : capture_cnt_valid;
always @(posedge core_clk)
begin
capture_cnt_valid <= `D capture_cnt_valid_nxt;
end
assign capture_cnt_nxt = capture_done ? 32'b0 :
(capture_valid_pre & (capture_cnt == sample_last_cnt)) ? 32'b0 :
(trig_en & ~full_speed & capture_valid_pre & loop0 & trig_hit & (capture_cnt >= trig_set_pos)) ? 32'b0 :
(trig_en & full_speed & capture_valid_pre & loop0 & trig_hit & (capture_cnt >= trig_set_pos_minus1)) ? 32'b0 :
(trig_en & capture_valid_pre & ~loop0 & trig_hit_pulse) ? 32'b0 :
(capture_valid_pre) ? capture_cnt + 1'b1 : capture_cnt;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
capture_cnt <= `D 32'b0;
else
capture_cnt <= `D capture_cnt_nxt;
end
// --
// trigger position
// --
reg sample_en_1T = 1'b0;
reg trig_hit_1T = 1'b0;
reg set_before_real;
wire set_before_real_nxt;
reg trig_real_hit;
wire trig_real_hit_nxt;
always @(posedge core_clk)
begin
sample_en_1T <= `D sample_en;
trig_hit_1T <= `D trig_hit;
end
assign set_before_real_nxt = capture_done ? 1'b0 :
(trig_real_hit & loop0 & capture_cnt < trig_set_pos) ? 1'b1 : set_before_real;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
set_before_real <= `D 1'b0;
else
set_before_real <= `D set_before_real_nxt;
end
assign trig_real_hit_nxt = trig_hit ? 1'b1 :
capture_valid_pre ? 1'b0 : trig_real_hit;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
trig_real_hit <= `D 1'b0;
else
trig_real_hit <= `D trig_real_hit_nxt;
end
assign trig_real_start_nxt = (sample_en & ~sample_en_1T) ? sample_real_start :
(~trig_real_hit & capture_valid_pre & trig_real_start == sample_last_cnt) ? 32'b0 :
(~trig_real_hit & capture_valid_pre) ? trig_real_start + 1'b1 : trig_real_start;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
trig_real_start <= `D 32'b0;
else
trig_real_start <= `D trig_real_start_nxt;
end
assign sd_saddr_nxt = (capture_done & (set_before_real | ~trig_en)) ? 32'b0 :
capture_done ? {trig_real_start[29:0], 2'b0} : sd_saddr;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
sd_saddr <= `D 32'b0;
else
sd_saddr <= `D sd_saddr_nxt;
end
wire [31:0] trig_real_pos_nxt;
reg trig_after;
wire trig_after_nxt;
assign trig_after_nxt = trig_hit ? 1'b1 :
capture_valid_pre ? 1'b0 : trig_after;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
trig_after <= `D 1'b0;
else
trig_after <= `D trig_after_nxt;
end
assign trig_real_pos_nxt = ~trig_en? 32'b0 :
(capture_valid_pre & ~trig_after & trig_real_pos < trig_set_pos) ? trig_real_pos + 1'b1 : trig_real_pos;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
trig_real_pos <= `D 32'b0;
else
trig_real_pos <= `D trig_real_pos_nxt;
end
// --
// capture_done
// --
assign loop0_nxt = capture_done ? 1'b1 :
(~full_speed & capture_valid_pre & capture_cnt >= trig_set_pos) ? 1'b0 :
(full_speed & capture_valid_pre & capture_cnt >= trig_set_pos_minus1) ? 1'b0 : loop0;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
loop0 <= `D 1'b1;
else
loop0 <= `D loop0_nxt;
end
assign capture_done_nxt = capture_done ? 1'b0 :
(~cons_mode & trig_hit & trig_en & capture_cnt_valid & (capture_cnt == after_trig_depth)) ? 1'b1 :
(~cons_mode & trig_hit & ~trig_en & capture_valid_pre & (capture_cnt == sample_last_cnt)) ? 1'b1 : capture_done;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
capture_done <= `D 1'b0;
else
capture_done <= `D capture_done_nxt;
end
// --
// sample_data delay for trigger
// --
// -- fix delay 3T for trigger module delay
wire [15:0] sample_data_fix_dly;
wire sample_valid_fix_dly;
SRL16E sv_fix(.A0(1'b1), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_valid), .Q(sample_valid_fix_dly));
SRL16E s0_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[0]), .Q(sample_data_fix_dly[0]));
SRL16E s1_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[1]), .Q(sample_data_fix_dly[1]));
SRL16E s2_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[2]), .Q(sample_data_fix_dly[2]));
SRL16E s3_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[3]), .Q(sample_data_fix_dly[3]));
SRL16E s4_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[4]), .Q(sample_data_fix_dly[4]));
SRL16E s5_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[5]), .Q(sample_data_fix_dly[5]));
SRL16E s6_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[6]), .Q(sample_data_fix_dly[6]));
SRL16E s7_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[7]), .Q(sample_data_fix_dly[7]));
SRL16E s8_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[8]), .Q(sample_data_fix_dly[8]));
SRL16E s9_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[9]), .Q(sample_data_fix_dly[9]));
SRL16E sa_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[10]), .Q(sample_data_fix_dly[10]));
SRL16E sb_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[11]), .Q(sample_data_fix_dly[11]));
SRL16E sc_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[12]), .Q(sample_data_fix_dly[12]));
SRL16E sd_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[13]), .Q(sample_data_fix_dly[13]));
SRL16E se_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[14]), .Q(sample_data_fix_dly[14]));
SRL16E sf_fix(.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(core_clk), .CE(1'b1), .D(sample_data[15]), .Q(sample_data_fix_dly[15]));
wire sample_valid_dly;
SRL16E sv(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_valid_fix_dly), .Q(sample_valid_dly));
assign capture_valid_pre_nxt = capture_done_nxt ? 1'b0 :
sample_en & ~capture_done? sample_valid_dly : 1'b0;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
capture_valid_pre <= `D 1'b0;
else
capture_valid_pre <= `D capture_valid_pre_nxt;
end
SRL16E s0(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[0]), .Q(capture_data_pre[0]));
SRL16E s1(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[1]), .Q(capture_data_pre[1]));
SRL16E s2(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[2]), .Q(capture_data_pre[2]));
SRL16E s3(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[3]), .Q(capture_data_pre[3]));
SRL16E s4(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[4]), .Q(capture_data_pre[4]));
SRL16E s5(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[5]), .Q(capture_data_pre[5]));
SRL16E s6(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[6]), .Q(capture_data_pre[6]));
SRL16E s7(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[7]), .Q(capture_data_pre[7]));
SRL16E s8(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[8]), .Q(capture_data_pre[8]));
SRL16E s9(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[9]), .Q(capture_data_pre[9]));
SRL16E sa(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[10]), .Q(capture_data_pre[10]));
SRL16E sb(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[11]), .Q(capture_data_pre[11]));
SRL16E sc(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[12]), .Q(capture_data_pre[12]));
SRL16E sd(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[13]), .Q(capture_data_pre[13]));
SRL16E se(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[14]), .Q(capture_data_pre[14]));
SRL16E sf(.A0(trig_dly[0]), .A1(trig_dly[1]), .A2(trig_dly[2]), .A3(trig_dly[3]), .CLK(core_clk), .CE(1'b1), .D(sample_data_fix_dly[15]), .Q(capture_data_pre[15]));
// -- data zero adjustemnt in DSO mode
reg dso_zero = 1'b0;
wire dso_zero_nxt;
wire dso_setZero_done_nxt;
reg [15:0] dso_zero_cnt = 16'b0;
wire [15:0] dso_zero_cnt_nxt;
reg [7:0] ch0_offset = 8'h0;
reg [7:0] ch1_offset = 8'h0;
wire [7:0] ch0_offset_nxt;
wire [7:0] ch1_offset_nxt;
reg ch0_sign = 1'b0;
reg ch1_sign = 1'b0;
wire ch0_sign_nxt;
wire ch1_sign_nxt;
reg [15:0] capture_data_fix;
wire [15:0] capture_data_fix_nxt;
reg [15:0] capture_data_zero;
wire [15:0] capture_data_zero_nxt;
reg capture_valid_pre_1T;
reg capture_valid_pre_2T;
wire capture_valid_zero;
reg zero_capture;
wire zero_capture_nxt;
assign dso_zero_nxt = dso_setZero ? 1'b1 :
dso_setZero_done_nxt ? 1'b0 : dso_zero;
assign dso_zero_cnt_nxt = dso_setZero ? 16'b0 :
(dso_zero & capture_valid_pre) ? dso_zero_cnt + 1'b1 : dso_zero_cnt;
assign dso_setZero_done_nxt = dso_setZero_done ? 1'b0 :
(dso_zero & &dso_zero_cnt) ? 1'b1 : dso_setZero_done;
assign capture_data_fix_nxt = capture_valid_pre ? 16'hffff - capture_data_pre : capture_data_fix;
assign capture_data_zero_nxt[7:0] = (ch0_sign & (capture_data_fix[7:0] > ch0_offset))? capture_data_fix[7:0] - ch0_offset : capture_data_fix[7:0] + ch0_offset;
assign capture_data_zero_nxt[15:8] = (ch1_sign & (capture_data_fix[15:8] > ch1_offset))? capture_data_fix[15:8] - ch1_offset : capture_data_fix[15:8] + ch1_offset;
assign ch0_sign_nxt = dso_zero ? ((capture_data_fix[7:0] > 8'h80) ? 1'b1 : 1'b0) : ch0_sign;
assign ch1_sign_nxt = dso_zero ? ((capture_data_fix[15:8] > 8'h80) ? 1'b1 : 1'b0) : ch1_sign;
assign ch0_offset_nxt = (dso_zero & dso_zero_cnt[15] & ch0_sign) ? (capture_data_fix[7:0] - 8'h80 + ch0_offset) >> 1 :
(dso_zero & dso_zero_cnt[15] & ~ch0_sign) ? (8'h80 - capture_data_fix[7:0] + ch0_offset) >> 1 : ch0_offset;
assign ch1_offset_nxt = (dso_zero & dso_zero_cnt[15] & ch1_sign) ? (capture_data_fix[15:8] - 8'h80 + ch1_offset) >> 1 :
(dso_zero & dso_zero_cnt[15] & ~ch1_sign) ? (8'h80 - capture_data_fix[15:8] + ch1_offset) >> 1 : ch1_offset;
assign zero_capture_nxt = dso_setZero ? 1'b1 :
(capture_valid_pre_2T & ~capture_valid_pre_1T) ? 1'b0 : zero_capture;
always @(posedge core_clk)
begin
dso_zero <= `D dso_zero_nxt;
dso_zero_cnt <= `D dso_zero_cnt_nxt;
dso_setZero_done <= `D dso_setZero_done_nxt;
end
always @(posedge core_clk)
begin
capture_valid_pre_1T <= `D capture_valid_pre;
capture_valid_pre_2T <= `D capture_valid_pre_1T;
capture_data_fix <= `D capture_data_fix_nxt;
capture_data_zero <= `D capture_data_zero_nxt;
ch0_sign <= `D ch0_sign_nxt;
ch1_sign <= `D ch1_sign_nxt;
ch0_offset <= `D ch0_offset_nxt;
ch1_offset <= `D ch1_offset_nxt;
zero_capture <= `D zero_capture_nxt;
end
assign capture_valid_zero = capture_valid_pre_1T & ~zero_capture;
assign capture_data = (cons_mode & !wireless_mode) ? capture_data_zero : capture_data_pre;
assign capture_valid = (cons_mode & !wireless_mode) ? capture_valid_zero : capture_valid_pre;
endmodule
|
/*
* Copyright (c) Mercury Federal Systems, Inc., Arlington VA., 2009-2010
*
* Mercury Federal Systems, Incorporated
* 1901 South Bell Street
* Suite 402
* Arlington, Virginia 22202
* United States of America
* Telephone 703-413-0781
* FAX 703-413-0784
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
//
// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24)
//
// On Thu Jul 1 08:56:10 EDT 2010
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiS1_SThreadBusy O 1
// wsiS1_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 256 reg
// wsiM0_MByteEn O 32 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wsiM1_MCmd O 3
// wsiM1_MReqLast O 1
// wsiM1_MBurstPrecise O 1
// wsiM1_MBurstLength O 12
// wsiM1_MData O 256 reg
// wsiM1_MByteEn O 32 reg
// wsiM1_MReqInfo O 8
// wsiM1_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 20
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 256
// wsiS0_MByteEn I 32
// wsiS0_MReqInfo I 8
// wsiS1_MCmd I 3
// wsiS1_MBurstLength I 12
// wsiS1_MData I 256
// wsiS1_MByteEn I 32
// wsiS1_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiS1_MReqLast I 1
// wsiS1_MBurstPrecise I 1
// wsiS1_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
// wsiM1_SThreadBusy I 1 reg
// wsiM1_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef ORIGINAL
module mkWsiSplitter2x232B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo,
wsiS1_SThreadBusy,
wsiS1_SReset_n,
wsiS1_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
wsiM1_MCmd,
wsiM1_MReqLast,
wsiM1_MBurstPrecise,
wsiM1_MBurstLength,
wsiM1_MData,
wsiM1_MByteEn,
wsiM1_MReqInfo,
wsiM1_SThreadBusy,
wsiM1_MReset_n,
wsiM1_SReset_n);
parameter [31 : 0] ctrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [19 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [255 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [31 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// action method wsiS1_mCmd
input [2 : 0] wsiS1_MCmd;
// action method wsiS1_mReqLast
input wsiS1_MReqLast;
// action method wsiS1_mBurstPrecise
input wsiS1_MBurstPrecise;
// action method wsiS1_mBurstLength
input [11 : 0] wsiS1_MBurstLength;
// action method wsiS1_mData
input [255 : 0] wsiS1_MData;
// action method wsiS1_mByteEn
input [31 : 0] wsiS1_MByteEn;
// action method wsiS1_mReqInfo
input [7 : 0] wsiS1_MReqInfo;
// action method wsiS1_mDataInfo
// value method wsiS1_sThreadBusy
output wsiS1_SThreadBusy;
// value method wsiS1_sReset_n
output wsiS1_SReset_n;
// action method wsiS1_mReset_n
input wsiS1_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [255 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [31 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// value method wsiM1_mCmd
output [2 : 0] wsiM1_MCmd;
// value method wsiM1_mReqLast
output wsiM1_MReqLast;
// value method wsiM1_mBurstPrecise
output wsiM1_MBurstPrecise;
// value method wsiM1_mBurstLength
output [11 : 0] wsiM1_MBurstLength;
// value method wsiM1_mData
output [255 : 0] wsiM1_MData;
// value method wsiM1_mByteEn
output [31 : 0] wsiM1_MByteEn;
// value method wsiM1_mReqInfo
output [7 : 0] wsiM1_MReqInfo;
// value method wsiM1_mDataInfo
// action method wsiM1_sThreadBusy
input wsiM1_SThreadBusy;
// value method wsiM1_mReset_n
output wsiM1_MReset_n;
// action method wsiM1_sReset_n
input wsiM1_SReset_n;
// signals for module outputs
wire [255 : 0] wsiM0_MData, wsiM1_MData;
wire [31 : 0] wciS0_SData, wsiM0_MByteEn, wsiM1_MByteEn;
wire [11 : 0] wsiM0_MBurstLength, wsiM1_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo, wsiM1_MReqInfo;
wire [2 : 0] wsiM0_MCmd, wsiM1_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiM1_MBurstPrecise,
wsiM1_MReqLast,
wsiM1_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy,
wsiS1_SReset_n,
wsiS1_SThreadBusy;
`else
`define NOT_EMPTY_splitter2x2.v
`include "splitter2x2_defs.v"
`endif
// inlined wires
wire [312 : 0] wsi_M0_reqFifo_x_wire$wget,
wsi_M1_reqFifo_x_wire$wget,
wsi_S0_wsiReq$wget,
wsi_S1_wsiReq$wget;
wire [255 : 0] wsi_Es0_mData_w$wget, wsi_Es1_mData_w$wget;
wire [95 : 0] wsi_M0_extStatusW$wget,
wsi_M1_extStatusW$wget,
wsi_S0_extStatusW$wget,
wsi_S1_extStatusW$wget;
wire [59 : 0] wci_wciReq$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] wci_Es_mData_w$wget,
wsi_Es0_mByteEn_w$wget,
wsi_Es1_mByteEn_w$wget;
wire [19 : 0] wci_Es_mAddr_w$wget;
wire [11 : 0] wsi_Es0_mBurstLength_w$wget, wsi_Es1_mBurstLength_w$wget;
wire [7 : 0] wsi_Es0_mReqInfo_w$wget, wsi_Es1_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget,
wci_wEdge$wget,
wsi_Es0_mCmd_w$wget,
wsi_Es1_mCmd_w$wget;
wire wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wsi_Es0_mBurstLength_w$whas,
wsi_Es0_mBurstPrecise_w$whas,
wsi_Es0_mByteEn_w$whas,
wsi_Es0_mCmd_w$whas,
wsi_Es0_mDataInfo_w$whas,
wsi_Es0_mData_w$whas,
wsi_Es0_mReqInfo_w$whas,
wsi_Es0_mReqLast_w$whas,
wsi_Es1_mBurstLength_w$whas,
wsi_Es1_mBurstPrecise_w$whas,
wsi_Es1_mByteEn_w$whas,
wsi_Es1_mCmd_w$whas,
wsi_Es1_mDataInfo_w$whas,
wsi_Es1_mData_w$whas,
wsi_Es1_mReqInfo_w$whas,
wsi_Es1_mReqLast_w$whas,
wsi_M0_operateD_1$wget,
wsi_M0_operateD_1$whas,
wsi_M0_peerIsReady_1$wget,
wsi_M0_peerIsReady_1$whas,
wsi_M0_reqFifo_dequeueing$whas,
wsi_M0_reqFifo_enqueueing$whas,
wsi_M0_reqFifo_x_wire$whas,
wsi_M0_sThreadBusy_pw$whas,
wsi_M1_operateD_1$wget,
wsi_M1_operateD_1$whas,
wsi_M1_peerIsReady_1$wget,
wsi_M1_peerIsReady_1$whas,
wsi_M1_reqFifo_dequeueing$whas,
wsi_M1_reqFifo_enqueueing$whas,
wsi_M1_reqFifo_x_wire$whas,
wsi_M1_sThreadBusy_pw$whas,
wsi_S0_operateD_1$wget,
wsi_S0_operateD_1$whas,
wsi_S0_peerIsReady_1$wget,
wsi_S0_peerIsReady_1$whas,
wsi_S0_reqFifo_r_clr$whas,
wsi_S0_reqFifo_r_deq$whas,
wsi_S0_reqFifo_r_enq$whas,
wsi_S0_wsiReq$whas,
wsi_S1_operateD_1$wget,
wsi_S1_operateD_1$whas,
wsi_S1_peerIsReady_1$wget,
wsi_S1_peerIsReady_1$whas,
wsi_S1_reqFifo_r_clr$whas,
wsi_S1_reqFifo_r_deq$whas,
wsi_S1_reqFifo_r_enq$whas,
wsi_S1_wsiReq$whas;
// register splitCtrl
reg [31 : 0] splitCtrl;
wire [31 : 0] splitCtrl$D_IN;
wire splitCtrl$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wsi_M0_burstKind
reg [1 : 0] wsi_M0_burstKind;
wire [1 : 0] wsi_M0_burstKind$D_IN;
wire wsi_M0_burstKind$EN;
// register wsi_M0_errorSticky
reg wsi_M0_errorSticky;
wire wsi_M0_errorSticky$D_IN, wsi_M0_errorSticky$EN;
// register wsi_M0_iMesgCount
reg [31 : 0] wsi_M0_iMesgCount;
wire [31 : 0] wsi_M0_iMesgCount$D_IN;
wire wsi_M0_iMesgCount$EN;
// register wsi_M0_operateD
reg wsi_M0_operateD;
wire wsi_M0_operateD$D_IN, wsi_M0_operateD$EN;
// register wsi_M0_pMesgCount
reg [31 : 0] wsi_M0_pMesgCount;
wire [31 : 0] wsi_M0_pMesgCount$D_IN;
wire wsi_M0_pMesgCount$EN;
// register wsi_M0_peerIsReady
reg wsi_M0_peerIsReady;
wire wsi_M0_peerIsReady$D_IN, wsi_M0_peerIsReady$EN;
// register wsi_M0_reqFifo_c_r
reg [1 : 0] wsi_M0_reqFifo_c_r;
wire [1 : 0] wsi_M0_reqFifo_c_r$D_IN;
wire wsi_M0_reqFifo_c_r$EN;
// register wsi_M0_reqFifo_q_0
reg [312 : 0] wsi_M0_reqFifo_q_0;
reg [312 : 0] wsi_M0_reqFifo_q_0$D_IN;
wire wsi_M0_reqFifo_q_0$EN;
// register wsi_M0_reqFifo_q_1
reg [312 : 0] wsi_M0_reqFifo_q_1;
reg [312 : 0] wsi_M0_reqFifo_q_1$D_IN;
wire wsi_M0_reqFifo_q_1$EN;
// register wsi_M0_sThreadBusy_d
reg wsi_M0_sThreadBusy_d;
wire wsi_M0_sThreadBusy_d$D_IN, wsi_M0_sThreadBusy_d$EN;
// register wsi_M0_statusR
reg [7 : 0] wsi_M0_statusR;
wire [7 : 0] wsi_M0_statusR$D_IN;
wire wsi_M0_statusR$EN;
// register wsi_M0_tBusyCount
reg [31 : 0] wsi_M0_tBusyCount;
wire [31 : 0] wsi_M0_tBusyCount$D_IN;
wire wsi_M0_tBusyCount$EN;
// register wsi_M0_trafficSticky
reg wsi_M0_trafficSticky;
wire wsi_M0_trafficSticky$D_IN, wsi_M0_trafficSticky$EN;
// register wsi_M1_burstKind
reg [1 : 0] wsi_M1_burstKind;
wire [1 : 0] wsi_M1_burstKind$D_IN;
wire wsi_M1_burstKind$EN;
// register wsi_M1_errorSticky
reg wsi_M1_errorSticky;
wire wsi_M1_errorSticky$D_IN, wsi_M1_errorSticky$EN;
// register wsi_M1_iMesgCount
reg [31 : 0] wsi_M1_iMesgCount;
wire [31 : 0] wsi_M1_iMesgCount$D_IN;
wire wsi_M1_iMesgCount$EN;
// register wsi_M1_operateD
reg wsi_M1_operateD;
wire wsi_M1_operateD$D_IN, wsi_M1_operateD$EN;
// register wsi_M1_pMesgCount
reg [31 : 0] wsi_M1_pMesgCount;
wire [31 : 0] wsi_M1_pMesgCount$D_IN;
wire wsi_M1_pMesgCount$EN;
// register wsi_M1_peerIsReady
reg wsi_M1_peerIsReady;
wire wsi_M1_peerIsReady$D_IN, wsi_M1_peerIsReady$EN;
// register wsi_M1_reqFifo_c_r
reg [1 : 0] wsi_M1_reqFifo_c_r;
wire [1 : 0] wsi_M1_reqFifo_c_r$D_IN;
wire wsi_M1_reqFifo_c_r$EN;
// register wsi_M1_reqFifo_q_0
reg [312 : 0] wsi_M1_reqFifo_q_0;
reg [312 : 0] wsi_M1_reqFifo_q_0$D_IN;
wire wsi_M1_reqFifo_q_0$EN;
// register wsi_M1_reqFifo_q_1
reg [312 : 0] wsi_M1_reqFifo_q_1;
reg [312 : 0] wsi_M1_reqFifo_q_1$D_IN;
wire wsi_M1_reqFifo_q_1$EN;
// register wsi_M1_sThreadBusy_d
reg wsi_M1_sThreadBusy_d;
wire wsi_M1_sThreadBusy_d$D_IN, wsi_M1_sThreadBusy_d$EN;
// register wsi_M1_statusR
reg [7 : 0] wsi_M1_statusR;
wire [7 : 0] wsi_M1_statusR$D_IN;
wire wsi_M1_statusR$EN;
// register wsi_M1_tBusyCount
reg [31 : 0] wsi_M1_tBusyCount;
wire [31 : 0] wsi_M1_tBusyCount$D_IN;
wire wsi_M1_tBusyCount$EN;
// register wsi_M1_trafficSticky
reg wsi_M1_trafficSticky;
wire wsi_M1_trafficSticky$D_IN, wsi_M1_trafficSticky$EN;
// register wsi_S0_burstKind
reg [1 : 0] wsi_S0_burstKind;
wire [1 : 0] wsi_S0_burstKind$D_IN;
wire wsi_S0_burstKind$EN;
// register wsi_S0_errorSticky
reg wsi_S0_errorSticky;
wire wsi_S0_errorSticky$D_IN, wsi_S0_errorSticky$EN;
// register wsi_S0_iMesgCount
reg [31 : 0] wsi_S0_iMesgCount;
wire [31 : 0] wsi_S0_iMesgCount$D_IN;
wire wsi_S0_iMesgCount$EN;
// register wsi_S0_operateD
reg wsi_S0_operateD;
wire wsi_S0_operateD$D_IN, wsi_S0_operateD$EN;
// register wsi_S0_pMesgCount
reg [31 : 0] wsi_S0_pMesgCount;
wire [31 : 0] wsi_S0_pMesgCount$D_IN;
wire wsi_S0_pMesgCount$EN;
// register wsi_S0_peerIsReady
reg wsi_S0_peerIsReady;
wire wsi_S0_peerIsReady$D_IN, wsi_S0_peerIsReady$EN;
// register wsi_S0_reqFifo_countReg
reg [1 : 0] wsi_S0_reqFifo_countReg;
wire [1 : 0] wsi_S0_reqFifo_countReg$D_IN;
wire wsi_S0_reqFifo_countReg$EN;
// register wsi_S0_statusR
reg [7 : 0] wsi_S0_statusR;
wire [7 : 0] wsi_S0_statusR$D_IN;
wire wsi_S0_statusR$EN;
// register wsi_S0_tBusyCount
reg [31 : 0] wsi_S0_tBusyCount;
wire [31 : 0] wsi_S0_tBusyCount$D_IN;
wire wsi_S0_tBusyCount$EN;
// register wsi_S0_trafficSticky
reg wsi_S0_trafficSticky;
wire wsi_S0_trafficSticky$D_IN, wsi_S0_trafficSticky$EN;
// register wsi_S1_burstKind
reg [1 : 0] wsi_S1_burstKind;
wire [1 : 0] wsi_S1_burstKind$D_IN;
wire wsi_S1_burstKind$EN;
// register wsi_S1_errorSticky
reg wsi_S1_errorSticky;
wire wsi_S1_errorSticky$D_IN, wsi_S1_errorSticky$EN;
// register wsi_S1_iMesgCount
reg [31 : 0] wsi_S1_iMesgCount;
wire [31 : 0] wsi_S1_iMesgCount$D_IN;
wire wsi_S1_iMesgCount$EN;
// register wsi_S1_operateD
reg wsi_S1_operateD;
wire wsi_S1_operateD$D_IN, wsi_S1_operateD$EN;
// register wsi_S1_pMesgCount
reg [31 : 0] wsi_S1_pMesgCount;
wire [31 : 0] wsi_S1_pMesgCount$D_IN;
wire wsi_S1_pMesgCount$EN;
// register wsi_S1_peerIsReady
reg wsi_S1_peerIsReady;
wire wsi_S1_peerIsReady$D_IN, wsi_S1_peerIsReady$EN;
// register wsi_S1_reqFifo_countReg
reg [1 : 0] wsi_S1_reqFifo_countReg;
wire [1 : 0] wsi_S1_reqFifo_countReg$D_IN;
wire wsi_S1_reqFifo_countReg$EN;
// register wsi_S1_statusR
reg [7 : 0] wsi_S1_statusR;
wire [7 : 0] wsi_S1_statusR$D_IN;
wire wsi_S1_statusR$EN;
// register wsi_S1_tBusyCount
reg [31 : 0] wsi_S1_tBusyCount;
wire [31 : 0] wsi_S1_tBusyCount$D_IN;
wire wsi_S1_tBusyCount$EN;
// register wsi_S1_trafficSticky
reg wsi_S1_trafficSticky;
wire wsi_S1_trafficSticky$D_IN, wsi_S1_trafficSticky$EN;
// ports of submodule wci_isReset
wire wci_isReset$VAL;
// ports of submodule wci_reqF
wire [59 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wsi_M0_isReset
wire wsi_M0_isReset$VAL;
// ports of submodule wsi_M1_isReset
wire wsi_M1_isReset$VAL;
// ports of submodule wsi_S0_isReset
wire wsi_S0_isReset$VAL;
// ports of submodule wsi_S0_reqFifo
wire [312 : 0] wsi_S0_reqFifo$D_IN, wsi_S0_reqFifo$D_OUT;
wire wsi_S0_reqFifo$CLR,
wsi_S0_reqFifo$DEQ,
wsi_S0_reqFifo$EMPTY_N,
wsi_S0_reqFifo$ENQ,
wsi_S0_reqFifo$FULL_N;
// ports of submodule wsi_S1_isReset
wire wsi_S1_isReset$VAL;
// ports of submodule wsi_S1_reqFifo
wire [312 : 0] wsi_S1_reqFifo$D_IN, wsi_S1_reqFifo$D_OUT;
wire wsi_S1_reqFifo$CLR,
wsi_S1_reqFifo$DEQ,
wsi_S1_reqFifo$EMPTY_N,
wsi_S1_reqFifo$ENQ,
wsi_S1_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_doMessageConsume_S0,
CAN_FIRE_RL_doMessageConsume_S1,
CAN_FIRE_RL_operating_actions,
CAN_FIRE_RL_wci_Es_doAlways_Req,
CAN_FIRE_RL_wci_cfrd,
CAN_FIRE_RL_wci_cfwr,
CAN_FIRE_RL_wci_ctlAckReg__dreg_update,
CAN_FIRE_RL_wci_ctl_op_complete,
CAN_FIRE_RL_wci_ctl_op_start,
CAN_FIRE_RL_wci_ctrl_EiI,
CAN_FIRE_RL_wci_ctrl_IsO,
CAN_FIRE_RL_wci_ctrl_OrE,
CAN_FIRE_RL_wci_reqF__updateLevelCounter,
CAN_FIRE_RL_wci_reqF_enq,
CAN_FIRE_RL_wci_request_decode,
CAN_FIRE_RL_wci_respF_both,
CAN_FIRE_RL_wci_respF_decCtr,
CAN_FIRE_RL_wci_respF_deq,
CAN_FIRE_RL_wci_respF_incCtr,
CAN_FIRE_RL_wci_sFlagReg__dreg_update,
CAN_FIRE_RL_wci_sThreadBusy_reg,
CAN_FIRE_RL_wsi_Es0_doAlways,
CAN_FIRE_RL_wsi_Es1_doAlways,
CAN_FIRE_RL_wsi_M0_ext_status_assign,
CAN_FIRE_RL_wsi_M0_inc_tBusyCount,
CAN_FIRE_RL_wsi_M0_operateD__dreg_update,
CAN_FIRE_RL_wsi_M0_peerIsReady__dreg_update,
CAN_FIRE_RL_wsi_M0_reqFifo_both,
CAN_FIRE_RL_wsi_M0_reqFifo_decCtr,
CAN_FIRE_RL_wsi_M0_reqFifo_deq,
CAN_FIRE_RL_wsi_M0_reqFifo_incCtr,
CAN_FIRE_RL_wsi_M0_sThreadBusy_reg,
CAN_FIRE_RL_wsi_M0_update_statusR,
CAN_FIRE_RL_wsi_M1_ext_status_assign,
CAN_FIRE_RL_wsi_M1_inc_tBusyCount,
CAN_FIRE_RL_wsi_M1_operateD__dreg_update,
CAN_FIRE_RL_wsi_M1_peerIsReady__dreg_update,
CAN_FIRE_RL_wsi_M1_reqFifo_both,
CAN_FIRE_RL_wsi_M1_reqFifo_decCtr,
CAN_FIRE_RL_wsi_M1_reqFifo_deq,
CAN_FIRE_RL_wsi_M1_reqFifo_incCtr,
CAN_FIRE_RL_wsi_M1_sThreadBusy_reg,
CAN_FIRE_RL_wsi_M1_update_statusR,
CAN_FIRE_RL_wsi_S0_ext_status_assign,
CAN_FIRE_RL_wsi_S0_inc_tBusyCount,
CAN_FIRE_RL_wsi_S0_operateD__dreg_update,
CAN_FIRE_RL_wsi_S0_peerIsReady__dreg_update,
CAN_FIRE_RL_wsi_S0_reqFifo__updateLevelCounter,
CAN_FIRE_RL_wsi_S0_reqFifo_enq,
CAN_FIRE_RL_wsi_S0_update_statusR,
CAN_FIRE_RL_wsi_S1_ext_status_assign,
CAN_FIRE_RL_wsi_S1_inc_tBusyCount,
CAN_FIRE_RL_wsi_S1_operateD__dreg_update,
CAN_FIRE_RL_wsi_S1_peerIsReady__dreg_update,
CAN_FIRE_RL_wsi_S1_reqFifo__updateLevelCounter,
CAN_FIRE_RL_wsi_S1_reqFifo_enq,
CAN_FIRE_RL_wsi_S1_update_statusR,
CAN_FIRE_wciS0_mAddr,
CAN_FIRE_wciS0_mAddrSpace,
CAN_FIRE_wciS0_mByteEn,
CAN_FIRE_wciS0_mCmd,
CAN_FIRE_wciS0_mData,
CAN_FIRE_wciS0_mFlag,
CAN_FIRE_wsiM0_sReset_n,
CAN_FIRE_wsiM0_sThreadBusy,
CAN_FIRE_wsiM1_sReset_n,
CAN_FIRE_wsiM1_sThreadBusy,
CAN_FIRE_wsiS0_mBurstLength,
CAN_FIRE_wsiS0_mBurstPrecise,
CAN_FIRE_wsiS0_mByteEn,
CAN_FIRE_wsiS0_mCmd,
CAN_FIRE_wsiS0_mData,
CAN_FIRE_wsiS0_mDataInfo,
CAN_FIRE_wsiS0_mReqInfo,
CAN_FIRE_wsiS0_mReqLast,
CAN_FIRE_wsiS0_mReset_n,
CAN_FIRE_wsiS1_mBurstLength,
CAN_FIRE_wsiS1_mBurstPrecise,
CAN_FIRE_wsiS1_mByteEn,
CAN_FIRE_wsiS1_mCmd,
CAN_FIRE_wsiS1_mData,
CAN_FIRE_wsiS1_mDataInfo,
CAN_FIRE_wsiS1_mReqInfo,
CAN_FIRE_wsiS1_mReqLast,
CAN_FIRE_wsiS1_mReset_n,
WILL_FIRE_RL_doMessageConsume_S0,
WILL_FIRE_RL_doMessageConsume_S1,
WILL_FIRE_RL_operating_actions,
WILL_FIRE_RL_wci_Es_doAlways_Req,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctlAckReg__dreg_update,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_reqF__updateLevelCounter,
WILL_FIRE_RL_wci_reqF_enq,
WILL_FIRE_RL_wci_request_decode,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_deq,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wci_sFlagReg__dreg_update,
WILL_FIRE_RL_wci_sThreadBusy_reg,
WILL_FIRE_RL_wsi_Es0_doAlways,
WILL_FIRE_RL_wsi_Es1_doAlways,
WILL_FIRE_RL_wsi_M0_ext_status_assign,
WILL_FIRE_RL_wsi_M0_inc_tBusyCount,
WILL_FIRE_RL_wsi_M0_operateD__dreg_update,
WILL_FIRE_RL_wsi_M0_peerIsReady__dreg_update,
WILL_FIRE_RL_wsi_M0_reqFifo_both,
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr,
WILL_FIRE_RL_wsi_M0_reqFifo_deq,
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr,
WILL_FIRE_RL_wsi_M0_sThreadBusy_reg,
WILL_FIRE_RL_wsi_M0_update_statusR,
WILL_FIRE_RL_wsi_M1_ext_status_assign,
WILL_FIRE_RL_wsi_M1_inc_tBusyCount,
WILL_FIRE_RL_wsi_M1_operateD__dreg_update,
WILL_FIRE_RL_wsi_M1_peerIsReady__dreg_update,
WILL_FIRE_RL_wsi_M1_reqFifo_both,
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr,
WILL_FIRE_RL_wsi_M1_reqFifo_deq,
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr,
WILL_FIRE_RL_wsi_M1_sThreadBusy_reg,
WILL_FIRE_RL_wsi_M1_update_statusR,
WILL_FIRE_RL_wsi_S0_ext_status_assign,
WILL_FIRE_RL_wsi_S0_inc_tBusyCount,
WILL_FIRE_RL_wsi_S0_operateD__dreg_update,
WILL_FIRE_RL_wsi_S0_peerIsReady__dreg_update,
WILL_FIRE_RL_wsi_S0_reqFifo__updateLevelCounter,
WILL_FIRE_RL_wsi_S0_reqFifo_enq,
WILL_FIRE_RL_wsi_S0_update_statusR,
WILL_FIRE_RL_wsi_S1_ext_status_assign,
WILL_FIRE_RL_wsi_S1_inc_tBusyCount,
WILL_FIRE_RL_wsi_S1_operateD__dreg_update,
WILL_FIRE_RL_wsi_S1_peerIsReady__dreg_update,
WILL_FIRE_RL_wsi_S1_reqFifo__updateLevelCounter,
WILL_FIRE_RL_wsi_S1_reqFifo_enq,
WILL_FIRE_RL_wsi_S1_update_statusR,
WILL_FIRE_wciS0_mAddr,
WILL_FIRE_wciS0_mAddrSpace,
WILL_FIRE_wciS0_mByteEn,
WILL_FIRE_wciS0_mCmd,
WILL_FIRE_wciS0_mData,
WILL_FIRE_wciS0_mFlag,
WILL_FIRE_wsiM0_sReset_n,
WILL_FIRE_wsiM0_sThreadBusy,
WILL_FIRE_wsiM1_sReset_n,
WILL_FIRE_wsiM1_sThreadBusy,
WILL_FIRE_wsiS0_mBurstLength,
WILL_FIRE_wsiS0_mBurstPrecise,
WILL_FIRE_wsiS0_mByteEn,
WILL_FIRE_wsiS0_mCmd,
WILL_FIRE_wsiS0_mData,
WILL_FIRE_wsiS0_mDataInfo,
WILL_FIRE_wsiS0_mReqInfo,
WILL_FIRE_wsiS0_mReqLast,
WILL_FIRE_wsiS0_mReset_n,
WILL_FIRE_wsiS1_mBurstLength,
WILL_FIRE_wsiS1_mBurstPrecise,
WILL_FIRE_wsiS1_mByteEn,
WILL_FIRE_wsiS1_mCmd,
WILL_FIRE_wsiS1_mData,
WILL_FIRE_wsiS1_mDataInfo,
WILL_FIRE_wsiS1_mReqInfo,
WILL_FIRE_wsiS1_mReqLast,
WILL_FIRE_wsiS1_mReset_n;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2;
wire [312 : 0] MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1,
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2,
MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2,
MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1,
MUX_wci_respF_q_1$write_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1,
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2,
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1,
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2;
wire MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_2,
MUX_wci_illegalEdge$write_1__VAL_2,
MUX_wci_respF_q_0$write_1__SEL_2,
MUX_wci_respF_q_1$write_1__SEL_2,
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2,
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2,
MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2,
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2,
MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h13749, v__h14297, v__h2633, v__h2780, v__h3679;
reg [31 : 0] _theResult____h13733;
wire [31 : 0] rdat__h13812,
rdat__h14001,
rdat__h14015,
rdat__h14023,
rdat__h14037,
rdat__h14045,
rdat__h14059,
rdat__h14067,
rdat__h14081;
wire NOT_wsi_S0_reqFifo_countReg_95_ULE_1_96___d397,
NOT_wsi_S1_reqFifo_countReg_31_ULE_1_32___d333;
// action method wciS0_mCmd
assign CAN_FIRE_wciS0_mCmd = 1'd1 ;
assign WILL_FIRE_wciS0_mCmd = 1'd1 ;
// action method wciS0_mAddrSpace
assign CAN_FIRE_wciS0_mAddrSpace = 1'd1 ;
assign WILL_FIRE_wciS0_mAddrSpace = 1'd1 ;
// action method wciS0_mByteEn
assign CAN_FIRE_wciS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wciS0_mByteEn = 1'd1 ;
// action method wciS0_mAddr
assign CAN_FIRE_wciS0_mAddr = 1'd1 ;
assign WILL_FIRE_wciS0_mAddr = 1'd1 ;
// action method wciS0_mData
assign CAN_FIRE_wciS0_mData = 1'd1 ;
assign WILL_FIRE_wciS0_mData = 1'd1 ;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy = wci_reqF_countReg > 2'd1 || wci_isReset$VAL ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// action method wciS0_mFlag
assign CAN_FIRE_wciS0_mFlag = 1'd1 ;
assign WILL_FIRE_wciS0_mFlag = 1'd1 ;
// action method wsiS0_mCmd
assign CAN_FIRE_wsiS0_mCmd = 1'd1 ;
assign WILL_FIRE_wsiS0_mCmd = 1'd1 ;
// action method wsiS0_mReqLast
assign CAN_FIRE_wsiS0_mReqLast = 1'd1 ;
assign WILL_FIRE_wsiS0_mReqLast = wsiS0_MReqLast ;
// action method wsiS0_mBurstPrecise
assign CAN_FIRE_wsiS0_mBurstPrecise = 1'd1 ;
assign WILL_FIRE_wsiS0_mBurstPrecise = wsiS0_MBurstPrecise ;
// action method wsiS0_mBurstLength
assign CAN_FIRE_wsiS0_mBurstLength = 1'd1 ;
assign WILL_FIRE_wsiS0_mBurstLength = 1'd1 ;
// action method wsiS0_mData
assign CAN_FIRE_wsiS0_mData = 1'd1 ;
assign WILL_FIRE_wsiS0_mData = 1'd1 ;
// action method wsiS0_mByteEn
assign CAN_FIRE_wsiS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wsiS0_mByteEn = 1'd1 ;
// action method wsiS0_mReqInfo
assign CAN_FIRE_wsiS0_mReqInfo = 1'd1 ;
assign WILL_FIRE_wsiS0_mReqInfo = 1'd1 ;
// action method wsiS0_mDataInfo
assign CAN_FIRE_wsiS0_mDataInfo = 1'd1 ;
assign WILL_FIRE_wsiS0_mDataInfo = 1'd1 ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
NOT_wsi_S0_reqFifo_countReg_95_ULE_1_96___d397 ||
wsi_S0_isReset$VAL ||
!wsi_S0_operateD ||
!wsi_S0_peerIsReady ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsi_S0_isReset$VAL && wsi_S0_operateD ;
// action method wsiS0_mReset_n
assign CAN_FIRE_wsiS0_mReset_n = 1'd1 ;
assign WILL_FIRE_wsiS0_mReset_n = wsiS0_MReset_n ;
// action method wsiS1_mCmd
assign CAN_FIRE_wsiS1_mCmd = 1'd1 ;
assign WILL_FIRE_wsiS1_mCmd = 1'd1 ;
// action method wsiS1_mReqLast
assign CAN_FIRE_wsiS1_mReqLast = 1'd1 ;
assign WILL_FIRE_wsiS1_mReqLast = wsiS1_MReqLast ;
// action method wsiS1_mBurstPrecise
assign CAN_FIRE_wsiS1_mBurstPrecise = 1'd1 ;
assign WILL_FIRE_wsiS1_mBurstPrecise = wsiS1_MBurstPrecise ;
// action method wsiS1_mBurstLength
assign CAN_FIRE_wsiS1_mBurstLength = 1'd1 ;
assign WILL_FIRE_wsiS1_mBurstLength = 1'd1 ;
// action method wsiS1_mData
assign CAN_FIRE_wsiS1_mData = 1'd1 ;
assign WILL_FIRE_wsiS1_mData = 1'd1 ;
// action method wsiS1_mByteEn
assign CAN_FIRE_wsiS1_mByteEn = 1'd1 ;
assign WILL_FIRE_wsiS1_mByteEn = 1'd1 ;
// action method wsiS1_mReqInfo
assign CAN_FIRE_wsiS1_mReqInfo = 1'd1 ;
assign WILL_FIRE_wsiS1_mReqInfo = 1'd1 ;
// action method wsiS1_mDataInfo
assign CAN_FIRE_wsiS1_mDataInfo = 1'd1 ;
assign WILL_FIRE_wsiS1_mDataInfo = 1'd1 ;
// value method wsiS1_sThreadBusy
assign wsiS1_SThreadBusy =
NOT_wsi_S1_reqFifo_countReg_31_ULE_1_32___d333 ||
wsi_S1_isReset$VAL ||
!wsi_S1_operateD ||
!wsi_S1_peerIsReady ;
// value method wsiS1_sReset_n
assign wsiS1_SReset_n = !wsi_S1_isReset$VAL && wsi_S1_operateD ;
// action method wsiS1_mReset_n
assign CAN_FIRE_wsiS1_mReset_n = 1'd1 ;
assign WILL_FIRE_wsiS1_mReset_n = wsiS1_MReset_n ;
// value method wsiM0_mCmd
assign wsiM0_MCmd =
wsi_M0_sThreadBusy_d ? 3'd0 : wsi_M0_reqFifo_q_0[312:310] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[309] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise =
!wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[308] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsi_M0_sThreadBusy_d ? 12'd0 : wsi_M0_reqFifo_q_0[307:296] ;
// value method wsiM0_mData
assign wsiM0_MData = wsi_M0_reqFifo_q_0[295:40] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsi_M0_reqFifo_q_0[39:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo =
wsi_M0_sThreadBusy_d ? 8'd0 : wsi_M0_reqFifo_q_0[7:0] ;
// action method wsiM0_sThreadBusy
assign CAN_FIRE_wsiM0_sThreadBusy = 1'd1 ;
assign WILL_FIRE_wsiM0_sThreadBusy = wsiM0_SThreadBusy ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsi_M0_isReset$VAL && wsi_M0_operateD ;
// action method wsiM0_sReset_n
assign CAN_FIRE_wsiM0_sReset_n = 1'd1 ;
assign WILL_FIRE_wsiM0_sReset_n = wsiM0_SReset_n ;
// value method wsiM1_mCmd
assign wsiM1_MCmd =
wsi_M1_sThreadBusy_d ? 3'd0 : wsi_M1_reqFifo_q_0[312:310] ;
// value method wsiM1_mReqLast
assign wsiM1_MReqLast = !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[309] ;
// value method wsiM1_mBurstPrecise
assign wsiM1_MBurstPrecise =
!wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[308] ;
// value method wsiM1_mBurstLength
assign wsiM1_MBurstLength =
wsi_M1_sThreadBusy_d ? 12'd0 : wsi_M1_reqFifo_q_0[307:296] ;
// value method wsiM1_mData
assign wsiM1_MData = wsi_M1_reqFifo_q_0[295:40] ;
// value method wsiM1_mByteEn
assign wsiM1_MByteEn = wsi_M1_reqFifo_q_0[39:8] ;
// value method wsiM1_mReqInfo
assign wsiM1_MReqInfo =
wsi_M1_sThreadBusy_d ? 8'd0 : wsi_M1_reqFifo_q_0[7:0] ;
// action method wsiM1_sThreadBusy
assign CAN_FIRE_wsiM1_sThreadBusy = 1'd1 ;
assign WILL_FIRE_wsiM1_sThreadBusy = wsiM1_SThreadBusy ;
// value method wsiM1_mReset_n
assign wsiM1_MReset_n = !wsi_M1_isReset$VAL && wsi_M1_operateD ;
// action method wsiM1_sReset_n
assign CAN_FIRE_wsiM1_sReset_n = 1'd1 ;
assign WILL_FIRE_wsiM1_sReset_n = wsiM1_SReset_n ;
// submodule wci_isReset
ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset$VAL));
// submodule wci_reqF
SizedFIFO #(.p1width(32'd60),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wsi_M0_isReset
ResetToBool wsi_M0_isReset(.RST(wciS0_MReset_n), .VAL(wsi_M0_isReset$VAL));
// submodule wsi_M1_isReset
ResetToBool wsi_M1_isReset(.RST(wciS0_MReset_n), .VAL(wsi_M1_isReset$VAL));
// submodule wsi_S0_isReset
ResetToBool wsi_S0_isReset(.RST(wciS0_MReset_n), .VAL(wsi_S0_isReset$VAL));
// submodule wsi_S0_reqFifo
SizedFIFO #(.p1width(32'd313),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsi_S0_reqFifo(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsi_S0_reqFifo$D_IN),
.ENQ(wsi_S0_reqFifo$ENQ),
.DEQ(wsi_S0_reqFifo$DEQ),
.CLR(wsi_S0_reqFifo$CLR),
.D_OUT(wsi_S0_reqFifo$D_OUT),
.FULL_N(wsi_S0_reqFifo$FULL_N),
.EMPTY_N(wsi_S0_reqFifo$EMPTY_N));
// submodule wsi_S1_isReset
ResetToBool wsi_S1_isReset(.RST(wciS0_MReset_n), .VAL(wsi_S1_isReset$VAL));
// submodule wsi_S1_reqFifo
SizedFIFO #(.p1width(32'd313),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsi_S1_reqFifo(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsi_S1_reqFifo$D_IN),
.ENQ(wsi_S1_reqFifo$ENQ),
.DEQ(wsi_S1_reqFifo$DEQ),
.CLR(wsi_S1_reqFifo$CLR),
.D_OUT(wsi_S1_reqFifo$D_OUT),
.FULL_N(wsi_S1_reqFifo$FULL_N),
.EMPTY_N(wsi_S1_reqFifo$EMPTY_N));
// rule RL_wci_request_decode
assign CAN_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
assign WILL_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
// rule RL_wci_ctl_op_start
assign CAN_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas ;
assign WILL_FIRE_RL_wci_ctl_op_start =
CAN_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign CAN_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ;
// rule RL_wci_ctrl_IsO
assign CAN_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ;
// rule RL_wci_ctrl_OrE
assign CAN_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ;
// rule RL_operating_actions
assign CAN_FIRE_RL_operating_actions = wci_cState == 3'd2 ;
assign WILL_FIRE_RL_operating_actions = CAN_FIRE_RL_operating_actions ;
// rule RL_wci_Es_doAlways_Req
assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
// rule RL_wci_respF_deq
assign CAN_FIRE_RL_wci_respF_deq = 1'd1 ;
assign WILL_FIRE_RL_wci_respF_deq = 1'd1 ;
// rule RL_wci_reqF_enq
assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq$wget[59:57] != 3'd0 ;
assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ;
// rule RL_wci_sThreadBusy_reg
assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
// rule RL_wci_sFlagReg__dreg_update
assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
// rule RL_wsi_Es1_doAlways
assign CAN_FIRE_RL_wsi_Es1_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wsi_Es1_doAlways = 1'd1 ;
// rule RL_wsi_Es0_doAlways
assign CAN_FIRE_RL_wsi_Es0_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wsi_Es0_doAlways = 1'd1 ;
// rule RL_wsi_M1_update_statusR
assign CAN_FIRE_RL_wsi_M1_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsi_M1_update_statusR = 1'd1 ;
// rule RL_wsi_M1_ext_status_assign
assign CAN_FIRE_RL_wsi_M1_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsi_M1_ext_status_assign = 1'd1 ;
// rule RL_wsi_M1_inc_tBusyCount
assign CAN_FIRE_RL_wsi_M1_inc_tBusyCount =
wsi_M1_operateD && wsi_M1_peerIsReady && wsi_M1_sThreadBusy_d ;
assign WILL_FIRE_RL_wsi_M1_inc_tBusyCount =
CAN_FIRE_RL_wsi_M1_inc_tBusyCount ;
// rule RL_wsi_M1_reqFifo_deq
assign CAN_FIRE_RL_wsi_M1_reqFifo_deq =
wsi_M1_reqFifo_c_r != 2'd0 && !wsi_M1_sThreadBusy_d ;
assign WILL_FIRE_RL_wsi_M1_reqFifo_deq = CAN_FIRE_RL_wsi_M1_reqFifo_deq ;
// rule RL_wsi_M1_sThreadBusy_reg
assign CAN_FIRE_RL_wsi_M1_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wsi_M1_sThreadBusy_reg = 1'd1 ;
// rule RL_wsi_M1_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsi_M1_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsi_M1_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsi_M1_operateD__dreg_update
assign CAN_FIRE_RL_wsi_M1_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsi_M1_operateD__dreg_update = 1'd1 ;
// rule RL_wsi_M0_update_statusR
assign CAN_FIRE_RL_wsi_M0_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsi_M0_update_statusR = 1'd1 ;
// rule RL_wsi_M0_ext_status_assign
assign CAN_FIRE_RL_wsi_M0_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsi_M0_ext_status_assign = 1'd1 ;
// rule RL_wsi_M0_inc_tBusyCount
assign CAN_FIRE_RL_wsi_M0_inc_tBusyCount =
wsi_M0_operateD && wsi_M0_peerIsReady && wsi_M0_sThreadBusy_d ;
assign WILL_FIRE_RL_wsi_M0_inc_tBusyCount =
CAN_FIRE_RL_wsi_M0_inc_tBusyCount ;
// rule RL_wsi_M0_reqFifo_deq
assign CAN_FIRE_RL_wsi_M0_reqFifo_deq =
wsi_M0_reqFifo_c_r != 2'd0 && !wsi_M0_sThreadBusy_d ;
assign WILL_FIRE_RL_wsi_M0_reqFifo_deq = CAN_FIRE_RL_wsi_M0_reqFifo_deq ;
// rule RL_wsi_M0_sThreadBusy_reg
assign CAN_FIRE_RL_wsi_M0_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wsi_M0_sThreadBusy_reg = 1'd1 ;
// rule RL_wsi_M0_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsi_M0_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsi_M0_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsi_M0_operateD__dreg_update
assign CAN_FIRE_RL_wsi_M0_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsi_M0_operateD__dreg_update = 1'd1 ;
// rule RL_wsi_S1_update_statusR
assign CAN_FIRE_RL_wsi_S1_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsi_S1_update_statusR = 1'd1 ;
// rule RL_wsi_S1_ext_status_assign
assign CAN_FIRE_RL_wsi_S1_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsi_S1_ext_status_assign = 1'd1 ;
// rule RL_wsi_S1_inc_tBusyCount
assign CAN_FIRE_RL_wsi_S1_inc_tBusyCount =
wsi_S1_operateD && wsi_S1_peerIsReady &&
NOT_wsi_S1_reqFifo_countReg_31_ULE_1_32___d333 ;
assign WILL_FIRE_RL_wsi_S1_inc_tBusyCount =
CAN_FIRE_RL_wsi_S1_inc_tBusyCount ;
// rule RL_wsi_S1_reqFifo_enq
assign CAN_FIRE_RL_wsi_S1_reqFifo_enq =
wsi_S1_operateD && wsi_S1_peerIsReady &&
wsi_S1_wsiReq$wget[312:310] == 3'd1 ;
assign WILL_FIRE_RL_wsi_S1_reqFifo_enq = CAN_FIRE_RL_wsi_S1_reqFifo_enq ;
// rule RL_doMessageConsume_S1
assign CAN_FIRE_RL_doMessageConsume_S1 =
wsi_S1_reqFifo$EMPTY_N &&
(!splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) &&
(!splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 ;
assign WILL_FIRE_RL_doMessageConsume_S1 = CAN_FIRE_RL_doMessageConsume_S1 ;
// rule RL_wsi_S1_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsi_S1_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsi_S1_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsi_S1_operateD__dreg_update
assign CAN_FIRE_RL_wsi_S1_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsi_S1_operateD__dreg_update = 1'd1 ;
// rule RL_wsi_S1_reqFifo__updateLevelCounter
assign CAN_FIRE_RL_wsi_S1_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsi_S1_reqFifo_enq !=
CAN_FIRE_RL_doMessageConsume_S1 ;
assign WILL_FIRE_RL_wsi_S1_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsi_S1_reqFifo__updateLevelCounter ;
// rule RL_wsi_S0_update_statusR
assign CAN_FIRE_RL_wsi_S0_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsi_S0_update_statusR = 1'd1 ;
// rule RL_wsi_S0_ext_status_assign
assign CAN_FIRE_RL_wsi_S0_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsi_S0_ext_status_assign = 1'd1 ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_reqF$EMPTY_N && wci_respF_c_r != 2'd2 &&
wci_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wsi_S0_inc_tBusyCount
assign CAN_FIRE_RL_wsi_S0_inc_tBusyCount =
wsi_S0_operateD && wsi_S0_peerIsReady &&
NOT_wsi_S0_reqFifo_countReg_95_ULE_1_96___d397 ;
assign WILL_FIRE_RL_wsi_S0_inc_tBusyCount =
CAN_FIRE_RL_wsi_S0_inc_tBusyCount ;
// rule RL_wsi_S0_reqFifo_enq
assign CAN_FIRE_RL_wsi_S0_reqFifo_enq =
wsi_S0_operateD && wsi_S0_peerIsReady &&
wsi_S0_wsiReq$wget[312:310] == 3'd1 ;
assign WILL_FIRE_RL_wsi_S0_reqFifo_enq = CAN_FIRE_RL_wsi_S0_reqFifo_enq ;
// rule RL_doMessageConsume_S0
assign CAN_FIRE_RL_doMessageConsume_S0 =
wsi_S0_reqFifo$EMPTY_N &&
(splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) &&
(splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 ;
assign WILL_FIRE_RL_doMessageConsume_S0 =
CAN_FIRE_RL_doMessageConsume_S0 &&
!WILL_FIRE_RL_doMessageConsume_S1 ;
// rule RL_wci_ctl_op_complete
assign CAN_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_cfwr
assign CAN_FIRE_RL_wci_cfwr =
wci_reqF$EMPTY_N && wci_respF_c_r != 2'd2 &&
wci_wci_cfwr_pw$whas ;
assign WILL_FIRE_RL_wci_cfwr =
CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctlAckReg__dreg_update
assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
// rule RL_wci_respF_both
assign CAN_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd2 || wci_respF_x_wire$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ;
// rule RL_wci_respF_decCtr
assign CAN_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ;
// rule RL_wci_respF_incCtr
assign CAN_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd1 || wci_respF_x_wire$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ;
// rule RL_wci_reqF__updateLevelCounter
assign CAN_FIRE_RL_wci_reqF__updateLevelCounter =
(wci_wciReq$wget[59:57] != 3'd0) != wci_reqF_r_deq$whas ;
assign WILL_FIRE_RL_wci_reqF__updateLevelCounter =
CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// rule RL_wsi_M1_reqFifo_both
assign CAN_FIRE_RL_wsi_M1_reqFifo_both =
((wsi_M1_reqFifo_c_r == 2'd1) ?
wsi_M1_reqFifo_enqueueing$whas :
wsi_M1_reqFifo_c_r != 2'd2 ||
wsi_M1_reqFifo_enqueueing$whas) &&
CAN_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsi_M1_reqFifo_both = CAN_FIRE_RL_wsi_M1_reqFifo_both ;
// rule RL_wsi_M1_reqFifo_decCtr
assign CAN_FIRE_RL_wsi_M1_reqFifo_decCtr =
CAN_FIRE_RL_wsi_M1_reqFifo_deq &&
!wsi_M1_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsi_M1_reqFifo_decCtr =
CAN_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// rule RL_wsi_M1_reqFifo_incCtr
assign CAN_FIRE_RL_wsi_M1_reqFifo_incCtr =
((wsi_M1_reqFifo_c_r == 2'd0) ?
wsi_M1_reqFifo_enqueueing$whas :
wsi_M1_reqFifo_c_r != 2'd1 ||
wsi_M1_reqFifo_enqueueing$whas) &&
wsi_M1_reqFifo_enqueueing$whas &&
!CAN_FIRE_RL_wsi_M1_reqFifo_deq ;
assign WILL_FIRE_RL_wsi_M1_reqFifo_incCtr =
CAN_FIRE_RL_wsi_M1_reqFifo_incCtr ;
// rule RL_wsi_M0_reqFifo_both
assign CAN_FIRE_RL_wsi_M0_reqFifo_both =
((wsi_M0_reqFifo_c_r == 2'd1) ?
wsi_M0_reqFifo_enqueueing$whas :
wsi_M0_reqFifo_c_r != 2'd2 ||
wsi_M0_reqFifo_enqueueing$whas) &&
CAN_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsi_M0_reqFifo_both = CAN_FIRE_RL_wsi_M0_reqFifo_both ;
// rule RL_wsi_M0_reqFifo_decCtr
assign CAN_FIRE_RL_wsi_M0_reqFifo_decCtr =
CAN_FIRE_RL_wsi_M0_reqFifo_deq &&
!wsi_M0_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsi_M0_reqFifo_decCtr =
CAN_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// rule RL_wsi_M0_reqFifo_incCtr
assign CAN_FIRE_RL_wsi_M0_reqFifo_incCtr =
((wsi_M0_reqFifo_c_r == 2'd0) ?
wsi_M0_reqFifo_enqueueing$whas :
wsi_M0_reqFifo_c_r != 2'd1 ||
wsi_M0_reqFifo_enqueueing$whas) &&
wsi_M0_reqFifo_enqueueing$whas &&
!CAN_FIRE_RL_wsi_M0_reqFifo_deq ;
assign WILL_FIRE_RL_wsi_M0_reqFifo_incCtr =
CAN_FIRE_RL_wsi_M0_reqFifo_incCtr ;
// rule RL_wsi_S0_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsi_S0_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsi_S0_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsi_S0_operateD__dreg_update
assign CAN_FIRE_RL_wsi_S0_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsi_S0_operateD__dreg_update = 1'd1 ;
// rule RL_wsi_S0_reqFifo__updateLevelCounter
assign CAN_FIRE_RL_wsi_S0_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsi_S0_reqFifo_enq !=
WILL_FIRE_RL_doMessageConsume_S0 ;
assign WILL_FIRE_RL_wsi_S0_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsi_S0_reqFifo__updateLevelCounter ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_illegalEdge$write_1__VAL_2 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] &&
!splitCtrl[7] ;
assign MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] &&
!splitCtrl[15] ;
assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 = wsi_M0_reqFifo_c_r - 2'd1 ;
assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 = wsi_M0_reqFifo_c_r + 2'd1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 =
MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 ?
wsi_S0_reqFifo$D_OUT :
wsi_S1_reqFifo$D_OUT ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 =
(wsi_M0_reqFifo_c_r == 2'd1) ?
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 :
wsi_M0_reqFifo_q_1 ;
assign MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 =
(wsi_M0_reqFifo_c_r == 2'd2) ?
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 :
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 = wsi_M1_reqFifo_c_r - 2'd1 ;
assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 = wsi_M1_reqFifo_c_r + 2'd1 ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 =
MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 ?
wsi_S0_reqFifo$D_OUT :
wsi_S1_reqFifo$D_OUT ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 =
(wsi_M1_reqFifo_c_r == 2'd1) ?
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 :
wsi_M1_reqFifo_q_1 ;
assign MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 =
(wsi_M1_reqFifo_c_r == 2'd2) ?
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 :
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd0 ;
assign MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd1 ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd0 ;
assign MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h13733 } ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_0$write_1__VAL_1 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
wci_respF_q_1 ;
assign MUX_wci_respF_q_1$write_1__VAL_1 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
// inlined wires
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_respF_x_wire$whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_S0_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsi_S0_wsiReq$whas = 1'd1 ;
assign wsi_S0_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo_r_enq$whas = CAN_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo_r_clr$whas = 1'b0 ;
assign wsi_S0_operateD_1$wget = 1'd1 ;
assign wsi_S0_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsi_S0_peerIsReady_1$wget = 1'd1 ;
assign wsi_S0_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsi_S0_extStatusW$wget =
{ wsi_S0_pMesgCount, wsi_S0_iMesgCount, wsi_S0_tBusyCount } ;
assign wsi_S1_wsiReq$wget =
{ wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo } ;
assign wsi_S1_wsiReq$whas = 1'd1 ;
assign wsi_S1_reqFifo_r_enq$whas = CAN_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo_r_deq$whas = CAN_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo_r_clr$whas = 1'b0 ;
assign wsi_S1_operateD_1$wget = 1'd1 ;
assign wsi_S1_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsi_S1_peerIsReady_1$wget = 1'd1 ;
assign wsi_M0_reqFifo_dequeueing$whas = CAN_FIRE_RL_wsi_M0_reqFifo_deq ;
assign wsi_S1_peerIsReady_1$whas = wsiS1_MReset_n ;
assign wsi_S1_extStatusW$wget =
{ wsi_S1_pMesgCount, wsi_S1_iMesgCount, wsi_S1_tBusyCount } ;
assign wsi_M0_reqFifo_enqueueing$whas =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] &&
!splitCtrl[7] ||
WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[0] &&
!splitCtrl[7] ;
assign wsi_M0_reqFifo_x_wire$wget = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 ;
assign wsi_M0_reqFifo_x_wire$whas = wsi_M0_reqFifo_enqueueing$whas ;
assign wsi_M0_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsi_M0_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsi_M0_operateD_1$wget = 1'd1 ;
assign wsi_M0_peerIsReady_1$wget = 1'd1 ;
assign wsi_M0_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wsi_M0_extStatusW$wget =
{ wsi_M0_pMesgCount, wsi_M0_iMesgCount, wsi_M0_tBusyCount } ;
assign wsi_M1_reqFifo_enqueueing$whas =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] &&
!splitCtrl[15] ||
WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[8] &&
!splitCtrl[15] ;
assign wsi_M1_reqFifo_x_wire$wget = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 ;
assign wsi_M1_reqFifo_x_wire$whas = wsi_M1_reqFifo_enqueueing$whas ;
assign wsi_M1_reqFifo_dequeueing$whas = CAN_FIRE_RL_wsi_M1_reqFifo_deq ;
assign wsi_M1_sThreadBusy_pw$whas = wsiM1_SThreadBusy ;
assign wsi_M1_operateD_1$wget = 1'd1 ;
assign wsi_M1_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsi_M1_peerIsReady_1$wget = 1'd1 ;
assign wsi_M1_peerIsReady_1$whas = wsiM1_SReset_n ;
assign wsi_M1_extStatusW$wget =
{ wsi_M1_pMesgCount, wsi_M1_iMesgCount, wsi_M1_tBusyCount } ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ;
assign wsi_Es0_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es0_mCmd_w$whas = 1'd1 ;
assign wsi_Es0_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es0_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es0_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es0_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es0_mData_w$wget = wsiS0_MData ;
assign wsi_Es0_mData_w$whas = 1'd1 ;
assign wsi_Es0_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es0_mByteEn_w$whas = 1'd1 ;
assign wsi_Es0_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es0_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es0_mDataInfo_w$whas = 1'd1 ;
assign wsi_Es1_mCmd_w$wget = wsiS1_MCmd ;
assign wsi_Es1_mCmd_w$whas = 1'd1 ;
assign wsi_Es1_mReqLast_w$whas = wsiS1_MReqLast ;
assign wsi_Es1_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ;
assign wsi_Es1_mBurstLength_w$wget = wsiS1_MBurstLength ;
assign wsi_Es1_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es1_mData_w$wget = wsiS1_MData ;
assign wsi_Es1_mData_w$whas = 1'd1 ;
assign wsi_Es1_mByteEn_w$wget = wsiS1_MByteEn ;
assign wsi_Es1_mByteEn_w$whas = 1'd1 ;
assign wsi_Es1_mReqInfo_w$wget = wsiS1_MReqInfo ;
assign wsi_Es1_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es1_mDataInfo_w$whas = 1'd1 ;
// register splitCtrl
assign splitCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign splitCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h04 ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
!MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_2 ;
assign wci_illegalEdge$EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge$write_1__SEL_2 ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[59:57] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_decCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ;
// register wci_respF_q_0
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_1 or
MUX_wci_respF_q_0$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
MUX_wci_respF_q_0$write_1__SEL_2:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
// register wci_respF_q_1
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_1 or
MUX_wci_respF_q_1$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1;
MUX_wci_respF_q_1$write_1__SEL_2:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M0_burstKind
assign wsi_M0_burstKind$D_IN =
(wsi_M0_burstKind == 2'd0) ?
(wsi_M0_reqFifo_q_0[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_M0_burstKind$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[312:310] == 3'd1 &&
(wsi_M0_burstKind == 2'd0 ||
(wsi_M0_burstKind == 2'd1 || wsi_M0_burstKind == 2'd2) &&
wsi_M0_reqFifo_q_0[309]) ;
// register wsi_M0_errorSticky
assign wsi_M0_errorSticky$D_IN = 1'b0 ;
assign wsi_M0_errorSticky$EN = 1'b0 ;
// register wsi_M0_iMesgCount
assign wsi_M0_iMesgCount$D_IN = wsi_M0_iMesgCount + 32'd1 ;
assign wsi_M0_iMesgCount$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[312:310] == 3'd1 &&
wsi_M0_burstKind == 2'd2 &&
wsi_M0_reqFifo_q_0[309] ;
// register wsi_M0_operateD
assign wsi_M0_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsi_M0_operateD$EN = 1'd1 ;
// register wsi_M0_pMesgCount
assign wsi_M0_pMesgCount$D_IN = wsi_M0_pMesgCount + 32'd1 ;
assign wsi_M0_pMesgCount$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[312:310] == 3'd1 &&
wsi_M0_burstKind == 2'd1 &&
wsi_M0_reqFifo_q_0[309] ;
// register wsi_M0_peerIsReady
assign wsi_M0_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsi_M0_peerIsReady$EN = 1'd1 ;
// register wsi_M0_reqFifo_c_r
assign wsi_M0_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ?
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 :
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 ;
assign wsi_M0_reqFifo_c_r$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ;
// register wsi_M0_reqFifo_q_0
always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 or
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr or wsi_M0_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M0_reqFifo_both:
wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1;
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2:
wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr:
wsi_M0_reqFifo_q_0$D_IN = wsi_M0_reqFifo_q_1;
default: wsi_M0_reqFifo_q_0$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M0_reqFifo_q_0$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_both ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_reqFifo_q_1
always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or
MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 or
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M0_reqFifo_both:
wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1;
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2:
wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr:
wsi_M0_reqFifo_q_1$D_IN =
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsi_M0_reqFifo_q_1$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M0_reqFifo_q_1$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_both ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_sThreadBusy_d
assign wsi_M0_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsi_M0_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M0_statusR
assign wsi_M0_statusR$D_IN =
{ wsi_M0_isReset$VAL,
!wsi_M0_peerIsReady,
!wsi_M0_operateD,
wsi_M0_errorSticky,
wsi_M0_burstKind != 2'd0,
wsi_M0_sThreadBusy_d,
1'd0,
wsi_M0_trafficSticky } ;
assign wsi_M0_statusR$EN = 1'd1 ;
// register wsi_M0_tBusyCount
assign wsi_M0_tBusyCount$D_IN = wsi_M0_tBusyCount + 32'd1 ;
assign wsi_M0_tBusyCount$EN = CAN_FIRE_RL_wsi_M0_inc_tBusyCount ;
// register wsi_M0_trafficSticky
assign wsi_M0_trafficSticky$D_IN = 1'd1 ;
assign wsi_M0_trafficSticky$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[312:310] == 3'd1 ;
// register wsi_M1_burstKind
assign wsi_M1_burstKind$D_IN =
(wsi_M1_burstKind == 2'd0) ?
(wsi_M1_reqFifo_q_0[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_M1_burstKind$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[312:310] == 3'd1 &&
(wsi_M1_burstKind == 2'd0 ||
(wsi_M1_burstKind == 2'd1 || wsi_M1_burstKind == 2'd2) &&
wsi_M1_reqFifo_q_0[309]) ;
// register wsi_M1_errorSticky
assign wsi_M1_errorSticky$D_IN = 1'b0 ;
assign wsi_M1_errorSticky$EN = 1'b0 ;
// register wsi_M1_iMesgCount
assign wsi_M1_iMesgCount$D_IN = wsi_M1_iMesgCount + 32'd1 ;
assign wsi_M1_iMesgCount$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[312:310] == 3'd1 &&
wsi_M1_burstKind == 2'd2 &&
wsi_M1_reqFifo_q_0[309] ;
// register wsi_M1_operateD
assign wsi_M1_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsi_M1_operateD$EN = 1'd1 ;
// register wsi_M1_pMesgCount
assign wsi_M1_pMesgCount$D_IN = wsi_M1_pMesgCount + 32'd1 ;
assign wsi_M1_pMesgCount$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[312:310] == 3'd1 &&
wsi_M1_burstKind == 2'd1 &&
wsi_M1_reqFifo_q_0[309] ;
// register wsi_M1_peerIsReady
assign wsi_M1_peerIsReady$D_IN = wsiM1_SReset_n ;
assign wsi_M1_peerIsReady$EN = 1'd1 ;
// register wsi_M1_reqFifo_c_r
assign wsi_M1_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ?
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 :
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 ;
assign wsi_M1_reqFifo_c_r$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ;
// register wsi_M1_reqFifo_q_0
always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 or
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr or wsi_M1_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M1_reqFifo_both:
wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1;
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2:
wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr:
wsi_M1_reqFifo_q_0$D_IN = wsi_M1_reqFifo_q_1;
default: wsi_M1_reqFifo_q_0$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M1_reqFifo_q_0$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_both ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_reqFifo_q_1
always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or
MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 or
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M1_reqFifo_both:
wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1;
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2:
wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr:
wsi_M1_reqFifo_q_1$D_IN =
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsi_M1_reqFifo_q_1$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M1_reqFifo_q_1$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_both ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_sThreadBusy_d
assign wsi_M1_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ;
assign wsi_M1_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M1_statusR
assign wsi_M1_statusR$D_IN =
{ wsi_M1_isReset$VAL,
!wsi_M1_peerIsReady,
!wsi_M1_operateD,
wsi_M1_errorSticky,
wsi_M1_burstKind != 2'd0,
wsi_M1_sThreadBusy_d,
1'd0,
wsi_M1_trafficSticky } ;
assign wsi_M1_statusR$EN = 1'd1 ;
// register wsi_M1_tBusyCount
assign wsi_M1_tBusyCount$D_IN = wsi_M1_tBusyCount + 32'd1 ;
assign wsi_M1_tBusyCount$EN = CAN_FIRE_RL_wsi_M1_inc_tBusyCount ;
// register wsi_M1_trafficSticky
assign wsi_M1_trafficSticky$D_IN = 1'd1 ;
assign wsi_M1_trafficSticky$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[312:310] == 3'd1 ;
// register wsi_S0_burstKind
assign wsi_S0_burstKind$D_IN =
(wsi_S0_burstKind == 2'd0) ?
(wsi_S0_wsiReq$wget[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_S0_burstKind$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq &&
(wsi_S0_burstKind == 2'd0 ||
(wsi_S0_burstKind == 2'd1 || wsi_S0_burstKind == 2'd2) &&
wsi_S0_wsiReq$wget[309]) ;
// register wsi_S0_errorSticky
assign wsi_S0_errorSticky$D_IN = 1'd1 ;
assign wsi_S0_errorSticky$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && !wsi_S0_reqFifo$FULL_N ;
// register wsi_S0_iMesgCount
assign wsi_S0_iMesgCount$D_IN = wsi_S0_iMesgCount + 32'd1 ;
assign wsi_S0_iMesgCount$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd2 &&
wsi_S0_wsiReq$wget[309] ;
// register wsi_S0_operateD
assign wsi_S0_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsi_S0_operateD$EN = 1'd1 ;
// register wsi_S0_pMesgCount
assign wsi_S0_pMesgCount$D_IN = wsi_S0_pMesgCount + 32'd1 ;
assign wsi_S0_pMesgCount$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd1 &&
wsi_S0_wsiReq$wget[309] ;
// register wsi_S0_peerIsReady
assign wsi_S0_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsi_S0_peerIsReady$EN = 1'd1 ;
// register wsi_S0_reqFifo_countReg
assign wsi_S0_reqFifo_countReg$D_IN =
CAN_FIRE_RL_wsi_S0_reqFifo_enq ?
wsi_S0_reqFifo_countReg + 2'd1 :
wsi_S0_reqFifo_countReg - 2'd1 ;
assign wsi_S0_reqFifo_countReg$EN =
CAN_FIRE_RL_wsi_S0_reqFifo__updateLevelCounter ;
// register wsi_S0_statusR
assign wsi_S0_statusR$D_IN =
{ wsi_S0_isReset$VAL,
!wsi_S0_peerIsReady,
!wsi_S0_operateD,
wsi_S0_errorSticky,
wsi_S0_burstKind != 2'd0,
NOT_wsi_S0_reqFifo_countReg_95_ULE_1_96___d397 ||
wsi_S0_isReset$VAL ||
!wsi_S0_operateD ||
!wsi_S0_peerIsReady,
1'd0,
wsi_S0_trafficSticky } ;
assign wsi_S0_statusR$EN = 1'd1 ;
// register wsi_S0_tBusyCount
assign wsi_S0_tBusyCount$D_IN = wsi_S0_tBusyCount + 32'd1 ;
assign wsi_S0_tBusyCount$EN = CAN_FIRE_RL_wsi_S0_inc_tBusyCount ;
// register wsi_S0_trafficSticky
assign wsi_S0_trafficSticky$D_IN = 1'd1 ;
assign wsi_S0_trafficSticky$EN = CAN_FIRE_RL_wsi_S0_reqFifo_enq ;
// register wsi_S1_burstKind
assign wsi_S1_burstKind$D_IN =
(wsi_S1_burstKind == 2'd0) ?
(wsi_S1_wsiReq$wget[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_S1_burstKind$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq &&
(wsi_S1_burstKind == 2'd0 ||
(wsi_S1_burstKind == 2'd1 || wsi_S1_burstKind == 2'd2) &&
wsi_S1_wsiReq$wget[309]) ;
// register wsi_S1_errorSticky
assign wsi_S1_errorSticky$D_IN = 1'd1 ;
assign wsi_S1_errorSticky$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && !wsi_S1_reqFifo$FULL_N ;
// register wsi_S1_iMesgCount
assign wsi_S1_iMesgCount$D_IN = wsi_S1_iMesgCount + 32'd1 ;
assign wsi_S1_iMesgCount$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd2 &&
wsi_S1_wsiReq$wget[309] ;
// register wsi_S1_operateD
assign wsi_S1_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsi_S1_operateD$EN = 1'd1 ;
// register wsi_S1_pMesgCount
assign wsi_S1_pMesgCount$D_IN = wsi_S1_pMesgCount + 32'd1 ;
assign wsi_S1_pMesgCount$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd1 &&
wsi_S1_wsiReq$wget[309] ;
// register wsi_S1_peerIsReady
assign wsi_S1_peerIsReady$D_IN = wsiS1_MReset_n ;
assign wsi_S1_peerIsReady$EN = 1'd1 ;
// register wsi_S1_reqFifo_countReg
assign wsi_S1_reqFifo_countReg$D_IN =
CAN_FIRE_RL_wsi_S1_reqFifo_enq ?
wsi_S1_reqFifo_countReg + 2'd1 :
wsi_S1_reqFifo_countReg - 2'd1 ;
assign wsi_S1_reqFifo_countReg$EN =
CAN_FIRE_RL_wsi_S1_reqFifo__updateLevelCounter ;
// register wsi_S1_statusR
assign wsi_S1_statusR$D_IN =
{ wsi_S1_isReset$VAL,
!wsi_S1_peerIsReady,
!wsi_S1_operateD,
wsi_S1_errorSticky,
wsi_S1_burstKind != 2'd0,
NOT_wsi_S1_reqFifo_countReg_31_ULE_1_32___d333 ||
wsi_S1_isReset$VAL ||
!wsi_S1_operateD ||
!wsi_S1_peerIsReady,
1'd0,
wsi_S1_trafficSticky } ;
assign wsi_S1_statusR$EN = 1'd1 ;
// register wsi_S1_tBusyCount
assign wsi_S1_tBusyCount$D_IN = wsi_S1_tBusyCount + 32'd1 ;
assign wsi_S1_tBusyCount$EN = CAN_FIRE_RL_wsi_S1_inc_tBusyCount ;
// register wsi_S1_trafficSticky
assign wsi_S1_trafficSticky$D_IN = 1'd1 ;
assign wsi_S1_trafficSticky$EN = CAN_FIRE_RL_wsi_S1_reqFifo_enq ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$ENQ = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wsi_S0_reqFifo
assign wsi_S0_reqFifo$D_IN = wsi_S0_wsiReq$wget ;
assign wsi_S0_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo$ENQ = CAN_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo$CLR = 1'b0 ;
// submodule wsi_S1_reqFifo
assign wsi_S1_reqFifo$D_IN = wsi_S1_wsiReq$wget ;
assign wsi_S1_reqFifo$DEQ = CAN_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo$ENQ = CAN_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo$CLR = 1'b0 ;
// remaining internal signals
assign NOT_wsi_S0_reqFifo_countReg_95_ULE_1_96___d397 =
wsi_S0_reqFifo_countReg > 2'd1 ;
assign NOT_wsi_S1_reqFifo_countReg_31_ULE_1_32___d333 =
wsi_S1_reqFifo_countReg > 2'd1 ;
assign rdat__h13812 =
hasDebugLogic ?
{ wsi_S0_statusR,
wsi_S1_statusR,
wsi_M0_statusR,
wsi_M1_statusR } :
32'd0 ;
assign rdat__h14001 =
hasDebugLogic ? wsi_S0_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h14015 =
hasDebugLogic ? wsi_S0_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h14023 =
hasDebugLogic ? wsi_S1_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h14037 =
hasDebugLogic ? wsi_S1_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h14045 =
hasDebugLogic ? wsi_M0_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h14059 =
hasDebugLogic ? wsi_M0_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h14067 =
hasDebugLogic ? wsi_M1_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h14081 =
hasDebugLogic ? wsi_M1_extStatusW$wget[63:32] : 32'd0 ;
always@(wci_reqF$D_OUT or
splitCtrl or
rdat__h13812 or
rdat__h14001 or
rdat__h14015 or
rdat__h14023 or
rdat__h14037 or
rdat__h14045 or rdat__h14059 or rdat__h14067 or rdat__h14081)
begin
case (wci_reqF$D_OUT[39:32])
8'h04: _theResult____h13733 = splitCtrl;
8'h1C: _theResult____h13733 = rdat__h13812;
8'h20: _theResult____h13733 = rdat__h14001;
8'h24: _theResult____h13733 = rdat__h14015;
8'h28: _theResult____h13733 = rdat__h14023;
8'h2C: _theResult____h13733 = rdat__h14037;
8'h30: _theResult____h13733 = rdat__h14045;
8'h34: _theResult____h13733 = rdat__h14059;
8'h38: _theResult____h13733 = rdat__h14067;
8'h3C: _theResult____h13733 = rdat__h14081;
default: _theResult____h13733 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (!wciS0_MReset_n)
begin
splitCtrl <= `BSV_ASSIGNMENT_DELAY ctrlInit;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'd7;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (splitCtrl$EN) splitCtrl <= `BSV_ASSIGNMENT_DELAY splitCtrl$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wsi_M0_burstKind$EN)
wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M0_burstKind$D_IN;
if (wsi_M0_errorSticky$EN)
wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M0_errorSticky$D_IN;
if (wsi_M0_iMesgCount$EN)
wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_iMesgCount$D_IN;
if (wsi_M0_operateD$EN)
wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M0_operateD$D_IN;
if (wsi_M0_pMesgCount$EN)
wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_pMesgCount$D_IN;
if (wsi_M0_peerIsReady$EN)
wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M0_peerIsReady$D_IN;
if (wsi_M0_reqFifo_c_r$EN)
wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_c_r$D_IN;
if (wsi_M0_reqFifo_q_0$EN)
wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_0$D_IN;
if (wsi_M0_reqFifo_q_1$EN)
wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_1$D_IN;
if (wsi_M0_sThreadBusy_d$EN)
wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wsi_M0_sThreadBusy_d$D_IN;
if (wsi_M0_tBusyCount$EN)
wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_tBusyCount$D_IN;
if (wsi_M0_trafficSticky$EN)
wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_M0_trafficSticky$D_IN;
if (wsi_M1_burstKind$EN)
wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M1_burstKind$D_IN;
if (wsi_M1_errorSticky$EN)
wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M1_errorSticky$D_IN;
if (wsi_M1_iMesgCount$EN)
wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_iMesgCount$D_IN;
if (wsi_M1_operateD$EN)
wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M1_operateD$D_IN;
if (wsi_M1_pMesgCount$EN)
wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_pMesgCount$D_IN;
if (wsi_M1_peerIsReady$EN)
wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M1_peerIsReady$D_IN;
if (wsi_M1_reqFifo_c_r$EN)
wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_c_r$D_IN;
if (wsi_M1_reqFifo_q_0$EN)
wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_0$D_IN;
if (wsi_M1_reqFifo_q_1$EN)
wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_1$D_IN;
if (wsi_M1_sThreadBusy_d$EN)
wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wsi_M1_sThreadBusy_d$D_IN;
if (wsi_M1_tBusyCount$EN)
wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_tBusyCount$D_IN;
if (wsi_M1_trafficSticky$EN)
wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_M1_trafficSticky$D_IN;
if (wsi_S0_burstKind$EN)
wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S0_burstKind$D_IN;
if (wsi_S0_errorSticky$EN)
wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S0_errorSticky$D_IN;
if (wsi_S0_iMesgCount$EN)
wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_iMesgCount$D_IN;
if (wsi_S0_operateD$EN)
wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S0_operateD$D_IN;
if (wsi_S0_pMesgCount$EN)
wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_pMesgCount$D_IN;
if (wsi_S0_peerIsReady$EN)
wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S0_peerIsReady$D_IN;
if (wsi_S0_reqFifo_countReg$EN)
wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsi_S0_reqFifo_countReg$D_IN;
if (wsi_S0_tBusyCount$EN)
wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_tBusyCount$D_IN;
if (wsi_S0_trafficSticky$EN)
wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_S0_trafficSticky$D_IN;
if (wsi_S1_burstKind$EN)
wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S1_burstKind$D_IN;
if (wsi_S1_errorSticky$EN)
wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S1_errorSticky$D_IN;
if (wsi_S1_iMesgCount$EN)
wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_iMesgCount$D_IN;
if (wsi_S1_operateD$EN)
wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S1_operateD$D_IN;
if (wsi_S1_pMesgCount$EN)
wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_pMesgCount$D_IN;
if (wsi_S1_peerIsReady$EN)
wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S1_peerIsReady$D_IN;
if (wsi_S1_reqFifo_countReg$EN)
wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsi_S1_reqFifo_countReg$D_IN;
if (wsi_S1_tBusyCount$EN)
wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_tBusyCount$D_IN;
if (wsi_S1_trafficSticky$EN)
wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_S1_trafficSticky$D_IN;
end
if (wsi_M0_statusR$EN)
wsi_M0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M0_statusR$D_IN;
if (wsi_M1_statusR$EN)
wsi_M1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M1_statusR$D_IN;
if (wsi_S0_statusR$EN)
wsi_S0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S0_statusR$D_IN;
if (wsi_S1_statusR$EN)
wsi_S1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S1_statusR$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
splitCtrl = 32'hAAAAAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wsi_M0_burstKind = 2'h2;
wsi_M0_errorSticky = 1'h0;
wsi_M0_iMesgCount = 32'hAAAAAAAA;
wsi_M0_operateD = 1'h0;
wsi_M0_pMesgCount = 32'hAAAAAAAA;
wsi_M0_peerIsReady = 1'h0;
wsi_M0_reqFifo_c_r = 2'h2;
wsi_M0_reqFifo_q_0 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M0_reqFifo_q_1 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M0_sThreadBusy_d = 1'h0;
wsi_M0_statusR = 8'hAA;
wsi_M0_tBusyCount = 32'hAAAAAAAA;
wsi_M0_trafficSticky = 1'h0;
wsi_M1_burstKind = 2'h2;
wsi_M1_errorSticky = 1'h0;
wsi_M1_iMesgCount = 32'hAAAAAAAA;
wsi_M1_operateD = 1'h0;
wsi_M1_pMesgCount = 32'hAAAAAAAA;
wsi_M1_peerIsReady = 1'h0;
wsi_M1_reqFifo_c_r = 2'h2;
wsi_M1_reqFifo_q_0 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M1_reqFifo_q_1 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M1_sThreadBusy_d = 1'h0;
wsi_M1_statusR = 8'hAA;
wsi_M1_tBusyCount = 32'hAAAAAAAA;
wsi_M1_trafficSticky = 1'h0;
wsi_S0_burstKind = 2'h2;
wsi_S0_errorSticky = 1'h0;
wsi_S0_iMesgCount = 32'hAAAAAAAA;
wsi_S0_operateD = 1'h0;
wsi_S0_pMesgCount = 32'hAAAAAAAA;
wsi_S0_peerIsReady = 1'h0;
wsi_S0_reqFifo_countReg = 2'h2;
wsi_S0_statusR = 8'hAA;
wsi_S0_tBusyCount = 32'hAAAAAAAA;
wsi_S0_trafficSticky = 1'h0;
wsi_S1_burstKind = 2'h2;
wsi_S1_errorSticky = 1'h0;
wsi_S1_iMesgCount = 32'hAAAAAAAA;
wsi_S1_operateD = 1'h0;
wsi_S1_pMesgCount = 32'hAAAAAAAA;
wsi_S1_peerIsReady = 1'h0;
wsi_S1_reqFifo_countReg = 2'h2;
wsi_S1_statusR = 8'hAA;
wsi_S1_tBusyCount = 32'hAAAAAAAA;
wsi_S1_trafficSticky = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3679 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3679,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 83, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 84, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_IsO fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 84, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h13749 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h13749,
wci_reqF$D_OUT[51:32],
wci_reqF$D_OUT[55:52],
_theResult____h13733);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 60, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 60, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 60, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h2780 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h2780,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h2633 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h2633,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h14297 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h14297,
wci_reqF$D_OUT[51:32],
wci_reqF$D_OUT[55:52],
wci_reqF$D_OUT[31:0]);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 50, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 50, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 50, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/WsiSplitter2x2.bsv\", line 50, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_cfrd fired in the same clock\n cycle.\n");
end
// synopsys translate_on
endmodule // mkWsiSplitter2x232B
|
(* -*- coding: utf-8; coq-prog-args: ("-coqlib" "../.." "-R" ".." "Coq" "-top" "Coq.Classes.Morphisms") -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based morphism definition and standard, minimal instances
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Require Export Coq.Classes.RelationClasses.
Generalizable Variables A eqA B C D R RA RB RC m f x y.
Local Obligation Tactic := simpl_relation.
(** * Morphisms.
We now turn to the definition of [Proper] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism for a relation [R] is a proper element of the relation.
The relation [R] will be instantiated by [respectful] and [A] by an arrow
type for usual morphisms. *)
Section Proper.
Let U := Type.
Context {A B : U}.
Class Proper (R : relation A) (m : A) : Prop :=
proper_prf : R m m.
(** Every element in the carrier of a reflexive relation is a morphism
for this relation. We use a proxy class for this case which is used
internally to discharge reflexivity constraints. The [Reflexive]
instance will almost always be used, but it won't apply in general to
any kind of [Proper (A -> B) _ _] goal, making proof-search much
slower. A cleaner solution would be to be able to set different
priorities in different hint bases and select a particular hint
database for resolution of a type class constraint. *)
Class ProperProxy (R : relation A) (m : A) : Prop :=
proper_proxy : R m m.
Lemma eq_proper_proxy (x : A) : ProperProxy (@eq A) x.
Proof. firstorder. Qed.
Lemma reflexive_proper_proxy `(Reflexive A R) (x : A) : ProperProxy R x.
Proof. firstorder. Qed.
Lemma proper_proper_proxy x `(Proper R x) : ProperProxy R x.
Proof. firstorder. Qed.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : A -> B -> Prop)
(R' : forall (x : A) (y : B), C x -> D y -> Prop) :
(forall x : A, C x) -> (forall x : B, D x) -> Prop :=
fun f g => forall x y, R x y -> R' x y (f x) (g y).
(** The non-dependent version is an instance where we forget dependencies. *)
Definition respectful (R : relation A) (R' : relation B) : relation (A -> B) :=
Eval compute in @respectful_hetero A A (fun _ => B) (fun _ => B) R (fun _ _ => R').
End Proper.
(** We favor the use of Leibniz equality or a declared reflexive relation
when resolving [ProperProxy], otherwise, if the relation is given (not an evar),
we fall back to [Proper]. *)
Hint Extern 1 (ProperProxy _ _) =>
class_apply @eq_proper_proxy || class_apply @reflexive_proper_proxy : typeclass_instances.
Hint Extern 2 (ProperProxy ?R _) =>
not_evar R; class_apply @proper_proper_proxy : typeclass_instances.
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Declare Scope signature_scope.
Delimit Scope signature_scope with signature.
Module ProperNotations.
Notation " R ++> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R ==> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R --> R' " := (@respectful _ _ (flip (R%signature)) (R'%signature))
(right associativity, at level 55) : signature_scope.
End ProperNotations.
Arguments Proper {A}%type R%signature m.
Arguments respectful {A B}%type (R R')%signature _ _.
Export ProperNotations.
Local Open Scope signature_scope.
(** [solve_proper] try to solve the goal [Proper (?==> ... ==>?) f]
by repeated introductions and setoid rewrites. It should work
fine when [f] is a combination of already known morphisms and
quantifiers. *)
Ltac solve_respectful t :=
match goal with
| |- respectful _ _ _ _ =>
let H := fresh "H" in
intros ? ? H; solve_respectful ltac:(setoid_rewrite H; t)
| _ => t; reflexivity
end.
Ltac solve_proper := unfold Proper; solve_respectful ltac:(idtac).
(** [f_equiv] is a clone of [f_equal] that handles setoid equivalences.
For example, if we know that [f] is a morphism for [E1==>E2==>E],
then the goal [E (f x y) (f x' y')] will be transformed by [f_equiv]
into the subgoals [E1 x x'] and [E2 y y'].
*)
Ltac f_equiv :=
match goal with
| |- ?R (?f ?x) (?f' _) =>
let T := type of x in
let Rx := fresh "R" in
evar (Rx : relation T);
let H := fresh in
assert (H : (Rx==>R)%signature f f');
unfold Rx in *; clear Rx; [ f_equiv | apply H; clear H; try reflexivity ]
| |- ?R ?f ?f' =>
solve [change (Proper R f); eauto with typeclass_instances | reflexivity ]
| _ => idtac
end.
Section Relations.
Let U := Type.
Context {A B : U} (P : A -> U).
(** [forall_def] reifies the dependent product as a definition. *)
Definition forall_def : Type := forall x : A, P x.
(** Dependent pointwise lifting of a relation on the range. *)
Definition forall_relation
(sig : forall a, relation (P a)) : relation (forall x, P x) :=
fun f g => forall a, sig a (f a) (g a).
(** Non-dependent pointwise lifting *)
Definition pointwise_relation (R : relation B) : relation (A -> B) :=
fun f g => forall a, R (f a) (g a).
Lemma pointwise_pointwise (R : relation B) :
relation_equivalence (pointwise_relation R) (@eq A ==> R).
Proof. intros. split; reduce; subst; firstorder. Qed.
(** Subrelations induce a morphism on the identity. *)
Global Instance subrelation_id_proper `(subrelation A RA RA') : Proper (RA ==> RA') id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Lemma subrelation_respectful `(subl : subrelation A RA' RA, subr : subrelation B RB RB') :
subrelation (RA ==> RB) (RA' ==> RB').
Proof. unfold subrelation in *; firstorder. Qed.
(** And of course it is reflexive. *)
Lemma subrelation_refl R : @subrelation A R R.
Proof. unfold subrelation; firstorder. Qed.
(** [Proper] is itself a covariant morphism for [subrelation].
We use an unconvertible premise to avoid looping.
*)
Lemma subrelation_proper `(mor : Proper A R' m)
`(unc : Unconvertible (relation A) R R')
`(sub : subrelation A R' R) : Proper R m.
Proof.
intros. apply sub. apply mor.
Qed.
Global Instance proper_subrelation_proper :
Proper (subrelation ++> eq ==> impl) (@Proper A).
Proof. reduce. subst. firstorder. Qed.
Global Instance pointwise_subrelation `(sub : subrelation B R R') :
subrelation (pointwise_relation R) (pointwise_relation R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. apply H. Qed.
(** For dependent function types. *)
Lemma forall_subrelation (R S : forall x : A, relation (P x)) :
(forall a, subrelation (R a) (S a)) -> subrelation (forall_relation R) (forall_relation S).
Proof. reduce. apply H. apply H0. Qed.
End Relations.
Typeclasses Opaque respectful pointwise_relation forall_relation.
Arguments forall_relation {A P}%type sig%signature _ _.
Arguments pointwise_relation A%type {B}%type R%signature _ _.
Hint Unfold Reflexive : core.
Hint Unfold Symmetric : core.
Hint Unfold Transitive : core.
(** Resolution with subrelation: favor decomposing products over applying reflexivity
for unconstrained goals. *)
Ltac subrelation_tac T U :=
(is_ground T ; is_ground U ; class_apply @subrelation_refl) ||
class_apply @subrelation_respectful || class_apply @subrelation_refl.
Hint Extern 3 (@subrelation _ ?T ?U) => subrelation_tac T U : typeclass_instances.
CoInductive apply_subrelation : Prop := do_subrelation.
Ltac proper_subrelation :=
match goal with
[ H : apply_subrelation |- _ ] => clear H ; class_apply @subrelation_proper
end.
Hint Extern 5 (@Proper _ ?H _) => proper_subrelation : typeclass_instances.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
Instance iff_impl_subrelation : subrelation iff impl | 2.
Proof. firstorder. Qed.
Instance iff_flip_impl_subrelation : subrelation iff (flip impl) | 2.
Proof. firstorder. Qed.
(** We use an extern hint to help unification. *)
Hint Extern 4 (subrelation (@forall_relation ?A ?B ?R) (@forall_relation _ _ ?S)) =>
apply (@forall_subrelation A B R S) ; intro : typeclass_instances.
Section GenericInstances.
(* Share universes *)
Let U := Type.
Context {A B C : U}.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Program Instance respectful_per `(PER A R, PER B R') : PER (R ==> R').
Next Obligation.
Proof with auto.
assert(R x0 x0).
- transitivity y0... symmetry...
- transitivity (y x0)...
Qed.
(** The complement of a relation conserves its proper elements. *)
Program Definition complement_proper
`(mR : Proper (A -> A -> Prop) (RA ==> RA ==> iff) R) :
Proper (RA ==> RA ==> iff) (complement R) := _.
Next Obligation.
Proof.
unfold complement.
pose (mR x y H x0 y0 H0).
intuition.
Qed.
(** The [flip] too, actually the [flip] instance is a bit more general. *)
Program Definition flip_proper
`(mor : Proper (A -> B -> C) (RA ==> RB ==> RC) f) :
Proper (RB ==> RA ==> RC) (flip f) := _.
Next Obligation.
Proof.
apply mor ; auto.
Qed.
(** Every Transitive relation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Global Program
Instance trans_contra_co_morphism
`(Transitive A R) : Proper (R --> R ++> impl) R.
Next Obligation.
Proof with auto.
transitivity x...
transitivity x0...
Qed.
(** Proper declarations for partial applications. *)
Global Program
Instance trans_contra_inv_impl_morphism
`(Transitive A R) : Proper (R --> flip impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
Global Program
Instance trans_co_impl_morphism
`(Transitive A R) : Proper (R ++> impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0...
Qed.
Global Program
Instance trans_sym_co_inv_impl_morphism
`(PER A R) : Proper (R ++> flip impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y... symmetry...
Qed.
Global Program Instance trans_sym_contra_impl_morphism
`(PER A R) : Proper (R --> impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0... symmetry...
Qed.
Global Program Instance per_partial_app_morphism
`(PER A R) : Proper (R ==> iff) (R x) | 2.
Next Obligation.
Proof with auto.
split.
- intros ; transitivity x0...
- intros.
transitivity y...
symmetry...
Qed.
(** Every Transitive relation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof to get an [R y z] goal. *)
Global Program
Instance trans_co_eq_inv_impl_morphism
`(Transitive A R) : Proper (R ==> (@eq A) ==> flip impl) R | 2.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
(** Every Symmetric and Transitive relation gives rise to an equivariant morphism. *)
Global Program
Instance PER_morphism `(PER A R) : Proper (R ==> R ==> iff) R | 1.
Next Obligation.
Proof with auto.
split ; intros.
- transitivity x0... transitivity x... symmetry...
- transitivity y... transitivity y0... symmetry...
Qed.
Lemma symmetric_equiv_flip `(Symmetric A R) : relation_equivalence R (flip R).
Proof. firstorder. Qed.
Global Program Instance compose_proper RA RB RC :
Proper ((RB ==> RC) ==> (RA ==> RB) ==> (RA ==> RC)) (@compose A B C).
Next Obligation.
Proof.
simpl_relation.
unfold compose. apply H. apply H0. apply H1.
Qed.
(** Coq functions are morphisms for Leibniz equality,
applied only if really needed. *)
Global Instance reflexive_eq_dom_reflexive `(Reflexive B R') :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_relation. Qed.
(** [respectful] is a morphism for relation equivalence. *)
Global Instance respectful_morphism :
Proper (relation_equivalence ++> relation_equivalence ++> relation_equivalence)
(@respectful A B).
Proof.
reduce.
unfold respectful, relation_equivalence, predicate_equivalence in * ; simpl in *.
split ; intros.
- rewrite <- H0.
apply H1.
rewrite H.
assumption.
- rewrite H0.
apply H1.
rewrite <- H.
assumption.
Qed.
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism `(Proper (A -> B) (R ==> R') m, ProperProxy A R x) :
Proper R' (m x).
Proof. simpl_relation. Qed.
Lemma flip_respectful (R : relation A) (R' : relation B) :
relation_equivalence (flip (R ==> R')) (flip R ==> flip R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Treating flip: can't make them direct instances as we
need at least a [flip] present in the goal. *)
Lemma flip1 `(subrelation A R' R) : subrelation (flip (flip R')) R.
Proof. firstorder. Qed.
Lemma flip2 `(subrelation A R R') : subrelation R (flip (flip R')).
Proof. firstorder. Qed.
(** That's if and only if *)
Lemma eq_subrelation `(Reflexive A R) : subrelation (@eq A) R.
Proof. simpl_relation. Qed.
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Definition proper_flip_proper `(mor : Proper A R m) : Proper (flip R) m := mor.
(** Every reflexive relation gives rise to a morphism,
only for immediately solving goals without variables. *)
Lemma reflexive_proper `{Reflexive A R} (x : A) : Proper R x.
Proof. firstorder. Qed.
Lemma proper_eq (x : A) : Proper (@eq A) x.
Proof. intros. apply reflexive_proper. Qed.
End GenericInstances.
Class PartialApplication.
CoInductive normalization_done : Prop := did_normalization.
Class Params {A : Type} (of : A) (arity : nat).
Ltac partial_application_tactic :=
let rec do_partial_apps H m cont :=
match m with
| ?m' ?x => class_apply @Reflexive_partial_app_morphism ;
[(do_partial_apps H m' ltac:(idtac))|clear H]
| _ => cont
end
in
let rec do_partial H ar m :=
lazymatch ar with
| 0%nat => do_partial_apps H m ltac:(fail 1)
| S ?n' =>
match m with
?m' ?x => do_partial H n' m'
end
end
in
let params m sk fk :=
(let m' := fresh in head_of_constr m' m ;
let n := fresh in evar (n:nat) ;
let v := eval compute in n in clear n ;
let H := fresh in
assert(H:Params m' v) by (subst m'; once typeclasses eauto) ;
let v' := eval compute in v in subst m';
(sk H v' || fail 1))
|| fk
in
let on_morphism m cont :=
params m ltac:(fun H n => do_partial H n m)
ltac:(cont)
in
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : @Params _ _ _ |- _ ] => fail 1
| [ |- @Proper ?T _ (?m ?x) ] =>
match goal with
| [ H : PartialApplication |- _ ] =>
class_apply @Reflexive_partial_app_morphism; [|clear H]
| _ => on_morphism (m x)
ltac:(class_apply @Reflexive_partial_app_morphism)
end
end.
(** Bootstrap !!! *)
Instance proper_proper : Proper (relation_equivalence ==> eq ==> iff) (@Proper A).
Proof.
simpl_relation.
reduce in H.
split ; red ; intros.
- setoid_rewrite <- H.
apply H0.
- setoid_rewrite H.
apply H0.
Qed.
Ltac proper_reflexive :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| _ => class_apply proper_eq || class_apply @reflexive_proper
end.
Hint Extern 1 (subrelation (flip _) _) => class_apply @flip1 : typeclass_instances.
Hint Extern 1 (subrelation _ (flip _)) => class_apply @flip2 : typeclass_instances.
Hint Extern 1 (Proper _ (complement _)) => apply @complement_proper
: typeclass_instances.
Hint Extern 1 (Proper _ (flip _)) => apply @flip_proper
: typeclass_instances.
Hint Extern 2 (@Proper _ (flip _) _) => class_apply @proper_flip_proper
: typeclass_instances.
Hint Extern 4 (@Proper _ _ _) => partial_application_tactic
: typeclass_instances.
Hint Extern 7 (@Proper _ _ _) => proper_reflexive
: typeclass_instances.
(** Special-purpose class to do normalization of signatures w.r.t. flip. *)
Section Normalize.
Context (A : Type).
Class Normalizes (m : relation A) (m' : relation A) : Prop :=
normalizes : relation_equivalence m m'.
(** Current strategy: add [flip] everywhere and reduce using [subrelation]
afterwards. *)
Lemma proper_normalizes_proper `(Normalizes R0 R1, Proper A R1 m) : Proper R0 m.
Proof.
red in H, H0.
rewrite H.
assumption.
Qed.
Lemma flip_atom R : Normalizes R (flip (flip R)).
Proof.
firstorder.
Qed.
End Normalize.
Lemma flip_arrow {A : Type} {B : Type}
`(NA : Normalizes A R (flip R'''), NB : Normalizes B R' (flip R'')) :
Normalizes (A -> B) (R ==> R') (flip (R''' ==> R'')%signature).
Proof.
unfold Normalizes in *. intros.
unfold relation_equivalence in *.
unfold predicate_equivalence in *. simpl in *.
unfold respectful. unfold flip in *. firstorder.
- apply NB. apply H. apply NA. apply H0.
- apply NB. apply H. apply NA. apply H0.
Qed.
Ltac normalizes :=
match goal with
| [ |- Normalizes _ (respectful _ _) _ ] => class_apply @flip_arrow
| _ => class_apply @flip_atom
end.
Ltac proper_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : apply_subrelation |- @Proper _ ?R _ ] =>
let H := fresh "H" in
set(H:=did_normalization) ; class_apply @proper_normalizes_proper
end.
Hint Extern 1 (Normalizes _ _ _) => normalizes : typeclass_instances.
Hint Extern 6 (@Proper _ _ _) => proper_normalization
: typeclass_instances.
(** When the relation on the domain is symmetric, we can
flip the relation on the codomain. Same for binary functions. *)
Lemma proper_sym_flip :
forall `(Symmetric A R1)`(Proper (A->B) (R1==>R2) f),
Proper (R1==>flip R2) f.
Proof.
intros A R1 Sym B R2 f Hf.
intros x x' Hxx'. apply Hf, Sym, Hxx'.
Qed.
Lemma proper_sym_flip_2 :
forall `(Symmetric A R1)`(Symmetric B R2)`(Proper (A->B->C) (R1==>R2==>R3) f),
Proper (R1==>R2==>flip R3) f.
Proof.
intros A R1 Sym1 B R2 Sym2 C R3 f Hf.
intros x x' Hxx' y y' Hyy'. apply Hf; auto.
Qed.
(** When the relation on the domain is symmetric, a predicate is
compatible with [iff] as soon as it is compatible with [impl].
Same with a binary relation. *)
Lemma proper_sym_impl_iff : forall `(Symmetric A R)`(Proper _ (R==>impl) f),
Proper (R==>iff) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_impl_iff_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>impl) f),
Proper (R==>R'==>iff) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
(** A [PartialOrder] is compatible with its underlying equivalence. *)
Instance PartialOrder_proper `(PartialOrder A eqA R) :
Proper (eqA==>eqA==>iff) R.
Proof.
intros.
apply proper_sym_impl_iff_2; auto with *.
intros x x' Hx y y' Hy Hr.
transitivity x.
- generalize (partial_order_equivalence x x'); compute; intuition.
- transitivity y; auto.
generalize (partial_order_equivalence y y'); compute; intuition.
Qed.
(** From a [PartialOrder] to the corresponding [StrictOrder]:
[lt = le /\ ~eq].
If the order is total, we could also say [gt = ~le]. *)
Lemma PartialOrder_StrictOrder `(PartialOrder A eqA R) :
StrictOrder (relation_conjunction R (complement eqA)).
Proof.
split; compute.
- intros x (_,Hx). apply Hx, Equivalence_Reflexive.
- intros x y z (Hxy,Hxy') (Hyz,Hyz'). split.
+ apply PreOrder_Transitive with y; assumption.
+ intro Hxz.
apply Hxy'.
apply partial_order_antisym; auto.
rewrite Hxz; auto.
Qed.
(** From a [StrictOrder] to the corresponding [PartialOrder]:
[le = lt \/ eq].
If the order is total, we could also say [ge = ~lt]. *)
Lemma StrictOrder_PreOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iff) R) :
PreOrder (relation_disjunction R eqA).
Proof.
split.
- intros x. right. reflexivity.
- intros x y z [Hxy|Hxy] [Hyz|Hyz].
+ left. transitivity y; auto.
+ left. rewrite <- Hyz; auto.
+ left. rewrite Hxy; auto.
+ right. transitivity y; auto.
Qed.
Hint Extern 4 (PreOrder (relation_disjunction _ _)) =>
class_apply StrictOrder_PreOrder : typeclass_instances.
Lemma StrictOrder_PartialOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iff) R) :
PartialOrder eqA (relation_disjunction R eqA).
Proof.
intros. intros x y. compute. intuition.
elim (StrictOrder_Irreflexive x).
transitivity y; auto.
Qed.
Hint Extern 4 (StrictOrder (relation_conjunction _ _)) =>
class_apply PartialOrder_StrictOrder : typeclass_instances.
Hint Extern 4 (PartialOrder _ (relation_disjunction _ _)) =>
class_apply StrictOrder_PartialOrder : typeclass_instances.
|
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
//----------------------------------------------------------------------------------------
//
// The MIT License (MIT)
// Copyright (c) 2016 Enrique Sedano ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify,
// merge, publish, distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be included in all copies
// or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
// CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
// OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//----------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------
//
// This module is a member of
// ____ __
// _ __/ __ \__ ______/ /_ __
// | | / / /_/ / / / / __ / / / /
// | |/ / _, _/ /_/ / /_/ / /_/ /
// |___/_/ |_|\__,_/\__,_/\__, /
// /____/ v 0.0 - Development
//
// Module: vrudy_top.v
// Version: 0.0
// Description:
// Top-level module of the vRudy processor.
// The design is based on the "Rudimentary Machine", as described in
//
// Pastor, E., Sanchez, F., & Del Corral, A. M. (1998, June). A rudimentary machine:
// Experiences in the design of a pedagogic computer. In Proceedings of the 1998
// workshop on Computer architecture education (p. 7). ACM.
//
//----------------------------------------------------------------------------------------
module vrudy_top (
//------------------------------
// Top level control signals
//------------------------------
input wire clk,
input wire rst_n,
//------------------------------
// Memory interface
//------------------------------
input wire [15:0] m_out,
output wire [15:0] m_in,
output wire [7:0] m_at,
output wire m_rw
);
ctrl_top control (
// Top level control signals
.clk ( clk ),
.rst_n ( rst_n ),
// Control inputs
.ir ( ir ),
.cond ( cond ),
// Control outputs
.ld_ra ( ld_ra ),
.ld_ir ( ld_ir ),
.ld_pc ( ld_pc ),
.ld_rat ( ld_rat ),
.ld_rz ( ld_rz ),
.ld_rn ( ld_rn ),
.pc_at ( pc_at ),
.crf ( crf ),
.erd ( erd ),
.rw ( rw ),
.operate( operate )
);
dpth_top datapath (
// Top level control signals
.clk ( clk ),
.rst_n ( rst_n ),
// Inputs from control
.ld_ra ( ld_ra ),
.ld_ir ( ld_ir ),
.ld_pc ( ld_pc ),
.ld_rat ( ld_rat ),
.ld_rz ( ld_rz ),
.ld_rn ( ld_rn ),
.pc_at ( pc_at ),
.crf ( crf ),
.erd ( erd ),
.operate( operate ),
// Outputs to control
.ir_ctrl( ir ),
.cond ( cond ),
// Input from memory
.m_out ( m_out ),
// Outputs to memory
.m_in ( m_in ),
.m_at ( m_at )
);
endmodule
//----------------------------------------------------------------------------------------
// Trivia: In Polish, brudy means "dirty laundry". Luckily, the processor's name is
// spelled with a 'v' instead...
//----------------------------------------------------------------------------------------
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module nfa_accept_sample (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address,
nfa_initials_buckets_datain,
nfa_initials_buckets_dataout,
nfa_initials_buckets_size,
nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address,
nfa_finals_buckets_datain,
nfa_finals_buckets_dataout,
nfa_finals_buckets_size,
nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address,
nfa_forward_buckets_datain,
nfa_forward_buckets_dataout,
nfa_forward_buckets_size,
nfa_symbols,
sample_req_din,
sample_req_full_n,
sample_req_write,
sample_rsp_empty_n,
sample_rsp_read,
sample_address,
sample_datain,
sample_dataout,
sample_size,
empty,
length_r,
ap_return
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output nfa_initials_buckets_req_din;
input nfa_initials_buckets_req_full_n;
output nfa_initials_buckets_req_write;
input nfa_initials_buckets_rsp_empty_n;
output nfa_initials_buckets_rsp_read;
output [31:0] nfa_initials_buckets_address;
input [31:0] nfa_initials_buckets_datain;
output [31:0] nfa_initials_buckets_dataout;
output [31:0] nfa_initials_buckets_size;
output nfa_finals_buckets_req_din;
input nfa_finals_buckets_req_full_n;
output nfa_finals_buckets_req_write;
input nfa_finals_buckets_rsp_empty_n;
output nfa_finals_buckets_rsp_read;
output [31:0] nfa_finals_buckets_address;
input [31:0] nfa_finals_buckets_datain;
output [31:0] nfa_finals_buckets_dataout;
output [31:0] nfa_finals_buckets_size;
output nfa_forward_buckets_req_din;
input nfa_forward_buckets_req_full_n;
output nfa_forward_buckets_req_write;
input nfa_forward_buckets_rsp_empty_n;
output nfa_forward_buckets_rsp_read;
output [31:0] nfa_forward_buckets_address;
input [31:0] nfa_forward_buckets_datain;
output [31:0] nfa_forward_buckets_dataout;
output [31:0] nfa_forward_buckets_size;
input [7:0] nfa_symbols;
output sample_req_din;
input sample_req_full_n;
output sample_req_write;
input sample_rsp_empty_n;
output sample_rsp_read;
output [31:0] sample_address;
input [7:0] sample_datain;
output [7:0] sample_dataout;
output [31:0] sample_size;
input [31:0] empty;
input [15:0] length_r;
output [0:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg nfa_forward_buckets_req_write;
reg nfa_forward_buckets_rsp_read;
reg[31:0] nfa_forward_buckets_address;
reg sample_req_write;
reg sample_rsp_read;
reg[0:0] ap_return;
reg [5:0] ap_CS_fsm = 6'b000000;
reg [31:0] reg_374;
reg [31:0] current_buckets_0_reg_577;
reg [31:0] current_buckets_1_reg_582;
wire [0:0] tmp_s_fu_397_p2;
reg [0:0] tmp_s_reg_597;
wire [15:0] grp_fu_402_p2;
reg [15:0] i_1_reg_601;
reg [31:0] sample_addr_1_reg_606;
wire [0:0] tmp_2_i_fu_420_p2;
reg [0:0] tmp_2_i_reg_612;
wire [31:0] grp_fu_414_p2;
reg [31:0] p_rec_reg_616;
reg [7:0] sym_reg_621;
wire [0:0] tmp_2_1_i_fu_426_p2;
reg [0:0] tmp_2_1_i_reg_626;
wire [4:0] grp_p_bsf32_hw_fu_368_ap_return;
reg [4:0] r_bit_reg_630;
wire [1:0] agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1;
wire [7:0] j_bucket_index1_ph_cast_fu_436_p1;
wire [7:0] j_bit1_ph_cast_fu_440_p1;
wire [13:0] tmp_18_i_cast_fu_444_p1;
reg [13:0] tmp_18_i_cast_reg_650;
wire [0:0] j_end_phi_fu_312_p4;
wire [5:0] grp_fu_463_p2;
reg [5:0] state_reg_665;
wire [13:0] grp_fu_476_p2;
reg [13:0] tmp_17_i_reg_680;
wire [13:0] grp_fu_482_p2;
reg [13:0] offset_i_reg_685;
reg [7:0] j_bit_reg_701;
reg [7:0] j_bucket_index_reg_706;
reg [31:0] j_bucket_reg_711;
reg [0:0] p_s_reg_716;
wire [31:0] next_buckets_0_1_fu_538_p2;
reg [31:0] next_buckets_0_1_reg_721;
wire [31:0] next_buckets_1_1_fu_544_p2;
reg [31:0] tmp_buckets_0_reg_731;
reg [31:0] tmp_buckets_1_reg_736;
wire [31:0] current_buckets_0_1_fu_558_p2;
reg [31:0] current_buckets_0_1_reg_741;
wire [31:0] current_buckets_1_1_fu_563_p2;
reg [31:0] current_buckets_1_1_reg_746;
wire [31:0] tmp_1_fu_568_p2;
reg [31:0] tmp_1_reg_751;
wire [0:0] tmp_2_fu_572_p2;
reg [0:0] tmp_2_reg_756;
wire [31:0] grp_bitset_next_fu_344_p_read;
wire [7:0] grp_bitset_next_fu_344_r_bit;
wire [7:0] grp_bitset_next_fu_344_r_bucket_index;
wire [31:0] grp_bitset_next_fu_344_r_bucket;
wire [7:0] grp_bitset_next_fu_344_ap_return_0;
wire [7:0] grp_bitset_next_fu_344_ap_return_1;
wire [31:0] grp_bitset_next_fu_344_ap_return_2;
wire [0:0] grp_bitset_next_fu_344_ap_return_3;
reg grp_bitset_next_fu_344_ap_ce;
reg grp_nfa_get_initials_fu_356_ap_start;
wire grp_nfa_get_initials_fu_356_ap_done;
wire grp_nfa_get_initials_fu_356_ap_idle;
wire grp_nfa_get_initials_fu_356_ap_ready;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_address;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_size;
wire grp_nfa_get_initials_fu_356_ap_ce;
wire [31:0] grp_nfa_get_initials_fu_356_ap_return_0;
wire [31:0] grp_nfa_get_initials_fu_356_ap_return_1;
wire grp_nfa_get_finals_fu_362_ap_start;
wire grp_nfa_get_finals_fu_362_ap_done;
wire grp_nfa_get_finals_fu_362_ap_idle;
wire grp_nfa_get_finals_fu_362_ap_ready;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_address;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_size;
wire grp_nfa_get_finals_fu_362_ap_ce;
wire [31:0] grp_nfa_get_finals_fu_362_ap_return_0;
wire [31:0] grp_nfa_get_finals_fu_362_ap_return_1;
wire [31:0] grp_p_bsf32_hw_fu_368_bus_r;
reg grp_p_bsf32_hw_fu_368_ap_ce;
reg [15:0] i_reg_134;
wire [0:0] any_phi_fu_324_p4;
reg [31:0] p_01_rec_reg_146;
reg [31:0] next_buckets_1_reg_158;
reg [31:0] next_buckets_0_reg_168;
reg [31:0] bus_assign_reg_178;
reg [0:0] agg_result_bucket_index_0_lcssa4_i_reg_190;
reg [31:0] j_bucket1_ph_reg_203;
reg [1:0] j_bucket_index1_ph_reg_216;
reg [4:0] j_bit1_ph_reg_227;
reg [0:0] j_end_ph_reg_238;
reg [31:0] tmp_buckets_1_3_reg_252;
reg [31:0] tmp_buckets_0_3_reg_265;
reg [31:0] j_bucket1_reg_278;
reg [7:0] j_bucket_index1_reg_289;
reg [7:0] j_bit1_reg_299;
reg [0:0] j_end_reg_309;
reg [0:0] any_reg_319;
reg [0:0] p_0_reg_332;
reg [5:0] ap_NS_fsm;
reg grp_nfa_get_finals_fu_362_ap_start_ap_start_reg = 1'b0;
wire [31:0] grp_fu_392_p2;
wire [31:0] tmp_5_i_cast_fu_493_p1;
wire [31:0] tmp_6_i_cast_fu_511_p1;
wire [31:0] grp_fu_392_p0;
wire [31:0] grp_fu_392_p1;
wire [15:0] grp_fu_402_p0;
wire [15:0] grp_fu_402_p1;
wire [31:0] grp_fu_414_p0;
wire [31:0] grp_fu_414_p1;
wire [0:0] tmp_5_fu_447_p1;
wire [5:0] grp_fu_463_p0;
wire [5:0] grp_fu_463_p1;
wire [7:0] grp_fu_476_p0;
wire [5:0] grp_fu_476_p1;
wire [13:0] grp_fu_482_p0;
wire [13:0] grp_fu_482_p1;
wire [14:0] tmp_5_i_fu_486_p3;
wire [14:0] tmp_6_i_fu_504_p3;
wire grp_fu_392_ce;
wire grp_fu_402_ce;
reg grp_fu_414_ce;
wire grp_fu_463_ce;
wire grp_fu_476_ce;
wire grp_fu_482_ce;
reg [0:0] ap_return_preg = 1'b0;
wire [13:0] grp_fu_476_p00;
wire [13:0] grp_fu_476_p10;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 6'b000000;
parameter ap_ST_st2_fsm_1 = 6'b1;
parameter ap_ST_st3_fsm_2 = 6'b10;
parameter ap_ST_st4_fsm_3 = 6'b11;
parameter ap_ST_st5_fsm_4 = 6'b100;
parameter ap_ST_st6_fsm_5 = 6'b101;
parameter ap_ST_st7_fsm_6 = 6'b110;
parameter ap_ST_st8_fsm_7 = 6'b111;
parameter ap_ST_st9_fsm_8 = 6'b1000;
parameter ap_ST_st10_fsm_9 = 6'b1001;
parameter ap_ST_st11_fsm_10 = 6'b1010;
parameter ap_ST_st12_fsm_11 = 6'b1011;
parameter ap_ST_st13_fsm_12 = 6'b1100;
parameter ap_ST_st14_fsm_13 = 6'b1101;
parameter ap_ST_st15_fsm_14 = 6'b1110;
parameter ap_ST_st16_fsm_15 = 6'b1111;
parameter ap_ST_st17_fsm_16 = 6'b10000;
parameter ap_ST_st18_fsm_17 = 6'b10001;
parameter ap_ST_st19_fsm_18 = 6'b10010;
parameter ap_ST_st20_fsm_19 = 6'b10011;
parameter ap_ST_st21_fsm_20 = 6'b10100;
parameter ap_ST_st22_fsm_21 = 6'b10101;
parameter ap_ST_st23_fsm_22 = 6'b10110;
parameter ap_ST_st24_fsm_23 = 6'b10111;
parameter ap_ST_st25_fsm_24 = 6'b11000;
parameter ap_ST_st26_fsm_25 = 6'b11001;
parameter ap_ST_st27_fsm_26 = 6'b11010;
parameter ap_ST_st28_fsm_27 = 6'b11011;
parameter ap_ST_st29_fsm_28 = 6'b11100;
parameter ap_ST_st30_fsm_29 = 6'b11101;
parameter ap_ST_st31_fsm_30 = 6'b11110;
parameter ap_ST_st32_fsm_31 = 6'b11111;
parameter ap_ST_st33_fsm_32 = 6'b100000;
parameter ap_ST_st34_fsm_33 = 6'b100001;
parameter ap_ST_st35_fsm_34 = 6'b100010;
parameter ap_ST_st36_fsm_35 = 6'b100011;
parameter ap_ST_st37_fsm_36 = 6'b100100;
parameter ap_ST_st38_fsm_37 = 6'b100101;
parameter ap_ST_st39_fsm_38 = 6'b100110;
parameter ap_ST_st40_fsm_39 = 6'b100111;
parameter ap_ST_st41_fsm_40 = 6'b101000;
parameter ap_ST_st42_fsm_41 = 6'b101001;
parameter ap_ST_st43_fsm_42 = 6'b101010;
parameter ap_ST_st44_fsm_43 = 6'b101011;
parameter ap_ST_st45_fsm_44 = 6'b101100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv16_1 = 16'b1;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_true = 1'b1;
bitset_next grp_bitset_next_fu_344(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p_read( grp_bitset_next_fu_344_p_read ),
.r_bit( grp_bitset_next_fu_344_r_bit ),
.r_bucket_index( grp_bitset_next_fu_344_r_bucket_index ),
.r_bucket( grp_bitset_next_fu_344_r_bucket ),
.ap_return_0( grp_bitset_next_fu_344_ap_return_0 ),
.ap_return_1( grp_bitset_next_fu_344_ap_return_1 ),
.ap_return_2( grp_bitset_next_fu_344_ap_return_2 ),
.ap_return_3( grp_bitset_next_fu_344_ap_return_3 ),
.ap_ce( grp_bitset_next_fu_344_ap_ce )
);
nfa_get_initials grp_nfa_get_initials_fu_356(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_initials_fu_356_ap_start ),
.ap_done( grp_nfa_get_initials_fu_356_ap_done ),
.ap_idle( grp_nfa_get_initials_fu_356_ap_idle ),
.ap_ready( grp_nfa_get_initials_fu_356_ap_ready ),
.nfa_initials_buckets_req_din( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din ),
.nfa_initials_buckets_req_full_n( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n ),
.nfa_initials_buckets_req_write( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write ),
.nfa_initials_buckets_rsp_empty_n( grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n ),
.nfa_initials_buckets_rsp_read( grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read ),
.nfa_initials_buckets_address( grp_nfa_get_initials_fu_356_nfa_initials_buckets_address ),
.nfa_initials_buckets_datain( grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain ),
.nfa_initials_buckets_dataout( grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout ),
.nfa_initials_buckets_size( grp_nfa_get_initials_fu_356_nfa_initials_buckets_size ),
.ap_ce( grp_nfa_get_initials_fu_356_ap_ce ),
.ap_return_0( grp_nfa_get_initials_fu_356_ap_return_0 ),
.ap_return_1( grp_nfa_get_initials_fu_356_ap_return_1 )
);
nfa_get_finals grp_nfa_get_finals_fu_362(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_finals_fu_362_ap_start ),
.ap_done( grp_nfa_get_finals_fu_362_ap_done ),
.ap_idle( grp_nfa_get_finals_fu_362_ap_idle ),
.ap_ready( grp_nfa_get_finals_fu_362_ap_ready ),
.nfa_finals_buckets_req_din( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din ),
.nfa_finals_buckets_req_full_n( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n ),
.nfa_finals_buckets_req_write( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write ),
.nfa_finals_buckets_rsp_empty_n( grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n ),
.nfa_finals_buckets_rsp_read( grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read ),
.nfa_finals_buckets_address( grp_nfa_get_finals_fu_362_nfa_finals_buckets_address ),
.nfa_finals_buckets_datain( grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain ),
.nfa_finals_buckets_dataout( grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout ),
.nfa_finals_buckets_size( grp_nfa_get_finals_fu_362_nfa_finals_buckets_size ),
.ap_ce( grp_nfa_get_finals_fu_362_ap_ce ),
.ap_return_0( grp_nfa_get_finals_fu_362_ap_return_0 ),
.ap_return_1( grp_nfa_get_finals_fu_362_ap_return_1 )
);
p_bsf32_hw grp_p_bsf32_hw_fu_368(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.bus_r( grp_p_bsf32_hw_fu_368_bus_r ),
.ap_return( grp_p_bsf32_hw_fu_368_ap_return ),
.ap_ce( grp_p_bsf32_hw_fu_368_ap_ce )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 17 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U17(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_392_p0 ),
.din1( grp_fu_392_p1 ),
.ce( grp_fu_392_ce ),
.dout( grp_fu_392_p2 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 #(
.ID( 18 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 16 ),
.din1_WIDTH( 16 ),
.dout_WIDTH( 16 ))
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_402_p0 ),
.din1( grp_fu_402_p1 ),
.ce( grp_fu_402_ce ),
.dout( grp_fu_402_p2 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 19 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U19(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_414_p0 ),
.din1( grp_fu_414_p1 ),
.ce( grp_fu_414_ce ),
.dout( grp_fu_414_p2 )
);
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 #(
.ID( 20 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 6 ),
.din1_WIDTH( 6 ),
.dout_WIDTH( 6 ))
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_463_p0 ),
.din1( grp_fu_463_p1 ),
.ce( grp_fu_463_ce ),
.dout( grp_fu_463_p2 )
);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 #(
.ID( 21 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 6 ),
.dout_WIDTH( 14 ))
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_U21(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_476_p0 ),
.din1( grp_fu_476_p1 ),
.ce( grp_fu_476_ce ),
.dout( grp_fu_476_p2 )
);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 #(
.ID( 22 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 14 ),
.din1_WIDTH( 14 ),
.dout_WIDTH( 14 ))
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_482_p0 ),
.din1( grp_fu_482_p1 ),
.ce( grp_fu_482_ce ),
.dout( grp_fu_482_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_return_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_preg
if (ap_rst == 1'b1) begin
ap_return_preg <= ap_const_lv1_0;
end else begin
if ((ap_ST_st45_fsm_44 == ap_CS_fsm)) begin
ap_return_preg <= p_0_reg_332;
end
end
end
/// grp_nfa_get_finals_fu_362_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_nfa_get_finals_fu_362_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st12_fsm_11 == ap_NS_fsm) & (ap_ST_st11_fsm_10 == ap_CS_fsm) & (tmp_s_reg_597 == ap_const_lv1_0))) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_nfa_get_finals_fu_362_ap_ready)) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & (tmp_2_1_i_reg_626 == ap_const_lv1_0))) begin
agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_1;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_2_i_reg_612 == ap_const_lv1_0))) begin
agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
any_reg_319 <= ap_const_lv1_0;
end else if ((ap_ST_st38_fsm_37 == ap_CS_fsm)) begin
any_reg_319 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & (tmp_2_1_i_reg_626 == ap_const_lv1_0))) begin
bus_assign_reg_178 <= next_buckets_1_reg_158;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_2_i_reg_612 == ap_const_lv1_0))) begin
bus_assign_reg_178 <= next_buckets_0_reg_168;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
i_reg_134 <= i_1_reg_601;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
i_reg_134 <= ap_const_lv16_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bit1_reg_299 <= j_bit1_ph_cast_fu_440_p1;
end else if ((ap_ST_st38_fsm_37 == ap_CS_fsm)) begin
j_bit1_reg_299 <= j_bit_reg_701;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bucket1_ph_reg_203 <= bus_assign_reg_178;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_2_1_i_reg_626 == ap_const_lv1_0))) begin
j_bucket1_ph_reg_203 <= ap_const_lv32_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bucket1_reg_278 <= j_bucket1_ph_reg_203;
end else if ((ap_ST_st38_fsm_37 == ap_CS_fsm)) begin
j_bucket1_reg_278 <= j_bucket_reg_711;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bucket_index1_ph_reg_216 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_2_1_i_reg_626 == ap_const_lv1_0))) begin
j_bucket_index1_ph_reg_216 <= ap_const_lv2_2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bucket_index1_reg_289 <= j_bucket_index1_ph_cast_fu_436_p1;
end else if ((ap_ST_st38_fsm_37 == ap_CS_fsm)) begin
j_bucket_index1_reg_289 <= j_bucket_index_reg_706;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_end_ph_reg_238 <= ap_const_lv1_0;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_2_1_i_reg_626 == ap_const_lv1_0))) begin
j_end_ph_reg_238 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_end_reg_309 <= j_end_ph_reg_238;
end else if ((ap_ST_st38_fsm_37 == ap_CS_fsm)) begin
j_end_reg_309 <= p_s_reg_716;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
next_buckets_0_reg_168 <= tmp_buckets_0_3_reg_265;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
next_buckets_0_reg_168 <= current_buckets_0_reg_577;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
next_buckets_1_reg_158 <= tmp_buckets_1_3_reg_252;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
next_buckets_1_reg_158 <= current_buckets_1_reg_582;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
p_01_rec_reg_146 <= p_rec_reg_616;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
p_01_rec_reg_146 <= ap_const_lv32_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & (ap_const_lv1_0 == any_phi_fu_324_p4))) begin
p_0_reg_332 <= ap_const_lv1_0;
end else if ((ap_ST_st44_fsm_43 == ap_CS_fsm)) begin
p_0_reg_332 <= tmp_2_reg_756;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_buckets_0_3_reg_265 <= ap_const_lv32_0;
end else if ((ap_ST_st38_fsm_37 == ap_CS_fsm)) begin
tmp_buckets_0_3_reg_265 <= next_buckets_0_1_reg_721;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_buckets_1_3_reg_252 <= ap_const_lv32_0;
end else if ((ap_ST_st38_fsm_37 == ap_CS_fsm)) begin
tmp_buckets_1_3_reg_252 <= next_buckets_1_1_fu_544_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st41_fsm_40 == ap_CS_fsm)) begin
current_buckets_0_1_reg_741 <= current_buckets_0_1_fu_558_p2;
current_buckets_1_1_reg_746 <= current_buckets_1_1_fu_563_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st3_fsm_2 == ap_CS_fsm)) begin
current_buckets_0_reg_577 <= grp_nfa_get_initials_fu_356_ap_return_0;
current_buckets_1_reg_582 <= grp_nfa_get_initials_fu_356_ap_return_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st8_fsm_7 == ap_CS_fsm)) begin
i_1_reg_601 <= grp_fu_402_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bit1_ph_reg_227 <= r_bit_reg_630;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st36_fsm_35 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0))) begin
j_bit_reg_701 <= grp_bitset_next_fu_344_ap_return_0;
j_bucket_index_reg_706 <= grp_bitset_next_fu_344_ap_return_1;
j_bucket_reg_711 <= grp_bitset_next_fu_344_ap_return_2;
p_s_reg_716 <= grp_bitset_next_fu_344_ap_return_3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st37_fsm_36 == ap_CS_fsm))) begin
next_buckets_0_1_reg_721 <= next_buckets_0_1_fu_538_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st34_fsm_33 == ap_CS_fsm)) begin
offset_i_reg_685 <= grp_fu_482_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0))) begin
p_rec_reg_616 <= grp_fu_414_p2;
sym_reg_621 <= sample_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st22_fsm_21 == ap_CS_fsm)) begin
r_bit_reg_630 <= grp_p_bsf32_hw_fu_368_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st36_fsm_35 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st37_fsm_36 == ap_CS_fsm)))) begin
reg_374 <= nfa_forward_buckets_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st12_fsm_11 == ap_CS_fsm)) begin
sample_addr_1_reg_606 <= grp_fu_392_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st26_fsm_25 == ap_CS_fsm)) begin
state_reg_665 <= grp_fu_463_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st30_fsm_29 == ap_CS_fsm)) begin
tmp_17_i_reg_680 <= grp_fu_476_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_18_i_cast_reg_650[0] <= tmp_18_i_cast_fu_444_p1[0];
tmp_18_i_cast_reg_650[1] <= tmp_18_i_cast_fu_444_p1[1];
tmp_18_i_cast_reg_650[2] <= tmp_18_i_cast_fu_444_p1[2];
tmp_18_i_cast_reg_650[3] <= tmp_18_i_cast_fu_444_p1[3];
tmp_18_i_cast_reg_650[4] <= tmp_18_i_cast_fu_444_p1[4];
tmp_18_i_cast_reg_650[5] <= tmp_18_i_cast_fu_444_p1[5];
tmp_18_i_cast_reg_650[6] <= tmp_18_i_cast_fu_444_p1[6];
tmp_18_i_cast_reg_650[7] <= tmp_18_i_cast_fu_444_p1[7];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st42_fsm_41 == ap_CS_fsm)) begin
tmp_1_reg_751 <= tmp_1_fu_568_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & ~(tmp_2_i_reg_612 == ap_const_lv1_0))) begin
tmp_2_1_i_reg_626 <= tmp_2_1_i_fu_426_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
tmp_2_i_reg_612 <= tmp_2_i_fu_420_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
tmp_2_reg_756 <= tmp_2_fu_572_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st40_fsm_39 == ap_CS_fsm)) begin
tmp_buckets_0_reg_731 <= grp_nfa_get_finals_fu_362_ap_return_0;
tmp_buckets_1_reg_736 <= grp_nfa_get_finals_fu_362_ap_return_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st5_fsm_4 == ap_CS_fsm)) begin
tmp_s_reg_597 <= tmp_s_fu_397_p2;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm)) | (ap_ST_st45_fsm_44 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st45_fsm_44 == ap_CS_fsm)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_return assign process. ///
always @ (ap_CS_fsm or p_0_reg_332 or ap_return_preg)
begin
if ((ap_ST_st45_fsm_44 == ap_CS_fsm)) begin
ap_return = p_0_reg_332;
end else begin
ap_return = ap_return_preg;
end
end
/// grp_bitset_next_fu_344_ap_ce assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or j_end_phi_fu_312_p4)
begin
if ((((ap_ST_st36_fsm_35 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | ((ap_ST_st25_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == j_end_phi_fu_312_p4)) | (ap_ST_st26_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_29 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm) | (ap_ST_st28_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_28 == ap_CS_fsm) | (ap_ST_st31_fsm_30 == ap_CS_fsm) | (ap_ST_st32_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm))) begin
grp_bitset_next_fu_344_ap_ce = ap_const_logic_1;
end else begin
grp_bitset_next_fu_344_ap_ce = ap_const_logic_0;
end
end
/// grp_fu_414_ce assign process. ///
always @ (ap_CS_fsm or sample_rsp_empty_n or tmp_s_reg_597)
begin
if (((ap_ST_st18_fsm_17 == ap_CS_fsm) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0)) | ((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(tmp_s_reg_597 == ap_const_lv1_0)) | (ap_ST_st13_fsm_12 == ap_CS_fsm) | (ap_ST_st14_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_14 == ap_CS_fsm) | (ap_ST_st16_fsm_15 == ap_CS_fsm) | (ap_ST_st17_fsm_16 == ap_CS_fsm))) begin
grp_fu_414_ce = ap_const_logic_1;
end else begin
grp_fu_414_ce = ap_const_logic_0;
end
end
/// grp_nfa_get_initials_fu_356_ap_start assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
grp_nfa_get_initials_fu_356_ap_start = ap_const_logic_1;
end else begin
grp_nfa_get_initials_fu_356_ap_start = ap_const_logic_0;
end
end
/// grp_p_bsf32_hw_fu_368_ap_ce assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) | (ap_ST_st21_fsm_20 == ap_CS_fsm))) begin
grp_p_bsf32_hw_fu_368_ap_ce = ap_const_logic_1;
end else begin
grp_p_bsf32_hw_fu_368_ap_ce = ap_const_logic_0;
end
end
/// nfa_forward_buckets_address assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or tmp_5_i_cast_fu_493_p1 or tmp_6_i_cast_fu_511_p1)
begin
if (((ap_ST_st36_fsm_35 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0))) begin
nfa_forward_buckets_address = tmp_6_i_cast_fu_511_p1;
end else if ((ap_ST_st35_fsm_34 == ap_CS_fsm)) begin
nfa_forward_buckets_address = tmp_5_i_cast_fu_493_p1;
end else begin
nfa_forward_buckets_address = 'bx;
end
end
/// nfa_forward_buckets_req_write assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st36_fsm_35 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (ap_ST_st35_fsm_34 == ap_CS_fsm))) begin
nfa_forward_buckets_req_write = ap_const_logic_1;
end else begin
nfa_forward_buckets_req_write = ap_const_logic_0;
end
end
/// nfa_forward_buckets_rsp_read assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st36_fsm_35 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st37_fsm_36 == ap_CS_fsm)))) begin
nfa_forward_buckets_rsp_read = ap_const_logic_1;
end else begin
nfa_forward_buckets_rsp_read = ap_const_logic_0;
end
end
/// sample_req_write assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sample_req_write = ap_const_logic_1;
end else begin
sample_req_write = ap_const_logic_0;
end
end
/// sample_rsp_read assign process. ///
always @ (ap_CS_fsm or sample_rsp_empty_n)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0))) begin
sample_rsp_read = ap_const_logic_1;
end else begin
sample_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or sample_rsp_empty_n or tmp_s_reg_597 or tmp_2_i_reg_612 or tmp_2_1_i_reg_626 or j_end_phi_fu_312_p4 or any_phi_fu_324_p4)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
ap_ST_st2_fsm_1 :
ap_NS_fsm = ap_ST_st3_fsm_2;
ap_ST_st3_fsm_2 :
ap_NS_fsm = ap_ST_st4_fsm_3;
ap_ST_st4_fsm_3 :
ap_NS_fsm = ap_ST_st5_fsm_4;
ap_ST_st5_fsm_4 :
ap_NS_fsm = ap_ST_st6_fsm_5;
ap_ST_st6_fsm_5 :
ap_NS_fsm = ap_ST_st7_fsm_6;
ap_ST_st7_fsm_6 :
ap_NS_fsm = ap_ST_st8_fsm_7;
ap_ST_st8_fsm_7 :
ap_NS_fsm = ap_ST_st9_fsm_8;
ap_ST_st9_fsm_8 :
ap_NS_fsm = ap_ST_st10_fsm_9;
ap_ST_st10_fsm_9 :
ap_NS_fsm = ap_ST_st11_fsm_10;
ap_ST_st11_fsm_10 :
ap_NS_fsm = ap_ST_st12_fsm_11;
ap_ST_st12_fsm_11 :
if ((tmp_s_reg_597 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st39_fsm_38;
end else begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st13_fsm_12 :
ap_NS_fsm = ap_ST_st14_fsm_13;
ap_ST_st14_fsm_13 :
ap_NS_fsm = ap_ST_st15_fsm_14;
ap_ST_st15_fsm_14 :
ap_NS_fsm = ap_ST_st16_fsm_15;
ap_ST_st16_fsm_15 :
ap_NS_fsm = ap_ST_st17_fsm_16;
ap_ST_st17_fsm_16 :
ap_NS_fsm = ap_ST_st18_fsm_17;
ap_ST_st18_fsm_17 :
ap_NS_fsm = ap_ST_st19_fsm_18;
ap_ST_st19_fsm_18 :
if ((~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_2_i_reg_612 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end else if ((~(sample_rsp_empty_n == ap_const_logic_0) & ~(tmp_2_i_reg_612 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end else begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end
ap_ST_st20_fsm_19 :
if (~(tmp_2_1_i_reg_626 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end else begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end
ap_ST_st21_fsm_20 :
ap_NS_fsm = ap_ST_st22_fsm_21;
ap_ST_st22_fsm_21 :
ap_NS_fsm = ap_ST_st23_fsm_22;
ap_ST_st23_fsm_22 :
ap_NS_fsm = ap_ST_st24_fsm_23;
ap_ST_st24_fsm_23 :
ap_NS_fsm = ap_ST_st25_fsm_24;
ap_ST_st25_fsm_24 :
if ((~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end else if ((~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & (ap_const_lv1_0 == any_phi_fu_324_p4))) begin
ap_NS_fsm = ap_ST_st45_fsm_44;
end else begin
ap_NS_fsm = ap_ST_st26_fsm_25;
end
ap_ST_st26_fsm_25 :
ap_NS_fsm = ap_ST_st27_fsm_26;
ap_ST_st27_fsm_26 :
ap_NS_fsm = ap_ST_st28_fsm_27;
ap_ST_st28_fsm_27 :
ap_NS_fsm = ap_ST_st29_fsm_28;
ap_ST_st29_fsm_28 :
ap_NS_fsm = ap_ST_st30_fsm_29;
ap_ST_st30_fsm_29 :
ap_NS_fsm = ap_ST_st31_fsm_30;
ap_ST_st31_fsm_30 :
ap_NS_fsm = ap_ST_st32_fsm_31;
ap_ST_st32_fsm_31 :
ap_NS_fsm = ap_ST_st33_fsm_32;
ap_ST_st33_fsm_32 :
ap_NS_fsm = ap_ST_st34_fsm_33;
ap_ST_st34_fsm_33 :
ap_NS_fsm = ap_ST_st35_fsm_34;
ap_ST_st35_fsm_34 :
ap_NS_fsm = ap_ST_st36_fsm_35;
ap_ST_st36_fsm_35 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end else begin
ap_NS_fsm = ap_ST_st36_fsm_35;
end
ap_ST_st37_fsm_36 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st38_fsm_37;
end else begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end
ap_ST_st38_fsm_37 :
ap_NS_fsm = ap_ST_st25_fsm_24;
ap_ST_st39_fsm_38 :
ap_NS_fsm = ap_ST_st40_fsm_39;
ap_ST_st40_fsm_39 :
ap_NS_fsm = ap_ST_st41_fsm_40;
ap_ST_st41_fsm_40 :
ap_NS_fsm = ap_ST_st42_fsm_41;
ap_ST_st42_fsm_41 :
ap_NS_fsm = ap_ST_st43_fsm_42;
ap_ST_st43_fsm_42 :
ap_NS_fsm = ap_ST_st44_fsm_43;
ap_ST_st44_fsm_43 :
ap_NS_fsm = ap_ST_st45_fsm_44;
ap_ST_st45_fsm_44 :
ap_NS_fsm = ap_ST_st1_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 = $unsigned(agg_result_bucket_index_0_lcssa4_i_reg_190);
assign any_phi_fu_324_p4 = any_reg_319;
assign current_buckets_0_1_fu_558_p2 = (next_buckets_0_reg_168 & tmp_buckets_0_reg_731);
assign current_buckets_1_1_fu_563_p2 = (next_buckets_1_reg_158 & tmp_buckets_1_reg_736);
assign grp_bitset_next_fu_344_p_read = next_buckets_1_reg_158;
assign grp_bitset_next_fu_344_r_bit = j_bit1_reg_299;
assign grp_bitset_next_fu_344_r_bucket = j_bucket1_reg_278;
assign grp_bitset_next_fu_344_r_bucket_index = j_bucket_index1_reg_289;
assign grp_fu_392_ce = ap_const_logic_1;
assign grp_fu_392_p0 = p_01_rec_reg_146;
assign grp_fu_392_p1 = empty;
assign grp_fu_402_ce = ap_const_logic_1;
assign grp_fu_402_p0 = i_reg_134;
assign grp_fu_402_p1 = ap_const_lv16_1;
assign grp_fu_414_p0 = p_01_rec_reg_146;
assign grp_fu_414_p1 = ap_const_lv32_1;
assign grp_fu_463_ce = ap_const_logic_1;
assign grp_fu_463_p0 = {{tmp_5_fu_447_p1}, {ap_const_lv5_0}};
assign grp_fu_463_p1 = j_bit1_reg_299[5:0];
assign grp_fu_476_ce = ap_const_logic_1;
assign grp_fu_476_p0 = grp_fu_476_p00;
assign grp_fu_476_p00 = $unsigned(nfa_symbols);
assign grp_fu_476_p1 = grp_fu_476_p10;
assign grp_fu_476_p10 = $unsigned(state_reg_665);
assign grp_fu_482_ce = ap_const_logic_1;
assign grp_fu_482_p0 = tmp_17_i_reg_680;
assign grp_fu_482_p1 = tmp_18_i_cast_reg_650;
assign grp_nfa_get_finals_fu_362_ap_ce = ap_const_logic_1;
assign grp_nfa_get_finals_fu_362_ap_start = grp_nfa_get_finals_fu_362_ap_start_ap_start_reg;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain = nfa_finals_buckets_datain;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n = nfa_finals_buckets_req_full_n;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n = nfa_finals_buckets_rsp_empty_n;
assign grp_nfa_get_initials_fu_356_ap_ce = ap_const_logic_1;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain = nfa_initials_buckets_datain;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n = nfa_initials_buckets_req_full_n;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n = nfa_initials_buckets_rsp_empty_n;
assign grp_p_bsf32_hw_fu_368_bus_r = bus_assign_reg_178;
assign j_bit1_ph_cast_fu_440_p1 = $unsigned(j_bit1_ph_reg_227);
assign j_bucket_index1_ph_cast_fu_436_p1 = $unsigned(j_bucket_index1_ph_reg_216);
assign j_end_phi_fu_312_p4 = j_end_reg_309;
assign next_buckets_0_1_fu_538_p2 = (tmp_buckets_0_3_reg_265 | reg_374);
assign next_buckets_1_1_fu_544_p2 = (tmp_buckets_1_3_reg_252 | reg_374);
assign nfa_finals_buckets_address = grp_nfa_get_finals_fu_362_nfa_finals_buckets_address;
assign nfa_finals_buckets_dataout = grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout;
assign nfa_finals_buckets_req_din = grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din;
assign nfa_finals_buckets_req_write = grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write;
assign nfa_finals_buckets_rsp_read = grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read;
assign nfa_finals_buckets_size = grp_nfa_get_finals_fu_362_nfa_finals_buckets_size;
assign nfa_forward_buckets_dataout = ap_const_lv32_0;
assign nfa_forward_buckets_req_din = ap_const_logic_0;
assign nfa_forward_buckets_size = ap_const_lv32_1;
assign nfa_initials_buckets_address = grp_nfa_get_initials_fu_356_nfa_initials_buckets_address;
assign nfa_initials_buckets_dataout = grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout;
assign nfa_initials_buckets_req_din = grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din;
assign nfa_initials_buckets_req_write = grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write;
assign nfa_initials_buckets_rsp_read = grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read;
assign nfa_initials_buckets_size = grp_nfa_get_initials_fu_356_nfa_initials_buckets_size;
assign sample_address = sample_addr_1_reg_606;
assign sample_dataout = ap_const_lv8_0;
assign sample_req_din = ap_const_logic_0;
assign sample_size = ap_const_lv32_1;
assign tmp_18_i_cast_fu_444_p1 = $unsigned(sym_reg_621);
assign tmp_1_fu_568_p2 = (current_buckets_1_1_reg_746 | current_buckets_0_1_reg_741);
assign tmp_2_1_i_fu_426_p2 = (next_buckets_1_reg_158 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_2_fu_572_p2 = (tmp_1_reg_751 != ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_2_i_fu_420_p2 = (next_buckets_0_reg_168 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_5_fu_447_p1 = j_bucket_index1_reg_289[0:0];
assign tmp_5_i_cast_fu_493_p1 = $unsigned(tmp_5_i_fu_486_p3);
assign tmp_5_i_fu_486_p3 = {{offset_i_reg_685}, {ap_const_lv1_0}};
assign tmp_6_i_cast_fu_511_p1 = $unsigned(tmp_6_i_fu_504_p3);
assign tmp_6_i_fu_504_p3 = {{offset_i_reg_685}, {ap_const_lv1_1}};
assign tmp_s_fu_397_p2 = (i_reg_134 < length_r? 1'b1: 1'b0);
always @ (posedge ap_clk)
begin
tmp_18_i_cast_reg_650[13:8] <= 6'b000000;
end
endmodule //nfa_accept_sample
|
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response)
and the DMA channel, arbitrates between the active channels, and forwards
the result to the transmit output pins.
Arbitration Priority:
1) host writes (highest)
2) read requests from host
3) read responses
*/
module etx_arbiter (/*AUTOARG*/
// Outputs
txwr_wait, txrd_wait, txrr_wait, etx_access, etx_packet, etx_rr,
// Inputs
clk, reset, txwr_access, txwr_packet, txrd_access, txrd_packet,
txrr_access, txrr_packet, etx_rd_wait, etx_wr_wait, etx_cfg_wait,
ctrlmode_bypass, ctrlmode
);
parameter PW = 104;
parameter ID = 0;
//tx clock and reset
input clk;
input reset;
//Write Request (from slave)
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Request (from slave)
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Read Response (from master)
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Wait signal inputs
input etx_rd_wait;
input etx_wr_wait;
input etx_cfg_wait;
//ctrlmode for rd/wr transactions
input ctrlmode_bypass;
input [3:0] ctrlmode;
//Transaction for IO protocol
output etx_access;
output [PW-1:0] etx_packet;
output etx_rr; //bypass translation on read response
//regs
reg etx_access;
reg [PW-1:0] etx_packet;
reg etx_rr; //bypass translation on read response
//wires
wire [3:0] txrd_ctrlmode;
wire [3:0] txwr_ctrlmode;
wire access_in;
wire [PW-1:0] etx_packet_mux;
wire txrr_grant;
wire txrd_grant;
wire txwr_grant;
wire txrr_arb_wait;
wire txrd_arb_wait;
wire txwr_arb_wait;
wire [PW-1:0] txrd_data;
wire [PW-1:0] txwr_data;
wire [PW-1:0] etx_mux;
wire write_in;
//##########################################################################
//# Insert special control mode
//##########################################################################
assign txrd_ctrlmode[3:0] = ctrlmode_bypass ? ctrlmode[3:0] :
txrd_packet[7:4];
assign txrd_data[PW-1:0] = {txrd_packet[PW-1:8],
txrd_ctrlmode[3:0],
txrd_packet[3:0]};
assign txwr_ctrlmode[3:0] = ctrlmode_bypass ? ctrlmode[3:0] :
txwr_packet[7:4];
assign txwr_data[PW-1:0] = {txwr_packet[PW-1:8],
txwr_ctrlmode[3:0],
txwr_packet[3:0]};
//##########################################################################
//# Arbiter
//##########################################################################
arbiter_priority #(.ARW(3)) arbiter (.grant({txrr_grant,
txrd_grant,
txwr_grant //highest priority
}),
.await({txrr_arb_wait,
txrd_arb_wait,
txwr_arb_wait
}),
.request({txrr_access,
txrd_access,
txwr_access
})
);
//Priority Mux
assign etx_mux[PW-1:0] =({(PW){txwr_grant}} & txwr_data[PW-1:0]) |
({(PW){txrd_grant}} & txrd_data[PW-1:0]) |
({(PW){txrr_grant}} & txrr_packet[PW-1:0]);
//######################################################################
//Pushback (stall) Signals
//######################################################################
//Write waits on pin wr wait or cfg_wait
assign txwr_wait = etx_wr_wait |
etx_cfg_wait;
//Host read request (self throttling, one read at a time)
assign txrd_wait = etx_rd_wait |
etx_cfg_wait |
txrd_arb_wait;
//Read response
assign txrr_wait = etx_wr_wait |
etx_cfg_wait |
txrr_arb_wait;
//#####################################################################
//# Pipeline stage (arbiter+mux takes time..)
//#####################################################################
assign access_in = (txwr_grant & ~txwr_wait) |
(txrd_grant & ~txrd_wait) |
(txrr_grant & ~txrr_wait);
//Pipeline + stall
assign write_in = etx_mux[1];
//access
always @ (posedge clk)
if (reset)
begin
etx_access <= 1'b0;
etx_rr <= 1'b0;
end
else if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
begin
etx_access <= access_in;
etx_rr <= txrr_grant;
end
//packet
always @ (posedge clk)
if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
etx_packet[PW-1:0] <= etx_mux[PW-1:0];
endmodule // etx_arbiter
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:27:33 03/11/2015
// Design Name:
// Module Name: delay_line_gen_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delay_line_gen_test #(
parameter WIDTH = 0,
parameter DELAY = 0
)(
output clk,
output [WIDTH - 1:0] out
);
reg clk_mem = 0;
reg [WIDTH - 1:0] out_mem = 0;
assign clk = clk_mem;
assign out = out_mem;
integer i;
initial
begin
while(1)
begin
out_mem = out_mem + 1;
for(i = 0; i < (DELAY + 1); i = i + 1)
begin
#1;
clk_mem = 0;
#1;
clk_mem = 1;
end
#1;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// CMOS PAD
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_cmos_pad(oe ,bsr_si ,rst_io_l ,se ,rst_val_up ,data ,
mode_ctl ,clock_dr ,update_dr ,rst_val_dn ,hiz_l ,
shift_dr ,bso ,to_core ,pad ,por_l, vddo );
output bso ;
output to_core ;
input oe ;
input bsr_si ;
input rst_io_l ;
input se ;
input rst_val_up ;
input data ;
input mode_ctl ;
input clock_dr ;
input update_dr ;
input rst_val_dn ;
input hiz_l ;
input shift_dr ;
input por_l ;
inout pad ;
input vddo ;
supply1 vdd ;
supply0 vss ;
wire q_up_pad ;
wire net84 ;
wire rcvr_data ;
wire bsr_dn_l ;
wire q_dn_pad_l ;
wire por ;
wire bsr_data_to_core ;
wire sel_data_n ;
wire pad_up ;
wire bsr_up ;
wire pad_dn_l ;
bw_io_cmos_edgelogic I2 (
.rcvr_data (rcvr_data ),
.to_core (to_core ),
.se (se ),
.bsr_up (q_up_pad ),
.bsr_dn_l (q_dn_pad_l ),
.pad_dn_l (pad_dn_l ),
.pad_up (pad_up ),
.oe (oe ),
.data (data ),
.por_l (por_l ),
.por (por ),
.bsr_data_to_core (bsr_data_to_core ),
.bsr_mode (mode_ctl ) );
bw_io_hstl_drv I3 (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.por (por ),
.bsr_dn_l (bsr_dn_l ),
.bsr_up (bsr_up ),
.pad_dn_l (pad_dn_l ),
.sel_data_n (sel_data_n ),
.pad_up (pad_up ),
.pad (pad ),
.vddo (vddo) );
bw_io_dtl_bscan bscan (
.bsr_data_to_core (bsr_data_to_core ),
.hiz_l (hiz_l ),
.rst_io_l (rst_io_l ),
.rst_val_dn (rst_val_dn ),
.rst_val_up (rst_val_up ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.update_dr (update_dr ),
.up_open (vdd ),
.bsr_so (bso ),
.se (se ),
.mode_ctl (mode_ctl ),
.bsr_si (bsr_si ),
.q_up_mux (bsr_up ),
.down_25 (vss ),
.sel_data_n (sel_data_n ),
.rcvr_data_to_bsr (rcvr_data ),
.q25_dn_pad_l (vdd ),
.q_dn_pad_l (q_dn_pad_l ),
.q_dn_mux_l (bsr_dn_l ),
.q25_dn_mux_l (net84 ),
.q_up_pad (q_up_pad ),
.serial_out (),
.bypass_enable (vss),
.clk (vss),
.bypass_in (vss),
.serial_in (vss),
.ps_select (vss),
.out_type (vss) );
bw_io_schmitt I41 (
.vddo (vddo ),
.out (rcvr_data ),
.in (pad ) );
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CPU Write SM
// File : sm_cpuwr.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// CPU Wite State Machine
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module sm_cpuwr
(
input ff_wr_pend,
input hreset_n,
input cpu_wr_gnt,
input crt_req,
input svga_ack,
input mem_clk,
output reg cpu_wr_req,
output cpu_wr_svga_req,
output enwr_cpu_ad_da_pl,
output cpu_fifo_read,
output reg int_cpu_fifo_rd,
output cpu_mem_wr,
output reg cpu_arb_wr
// output [2:0] probe
);
reg [2:0] current_state;
reg [2:0] next_state;
reg en_cpu_fifo_read;
reg wen;
reg int_cpu_wr_svga_req;
wire t32;
wire t34;
// assign probe = current_state;
parameter cpuwr_state0 = 3'b000,
cpuwr_state1 = 3'b001,
cpuwr_state2 = 3'b011,
cpuwr_state3 = 3'b111,
cpuwr_state4 = 3'b110;
assign t32 = (ff_wr_pend & (~crt_req));
assign t34 = ((~ff_wr_pend) | crt_req);
//
// Yes both the logic is same but different outputs
//
assign cpu_fifo_read = ff_wr_pend & en_cpu_fifo_read;
assign enwr_cpu_ad_da_pl = ff_wr_pend & en_cpu_fifo_read;
assign cpu_wr_svga_req = int_cpu_wr_svga_req & ff_wr_pend;
assign cpu_mem_wr = cpu_wr_req;
always @ (posedge mem_clk or negedge hreset_n) begin
if (hreset_n == 0) current_state = cpuwr_state0;
else current_state = next_state;
end
always @* begin
cpu_wr_req = 1'b0;
int_cpu_wr_svga_req = 1'b0;
int_cpu_fifo_rd = 1'b0;
en_cpu_fifo_read = 1'b0;
cpu_arb_wr = 1'b0;
case(current_state) // synopsys parallel_case full_case
cpuwr_state0: next_state = (ff_wr_pend) ? cpuwr_state1 : cpuwr_state0;
cpuwr_state1: begin
cpu_wr_req = 1'b1; // At state1, cpu_wr_req is active.
next_state = (cpu_wr_gnt) ? cpuwr_state2 : cpuwr_state1;
end
cpuwr_state2: begin
cpu_arb_wr = 1'b1;
cpu_wr_req = 1'b1;
int_cpu_wr_svga_req = 1'b1; // At state2, cpu_wr_svga_req is active.
int_cpu_fifo_rd = 1'b1; // At state2, int_cpu_fifo_r is active.
if (svga_ack)
next_state = cpuwr_state3;
else
next_state = cpuwr_state2;
end
cpuwr_state3: begin
cpu_wr_req = 1'b1;
cpu_arb_wr = 1'b1;
en_cpu_fifo_read = 1'b1;
next_state = cpuwr_state4;
end
cpuwr_state4: begin
cpu_wr_req = 1'b1;
cpu_arb_wr = 1'b1;
if (t34) next_state = cpuwr_state0;
else if (t32) next_state = cpuwr_state2;
else next_state = cpuwr_state4;
end
endcase
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_protocol_converter_v2_1_7_axi_protocol_converter,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_TEST_auto_pc_0,axi_protocol_converter_v2_1_7_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_TEST_auto_pc_0,axi_protocol_converter_v2_1_7_axi_protocol_converter,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_TEST_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [0 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_7_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_1_V
`define SKY130_FD_SC_HS__AND4BB_1_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_2_V
`define SKY130_FD_SC_MS__A32O_2_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_2_V
|
(* Copyright (c) 2008-2010, 2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import String List.
Require Import CpdtTactics DepList.
Set Implicit Arguments.
(* end hide *)
(** printing ~> $\leadsto$ *)
(** %\chapter{Generic Programming}% *)
(** %\index{generic programming}% _Generic programming_ makes it possible to write functions that operate over different types of data. %\index{parametric polymorphism}%Parametric polymorphism in ML and Haskell is one of the simplest examples. ML-style %\index{module systems}%module systems%~\cite{modules}% and Haskell %\index{type classes}%type classes%~\cite{typeclasses}% are more flexible cases. These language features are often not as powerful as we would like. For instance, while Haskell includes a type class classifying those types whose values can be pretty-printed, per-type pretty-printing is usually either implemented manually or implemented via a %\index{deriving clauses}%[deriving] clause%~\cite{deriving}%, which triggers ad-hoc code generation. Some clever encoding tricks have been used to achieve better within Haskell and other languages, but we can do%\index{datatype-generic programming}% _datatype-generic programming_ much more cleanly with dependent types. Thanks to the expressive power of CIC, we need no special language support.
Generic programming can often be very useful in Coq developments, so we devote this chapter to studying it. In a proof assistant, there is the new possibility of generic proofs about generic programs, which we also devote some space to. *)
(** * Reifying Datatype Definitions *)
(** The key to generic programming with dependent types is%\index{universe types}% _universe types_. This concept should not be confused with the idea of _universes_ from the metatheory of CIC and related languages, which we will study in more detail in the next chapter. Rather, the idea of universe types is to define inductive types that provide _syntactic representations_ of Coq types. We cannot directly write CIC programs that do case analysis on types, but we _can_ case analyze on reified syntactic versions of those types.
Thus, to begin, we must define a syntactic representation of some class of datatypes. In this chapter, our running example will have to do with basic algebraic datatypes, of the kind found in ML and Haskell, but without additional bells and whistles like type parameters and mutually recursive definitions.
The first step is to define a representation for constructors of our datatypes. We use the [Record] command as a shorthand for defining an inductive type with a single constructor, plus projection functions for pulling out any of the named arguments to that constructor. *)
(* EX: Define a reified representation of simple algebraic datatypes. *)
(* begin thide *)
Record constructor : Type := Con {
nonrecursive : Type;
recursive : nat
}.
(** The idea is that a constructor represented as [Con T n] has [n] arguments of the type that we are defining. Additionally, all of the other, non-recursive arguments can be encoded in the type [T]. When there are no non-recursive arguments, [T] can be [unit]. When there are two non-recursive arguments, of types [A] and [B], [T] can be [A * B]. We can generalize to any number of arguments via tupling.
With this definition, it is easy to define a datatype representation in terms of lists of constructors. The intended meaning is that the datatype came from an inductive definition including exactly the constructors in the list. *)
Definition datatype := list constructor.
(** Here are a few example encodings for some common types from the Coq standard library. While our syntax type does not support type parameters directly, we can implement them at the meta level, via functions from types to [datatype]s. *)
Definition Empty_set_dt : datatype := nil.
Definition unit_dt : datatype := Con unit 0 :: nil.
Definition bool_dt : datatype := Con unit 0 :: Con unit 0 :: nil.
Definition nat_dt : datatype := Con unit 0 :: Con unit 1 :: nil.
Definition list_dt (A : Type) : datatype := Con unit 0 :: Con A 1 :: nil.
(** The type [Empty_set] has no constructors, so its representation is the empty list. The type [unit] has one constructor with no arguments, so its one reified constructor indicates no non-recursive data and [0] recursive arguments. The representation for [bool] just duplicates this single argumentless constructor. We get from [bool] to [nat] by changing one of the constructors to indicate 1 recursive argument. We get from [nat] to [list] by adding a non-recursive argument of a parameter type [A].
As a further example, we can do the same encoding for a generic binary tree type. *)
(* end thide *)
Section tree.
Variable A : Type.
Inductive tree : Type :=
| Leaf : A -> tree
| Node : tree -> tree -> tree.
End tree.
(* begin thide *)
Definition tree_dt (A : Type) : datatype := Con A 0 :: Con unit 2 :: nil.
(** Each datatype representation stands for a family of inductive types. For a specific real datatype and a reputed representation for it, it is useful to define a type of _evidence_ that the datatype is compatible with the encoding. *)
Section denote.
Variable T : Type.
(** This variable stands for the concrete datatype that we are interested in. *)
Definition constructorDenote (c : constructor) :=
nonrecursive c -> ilist T (recursive c) -> T.
(** We write that a constructor is represented as a function returning a [T]. Such a function takes two arguments, which pack together the non-recursive and recursive arguments of the constructor. We represent a tuple of all recursive arguments using the length-indexed list type %\index{Gallina terms!ilist}%[ilist] that we met in Chapter 8. *)
Definition datatypeDenote := hlist constructorDenote.
(** Finally, the evidence for type [T] is a %\index{Gallina terms!hlist}%heterogeneous list, including a constructor denotation for every constructor encoding in a datatype encoding. Recall that, since we are inside a section binding [T] as a variable, [constructorDenote] is automatically parameterized by [T]. *)
End denote.
(* end thide *)
(** Some example pieces of evidence should help clarify the convention. First, we define a helpful notation for constructor denotations. %The ASCII \texttt{\textasciitilde{}>} from the notation will be rendered later as $\leadsto$.% *)
Notation "[ v , r ~> x ]" := ((fun v r => x) : constructorDenote _ (Con _ _)).
(* begin thide *)
Definition Empty_set_den : datatypeDenote Empty_set Empty_set_dt :=
HNil.
Definition unit_den : datatypeDenote unit unit_dt :=
[_, _ ~> tt] ::: HNil.
Definition bool_den : datatypeDenote bool bool_dt :=
[_, _ ~> true] ::: [_, _ ~> false] ::: HNil.
Definition nat_den : datatypeDenote nat nat_dt :=
[_, _ ~> O] ::: [_, r ~> S (hd r)] ::: HNil.
Definition list_den (A : Type) : datatypeDenote (list A) (list_dt A) :=
[_, _ ~> nil] ::: [x, r ~> x :: hd r] ::: HNil.
Definition tree_den (A : Type) : datatypeDenote (tree A) (tree_dt A) :=
[v, _ ~> Leaf v] ::: [_, r ~> Node (hd r) (hd (tl r))] ::: HNil.
(* end thide *)
(** Recall that the [hd] and [tl] calls above operate on richly typed lists, where type indices tell us the lengths of lists, guaranteeing the safety of operations like [hd]. The type annotation attached to each definition provides enough information for Coq to infer list lengths at appropriate points. *)
(** * Recursive Definitions *)
(* EX: Define a generic [size] function. *)
(** We built these encodings of datatypes to help us write datatype-generic recursive functions. To do so, we will want a reified representation of a%\index{recursion schemes}% _recursion scheme_ for each type, similar to the [T_rect] principle generated automatically for an inductive definition of [T]. A clever reuse of [datatypeDenote] yields a short definition. *)
(* begin thide *)
Definition fixDenote (T : Type) (dt : datatype) :=
forall (R : Type), datatypeDenote R dt -> (T -> R).
(** The idea of a recursion scheme is parameterized by a type and a reputed encoding of it. The principle itself is polymorphic in a type [R], which is the return type of the recursive function that we mean to write. The next argument is a heterogeneous list of one case of the recursive function definition for each datatype constructor. The [datatypeDenote] function turns out to have just the right definition to express the type we need; a set of function cases is just like an alternate set of constructors where we replace the original type [T] with the function result type [R]. Given such a reified definition, a [fixDenote] invocation returns a function from [T] to [R], which is just what we wanted.
We are ready to write some example functions now. It will be useful to use one new function from the [DepList] library included in the book source. *)
Check hmake.
(** %\vspace{-.15in}% [[
hmake
: forall (A : Type) (B : A -> Type),
(forall x : A, B x) -> forall ls : list A, hlist B ls
]]
The function [hmake] is a kind of [map] alternative that goes from a regular [list] to an [hlist]. We can use it to define a generic size function that counts the number of constructors used to build a value in a datatype. *)
Definition size T dt (fx : fixDenote T dt) : T -> nat :=
fx nat (hmake (B := constructorDenote nat) (fun _ _ r => foldr plus 1 r) dt).
(** Our definition is parameterized over a recursion scheme [fx]. We instantiate [fx] by passing it the function result type and a set of function cases, where we build the latter with [hmake]. The function argument to [hmake] takes three arguments: the representation of a constructor, its non-recursive arguments, and the results of recursive calls on all of its recursive arguments. We only need the recursive call results here, so we call them [r] and bind the other two inputs with wildcards. The actual case body is simple: we add together the recursive call results and increment the result by one (to account for the current constructor). This [foldr] function is an [ilist]-specific version defined in the [DepList] module.
It is instructive to build [fixDenote] values for our example types and see what specialized [size] functions result from them. *)
Definition Empty_set_fix : fixDenote Empty_set Empty_set_dt :=
fun R _ emp => match emp with end.
Eval compute in size Empty_set_fix.
(** %\vspace{-.15in}% [[
= fun emp : Empty_set => match emp return nat with
end
: Empty_set -> nat
]]
Despite all the fanciness of the generic [size] function, CIC's standard computation rules suffice to normalize the generic function specialization to exactly what we would have written manually. *)
Definition unit_fix : fixDenote unit unit_dt :=
fun R cases _ => (hhd cases) tt INil.
Eval compute in size unit_fix.
(** %\vspace{-.15in}% [[
= fun _ : unit => 1
: unit -> nat
]]
Again normalization gives us the natural function definition. We see this pattern repeated for our other example types. *)
Definition bool_fix : fixDenote bool bool_dt :=
fun R cases b => if b
then (hhd cases) tt INil
else (hhd (htl cases)) tt INil.
Eval compute in size bool_fix.
(** %\vspace{-.15in}% [[
= fun b : bool => if b then 1 else 1
: bool -> nat
]]
*)
Definition nat_fix : fixDenote nat nat_dt :=
fun R cases => fix F (n : nat) : R :=
match n with
| O => (hhd cases) tt INil
| S n' => (hhd (htl cases)) tt (ICons (F n') INil)
end.
(** To peek at the [size] function for [nat], it is useful to avoid full computation, so that the recursive definition of addition is not expanded inline. We can accomplish this with proper flags for the [cbv] reduction strategy. *)
Eval cbv beta iota delta -[plus] in size nat_fix.
(** %\vspace{-.15in}% [[
= fix F (n : nat) : nat := match n with
| 0 => 1
| S n' => F n' + 1
end
: nat -> nat
]]
*)
Definition list_fix (A : Type) : fixDenote (list A) (list_dt A) :=
fun R cases => fix F (ls : list A) : R :=
match ls with
| nil => (hhd cases) tt INil
| x :: ls' => (hhd (htl cases)) x (ICons (F ls') INil)
end.
Eval cbv beta iota delta -[plus] in fun A => size (@list_fix A).
(** %\vspace{-.15in}% [[
= fun A : Type =>
fix F (ls : list A) : nat :=
match ls with
| nil => 1
| _ :: ls' => F ls' + 1
end
: forall A : Type, list A -> nat
]]
*)
Definition tree_fix (A : Type) : fixDenote (tree A) (tree_dt A) :=
fun R cases => fix F (t : tree A) : R :=
match t with
| Leaf x => (hhd cases) x INil
| Node t1 t2 => (hhd (htl cases)) tt (ICons (F t1) (ICons (F t2) INil))
end.
Eval cbv beta iota delta -[plus] in fun A => size (@tree_fix A).
(** %\vspace{-.15in}% [[
= fun A : Type =>
fix F (t : tree A) : nat :=
match t with
| Leaf _ => 1
| Node t1 t2 => F t1 + (F t2 + 1)
end
: forall A : Type, tree A -> n
]]
*)
(* end thide *)
(** As our examples show, even recursive datatypes are mapped to normal-looking size functions. *)
(** ** Pretty-Printing *)
(** It is also useful to do generic pretty-printing of datatype values, rendering them as human-readable strings. To do so, we will need a bit of metadata for each constructor. Specifically, we need the name to print for the constructor and the function to use to render its non-recursive arguments. Everything else can be done generically. *)
Record print_constructor (c : constructor) : Type := PI {
printName : string;
printNonrec : nonrecursive c -> string
}.
(** It is useful to define a shorthand for applying the constructor [PI]. By applying it explicitly to an unknown application of the constructor [Con], we help type inference work. *)
Notation "^" := (PI (Con _ _)).
(** As in earlier examples, we define the type of metadata for a datatype to be a heterogeneous list type collecting metadata for each constructor. *)
Definition print_datatype := hlist print_constructor.
(** We will be doing some string manipulation here, so we import the notations associated with strings. *)
Local Open Scope string_scope.
(** Now it is easy to implement our generic printer, using another function from [DepList.] *)
Check hmap.
(** %\vspace{-.15in}% [[
hmap
: forall (A : Type) (B1 B2 : A -> Type),
(forall x : A, B1 x -> B2 x) ->
forall ls : list A, hlist B1 ls -> hlist B2 ls
]]
*)
Definition print T dt (pr : print_datatype dt) (fx : fixDenote T dt) : T -> string :=
fx string (hmap (B1 := print_constructor) (B2 := constructorDenote string)
(fun _ pc x r => printName pc ++ "(" ++ printNonrec pc x
++ foldr (fun s acc => ", " ++ s ++ acc) ")" r) pr).
(** Some simple tests establish that [print] gets the job done. *)
Eval compute in print HNil Empty_set_fix.
(** %\vspace{-.15in}% [[
= fun emp : Empty_set => match emp return string with
end
: Empty_set -> string
]]
*)
Eval compute in print (^ "tt" (fun _ => "") ::: HNil) unit_fix.
(** %\vspace{-.15in}% [[
= fun _ : unit => "tt()"
: unit -> string
]]
*)
Eval compute in print (^ "true" (fun _ => "")
::: ^ "false" (fun _ => "")
::: HNil) bool_fix.
(** %\vspace{-.15in}% [[
= fun b : bool => if b then "true()" else "false()"
: bool -> string
]]
*)
Definition print_nat := print (^ "O" (fun _ => "")
::: ^ "S" (fun _ => "")
::: HNil) nat_fix.
Eval cbv beta iota delta -[append] in print_nat.
(** %\vspace{-.15in}% [[
= fix F (n : nat) : string :=
match n with
| 0%nat => "O" ++ "(" ++ "" ++ ")"
| S n' => "S" ++ "(" ++ "" ++ ", " ++ F n' ++ ")"
end
: nat -> string
]]
*)
Eval simpl in print_nat 0.
(** %\vspace{-.15in}% [[
= "O()"
: string
]]
*)
Eval simpl in print_nat 1.
(** %\vspace{-.15in}% [[
= "S(, O())"
: string
]]
*)
Eval simpl in print_nat 2.
(** %\vspace{-.15in}% [[
= "S(, S(, O()))"
: string
]]
*)
Eval cbv beta iota delta -[append] in fun A (pr : A -> string) =>
print (^ "nil" (fun _ => "")
::: ^ "cons" pr
::: HNil) (@list_fix A).
(** %\vspace{-.15in}% [[
= fun (A : Type) (pr : A -> string) =>
fix F (ls : list A) : string :=
match ls with
| nil => "nil" ++ "(" ++ "" ++ ")"
| x :: ls' => "cons" ++ "(" ++ pr x ++ ", " ++ F ls' ++ ")"
end
: forall A : Type, (A -> string) -> list A -> string
]]
*)
Eval cbv beta iota delta -[append] in fun A (pr : A -> string) =>
print (^ "Leaf" pr
::: ^ "Node" (fun _ => "")
::: HNil) (@tree_fix A).
(** %\vspace{-.15in}% [[
= fun (A : Type) (pr : A -> string) =>
fix F (t : tree A) : string :=
match t with
| Leaf x => "Leaf" ++ "(" ++ pr x ++ ")"
| Node t1 t2 =>
"Node" ++ "(" ++ "" ++ ", " ++ F t1 ++ ", " ++ F t2 ++ ")"
end
: forall A : Type, (A -> string) -> tree A -> string
]]
*)
(* begin hide *)
(* begin thide *)
Definition append' := append.
(* end thide *)
(* end hide *)
(** Some of these simplified terms seem overly complex because we have turned off simplification of calls to [append], which is what uses of the [++] operator desugar to. Selective [++] simplification would combine adjacent string literals, yielding more or less the code we would write manually to implement this printing scheme. *)
(** ** Mapping *)
(** By this point, we have developed enough machinery that it is old hat to define a generic function similar to the list [map] function. *)
Definition map T dt (dd : datatypeDenote T dt) (fx : fixDenote T dt) (f : T -> T)
: T -> T :=
fx T (hmap (B1 := constructorDenote T) (B2 := constructorDenote T)
(fun _ c x r => f (c x r)) dd).
Eval compute in map Empty_set_den Empty_set_fix.
(** %\vspace{-.15in}% [[
= fun (_ : Empty_set -> Empty_set) (emp : Empty_set) =>
match emp return Empty_set with
end
: (Empty_set -> Empty_set) -> Empty_set -> Empty_set
]]
*)
Eval compute in map unit_den unit_fix.
(** %\vspace{-.15in}% [[
= fun (f : unit -> unit) (_ : unit) => f tt
: (unit -> unit) -> unit -> unit
]]
*)
Eval compute in map bool_den bool_fix.
(** %\vspace{-.15in}% [[
= fun (f : bool -> bool) (b : bool) => if b then f true else f false
: (bool -> bool) -> bool -> bool
]]
*)
Eval compute in map nat_den nat_fix.
(** %\vspace{-.15in}% [[
= fun f : nat -> nat =>
fix F (n : nat) : nat :=
match n with
| 0%nat => f 0%nat
| S n' => f (S (F n'))
end
: (nat -> nat) -> nat -> nat
]]
*)
Eval compute in fun A => map (list_den A) (@list_fix A).
(** %\vspace{-.15in}% [[
= fun (A : Type) (f : list A -> list A) =>
fix F (ls : list A) : list A :=
match ls with
| nil => f nil
| x :: ls' => f (x :: F ls')
end
: forall A : Type, (list A -> list A) -> list A -> list A
]]
*)
Eval compute in fun A => map (tree_den A) (@tree_fix A).
(** %\vspace{-.15in}% [[
= fun (A : Type) (f : tree A -> tree A) =>
fix F (t : tree A) : tree A :=
match t with
| Leaf x => f (Leaf x)
| Node t1 t2 => f (Node (F t1) (F t2))
end
: forall A : Type, (tree A -> tree A) -> tree A -> tree A
]]
*)
(** These [map] functions are just as easy to use as those we write by hand. Can you figure out the input-output pattern that [map_nat S] displays in these examples? *)
Definition map_nat := map nat_den nat_fix.
Eval simpl in map_nat S 0.
(** %\vspace{-.15in}% [[
= 1%nat
: nat
]]
*)
Eval simpl in map_nat S 1.
(** %\vspace{-.15in}% [[
= 3%nat
: nat
]]
*)
Eval simpl in map_nat S 2.
(** %\vspace{-.15in}% [[
= 5%nat
: nat
]]
*)
(** We get [map_nat S n] = [2 * n + 1], because the mapping process adds an extra [S] at every level of the inductive tree that defines a natural, including at the last level, the [O] constructor. *)
(** * Proving Theorems about Recursive Definitions *)
(** We would like to be able to prove theorems about our generic functions. To do so, we need to establish additional well-formedness properties that must hold of pieces of evidence. *)
Section ok.
Variable T : Type.
Variable dt : datatype.
Variable dd : datatypeDenote T dt.
Variable fx : fixDenote T dt.
(** First, we characterize when a piece of evidence about a datatype is acceptable. The basic idea is that the type [T] should really be an inductive type with the definition given by [dd]. Semantically, inductive types are characterized by the ability to do induction on them. Therefore, we require that the usual induction principle is true, with respect to the constructors given in the encoding [dd]. *)
Definition datatypeDenoteOk :=
forall P : T -> Prop,
(forall c (m : member c dt) (x : nonrecursive c) (r : ilist T (recursive c)),
(forall i : fin (recursive c), P (get r i))
-> P ((hget dd m) x r))
-> forall v, P v.
(** This definition can take a while to digest. The quantifier over [m : member c dt] is considering each constructor in turn; like in normal induction principles, each constructor has an associated proof case. The expression [hget dd m] then names the constructor we have selected. After binding [m], we quantify over all possible arguments (encoded with [x] and [r]) to the constructor that [m] selects. Within each specific case, we quantify further over [i : fin (recursive c)] to consider all of our induction hypotheses, one for each recursive argument of the current constructor.
We have completed half the burden of defining side conditions. The other half comes in characterizing when a recursion scheme [fx] is valid. The natural condition is that [fx] behaves appropriately when applied to any constructor application. *)
Definition fixDenoteOk :=
forall (R : Type) (cases : datatypeDenote R dt)
c (m : member c dt)
(x : nonrecursive c) (r : ilist T (recursive c)),
fx cases ((hget dd m) x r)
= (hget cases m) x (imap (fx cases) r).
(** As for [datatypeDenoteOk], we consider all constructors and all possible arguments to them by quantifying over [m], [x], and [r]. The lefthand side of the equality that follows shows a call to the recursive function on the specific constructor application that we selected. The righthand side shows an application of the function case associated with constructor [m], applied to the non-recursive arguments and to appropriate recursive calls on the recursive arguments. *)
End ok.
(** We are now ready to prove that the [size] function we defined earlier always returns positive results. First, we establish a simple lemma. *)
(* begin thide *)
Lemma foldr_plus : forall n (ils : ilist nat n),
foldr plus 1 ils > 0.
induction ils; crush.
Qed.
(* end thide *)
Theorem size_positive : forall T dt
(dd : datatypeDenote T dt) (fx : fixDenote T dt)
(dok : datatypeDenoteOk dd) (fok : fixDenoteOk dd fx)
(v : T),
size fx v > 0.
(* begin thide *)
unfold size; intros.
(** [[
============================
fx nat
(hmake
(fun (x : constructor) (_ : nonrecursive x)
(r : ilist nat (recursive x)) => foldr plus 1%nat r) dt) v > 0
]]
Our goal is an inequality over a particular call to [size], with its definition expanded. How can we proceed here? We cannot use [induction] directly, because there is no way for Coq to know that [T] is an inductive type. Instead, we need to use the induction principle encoded in our hypothesis [dok] of type [datatypeDenoteOk dd]. Let us try applying it directly.
[[
apply dok.
]]
%\vspace{-.3in}%
<<
Error: Impossible to unify "datatypeDenoteOk dd" with
"fx nat
(hmake
(fun (x : constructor) (_ : nonrecursive x)
(r : ilist nat (recursive x)) => foldr plus 1%nat r) dt) v > 0".
>>
Matching the type of [dok] with the type of our conclusion requires more than simple first-order unification, so [apply] is not up to the challenge. We can use the %\index{tactics!pattern}%[pattern] tactic to get our goal into a form that makes it apparent exactly what the induction hypothesis is. *)
pattern v.
(** %\vspace{-.15in}%[[
============================
(fun t : T =>
fx nat
(hmake
(fun (x : constructor) (_ : nonrecursive x)
(r : ilist nat (recursive x)) => foldr plus 1%nat r) dt) t > 0) v
]]
*)
apply dok; crush.
(** %\vspace{-.15in}%[[
H : forall i : fin (recursive c),
fx nat
(hmake
(fun (x : constructor) (_ : nonrecursive x)
(r : ilist nat (recursive x)) => foldr plus 1%nat r) dt)
(get r i) > 0
============================
hget
(hmake
(fun (x0 : constructor) (_ : nonrecursive x0)
(r0 : ilist nat (recursive x0)) => foldr plus 1%nat r0) dt) m x
(imap
(fx nat
(hmake
(fun (x0 : constructor) (_ : nonrecursive x0)
(r0 : ilist nat (recursive x0)) =>
foldr plus 1%nat r0) dt)) r) > 0
]]
An induction hypothesis [H] is generated, but we turn out not to need it for this example. We can simplify the goal using a library theorem about the composition of [hget] and [hmake]. *)
rewrite hget_hmake.
(** %\vspace{-.15in}%[[
============================
foldr plus 1%nat
(imap
(fx nat
(hmake
(fun (x0 : constructor) (_ : nonrecursive x0)
(r0 : ilist nat (recursive x0)) =>
foldr plus 1%nat r0) dt)) r) > 0
]]
The lemma we proved earlier finishes the proof. *)
apply foldr_plus.
(** Using hints, we can redo this proof in a nice automated form. *)
Restart.
Hint Rewrite hget_hmake.
Hint Resolve foldr_plus.
unfold size; intros; pattern v; apply dok; crush.
Qed.
(* end thide *)
(** It turned out that, in this example, we only needed to use induction degenerately as case analysis. A more involved theorem may only be proved using induction hypotheses. We will give its proof only in unautomated form and leave effective automation as an exercise for the motivated reader.
In particular, it ought to be the case that generic [map] applied to an identity function is itself an identity function. *)
Theorem map_id : forall T dt
(dd : datatypeDenote T dt) (fx : fixDenote T dt)
(dok : datatypeDenoteOk dd) (fok : fixDenoteOk dd fx)
(v : T),
map dd fx (fun x => x) v = v.
(* begin thide *)
(** Let us begin as we did in the last theorem, after adding another useful library equality as a hint. *)
Hint Rewrite hget_hmap.
unfold map; intros; pattern v; apply dok; crush.
(** %\vspace{-.15in}%[[
H : forall i : fin (recursive c),
fx T
(hmap
(fun (x : constructor) (c : constructorDenote T x)
(x0 : nonrecursive x) (r : ilist T (recursive x)) =>
c x0 r) dd) (get r i) = get r i
============================
hget dd m x
(imap
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd)) r) = hget dd m x r
]]
Our goal is an equality whose two sides begin with the same function call and initial arguments. We believe that the remaining arguments are in fact equal as well, and the [f_equal] tactic applies this reasoning step for us formally. *)
f_equal.
(** %\vspace{-.15in}%[[
============================
imap
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd)) r = r
]]
At this point, it is helpful to proceed by an inner induction on the heterogeneous list [r] of recursive call results. We could arrive at a cleaner proof by breaking this step out into an explicit lemma, but here we will do the induction inline to save space.*)
induction r; crush.
(* begin hide *)
(* begin thide *)
Definition pred' := pred.
(* end thide *)
(* end hide *)
(** The base case is discharged automatically, and the inductive case looks like this, where [H] is the outer IH (for induction over [T] values) and [IHr] is the inner IH (for induction over the recursive arguments).
[[
H : forall i : fin (S n),
fx T
(hmap
(fun (x : constructor) (c : constructorDenote T x)
(x0 : nonrecursive x) (r : ilist T (recursive x)) =>
c x0 r) dd)
(match i in (fin n') return ((fin (pred n') -> T) -> T) with
| First n => fun _ : fin n -> T => a
| Next n idx' => fun get_ls' : fin n -> T => get_ls' idx'
end (get r)) =
match i in (fin n') return ((fin (pred n') -> T) -> T) with
| First n => fun _ : fin n -> T => a
| Next n idx' => fun get_ls' : fin n -> T => get_ls' idx'
end (get r)
IHr : (forall i : fin n,
fx T
(hmap
(fun (x : constructor) (c : constructorDenote T x)
(x0 : nonrecursive x) (r : ilist T (recursive x)) =>
c x0 r) dd) (get r i) = get r i) ->
imap
(fx T
(hmap
(fun (x : constructor) (c : constructorDenote T x)
(x0 : nonrecursive x) (r : ilist T (recursive x)) =>
c x0 r) dd)) r = r
============================
ICons
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd) a)
(imap
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd)) r) = ICons a r
]]
We see another opportunity to apply [f_equal], this time to split our goal into two different equalities over corresponding arguments. After that, the form of the first goal matches our outer induction hypothesis [H], when we give type inference some help by specifying the right quantifier instantiation. *)
f_equal.
apply (H First).
(** %\vspace{-.15in}%[[
============================
imap
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd)) r = r
]]
Now the goal matches the inner IH [IHr]. *)
apply IHr; crush.
(** %\vspace{-.15in}%[[
i : fin n
============================
fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd) (get r i) = get r i
]]
We can finish the proof by applying the outer IH again, specialized to a different [fin] value. *)
apply (H (Next i)).
Qed.
(* end thide *)
(** The proof involves complex subgoals, but, still, few steps are required, and then we may reuse our work across a variety of datatypes. *)
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Memory_16x256.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Memory_16x256 (
aclr,
address,
clock,
data,
wren,
q);
input aclr;
input [7:0] address;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Sun Oct 28 11:02:37 EDT 2012
//
//
// Ports:
// Name I/O size props
// pcie_txp O 4
// pcie_txn O 4
// RDY_usr_sw O 1 const
// led O 8
// lcd_db O 4
// lcd_e O 1
// lcd_rs O 1
// lcd_rw O 1
// debug O 16 reg
// RDY_debug O 1 const
// gmii_tx_txd O 8
// gmii_tx_tx_en O 1
// gmii_tx_tx_er O 1
// gmii_led O 1 reg
// p125clk O 1 clock
// CLK_GATE_p125clk O 1 const
// rxclk O 1 clock
// CLK_GATE_rxclk O 1 const
// gmii_tx_tx_clk O 1 clock
// CLK_GATE_gmii_tx_tx_clk O 1 const
// p125rst O 1 reset
// gmii_rstn O 1 reset
// sys0_clkp I 1 clock
// sys0_clkn I 1 clock
// sys0_rstn I 1 reset
// sys1_clkp I 1 clock
// sys1_clkn I 1 clock
// gmii_rx_clk I 1 clock
// pci0_clkp I 1 clock
// pci0_clkn I 1 clock
// pci0_rstn I 1 reset
// pcie_rxp_i I 4
// pcie_rxn_i I 4
// usr_sw_i I 8 unused
// gmii_rx_rxd_i I 8 reg
// gmii_rx_rx_dv_i I 1 reg
// gmii_rx_rx_er_i I 1 reg
// gmii_col_i I 1
// gmii_crs_i I 1
// gmii_intr_i I 1
// EN_usr_sw I 1 unused
// mdio_mdd IO 1 inout
// mdio_mdc IO 1 inout
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFTop_kc705(sys0_clkp,
sys0_clkn,
sys0_rstn,
sys1_clkp,
sys1_clkn,
gmii_rx_clk,
pci0_clkp,
pci0_clkn,
pci0_rstn,
mdio_mdd,
mdio_mdc,
pcie_rxp_i,
pcie_rxn_i,
pcie_txp,
pcie_txn,
usr_sw_i,
EN_usr_sw,
RDY_usr_sw,
led,
lcd_db,
lcd_e,
lcd_rs,
lcd_rw,
debug,
RDY_debug,
gmii_rx_rxd_i,
gmii_rx_rx_dv_i,
gmii_rx_rx_er_i,
gmii_tx_txd,
gmii_tx_tx_en,
gmii_tx_tx_er,
gmii_col_i,
gmii_crs_i,
gmii_intr_i,
gmii_led,
p125clk,
CLK_GATE_p125clk,
rxclk,
CLK_GATE_rxclk,
gmii_tx_tx_clk,
CLK_GATE_gmii_tx_tx_clk,
p125rst,
gmii_rstn);
input sys0_clkp;
input sys0_clkn;
input sys0_rstn;
input sys1_clkp;
input sys1_clkn;
input gmii_rx_clk;
input pci0_clkp;
input pci0_clkn;
input pci0_rstn;
inout mdio_mdd;
inout mdio_mdc;
// action method pcie_rxp
input [3 : 0] pcie_rxp_i;
// action method pcie_rxn
input [3 : 0] pcie_rxn_i;
// value method pcie_txp
output [3 : 0] pcie_txp;
// value method pcie_txn
output [3 : 0] pcie_txn;
// action method usr_sw
input [7 : 0] usr_sw_i;
input EN_usr_sw;
output RDY_usr_sw;
// value method led
output [7 : 0] led;
// value method lcd_db
output [3 : 0] lcd_db;
// value method lcd_e
output lcd_e;
// value method lcd_rs
output lcd_rs;
// value method lcd_rw
output lcd_rw;
// value method debug
output [15 : 0] debug;
output RDY_debug;
// action method gmii_rx_rxd
input [7 : 0] gmii_rx_rxd_i;
// action method gmii_rx_rx_dv
input gmii_rx_rx_dv_i;
// action method gmii_rx_rx_er
input gmii_rx_rx_er_i;
// value method gmii_tx_txd
output [7 : 0] gmii_tx_txd;
// value method gmii_tx_tx_en
output gmii_tx_tx_en;
// value method gmii_tx_tx_er
output gmii_tx_tx_er;
// action method gmii_col
input gmii_col_i;
// action method gmii_crs
input gmii_crs_i;
// action method gmii_intr
input gmii_intr_i;
// value method gmii_led
output gmii_led;
// oscillator and gates for output clock p125clk
output p125clk;
output CLK_GATE_p125clk;
// oscillator and gates for output clock rxclk
output rxclk;
output CLK_GATE_rxclk;
// oscillator and gates for output clock gmii_tx_tx_clk
output gmii_tx_tx_clk;
output CLK_GATE_gmii_tx_tx_clk;
// output resets
output p125rst;
output gmii_rstn;
// signals for module outputs
wire [15 : 0] debug;
wire [7 : 0] gmii_tx_txd, led;
wire [3 : 0] lcd_db, pcie_txn, pcie_txp;
wire CLK_GATE_gmii_tx_tx_clk,
CLK_GATE_p125clk,
CLK_GATE_rxclk,
RDY_debug,
RDY_usr_sw,
gmii_led,
gmii_rstn,
gmii_tx_tx_clk,
gmii_tx_tx_en,
gmii_tx_tx_er,
lcd_e,
lcd_rs,
lcd_rw,
p125clk,
p125rst,
rxclk;
// inlined wires
wire [127 : 0] pciw_pci0_axiTxData$wget;
wire [95 : 0] cap0_wsiS_extStatusW$wget;
wire [71 : 0] cap0_wci_wslv_wciReq$wget;
wire [66 : 0] cap0_wtiS_wtiReq$wget;
wire [63 : 0] cap0_nowW$wget, cap0_wti_Es_mData_w$wget;
wire [60 : 0] cap0_wsiS_wsiReq$wget;
wire [33 : 0] cap0_wci_wslv_respF_x_wire$wget;
wire [31 : 0] cap0_dataBram_serverAdapterA_outData_enqData$wget,
cap0_dataBram_serverAdapterA_outData_outData$wget,
cap0_dataBram_serverAdapterB_outData_enqData$wget,
cap0_dataBram_serverAdapterB_outData_outData$wget,
cap0_metaBram_serverAdapterA_1_outData_enqData$wget,
cap0_metaBram_serverAdapterA_1_outData_outData$wget,
cap0_metaBram_serverAdapterA_2_outData_enqData$wget,
cap0_metaBram_serverAdapterA_2_outData_outData$wget,
cap0_metaBram_serverAdapterA_3_outData_enqData$wget,
cap0_metaBram_serverAdapterA_3_outData_outData$wget,
cap0_metaBram_serverAdapterA_outData_enqData$wget,
cap0_metaBram_serverAdapterA_outData_outData$wget,
cap0_metaBram_serverAdapterB_1_outData_enqData$wget,
cap0_metaBram_serverAdapterB_1_outData_outData$wget,
cap0_metaBram_serverAdapterB_2_outData_enqData$wget,
cap0_metaBram_serverAdapterB_2_outData_outData$wget,
cap0_metaBram_serverAdapterB_3_outData_enqData$wget,
cap0_metaBram_serverAdapterB_3_outData_outData$wget,
cap0_metaBram_serverAdapterB_outData_enqData$wget,
cap0_metaBram_serverAdapterB_outData_outData$wget,
cap0_statusReg_w$wget,
cap0_wci_wci_Es_mAddr_w$wget,
cap0_wci_wci_Es_mData_w$wget,
cap0_wsi_Es_mData_w$wget;
wire [15 : 0] pciw_pci0_axiTxKeep$wget;
wire [11 : 0] cap0_wsi_Es_mBurstLength_w$wget;
wire [7 : 0] cap0_wsi_Es_mReqInfo_w$wget;
wire [3 : 0] cap0_wci_wci_Es_mByteEn_w$wget,
cap0_wsi_Es_mByteEn_w$wget,
pciw_pci0_axiTxUser$wget;
wire [2 : 0] cap0_dataBram_serverAdapterA_cnt_1$wget,
cap0_dataBram_serverAdapterA_cnt_2$wget,
cap0_dataBram_serverAdapterA_cnt_3$wget,
cap0_dataBram_serverAdapterB_cnt_1$wget,
cap0_dataBram_serverAdapterB_cnt_2$wget,
cap0_dataBram_serverAdapterB_cnt_3$wget,
cap0_metaBram_serverAdapterA_1_cnt_1$wget,
cap0_metaBram_serverAdapterA_1_cnt_2$wget,
cap0_metaBram_serverAdapterA_1_cnt_3$wget,
cap0_metaBram_serverAdapterA_2_cnt_1$wget,
cap0_metaBram_serverAdapterA_2_cnt_2$wget,
cap0_metaBram_serverAdapterA_2_cnt_3$wget,
cap0_metaBram_serverAdapterA_3_cnt_1$wget,
cap0_metaBram_serverAdapterA_3_cnt_2$wget,
cap0_metaBram_serverAdapterA_3_cnt_3$wget,
cap0_metaBram_serverAdapterA_cnt_1$wget,
cap0_metaBram_serverAdapterA_cnt_2$wget,
cap0_metaBram_serverAdapterA_cnt_3$wget,
cap0_metaBram_serverAdapterB_1_cnt_1$wget,
cap0_metaBram_serverAdapterB_1_cnt_2$wget,
cap0_metaBram_serverAdapterB_1_cnt_3$wget,
cap0_metaBram_serverAdapterB_2_cnt_1$wget,
cap0_metaBram_serverAdapterB_2_cnt_2$wget,
cap0_metaBram_serverAdapterB_2_cnt_3$wget,
cap0_metaBram_serverAdapterB_3_cnt_1$wget,
cap0_metaBram_serverAdapterB_3_cnt_2$wget,
cap0_metaBram_serverAdapterB_3_cnt_3$wget,
cap0_metaBram_serverAdapterB_cnt_1$wget,
cap0_metaBram_serverAdapterB_cnt_2$wget,
cap0_metaBram_serverAdapterB_cnt_3$wget,
cap0_wci_wci_Es_mCmd_w$wget,
cap0_wci_wslv_wEdge$wget,
cap0_wsi_Es_mCmd_w$wget,
cap0_wti_Es_mCmd_w$wget;
wire [1 : 0] cap0_dataBram_serverAdapterA_s1_1$wget,
cap0_dataBram_serverAdapterA_writeWithResp$wget,
cap0_dataBram_serverAdapterB_s1_1$wget,
cap0_dataBram_serverAdapterB_writeWithResp$wget,
cap0_metaBram_serverAdapterA_1_s1_1$wget,
cap0_metaBram_serverAdapterA_1_writeWithResp$wget,
cap0_metaBram_serverAdapterA_2_s1_1$wget,
cap0_metaBram_serverAdapterA_2_writeWithResp$wget,
cap0_metaBram_serverAdapterA_3_s1_1$wget,
cap0_metaBram_serverAdapterA_3_writeWithResp$wget,
cap0_metaBram_serverAdapterA_s1_1$wget,
cap0_metaBram_serverAdapterA_writeWithResp$wget,
cap0_metaBram_serverAdapterB_1_s1_1$wget,
cap0_metaBram_serverAdapterB_1_writeWithResp$wget,
cap0_metaBram_serverAdapterB_2_s1_1$wget,
cap0_metaBram_serverAdapterB_2_writeWithResp$wget,
cap0_metaBram_serverAdapterB_3_s1_1$wget,
cap0_metaBram_serverAdapterB_3_writeWithResp$wget,
cap0_metaBram_serverAdapterB_s1_1$wget,
cap0_metaBram_serverAdapterB_writeWithResp$wget,
infLed$wget;
wire blinkLed$wget,
cap0_dataBram_serverAdapterA_cnt_1$whas,
cap0_dataBram_serverAdapterA_cnt_2$whas,
cap0_dataBram_serverAdapterA_cnt_3$whas,
cap0_dataBram_serverAdapterA_outData_deqCalled$whas,
cap0_dataBram_serverAdapterA_outData_enqData$whas,
cap0_dataBram_serverAdapterA_outData_outData$whas,
cap0_dataBram_serverAdapterA_s1_1$whas,
cap0_dataBram_serverAdapterA_writeWithResp$whas,
cap0_dataBram_serverAdapterB_cnt_1$whas,
cap0_dataBram_serverAdapterB_cnt_2$whas,
cap0_dataBram_serverAdapterB_cnt_3$whas,
cap0_dataBram_serverAdapterB_outData_deqCalled$whas,
cap0_dataBram_serverAdapterB_outData_enqData$whas,
cap0_dataBram_serverAdapterB_outData_outData$whas,
cap0_dataBram_serverAdapterB_s1_1$whas,
cap0_dataBram_serverAdapterB_writeWithResp$whas,
cap0_metaBram_serverAdapterA_1_cnt_1$whas,
cap0_metaBram_serverAdapterA_1_cnt_2$whas,
cap0_metaBram_serverAdapterA_1_cnt_3$whas,
cap0_metaBram_serverAdapterA_1_outData_deqCalled$whas,
cap0_metaBram_serverAdapterA_1_outData_enqData$whas,
cap0_metaBram_serverAdapterA_1_outData_outData$whas,
cap0_metaBram_serverAdapterA_1_s1_1$whas,
cap0_metaBram_serverAdapterA_1_writeWithResp$whas,
cap0_metaBram_serverAdapterA_2_cnt_1$whas,
cap0_metaBram_serverAdapterA_2_cnt_2$whas,
cap0_metaBram_serverAdapterA_2_cnt_3$whas,
cap0_metaBram_serverAdapterA_2_outData_deqCalled$whas,
cap0_metaBram_serverAdapterA_2_outData_enqData$whas,
cap0_metaBram_serverAdapterA_2_outData_outData$whas,
cap0_metaBram_serverAdapterA_2_s1_1$whas,
cap0_metaBram_serverAdapterA_2_writeWithResp$whas,
cap0_metaBram_serverAdapterA_3_cnt_1$whas,
cap0_metaBram_serverAdapterA_3_cnt_2$whas,
cap0_metaBram_serverAdapterA_3_cnt_3$whas,
cap0_metaBram_serverAdapterA_3_outData_deqCalled$whas,
cap0_metaBram_serverAdapterA_3_outData_enqData$whas,
cap0_metaBram_serverAdapterA_3_outData_outData$whas,
cap0_metaBram_serverAdapterA_3_s1_1$whas,
cap0_metaBram_serverAdapterA_3_writeWithResp$whas,
cap0_metaBram_serverAdapterA_cnt_1$whas,
cap0_metaBram_serverAdapterA_cnt_2$whas,
cap0_metaBram_serverAdapterA_cnt_3$whas,
cap0_metaBram_serverAdapterA_outData_deqCalled$whas,
cap0_metaBram_serverAdapterA_outData_enqData$whas,
cap0_metaBram_serverAdapterA_outData_outData$whas,
cap0_metaBram_serverAdapterA_s1_1$whas,
cap0_metaBram_serverAdapterA_writeWithResp$whas,
cap0_metaBram_serverAdapterB_1_cnt_1$whas,
cap0_metaBram_serverAdapterB_1_cnt_2$whas,
cap0_metaBram_serverAdapterB_1_cnt_3$whas,
cap0_metaBram_serverAdapterB_1_outData_deqCalled$whas,
cap0_metaBram_serverAdapterB_1_outData_enqData$whas,
cap0_metaBram_serverAdapterB_1_outData_outData$whas,
cap0_metaBram_serverAdapterB_1_s1_1$whas,
cap0_metaBram_serverAdapterB_1_writeWithResp$whas,
cap0_metaBram_serverAdapterB_2_cnt_1$whas,
cap0_metaBram_serverAdapterB_2_cnt_2$whas,
cap0_metaBram_serverAdapterB_2_cnt_3$whas,
cap0_metaBram_serverAdapterB_2_outData_deqCalled$whas,
cap0_metaBram_serverAdapterB_2_outData_enqData$whas,
cap0_metaBram_serverAdapterB_2_outData_outData$whas,
cap0_metaBram_serverAdapterB_2_s1_1$whas,
cap0_metaBram_serverAdapterB_2_writeWithResp$whas,
cap0_metaBram_serverAdapterB_3_cnt_1$whas,
cap0_metaBram_serverAdapterB_3_cnt_2$whas,
cap0_metaBram_serverAdapterB_3_cnt_3$whas,
cap0_metaBram_serverAdapterB_3_outData_deqCalled$whas,
cap0_metaBram_serverAdapterB_3_outData_enqData$whas,
cap0_metaBram_serverAdapterB_3_outData_outData$whas,
cap0_metaBram_serverAdapterB_3_s1_1$whas,
cap0_metaBram_serverAdapterB_3_writeWithResp$whas,
cap0_metaBram_serverAdapterB_cnt_1$whas,
cap0_metaBram_serverAdapterB_cnt_2$whas,
cap0_metaBram_serverAdapterB_cnt_3$whas,
cap0_metaBram_serverAdapterB_outData_deqCalled$whas,
cap0_metaBram_serverAdapterB_outData_enqData$whas,
cap0_metaBram_serverAdapterB_outData_outData$whas,
cap0_metaBram_serverAdapterB_s1_1$whas,
cap0_metaBram_serverAdapterB_writeWithResp$whas,
cap0_nowW$whas,
cap0_statusReg_w$whas,
cap0_wci_wci_Es_mAddrSpace_w$wget,
cap0_wci_wci_Es_mAddrSpace_w$whas,
cap0_wci_wci_Es_mAddr_w$whas,
cap0_wci_wci_Es_mByteEn_w$whas,
cap0_wci_wci_Es_mCmd_w$whas,
cap0_wci_wci_Es_mData_w$whas,
cap0_wci_wslv_ctlAckReg_1$wget,
cap0_wci_wslv_ctlAckReg_1$whas,
cap0_wci_wslv_reqF_r_clr$whas,
cap0_wci_wslv_reqF_r_deq$whas,
cap0_wci_wslv_reqF_r_enq$whas,
cap0_wci_wslv_respF_dequeueing$whas,
cap0_wci_wslv_respF_enqueueing$whas,
cap0_wci_wslv_respF_x_wire$whas,
cap0_wci_wslv_sFlagReg_1$wget,
cap0_wci_wslv_sFlagReg_1$whas,
cap0_wci_wslv_sThreadBusy_pw$whas,
cap0_wci_wslv_wEdge$whas,
cap0_wci_wslv_wciReq$whas,
cap0_wci_wslv_wci_cfrd_pw$whas,
cap0_wci_wslv_wci_cfwr_pw$whas,
cap0_wci_wslv_wci_ctrl_pw$whas,
cap0_wsiS_operateD_1$wget,
cap0_wsiS_operateD_1$whas,
cap0_wsiS_peerIsReady_1$wget,
cap0_wsiS_peerIsReady_1$whas,
cap0_wsiS_reqFifo_doResetClr$whas,
cap0_wsiS_reqFifo_doResetDeq$whas,
cap0_wsiS_reqFifo_doResetEnq$whas,
cap0_wsiS_reqFifo_r_clr$whas,
cap0_wsiS_reqFifo_r_deq$whas,
cap0_wsiS_reqFifo_r_enq$whas,
cap0_wsiS_sThreadBusy_dw$wget,
cap0_wsiS_sThreadBusy_dw$whas,
cap0_wsiS_wsiReq$whas,
cap0_wsi_Es_mBurstLength_w$whas,
cap0_wsi_Es_mBurstPrecise_w$whas,
cap0_wsi_Es_mByteEn_w$whas,
cap0_wsi_Es_mCmd_w$whas,
cap0_wsi_Es_mDataInfo_w$whas,
cap0_wsi_Es_mData_w$whas,
cap0_wsi_Es_mReqInfo_w$whas,
cap0_wsi_Es_mReqLast_w$whas,
cap0_wtiS_operateD_1$wget,
cap0_wtiS_operateD_1$whas,
cap0_wtiS_wtiReq$whas,
cap0_wti_Es_mCmd_w$whas,
cap0_wti_Es_mData_w$whas,
pciw_pci0_axiTxData$whas,
pciw_pci0_axiTxKeep$whas,
pciw_pci0_axiTxLast$wget,
pciw_pci0_axiTxLast$whas,
pciw_pci0_axiTxUser$whas,
pciw_pci0_axiTxValid$wget,
pciw_pci0_axiTxValid$whas;
// register cap0_controlReg
reg [31 : 0] cap0_controlReg;
wire [31 : 0] cap0_controlReg$D_IN;
wire cap0_controlReg$EN;
// register cap0_dataBram_serverAdapterA_cnt
reg [2 : 0] cap0_dataBram_serverAdapterA_cnt;
wire [2 : 0] cap0_dataBram_serverAdapterA_cnt$D_IN;
wire cap0_dataBram_serverAdapterA_cnt$EN;
// register cap0_dataBram_serverAdapterA_s1
reg [1 : 0] cap0_dataBram_serverAdapterA_s1;
wire [1 : 0] cap0_dataBram_serverAdapterA_s1$D_IN;
wire cap0_dataBram_serverAdapterA_s1$EN;
// register cap0_dataBram_serverAdapterB_cnt
reg [2 : 0] cap0_dataBram_serverAdapterB_cnt;
wire [2 : 0] cap0_dataBram_serverAdapterB_cnt$D_IN;
wire cap0_dataBram_serverAdapterB_cnt$EN;
// register cap0_dataBram_serverAdapterB_s1
reg [1 : 0] cap0_dataBram_serverAdapterB_s1;
wire [1 : 0] cap0_dataBram_serverAdapterB_s1$D_IN;
wire cap0_dataBram_serverAdapterB_s1$EN;
// register cap0_dataCount
reg [31 : 0] cap0_dataCount;
reg [31 : 0] cap0_dataCount$D_IN;
wire cap0_dataCount$EN;
// register cap0_isFirst
reg cap0_isFirst;
wire cap0_isFirst$D_IN, cap0_isFirst$EN;
// register cap0_mesgLengthSoFar
reg [13 : 0] cap0_mesgLengthSoFar;
wire [13 : 0] cap0_mesgLengthSoFar$D_IN;
wire cap0_mesgLengthSoFar$EN;
// register cap0_metaBram_serverAdapterA_1_cnt
reg [2 : 0] cap0_metaBram_serverAdapterA_1_cnt;
wire [2 : 0] cap0_metaBram_serverAdapterA_1_cnt$D_IN;
wire cap0_metaBram_serverAdapterA_1_cnt$EN;
// register cap0_metaBram_serverAdapterA_1_s1
reg [1 : 0] cap0_metaBram_serverAdapterA_1_s1;
wire [1 : 0] cap0_metaBram_serverAdapterA_1_s1$D_IN;
wire cap0_metaBram_serverAdapterA_1_s1$EN;
// register cap0_metaBram_serverAdapterA_2_cnt
reg [2 : 0] cap0_metaBram_serverAdapterA_2_cnt;
wire [2 : 0] cap0_metaBram_serverAdapterA_2_cnt$D_IN;
wire cap0_metaBram_serverAdapterA_2_cnt$EN;
// register cap0_metaBram_serverAdapterA_2_s1
reg [1 : 0] cap0_metaBram_serverAdapterA_2_s1;
wire [1 : 0] cap0_metaBram_serverAdapterA_2_s1$D_IN;
wire cap0_metaBram_serverAdapterA_2_s1$EN;
// register cap0_metaBram_serverAdapterA_3_cnt
reg [2 : 0] cap0_metaBram_serverAdapterA_3_cnt;
wire [2 : 0] cap0_metaBram_serverAdapterA_3_cnt$D_IN;
wire cap0_metaBram_serverAdapterA_3_cnt$EN;
// register cap0_metaBram_serverAdapterA_3_s1
reg [1 : 0] cap0_metaBram_serverAdapterA_3_s1;
wire [1 : 0] cap0_metaBram_serverAdapterA_3_s1$D_IN;
wire cap0_metaBram_serverAdapterA_3_s1$EN;
// register cap0_metaBram_serverAdapterA_cnt
reg [2 : 0] cap0_metaBram_serverAdapterA_cnt;
wire [2 : 0] cap0_metaBram_serverAdapterA_cnt$D_IN;
wire cap0_metaBram_serverAdapterA_cnt$EN;
// register cap0_metaBram_serverAdapterA_s1
reg [1 : 0] cap0_metaBram_serverAdapterA_s1;
wire [1 : 0] cap0_metaBram_serverAdapterA_s1$D_IN;
wire cap0_metaBram_serverAdapterA_s1$EN;
// register cap0_metaBram_serverAdapterB_1_cnt
reg [2 : 0] cap0_metaBram_serverAdapterB_1_cnt;
wire [2 : 0] cap0_metaBram_serverAdapterB_1_cnt$D_IN;
wire cap0_metaBram_serverAdapterB_1_cnt$EN;
// register cap0_metaBram_serverAdapterB_1_s1
reg [1 : 0] cap0_metaBram_serverAdapterB_1_s1;
wire [1 : 0] cap0_metaBram_serverAdapterB_1_s1$D_IN;
wire cap0_metaBram_serverAdapterB_1_s1$EN;
// register cap0_metaBram_serverAdapterB_2_cnt
reg [2 : 0] cap0_metaBram_serverAdapterB_2_cnt;
wire [2 : 0] cap0_metaBram_serverAdapterB_2_cnt$D_IN;
wire cap0_metaBram_serverAdapterB_2_cnt$EN;
// register cap0_metaBram_serverAdapterB_2_s1
reg [1 : 0] cap0_metaBram_serverAdapterB_2_s1;
wire [1 : 0] cap0_metaBram_serverAdapterB_2_s1$D_IN;
wire cap0_metaBram_serverAdapterB_2_s1$EN;
// register cap0_metaBram_serverAdapterB_3_cnt
reg [2 : 0] cap0_metaBram_serverAdapterB_3_cnt;
wire [2 : 0] cap0_metaBram_serverAdapterB_3_cnt$D_IN;
wire cap0_metaBram_serverAdapterB_3_cnt$EN;
// register cap0_metaBram_serverAdapterB_3_s1
reg [1 : 0] cap0_metaBram_serverAdapterB_3_s1;
wire [1 : 0] cap0_metaBram_serverAdapterB_3_s1$D_IN;
wire cap0_metaBram_serverAdapterB_3_s1$EN;
// register cap0_metaBram_serverAdapterB_cnt
reg [2 : 0] cap0_metaBram_serverAdapterB_cnt;
wire [2 : 0] cap0_metaBram_serverAdapterB_cnt$D_IN;
wire cap0_metaBram_serverAdapterB_cnt$EN;
// register cap0_metaBram_serverAdapterB_s1
reg [1 : 0] cap0_metaBram_serverAdapterB_s1;
wire [1 : 0] cap0_metaBram_serverAdapterB_s1$D_IN;
wire cap0_metaBram_serverAdapterB_s1$EN;
// register cap0_metaCount
reg [31 : 0] cap0_metaCount;
reg [31 : 0] cap0_metaCount$D_IN;
wire cap0_metaCount$EN;
// register cap0_splitReadInFlight
reg cap0_splitReadInFlight;
wire cap0_splitReadInFlight$D_IN, cap0_splitReadInFlight$EN;
// register cap0_wci_wslv_cEdge
reg [2 : 0] cap0_wci_wslv_cEdge;
wire [2 : 0] cap0_wci_wslv_cEdge$D_IN;
wire cap0_wci_wslv_cEdge$EN;
// register cap0_wci_wslv_cState
reg [2 : 0] cap0_wci_wslv_cState;
wire [2 : 0] cap0_wci_wslv_cState$D_IN;
wire cap0_wci_wslv_cState$EN;
// register cap0_wci_wslv_ctlAckReg
reg cap0_wci_wslv_ctlAckReg;
wire cap0_wci_wslv_ctlAckReg$D_IN, cap0_wci_wslv_ctlAckReg$EN;
// register cap0_wci_wslv_ctlOpActive
reg cap0_wci_wslv_ctlOpActive;
wire cap0_wci_wslv_ctlOpActive$D_IN, cap0_wci_wslv_ctlOpActive$EN;
// register cap0_wci_wslv_illegalEdge
reg cap0_wci_wslv_illegalEdge;
wire cap0_wci_wslv_illegalEdge$D_IN, cap0_wci_wslv_illegalEdge$EN;
// register cap0_wci_wslv_isReset_isInReset
reg cap0_wci_wslv_isReset_isInReset;
wire cap0_wci_wslv_isReset_isInReset$D_IN,
cap0_wci_wslv_isReset_isInReset$EN;
// register cap0_wci_wslv_nState
reg [2 : 0] cap0_wci_wslv_nState;
reg [2 : 0] cap0_wci_wslv_nState$D_IN;
wire cap0_wci_wslv_nState$EN;
// register cap0_wci_wslv_reqF_countReg
reg [1 : 0] cap0_wci_wslv_reqF_countReg;
wire [1 : 0] cap0_wci_wslv_reqF_countReg$D_IN;
wire cap0_wci_wslv_reqF_countReg$EN;
// register cap0_wci_wslv_respF_c_r
reg [1 : 0] cap0_wci_wslv_respF_c_r;
wire [1 : 0] cap0_wci_wslv_respF_c_r$D_IN;
wire cap0_wci_wslv_respF_c_r$EN;
// register cap0_wci_wslv_respF_q_0
reg [33 : 0] cap0_wci_wslv_respF_q_0;
reg [33 : 0] cap0_wci_wslv_respF_q_0$D_IN;
wire cap0_wci_wslv_respF_q_0$EN;
// register cap0_wci_wslv_respF_q_1
reg [33 : 0] cap0_wci_wslv_respF_q_1;
reg [33 : 0] cap0_wci_wslv_respF_q_1$D_IN;
wire cap0_wci_wslv_respF_q_1$EN;
// register cap0_wci_wslv_sFlagReg
reg cap0_wci_wslv_sFlagReg;
wire cap0_wci_wslv_sFlagReg$D_IN, cap0_wci_wslv_sFlagReg$EN;
// register cap0_wci_wslv_sThreadBusy_d
reg cap0_wci_wslv_sThreadBusy_d;
wire cap0_wci_wslv_sThreadBusy_d$D_IN, cap0_wci_wslv_sThreadBusy_d$EN;
// register cap0_wsiS_burstKind
reg [1 : 0] cap0_wsiS_burstKind;
wire [1 : 0] cap0_wsiS_burstKind$D_IN;
wire cap0_wsiS_burstKind$EN;
// register cap0_wsiS_errorSticky
reg cap0_wsiS_errorSticky;
wire cap0_wsiS_errorSticky$D_IN, cap0_wsiS_errorSticky$EN;
// register cap0_wsiS_iMesgCount
reg [31 : 0] cap0_wsiS_iMesgCount;
wire [31 : 0] cap0_wsiS_iMesgCount$D_IN;
wire cap0_wsiS_iMesgCount$EN;
// register cap0_wsiS_isReset_isInReset
reg cap0_wsiS_isReset_isInReset;
wire cap0_wsiS_isReset_isInReset$D_IN, cap0_wsiS_isReset_isInReset$EN;
// register cap0_wsiS_mesgWordLength
reg [11 : 0] cap0_wsiS_mesgWordLength;
wire [11 : 0] cap0_wsiS_mesgWordLength$D_IN;
wire cap0_wsiS_mesgWordLength$EN;
// register cap0_wsiS_operateD
reg cap0_wsiS_operateD;
wire cap0_wsiS_operateD$D_IN, cap0_wsiS_operateD$EN;
// register cap0_wsiS_pMesgCount
reg [31 : 0] cap0_wsiS_pMesgCount;
wire [31 : 0] cap0_wsiS_pMesgCount$D_IN;
wire cap0_wsiS_pMesgCount$EN;
// register cap0_wsiS_peerIsReady
reg cap0_wsiS_peerIsReady;
wire cap0_wsiS_peerIsReady$D_IN, cap0_wsiS_peerIsReady$EN;
// register cap0_wsiS_reqFifo_countReg
reg [1 : 0] cap0_wsiS_reqFifo_countReg;
wire [1 : 0] cap0_wsiS_reqFifo_countReg$D_IN;
wire cap0_wsiS_reqFifo_countReg$EN;
// register cap0_wsiS_reqFifo_levelsValid
reg cap0_wsiS_reqFifo_levelsValid;
wire cap0_wsiS_reqFifo_levelsValid$D_IN, cap0_wsiS_reqFifo_levelsValid$EN;
// register cap0_wsiS_statusR
reg [7 : 0] cap0_wsiS_statusR;
wire [7 : 0] cap0_wsiS_statusR$D_IN;
wire cap0_wsiS_statusR$EN;
// register cap0_wsiS_tBusyCount
reg [31 : 0] cap0_wsiS_tBusyCount;
wire [31 : 0] cap0_wsiS_tBusyCount$D_IN;
wire cap0_wsiS_tBusyCount$EN;
// register cap0_wsiS_trafficSticky
reg cap0_wsiS_trafficSticky;
wire cap0_wsiS_trafficSticky$D_IN, cap0_wsiS_trafficSticky$EN;
// register cap0_wsiS_wordCount
reg [11 : 0] cap0_wsiS_wordCount;
wire [11 : 0] cap0_wsiS_wordCount$D_IN;
wire cap0_wsiS_wordCount$EN;
// register cap0_wtiS_isReset_isInReset
reg cap0_wtiS_isReset_isInReset;
wire cap0_wtiS_isReset_isInReset$D_IN, cap0_wtiS_isReset_isInReset$EN;
// register cap0_wtiS_nowReq
reg [66 : 0] cap0_wtiS_nowReq;
wire [66 : 0] cap0_wtiS_nowReq$D_IN;
wire cap0_wtiS_nowReq$EN;
// register cap0_wtiS_operateD
reg cap0_wtiS_operateD;
wire cap0_wtiS_operateD$D_IN, cap0_wtiS_operateD$EN;
// register freeCnt
reg [31 : 0] freeCnt;
wire [31 : 0] freeCnt$D_IN;
wire freeCnt$EN;
// register needs_init
reg needs_init;
wire needs_init$D_IN, needs_init$EN;
// register pciDevice
reg [15 : 0] pciDevice;
wire [15 : 0] pciDevice$D_IN;
wire pciDevice$EN;
// register pciw_pciDevice
reg [15 : 0] pciw_pciDevice;
wire [15 : 0] pciw_pciDevice$D_IN;
wire pciw_pciDevice$EN;
// ports of submodule cap0_dataBram_memory
wire [31 : 0] cap0_dataBram_memory$DIA,
cap0_dataBram_memory$DIB,
cap0_dataBram_memory$DOA,
cap0_dataBram_memory$DOB;
wire [9 : 0] cap0_dataBram_memory$ADDRA, cap0_dataBram_memory$ADDRB;
wire cap0_dataBram_memory$ENA,
cap0_dataBram_memory$ENB,
cap0_dataBram_memory$WEA,
cap0_dataBram_memory$WEB;
// ports of submodule cap0_dataBram_serverAdapterA_outDataCore
wire [31 : 0] cap0_dataBram_serverAdapterA_outDataCore$D_IN,
cap0_dataBram_serverAdapterA_outDataCore$D_OUT;
wire cap0_dataBram_serverAdapterA_outDataCore$CLR,
cap0_dataBram_serverAdapterA_outDataCore$DEQ,
cap0_dataBram_serverAdapterA_outDataCore$EMPTY_N,
cap0_dataBram_serverAdapterA_outDataCore$ENQ,
cap0_dataBram_serverAdapterA_outDataCore$FULL_N;
// ports of submodule cap0_dataBram_serverAdapterB_outDataCore
wire [31 : 0] cap0_dataBram_serverAdapterB_outDataCore$D_IN,
cap0_dataBram_serverAdapterB_outDataCore$D_OUT;
wire cap0_dataBram_serverAdapterB_outDataCore$CLR,
cap0_dataBram_serverAdapterB_outDataCore$DEQ,
cap0_dataBram_serverAdapterB_outDataCore$EMPTY_N,
cap0_dataBram_serverAdapterB_outDataCore$ENQ,
cap0_dataBram_serverAdapterB_outDataCore$FULL_N;
// ports of submodule cap0_metaBram_memory
wire [31 : 0] cap0_metaBram_memory$DIA,
cap0_metaBram_memory$DIB,
cap0_metaBram_memory$DOA,
cap0_metaBram_memory$DOB;
wire [9 : 0] cap0_metaBram_memory$ADDRA, cap0_metaBram_memory$ADDRB;
wire cap0_metaBram_memory$ENA,
cap0_metaBram_memory$ENB,
cap0_metaBram_memory$WEA,
cap0_metaBram_memory$WEB;
// ports of submodule cap0_metaBram_memory_1
wire [31 : 0] cap0_metaBram_memory_1$DIA,
cap0_metaBram_memory_1$DIB,
cap0_metaBram_memory_1$DOA,
cap0_metaBram_memory_1$DOB;
wire [9 : 0] cap0_metaBram_memory_1$ADDRA, cap0_metaBram_memory_1$ADDRB;
wire cap0_metaBram_memory_1$ENA,
cap0_metaBram_memory_1$ENB,
cap0_metaBram_memory_1$WEA,
cap0_metaBram_memory_1$WEB;
// ports of submodule cap0_metaBram_memory_2
wire [31 : 0] cap0_metaBram_memory_2$DIA,
cap0_metaBram_memory_2$DIB,
cap0_metaBram_memory_2$DOA,
cap0_metaBram_memory_2$DOB;
wire [9 : 0] cap0_metaBram_memory_2$ADDRA, cap0_metaBram_memory_2$ADDRB;
wire cap0_metaBram_memory_2$ENA,
cap0_metaBram_memory_2$ENB,
cap0_metaBram_memory_2$WEA,
cap0_metaBram_memory_2$WEB;
// ports of submodule cap0_metaBram_memory_3
wire [31 : 0] cap0_metaBram_memory_3$DIA,
cap0_metaBram_memory_3$DIB,
cap0_metaBram_memory_3$DOA,
cap0_metaBram_memory_3$DOB;
wire [9 : 0] cap0_metaBram_memory_3$ADDRA, cap0_metaBram_memory_3$ADDRB;
wire cap0_metaBram_memory_3$ENA,
cap0_metaBram_memory_3$ENB,
cap0_metaBram_memory_3$WEA,
cap0_metaBram_memory_3$WEB;
// ports of submodule cap0_metaBram_serverAdapterA_1_outDataCore
wire [31 : 0] cap0_metaBram_serverAdapterA_1_outDataCore$D_IN,
cap0_metaBram_serverAdapterA_1_outDataCore$D_OUT;
wire cap0_metaBram_serverAdapterA_1_outDataCore$CLR,
cap0_metaBram_serverAdapterA_1_outDataCore$DEQ,
cap0_metaBram_serverAdapterA_1_outDataCore$EMPTY_N,
cap0_metaBram_serverAdapterA_1_outDataCore$ENQ,
cap0_metaBram_serverAdapterA_1_outDataCore$FULL_N;
// ports of submodule cap0_metaBram_serverAdapterA_2_outDataCore
wire [31 : 0] cap0_metaBram_serverAdapterA_2_outDataCore$D_IN,
cap0_metaBram_serverAdapterA_2_outDataCore$D_OUT;
wire cap0_metaBram_serverAdapterA_2_outDataCore$CLR,
cap0_metaBram_serverAdapterA_2_outDataCore$DEQ,
cap0_metaBram_serverAdapterA_2_outDataCore$EMPTY_N,
cap0_metaBram_serverAdapterA_2_outDataCore$ENQ,
cap0_metaBram_serverAdapterA_2_outDataCore$FULL_N;
// ports of submodule cap0_metaBram_serverAdapterA_3_outDataCore
wire [31 : 0] cap0_metaBram_serverAdapterA_3_outDataCore$D_IN,
cap0_metaBram_serverAdapterA_3_outDataCore$D_OUT;
wire cap0_metaBram_serverAdapterA_3_outDataCore$CLR,
cap0_metaBram_serverAdapterA_3_outDataCore$DEQ,
cap0_metaBram_serverAdapterA_3_outDataCore$EMPTY_N,
cap0_metaBram_serverAdapterA_3_outDataCore$ENQ,
cap0_metaBram_serverAdapterA_3_outDataCore$FULL_N;
// ports of submodule cap0_metaBram_serverAdapterA_outDataCore
wire [31 : 0] cap0_metaBram_serverAdapterA_outDataCore$D_IN,
cap0_metaBram_serverAdapterA_outDataCore$D_OUT;
wire cap0_metaBram_serverAdapterA_outDataCore$CLR,
cap0_metaBram_serverAdapterA_outDataCore$DEQ,
cap0_metaBram_serverAdapterA_outDataCore$EMPTY_N,
cap0_metaBram_serverAdapterA_outDataCore$ENQ,
cap0_metaBram_serverAdapterA_outDataCore$FULL_N;
// ports of submodule cap0_metaBram_serverAdapterB_1_outDataCore
wire [31 : 0] cap0_metaBram_serverAdapterB_1_outDataCore$D_IN,
cap0_metaBram_serverAdapterB_1_outDataCore$D_OUT;
wire cap0_metaBram_serverAdapterB_1_outDataCore$CLR,
cap0_metaBram_serverAdapterB_1_outDataCore$DEQ,
cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N,
cap0_metaBram_serverAdapterB_1_outDataCore$ENQ,
cap0_metaBram_serverAdapterB_1_outDataCore$FULL_N;
// ports of submodule cap0_metaBram_serverAdapterB_2_outDataCore
wire [31 : 0] cap0_metaBram_serverAdapterB_2_outDataCore$D_IN,
cap0_metaBram_serverAdapterB_2_outDataCore$D_OUT;
wire cap0_metaBram_serverAdapterB_2_outDataCore$CLR,
cap0_metaBram_serverAdapterB_2_outDataCore$DEQ,
cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N,
cap0_metaBram_serverAdapterB_2_outDataCore$ENQ,
cap0_metaBram_serverAdapterB_2_outDataCore$FULL_N;
// ports of submodule cap0_metaBram_serverAdapterB_3_outDataCore
wire [31 : 0] cap0_metaBram_serverAdapterB_3_outDataCore$D_IN,
cap0_metaBram_serverAdapterB_3_outDataCore$D_OUT;
wire cap0_metaBram_serverAdapterB_3_outDataCore$CLR,
cap0_metaBram_serverAdapterB_3_outDataCore$DEQ,
cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N,
cap0_metaBram_serverAdapterB_3_outDataCore$ENQ,
cap0_metaBram_serverAdapterB_3_outDataCore$FULL_N;
// ports of submodule cap0_metaBram_serverAdapterB_outDataCore
wire [31 : 0] cap0_metaBram_serverAdapterB_outDataCore$D_IN,
cap0_metaBram_serverAdapterB_outDataCore$D_OUT;
wire cap0_metaBram_serverAdapterB_outDataCore$CLR,
cap0_metaBram_serverAdapterB_outDataCore$DEQ,
cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N,
cap0_metaBram_serverAdapterB_outDataCore$ENQ,
cap0_metaBram_serverAdapterB_outDataCore$FULL_N;
// ports of submodule cap0_splaF
wire [2 : 0] cap0_splaF$D_IN, cap0_splaF$D_OUT;
wire cap0_splaF$CLR,
cap0_splaF$DEQ,
cap0_splaF$EMPTY_N,
cap0_splaF$ENQ,
cap0_splaF$FULL_N;
// ports of submodule cap0_wci_wslv_reqF
wire [71 : 0] cap0_wci_wslv_reqF$D_IN, cap0_wci_wslv_reqF$D_OUT;
wire cap0_wci_wslv_reqF$CLR,
cap0_wci_wslv_reqF$DEQ,
cap0_wci_wslv_reqF$EMPTY_N,
cap0_wci_wslv_reqF$ENQ;
// ports of submodule cap0_wsiS_reqFifo
wire [60 : 0] cap0_wsiS_reqFifo$D_IN, cap0_wsiS_reqFifo$D_OUT;
wire cap0_wsiS_reqFifo$CLR,
cap0_wsiS_reqFifo$DEQ,
cap0_wsiS_reqFifo$EMPTY_N,
cap0_wsiS_reqFifo$ENQ,
cap0_wsiS_reqFifo$FULL_N;
// ports of submodule ctop
wire [152 : 0] ctop$server_request_put, ctop$server_response_get;
wire [127 : 0] ctop$wmemiM0_SData;
wire [58 : 0] ctop$cpServer_request_put;
wire [31 : 0] ctop$wci_m_0_SData,
ctop$wci_m_1_SData,
ctop$wci_m_2_MAddr,
ctop$wci_m_2_MData,
ctop$wci_m_2_SData,
ctop$wci_m_3_MAddr,
ctop$wci_m_3_MData,
ctop$wci_m_3_SData,
ctop$wci_m_4_SData,
ctop$wsi_s_adc_MData;
wire [11 : 0] ctop$wsi_s_adc_MBurstLength;
wire [7 : 0] ctop$wsi_s_adc_MReqInfo;
wire [3 : 0] ctop$wci_m_2_MByteEn,
ctop$wci_m_3_MByteEn,
ctop$wsi_s_adc_MByteEn;
wire [2 : 0] ctop$switch_x,
ctop$wci_m_2_MCmd,
ctop$wci_m_3_MCmd,
ctop$wsi_s_adc_MCmd;
wire [1 : 0] ctop$led,
ctop$wci_m_0_SFlag,
ctop$wci_m_0_SResp,
ctop$wci_m_1_SFlag,
ctop$wci_m_1_SResp,
ctop$wci_m_2_MFlag,
ctop$wci_m_2_SFlag,
ctop$wci_m_2_SResp,
ctop$wci_m_3_SFlag,
ctop$wci_m_3_SResp,
ctop$wci_m_4_SFlag,
ctop$wci_m_4_SResp,
ctop$wmemiM0_SResp;
wire ctop$EN_cpServer_request_put,
ctop$EN_cpServer_response_get,
ctop$EN_server_request_put,
ctop$EN_server_response_get,
ctop$RDY_server_request_put,
ctop$RDY_server_response_get,
ctop$RST_N_wci_m_2,
ctop$RST_N_wci_m_3,
ctop$gps_ppsSyncIn_x,
ctop$wci_m_0_SThreadBusy,
ctop$wci_m_1_SThreadBusy,
ctop$wci_m_2_MAddrSpace,
ctop$wci_m_2_SThreadBusy,
ctop$wci_m_3_MAddrSpace,
ctop$wci_m_3_SThreadBusy,
ctop$wci_m_4_SThreadBusy,
ctop$wmemiM0_SCmdAccept,
ctop$wmemiM0_SDataAccept,
ctop$wmemiM0_SRespLast,
ctop$wsi_m_dac_SReset_n,
ctop$wsi_m_dac_SThreadBusy,
ctop$wsi_s_adc_MBurstPrecise,
ctop$wsi_s_adc_MReqLast,
ctop$wsi_s_adc_MReset_n;
// ports of submodule gbe0
wire [66 : 0] gbe0$wtiS0_req;
wire [39 : 0] gbe0$cpClient_response_put;
wire [31 : 0] gbe0$wciS0_MAddr,
gbe0$wciS0_MData,
gbe0$wciS0_SData,
gbe0$wsiM0_MData,
gbe0$wsiS0_MData;
wire [11 : 0] gbe0$wsiM0_MBurstLength, gbe0$wsiS0_MBurstLength;
wire [7 : 0] gbe0$gmii_rx_rxd_i,
gbe0$gmii_tx_txd,
gbe0$wsiM0_MReqInfo,
gbe0$wsiS0_MReqInfo;
wire [3 : 0] gbe0$wciS0_MByteEn, gbe0$wsiM0_MByteEn, gbe0$wsiS0_MByteEn;
wire [2 : 0] gbe0$wciS0_MCmd, gbe0$wsiM0_MCmd, gbe0$wsiS0_MCmd;
wire [1 : 0] gbe0$wciS0_MFlag, gbe0$wciS0_SFlag, gbe0$wciS0_SResp;
wire gbe0$CLK_gmii_tx_tx_clk,
gbe0$CLK_rxclkBnd,
gbe0$EN_cpClient_request_get,
gbe0$EN_cpClient_response_put,
gbe0$RST_N_gmii_rstn,
gbe0$gmii_col_i,
gbe0$gmii_crs_i,
gbe0$gmii_intr_i,
gbe0$gmii_led,
gbe0$gmii_rx_rx_dv_i,
gbe0$gmii_rx_rx_er_i,
gbe0$gmii_tx_tx_en,
gbe0$gmii_tx_tx_er,
gbe0$mdio_mdc,
gbe0$mdio_mdd,
gbe0$wciS0_MAddrSpace,
gbe0$wciS0_SThreadBusy,
gbe0$wsiM0_MBurstPrecise,
gbe0$wsiM0_MReqLast,
gbe0$wsiM0_MReset_n,
gbe0$wsiM0_SReset_n,
gbe0$wsiM0_SThreadBusy,
gbe0$wsiS0_MBurstPrecise,
gbe0$wsiS0_MReqLast,
gbe0$wsiS0_MReset_n;
// ports of submodule idc_resetP
wire idc_resetP$RESET_OUT;
// ports of submodule lcd_ctrl
wire [127 : 0] lcd_ctrl$setLine1_text, lcd_ctrl$setLine2_text;
wire [3 : 0] lcd_ctrl$db;
wire lcd_ctrl$EN_setLine1,
lcd_ctrl$EN_setLine2,
lcd_ctrl$e,
lcd_ctrl$rs,
lcd_ctrl$rw;
// ports of submodule pciw_fI2P
wire [152 : 0] pciw_fI2P$D_IN, pciw_fI2P$D_OUT;
wire pciw_fI2P$CLR,
pciw_fI2P$DEQ,
pciw_fI2P$EMPTY_N,
pciw_fI2P$ENQ,
pciw_fI2P$FULL_N;
// ports of submodule pciw_fP2I
wire [152 : 0] pciw_fP2I$D_IN, pciw_fP2I$D_OUT;
wire pciw_fP2I$CLR,
pciw_fP2I$DEQ,
pciw_fP2I$EMPTY_N,
pciw_fP2I$ENQ,
pciw_fP2I$FULL_N;
// ports of submodule pciw_p125rst
wire pciw_p125rst$OUT_RST;
// ports of submodule pciw_pci0_axiRst125
wire pciw_pci0_axiRst125$OUT_RST;
// ports of submodule pciw_pci0_clk
wire pciw_pci0_clk$O;
// ports of submodule pciw_pci0_pcie_ep
wire [127 : 0] pciw_pci0_pcie_ep$cfg_err_aer_headerlog,
pciw_pci0_pcie_ep$m_axis_rx_tdata,
pciw_pci0_pcie_ep$s_axis_tx_tdata;
wire [63 : 0] pciw_pci0_pcie_ep$cfg_dsn;
wire [47 : 0] pciw_pci0_pcie_ep$cfg_err_tlp_cpl_header;
wire [31 : 0] pciw_pci0_pcie_ep$cfg_mgmt_di;
wire [21 : 0] pciw_pci0_pcie_ep$m_axis_rx_tuser;
wire [15 : 0] pciw_pci0_pcie_ep$s_axis_tx_tkeep;
wire [9 : 0] pciw_pci0_pcie_ep$cfg_mgmt_dwaddr;
wire [7 : 0] pciw_pci0_pcie_ep$cfg_bus_number,
pciw_pci0_pcie_ep$cfg_interrupt_di;
wire [4 : 0] pciw_pci0_pcie_ep$cfg_device_number,
pciw_pci0_pcie_ep$cfg_pciecap_interrupt_msgnum;
wire [3 : 0] pciw_pci0_pcie_ep$PIPE_RXUSRCLK_IN,
pciw_pci0_pcie_ep$cfg_mgmt_byte_en,
pciw_pci0_pcie_ep$pci_exp_rxn,
pciw_pci0_pcie_ep$pci_exp_rxp,
pciw_pci0_pcie_ep$pci_exp_txn,
pciw_pci0_pcie_ep$pci_exp_txp,
pciw_pci0_pcie_ep$s_axis_tx_tuser;
wire [2 : 0] pciw_pci0_pcie_ep$cfg_function_number,
pciw_pci0_pcie_ep$fc_sel;
wire [1 : 0] pciw_pci0_pcie_ep$cfg_pm_force_state,
pciw_pci0_pcie_ep$pl_directed_link_change,
pciw_pci0_pcie_ep$pl_directed_link_width;
wire pciw_pci0_pcie_ep$PIPE_DCLK_IN,
pciw_pci0_pcie_ep$PIPE_MMCM_LOCK_IN,
pciw_pci0_pcie_ep$PIPE_OOBCLK_IN,
pciw_pci0_pcie_ep$PIPE_PCLK_IN,
pciw_pci0_pcie_ep$PIPE_RXOUTCLK_IN,
pciw_pci0_pcie_ep$PIPE_USERCLK1_IN,
pciw_pci0_pcie_ep$PIPE_USERCLK2_IN,
pciw_pci0_pcie_ep$cfg_err_acs,
pciw_pci0_pcie_ep$cfg_err_atomic_egress_blocked,
pciw_pci0_pcie_ep$cfg_err_cor,
pciw_pci0_pcie_ep$cfg_err_cpl_abort,
pciw_pci0_pcie_ep$cfg_err_cpl_timeout,
pciw_pci0_pcie_ep$cfg_err_cpl_unexpect,
pciw_pci0_pcie_ep$cfg_err_ecrc,
pciw_pci0_pcie_ep$cfg_err_internal_cor,
pciw_pci0_pcie_ep$cfg_err_internal_uncor,
pciw_pci0_pcie_ep$cfg_err_locked,
pciw_pci0_pcie_ep$cfg_err_malformed,
pciw_pci0_pcie_ep$cfg_err_mc_blocked,
pciw_pci0_pcie_ep$cfg_err_norecovery,
pciw_pci0_pcie_ep$cfg_err_poisoned,
pciw_pci0_pcie_ep$cfg_err_posted,
pciw_pci0_pcie_ep$cfg_err_ur,
pciw_pci0_pcie_ep$cfg_interrupt,
pciw_pci0_pcie_ep$cfg_interrupt_assert,
pciw_pci0_pcie_ep$cfg_interrupt_stat,
pciw_pci0_pcie_ep$cfg_mgmt_rd_en,
pciw_pci0_pcie_ep$cfg_mgmt_wr_en,
pciw_pci0_pcie_ep$cfg_mgmt_wr_readonly,
pciw_pci0_pcie_ep$cfg_pm_force_state_en,
pciw_pci0_pcie_ep$cfg_pm_halt_aspm_l0s,
pciw_pci0_pcie_ep$cfg_pm_halt_aspm_l1,
pciw_pci0_pcie_ep$cfg_pm_wake,
pciw_pci0_pcie_ep$cfg_trn_pending,
pciw_pci0_pcie_ep$cfg_turnoff_ok,
pciw_pci0_pcie_ep$m_axis_rx_tready,
pciw_pci0_pcie_ep$m_axis_rx_tvalid,
pciw_pci0_pcie_ep$pl_directed_link_auton,
pciw_pci0_pcie_ep$pl_directed_link_speed,
pciw_pci0_pcie_ep$pl_upstream_prefer_deemph,
pciw_pci0_pcie_ep$rx_np_ok,
pciw_pci0_pcie_ep$rx_np_req,
pciw_pci0_pcie_ep$s_axis_tx_tlast,
pciw_pci0_pcie_ep$s_axis_tx_tready,
pciw_pci0_pcie_ep$s_axis_tx_tvalid,
pciw_pci0_pcie_ep$tx_cfg_gnt,
pciw_pci0_pcie_ep$user_clk_out,
pciw_pci0_pcie_ep$user_lnk_up,
pciw_pci0_pcie_ep$user_reset_out;
// ports of submodule pciw_pci0_pcie_ep_reset
wire pciw_pci0_pcie_ep_reset$RESET_OUT;
// ports of submodule pciw_pci0_rxF
wire [152 : 0] pciw_pci0_rxF$D_IN, pciw_pci0_rxF$D_OUT;
wire pciw_pci0_rxF$CLR,
pciw_pci0_rxF$DEQ,
pciw_pci0_rxF$EMPTY_N,
pciw_pci0_rxF$ENQ,
pciw_pci0_rxF$FULL_N;
// ports of submodule pciw_pci0_txF
wire [152 : 0] pciw_pci0_txF$D_IN, pciw_pci0_txF$D_OUT;
wire pciw_pci0_txF$CLR,
pciw_pci0_txF$DEQ,
pciw_pci0_txF$EMPTY_N,
pciw_pci0_txF$ENQ,
pciw_pci0_txF$FULL_N;
// ports of submodule pciw_pci0_usr_rst_n
wire pciw_pci0_usr_rst_n$RESET_OUT;
// ports of submodule sys0_clk
wire sys0_clk$O;
// ports of submodule sys0_rst
wire sys0_rst$OUT_RST;
// ports of submodule sys1_clk
wire sys1_clk$O;
// ports of submodule sys1_clki
wire sys1_clki$O;
// ports of submodule sys1_rst
wire sys1_rst$OUT_RST;
// rule scheduling signals
wire CAN_FIRE_RL_cap0_wci_cfrd,
WILL_FIRE_RL_cap0_advance_split_response,
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_cap0_doMessageAccept,
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_outData_enqAndDeq,
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways,
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_outData_enqAndDeq,
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways,
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_outData_enqAndDeq,
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways,
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_cap0_wci_cfrd,
WILL_FIRE_RL_cap0_wci_cfwr,
WILL_FIRE_RL_cap0_wci_ctrl_EiI,
WILL_FIRE_RL_cap0_wci_ctrl_IsO,
WILL_FIRE_RL_cap0_wci_ctrl_OrE,
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start,
WILL_FIRE_RL_cap0_wci_wslv_respF_both,
WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr,
WILL_FIRE_RL_cap0_wci_wslv_respF_incCtr,
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq,
WILL_FIRE_RL_cap0_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2;
wire [33 : 0] MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_1,
MUX_cap0_wci_wslv_respF_q_1$write_1__VAL_1,
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_1,
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_2,
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_3;
wire [31 : 0] MUX_cap0_dataCount$write_1__VAL_2,
MUX_cap0_metaCount$write_1__VAL_2;
wire [1 : 0] MUX_cap0_wci_wslv_respF_c_r$write_1__VAL_1,
MUX_cap0_wci_wslv_respF_c_r$write_1__VAL_2;
wire MUX_cap0_controlReg$write_1__SEL_1,
MUX_cap0_dataCount$write_1__SEL_1,
MUX_cap0_dataCount$write_1__SEL_2,
MUX_cap0_metaCount$write_1__SEL_1,
MUX_cap0_metaCount$write_1__SEL_2,
MUX_cap0_splitReadInFlight$write_1__SEL_1,
MUX_cap0_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_cap0_wci_wslv_illegalEdge$write_1__SEL_2,
MUX_cap0_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_cap0_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_cap0_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_cap0_wci_wslv_respF_x_wire$wset_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h14804,
v__h14979,
v__h15123,
v__h36538,
v__h37583,
v__h37878,
v__h38083;
reg [31 : 0] IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1081,
v__h38064;
reg [15 : 0] CASE_pciw_pci0_pcie_epm_axis_rx_tuser_BITS_20_ETC__q1;
reg CASE_cap0_splaFD_OUT_BITS_1_TO_0_NOT_cap0_spl_ETC__q2,
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1048,
IF_cap0_wci_wslv_reqF_first__75_BITS_35_TO_34__ETC___d1124,
IF_cap0_wci_wslv_reqF_first__75_BITS_63_TO_52__ETC___d1128;
wire [127 : 0] x_data__h1483;
wire [31 : 0] g_data__h39139,
rdat___1__h38161,
rdat___1__h38235,
v__h36664,
y_avValue__h37291,
y_avValue__h37335,
y_avValue__h37375,
y_avValue__h37415,
y_avValue__h37455;
wire [15 : 0] IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291,
x_be__h1482;
wire [13 : 0] mlB__h34434, mlInc__h34433;
wire [2 : 0] cap0_dataBram_serverAdapterB_cnt_51_PLUS_IF_ca_ETC___d457,
cap0_metaBram_serverAdapterB_1_cnt_87_PLUS_IF__ETC___d693,
cap0_metaBram_serverAdapterB_2_cnt_05_PLUS_IF__ETC___d811,
cap0_metaBram_serverAdapterB_3_cnt_23_PLUS_IF__ETC___d929,
cap0_metaBram_serverAdapterB_cnt_69_PLUS_IF_ca_ETC___d575,
x__h34482,
x__h34494,
x__h34506,
y__h34483,
y__h34495,
y__h34507;
wire IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1057,
NOT_cap0_controlReg_60_BIT_0_61_62_OR_cap0_con_ETC___d986,
cap0_controlReg_60_BIT_0_61_AND_NOT_cap0_contr_ETC___d1008,
cap0_dataCount_67_ULT_1024___d1378,
cap0_metaCount_64_ULT_1024___d1257,
cap0_splaF_i_notEmpty__026_AND_IF_cap0_splaF_f_ETC___d1059;
// oscillator and gates for output clock p125clk
assign p125clk = pciw_pci0_pcie_ep$user_clk_out ;
assign CLK_GATE_p125clk = 1'b1 ;
// oscillator and gates for output clock rxclk
assign rxclk = gbe0$CLK_rxclkBnd ;
assign CLK_GATE_rxclk = 1'b1 ;
// oscillator and gates for output clock gmii_tx_tx_clk
assign gmii_tx_tx_clk = gbe0$CLK_gmii_tx_tx_clk ;
assign CLK_GATE_gmii_tx_tx_clk = 1'b1 ;
// output resets
assign p125rst = pciw_p125rst$OUT_RST ;
assign gmii_rstn = gbe0$RST_N_gmii_rstn ;
// value method pcie_txp
assign pcie_txp = pciw_pci0_pcie_ep$pci_exp_txp ;
// value method pcie_txn
assign pcie_txn = pciw_pci0_pcie_ep$pci_exp_txn ;
// action method usr_sw
assign RDY_usr_sw = 1'd1 ;
// value method led
assign led =
{ freeCnt[25], 4'b0, ctop$led, pciw_pci0_pcie_ep$user_lnk_up } ;
// value method lcd_db
assign lcd_db = lcd_ctrl$db ;
// value method lcd_e
assign lcd_e = lcd_ctrl$e ;
// value method lcd_rs
assign lcd_rs = lcd_ctrl$rs ;
// value method lcd_rw
assign lcd_rw = lcd_ctrl$rw ;
// value method debug
assign debug = freeCnt[31:16] ;
assign RDY_debug = 1'd1 ;
// value method gmii_tx_txd
assign gmii_tx_txd = gbe0$gmii_tx_txd ;
// value method gmii_tx_tx_en
assign gmii_tx_tx_en = gbe0$gmii_tx_tx_en ;
// value method gmii_tx_tx_er
assign gmii_tx_tx_er = gbe0$gmii_tx_tx_er ;
// value method gmii_led
assign gmii_led = gbe0$gmii_led ;
// submodule cap0_dataBram_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) cap0_dataBram_memory(.CLKA(pciw_pci0_pcie_ep$user_clk_out),
.CLKB(pciw_pci0_pcie_ep$user_clk_out),
.ADDRA(cap0_dataBram_memory$ADDRA),
.ADDRB(cap0_dataBram_memory$ADDRB),
.DIA(cap0_dataBram_memory$DIA),
.DIB(cap0_dataBram_memory$DIB),
.WEA(cap0_dataBram_memory$WEA),
.WEB(cap0_dataBram_memory$WEB),
.ENA(cap0_dataBram_memory$ENA),
.ENB(cap0_dataBram_memory$ENB),
.DOA(cap0_dataBram_memory$DOA),
.DOB(cap0_dataBram_memory$DOB));
// submodule cap0_dataBram_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_dataBram_serverAdapterA_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_dataBram_serverAdapterA_outDataCore$D_IN),
.ENQ(cap0_dataBram_serverAdapterA_outDataCore$ENQ),
.DEQ(cap0_dataBram_serverAdapterA_outDataCore$DEQ),
.CLR(cap0_dataBram_serverAdapterA_outDataCore$CLR),
.D_OUT(cap0_dataBram_serverAdapterA_outDataCore$D_OUT),
.FULL_N(cap0_dataBram_serverAdapterA_outDataCore$FULL_N),
.EMPTY_N(cap0_dataBram_serverAdapterA_outDataCore$EMPTY_N));
// submodule cap0_dataBram_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_dataBram_serverAdapterB_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_dataBram_serverAdapterB_outDataCore$D_IN),
.ENQ(cap0_dataBram_serverAdapterB_outDataCore$ENQ),
.DEQ(cap0_dataBram_serverAdapterB_outDataCore$DEQ),
.CLR(cap0_dataBram_serverAdapterB_outDataCore$CLR),
.D_OUT(cap0_dataBram_serverAdapterB_outDataCore$D_OUT),
.FULL_N(cap0_dataBram_serverAdapterB_outDataCore$FULL_N),
.EMPTY_N(cap0_dataBram_serverAdapterB_outDataCore$EMPTY_N));
// submodule cap0_metaBram_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) cap0_metaBram_memory(.CLKA(pciw_pci0_pcie_ep$user_clk_out),
.CLKB(pciw_pci0_pcie_ep$user_clk_out),
.ADDRA(cap0_metaBram_memory$ADDRA),
.ADDRB(cap0_metaBram_memory$ADDRB),
.DIA(cap0_metaBram_memory$DIA),
.DIB(cap0_metaBram_memory$DIB),
.WEA(cap0_metaBram_memory$WEA),
.WEB(cap0_metaBram_memory$WEB),
.ENA(cap0_metaBram_memory$ENA),
.ENB(cap0_metaBram_memory$ENB),
.DOA(cap0_metaBram_memory$DOA),
.DOB(cap0_metaBram_memory$DOB));
// submodule cap0_metaBram_memory_1
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) cap0_metaBram_memory_1(.CLKA(pciw_pci0_pcie_ep$user_clk_out),
.CLKB(pciw_pci0_pcie_ep$user_clk_out),
.ADDRA(cap0_metaBram_memory_1$ADDRA),
.ADDRB(cap0_metaBram_memory_1$ADDRB),
.DIA(cap0_metaBram_memory_1$DIA),
.DIB(cap0_metaBram_memory_1$DIB),
.WEA(cap0_metaBram_memory_1$WEA),
.WEB(cap0_metaBram_memory_1$WEB),
.ENA(cap0_metaBram_memory_1$ENA),
.ENB(cap0_metaBram_memory_1$ENB),
.DOA(cap0_metaBram_memory_1$DOA),
.DOB(cap0_metaBram_memory_1$DOB));
// submodule cap0_metaBram_memory_2
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) cap0_metaBram_memory_2(.CLKA(pciw_pci0_pcie_ep$user_clk_out),
.CLKB(pciw_pci0_pcie_ep$user_clk_out),
.ADDRA(cap0_metaBram_memory_2$ADDRA),
.ADDRB(cap0_metaBram_memory_2$ADDRB),
.DIA(cap0_metaBram_memory_2$DIA),
.DIB(cap0_metaBram_memory_2$DIB),
.WEA(cap0_metaBram_memory_2$WEA),
.WEB(cap0_metaBram_memory_2$WEB),
.ENA(cap0_metaBram_memory_2$ENA),
.ENB(cap0_metaBram_memory_2$ENB),
.DOA(cap0_metaBram_memory_2$DOA),
.DOB(cap0_metaBram_memory_2$DOB));
// submodule cap0_metaBram_memory_3
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) cap0_metaBram_memory_3(.CLKA(pciw_pci0_pcie_ep$user_clk_out),
.CLKB(pciw_pci0_pcie_ep$user_clk_out),
.ADDRA(cap0_metaBram_memory_3$ADDRA),
.ADDRB(cap0_metaBram_memory_3$ADDRB),
.DIA(cap0_metaBram_memory_3$DIA),
.DIB(cap0_metaBram_memory_3$DIB),
.WEA(cap0_metaBram_memory_3$WEA),
.WEB(cap0_metaBram_memory_3$WEB),
.ENA(cap0_metaBram_memory_3$ENA),
.ENB(cap0_metaBram_memory_3$ENB),
.DOA(cap0_metaBram_memory_3$DOA),
.DOB(cap0_metaBram_memory_3$DOB));
// submodule cap0_metaBram_serverAdapterA_1_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_metaBram_serverAdapterA_1_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_metaBram_serverAdapterA_1_outDataCore$D_IN),
.ENQ(cap0_metaBram_serverAdapterA_1_outDataCore$ENQ),
.DEQ(cap0_metaBram_serverAdapterA_1_outDataCore$DEQ),
.CLR(cap0_metaBram_serverAdapterA_1_outDataCore$CLR),
.D_OUT(cap0_metaBram_serverAdapterA_1_outDataCore$D_OUT),
.FULL_N(cap0_metaBram_serverAdapterA_1_outDataCore$FULL_N),
.EMPTY_N(cap0_metaBram_serverAdapterA_1_outDataCore$EMPTY_N));
// submodule cap0_metaBram_serverAdapterA_2_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_metaBram_serverAdapterA_2_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_metaBram_serverAdapterA_2_outDataCore$D_IN),
.ENQ(cap0_metaBram_serverAdapterA_2_outDataCore$ENQ),
.DEQ(cap0_metaBram_serverAdapterA_2_outDataCore$DEQ),
.CLR(cap0_metaBram_serverAdapterA_2_outDataCore$CLR),
.D_OUT(cap0_metaBram_serverAdapterA_2_outDataCore$D_OUT),
.FULL_N(cap0_metaBram_serverAdapterA_2_outDataCore$FULL_N),
.EMPTY_N(cap0_metaBram_serverAdapterA_2_outDataCore$EMPTY_N));
// submodule cap0_metaBram_serverAdapterA_3_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_metaBram_serverAdapterA_3_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_metaBram_serverAdapterA_3_outDataCore$D_IN),
.ENQ(cap0_metaBram_serverAdapterA_3_outDataCore$ENQ),
.DEQ(cap0_metaBram_serverAdapterA_3_outDataCore$DEQ),
.CLR(cap0_metaBram_serverAdapterA_3_outDataCore$CLR),
.D_OUT(cap0_metaBram_serverAdapterA_3_outDataCore$D_OUT),
.FULL_N(cap0_metaBram_serverAdapterA_3_outDataCore$FULL_N),
.EMPTY_N(cap0_metaBram_serverAdapterA_3_outDataCore$EMPTY_N));
// submodule cap0_metaBram_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_metaBram_serverAdapterA_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_metaBram_serverAdapterA_outDataCore$D_IN),
.ENQ(cap0_metaBram_serverAdapterA_outDataCore$ENQ),
.DEQ(cap0_metaBram_serverAdapterA_outDataCore$DEQ),
.CLR(cap0_metaBram_serverAdapterA_outDataCore$CLR),
.D_OUT(cap0_metaBram_serverAdapterA_outDataCore$D_OUT),
.FULL_N(cap0_metaBram_serverAdapterA_outDataCore$FULL_N),
.EMPTY_N(cap0_metaBram_serverAdapterA_outDataCore$EMPTY_N));
// submodule cap0_metaBram_serverAdapterB_1_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_metaBram_serverAdapterB_1_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_metaBram_serverAdapterB_1_outDataCore$D_IN),
.ENQ(cap0_metaBram_serverAdapterB_1_outDataCore$ENQ),
.DEQ(cap0_metaBram_serverAdapterB_1_outDataCore$DEQ),
.CLR(cap0_metaBram_serverAdapterB_1_outDataCore$CLR),
.D_OUT(cap0_metaBram_serverAdapterB_1_outDataCore$D_OUT),
.FULL_N(cap0_metaBram_serverAdapterB_1_outDataCore$FULL_N),
.EMPTY_N(cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N));
// submodule cap0_metaBram_serverAdapterB_2_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_metaBram_serverAdapterB_2_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_metaBram_serverAdapterB_2_outDataCore$D_IN),
.ENQ(cap0_metaBram_serverAdapterB_2_outDataCore$ENQ),
.DEQ(cap0_metaBram_serverAdapterB_2_outDataCore$DEQ),
.CLR(cap0_metaBram_serverAdapterB_2_outDataCore$CLR),
.D_OUT(cap0_metaBram_serverAdapterB_2_outDataCore$D_OUT),
.FULL_N(cap0_metaBram_serverAdapterB_2_outDataCore$FULL_N),
.EMPTY_N(cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N));
// submodule cap0_metaBram_serverAdapterB_3_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_metaBram_serverAdapterB_3_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_metaBram_serverAdapterB_3_outDataCore$D_IN),
.ENQ(cap0_metaBram_serverAdapterB_3_outDataCore$ENQ),
.DEQ(cap0_metaBram_serverAdapterB_3_outDataCore$DEQ),
.CLR(cap0_metaBram_serverAdapterB_3_outDataCore$CLR),
.D_OUT(cap0_metaBram_serverAdapterB_3_outDataCore$D_OUT),
.FULL_N(cap0_metaBram_serverAdapterB_3_outDataCore$FULL_N),
.EMPTY_N(cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N));
// submodule cap0_metaBram_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_metaBram_serverAdapterB_outDataCore(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_metaBram_serverAdapterB_outDataCore$D_IN),
.ENQ(cap0_metaBram_serverAdapterB_outDataCore$ENQ),
.DEQ(cap0_metaBram_serverAdapterB_outDataCore$DEQ),
.CLR(cap0_metaBram_serverAdapterB_outDataCore$CLR),
.D_OUT(cap0_metaBram_serverAdapterB_outDataCore$D_OUT),
.FULL_N(cap0_metaBram_serverAdapterB_outDataCore$FULL_N),
.EMPTY_N(cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N));
// submodule cap0_splaF
FIFO2 #(.width(32'd3), .guarded(32'd1)) cap0_splaF(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_splaF$D_IN),
.ENQ(cap0_splaF$ENQ),
.DEQ(cap0_splaF$DEQ),
.CLR(cap0_splaF$CLR),
.D_OUT(cap0_splaF$D_OUT),
.FULL_N(cap0_splaF$FULL_N),
.EMPTY_N(cap0_splaF$EMPTY_N));
// submodule cap0_wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_wci_wslv_reqF(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_wci_wslv_reqF$D_IN),
.ENQ(cap0_wci_wslv_reqF$ENQ),
.DEQ(cap0_wci_wslv_reqF$DEQ),
.CLR(cap0_wci_wslv_reqF$CLR),
.D_OUT(cap0_wci_wslv_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(cap0_wci_wslv_reqF$EMPTY_N));
// submodule cap0_wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) cap0_wsiS_reqFifo(.RST(ctop$RST_N_wci_m_3),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(cap0_wsiS_reqFifo$D_IN),
.ENQ(cap0_wsiS_reqFifo$ENQ),
.DEQ(cap0_wsiS_reqFifo$DEQ),
.CLR(cap0_wsiS_reqFifo$CLR),
.D_OUT(cap0_wsiS_reqFifo$D_OUT),
.FULL_N(cap0_wsiS_reqFifo$FULL_N),
.EMPTY_N(cap0_wsiS_reqFifo$EMPTY_N));
// submodule ctop
mkCTop4B ctop(.pciDevice(pciDevice),
.CLK_sys0_clk(sys0_clk$O),
.RST_N_sys0_rst(sys0_rst$OUT_RST),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.RST_N(pciw_p125rst$OUT_RST),
.cpServer_request_put(ctop$cpServer_request_put),
.gps_ppsSyncIn_x(ctop$gps_ppsSyncIn_x),
.server_request_put(ctop$server_request_put),
.switch_x(ctop$switch_x),
.wci_m_0_SData(ctop$wci_m_0_SData),
.wci_m_0_SFlag(ctop$wci_m_0_SFlag),
.wci_m_0_SResp(ctop$wci_m_0_SResp),
.wci_m_1_SData(ctop$wci_m_1_SData),
.wci_m_1_SFlag(ctop$wci_m_1_SFlag),
.wci_m_1_SResp(ctop$wci_m_1_SResp),
.wci_m_2_SData(ctop$wci_m_2_SData),
.wci_m_2_SFlag(ctop$wci_m_2_SFlag),
.wci_m_2_SResp(ctop$wci_m_2_SResp),
.wci_m_3_SData(ctop$wci_m_3_SData),
.wci_m_3_SFlag(ctop$wci_m_3_SFlag),
.wci_m_3_SResp(ctop$wci_m_3_SResp),
.wci_m_4_SData(ctop$wci_m_4_SData),
.wci_m_4_SFlag(ctop$wci_m_4_SFlag),
.wci_m_4_SResp(ctop$wci_m_4_SResp),
.wmemiM0_SData(ctop$wmemiM0_SData),
.wmemiM0_SResp(ctop$wmemiM0_SResp),
.wsi_s_adc_MBurstLength(ctop$wsi_s_adc_MBurstLength),
.wsi_s_adc_MByteEn(ctop$wsi_s_adc_MByteEn),
.wsi_s_adc_MCmd(ctop$wsi_s_adc_MCmd),
.wsi_s_adc_MData(ctop$wsi_s_adc_MData),
.wsi_s_adc_MReqInfo(ctop$wsi_s_adc_MReqInfo),
.EN_server_request_put(ctop$EN_server_request_put),
.EN_server_response_get(ctop$EN_server_response_get),
.EN_cpServer_request_put(ctop$EN_cpServer_request_put),
.EN_cpServer_response_get(ctop$EN_cpServer_response_get),
.wci_m_0_SThreadBusy(ctop$wci_m_0_SThreadBusy),
.wci_m_1_SThreadBusy(ctop$wci_m_1_SThreadBusy),
.wci_m_2_SThreadBusy(ctop$wci_m_2_SThreadBusy),
.wci_m_3_SThreadBusy(ctop$wci_m_3_SThreadBusy),
.wci_m_4_SThreadBusy(ctop$wci_m_4_SThreadBusy),
.wsi_s_adc_MReqLast(ctop$wsi_s_adc_MReqLast),
.wsi_s_adc_MBurstPrecise(ctop$wsi_s_adc_MBurstPrecise),
.wsi_s_adc_MReset_n(ctop$wsi_s_adc_MReset_n),
.wsi_m_dac_SThreadBusy(ctop$wsi_m_dac_SThreadBusy),
.wsi_m_dac_SReset_n(ctop$wsi_m_dac_SReset_n),
.wmemiM0_SRespLast(ctop$wmemiM0_SRespLast),
.wmemiM0_SCmdAccept(ctop$wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept(ctop$wmemiM0_SDataAccept),
.RDY_server_request_put(ctop$RDY_server_request_put),
.server_response_get(ctop$server_response_get),
.RDY_server_response_get(ctop$RDY_server_response_get),
.RDY_cpServer_request_put(),
.cpServer_response_get(),
.RDY_cpServer_response_get(),
.led(ctop$led),
.wci_m_0_MCmd(),
.wci_m_0_MAddrSpace(),
.wci_m_0_MByteEn(),
.wci_m_0_MAddr(),
.wci_m_0_MData(),
.wci_m_0_MFlag(),
.wci_m_1_MCmd(),
.wci_m_1_MAddrSpace(),
.wci_m_1_MByteEn(),
.wci_m_1_MAddr(),
.wci_m_1_MData(),
.wci_m_1_MFlag(),
.wci_m_2_MCmd(ctop$wci_m_2_MCmd),
.wci_m_2_MAddrSpace(ctop$wci_m_2_MAddrSpace),
.wci_m_2_MByteEn(ctop$wci_m_2_MByteEn),
.wci_m_2_MAddr(ctop$wci_m_2_MAddr),
.wci_m_2_MData(ctop$wci_m_2_MData),
.wci_m_2_MFlag(ctop$wci_m_2_MFlag),
.wci_m_3_MCmd(ctop$wci_m_3_MCmd),
.wci_m_3_MAddrSpace(ctop$wci_m_3_MAddrSpace),
.wci_m_3_MByteEn(ctop$wci_m_3_MByteEn),
.wci_m_3_MAddr(ctop$wci_m_3_MAddr),
.wci_m_3_MData(ctop$wci_m_3_MData),
.wci_m_3_MFlag(),
.wci_m_4_MCmd(),
.wci_m_4_MAddrSpace(),
.wci_m_4_MByteEn(),
.wci_m_4_MAddr(),
.wci_m_4_MData(),
.wci_m_4_MFlag(),
.cpNow(),
.RDY_cpNow(),
.wsi_s_adc_SThreadBusy(),
.wsi_s_adc_SReset_n(),
.wsi_m_dac_MCmd(),
.wsi_m_dac_MReqLast(),
.wsi_m_dac_MBurstPrecise(),
.wsi_m_dac_MBurstLength(),
.wsi_m_dac_MData(),
.wsi_m_dac_MByteEn(),
.wsi_m_dac_MReqInfo(),
.wsi_m_dac_MReset_n(),
.wmemiM0_MCmd(),
.wmemiM0_MReqLast(),
.wmemiM0_MAddr(),
.wmemiM0_MBurstLength(),
.wmemiM0_MDataValid(),
.wmemiM0_MDataLast(),
.wmemiM0_MData(),
.wmemiM0_MDataByteEn(),
.wmemiM0_MReset_n(),
.gps_ppsSyncOut(),
.RST_N_wci_m_0(),
.RST_N_wci_m_1(),
.RST_N_wci_m_2(ctop$RST_N_wci_m_2),
.RST_N_wci_m_3(ctop$RST_N_wci_m_3),
.RST_N_wci_m_4());
// submodule gbe0
mkGbeWorker #(.hasDebugLogic(1'd1)) gbe0(.CLK_gmii_rx_clk(gmii_rx_clk),
.CLK_sys1_clk(sys1_clk$O),
.RST_N_sys1_rst(sys1_rst$OUT_RST),
.wciS0_Clk(pciw_pci0_pcie_ep$user_clk_out),
.wciS0_MReset_n(ctop$RST_N_wci_m_2),
.cpClient_response_put(gbe0$cpClient_response_put),
.gmii_col_i(gbe0$gmii_col_i),
.gmii_crs_i(gbe0$gmii_crs_i),
.gmii_intr_i(gbe0$gmii_intr_i),
.gmii_rx_rx_dv_i(gbe0$gmii_rx_rx_dv_i),
.gmii_rx_rx_er_i(gbe0$gmii_rx_rx_er_i),
.gmii_rx_rxd_i(gbe0$gmii_rx_rxd_i),
.wciS0_MAddr(gbe0$wciS0_MAddr),
.wciS0_MAddrSpace(gbe0$wciS0_MAddrSpace),
.wciS0_MByteEn(gbe0$wciS0_MByteEn),
.wciS0_MCmd(gbe0$wciS0_MCmd),
.wciS0_MData(gbe0$wciS0_MData),
.wciS0_MFlag(gbe0$wciS0_MFlag),
.wsiS0_MBurstLength(gbe0$wsiS0_MBurstLength),
.wsiS0_MByteEn(gbe0$wsiS0_MByteEn),
.wsiS0_MCmd(gbe0$wsiS0_MCmd),
.wsiS0_MData(gbe0$wsiS0_MData),
.wsiS0_MReqInfo(gbe0$wsiS0_MReqInfo),
.wtiS0_req(gbe0$wtiS0_req),
.wsiM0_SThreadBusy(gbe0$wsiM0_SThreadBusy),
.wsiM0_SReset_n(gbe0$wsiM0_SReset_n),
.wsiS0_MReqLast(gbe0$wsiS0_MReqLast),
.wsiS0_MBurstPrecise(gbe0$wsiS0_MBurstPrecise),
.wsiS0_MReset_n(gbe0$wsiS0_MReset_n),
.EN_cpClient_request_get(gbe0$EN_cpClient_request_get),
.EN_cpClient_response_put(gbe0$EN_cpClient_response_put),
.wciS0_SResp(gbe0$wciS0_SResp),
.wciS0_SData(gbe0$wciS0_SData),
.wciS0_SThreadBusy(gbe0$wciS0_SThreadBusy),
.wciS0_SFlag(gbe0$wciS0_SFlag),
.wtiS0_SThreadBusy(),
.wtiS0_SReset_n(),
.wsiM0_MCmd(gbe0$wsiM0_MCmd),
.wsiM0_MReqLast(gbe0$wsiM0_MReqLast),
.wsiM0_MBurstPrecise(gbe0$wsiM0_MBurstPrecise),
.wsiM0_MBurstLength(gbe0$wsiM0_MBurstLength),
.wsiM0_MData(gbe0$wsiM0_MData),
.wsiM0_MByteEn(gbe0$wsiM0_MByteEn),
.wsiM0_MReqInfo(gbe0$wsiM0_MReqInfo),
.wsiM0_MReset_n(gbe0$wsiM0_MReset_n),
.wsiS0_SThreadBusy(),
.wsiS0_SReset_n(),
.cpClient_request_get(),
.RDY_cpClient_request_get(),
.RDY_cpClient_response_put(),
.gmii_tx_txd(gbe0$gmii_tx_txd),
.gmii_tx_tx_en(gbe0$gmii_tx_tx_en),
.gmii_tx_tx_er(gbe0$gmii_tx_tx_er),
.gmii_led(gbe0$gmii_led),
.CLK_gmii_tx_tx_clk(gbe0$CLK_gmii_tx_tx_clk),
.CLK_GATE_gmii_tx_tx_clk(),
.CLK_rxclkBnd(gbe0$CLK_rxclkBnd),
.CLK_GATE_rxclkBnd(),
.RST_N_gmii_rstn(gbe0$RST_N_gmii_rstn),
.mdio_mdd(mdio_mdd),
.mdio_mdc(mdio_mdc));
// submodule idc
IDELAYCTRL idc(.REFCLK(sys0_clk$O), .RST(idc_resetP$RESET_OUT), .RDY());
// submodule idc_resetP
ResetInverter idc_resetP(.RESET_IN(sys0_rst$OUT_RST),
.RESET_OUT(idc_resetP$RESET_OUT));
// submodule lcd_ctrl
mkLCDController lcd_ctrl(.CLK(sys0_clk$O),
.RST_N(sys0_rst$OUT_RST),
.setLine1_text(lcd_ctrl$setLine1_text),
.setLine2_text(lcd_ctrl$setLine2_text),
.EN_setLine1(lcd_ctrl$EN_setLine1),
.EN_setLine2(lcd_ctrl$EN_setLine2),
.db(lcd_ctrl$db),
.e(lcd_ctrl$e),
.rs(lcd_ctrl$rs),
.rw(lcd_ctrl$rw));
// submodule pciw_fI2P
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_fI2P(.RST(pciw_p125rst$OUT_RST),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(pciw_fI2P$D_IN),
.ENQ(pciw_fI2P$ENQ),
.DEQ(pciw_fI2P$DEQ),
.CLR(pciw_fI2P$CLR),
.D_OUT(pciw_fI2P$D_OUT),
.FULL_N(pciw_fI2P$FULL_N),
.EMPTY_N(pciw_fI2P$EMPTY_N));
// submodule pciw_fP2I
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_fP2I(.RST(pciw_p125rst$OUT_RST),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(pciw_fP2I$D_IN),
.ENQ(pciw_fP2I$ENQ),
.DEQ(pciw_fP2I$DEQ),
.CLR(pciw_fP2I$CLR),
.D_OUT(pciw_fP2I$D_OUT),
.FULL_N(pciw_fP2I$FULL_N),
.EMPTY_N(pciw_fP2I$EMPTY_N));
// submodule pciw_p125rst
SyncResetA #(.RSTDELAY(32'd0)) pciw_p125rst(.CLK(pciw_pci0_pcie_ep$user_clk_out),
.IN_RST(pciw_pci0_usr_rst_n$RESET_OUT),
.OUT_RST(pciw_p125rst$OUT_RST));
// submodule pciw_pci0_axiRst125
SyncResetA #(.RSTDELAY(32'd1)) pciw_pci0_axiRst125(.CLK(pciw_pci0_pcie_ep$user_clk_out),
.IN_RST(pciw_pci0_usr_rst_n$RESET_OUT),
.OUT_RST(pciw_pci0_axiRst125$OUT_RST));
// submodule pciw_pci0_clk
IBUFDS_GTE2 pciw_pci0_clk(.I(pci0_clkp),
.IB(pci0_clkn),
.CEB(1'd0),
.O(pciw_pci0_clk$O),
.ODIV2());
// submodule pciw_pci0_pcie_ep
pcie_7x_v1_3 #(.PL_FAST_TRAIN("FALSE")) pciw_pci0_pcie_ep(.sys_clk(pciw_pci0_clk$O),
.sys_reset(pciw_pci0_pcie_ep_reset$RESET_OUT),
.PIPE_DCLK_IN(pciw_pci0_pcie_ep$PIPE_DCLK_IN),
.PIPE_MMCM_LOCK_IN(pciw_pci0_pcie_ep$PIPE_MMCM_LOCK_IN),
.PIPE_OOBCLK_IN(pciw_pci0_pcie_ep$PIPE_OOBCLK_IN),
.PIPE_PCLK_IN(pciw_pci0_pcie_ep$PIPE_PCLK_IN),
.PIPE_RXOUTCLK_IN(pciw_pci0_pcie_ep$PIPE_RXOUTCLK_IN),
.PIPE_RXUSRCLK_IN(pciw_pci0_pcie_ep$PIPE_RXUSRCLK_IN),
.PIPE_USERCLK1_IN(pciw_pci0_pcie_ep$PIPE_USERCLK1_IN),
.PIPE_USERCLK2_IN(pciw_pci0_pcie_ep$PIPE_USERCLK2_IN),
.cfg_dsn(pciw_pci0_pcie_ep$cfg_dsn),
.cfg_err_acs(pciw_pci0_pcie_ep$cfg_err_acs),
.cfg_err_aer_headerlog(pciw_pci0_pcie_ep$cfg_err_aer_headerlog),
.cfg_err_atomic_egress_blocked(pciw_pci0_pcie_ep$cfg_err_atomic_egress_blocked),
.cfg_err_cor(pciw_pci0_pcie_ep$cfg_err_cor),
.cfg_err_cpl_abort(pciw_pci0_pcie_ep$cfg_err_cpl_abort),
.cfg_err_cpl_timeout(pciw_pci0_pcie_ep$cfg_err_cpl_timeout),
.cfg_err_cpl_unexpect(pciw_pci0_pcie_ep$cfg_err_cpl_unexpect),
.cfg_err_ecrc(pciw_pci0_pcie_ep$cfg_err_ecrc),
.cfg_err_internal_cor(pciw_pci0_pcie_ep$cfg_err_internal_cor),
.cfg_err_internal_uncor(pciw_pci0_pcie_ep$cfg_err_internal_uncor),
.cfg_err_locked(pciw_pci0_pcie_ep$cfg_err_locked),
.cfg_err_malformed(pciw_pci0_pcie_ep$cfg_err_malformed),
.cfg_err_mc_blocked(pciw_pci0_pcie_ep$cfg_err_mc_blocked),
.cfg_err_norecovery(pciw_pci0_pcie_ep$cfg_err_norecovery),
.cfg_err_poisoned(pciw_pci0_pcie_ep$cfg_err_poisoned),
.cfg_err_posted(pciw_pci0_pcie_ep$cfg_err_posted),
.cfg_err_tlp_cpl_header(pciw_pci0_pcie_ep$cfg_err_tlp_cpl_header),
.cfg_err_ur(pciw_pci0_pcie_ep$cfg_err_ur),
.cfg_interrupt(pciw_pci0_pcie_ep$cfg_interrupt),
.cfg_interrupt_assert(pciw_pci0_pcie_ep$cfg_interrupt_assert),
.cfg_interrupt_di(pciw_pci0_pcie_ep$cfg_interrupt_di),
.cfg_interrupt_stat(pciw_pci0_pcie_ep$cfg_interrupt_stat),
.cfg_mgmt_byte_en(pciw_pci0_pcie_ep$cfg_mgmt_byte_en),
.cfg_mgmt_di(pciw_pci0_pcie_ep$cfg_mgmt_di),
.cfg_mgmt_dwaddr(pciw_pci0_pcie_ep$cfg_mgmt_dwaddr),
.cfg_mgmt_rd_en(pciw_pci0_pcie_ep$cfg_mgmt_rd_en),
.cfg_mgmt_wr_en(pciw_pci0_pcie_ep$cfg_mgmt_wr_en),
.cfg_mgmt_wr_readonly(pciw_pci0_pcie_ep$cfg_mgmt_wr_readonly),
.cfg_pciecap_interrupt_msgnum(pciw_pci0_pcie_ep$cfg_pciecap_interrupt_msgnum),
.cfg_pm_force_state(pciw_pci0_pcie_ep$cfg_pm_force_state),
.cfg_pm_force_state_en(pciw_pci0_pcie_ep$cfg_pm_force_state_en),
.cfg_pm_halt_aspm_l0s(pciw_pci0_pcie_ep$cfg_pm_halt_aspm_l0s),
.cfg_pm_halt_aspm_l1(pciw_pci0_pcie_ep$cfg_pm_halt_aspm_l1),
.cfg_pm_wake(pciw_pci0_pcie_ep$cfg_pm_wake),
.cfg_trn_pending(pciw_pci0_pcie_ep$cfg_trn_pending),
.cfg_turnoff_ok(pciw_pci0_pcie_ep$cfg_turnoff_ok),
.fc_sel(pciw_pci0_pcie_ep$fc_sel),
.m_axis_rx_tready(pciw_pci0_pcie_ep$m_axis_rx_tready),
.pci_exp_rxn(pciw_pci0_pcie_ep$pci_exp_rxn),
.pci_exp_rxp(pciw_pci0_pcie_ep$pci_exp_rxp),
.pl_directed_link_auton(pciw_pci0_pcie_ep$pl_directed_link_auton),
.pl_directed_link_change(pciw_pci0_pcie_ep$pl_directed_link_change),
.pl_directed_link_speed(pciw_pci0_pcie_ep$pl_directed_link_speed),
.pl_directed_link_width(pciw_pci0_pcie_ep$pl_directed_link_width),
.pl_upstream_prefer_deemph(pciw_pci0_pcie_ep$pl_upstream_prefer_deemph),
.rx_np_ok(pciw_pci0_pcie_ep$rx_np_ok),
.rx_np_req(pciw_pci0_pcie_ep$rx_np_req),
.s_axis_tx_tdata(pciw_pci0_pcie_ep$s_axis_tx_tdata),
.s_axis_tx_tkeep(pciw_pci0_pcie_ep$s_axis_tx_tkeep),
.s_axis_tx_tlast(pciw_pci0_pcie_ep$s_axis_tx_tlast),
.s_axis_tx_tuser(pciw_pci0_pcie_ep$s_axis_tx_tuser),
.s_axis_tx_tvalid(pciw_pci0_pcie_ep$s_axis_tx_tvalid),
.tx_cfg_gnt(pciw_pci0_pcie_ep$tx_cfg_gnt),
.pci_exp_txp(pciw_pci0_pcie_ep$pci_exp_txp),
.pci_exp_txn(pciw_pci0_pcie_ep$pci_exp_txn),
.cfg_mgmt_do(),
.cfg_mgmt_rd_wr_done(),
.cfg_to_turnoff(),
.cfg_bus_number(pciw_pci0_pcie_ep$cfg_bus_number),
.cfg_device_number(pciw_pci0_pcie_ep$cfg_device_number),
.cfg_function_number(pciw_pci0_pcie_ep$cfg_function_number),
.cfg_interrupt_rdy(),
.cfg_interrupt_do(),
.cfg_interrupt_mmenable(),
.cfg_interrupt_msienable(),
.cfg_interrupt_msixenable(),
.cfg_interrupt_msixfm(),
.pl_initial_link_width(),
.pl_lane_reversal_mode(),
.pl_link_gen2_cap(),
.pl_link_partner_gen2_supported(),
.pl_link_upcfg_cap(),
.pl_sel_lnk_rate(),
.pl_sel_lnk_width(),
.pl_ltssm_state(),
.pl_received_hot_rst(),
.user_lnk_up(pciw_pci0_pcie_ep$user_lnk_up),
.tx_buf_av(),
.tx_err_drop(),
.tx_cfg_req(),
.s_axis_tx_tready(pciw_pci0_pcie_ep$s_axis_tx_tready),
.m_axis_rx_tdata(pciw_pci0_pcie_ep$m_axis_rx_tdata),
.m_axis_rx_tkeep(),
.m_axis_rx_tlast(),
.m_axis_rx_tvalid(pciw_pci0_pcie_ep$m_axis_rx_tvalid),
.m_axis_rx_tuser(pciw_pci0_pcie_ep$m_axis_rx_tuser),
.fc_cpld(),
.fc_cplh(),
.fc_npd(),
.fc_nph(),
.fc_pd(),
.fc_ph(),
.cfg_status(),
.cfg_command(),
.cfg_dstatus(),
.cfg_dcommand(),
.cfg_lstatus(),
.cfg_lcommand(),
.cfg_dcommand2(),
.cfg_pcie_link_state(),
.cfg_pmcsr_pme_en(),
.cfg_pmcsr_powerstate(),
.cfg_pmcsr_pme_status(),
.cfg_received_func_lvl_rst(),
.cfg_err_cpl_rdy(),
.cfg_err_aer_headerlog_set(),
.PIPE_TXOUTCLK_OUT(),
.PIPE_RXOUTCLK_OUT(),
.PIPE_PCLK_SEL_OUT(),
.PIPE_GEN3_OUT(),
.user_clk_out(pciw_pci0_pcie_ep$user_clk_out),
.user_reset_out(pciw_pci0_pcie_ep$user_reset_out));
// submodule pciw_pci0_pcie_ep_reset
ResetInverter pciw_pci0_pcie_ep_reset(.RESET_IN(pci0_rstn),
.RESET_OUT(pciw_pci0_pcie_ep_reset$RESET_OUT));
// submodule pciw_pci0_rxF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_pci0_rxF(.RST(pciw_pci0_axiRst125$OUT_RST),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(pciw_pci0_rxF$D_IN),
.ENQ(pciw_pci0_rxF$ENQ),
.DEQ(pciw_pci0_rxF$DEQ),
.CLR(pciw_pci0_rxF$CLR),
.D_OUT(pciw_pci0_rxF$D_OUT),
.FULL_N(pciw_pci0_rxF$FULL_N),
.EMPTY_N(pciw_pci0_rxF$EMPTY_N));
// submodule pciw_pci0_txF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_pci0_txF(.RST(pciw_pci0_axiRst125$OUT_RST),
.CLK(pciw_pci0_pcie_ep$user_clk_out),
.D_IN(pciw_pci0_txF$D_IN),
.ENQ(pciw_pci0_txF$ENQ),
.DEQ(pciw_pci0_txF$DEQ),
.CLR(pciw_pci0_txF$CLR),
.D_OUT(pciw_pci0_txF$D_OUT),
.FULL_N(pciw_pci0_txF$FULL_N),
.EMPTY_N(pciw_pci0_txF$EMPTY_N));
// submodule pciw_pci0_usr_rst_n
ResetInverter pciw_pci0_usr_rst_n(.RESET_IN(pciw_pci0_pcie_ep$user_reset_out),
.RESET_OUT(pciw_pci0_usr_rst_n$RESET_OUT));
// submodule sys0_clk
IBUFDS sys0_clk(.I(sys0_clkp), .IB(sys0_clkn), .O(sys0_clk$O));
// submodule sys0_rst
SyncResetA #(.RSTDELAY(32'd15)) sys0_rst(.CLK(sys0_clk$O),
.IN_RST(sys0_rstn),
.OUT_RST(sys0_rst$OUT_RST));
// submodule sys1_clk
BUFG sys1_clk(.I(sys1_clki$O), .O(sys1_clk$O));
// submodule sys1_clki
IBUFDS_GTE2 sys1_clki(.I(sys1_clkp),
.IB(sys1_clkn),
.CEB(1'd0),
.O(sys1_clki$O),
.ODIV2());
// submodule sys1_rst
SyncResetA #(.RSTDELAY(32'd0)) sys1_rst(.CLK(sys1_clk$O),
.IN_RST(pciw_p125rst$OUT_RST),
.OUT_RST(sys1_rst$OUT_RST));
// rule RL_cap0_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start =
cap0_wci_wslv_reqF$EMPTY_N && cap0_wci_wslv_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete ;
// rule RL_cap0_wci_ctrl_EiI
assign WILL_FIRE_RL_cap0_wci_ctrl_EiI =
cap0_wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start &&
cap0_wci_wslv_cState == 3'd0 &&
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_cap0_wci_ctrl_IsO
assign WILL_FIRE_RL_cap0_wci_ctrl_IsO =
cap0_wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start &&
cap0_wci_wslv_cState == 3'd1 &&
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_cap0_wci_ctrl_OrE
assign WILL_FIRE_RL_cap0_wci_ctrl_OrE =
cap0_wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start &&
cap0_wci_wslv_cState == 3'd2 &&
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_cap0_wci_cfrd
assign CAN_FIRE_RL_cap0_wci_cfrd =
cap0_wci_wslv_reqF$EMPTY_N &&
IF_cap0_wci_wslv_reqF_first__75_BITS_63_TO_52__ETC___d1128 &&
(cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h800 ||
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h400 ||
cap0_wci_wslv_respF_c_r != 2'd2) &&
cap0_wci_wslv_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_cap0_wci_cfrd =
CAN_FIRE_RL_cap0_wci_cfrd &&
!WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete ;
// rule RL_cap0_doMessageAccept
assign WILL_FIRE_RL_cap0_doMessageAccept =
cap0_wsiS_reqFifo$EMPTY_N &&
NOT_cap0_controlReg_60_BIT_0_61_62_OR_cap0_con_ETC___d986 &&
cap0_wci_wslv_cState == 3'd2 ;
// rule RL_cap0_wci_cfwr
assign WILL_FIRE_RL_cap0_wci_cfwr =
cap0_wci_wslv_respF_c_r != 2'd2 && cap0_wci_wslv_reqF$EMPTY_N &&
cap0_wci_wslv_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete ;
// rule RL_cap0_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete =
cap0_wci_wslv_respF_c_r != 2'd2 && cap0_wci_wslv_ctlOpActive &&
cap0_wci_wslv_ctlAckReg ;
// rule RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways =
WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h800 ;
// rule RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways =
WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
cap0_wci_wslv_reqF$D_OUT[35:34] == 2'd0 ;
// rule RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways
assign WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways =
WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
cap0_wci_wslv_reqF$D_OUT[35:34] == 2'd1 ;
// rule RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways
assign WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways =
WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
cap0_wci_wslv_reqF$D_OUT[35:34] == 2'd2 ;
// rule RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways
assign WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways =
WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
cap0_wci_wslv_reqF$D_OUT[35:34] == 2'd3 ;
// rule RL_cap0_advance_split_response
assign WILL_FIRE_RL_cap0_advance_split_response =
cap0_wci_wslv_respF_c_r != 2'd2 &&
cap0_splaF_i_notEmpty__026_AND_IF_cap0_splaF_f_ETC___d1059 &&
!cap0_wci_wslv_wci_cfwr_pw$whas &&
cap0_splitReadInFlight &&
!WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete ;
// rule RL_cap0_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_cap0_wci_wslv_respF_incCtr =
((cap0_wci_wslv_respF_c_r == 2'd0) ?
cap0_wci_wslv_respF_x_wire$whas :
cap0_wci_wslv_respF_c_r != 2'd1 ||
cap0_wci_wslv_respF_x_wire$whas) &&
cap0_wci_wslv_respF_enqueueing$whas &&
!(cap0_wci_wslv_respF_c_r != 2'd0) ;
// rule RL_cap0_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr =
cap0_wci_wslv_respF_c_r != 2'd0 &&
!cap0_wci_wslv_respF_enqueueing$whas ;
// rule RL_cap0_wci_wslv_respF_both
assign WILL_FIRE_RL_cap0_wci_wslv_respF_both =
((cap0_wci_wslv_respF_c_r == 2'd1) ?
cap0_wci_wslv_respF_x_wire$whas :
cap0_wci_wslv_respF_c_r != 2'd2 ||
cap0_wci_wslv_respF_x_wire$whas) &&
cap0_wci_wslv_respF_c_r != 2'd0 &&
cap0_wci_wslv_respF_enqueueing$whas ;
// rule RL_cap0_dataBram_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_cap0_dataBram_serverAdapterB_outData_enqAndDeq =
cap0_dataBram_serverAdapterB_outDataCore$EMPTY_N &&
cap0_dataBram_serverAdapterB_outDataCore$FULL_N &&
cap0_dataBram_serverAdapterB_outData_deqCalled$whas &&
cap0_dataBram_serverAdapterB_outData_enqData$whas ;
// rule RL_cap0_metaBram_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_cap0_metaBram_serverAdapterB_outData_enqAndDeq =
cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_outDataCore$FULL_N &&
cap0_metaBram_serverAdapterB_outData_deqCalled$whas &&
cap0_metaBram_serverAdapterB_outData_enqData$whas ;
// rule RL_cap0_metaBram_serverAdapterB_1_outData_enqAndDeq
assign WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_outData_enqAndDeq =
cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_1_outDataCore$FULL_N &&
cap0_metaBram_serverAdapterB_1_outData_deqCalled$whas &&
cap0_metaBram_serverAdapterB_1_outData_enqData$whas ;
// rule RL_cap0_metaBram_serverAdapterB_2_outData_enqAndDeq
assign WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_outData_enqAndDeq =
cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_2_outDataCore$FULL_N &&
cap0_metaBram_serverAdapterB_2_outData_deqCalled$whas &&
cap0_metaBram_serverAdapterB_2_outData_enqData$whas ;
// rule RL_cap0_metaBram_serverAdapterB_3_outData_enqAndDeq
assign WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_outData_enqAndDeq =
cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_3_outDataCore$FULL_N &&
cap0_metaBram_serverAdapterB_3_outData_deqCalled$whas &&
cap0_metaBram_serverAdapterB_3_outData_enqData$whas ;
// rule RL_cap0_wsiS_reqFifo_enq
assign WILL_FIRE_RL_cap0_wsiS_reqFifo_enq =
cap0_wsiS_reqFifo$FULL_N && cap0_wsiS_operateD &&
cap0_wsiS_peerIsReady &&
cap0_wsiS_wsiReq$wget[60:58] == 3'd1 ;
// rule RL_cap0_wsiS_reqFifo_reset
assign WILL_FIRE_RL_cap0_wsiS_reqFifo_reset =
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq ||
WILL_FIRE_RL_cap0_doMessageAccept ;
// inputs to muxes for submodule ports
assign MUX_cap0_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_cap0_wci_cfwr &&
cap0_wci_wslv_reqF$D_OUT[39:32] == 8'h0 ;
assign MUX_cap0_dataCount$write_1__SEL_1 =
WILL_FIRE_RL_cap0_wci_cfwr &&
cap0_wci_wslv_reqF$D_OUT[39:32] == 8'h08 ;
assign MUX_cap0_dataCount$write_1__SEL_2 =
WILL_FIRE_RL_cap0_doMessageAccept &&
cap0_controlReg_60_BIT_0_61_AND_NOT_cap0_contr_ETC___d1008 ;
assign MUX_cap0_metaCount$write_1__SEL_1 =
WILL_FIRE_RL_cap0_wci_cfwr &&
cap0_wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_cap0_metaCount$write_1__SEL_2 =
WILL_FIRE_RL_cap0_doMessageAccept &&
cap0_controlReg_60_BIT_0_61_AND_NOT_cap0_contr_ETC___d1008 &&
cap0_wsiS_reqFifo$D_OUT[57] ;
assign MUX_cap0_splitReadInFlight$write_1__SEL_1 =
WILL_FIRE_RL_cap0_wci_cfrd &&
(cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h800 ||
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h400) ;
assign MUX_cap0_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete &&
cap0_wci_wslv_illegalEdge ;
assign MUX_cap0_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start &&
(cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd0 &&
cap0_wci_wslv_cState != 3'd0 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
cap0_wci_wslv_cState != 3'd1 &&
cap0_wci_wslv_cState != 3'd3 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd2 &&
cap0_wci_wslv_cState != 3'd2 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
cap0_wci_wslv_cState != 3'd3 &&
cap0_wci_wslv_cState != 3'd2 &&
cap0_wci_wslv_cState != 3'd1 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd4 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd5 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd6 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_cap0_wci_wslv_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_cap0_wci_wslv_respF_incCtr &&
cap0_wci_wslv_respF_c_r == 2'd0 ;
assign MUX_cap0_wci_wslv_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_cap0_wci_wslv_respF_incCtr &&
cap0_wci_wslv_respF_c_r == 2'd1 ;
assign MUX_cap0_wci_wslv_respF_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] != 12'h800 &&
cap0_wci_wslv_reqF$D_OUT[63:52] != 12'h400 ;
assign MUX_cap0_dataCount$write_1__VAL_2 = cap0_dataCount + 32'd1 ;
assign MUX_cap0_metaCount$write_1__VAL_2 = cap0_metaCount + 32'd1 ;
assign MUX_cap0_wci_wslv_illegalEdge$write_1__VAL_2 =
cap0_wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
cap0_wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
cap0_wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_cap0_wci_wslv_respF_c_r$write_1__VAL_1 =
cap0_wci_wslv_respF_c_r + 2'd1 ;
assign MUX_cap0_wci_wslv_respF_c_r$write_1__VAL_2 =
cap0_wci_wslv_respF_c_r - 2'd1 ;
assign MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_1 =
(cap0_wci_wslv_respF_c_r == 2'd1) ?
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 :
cap0_wci_wslv_respF_q_1 ;
always@(MUX_cap0_wci_wslv_respF_x_wire$wset_1__SEL_1 or
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete or
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_2 or
WILL_FIRE_RL_cap0_advance_split_response or
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_3 or
WILL_FIRE_RL_cap0_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
MUX_cap0_wci_wslv_respF_x_wire$wset_1__SEL_1:
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete:
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_cap0_advance_split_response:
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_3;
WILL_FIRE_RL_cap0_wci_cfwr:
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_cap0_wci_wslv_respF_q_1$write_1__VAL_1 =
(cap0_wci_wslv_respF_c_r == 2'd2) ?
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_1 =
{ 2'd1, g_data__h39139 } ;
assign MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_2 =
cap0_wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_cap0_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 2'd1, v__h36664 } ;
// inlined wires
assign pciw_pci0_axiTxData$wget =
{ pciw_pci0_txF$D_OUT[31:0],
pciw_pci0_txF$D_OUT[63:32],
pciw_pci0_txF$D_OUT[95:64],
pciw_pci0_txF$D_OUT[127:96] } ;
assign pciw_pci0_axiTxData$whas =
pciw_pci0_txF$EMPTY_N && pciw_pci0_pcie_ep$s_axis_tx_tready ;
assign pciw_pci0_axiTxKeep$wget =
pciw_pci0_txF$D_OUT[151] ?
{ pciw_pci0_txF$D_OUT[128],
pciw_pci0_txF$D_OUT[129],
pciw_pci0_txF$D_OUT[130],
pciw_pci0_txF$D_OUT[131],
pciw_pci0_txF$D_OUT[132],
pciw_pci0_txF$D_OUT[133],
pciw_pci0_txF$D_OUT[134],
pciw_pci0_txF$D_OUT[135],
pciw_pci0_txF$D_OUT[136],
pciw_pci0_txF$D_OUT[137],
pciw_pci0_txF$D_OUT[138],
pciw_pci0_txF$D_OUT[139],
pciw_pci0_txF$D_OUT[140],
pciw_pci0_txF$D_OUT[141],
pciw_pci0_txF$D_OUT[142],
pciw_pci0_txF$D_OUT[143] } :
16'd65535 ;
assign pciw_pci0_axiTxKeep$whas = pciw_pci0_axiTxData$whas ;
assign pciw_pci0_axiTxUser$wget = 4'b0 ;
assign pciw_pci0_axiTxUser$whas = pciw_pci0_axiTxData$whas ;
assign pciw_pci0_axiTxLast$wget = pciw_pci0_txF$D_OUT[151] ;
assign pciw_pci0_axiTxLast$whas = pciw_pci0_axiTxData$whas ;
assign pciw_pci0_axiTxValid$wget = 1'd1 ;
assign pciw_pci0_axiTxValid$whas = pciw_pci0_axiTxData$whas ;
assign cap0_wci_wslv_wciReq$wget =
{ ctop$wci_m_3_MCmd,
ctop$wci_m_3_MAddrSpace,
ctop$wci_m_3_MByteEn,
ctop$wci_m_3_MAddr,
ctop$wci_m_3_MData } ;
assign cap0_wci_wslv_wciReq$whas = 1'd1 ;
assign cap0_wci_wslv_respF_x_wire$wget =
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 ;
assign cap0_wci_wslv_respF_x_wire$whas =
WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] != 12'h800 &&
cap0_wci_wslv_reqF$D_OUT[63:52] != 12'h400 ||
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_cap0_advance_split_response ||
WILL_FIRE_RL_cap0_wci_cfwr ;
assign cap0_wci_wslv_wEdge$wget = cap0_wci_wslv_reqF$D_OUT[36:34] ;
assign cap0_wci_wslv_wEdge$whas = WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start ;
assign cap0_wci_wslv_sFlagReg_1$wget = 1'b0 ;
assign cap0_wci_wslv_sFlagReg_1$whas = 1'b0 ;
assign cap0_wci_wslv_ctlAckReg_1$wget = 1'd1 ;
assign cap0_wci_wslv_ctlAckReg_1$whas =
WILL_FIRE_RL_cap0_wci_ctrl_OrE ||
WILL_FIRE_RL_cap0_wci_ctrl_IsO ||
WILL_FIRE_RL_cap0_wci_ctrl_EiI ;
assign cap0_wci_wci_Es_mCmd_w$wget = ctop$wci_m_3_MCmd ;
assign cap0_wci_wci_Es_mCmd_w$whas = 1'd1 ;
assign cap0_wci_wci_Es_mAddrSpace_w$wget = ctop$wci_m_3_MAddrSpace ;
assign cap0_wci_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign cap0_wci_wci_Es_mByteEn_w$wget = ctop$wci_m_3_MByteEn ;
assign cap0_wci_wci_Es_mByteEn_w$whas = 1'd1 ;
assign cap0_wci_wci_Es_mAddr_w$wget = ctop$wci_m_3_MAddr ;
assign cap0_wci_wci_Es_mAddr_w$whas = 1'd1 ;
assign cap0_wci_wci_Es_mData_w$wget = ctop$wci_m_3_MData ;
assign cap0_wci_wci_Es_mData_w$whas = 1'd1 ;
assign cap0_wsiS_wsiReq$wget =
{ gbe0$wsiM0_MCmd,
gbe0$wsiM0_MReqLast,
gbe0$wsiM0_MBurstPrecise,
gbe0$wsiM0_MBurstLength,
gbe0$wsiM0_MData,
gbe0$wsiM0_MByteEn,
gbe0$wsiM0_MReqInfo } ;
assign cap0_wsiS_wsiReq$whas = 1'd1 ;
assign cap0_wsiS_operateD_1$wget = 1'd1 ;
assign cap0_wsiS_operateD_1$whas = cap0_wci_wslv_cState == 3'd2 ;
assign cap0_wsiS_peerIsReady_1$wget = 1'd1 ;
assign cap0_wsiS_peerIsReady_1$whas = gbe0$wsiM0_MReset_n ;
assign cap0_wsiS_sThreadBusy_dw$wget = cap0_wsiS_reqFifo_countReg > 2'd1 ;
assign cap0_wsiS_sThreadBusy_dw$whas =
cap0_wsiS_reqFifo_levelsValid && cap0_wsiS_operateD &&
cap0_wsiS_peerIsReady ;
assign cap0_wtiS_wtiReq$wget = 67'h0 ;
assign cap0_wtiS_wtiReq$whas = 1'b0 ;
assign cap0_wtiS_operateD_1$wget = 1'b0 ;
assign cap0_wtiS_operateD_1$whas = 1'b0 ;
assign cap0_nowW$wget = cap0_wtiS_nowReq[63:0] ;
assign cap0_nowW$whas = 1'd1 ;
assign cap0_statusReg_w$wget = rdat___1__h38161 ;
assign cap0_statusReg_w$whas = 1'd1 ;
assign cap0_dataBram_serverAdapterA_outData_enqData$wget =
cap0_dataBram_memory$DOA ;
assign cap0_dataBram_serverAdapterA_outData_enqData$whas =
(!cap0_dataBram_serverAdapterA_s1[0] ||
cap0_dataBram_serverAdapterA_outDataCore$FULL_N) &&
cap0_dataBram_serverAdapterA_s1[1] &&
cap0_dataBram_serverAdapterA_s1[0] ;
assign cap0_dataBram_serverAdapterA_outData_outData$wget =
cap0_dataBram_serverAdapterA_outDataCore$EMPTY_N ?
cap0_dataBram_serverAdapterA_outDataCore$D_OUT :
cap0_dataBram_memory$DOA ;
assign cap0_dataBram_serverAdapterA_outData_outData$whas =
cap0_dataBram_serverAdapterA_outDataCore$EMPTY_N ||
!cap0_dataBram_serverAdapterA_outDataCore$EMPTY_N &&
cap0_dataBram_serverAdapterA_outData_enqData$whas ;
assign cap0_dataBram_serverAdapterA_cnt_1$wget = 3'd1 ;
assign cap0_dataBram_serverAdapterA_cnt_1$whas = 1'b0 ;
assign cap0_dataBram_serverAdapterA_cnt_2$wget = 3'h0 ;
assign cap0_dataBram_serverAdapterA_cnt_2$whas = 1'b0 ;
assign cap0_dataBram_serverAdapterA_cnt_3$wget = 3'h0 ;
assign cap0_dataBram_serverAdapterA_cnt_3$whas = 1'b0 ;
assign cap0_dataBram_serverAdapterA_writeWithResp$wget = 2'd2 ;
assign cap0_dataBram_serverAdapterA_writeWithResp$whas =
MUX_cap0_dataCount$write_1__SEL_2 ;
assign cap0_dataBram_serverAdapterA_s1_1$wget = 2'd2 ;
assign cap0_dataBram_serverAdapterA_s1_1$whas =
MUX_cap0_dataCount$write_1__SEL_2 ;
assign cap0_dataBram_serverAdapterB_outData_enqData$wget =
cap0_dataBram_memory$DOB ;
assign cap0_dataBram_serverAdapterB_outData_enqData$whas =
(!cap0_dataBram_serverAdapterB_s1[0] ||
cap0_dataBram_serverAdapterB_outDataCore$FULL_N) &&
cap0_dataBram_serverAdapterB_s1[1] &&
cap0_dataBram_serverAdapterB_s1[0] ;
assign cap0_dataBram_serverAdapterB_outData_outData$wget =
y_avValue__h37291 ;
assign cap0_dataBram_serverAdapterB_outData_outData$whas =
cap0_dataBram_serverAdapterB_outDataCore$EMPTY_N ||
!cap0_dataBram_serverAdapterB_outDataCore$EMPTY_N &&
cap0_dataBram_serverAdapterB_outData_enqData$whas ;
assign cap0_dataBram_serverAdapterB_cnt_1$wget = 3'd1 ;
assign cap0_dataBram_serverAdapterB_cnt_1$whas =
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways ;
assign cap0_dataBram_serverAdapterB_cnt_2$wget = 3'd7 ;
assign cap0_dataBram_serverAdapterB_cnt_2$whas =
cap0_dataBram_serverAdapterB_outData_deqCalled$whas ;
assign cap0_dataBram_serverAdapterB_cnt_3$wget = 3'h0 ;
assign cap0_dataBram_serverAdapterB_cnt_3$whas = 1'b0 ;
assign cap0_dataBram_serverAdapterB_writeWithResp$wget = 2'd0 ;
assign cap0_dataBram_serverAdapterB_writeWithResp$whas =
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways ;
assign cap0_dataBram_serverAdapterB_s1_1$wget = 2'd3 ;
assign cap0_dataBram_serverAdapterB_s1_1$whas =
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterA_outData_enqData$wget =
cap0_metaBram_memory$DOA ;
assign cap0_metaBram_serverAdapterA_outData_enqData$whas =
(!cap0_metaBram_serverAdapterA_s1[0] ||
cap0_metaBram_serverAdapterA_outDataCore$FULL_N) &&
cap0_metaBram_serverAdapterA_s1[1] &&
cap0_metaBram_serverAdapterA_s1[0] ;
assign cap0_metaBram_serverAdapterA_outData_outData$wget =
cap0_metaBram_serverAdapterA_outDataCore$EMPTY_N ?
cap0_metaBram_serverAdapterA_outDataCore$D_OUT :
cap0_metaBram_memory$DOA ;
assign cap0_metaBram_serverAdapterA_outData_outData$whas =
cap0_metaBram_serverAdapterA_outDataCore$EMPTY_N ||
!cap0_metaBram_serverAdapterA_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterA_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterA_cnt_1$wget = 3'd1 ;
assign cap0_metaBram_serverAdapterA_cnt_1$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_cnt_2$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterA_cnt_2$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_cnt_3$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterA_cnt_3$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_writeWithResp$wget = 2'd2 ;
assign cap0_metaBram_serverAdapterA_writeWithResp$whas =
MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_serverAdapterA_s1_1$wget = 2'd2 ;
assign cap0_metaBram_serverAdapterA_s1_1$whas =
MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_serverAdapterB_outData_enqData$wget =
cap0_metaBram_memory$DOB ;
assign cap0_metaBram_serverAdapterB_outData_enqData$whas =
(!cap0_metaBram_serverAdapterB_s1[0] ||
cap0_metaBram_serverAdapterB_outDataCore$FULL_N) &&
cap0_metaBram_serverAdapterB_s1[1] &&
cap0_metaBram_serverAdapterB_s1[0] ;
assign cap0_metaBram_serverAdapterB_outData_outData$wget =
y_avValue__h37335 ;
assign cap0_metaBram_serverAdapterB_outData_outData$whas =
cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N ||
!cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_cnt_1$wget = 3'd1 ;
assign cap0_metaBram_serverAdapterB_cnt_1$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterB_cnt_2$wget = 3'd7 ;
assign cap0_metaBram_serverAdapterB_cnt_2$whas =
cap0_metaBram_serverAdapterB_outData_deqCalled$whas ;
assign cap0_metaBram_serverAdapterB_cnt_3$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterB_cnt_3$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterB_writeWithResp$wget = 2'd0 ;
assign cap0_metaBram_serverAdapterB_writeWithResp$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterB_s1_1$wget = 2'd3 ;
assign cap0_metaBram_serverAdapterB_s1_1$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterA_1_outData_enqData$wget =
cap0_metaBram_memory_1$DOA ;
assign cap0_metaBram_serverAdapterA_1_outData_enqData$whas =
(!cap0_metaBram_serverAdapterA_1_s1[0] ||
cap0_metaBram_serverAdapterA_1_outDataCore$FULL_N) &&
cap0_metaBram_serverAdapterA_1_s1[1] &&
cap0_metaBram_serverAdapterA_1_s1[0] ;
assign cap0_metaBram_serverAdapterA_1_outData_outData$wget =
cap0_metaBram_serverAdapterA_1_outDataCore$EMPTY_N ?
cap0_metaBram_serverAdapterA_1_outDataCore$D_OUT :
cap0_metaBram_memory_1$DOA ;
assign cap0_metaBram_serverAdapterA_1_outData_outData$whas =
cap0_metaBram_serverAdapterA_1_outDataCore$EMPTY_N ||
!cap0_metaBram_serverAdapterA_1_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterA_1_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterA_1_cnt_1$wget = 3'd1 ;
assign cap0_metaBram_serverAdapterA_1_cnt_1$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_1_cnt_2$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterA_1_cnt_2$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_1_cnt_3$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterA_1_cnt_3$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_1_writeWithResp$wget = 2'd2 ;
assign cap0_metaBram_serverAdapterA_1_writeWithResp$whas =
MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_serverAdapterA_1_s1_1$wget = 2'd2 ;
assign cap0_metaBram_serverAdapterA_1_s1_1$whas =
MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_serverAdapterB_1_outData_enqData$wget =
cap0_metaBram_memory_1$DOB ;
assign cap0_metaBram_serverAdapterB_1_outData_enqData$whas =
(!cap0_metaBram_serverAdapterB_1_s1[0] ||
cap0_metaBram_serverAdapterB_1_outDataCore$FULL_N) &&
cap0_metaBram_serverAdapterB_1_s1[1] &&
cap0_metaBram_serverAdapterB_1_s1[0] ;
assign cap0_metaBram_serverAdapterB_1_outData_outData$wget =
y_avValue__h37375 ;
assign cap0_metaBram_serverAdapterB_1_outData_outData$whas =
cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N ||
!cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_1_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_1_cnt_1$wget = 3'd1 ;
assign cap0_metaBram_serverAdapterB_1_cnt_1$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterB_1_cnt_2$wget = 3'd7 ;
assign cap0_metaBram_serverAdapterB_1_cnt_2$whas =
cap0_metaBram_serverAdapterB_1_outData_deqCalled$whas ;
assign cap0_metaBram_serverAdapterB_1_cnt_3$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterB_1_cnt_3$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterB_1_writeWithResp$wget = 2'd0 ;
assign cap0_metaBram_serverAdapterB_1_writeWithResp$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterB_1_s1_1$wget = 2'd3 ;
assign cap0_metaBram_serverAdapterB_1_s1_1$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterA_2_outData_enqData$wget =
cap0_metaBram_memory_2$DOA ;
assign cap0_metaBram_serverAdapterA_2_outData_enqData$whas =
(!cap0_metaBram_serverAdapterA_2_s1[0] ||
cap0_metaBram_serverAdapterA_2_outDataCore$FULL_N) &&
cap0_metaBram_serverAdapterA_2_s1[1] &&
cap0_metaBram_serverAdapterA_2_s1[0] ;
assign cap0_metaBram_serverAdapterA_2_outData_outData$wget =
cap0_metaBram_serverAdapterA_2_outDataCore$EMPTY_N ?
cap0_metaBram_serverAdapterA_2_outDataCore$D_OUT :
cap0_metaBram_memory_2$DOA ;
assign cap0_metaBram_serverAdapterA_2_outData_outData$whas =
cap0_metaBram_serverAdapterA_2_outDataCore$EMPTY_N ||
!cap0_metaBram_serverAdapterA_2_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterA_2_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterA_2_cnt_1$wget = 3'd1 ;
assign cap0_metaBram_serverAdapterA_2_cnt_1$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_2_cnt_2$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterA_2_cnt_2$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_2_cnt_3$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterA_2_cnt_3$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_2_writeWithResp$wget = 2'd2 ;
assign cap0_metaBram_serverAdapterA_2_writeWithResp$whas =
MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_serverAdapterA_2_s1_1$wget = 2'd2 ;
assign cap0_metaBram_serverAdapterA_2_s1_1$whas =
MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_serverAdapterB_2_outData_enqData$wget =
cap0_metaBram_memory_2$DOB ;
assign cap0_metaBram_serverAdapterB_2_outData_enqData$whas =
(!cap0_metaBram_serverAdapterB_2_s1[0] ||
cap0_metaBram_serverAdapterB_2_outDataCore$FULL_N) &&
cap0_metaBram_serverAdapterB_2_s1[1] &&
cap0_metaBram_serverAdapterB_2_s1[0] ;
assign cap0_metaBram_serverAdapterB_2_outData_outData$wget =
y_avValue__h37415 ;
assign cap0_metaBram_serverAdapterB_2_outData_outData$whas =
cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N ||
!cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_2_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_2_cnt_1$wget = 3'd1 ;
assign cap0_metaBram_serverAdapterB_2_cnt_1$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterB_2_cnt_2$wget = 3'd7 ;
assign cap0_metaBram_serverAdapterB_2_cnt_2$whas =
cap0_metaBram_serverAdapterB_2_outData_deqCalled$whas ;
assign cap0_metaBram_serverAdapterB_2_cnt_3$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterB_2_cnt_3$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterB_2_writeWithResp$wget = 2'd0 ;
assign cap0_metaBram_serverAdapterB_2_writeWithResp$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterB_2_s1_1$wget = 2'd3 ;
assign cap0_metaBram_serverAdapterB_2_s1_1$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterA_3_outData_enqData$wget =
cap0_metaBram_memory_3$DOA ;
assign cap0_metaBram_serverAdapterA_3_outData_enqData$whas =
(!cap0_metaBram_serverAdapterA_3_s1[0] ||
cap0_metaBram_serverAdapterA_3_outDataCore$FULL_N) &&
cap0_metaBram_serverAdapterA_3_s1[1] &&
cap0_metaBram_serverAdapterA_3_s1[0] ;
assign cap0_metaBram_serverAdapterA_3_outData_outData$wget =
cap0_metaBram_serverAdapterA_3_outDataCore$EMPTY_N ?
cap0_metaBram_serverAdapterA_3_outDataCore$D_OUT :
cap0_metaBram_memory_3$DOA ;
assign cap0_metaBram_serverAdapterA_3_outData_outData$whas =
cap0_metaBram_serverAdapterA_3_outDataCore$EMPTY_N ||
!cap0_metaBram_serverAdapterA_3_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterA_3_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterA_3_cnt_1$wget = 3'd1 ;
assign cap0_metaBram_serverAdapterA_3_cnt_1$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_3_cnt_2$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterA_3_cnt_2$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_3_cnt_3$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterA_3_cnt_3$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterA_3_writeWithResp$wget = 2'd2 ;
assign cap0_metaBram_serverAdapterA_3_writeWithResp$whas =
MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_serverAdapterA_3_s1_1$wget = 2'd2 ;
assign cap0_metaBram_serverAdapterA_3_s1_1$whas =
MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_serverAdapterB_3_outData_enqData$wget =
cap0_metaBram_memory_3$DOB ;
assign cap0_metaBram_serverAdapterB_3_outData_enqData$whas =
(!cap0_metaBram_serverAdapterB_3_s1[0] ||
cap0_metaBram_serverAdapterB_3_outDataCore$FULL_N) &&
cap0_metaBram_serverAdapterB_3_s1[1] &&
cap0_metaBram_serverAdapterB_3_s1[0] ;
assign cap0_metaBram_serverAdapterB_3_outData_outData$wget =
y_avValue__h37455 ;
assign cap0_metaBram_serverAdapterB_3_outData_outData$whas =
cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N ||
!cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_3_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_3_cnt_1$wget = 3'd1 ;
assign cap0_metaBram_serverAdapterB_3_cnt_1$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterB_3_cnt_2$wget = 3'd7 ;
assign cap0_metaBram_serverAdapterB_3_cnt_2$whas =
cap0_metaBram_serverAdapterB_3_outData_deqCalled$whas ;
assign cap0_metaBram_serverAdapterB_3_cnt_3$wget = 3'h0 ;
assign cap0_metaBram_serverAdapterB_3_cnt_3$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterB_3_writeWithResp$wget = 2'd0 ;
assign cap0_metaBram_serverAdapterB_3_writeWithResp$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways ;
assign cap0_metaBram_serverAdapterB_3_s1_1$wget = 2'd3 ;
assign cap0_metaBram_serverAdapterB_3_s1_1$whas =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways ;
assign cap0_wsi_Es_mCmd_w$wget = gbe0$wsiM0_MCmd ;
assign cap0_wsi_Es_mCmd_w$whas = 1'd1 ;
assign cap0_wsi_Es_mBurstLength_w$wget = gbe0$wsiM0_MBurstLength ;
assign cap0_wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign cap0_wsi_Es_mData_w$wget = gbe0$wsiM0_MData ;
assign cap0_wsi_Es_mData_w$whas = 1'd1 ;
assign cap0_wsi_Es_mByteEn_w$wget = gbe0$wsiM0_MByteEn ;
assign cap0_wsi_Es_mByteEn_w$whas = 1'd1 ;
assign cap0_wsi_Es_mReqInfo_w$wget = gbe0$wsiM0_MReqInfo ;
assign cap0_wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign cap0_wti_Es_mCmd_w$wget = 3'h0 ;
assign cap0_wti_Es_mCmd_w$whas = 1'b0 ;
assign cap0_wti_Es_mData_w$wget = 64'h0 ;
assign cap0_wti_Es_mData_w$whas = 1'b0 ;
assign cap0_wci_wslv_reqF_r_enq$whas =
cap0_wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign cap0_wci_wslv_reqF_r_deq$whas =
WILL_FIRE_RL_cap0_wci_cfrd || WILL_FIRE_RL_cap0_wci_cfwr ||
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start ;
assign cap0_wci_wslv_reqF_r_clr$whas = 1'b0 ;
assign cap0_wci_wslv_respF_enqueueing$whas =
WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] != 12'h800 &&
cap0_wci_wslv_reqF$D_OUT[63:52] != 12'h400 ||
WILL_FIRE_RL_cap0_advance_split_response ||
WILL_FIRE_RL_cap0_wci_cfwr ||
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete ;
assign cap0_wci_wslv_respF_dequeueing$whas =
cap0_wci_wslv_respF_c_r != 2'd0 ;
assign cap0_wci_wslv_sThreadBusy_pw$whas = 1'b0 ;
assign cap0_wci_wslv_wci_cfwr_pw$whas =
cap0_wci_wslv_reqF$EMPTY_N && cap0_wci_wslv_reqF$D_OUT[68] &&
cap0_wci_wslv_reqF$D_OUT[71:69] == 3'd1 ;
assign cap0_wci_wslv_wci_cfrd_pw$whas =
cap0_wci_wslv_reqF$EMPTY_N && cap0_wci_wslv_reqF$D_OUT[68] &&
cap0_wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign cap0_wci_wslv_wci_ctrl_pw$whas =
cap0_wci_wslv_reqF$EMPTY_N && !cap0_wci_wslv_reqF$D_OUT[68] &&
cap0_wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign cap0_wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_cap0_wsiS_reqFifo_enq ;
assign cap0_wsiS_reqFifo_r_deq$whas = WILL_FIRE_RL_cap0_doMessageAccept ;
assign cap0_wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign cap0_wsiS_reqFifo_doResetEnq$whas =
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq ;
assign cap0_wsiS_reqFifo_doResetDeq$whas =
WILL_FIRE_RL_cap0_doMessageAccept ;
assign cap0_wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign cap0_dataBram_serverAdapterA_outData_deqCalled$whas = 1'b0 ;
assign cap0_dataBram_serverAdapterB_outData_deqCalled$whas =
WILL_FIRE_RL_cap0_advance_split_response &&
cap0_splaF$D_OUT[2] &&
cap0_splaF$D_OUT[1:0] == 2'd0 ;
assign cap0_metaBram_serverAdapterA_outData_deqCalled$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterB_outData_deqCalled$whas =
WILL_FIRE_RL_cap0_advance_split_response &&
!cap0_splaF$D_OUT[2] &&
cap0_splaF$D_OUT[1:0] == 2'd0 ;
assign cap0_metaBram_serverAdapterA_1_outData_deqCalled$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterB_1_outData_deqCalled$whas =
WILL_FIRE_RL_cap0_advance_split_response &&
!cap0_splaF$D_OUT[2] &&
cap0_splaF$D_OUT[1:0] == 2'd1 ;
assign cap0_metaBram_serverAdapterA_2_outData_deqCalled$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterB_2_outData_deqCalled$whas =
WILL_FIRE_RL_cap0_advance_split_response &&
!cap0_splaF$D_OUT[2] &&
cap0_splaF$D_OUT[1:0] == 2'd2 ;
assign cap0_metaBram_serverAdapterA_3_outData_deqCalled$whas = 1'b0 ;
assign cap0_metaBram_serverAdapterB_3_outData_deqCalled$whas =
WILL_FIRE_RL_cap0_advance_split_response &&
!cap0_splaF$D_OUT[2] &&
cap0_splaF$D_OUT[1:0] == 2'd3 ;
assign cap0_wsi_Es_mReqLast_w$whas = gbe0$wsiM0_MReqLast ;
assign cap0_wsi_Es_mBurstPrecise_w$whas = gbe0$wsiM0_MBurstPrecise ;
assign cap0_wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign infLed$wget = ctop$led ;
assign blinkLed$wget = freeCnt[25] ;
assign cap0_wsiS_extStatusW$wget =
{ cap0_wsiS_pMesgCount,
cap0_wsiS_iMesgCount,
cap0_wsiS_tBusyCount } ;
// register cap0_controlReg
assign cap0_controlReg$D_IN =
MUX_cap0_controlReg$write_1__SEL_1 ?
cap0_wci_wslv_reqF$D_OUT[31:0] :
32'd0 ;
assign cap0_controlReg$EN =
WILL_FIRE_RL_cap0_wci_cfwr &&
cap0_wci_wslv_reqF$D_OUT[39:32] == 8'h0 ||
WILL_FIRE_RL_cap0_wci_ctrl_EiI ;
// register cap0_dataBram_serverAdapterA_cnt
assign cap0_dataBram_serverAdapterA_cnt$D_IN =
cap0_dataBram_serverAdapterA_cnt + 3'd0 + 3'd0 ;
assign cap0_dataBram_serverAdapterA_cnt$EN = 1'b0 ;
// register cap0_dataBram_serverAdapterA_s1
assign cap0_dataBram_serverAdapterA_s1$D_IN =
{ MUX_cap0_dataCount$write_1__SEL_2, 1'b0 } ;
assign cap0_dataBram_serverAdapterA_s1$EN = 1'd1 ;
// register cap0_dataBram_serverAdapterB_cnt
assign cap0_dataBram_serverAdapterB_cnt$D_IN =
cap0_dataBram_serverAdapterB_cnt_51_PLUS_IF_ca_ETC___d457 ;
assign cap0_dataBram_serverAdapterB_cnt$EN =
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways ||
cap0_dataBram_serverAdapterB_outData_deqCalled$whas ;
// register cap0_dataBram_serverAdapterB_s1
assign cap0_dataBram_serverAdapterB_s1$D_IN =
{ WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways,
1'b1 } ;
assign cap0_dataBram_serverAdapterB_s1$EN = 1'd1 ;
// register cap0_dataCount
always@(MUX_cap0_dataCount$write_1__SEL_1 or
cap0_wci_wslv_reqF$D_OUT or
MUX_cap0_dataCount$write_1__SEL_2 or
MUX_cap0_dataCount$write_1__VAL_2 or WILL_FIRE_RL_cap0_wci_ctrl_EiI)
case (1'b1)
MUX_cap0_dataCount$write_1__SEL_1:
cap0_dataCount$D_IN = cap0_wci_wslv_reqF$D_OUT[31:0];
MUX_cap0_dataCount$write_1__SEL_2:
cap0_dataCount$D_IN = MUX_cap0_dataCount$write_1__VAL_2;
WILL_FIRE_RL_cap0_wci_ctrl_EiI: cap0_dataCount$D_IN = 32'd0;
default: cap0_dataCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign cap0_dataCount$EN =
WILL_FIRE_RL_cap0_doMessageAccept &&
cap0_controlReg_60_BIT_0_61_AND_NOT_cap0_contr_ETC___d1008 ||
WILL_FIRE_RL_cap0_wci_cfwr &&
cap0_wci_wslv_reqF$D_OUT[39:32] == 8'h08 ||
WILL_FIRE_RL_cap0_wci_ctrl_EiI ;
// register cap0_isFirst
assign cap0_isFirst$D_IN = 1'b0 ;
assign cap0_isFirst$EN = 1'b0 ;
// register cap0_mesgLengthSoFar
assign cap0_mesgLengthSoFar$D_IN =
cap0_wsiS_reqFifo$D_OUT[57] ? 14'd0 : mlB__h34434 ;
assign cap0_mesgLengthSoFar$EN = WILL_FIRE_RL_cap0_doMessageAccept ;
// register cap0_metaBram_serverAdapterA_1_cnt
assign cap0_metaBram_serverAdapterA_1_cnt$D_IN =
cap0_metaBram_serverAdapterA_1_cnt + 3'd0 + 3'd0 ;
assign cap0_metaBram_serverAdapterA_1_cnt$EN = 1'b0 ;
// register cap0_metaBram_serverAdapterA_1_s1
assign cap0_metaBram_serverAdapterA_1_s1$D_IN =
{ MUX_cap0_metaCount$write_1__SEL_2, 1'b0 } ;
assign cap0_metaBram_serverAdapterA_1_s1$EN = 1'd1 ;
// register cap0_metaBram_serverAdapterA_2_cnt
assign cap0_metaBram_serverAdapterA_2_cnt$D_IN =
cap0_metaBram_serverAdapterA_2_cnt + 3'd0 + 3'd0 ;
assign cap0_metaBram_serverAdapterA_2_cnt$EN = 1'b0 ;
// register cap0_metaBram_serverAdapterA_2_s1
assign cap0_metaBram_serverAdapterA_2_s1$D_IN =
{ MUX_cap0_metaCount$write_1__SEL_2, 1'b0 } ;
assign cap0_metaBram_serverAdapterA_2_s1$EN = 1'd1 ;
// register cap0_metaBram_serverAdapterA_3_cnt
assign cap0_metaBram_serverAdapterA_3_cnt$D_IN =
cap0_metaBram_serverAdapterA_3_cnt + 3'd0 + 3'd0 ;
assign cap0_metaBram_serverAdapterA_3_cnt$EN = 1'b0 ;
// register cap0_metaBram_serverAdapterA_3_s1
assign cap0_metaBram_serverAdapterA_3_s1$D_IN =
{ MUX_cap0_metaCount$write_1__SEL_2, 1'b0 } ;
assign cap0_metaBram_serverAdapterA_3_s1$EN = 1'd1 ;
// register cap0_metaBram_serverAdapterA_cnt
assign cap0_metaBram_serverAdapterA_cnt$D_IN =
cap0_metaBram_serverAdapterA_cnt + 3'd0 + 3'd0 ;
assign cap0_metaBram_serverAdapterA_cnt$EN = 1'b0 ;
// register cap0_metaBram_serverAdapterA_s1
assign cap0_metaBram_serverAdapterA_s1$D_IN =
{ MUX_cap0_metaCount$write_1__SEL_2, 1'b0 } ;
assign cap0_metaBram_serverAdapterA_s1$EN = 1'd1 ;
// register cap0_metaBram_serverAdapterB_1_cnt
assign cap0_metaBram_serverAdapterB_1_cnt$D_IN =
cap0_metaBram_serverAdapterB_1_cnt_87_PLUS_IF__ETC___d693 ;
assign cap0_metaBram_serverAdapterB_1_cnt$EN =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways ||
cap0_metaBram_serverAdapterB_1_outData_deqCalled$whas ;
// register cap0_metaBram_serverAdapterB_1_s1
assign cap0_metaBram_serverAdapterB_1_s1$D_IN =
{ WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways,
1'b1 } ;
assign cap0_metaBram_serverAdapterB_1_s1$EN = 1'd1 ;
// register cap0_metaBram_serverAdapterB_2_cnt
assign cap0_metaBram_serverAdapterB_2_cnt$D_IN =
cap0_metaBram_serverAdapterB_2_cnt_05_PLUS_IF__ETC___d811 ;
assign cap0_metaBram_serverAdapterB_2_cnt$EN =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways ||
cap0_metaBram_serverAdapterB_2_outData_deqCalled$whas ;
// register cap0_metaBram_serverAdapterB_2_s1
assign cap0_metaBram_serverAdapterB_2_s1$D_IN =
{ WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways,
1'b1 } ;
assign cap0_metaBram_serverAdapterB_2_s1$EN = 1'd1 ;
// register cap0_metaBram_serverAdapterB_3_cnt
assign cap0_metaBram_serverAdapterB_3_cnt$D_IN =
cap0_metaBram_serverAdapterB_3_cnt_23_PLUS_IF__ETC___d929 ;
assign cap0_metaBram_serverAdapterB_3_cnt$EN =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways ||
cap0_metaBram_serverAdapterB_3_outData_deqCalled$whas ;
// register cap0_metaBram_serverAdapterB_3_s1
assign cap0_metaBram_serverAdapterB_3_s1$D_IN =
{ WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways,
1'b1 } ;
assign cap0_metaBram_serverAdapterB_3_s1$EN = 1'd1 ;
// register cap0_metaBram_serverAdapterB_cnt
assign cap0_metaBram_serverAdapterB_cnt$D_IN =
cap0_metaBram_serverAdapterB_cnt_69_PLUS_IF_ca_ETC___d575 ;
assign cap0_metaBram_serverAdapterB_cnt$EN =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways ||
cap0_metaBram_serverAdapterB_outData_deqCalled$whas ;
// register cap0_metaBram_serverAdapterB_s1
assign cap0_metaBram_serverAdapterB_s1$D_IN =
{ WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways,
1'b1 } ;
assign cap0_metaBram_serverAdapterB_s1$EN = 1'd1 ;
// register cap0_metaCount
always@(MUX_cap0_metaCount$write_1__SEL_1 or
cap0_wci_wslv_reqF$D_OUT or
MUX_cap0_metaCount$write_1__SEL_2 or
MUX_cap0_metaCount$write_1__VAL_2 or WILL_FIRE_RL_cap0_wci_ctrl_EiI)
case (1'b1)
MUX_cap0_metaCount$write_1__SEL_1:
cap0_metaCount$D_IN = cap0_wci_wslv_reqF$D_OUT[31:0];
MUX_cap0_metaCount$write_1__SEL_2:
cap0_metaCount$D_IN = MUX_cap0_metaCount$write_1__VAL_2;
WILL_FIRE_RL_cap0_wci_ctrl_EiI: cap0_metaCount$D_IN = 32'd0;
default: cap0_metaCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign cap0_metaCount$EN =
WILL_FIRE_RL_cap0_doMessageAccept &&
cap0_controlReg_60_BIT_0_61_AND_NOT_cap0_contr_ETC___d1008 &&
cap0_wsiS_reqFifo$D_OUT[57] ||
WILL_FIRE_RL_cap0_wci_cfwr &&
cap0_wci_wslv_reqF$D_OUT[39:32] == 8'h04 ||
WILL_FIRE_RL_cap0_wci_ctrl_EiI ;
// register cap0_splitReadInFlight
assign cap0_splitReadInFlight$D_IN =
MUX_cap0_splitReadInFlight$write_1__SEL_1 ;
assign cap0_splitReadInFlight$EN =
WILL_FIRE_RL_cap0_wci_cfrd &&
(cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h800 ||
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h400) ||
WILL_FIRE_RL_cap0_advance_split_response ;
// register cap0_wci_wslv_cEdge
assign cap0_wci_wslv_cEdge$D_IN = cap0_wci_wslv_reqF$D_OUT[36:34] ;
assign cap0_wci_wslv_cEdge$EN = WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start ;
// register cap0_wci_wslv_cState
assign cap0_wci_wslv_cState$D_IN = cap0_wci_wslv_nState ;
assign cap0_wci_wslv_cState$EN =
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete &&
!cap0_wci_wslv_illegalEdge ;
// register cap0_wci_wslv_ctlAckReg
assign cap0_wci_wslv_ctlAckReg$D_IN = cap0_wci_wslv_ctlAckReg_1$whas ;
assign cap0_wci_wslv_ctlAckReg$EN = 1'd1 ;
// register cap0_wci_wslv_ctlOpActive
assign cap0_wci_wslv_ctlOpActive$D_IN =
!WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete ;
assign cap0_wci_wslv_ctlOpActive$EN =
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start ;
// register cap0_wci_wslv_illegalEdge
assign cap0_wci_wslv_illegalEdge$D_IN =
!MUX_cap0_wci_wslv_illegalEdge$write_1__SEL_1 &&
MUX_cap0_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign cap0_wci_wslv_illegalEdge$EN =
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete &&
cap0_wci_wslv_illegalEdge ||
MUX_cap0_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register cap0_wci_wslv_isReset_isInReset
assign cap0_wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
assign cap0_wci_wslv_isReset_isInReset$EN =
cap0_wci_wslv_isReset_isInReset ;
// register cap0_wci_wslv_nState
always@(cap0_wci_wslv_reqF$D_OUT)
begin
case (cap0_wci_wslv_reqF$D_OUT[36:34])
3'd0: cap0_wci_wslv_nState$D_IN = 3'd1;
3'd1: cap0_wci_wslv_nState$D_IN = 3'd2;
3'd2: cap0_wci_wslv_nState$D_IN = 3'd3;
default: cap0_wci_wslv_nState$D_IN = 3'd0;
endcase
end
assign cap0_wci_wslv_nState$EN =
WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start &&
(cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd0 &&
cap0_wci_wslv_cState == 3'd0 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
(cap0_wci_wslv_cState == 3'd1 ||
cap0_wci_wslv_cState == 3'd3) ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd2 &&
cap0_wci_wslv_cState == 3'd2 ||
cap0_wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
(cap0_wci_wslv_cState == 3'd3 || cap0_wci_wslv_cState == 3'd2 ||
cap0_wci_wslv_cState == 3'd1)) ;
// register cap0_wci_wslv_reqF_countReg
assign cap0_wci_wslv_reqF_countReg$D_IN =
(cap0_wci_wslv_wciReq$wget[71:69] != 3'd0) ?
cap0_wci_wslv_reqF_countReg + 2'd1 :
cap0_wci_wslv_reqF_countReg - 2'd1 ;
assign cap0_wci_wslv_reqF_countReg$EN =
(cap0_wci_wslv_wciReq$wget[71:69] != 3'd0) !=
cap0_wci_wslv_reqF_r_deq$whas ;
// register cap0_wci_wslv_respF_c_r
assign cap0_wci_wslv_respF_c_r$D_IN =
WILL_FIRE_RL_cap0_wci_wslv_respF_incCtr ?
MUX_cap0_wci_wslv_respF_c_r$write_1__VAL_1 :
MUX_cap0_wci_wslv_respF_c_r$write_1__VAL_2 ;
assign cap0_wci_wslv_respF_c_r$EN =
WILL_FIRE_RL_cap0_wci_wslv_respF_incCtr ||
WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr ;
// register cap0_wci_wslv_respF_q_0
always@(WILL_FIRE_RL_cap0_wci_wslv_respF_both or
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_1 or
MUX_cap0_wci_wslv_respF_q_0$write_1__SEL_2 or
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr or cap0_wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_cap0_wci_wslv_respF_both:
cap0_wci_wslv_respF_q_0$D_IN =
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_1;
MUX_cap0_wci_wslv_respF_q_0$write_1__SEL_2:
cap0_wci_wslv_respF_q_0$D_IN =
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr:
cap0_wci_wslv_respF_q_0$D_IN = cap0_wci_wslv_respF_q_1;
default: cap0_wci_wslv_respF_q_0$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign cap0_wci_wslv_respF_q_0$EN =
WILL_FIRE_RL_cap0_wci_wslv_respF_both ||
WILL_FIRE_RL_cap0_wci_wslv_respF_incCtr &&
cap0_wci_wslv_respF_c_r == 2'd0 ||
WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr ;
// register cap0_wci_wslv_respF_q_1
always@(WILL_FIRE_RL_cap0_wci_wslv_respF_both or
MUX_cap0_wci_wslv_respF_q_1$write_1__VAL_1 or
MUX_cap0_wci_wslv_respF_q_1$write_1__SEL_2 or
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_cap0_wci_wslv_respF_both:
cap0_wci_wslv_respF_q_1$D_IN =
MUX_cap0_wci_wslv_respF_q_1$write_1__VAL_1;
MUX_cap0_wci_wslv_respF_q_1$write_1__SEL_2:
cap0_wci_wslv_respF_q_1$D_IN =
MUX_cap0_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr:
cap0_wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: cap0_wci_wslv_respF_q_1$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign cap0_wci_wslv_respF_q_1$EN =
WILL_FIRE_RL_cap0_wci_wslv_respF_both ||
WILL_FIRE_RL_cap0_wci_wslv_respF_incCtr &&
cap0_wci_wslv_respF_c_r == 2'd1 ||
WILL_FIRE_RL_cap0_wci_wslv_respF_decCtr ;
// register cap0_wci_wslv_sFlagReg
assign cap0_wci_wslv_sFlagReg$D_IN = 1'b0 ;
assign cap0_wci_wslv_sFlagReg$EN = 1'd1 ;
// register cap0_wci_wslv_sThreadBusy_d
assign cap0_wci_wslv_sThreadBusy_d$D_IN = 1'b0 ;
assign cap0_wci_wslv_sThreadBusy_d$EN = 1'd1 ;
// register cap0_wsiS_burstKind
assign cap0_wsiS_burstKind$D_IN =
(cap0_wsiS_burstKind == 2'd0) ?
(cap0_wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign cap0_wsiS_burstKind$EN =
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq &&
(cap0_wsiS_burstKind == 2'd0 ||
(cap0_wsiS_burstKind == 2'd1 || cap0_wsiS_burstKind == 2'd2) &&
cap0_wsiS_wsiReq$wget[57]) ;
// register cap0_wsiS_errorSticky
assign cap0_wsiS_errorSticky$D_IN = 1'b0 ;
assign cap0_wsiS_errorSticky$EN = 1'b0 ;
// register cap0_wsiS_iMesgCount
assign cap0_wsiS_iMesgCount$D_IN = cap0_wsiS_iMesgCount + 32'd1 ;
assign cap0_wsiS_iMesgCount$EN =
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq &&
cap0_wsiS_burstKind == 2'd2 &&
cap0_wsiS_wsiReq$wget[57] ;
// register cap0_wsiS_isReset_isInReset
assign cap0_wsiS_isReset_isInReset$D_IN = 1'd0 ;
assign cap0_wsiS_isReset_isInReset$EN = cap0_wsiS_isReset_isInReset ;
// register cap0_wsiS_mesgWordLength
assign cap0_wsiS_mesgWordLength$D_IN = cap0_wsiS_wordCount ;
assign cap0_wsiS_mesgWordLength$EN =
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq && cap0_wsiS_wsiReq$wget[57] ;
// register cap0_wsiS_operateD
assign cap0_wsiS_operateD$D_IN = cap0_wci_wslv_cState == 3'd2 ;
assign cap0_wsiS_operateD$EN = 1'd1 ;
// register cap0_wsiS_pMesgCount
assign cap0_wsiS_pMesgCount$D_IN = cap0_wsiS_pMesgCount + 32'd1 ;
assign cap0_wsiS_pMesgCount$EN =
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq &&
cap0_wsiS_burstKind == 2'd1 &&
cap0_wsiS_wsiReq$wget[57] ;
// register cap0_wsiS_peerIsReady
assign cap0_wsiS_peerIsReady$D_IN = gbe0$wsiM0_MReset_n ;
assign cap0_wsiS_peerIsReady$EN = 1'd1 ;
// register cap0_wsiS_reqFifo_countReg
assign cap0_wsiS_reqFifo_countReg$D_IN =
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq ?
cap0_wsiS_reqFifo_countReg + 2'd1 :
cap0_wsiS_reqFifo_countReg - 2'd1 ;
assign cap0_wsiS_reqFifo_countReg$EN =
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq !=
WILL_FIRE_RL_cap0_doMessageAccept ;
// register cap0_wsiS_reqFifo_levelsValid
assign cap0_wsiS_reqFifo_levelsValid$D_IN =
WILL_FIRE_RL_cap0_wsiS_reqFifo_reset ;
assign cap0_wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_cap0_doMessageAccept ||
WILL_FIRE_RL_cap0_wsiS_reqFifo_enq ||
WILL_FIRE_RL_cap0_wsiS_reqFifo_reset ;
// register cap0_wsiS_statusR
assign cap0_wsiS_statusR$D_IN =
{ cap0_wsiS_isReset_isInReset,
!cap0_wsiS_peerIsReady,
!cap0_wsiS_operateD,
cap0_wsiS_errorSticky,
cap0_wsiS_burstKind != 2'd0,
!cap0_wsiS_sThreadBusy_dw$whas ||
cap0_wsiS_sThreadBusy_dw$wget,
1'd0,
cap0_wsiS_trafficSticky } ;
assign cap0_wsiS_statusR$EN = 1'd1 ;
// register cap0_wsiS_tBusyCount
assign cap0_wsiS_tBusyCount$D_IN = cap0_wsiS_tBusyCount + 32'd1 ;
assign cap0_wsiS_tBusyCount$EN =
cap0_wsiS_operateD && cap0_wsiS_peerIsReady &&
(!cap0_wsiS_sThreadBusy_dw$whas ||
cap0_wsiS_sThreadBusy_dw$wget) ;
// register cap0_wsiS_trafficSticky
assign cap0_wsiS_trafficSticky$D_IN = 1'd1 ;
assign cap0_wsiS_trafficSticky$EN = WILL_FIRE_RL_cap0_wsiS_reqFifo_enq ;
// register cap0_wsiS_wordCount
assign cap0_wsiS_wordCount$D_IN =
cap0_wsiS_wsiReq$wget[57] ? 12'd1 : cap0_wsiS_wordCount + 12'd1 ;
assign cap0_wsiS_wordCount$EN = WILL_FIRE_RL_cap0_wsiS_reqFifo_enq ;
// register cap0_wtiS_isReset_isInReset
assign cap0_wtiS_isReset_isInReset$D_IN = 1'd0 ;
assign cap0_wtiS_isReset_isInReset$EN = cap0_wtiS_isReset_isInReset ;
// register cap0_wtiS_nowReq
assign cap0_wtiS_nowReq$D_IN = 67'd0 ;
assign cap0_wtiS_nowReq$EN = 1'd1 ;
// register cap0_wtiS_operateD
assign cap0_wtiS_operateD$D_IN = 1'b1 ;
assign cap0_wtiS_operateD$EN = 1'd1 ;
// register freeCnt
assign freeCnt$D_IN = freeCnt + 32'd1 ;
assign freeCnt$EN = 1'd1 ;
// register needs_init
assign needs_init$D_IN = 1'd0 ;
assign needs_init$EN = needs_init ;
// register pciDevice
assign pciDevice$D_IN = pciw_pciDevice ;
assign pciDevice$EN = 1'd1 ;
// register pciw_pciDevice
assign pciw_pciDevice$D_IN =
{ pciw_pci0_pcie_ep$cfg_bus_number,
pciw_pci0_pcie_ep$cfg_device_number,
pciw_pci0_pcie_ep$cfg_function_number } ;
assign pciw_pciDevice$EN = 1'd1 ;
// submodule cap0_dataBram_memory
assign cap0_dataBram_memory$ADDRA = cap0_dataCount[9:0] ;
assign cap0_dataBram_memory$ADDRB = cap0_wci_wslv_reqF$D_OUT[43:34] ;
assign cap0_dataBram_memory$DIA = cap0_wsiS_reqFifo$D_OUT[43:12] ;
assign cap0_dataBram_memory$DIB = 32'd0 ;
assign cap0_dataBram_memory$WEA = 1'd1 ;
assign cap0_dataBram_memory$WEB = 1'd0 ;
assign cap0_dataBram_memory$ENA = MUX_cap0_dataCount$write_1__SEL_2 ;
assign cap0_dataBram_memory$ENB =
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways ;
// submodule cap0_dataBram_serverAdapterA_outDataCore
assign cap0_dataBram_serverAdapterA_outDataCore$D_IN =
cap0_dataBram_memory$DOA ;
assign cap0_dataBram_serverAdapterA_outDataCore$ENQ =
cap0_dataBram_serverAdapterA_outDataCore$FULL_N &&
cap0_dataBram_serverAdapterA_outData_enqData$whas ;
assign cap0_dataBram_serverAdapterA_outDataCore$DEQ = 1'b0 ;
assign cap0_dataBram_serverAdapterA_outDataCore$CLR = 1'b0 ;
// submodule cap0_dataBram_serverAdapterB_outDataCore
assign cap0_dataBram_serverAdapterB_outDataCore$D_IN =
cap0_dataBram_memory$DOB ;
assign cap0_dataBram_serverAdapterB_outDataCore$ENQ =
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_outData_enqAndDeq ||
cap0_dataBram_serverAdapterB_outDataCore$FULL_N &&
!cap0_dataBram_serverAdapterB_outData_deqCalled$whas &&
cap0_dataBram_serverAdapterB_outData_enqData$whas ;
assign cap0_dataBram_serverAdapterB_outDataCore$DEQ =
WILL_FIRE_RL_cap0_dataBram_serverAdapterB_outData_enqAndDeq ||
cap0_dataBram_serverAdapterB_outDataCore$EMPTY_N &&
cap0_dataBram_serverAdapterB_outData_deqCalled$whas &&
!cap0_dataBram_serverAdapterB_outData_enqData$whas ;
assign cap0_dataBram_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule cap0_metaBram_memory
assign cap0_metaBram_memory$ADDRA = cap0_metaCount[9:0] ;
assign cap0_metaBram_memory$ADDRB = cap0_wci_wslv_reqF$D_OUT[45:36] ;
assign cap0_metaBram_memory$DIA = { 18'd0, mlB__h34434 } ;
assign cap0_metaBram_memory$DIB = 32'd0 ;
assign cap0_metaBram_memory$WEA = 1'd1 ;
assign cap0_metaBram_memory$WEB = 1'd0 ;
assign cap0_metaBram_memory$ENA = MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_memory$ENB =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways ;
// submodule cap0_metaBram_memory_1
assign cap0_metaBram_memory_1$ADDRA = cap0_metaCount[9:0] ;
assign cap0_metaBram_memory_1$ADDRB = cap0_wci_wslv_reqF$D_OUT[45:36] ;
assign cap0_metaBram_memory_1$DIA =
{ 24'd0, cap0_wsiS_reqFifo$D_OUT[7:0] } ;
assign cap0_metaBram_memory_1$DIB = 32'd0 ;
assign cap0_metaBram_memory_1$WEA = 1'd1 ;
assign cap0_metaBram_memory_1$WEB = 1'd0 ;
assign cap0_metaBram_memory_1$ENA = MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_memory_1$ENB =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways ;
// submodule cap0_metaBram_memory_2
assign cap0_metaBram_memory_2$ADDRA = cap0_metaCount[9:0] ;
assign cap0_metaBram_memory_2$ADDRB = cap0_wci_wslv_reqF$D_OUT[45:36] ;
assign cap0_metaBram_memory_2$DIA = cap0_nowW$wget[63:32] ;
assign cap0_metaBram_memory_2$DIB = 32'd0 ;
assign cap0_metaBram_memory_2$WEA = 1'd1 ;
assign cap0_metaBram_memory_2$WEB = 1'd0 ;
assign cap0_metaBram_memory_2$ENA = MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_memory_2$ENB =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways ;
// submodule cap0_metaBram_memory_3
assign cap0_metaBram_memory_3$ADDRA = cap0_metaCount[9:0] ;
assign cap0_metaBram_memory_3$ADDRB = cap0_wci_wslv_reqF$D_OUT[45:36] ;
assign cap0_metaBram_memory_3$DIA = cap0_nowW$wget[31:0] ;
assign cap0_metaBram_memory_3$DIB = 32'd0 ;
assign cap0_metaBram_memory_3$WEA = 1'd1 ;
assign cap0_metaBram_memory_3$WEB = 1'd0 ;
assign cap0_metaBram_memory_3$ENA = MUX_cap0_metaCount$write_1__SEL_2 ;
assign cap0_metaBram_memory_3$ENB =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways ;
// submodule cap0_metaBram_serverAdapterA_1_outDataCore
assign cap0_metaBram_serverAdapterA_1_outDataCore$D_IN =
cap0_metaBram_memory_1$DOA ;
assign cap0_metaBram_serverAdapterA_1_outDataCore$ENQ =
cap0_metaBram_serverAdapterA_1_outDataCore$FULL_N &&
cap0_metaBram_serverAdapterA_1_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterA_1_outDataCore$DEQ = 1'b0 ;
assign cap0_metaBram_serverAdapterA_1_outDataCore$CLR = 1'b0 ;
// submodule cap0_metaBram_serverAdapterA_2_outDataCore
assign cap0_metaBram_serverAdapterA_2_outDataCore$D_IN =
cap0_metaBram_memory_2$DOA ;
assign cap0_metaBram_serverAdapterA_2_outDataCore$ENQ =
cap0_metaBram_serverAdapterA_2_outDataCore$FULL_N &&
cap0_metaBram_serverAdapterA_2_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterA_2_outDataCore$DEQ = 1'b0 ;
assign cap0_metaBram_serverAdapterA_2_outDataCore$CLR = 1'b0 ;
// submodule cap0_metaBram_serverAdapterA_3_outDataCore
assign cap0_metaBram_serverAdapterA_3_outDataCore$D_IN =
cap0_metaBram_memory_3$DOA ;
assign cap0_metaBram_serverAdapterA_3_outDataCore$ENQ =
cap0_metaBram_serverAdapterA_3_outDataCore$FULL_N &&
cap0_metaBram_serverAdapterA_3_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterA_3_outDataCore$DEQ = 1'b0 ;
assign cap0_metaBram_serverAdapterA_3_outDataCore$CLR = 1'b0 ;
// submodule cap0_metaBram_serverAdapterA_outDataCore
assign cap0_metaBram_serverAdapterA_outDataCore$D_IN =
cap0_metaBram_memory$DOA ;
assign cap0_metaBram_serverAdapterA_outDataCore$ENQ =
cap0_metaBram_serverAdapterA_outDataCore$FULL_N &&
cap0_metaBram_serverAdapterA_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterA_outDataCore$DEQ = 1'b0 ;
assign cap0_metaBram_serverAdapterA_outDataCore$CLR = 1'b0 ;
// submodule cap0_metaBram_serverAdapterB_1_outDataCore
assign cap0_metaBram_serverAdapterB_1_outDataCore$D_IN =
cap0_metaBram_memory_1$DOB ;
assign cap0_metaBram_serverAdapterB_1_outDataCore$ENQ =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_outData_enqAndDeq ||
cap0_metaBram_serverAdapterB_1_outDataCore$FULL_N &&
!cap0_metaBram_serverAdapterB_1_outData_deqCalled$whas &&
cap0_metaBram_serverAdapterB_1_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_1_outDataCore$DEQ =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_outData_enqAndDeq ||
cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_1_outData_deqCalled$whas &&
!cap0_metaBram_serverAdapterB_1_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_1_outDataCore$CLR = 1'b0 ;
// submodule cap0_metaBram_serverAdapterB_2_outDataCore
assign cap0_metaBram_serverAdapterB_2_outDataCore$D_IN =
cap0_metaBram_memory_2$DOB ;
assign cap0_metaBram_serverAdapterB_2_outDataCore$ENQ =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_outData_enqAndDeq ||
cap0_metaBram_serverAdapterB_2_outDataCore$FULL_N &&
!cap0_metaBram_serverAdapterB_2_outData_deqCalled$whas &&
cap0_metaBram_serverAdapterB_2_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_2_outDataCore$DEQ =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_outData_enqAndDeq ||
cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_2_outData_deqCalled$whas &&
!cap0_metaBram_serverAdapterB_2_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_2_outDataCore$CLR = 1'b0 ;
// submodule cap0_metaBram_serverAdapterB_3_outDataCore
assign cap0_metaBram_serverAdapterB_3_outDataCore$D_IN =
cap0_metaBram_memory_3$DOB ;
assign cap0_metaBram_serverAdapterB_3_outDataCore$ENQ =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_outData_enqAndDeq ||
cap0_metaBram_serverAdapterB_3_outDataCore$FULL_N &&
!cap0_metaBram_serverAdapterB_3_outData_deqCalled$whas &&
cap0_metaBram_serverAdapterB_3_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_3_outDataCore$DEQ =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_outData_enqAndDeq ||
cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_3_outData_deqCalled$whas &&
!cap0_metaBram_serverAdapterB_3_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_3_outDataCore$CLR = 1'b0 ;
// submodule cap0_metaBram_serverAdapterB_outDataCore
assign cap0_metaBram_serverAdapterB_outDataCore$D_IN =
cap0_metaBram_memory$DOB ;
assign cap0_metaBram_serverAdapterB_outDataCore$ENQ =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_outData_enqAndDeq ||
cap0_metaBram_serverAdapterB_outDataCore$FULL_N &&
!cap0_metaBram_serverAdapterB_outData_deqCalled$whas &&
cap0_metaBram_serverAdapterB_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_outDataCore$DEQ =
WILL_FIRE_RL_cap0_metaBram_serverAdapterB_outData_enqAndDeq ||
cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N &&
cap0_metaBram_serverAdapterB_outData_deqCalled$whas &&
!cap0_metaBram_serverAdapterB_outData_enqData$whas ;
assign cap0_metaBram_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule cap0_splaF
assign cap0_splaF$D_IN =
(cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h800) ?
3'd4 :
{ 1'd0, cap0_wci_wslv_reqF$D_OUT[35:34] } ;
assign cap0_splaF$ENQ = MUX_cap0_splitReadInFlight$write_1__SEL_1 ;
assign cap0_splaF$DEQ = WILL_FIRE_RL_cap0_advance_split_response ;
assign cap0_splaF$CLR = 1'b0 ;
// submodule cap0_wci_wslv_reqF
assign cap0_wci_wslv_reqF$D_IN = cap0_wci_wslv_wciReq$wget ;
assign cap0_wci_wslv_reqF$ENQ = cap0_wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign cap0_wci_wslv_reqF$DEQ = cap0_wci_wslv_reqF_r_deq$whas ;
assign cap0_wci_wslv_reqF$CLR = 1'b0 ;
// submodule cap0_wsiS_reqFifo
assign cap0_wsiS_reqFifo$D_IN = cap0_wsiS_wsiReq$wget ;
assign cap0_wsiS_reqFifo$ENQ = WILL_FIRE_RL_cap0_wsiS_reqFifo_enq ;
assign cap0_wsiS_reqFifo$DEQ = WILL_FIRE_RL_cap0_doMessageAccept ;
assign cap0_wsiS_reqFifo$CLR = 1'b0 ;
// submodule ctop
assign ctop$cpServer_request_put = 59'h0 ;
assign ctop$gps_ppsSyncIn_x = 1'b0 ;
assign ctop$server_request_put = pciw_fP2I$D_OUT ;
assign ctop$switch_x = 3'h0 ;
assign ctop$wci_m_0_SData = 32'h0 ;
assign ctop$wci_m_0_SFlag = 2'h0 ;
assign ctop$wci_m_0_SResp = 2'h0 ;
assign ctop$wci_m_1_SData = 32'h0 ;
assign ctop$wci_m_1_SFlag = 2'h0 ;
assign ctop$wci_m_1_SResp = 2'h0 ;
assign ctop$wci_m_2_SData = gbe0$wciS0_SData ;
assign ctop$wci_m_2_SFlag = gbe0$wciS0_SFlag ;
assign ctop$wci_m_2_SResp = gbe0$wciS0_SResp ;
assign ctop$wci_m_3_SData = cap0_wci_wslv_respF_q_0[31:0] ;
assign ctop$wci_m_3_SFlag = { 1'd1, cap0_wci_wslv_sFlagReg } ;
assign ctop$wci_m_3_SResp = cap0_wci_wslv_respF_q_0[33:32] ;
assign ctop$wci_m_4_SData = 32'h0 ;
assign ctop$wci_m_4_SFlag = 2'h0 ;
assign ctop$wci_m_4_SResp = 2'h0 ;
assign ctop$wmemiM0_SData = 128'h0 ;
assign ctop$wmemiM0_SResp = 2'h0 ;
assign ctop$wsi_s_adc_MBurstLength = 12'h0 ;
assign ctop$wsi_s_adc_MByteEn = 4'h0 ;
assign ctop$wsi_s_adc_MCmd = 3'h0 ;
assign ctop$wsi_s_adc_MData = 32'h0 ;
assign ctop$wsi_s_adc_MReqInfo = 8'h0 ;
assign ctop$EN_server_request_put =
ctop$RDY_server_request_put && pciw_fP2I$EMPTY_N ;
assign ctop$EN_server_response_get =
ctop$RDY_server_response_get && pciw_fI2P$FULL_N ;
assign ctop$EN_cpServer_request_put = 1'b0 ;
assign ctop$EN_cpServer_response_get = 1'b0 ;
assign ctop$wci_m_0_SThreadBusy = 1'b0 ;
assign ctop$wci_m_1_SThreadBusy = 1'b0 ;
assign ctop$wci_m_2_SThreadBusy = gbe0$wciS0_SThreadBusy ;
assign ctop$wci_m_3_SThreadBusy =
cap0_wci_wslv_reqF_countReg > 2'd1 ||
cap0_wci_wslv_isReset_isInReset ;
assign ctop$wci_m_4_SThreadBusy = 1'b0 ;
assign ctop$wsi_s_adc_MReqLast = 1'b0 ;
assign ctop$wsi_s_adc_MBurstPrecise = 1'b0 ;
assign ctop$wsi_s_adc_MReset_n = 1'b0 ;
assign ctop$wsi_m_dac_SThreadBusy = 1'b0 ;
assign ctop$wsi_m_dac_SReset_n = 1'b0 ;
assign ctop$wmemiM0_SRespLast = 1'b0 ;
assign ctop$wmemiM0_SCmdAccept = 1'b0 ;
assign ctop$wmemiM0_SDataAccept = 1'b0 ;
// submodule gbe0
assign gbe0$cpClient_response_put = 40'h0 ;
assign gbe0$gmii_col_i = gmii_col_i ;
assign gbe0$gmii_crs_i = gmii_crs_i ;
assign gbe0$gmii_intr_i = gmii_intr_i ;
assign gbe0$gmii_rx_rx_dv_i = gmii_rx_rx_dv_i ;
assign gbe0$gmii_rx_rx_er_i = gmii_rx_rx_er_i ;
assign gbe0$gmii_rx_rxd_i = gmii_rx_rxd_i ;
assign gbe0$wciS0_MAddr = ctop$wci_m_2_MAddr ;
assign gbe0$wciS0_MAddrSpace = ctop$wci_m_2_MAddrSpace ;
assign gbe0$wciS0_MByteEn = ctop$wci_m_2_MByteEn ;
assign gbe0$wciS0_MCmd = ctop$wci_m_2_MCmd ;
assign gbe0$wciS0_MData = ctop$wci_m_2_MData ;
assign gbe0$wciS0_MFlag = ctop$wci_m_2_MFlag ;
assign gbe0$wsiS0_MBurstLength = 12'h0 ;
assign gbe0$wsiS0_MByteEn = 4'h0 ;
assign gbe0$wsiS0_MCmd = 3'h0 ;
assign gbe0$wsiS0_MData = 32'h0 ;
assign gbe0$wsiS0_MReqInfo = 8'h0 ;
assign gbe0$wtiS0_req = 67'h0 ;
assign gbe0$wsiM0_SThreadBusy =
!cap0_wsiS_sThreadBusy_dw$whas || cap0_wsiS_sThreadBusy_dw$wget ;
assign gbe0$wsiM0_SReset_n =
!cap0_wsiS_isReset_isInReset && cap0_wsiS_operateD ;
assign gbe0$wsiS0_MReqLast = 1'b0 ;
assign gbe0$wsiS0_MBurstPrecise = 1'b0 ;
assign gbe0$wsiS0_MReset_n = 1'b0 ;
assign gbe0$EN_cpClient_request_get = 1'b0 ;
assign gbe0$EN_cpClient_response_put = 1'b0 ;
// submodule lcd_ctrl
assign lcd_ctrl$setLine1_text = 128'h202073656C75522063696D6F74412020 ;
assign lcd_ctrl$setLine2_text = 128'h20353037636B203A204950436E65704F ;
assign lcd_ctrl$EN_setLine1 = needs_init ;
assign lcd_ctrl$EN_setLine2 = needs_init ;
// submodule pciw_fI2P
assign pciw_fI2P$D_IN = ctop$server_response_get ;
assign pciw_fI2P$ENQ = ctop$RDY_server_response_get && pciw_fI2P$FULL_N ;
assign pciw_fI2P$DEQ = pciw_fI2P$EMPTY_N && pciw_pci0_txF$FULL_N ;
assign pciw_fI2P$CLR = 1'b0 ;
// submodule pciw_fP2I
assign pciw_fP2I$D_IN = pciw_pci0_rxF$D_OUT ;
assign pciw_fP2I$ENQ = pciw_pci0_rxF$EMPTY_N && pciw_fP2I$FULL_N ;
assign pciw_fP2I$DEQ = ctop$RDY_server_request_put && pciw_fP2I$EMPTY_N ;
assign pciw_fP2I$CLR = 1'b0 ;
// submodule pciw_pci0_pcie_ep
assign pciw_pci0_pcie_ep$PIPE_DCLK_IN = 1'b0 ;
assign pciw_pci0_pcie_ep$PIPE_MMCM_LOCK_IN = 1'b0 ;
assign pciw_pci0_pcie_ep$PIPE_OOBCLK_IN = 1'b0 ;
assign pciw_pci0_pcie_ep$PIPE_PCLK_IN = 1'b0 ;
assign pciw_pci0_pcie_ep$PIPE_RXOUTCLK_IN = 1'b0 ;
assign pciw_pci0_pcie_ep$PIPE_RXUSRCLK_IN = 4'h0 ;
assign pciw_pci0_pcie_ep$PIPE_USERCLK1_IN = 1'b0 ;
assign pciw_pci0_pcie_ep$PIPE_USERCLK2_IN = 1'b0 ;
assign pciw_pci0_pcie_ep$cfg_dsn = 64'h0 ;
assign pciw_pci0_pcie_ep$cfg_err_acs = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_aer_headerlog = 128'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_atomic_egress_blocked = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_cor = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_cpl_abort = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_cpl_timeout = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_cpl_unexpect = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_ecrc = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_internal_cor = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_internal_uncor = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_locked = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_malformed = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_mc_blocked = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_norecovery = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_poisoned = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_posted = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_tlp_cpl_header = 48'd0 ;
assign pciw_pci0_pcie_ep$cfg_err_ur = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_interrupt = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_interrupt_assert = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_interrupt_di = 8'd0 ;
assign pciw_pci0_pcie_ep$cfg_interrupt_stat = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_mgmt_byte_en = 4'd0 ;
assign pciw_pci0_pcie_ep$cfg_mgmt_di = 32'd0 ;
assign pciw_pci0_pcie_ep$cfg_mgmt_dwaddr = 10'd0 ;
assign pciw_pci0_pcie_ep$cfg_mgmt_rd_en = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_mgmt_wr_en = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_mgmt_wr_readonly = 1'd0 ;
assign pciw_pci0_pcie_ep$cfg_pciecap_interrupt_msgnum = 5'd0 ;
assign pciw_pci0_pcie_ep$cfg_pm_force_state = 2'h0 ;
assign pciw_pci0_pcie_ep$cfg_pm_force_state_en = 1'b0 ;
assign pciw_pci0_pcie_ep$cfg_pm_halt_aspm_l0s = 1'b0 ;
assign pciw_pci0_pcie_ep$cfg_pm_halt_aspm_l1 = 1'b0 ;
assign pciw_pci0_pcie_ep$cfg_pm_wake = 1'b0 ;
assign pciw_pci0_pcie_ep$cfg_trn_pending = 1'b0 ;
assign pciw_pci0_pcie_ep$cfg_turnoff_ok = 1'b0 ;
assign pciw_pci0_pcie_ep$fc_sel = 3'd0 ;
assign pciw_pci0_pcie_ep$m_axis_rx_tready = pciw_pci0_rxF$FULL_N ;
assign pciw_pci0_pcie_ep$pci_exp_rxn = pcie_rxn_i ;
assign pciw_pci0_pcie_ep$pci_exp_rxp = pcie_rxp_i ;
assign pciw_pci0_pcie_ep$pl_directed_link_auton = 1'd0 ;
assign pciw_pci0_pcie_ep$pl_directed_link_change = 2'd0 ;
assign pciw_pci0_pcie_ep$pl_directed_link_speed = 1'd0 ;
assign pciw_pci0_pcie_ep$pl_directed_link_width = 2'd0 ;
assign pciw_pci0_pcie_ep$pl_upstream_prefer_deemph = 1'b1 ;
assign pciw_pci0_pcie_ep$rx_np_ok = 1'd1 ;
assign pciw_pci0_pcie_ep$rx_np_req = 1'd1 ;
assign pciw_pci0_pcie_ep$s_axis_tx_tdata =
pciw_pci0_axiTxData$whas ? pciw_pci0_axiTxData$wget : 128'd0 ;
assign pciw_pci0_pcie_ep$s_axis_tx_tkeep =
pciw_pci0_axiTxData$whas ? pciw_pci0_axiTxKeep$wget : 16'd0 ;
assign pciw_pci0_pcie_ep$s_axis_tx_tlast =
pciw_pci0_axiTxData$whas && pciw_pci0_txF$D_OUT[151] ;
assign pciw_pci0_pcie_ep$s_axis_tx_tuser = 4'd0 ;
assign pciw_pci0_pcie_ep$s_axis_tx_tvalid = pciw_pci0_axiTxData$whas ;
assign pciw_pci0_pcie_ep$tx_cfg_gnt = 1'd1 ;
// submodule pciw_pci0_rxF
assign pciw_pci0_rxF$D_IN =
{ pciw_pci0_pcie_ep$m_axis_rx_tuser[14],
pciw_pci0_pcie_ep$m_axis_rx_tuser[21],
pciw_pci0_pcie_ep$m_axis_rx_tuser[8:2],
x_be__h1482,
x_data__h1483 } ;
assign pciw_pci0_rxF$ENQ =
pciw_pci0_rxF$FULL_N && pciw_pci0_pcie_ep$m_axis_rx_tvalid ;
assign pciw_pci0_rxF$DEQ = pciw_pci0_rxF$EMPTY_N && pciw_fP2I$FULL_N ;
assign pciw_pci0_rxF$CLR = 1'b0 ;
// submodule pciw_pci0_txF
assign pciw_pci0_txF$D_IN = pciw_fI2P$D_OUT ;
assign pciw_pci0_txF$ENQ = pciw_fI2P$EMPTY_N && pciw_pci0_txF$FULL_N ;
assign pciw_pci0_txF$DEQ = pciw_pci0_axiTxData$whas ;
assign pciw_pci0_txF$CLR = 1'b0 ;
// remaining internal signals
assign IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1057 =
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1048 &&
CASE_cap0_splaFD_OUT_BITS_1_TO_0_NOT_cap0_spl_ETC__q2 ;
assign IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291 =
pciw_pci0_pcie_ep$m_axis_rx_tuser[21] ?
CASE_pciw_pci0_pcie_epm_axis_rx_tuser_BITS_20_ETC__q1 :
16'd65535 ;
assign NOT_cap0_controlReg_60_BIT_0_61_62_OR_cap0_con_ETC___d986 =
!cap0_controlReg[0] ||
cap0_controlReg[1] &&
(!cap0_metaCount_64_ULT_1024___d1257 ||
!cap0_dataCount_67_ULT_1024___d1378) ||
(cap0_dataBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
(!cap0_wsiS_reqFifo$D_OUT[57] ||
(cap0_metaBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
(cap0_metaBram_serverAdapterA_1_cnt ^ 3'h4) < 3'd7 &&
(cap0_metaBram_serverAdapterA_2_cnt ^ 3'h4) < 3'd7 &&
(cap0_metaBram_serverAdapterA_3_cnt ^ 3'h4) < 3'd7) ;
assign cap0_controlReg_60_BIT_0_61_AND_NOT_cap0_contr_ETC___d1008 =
cap0_controlReg[0] &&
(!cap0_controlReg[1] ||
cap0_metaCount_64_ULT_1024___d1257 &&
cap0_dataCount_67_ULT_1024___d1378) ;
assign cap0_dataBram_serverAdapterB_cnt_51_PLUS_IF_ca_ETC___d457 =
cap0_dataBram_serverAdapterB_cnt +
(WILL_FIRE_RL_cap0_dataBram_serverAdapterB_stageReadResponseAlways ?
3'd1 :
3'd0) +
(cap0_dataBram_serverAdapterB_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign cap0_dataCount_67_ULT_1024___d1378 = cap0_dataCount < 32'd1024 ;
assign cap0_metaBram_serverAdapterB_1_cnt_87_PLUS_IF__ETC___d693 =
cap0_metaBram_serverAdapterB_1_cnt +
(WILL_FIRE_RL_cap0_metaBram_serverAdapterB_1_stageReadResponseAlways ?
3'd1 :
3'd0) +
(cap0_metaBram_serverAdapterB_1_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign cap0_metaBram_serverAdapterB_2_cnt_05_PLUS_IF__ETC___d811 =
cap0_metaBram_serverAdapterB_2_cnt +
(WILL_FIRE_RL_cap0_metaBram_serverAdapterB_2_stageReadResponseAlways ?
3'd1 :
3'd0) +
(cap0_metaBram_serverAdapterB_2_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign cap0_metaBram_serverAdapterB_3_cnt_23_PLUS_IF__ETC___d929 =
cap0_metaBram_serverAdapterB_3_cnt +
(WILL_FIRE_RL_cap0_metaBram_serverAdapterB_3_stageReadResponseAlways ?
3'd1 :
3'd0) +
(cap0_metaBram_serverAdapterB_3_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign cap0_metaBram_serverAdapterB_cnt_69_PLUS_IF_ca_ETC___d575 =
cap0_metaBram_serverAdapterB_cnt +
(WILL_FIRE_RL_cap0_metaBram_serverAdapterB_stageReadResponseAlways ?
3'd1 :
3'd0) +
(cap0_metaBram_serverAdapterB_outData_deqCalled$whas ?
3'd7 :
3'd0) ;
assign cap0_metaCount_64_ULT_1024___d1257 = cap0_metaCount < 32'd1024 ;
assign cap0_splaF_i_notEmpty__026_AND_IF_cap0_splaF_f_ETC___d1059 =
cap0_splaF$EMPTY_N &&
(cap0_splaF$D_OUT[2] ?
(cap0_splaF$D_OUT[1:0] != 2'd0 ||
cap0_dataBram_serverAdapterB_outDataCore$EMPTY_N ||
cap0_dataBram_serverAdapterB_outData_enqData$whas) &&
(cap0_splaF$D_OUT[1:0] != 2'd0 ||
cap0_dataBram_serverAdapterB_outData_outData$whas) :
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1057) ;
assign g_data__h39139 =
(cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h38064 : 32'd0 ;
assign mlB__h34434 = cap0_mesgLengthSoFar + mlInc__h34433 ;
assign mlInc__h34433 =
cap0_wsiS_reqFifo$D_OUT[57] ?
{ 11'd0, x__h34482 + y__h34483 } :
14'd4 ;
assign rdat___1__h38161 =
{ 6'd40,
!cap0_metaCount_64_ULT_1024___d1257,
!cap0_dataCount_67_ULT_1024___d1378,
24'd2361866 } ;
assign rdat___1__h38235 = { 24'd0, cap0_wsiS_statusR } ;
assign v__h36664 =
cap0_splaF$D_OUT[2] ?
y_avValue__h37291 :
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1081 ;
assign x__h34482 = x__h34494 + y__h34495 ;
assign x__h34494 = x__h34506 + y__h34507 ;
assign x__h34506 = { 2'd0, cap0_wsiS_reqFifo$D_OUT[11] } ;
assign x_be__h1482 =
{ IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[0],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[1],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[2],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[3],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[4],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[5],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[6],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[7],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[8],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[9],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[10],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[11],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[12],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[13],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[14],
IF_pciw_pci0_pcie_ep_axi_rx_tuser_BIT_21_THEN__ETC___d1291[15] } ;
assign x_data__h1483 =
{ pciw_pci0_pcie_ep$m_axis_rx_tdata[31:0],
pciw_pci0_pcie_ep$m_axis_rx_tdata[63:32],
pciw_pci0_pcie_ep$m_axis_rx_tdata[95:64],
pciw_pci0_pcie_ep$m_axis_rx_tdata[127:96] } ;
assign y__h34483 = { 2'd0, cap0_wsiS_reqFifo$D_OUT[8] } ;
assign y__h34495 = { 2'd0, cap0_wsiS_reqFifo$D_OUT[9] } ;
assign y__h34507 = { 2'd0, cap0_wsiS_reqFifo$D_OUT[10] } ;
assign y_avValue__h37291 =
cap0_dataBram_serverAdapterB_outDataCore$EMPTY_N ?
cap0_dataBram_serverAdapterB_outDataCore$D_OUT :
cap0_dataBram_memory$DOB ;
assign y_avValue__h37335 =
cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N ?
cap0_metaBram_serverAdapterB_outDataCore$D_OUT :
cap0_metaBram_memory$DOB ;
assign y_avValue__h37375 =
cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N ?
cap0_metaBram_serverAdapterB_1_outDataCore$D_OUT :
cap0_metaBram_memory_1$DOB ;
assign y_avValue__h37415 =
cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N ?
cap0_metaBram_serverAdapterB_2_outDataCore$D_OUT :
cap0_metaBram_memory_2$DOB ;
assign y_avValue__h37455 =
cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N ?
cap0_metaBram_serverAdapterB_3_outDataCore$D_OUT :
cap0_metaBram_memory_3$DOB ;
always@(cap0_wci_wslv_reqF$D_OUT or
cap0_metaBram_serverAdapterB_3_cnt or
cap0_metaBram_serverAdapterB_cnt or
cap0_metaBram_serverAdapterB_1_cnt or
cap0_metaBram_serverAdapterB_2_cnt)
begin
case (cap0_wci_wslv_reqF$D_OUT[35:34])
2'd0:
IF_cap0_wci_wslv_reqF_first__75_BITS_35_TO_34__ETC___d1124 =
(cap0_metaBram_serverAdapterB_cnt ^ 3'h4) < 3'd7;
2'd1:
IF_cap0_wci_wslv_reqF_first__75_BITS_35_TO_34__ETC___d1124 =
(cap0_metaBram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7;
2'd2:
IF_cap0_wci_wslv_reqF_first__75_BITS_35_TO_34__ETC___d1124 =
(cap0_metaBram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7;
2'd3:
IF_cap0_wci_wslv_reqF_first__75_BITS_35_TO_34__ETC___d1124 =
cap0_wci_wslv_reqF$D_OUT[35:34] != 2'd3 ||
(cap0_metaBram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7;
endcase
end
always@(cap0_wci_wslv_reqF$D_OUT or
cap0_splaF$FULL_N or
IF_cap0_wci_wslv_reqF_first__75_BITS_35_TO_34__ETC___d1124 or
cap0_dataBram_serverAdapterB_cnt)
begin
case (cap0_wci_wslv_reqF$D_OUT[63:52])
12'h0:
IF_cap0_wci_wslv_reqF_first__75_BITS_63_TO_52__ETC___d1128 = 1'b1;
12'h800:
IF_cap0_wci_wslv_reqF_first__75_BITS_63_TO_52__ETC___d1128 =
(cap0_dataBram_serverAdapterB_cnt ^ 3'h4) < 3'd7 &&
cap0_splaF$FULL_N;
default: IF_cap0_wci_wslv_reqF_first__75_BITS_63_TO_52__ETC___d1128 =
cap0_wci_wslv_reqF$D_OUT[63:52] != 12'h400 ||
cap0_splaF$FULL_N &&
IF_cap0_wci_wslv_reqF_first__75_BITS_35_TO_34__ETC___d1124;
endcase
end
always@(cap0_splaF$D_OUT or
y_avValue__h37455 or
y_avValue__h37335 or y_avValue__h37375 or y_avValue__h37415)
begin
case (cap0_splaF$D_OUT[1:0])
2'd0:
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1081 =
y_avValue__h37335;
2'd1:
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1081 =
y_avValue__h37375;
2'd2:
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1081 =
y_avValue__h37415;
2'd3:
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1081 =
y_avValue__h37455;
endcase
end
always@(pciw_pci0_pcie_ep$m_axis_rx_tuser)
begin
case (pciw_pci0_pcie_ep$m_axis_rx_tuser[20:19])
2'd0: CASE_pciw_pci0_pcie_epm_axis_rx_tuser_BITS_20_ETC__q1 = 16'h000F;
2'd1: CASE_pciw_pci0_pcie_epm_axis_rx_tuser_BITS_20_ETC__q1 = 16'h00FF;
2'd2: CASE_pciw_pci0_pcie_epm_axis_rx_tuser_BITS_20_ETC__q1 = 16'h0FFF;
2'd3: CASE_pciw_pci0_pcie_epm_axis_rx_tuser_BITS_20_ETC__q1 = 16'hFFFF;
endcase
end
always@(cap0_wci_wslv_reqF$D_OUT or
cap0_controlReg or
cap0_metaCount or
cap0_dataCount or
rdat___1__h38161 or rdat___1__h38235 or cap0_wsiS_extStatusW$wget)
begin
case (cap0_wci_wslv_reqF$D_OUT[39:32])
8'h0: v__h38064 = cap0_controlReg;
8'h04: v__h38064 = cap0_metaCount;
8'h08: v__h38064 = cap0_dataCount;
8'h0C: v__h38064 = rdat___1__h38161;
8'h10: v__h38064 = rdat___1__h38235;
8'h14: v__h38064 = cap0_wsiS_extStatusW$wget[95:64];
8'h18: v__h38064 = cap0_wsiS_extStatusW$wget[63:32];
8'h1C: v__h38064 = cap0_wsiS_extStatusW$wget[31:0];
default: v__h38064 = 32'd0;
endcase
end
always@(cap0_splaF$D_OUT or
cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N or
cap0_metaBram_serverAdapterB_3_outData_enqData$whas or
cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N or
cap0_metaBram_serverAdapterB_outData_enqData$whas or
cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N or
cap0_metaBram_serverAdapterB_1_outData_enqData$whas or
cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N or
cap0_metaBram_serverAdapterB_2_outData_enqData$whas)
begin
case (cap0_splaF$D_OUT[1:0])
2'd0:
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1048 =
cap0_metaBram_serverAdapterB_outDataCore$EMPTY_N ||
cap0_metaBram_serverAdapterB_outData_enqData$whas;
2'd1:
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1048 =
cap0_metaBram_serverAdapterB_1_outDataCore$EMPTY_N ||
cap0_metaBram_serverAdapterB_1_outData_enqData$whas;
2'd2:
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1048 =
cap0_metaBram_serverAdapterB_2_outDataCore$EMPTY_N ||
cap0_metaBram_serverAdapterB_2_outData_enqData$whas;
2'd3:
IF_cap0_splaF_first__027_BITS_1_TO_0_029_EQ_0__ETC___d1048 =
cap0_splaF$D_OUT[1:0] != 2'd3 ||
cap0_metaBram_serverAdapterB_3_outDataCore$EMPTY_N ||
cap0_metaBram_serverAdapterB_3_outData_enqData$whas;
endcase
end
always@(cap0_splaF$D_OUT or
cap0_metaBram_serverAdapterB_3_outData_outData$whas or
cap0_metaBram_serverAdapterB_outData_outData$whas or
cap0_metaBram_serverAdapterB_1_outData_outData$whas or
cap0_metaBram_serverAdapterB_2_outData_outData$whas)
begin
case (cap0_splaF$D_OUT[1:0])
2'd0:
CASE_cap0_splaFD_OUT_BITS_1_TO_0_NOT_cap0_spl_ETC__q2 =
cap0_metaBram_serverAdapterB_outData_outData$whas;
2'd1:
CASE_cap0_splaFD_OUT_BITS_1_TO_0_NOT_cap0_spl_ETC__q2 =
cap0_metaBram_serverAdapterB_1_outData_outData$whas;
2'd2:
CASE_cap0_splaFD_OUT_BITS_1_TO_0_NOT_cap0_spl_ETC__q2 =
cap0_metaBram_serverAdapterB_2_outData_outData$whas;
2'd3:
CASE_cap0_splaFD_OUT_BITS_1_TO_0_NOT_cap0_spl_ETC__q2 =
cap0_splaF$D_OUT[1:0] != 2'd3 ||
cap0_metaBram_serverAdapterB_3_outData_outData$whas;
endcase
end
// handling of inlined registers
always@(posedge sys0_clk$O)
begin
if (sys0_rst$OUT_RST == `BSV_RESET_VALUE)
begin
needs_init <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (needs_init$EN)
needs_init <= `BSV_ASSIGNMENT_DELAY needs_init$D_IN;
end
end
always@(posedge pciw_pci0_pcie_ep$user_clk_out)
begin
if (ctop$RST_N_wci_m_3 == `BSV_RESET_VALUE)
begin
cap0_dataBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_dataBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_dataBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_dataBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_isFirst <= `BSV_ASSIGNMENT_DELAY 1'd1;
cap0_mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0;
cap0_metaBram_serverAdapterA_1_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_metaBram_serverAdapterA_1_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_metaBram_serverAdapterA_2_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_metaBram_serverAdapterA_2_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_metaBram_serverAdapterA_3_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_metaBram_serverAdapterA_3_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_metaBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_metaBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_metaBram_serverAdapterB_1_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_metaBram_serverAdapterB_1_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_metaBram_serverAdapterB_2_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_metaBram_serverAdapterB_2_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_metaBram_serverAdapterB_3_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_metaBram_serverAdapterB_3_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_metaBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_metaBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
cap0_wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
cap0_wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
cap0_wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
cap0_wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
cap0_wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
cap0_wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
cap0_wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
cap0_wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
cap0_wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
cap0_wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
cap0_wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
cap0_wtiS_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
cap0_wtiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (cap0_dataBram_serverAdapterA_cnt$EN)
cap0_dataBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_dataBram_serverAdapterA_cnt$D_IN;
if (cap0_dataBram_serverAdapterA_s1$EN)
cap0_dataBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_dataBram_serverAdapterA_s1$D_IN;
if (cap0_dataBram_serverAdapterB_cnt$EN)
cap0_dataBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_dataBram_serverAdapterB_cnt$D_IN;
if (cap0_dataBram_serverAdapterB_s1$EN)
cap0_dataBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_dataBram_serverAdapterB_s1$D_IN;
if (cap0_isFirst$EN)
cap0_isFirst <= `BSV_ASSIGNMENT_DELAY cap0_isFirst$D_IN;
if (cap0_mesgLengthSoFar$EN)
cap0_mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY
cap0_mesgLengthSoFar$D_IN;
if (cap0_metaBram_serverAdapterA_1_cnt$EN)
cap0_metaBram_serverAdapterA_1_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterA_1_cnt$D_IN;
if (cap0_metaBram_serverAdapterA_1_s1$EN)
cap0_metaBram_serverAdapterA_1_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterA_1_s1$D_IN;
if (cap0_metaBram_serverAdapterA_2_cnt$EN)
cap0_metaBram_serverAdapterA_2_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterA_2_cnt$D_IN;
if (cap0_metaBram_serverAdapterA_2_s1$EN)
cap0_metaBram_serverAdapterA_2_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterA_2_s1$D_IN;
if (cap0_metaBram_serverAdapterA_3_cnt$EN)
cap0_metaBram_serverAdapterA_3_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterA_3_cnt$D_IN;
if (cap0_metaBram_serverAdapterA_3_s1$EN)
cap0_metaBram_serverAdapterA_3_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterA_3_s1$D_IN;
if (cap0_metaBram_serverAdapterA_cnt$EN)
cap0_metaBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterA_cnt$D_IN;
if (cap0_metaBram_serverAdapterA_s1$EN)
cap0_metaBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterA_s1$D_IN;
if (cap0_metaBram_serverAdapterB_1_cnt$EN)
cap0_metaBram_serverAdapterB_1_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterB_1_cnt$D_IN;
if (cap0_metaBram_serverAdapterB_1_s1$EN)
cap0_metaBram_serverAdapterB_1_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterB_1_s1$D_IN;
if (cap0_metaBram_serverAdapterB_2_cnt$EN)
cap0_metaBram_serverAdapterB_2_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterB_2_cnt$D_IN;
if (cap0_metaBram_serverAdapterB_2_s1$EN)
cap0_metaBram_serverAdapterB_2_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterB_2_s1$D_IN;
if (cap0_metaBram_serverAdapterB_3_cnt$EN)
cap0_metaBram_serverAdapterB_3_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterB_3_cnt$D_IN;
if (cap0_metaBram_serverAdapterB_3_s1$EN)
cap0_metaBram_serverAdapterB_3_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterB_3_s1$D_IN;
if (cap0_metaBram_serverAdapterB_cnt$EN)
cap0_metaBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterB_cnt$D_IN;
if (cap0_metaBram_serverAdapterB_s1$EN)
cap0_metaBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
cap0_metaBram_serverAdapterB_s1$D_IN;
if (cap0_splitReadInFlight$EN)
cap0_splitReadInFlight <= `BSV_ASSIGNMENT_DELAY
cap0_splitReadInFlight$D_IN;
if (cap0_wci_wslv_cEdge$EN)
cap0_wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_cEdge$D_IN;
if (cap0_wci_wslv_cState$EN)
cap0_wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_cState$D_IN;
if (cap0_wci_wslv_ctlAckReg$EN)
cap0_wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_ctlAckReg$D_IN;
if (cap0_wci_wslv_ctlOpActive$EN)
cap0_wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_ctlOpActive$D_IN;
if (cap0_wci_wslv_illegalEdge$EN)
cap0_wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_illegalEdge$D_IN;
if (cap0_wci_wslv_nState$EN)
cap0_wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_nState$D_IN;
if (cap0_wci_wslv_reqF_countReg$EN)
cap0_wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_reqF_countReg$D_IN;
if (cap0_wci_wslv_respF_c_r$EN)
cap0_wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_respF_c_r$D_IN;
if (cap0_wci_wslv_respF_q_0$EN)
cap0_wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_respF_q_0$D_IN;
if (cap0_wci_wslv_respF_q_1$EN)
cap0_wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_respF_q_1$D_IN;
if (cap0_wci_wslv_sFlagReg$EN)
cap0_wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_sFlagReg$D_IN;
if (cap0_wci_wslv_sThreadBusy_d$EN)
cap0_wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_sThreadBusy_d$D_IN;
if (cap0_wsiS_burstKind$EN)
cap0_wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_burstKind$D_IN;
if (cap0_wsiS_errorSticky$EN)
cap0_wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_errorSticky$D_IN;
if (cap0_wsiS_iMesgCount$EN)
cap0_wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_iMesgCount$D_IN;
if (cap0_wsiS_operateD$EN)
cap0_wsiS_operateD <= `BSV_ASSIGNMENT_DELAY cap0_wsiS_operateD$D_IN;
if (cap0_wsiS_pMesgCount$EN)
cap0_wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_pMesgCount$D_IN;
if (cap0_wsiS_peerIsReady$EN)
cap0_wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_peerIsReady$D_IN;
if (cap0_wsiS_reqFifo_countReg$EN)
cap0_wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_reqFifo_countReg$D_IN;
if (cap0_wsiS_reqFifo_levelsValid$EN)
cap0_wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_reqFifo_levelsValid$D_IN;
if (cap0_wsiS_tBusyCount$EN)
cap0_wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_tBusyCount$D_IN;
if (cap0_wsiS_trafficSticky$EN)
cap0_wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_trafficSticky$D_IN;
if (cap0_wsiS_wordCount$EN)
cap0_wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_wordCount$D_IN;
if (cap0_wtiS_nowReq$EN)
cap0_wtiS_nowReq <= `BSV_ASSIGNMENT_DELAY cap0_wtiS_nowReq$D_IN;
if (cap0_wtiS_operateD$EN)
cap0_wtiS_operateD <= `BSV_ASSIGNMENT_DELAY cap0_wtiS_operateD$D_IN;
end
if (pciw_p125rst$OUT_RST == `BSV_RESET_VALUE)
begin
freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
pciDevice <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pciDevice <= `BSV_ASSIGNMENT_DELAY 16'd0;
end
else
begin
if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN;
if (pciDevice$EN) pciDevice <= `BSV_ASSIGNMENT_DELAY pciDevice$D_IN;
if (pciw_pciDevice$EN)
pciw_pciDevice <= `BSV_ASSIGNMENT_DELAY pciw_pciDevice$D_IN;
end
if (cap0_controlReg$EN)
cap0_controlReg <= `BSV_ASSIGNMENT_DELAY cap0_controlReg$D_IN;
if (cap0_dataCount$EN)
cap0_dataCount <= `BSV_ASSIGNMENT_DELAY cap0_dataCount$D_IN;
if (cap0_metaCount$EN)
cap0_metaCount <= `BSV_ASSIGNMENT_DELAY cap0_metaCount$D_IN;
if (cap0_wsiS_mesgWordLength$EN)
cap0_wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_mesgWordLength$D_IN;
if (cap0_wsiS_statusR$EN)
cap0_wsiS_statusR <= `BSV_ASSIGNMENT_DELAY cap0_wsiS_statusR$D_IN;
end
always@(posedge pciw_pci0_pcie_ep$user_clk_out or
`BSV_RESET_EDGE ctop$RST_N_wci_m_3)
if (ctop$RST_N_wci_m_3 == `BSV_RESET_VALUE)
begin
cap0_wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
cap0_wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
cap0_wtiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (cap0_wci_wslv_isReset_isInReset$EN)
cap0_wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
cap0_wci_wslv_isReset_isInReset$D_IN;
if (cap0_wsiS_isReset_isInReset$EN)
cap0_wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
cap0_wsiS_isReset_isInReset$D_IN;
if (cap0_wtiS_isReset_isInReset$EN)
cap0_wtiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
cap0_wtiS_isReset_isInReset$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cap0_controlReg = 32'hAAAAAAAA;
cap0_dataBram_serverAdapterA_cnt = 3'h2;
cap0_dataBram_serverAdapterA_s1 = 2'h2;
cap0_dataBram_serverAdapterB_cnt = 3'h2;
cap0_dataBram_serverAdapterB_s1 = 2'h2;
cap0_dataCount = 32'hAAAAAAAA;
cap0_isFirst = 1'h0;
cap0_mesgLengthSoFar = 14'h2AAA;
cap0_metaBram_serverAdapterA_1_cnt = 3'h2;
cap0_metaBram_serverAdapterA_1_s1 = 2'h2;
cap0_metaBram_serverAdapterA_2_cnt = 3'h2;
cap0_metaBram_serverAdapterA_2_s1 = 2'h2;
cap0_metaBram_serverAdapterA_3_cnt = 3'h2;
cap0_metaBram_serverAdapterA_3_s1 = 2'h2;
cap0_metaBram_serverAdapterA_cnt = 3'h2;
cap0_metaBram_serverAdapterA_s1 = 2'h2;
cap0_metaBram_serverAdapterB_1_cnt = 3'h2;
cap0_metaBram_serverAdapterB_1_s1 = 2'h2;
cap0_metaBram_serverAdapterB_2_cnt = 3'h2;
cap0_metaBram_serverAdapterB_2_s1 = 2'h2;
cap0_metaBram_serverAdapterB_3_cnt = 3'h2;
cap0_metaBram_serverAdapterB_3_s1 = 2'h2;
cap0_metaBram_serverAdapterB_cnt = 3'h2;
cap0_metaBram_serverAdapterB_s1 = 2'h2;
cap0_metaCount = 32'hAAAAAAAA;
cap0_splitReadInFlight = 1'h0;
cap0_wci_wslv_cEdge = 3'h2;
cap0_wci_wslv_cState = 3'h2;
cap0_wci_wslv_ctlAckReg = 1'h0;
cap0_wci_wslv_ctlOpActive = 1'h0;
cap0_wci_wslv_illegalEdge = 1'h0;
cap0_wci_wslv_isReset_isInReset = 1'h0;
cap0_wci_wslv_nState = 3'h2;
cap0_wci_wslv_reqF_countReg = 2'h2;
cap0_wci_wslv_respF_c_r = 2'h2;
cap0_wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
cap0_wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
cap0_wci_wslv_sFlagReg = 1'h0;
cap0_wci_wslv_sThreadBusy_d = 1'h0;
cap0_wsiS_burstKind = 2'h2;
cap0_wsiS_errorSticky = 1'h0;
cap0_wsiS_iMesgCount = 32'hAAAAAAAA;
cap0_wsiS_isReset_isInReset = 1'h0;
cap0_wsiS_mesgWordLength = 12'hAAA;
cap0_wsiS_operateD = 1'h0;
cap0_wsiS_pMesgCount = 32'hAAAAAAAA;
cap0_wsiS_peerIsReady = 1'h0;
cap0_wsiS_reqFifo_countReg = 2'h2;
cap0_wsiS_reqFifo_levelsValid = 1'h0;
cap0_wsiS_statusR = 8'hAA;
cap0_wsiS_tBusyCount = 32'hAAAAAAAA;
cap0_wsiS_trafficSticky = 1'h0;
cap0_wsiS_wordCount = 12'hAAA;
cap0_wtiS_isReset_isInReset = 1'h0;
cap0_wtiS_nowReq = 67'h2AAAAAAAAAAAAAAAA;
cap0_wtiS_operateD = 1'h0;
freeCnt = 32'hAAAAAAAA;
needs_init = 1'h0;
pciDevice = 16'hAAAA;
pciw_pciDevice = 16'hAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge pciw_pci0_pcie_ep$user_clk_out)
begin
#0;
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start)
begin
v__h14804 = $time;
#0;
end
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h14804,
cap0_wci_wslv_reqF$D_OUT[36:34],
cap0_wci_wslv_cState);
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_ctrl_EiI && WILL_FIRE_RL_cap0_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_ctrl_EiI] and\n [RL_cap0_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_ctrl_EiI && WILL_FIRE_RL_cap0_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_ctrl_EiI] and\n [RL_cap0_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_ctrl_IsO && WILL_FIRE_RL_cap0_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_ctrl_IsO] and\n [RL_cap0_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h0)
begin
v__h38083 = $time;
#0;
end
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfrd &&
cap0_wci_wslv_reqF$D_OUT[63:52] == 12'h0)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h38083,
cap0_wci_wslv_reqF$D_OUT[63:32],
cap0_wci_wslv_reqF$D_OUT[67:64],
v__h38064);
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_doMessageAccept &&
cap0_controlReg_60_BIT_0_61_AND_NOT_cap0_contr_ETC___d1008 &&
cap0_wsiS_reqFifo$D_OUT[57])
begin
v__h36538 = $time;
#0;
end
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_doMessageAccept &&
cap0_controlReg_60_BIT_0_61_AND_NOT_cap0_contr_ETC___d1008 &&
cap0_wsiS_reqFifo$D_OUT[57])
$display("[%0d]: %m: doMessageAccept DWM metaCount:%0x WSI opcode:%0x length:%0x",
v__h36538,
cap0_metaCount,
cap0_wsiS_reqFifo$D_OUT[7:0],
mlB__h34434);
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfwr)
begin
v__h37878 = $time;
#0;
end
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h37878,
cap0_wci_wslv_reqF$D_OUT[63:32],
cap0_wci_wslv_reqF$D_OUT[67:64],
cap0_wci_wslv_reqF$D_OUT[31:0]);
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete &&
cap0_wci_wslv_illegalEdge)
begin
v__h15123 = $time;
#0;
end
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete &&
cap0_wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h15123,
cap0_wci_wslv_cEdge,
cap0_wci_wslv_cState);
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete &&
!cap0_wci_wslv_illegalEdge)
begin
v__h14979 = $time;
#0;
end
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_wslv_ctl_op_complete &&
!cap0_wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h14979,
cap0_wci_wslv_cEdge,
cap0_wci_wslv_cState,
cap0_wci_wslv_nState);
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_dataBram_serverAdapterA_s1[1] &&
!cap0_dataBram_serverAdapterA_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_dataBram_serverAdapterB_s1[1] &&
!cap0_dataBram_serverAdapterB_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_metaBram_serverAdapterA_s1[1] &&
!cap0_metaBram_serverAdapterA_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_metaBram_serverAdapterB_s1[1] &&
!cap0_metaBram_serverAdapterB_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_metaBram_serverAdapterA_1_s1[1] &&
!cap0_metaBram_serverAdapterA_1_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_metaBram_serverAdapterB_1_s1[1] &&
!cap0_metaBram_serverAdapterB_1_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_metaBram_serverAdapterA_2_s1[1] &&
!cap0_metaBram_serverAdapterA_2_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_metaBram_serverAdapterB_2_s1[1] &&
!cap0_metaBram_serverAdapterB_2_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_metaBram_serverAdapterA_3_s1[1] &&
!cap0_metaBram_serverAdapterA_3_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (cap0_metaBram_serverAdapterB_3_s1[1] &&
!cap0_metaBram_serverAdapterB_3_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_advance_split_response)
begin
v__h37583 = $time;
#0;
end
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_advance_split_response)
$display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h37583, v__h36664);
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_advance_split_response &&
WILL_FIRE_RL_cap0_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_advance_split_response]\n and [RL_cap0_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_advance_split_response &&
WILL_FIRE_RL_cap0_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_advance_split_response]\n and [RL_cap0_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_advance_split_response &&
WILL_FIRE_RL_cap0_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_advance_split_response]\n and [RL_cap0_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfwr &&
WILL_FIRE_RL_cap0_advance_split_response)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfwr] and\n [RL_cap0_advance_split_response] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfwr && WILL_FIRE_RL_cap0_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfwr] and\n [RL_cap0_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfwr && WILL_FIRE_RL_cap0_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfwr] and\n [RL_cap0_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfwr && WILL_FIRE_RL_cap0_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfwr] and\n [RL_cap0_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfwr && WILL_FIRE_RL_cap0_wci_cfrd)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfwr] and\n [RL_cap0_wci_cfrd] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfrd &&
WILL_FIRE_RL_cap0_advance_split_response)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfrd] and\n [RL_cap0_advance_split_response] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfrd && WILL_FIRE_RL_cap0_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfrd] and\n [RL_cap0_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfrd && WILL_FIRE_RL_cap0_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfrd] and\n [RL_cap0_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (ctop$RST_N_wci_m_3 != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cap0_wci_cfrd && WILL_FIRE_RL_cap0_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_cap0_wci_cfrd] and\n [RL_cap0_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkFTop_kc705
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_qpll_wrapper.v
// Version : 1.3
//------------------------------------------------------------------------------
// Filename : qpll_wrapper.v
// Description : QPLL Wrapper Module for 7 Series Transceiver
// Version : 11.4
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL Wrapper ----------------------------------------------------
module pcie_7x_v1_3_qpll_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "1.1", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
)
(
//---------- QPLL Clock Ports --------------------------
input QPLL_GTGREFCLK,
input QPLL_QPLLLOCKDETCLK,
output QPLL_QPLLOUTCLK,
output QPLL_QPLLOUTREFCLK,
output QPLL_QPLLLOCK,
//---------- QPLL Reset Ports --------------------------
input QPLL_QPLLPD,
input QPLL_QPLLRESET,
//---------- QPLL DRP Ports ----------------------------
input QPLL_DRPCLK,
input [ 7:0] QPLL_DRPADDR,
input QPLL_DRPEN,
input [15:0] QPLL_DRPDI,
input QPLL_DRPWE,
output [15:0] QPLL_DRPDO,
output QPLL_DRPRDY
);
//---------- Select QPLL Feedback Divider --------------
// N = 100 for 100 MHz ref clk and 10Gb/s line rate
// N = 80 for 125 MHz ref clk and 10Gb/s line rate
// N = 40 for 250 MHz ref clk and 10Gb/s line rate
//------------------------------------------------------
// N = 80 for 100 MHz ref clk and 8Gb/s line rate
// N = 64 for 125 MHz ref clk and 8Gb/s line rate
// N = 32 for 250 MHz ref clk and 8Gb/s line rate
//------------------------------------------------------
localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 10'b0010000000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 10'b0100100000 :
(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 10'b0101110000 :
(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 10'b0001100000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 10'b0011100000 : 10'b0100100000;
//---------- Select BIAS_CFG ---------------------------
localparam BIAS_CFG = ((PCIE_USE_MODE == "1.0") && (PCIE_PLL_SEL == "CPLL")) ? 64'h0000042000001000 : 64'h0000040000001000;
//---------- Select GTX or GTH -------------------------------------------------
// Notes : Attributes that are commented out uses the GT default settings
//------------------------------------------------------------------------------
generate if (PCIE_GT_DEVICE == "GTH")
//---------- GTH Common ----------------------------------------------------
begin : gth_common
//---------- GTX Common Module ---------------------------------------------
GTHE2_COMMON #
(
//---------- Simulation Attributes -------------------------------------
.SIM_QPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.QPLL_CFG (27'h06801C1), // Optimized for silicon
//.QPLL_CLKOUT_CFG ( 4'b0000), //
.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
.QPLL_COARSE_FREQ_OVRD_EN ( 1'b0), //
.QPLL_CP (10'h1FF), // Optimized for compliance
.QPLL_CP_MONITOR_EN ( 1'b0), //
.QPLL_DMONITOR_SEL ( 1'b0), //
.QPLL_FBDIV (QPLL_FBDIV), //
.QPLL_FBDIV_MONITOR_EN ( 1'b0), //
.QPLL_FBDIV_RATIO ( 1'b1), //
//.QPLL_INIT_CFG (24'h000006), //
.QPLL_LOCK_CFG (16'h01D0), // Optimized for silicon
.QPLL_LPF ( 4'hD), // Optimized for silicon
.QPLL_REFCLK_DIV ( 1), //
//----------------------------------------------------------------------
.BIAS_CFG (BIAS_CFG) // Optimized for silicon
//.COMMON_CFG (32'h00000000), //
//---------- GTH -------------------------------------------------------
//.RSVD_ATTR0 (16'h0000), //
//.RSVD_ATTR1 (16'h0000) //
)
gthe2_common_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK ( 1'd0), //
.GTREFCLK0 (QPLL_GTGREFCLK), //
.GTREFCLK1 ( 1'd0), //
.GTNORTHREFCLK0 ( 1'd0), //
.GTNORTHREFCLK1 ( 1'd0), //
.GTSOUTHREFCLK0 ( 1'd0), //
.GTSOUTHREFCLK1 ( 1'd0), //
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
.QPLLLOCKEN ( 1'd1), //
.QPLLREFCLKSEL ( 3'd1), //
.QPLLRSVD1 (16'd0), //
.QPLLRSVD2 ( 5'b11111), //
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
.QPLLLOCK (QPLL_QPLLLOCK), //
.QPLLFBCLKLOST (), //
.QPLLREFCLKLOST (), //
.QPLLDMONITOR (), //
//---------- Reset -----------------------------------------------------
.QPLLPD (QPLL_QPLLPD), //
.QPLLRESET (QPLL_QPLLRESET), //
.QPLLOUTRESET (1'd0), //
//---------- DRP -------------------------------------------------------
.DRPCLK (QPLL_DRPCLK), //
.DRPADDR (QPLL_DRPADDR), //
.DRPEN (QPLL_DRPEN), //
.DRPDI (QPLL_DRPDI), //
.DRPWE (QPLL_DRPWE), //
.DRPDO (QPLL_DRPDO), //
.DRPRDY (QPLL_DRPRDY), //
//---------- Band Gap --------------------------------------------------
.BGBYPASSB ( 1'd1), //
.BGMONITORENB ( 1'd1), //
.BGPDB ( 1'd1), //
.BGRCALOVRD ( 5'd0), //
//----------------------------------------------------------------------
.PMARSVD ( 8'd0), //
.RCALENB ( 1'b0), //
.REFCLKOUTMONITOR (), //
//---------- GTH -------------------------------------------------------
.BGRCALOVRDENB ( 1'd0), //
.PMARSVDOUT () //
);
end
else
begin : gtx_common
//---------- GTX Common Module ---------------------------------------------
GTXE2_COMMON #
(
//---------- Simulation Attributes -------------------------------------
.SIM_QPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.QPLL_CFG (27'h06801C1), // Optimized for silicon
//.QPLL_CLKOUT_CFG ( 4'b0000), //
.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
.QPLL_COARSE_FREQ_OVRD_EN ( 1'b0), //
.QPLL_CP (10'h1FF), // Optimized for compliance
.QPLL_CP_MONITOR_EN ( 1'b0), //
.QPLL_DMONITOR_SEL ( 1'b0), //
.QPLL_FBDIV (QPLL_FBDIV), //
.QPLL_FBDIV_MONITOR_EN ( 1'b0), //
.QPLL_FBDIV_RATIO ( 1'b1), //
//.QPLL_INIT_CFG (24'h000006), //
.QPLL_LOCK_CFG (16'h01D0), // Optimized for silicon
.QPLL_LPF ( 4'hD), // Optimized for silicon
.QPLL_REFCLK_DIV ( 1), //
//----------------------------------------------------------------------
.BIAS_CFG (BIAS_CFG) // Optimized for silicon
//.COMMON_CFG (32'h00000000) //
)
gtxe2_common_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK ( 1'd0), //
.GTREFCLK0 (QPLL_GTGREFCLK), //
.GTREFCLK1 ( 1'd0), //
.GTNORTHREFCLK0 ( 1'd0), //
.GTNORTHREFCLK1 ( 1'd0), //
.GTSOUTHREFCLK0 ( 1'd0), //
.GTSOUTHREFCLK1 ( 1'd0), //
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
.QPLLLOCKEN ( 1'd1), //
.QPLLREFCLKSEL ( 3'd1), //
.QPLLRSVD1 (16'd0), //
.QPLLRSVD2 ( 5'b11111), //
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
.QPLLLOCK (QPLL_QPLLLOCK), //
.QPLLFBCLKLOST (), //
.QPLLREFCLKLOST (), //
.QPLLDMONITOR (), //
//---------- Reset -----------------------------------------------------
.QPLLPD (QPLL_QPLLPD), //
.QPLLRESET (QPLL_QPLLRESET), //
.QPLLOUTRESET ( 1'd0), //
//---------- DRP -------------------------------------------------------
.DRPCLK (QPLL_DRPCLK), //
.DRPADDR (QPLL_DRPADDR), //
.DRPEN (QPLL_DRPEN), //
.DRPDI (QPLL_DRPDI), //
.DRPWE (QPLL_DRPWE), //
.DRPDO (QPLL_DRPDO), //
.DRPRDY (QPLL_DRPRDY), //
//---------- Band Gap --------------------------------------------------
.BGBYPASSB ( 1'd1), //
.BGMONITORENB ( 1'd1), //
.BGPDB ( 1'd1), //
.BGRCALOVRD ( 5'd0), //
//----------------------------------------------------------------------
.PMARSVD ( 8'd0), //
.RCALENB ( 1'b0), //
.REFCLKOUTMONITOR () //
);
end
endgenerate
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=811,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=125,HLS_SYN_FF=23835,HLS_SYN_LUT=25571}" *)
module convolve_kernel (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
bufw_0_0_Addr_A,
bufw_0_0_EN_A,
bufw_0_0_WEN_A,
bufw_0_0_Din_A,
bufw_0_0_Dout_A,
bufw_0_0_Clk_A,
bufw_0_0_Rst_A,
bufw_0_1_Addr_A,
bufw_0_1_EN_A,
bufw_0_1_WEN_A,
bufw_0_1_Din_A,
bufw_0_1_Dout_A,
bufw_0_1_Clk_A,
bufw_0_1_Rst_A,
bufw_0_2_Addr_A,
bufw_0_2_EN_A,
bufw_0_2_WEN_A,
bufw_0_2_Din_A,
bufw_0_2_Dout_A,
bufw_0_2_Clk_A,
bufw_0_2_Rst_A,
bufw_0_3_Addr_A,
bufw_0_3_EN_A,
bufw_0_3_WEN_A,
bufw_0_3_Din_A,
bufw_0_3_Dout_A,
bufw_0_3_Clk_A,
bufw_0_3_Rst_A,
bufw_0_4_Addr_A,
bufw_0_4_EN_A,
bufw_0_4_WEN_A,
bufw_0_4_Din_A,
bufw_0_4_Dout_A,
bufw_0_4_Clk_A,
bufw_0_4_Rst_A,
bufw_1_0_Addr_A,
bufw_1_0_EN_A,
bufw_1_0_WEN_A,
bufw_1_0_Din_A,
bufw_1_0_Dout_A,
bufw_1_0_Clk_A,
bufw_1_0_Rst_A,
bufw_1_1_Addr_A,
bufw_1_1_EN_A,
bufw_1_1_WEN_A,
bufw_1_1_Din_A,
bufw_1_1_Dout_A,
bufw_1_1_Clk_A,
bufw_1_1_Rst_A,
bufw_1_2_Addr_A,
bufw_1_2_EN_A,
bufw_1_2_WEN_A,
bufw_1_2_Din_A,
bufw_1_2_Dout_A,
bufw_1_2_Clk_A,
bufw_1_2_Rst_A,
bufw_1_3_Addr_A,
bufw_1_3_EN_A,
bufw_1_3_WEN_A,
bufw_1_3_Din_A,
bufw_1_3_Dout_A,
bufw_1_3_Clk_A,
bufw_1_3_Rst_A,
bufw_1_4_Addr_A,
bufw_1_4_EN_A,
bufw_1_4_WEN_A,
bufw_1_4_Din_A,
bufw_1_4_Dout_A,
bufw_1_4_Clk_A,
bufw_1_4_Rst_A,
bufw_2_0_Addr_A,
bufw_2_0_EN_A,
bufw_2_0_WEN_A,
bufw_2_0_Din_A,
bufw_2_0_Dout_A,
bufw_2_0_Clk_A,
bufw_2_0_Rst_A,
bufw_2_1_Addr_A,
bufw_2_1_EN_A,
bufw_2_1_WEN_A,
bufw_2_1_Din_A,
bufw_2_1_Dout_A,
bufw_2_1_Clk_A,
bufw_2_1_Rst_A,
bufw_2_2_Addr_A,
bufw_2_2_EN_A,
bufw_2_2_WEN_A,
bufw_2_2_Din_A,
bufw_2_2_Dout_A,
bufw_2_2_Clk_A,
bufw_2_2_Rst_A,
bufw_2_3_Addr_A,
bufw_2_3_EN_A,
bufw_2_3_WEN_A,
bufw_2_3_Din_A,
bufw_2_3_Dout_A,
bufw_2_3_Clk_A,
bufw_2_3_Rst_A,
bufw_2_4_Addr_A,
bufw_2_4_EN_A,
bufw_2_4_WEN_A,
bufw_2_4_Din_A,
bufw_2_4_Dout_A,
bufw_2_4_Clk_A,
bufw_2_4_Rst_A,
bufw_3_0_Addr_A,
bufw_3_0_EN_A,
bufw_3_0_WEN_A,
bufw_3_0_Din_A,
bufw_3_0_Dout_A,
bufw_3_0_Clk_A,
bufw_3_0_Rst_A,
bufw_3_1_Addr_A,
bufw_3_1_EN_A,
bufw_3_1_WEN_A,
bufw_3_1_Din_A,
bufw_3_1_Dout_A,
bufw_3_1_Clk_A,
bufw_3_1_Rst_A,
bufw_3_2_Addr_A,
bufw_3_2_EN_A,
bufw_3_2_WEN_A,
bufw_3_2_Din_A,
bufw_3_2_Dout_A,
bufw_3_2_Clk_A,
bufw_3_2_Rst_A,
bufw_3_3_Addr_A,
bufw_3_3_EN_A,
bufw_3_3_WEN_A,
bufw_3_3_Din_A,
bufw_3_3_Dout_A,
bufw_3_3_Clk_A,
bufw_3_3_Rst_A,
bufw_3_4_Addr_A,
bufw_3_4_EN_A,
bufw_3_4_WEN_A,
bufw_3_4_Din_A,
bufw_3_4_Dout_A,
bufw_3_4_Clk_A,
bufw_3_4_Rst_A,
bufw_4_0_Addr_A,
bufw_4_0_EN_A,
bufw_4_0_WEN_A,
bufw_4_0_Din_A,
bufw_4_0_Dout_A,
bufw_4_0_Clk_A,
bufw_4_0_Rst_A,
bufw_4_1_Addr_A,
bufw_4_1_EN_A,
bufw_4_1_WEN_A,
bufw_4_1_Din_A,
bufw_4_1_Dout_A,
bufw_4_1_Clk_A,
bufw_4_1_Rst_A,
bufw_4_2_Addr_A,
bufw_4_2_EN_A,
bufw_4_2_WEN_A,
bufw_4_2_Din_A,
bufw_4_2_Dout_A,
bufw_4_2_Clk_A,
bufw_4_2_Rst_A,
bufw_4_3_Addr_A,
bufw_4_3_EN_A,
bufw_4_3_WEN_A,
bufw_4_3_Din_A,
bufw_4_3_Dout_A,
bufw_4_3_Clk_A,
bufw_4_3_Rst_A,
bufw_4_4_Addr_A,
bufw_4_4_EN_A,
bufw_4_4_WEN_A,
bufw_4_4_Din_A,
bufw_4_4_Dout_A,
bufw_4_4_Clk_A,
bufw_4_4_Rst_A,
bufi_0_Addr_A,
bufi_0_EN_A,
bufi_0_WEN_A,
bufi_0_Din_A,
bufi_0_Dout_A,
bufi_0_Clk_A,
bufi_0_Rst_A,
bufi_0_Addr_B,
bufi_0_EN_B,
bufi_0_WEN_B,
bufi_0_Din_B,
bufi_0_Dout_B,
bufi_0_Clk_B,
bufi_0_Rst_B,
bufi_1_Addr_A,
bufi_1_EN_A,
bufi_1_WEN_A,
bufi_1_Din_A,
bufi_1_Dout_A,
bufi_1_Clk_A,
bufi_1_Rst_A,
bufi_1_Addr_B,
bufi_1_EN_B,
bufi_1_WEN_B,
bufi_1_Din_B,
bufi_1_Dout_B,
bufi_1_Clk_B,
bufi_1_Rst_B,
bufi_2_Addr_A,
bufi_2_EN_A,
bufi_2_WEN_A,
bufi_2_Din_A,
bufi_2_Dout_A,
bufi_2_Clk_A,
bufi_2_Rst_A,
bufi_2_Addr_B,
bufi_2_EN_B,
bufi_2_WEN_B,
bufi_2_Din_B,
bufi_2_Dout_B,
bufi_2_Clk_B,
bufi_2_Rst_B,
bufi_3_Addr_A,
bufi_3_EN_A,
bufi_3_WEN_A,
bufi_3_Din_A,
bufi_3_Dout_A,
bufi_3_Clk_A,
bufi_3_Rst_A,
bufi_3_Addr_B,
bufi_3_EN_B,
bufi_3_WEN_B,
bufi_3_Din_B,
bufi_3_Dout_B,
bufi_3_Clk_B,
bufi_3_Rst_B,
bufi_4_Addr_A,
bufi_4_EN_A,
bufi_4_WEN_A,
bufi_4_Din_A,
bufi_4_Dout_A,
bufi_4_Clk_A,
bufi_4_Rst_A,
bufi_4_Addr_B,
bufi_4_EN_B,
bufi_4_WEN_B,
bufi_4_Din_B,
bufi_4_Dout_B,
bufi_4_Clk_B,
bufi_4_Rst_B,
bufi_5_Addr_A,
bufi_5_EN_A,
bufi_5_WEN_A,
bufi_5_Din_A,
bufi_5_Dout_A,
bufi_5_Clk_A,
bufi_5_Rst_A,
bufi_5_Addr_B,
bufi_5_EN_B,
bufi_5_WEN_B,
bufi_5_Din_B,
bufi_5_Dout_B,
bufi_5_Clk_B,
bufi_5_Rst_B,
bufi_6_Addr_A,
bufi_6_EN_A,
bufi_6_WEN_A,
bufi_6_Din_A,
bufi_6_Dout_A,
bufi_6_Clk_A,
bufi_6_Rst_A,
bufi_6_Addr_B,
bufi_6_EN_B,
bufi_6_WEN_B,
bufi_6_Din_B,
bufi_6_Dout_B,
bufi_6_Clk_B,
bufi_6_Rst_B,
bufo_0_Addr_A,
bufo_0_EN_A,
bufo_0_WEN_A,
bufo_0_Din_A,
bufo_0_Dout_A,
bufo_0_Clk_A,
bufo_0_Rst_A,
bufo_0_Addr_B,
bufo_0_EN_B,
bufo_0_WEN_B,
bufo_0_Din_B,
bufo_0_Dout_B,
bufo_0_Clk_B,
bufo_0_Rst_B,
bufo_1_Addr_A,
bufo_1_EN_A,
bufo_1_WEN_A,
bufo_1_Din_A,
bufo_1_Dout_A,
bufo_1_Clk_A,
bufo_1_Rst_A,
bufo_1_Addr_B,
bufo_1_EN_B,
bufo_1_WEN_B,
bufo_1_Din_B,
bufo_1_Dout_B,
bufo_1_Clk_B,
bufo_1_Rst_B,
bufo_2_Addr_A,
bufo_2_EN_A,
bufo_2_WEN_A,
bufo_2_Din_A,
bufo_2_Dout_A,
bufo_2_Clk_A,
bufo_2_Rst_A,
bufo_2_Addr_B,
bufo_2_EN_B,
bufo_2_WEN_B,
bufo_2_Din_B,
bufo_2_Dout_B,
bufo_2_Clk_B,
bufo_2_Rst_B
);
parameter ap_ST_fsm_state1 = 5'd1;
parameter ap_ST_fsm_pp0_stage0 = 5'd2;
parameter ap_ST_fsm_pp0_stage1 = 5'd4;
parameter ap_ST_fsm_pp0_stage2 = 5'd8;
parameter ap_ST_fsm_state239 = 5'd16;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [31:0] bufw_0_0_Addr_A;
output bufw_0_0_EN_A;
output [3:0] bufw_0_0_WEN_A;
output [31:0] bufw_0_0_Din_A;
input [31:0] bufw_0_0_Dout_A;
output bufw_0_0_Clk_A;
output bufw_0_0_Rst_A;
output [31:0] bufw_0_1_Addr_A;
output bufw_0_1_EN_A;
output [3:0] bufw_0_1_WEN_A;
output [31:0] bufw_0_1_Din_A;
input [31:0] bufw_0_1_Dout_A;
output bufw_0_1_Clk_A;
output bufw_0_1_Rst_A;
output [31:0] bufw_0_2_Addr_A;
output bufw_0_2_EN_A;
output [3:0] bufw_0_2_WEN_A;
output [31:0] bufw_0_2_Din_A;
input [31:0] bufw_0_2_Dout_A;
output bufw_0_2_Clk_A;
output bufw_0_2_Rst_A;
output [31:0] bufw_0_3_Addr_A;
output bufw_0_3_EN_A;
output [3:0] bufw_0_3_WEN_A;
output [31:0] bufw_0_3_Din_A;
input [31:0] bufw_0_3_Dout_A;
output bufw_0_3_Clk_A;
output bufw_0_3_Rst_A;
output [31:0] bufw_0_4_Addr_A;
output bufw_0_4_EN_A;
output [3:0] bufw_0_4_WEN_A;
output [31:0] bufw_0_4_Din_A;
input [31:0] bufw_0_4_Dout_A;
output bufw_0_4_Clk_A;
output bufw_0_4_Rst_A;
output [31:0] bufw_1_0_Addr_A;
output bufw_1_0_EN_A;
output [3:0] bufw_1_0_WEN_A;
output [31:0] bufw_1_0_Din_A;
input [31:0] bufw_1_0_Dout_A;
output bufw_1_0_Clk_A;
output bufw_1_0_Rst_A;
output [31:0] bufw_1_1_Addr_A;
output bufw_1_1_EN_A;
output [3:0] bufw_1_1_WEN_A;
output [31:0] bufw_1_1_Din_A;
input [31:0] bufw_1_1_Dout_A;
output bufw_1_1_Clk_A;
output bufw_1_1_Rst_A;
output [31:0] bufw_1_2_Addr_A;
output bufw_1_2_EN_A;
output [3:0] bufw_1_2_WEN_A;
output [31:0] bufw_1_2_Din_A;
input [31:0] bufw_1_2_Dout_A;
output bufw_1_2_Clk_A;
output bufw_1_2_Rst_A;
output [31:0] bufw_1_3_Addr_A;
output bufw_1_3_EN_A;
output [3:0] bufw_1_3_WEN_A;
output [31:0] bufw_1_3_Din_A;
input [31:0] bufw_1_3_Dout_A;
output bufw_1_3_Clk_A;
output bufw_1_3_Rst_A;
output [31:0] bufw_1_4_Addr_A;
output bufw_1_4_EN_A;
output [3:0] bufw_1_4_WEN_A;
output [31:0] bufw_1_4_Din_A;
input [31:0] bufw_1_4_Dout_A;
output bufw_1_4_Clk_A;
output bufw_1_4_Rst_A;
output [31:0] bufw_2_0_Addr_A;
output bufw_2_0_EN_A;
output [3:0] bufw_2_0_WEN_A;
output [31:0] bufw_2_0_Din_A;
input [31:0] bufw_2_0_Dout_A;
output bufw_2_0_Clk_A;
output bufw_2_0_Rst_A;
output [31:0] bufw_2_1_Addr_A;
output bufw_2_1_EN_A;
output [3:0] bufw_2_1_WEN_A;
output [31:0] bufw_2_1_Din_A;
input [31:0] bufw_2_1_Dout_A;
output bufw_2_1_Clk_A;
output bufw_2_1_Rst_A;
output [31:0] bufw_2_2_Addr_A;
output bufw_2_2_EN_A;
output [3:0] bufw_2_2_WEN_A;
output [31:0] bufw_2_2_Din_A;
input [31:0] bufw_2_2_Dout_A;
output bufw_2_2_Clk_A;
output bufw_2_2_Rst_A;
output [31:0] bufw_2_3_Addr_A;
output bufw_2_3_EN_A;
output [3:0] bufw_2_3_WEN_A;
output [31:0] bufw_2_3_Din_A;
input [31:0] bufw_2_3_Dout_A;
output bufw_2_3_Clk_A;
output bufw_2_3_Rst_A;
output [31:0] bufw_2_4_Addr_A;
output bufw_2_4_EN_A;
output [3:0] bufw_2_4_WEN_A;
output [31:0] bufw_2_4_Din_A;
input [31:0] bufw_2_4_Dout_A;
output bufw_2_4_Clk_A;
output bufw_2_4_Rst_A;
output [31:0] bufw_3_0_Addr_A;
output bufw_3_0_EN_A;
output [3:0] bufw_3_0_WEN_A;
output [31:0] bufw_3_0_Din_A;
input [31:0] bufw_3_0_Dout_A;
output bufw_3_0_Clk_A;
output bufw_3_0_Rst_A;
output [31:0] bufw_3_1_Addr_A;
output bufw_3_1_EN_A;
output [3:0] bufw_3_1_WEN_A;
output [31:0] bufw_3_1_Din_A;
input [31:0] bufw_3_1_Dout_A;
output bufw_3_1_Clk_A;
output bufw_3_1_Rst_A;
output [31:0] bufw_3_2_Addr_A;
output bufw_3_2_EN_A;
output [3:0] bufw_3_2_WEN_A;
output [31:0] bufw_3_2_Din_A;
input [31:0] bufw_3_2_Dout_A;
output bufw_3_2_Clk_A;
output bufw_3_2_Rst_A;
output [31:0] bufw_3_3_Addr_A;
output bufw_3_3_EN_A;
output [3:0] bufw_3_3_WEN_A;
output [31:0] bufw_3_3_Din_A;
input [31:0] bufw_3_3_Dout_A;
output bufw_3_3_Clk_A;
output bufw_3_3_Rst_A;
output [31:0] bufw_3_4_Addr_A;
output bufw_3_4_EN_A;
output [3:0] bufw_3_4_WEN_A;
output [31:0] bufw_3_4_Din_A;
input [31:0] bufw_3_4_Dout_A;
output bufw_3_4_Clk_A;
output bufw_3_4_Rst_A;
output [31:0] bufw_4_0_Addr_A;
output bufw_4_0_EN_A;
output [3:0] bufw_4_0_WEN_A;
output [31:0] bufw_4_0_Din_A;
input [31:0] bufw_4_0_Dout_A;
output bufw_4_0_Clk_A;
output bufw_4_0_Rst_A;
output [31:0] bufw_4_1_Addr_A;
output bufw_4_1_EN_A;
output [3:0] bufw_4_1_WEN_A;
output [31:0] bufw_4_1_Din_A;
input [31:0] bufw_4_1_Dout_A;
output bufw_4_1_Clk_A;
output bufw_4_1_Rst_A;
output [31:0] bufw_4_2_Addr_A;
output bufw_4_2_EN_A;
output [3:0] bufw_4_2_WEN_A;
output [31:0] bufw_4_2_Din_A;
input [31:0] bufw_4_2_Dout_A;
output bufw_4_2_Clk_A;
output bufw_4_2_Rst_A;
output [31:0] bufw_4_3_Addr_A;
output bufw_4_3_EN_A;
output [3:0] bufw_4_3_WEN_A;
output [31:0] bufw_4_3_Din_A;
input [31:0] bufw_4_3_Dout_A;
output bufw_4_3_Clk_A;
output bufw_4_3_Rst_A;
output [31:0] bufw_4_4_Addr_A;
output bufw_4_4_EN_A;
output [3:0] bufw_4_4_WEN_A;
output [31:0] bufw_4_4_Din_A;
input [31:0] bufw_4_4_Dout_A;
output bufw_4_4_Clk_A;
output bufw_4_4_Rst_A;
output [31:0] bufi_0_Addr_A;
output bufi_0_EN_A;
output [3:0] bufi_0_WEN_A;
output [31:0] bufi_0_Din_A;
input [31:0] bufi_0_Dout_A;
output bufi_0_Clk_A;
output bufi_0_Rst_A;
output [31:0] bufi_0_Addr_B;
output bufi_0_EN_B;
output [3:0] bufi_0_WEN_B;
output [31:0] bufi_0_Din_B;
input [31:0] bufi_0_Dout_B;
output bufi_0_Clk_B;
output bufi_0_Rst_B;
output [31:0] bufi_1_Addr_A;
output bufi_1_EN_A;
output [3:0] bufi_1_WEN_A;
output [31:0] bufi_1_Din_A;
input [31:0] bufi_1_Dout_A;
output bufi_1_Clk_A;
output bufi_1_Rst_A;
output [31:0] bufi_1_Addr_B;
output bufi_1_EN_B;
output [3:0] bufi_1_WEN_B;
output [31:0] bufi_1_Din_B;
input [31:0] bufi_1_Dout_B;
output bufi_1_Clk_B;
output bufi_1_Rst_B;
output [31:0] bufi_2_Addr_A;
output bufi_2_EN_A;
output [3:0] bufi_2_WEN_A;
output [31:0] bufi_2_Din_A;
input [31:0] bufi_2_Dout_A;
output bufi_2_Clk_A;
output bufi_2_Rst_A;
output [31:0] bufi_2_Addr_B;
output bufi_2_EN_B;
output [3:0] bufi_2_WEN_B;
output [31:0] bufi_2_Din_B;
input [31:0] bufi_2_Dout_B;
output bufi_2_Clk_B;
output bufi_2_Rst_B;
output [31:0] bufi_3_Addr_A;
output bufi_3_EN_A;
output [3:0] bufi_3_WEN_A;
output [31:0] bufi_3_Din_A;
input [31:0] bufi_3_Dout_A;
output bufi_3_Clk_A;
output bufi_3_Rst_A;
output [31:0] bufi_3_Addr_B;
output bufi_3_EN_B;
output [3:0] bufi_3_WEN_B;
output [31:0] bufi_3_Din_B;
input [31:0] bufi_3_Dout_B;
output bufi_3_Clk_B;
output bufi_3_Rst_B;
output [31:0] bufi_4_Addr_A;
output bufi_4_EN_A;
output [3:0] bufi_4_WEN_A;
output [31:0] bufi_4_Din_A;
input [31:0] bufi_4_Dout_A;
output bufi_4_Clk_A;
output bufi_4_Rst_A;
output [31:0] bufi_4_Addr_B;
output bufi_4_EN_B;
output [3:0] bufi_4_WEN_B;
output [31:0] bufi_4_Din_B;
input [31:0] bufi_4_Dout_B;
output bufi_4_Clk_B;
output bufi_4_Rst_B;
output [31:0] bufi_5_Addr_A;
output bufi_5_EN_A;
output [3:0] bufi_5_WEN_A;
output [31:0] bufi_5_Din_A;
input [31:0] bufi_5_Dout_A;
output bufi_5_Clk_A;
output bufi_5_Rst_A;
output [31:0] bufi_5_Addr_B;
output bufi_5_EN_B;
output [3:0] bufi_5_WEN_B;
output [31:0] bufi_5_Din_B;
input [31:0] bufi_5_Dout_B;
output bufi_5_Clk_B;
output bufi_5_Rst_B;
output [31:0] bufi_6_Addr_A;
output bufi_6_EN_A;
output [3:0] bufi_6_WEN_A;
output [31:0] bufi_6_Din_A;
input [31:0] bufi_6_Dout_A;
output bufi_6_Clk_A;
output bufi_6_Rst_A;
output [31:0] bufi_6_Addr_B;
output bufi_6_EN_B;
output [3:0] bufi_6_WEN_B;
output [31:0] bufi_6_Din_B;
input [31:0] bufi_6_Dout_B;
output bufi_6_Clk_B;
output bufi_6_Rst_B;
output [31:0] bufo_0_Addr_A;
output bufo_0_EN_A;
output [3:0] bufo_0_WEN_A;
output [31:0] bufo_0_Din_A;
input [31:0] bufo_0_Dout_A;
output bufo_0_Clk_A;
output bufo_0_Rst_A;
output [31:0] bufo_0_Addr_B;
output bufo_0_EN_B;
output [3:0] bufo_0_WEN_B;
output [31:0] bufo_0_Din_B;
input [31:0] bufo_0_Dout_B;
output bufo_0_Clk_B;
output bufo_0_Rst_B;
output [31:0] bufo_1_Addr_A;
output bufo_1_EN_A;
output [3:0] bufo_1_WEN_A;
output [31:0] bufo_1_Din_A;
input [31:0] bufo_1_Dout_A;
output bufo_1_Clk_A;
output bufo_1_Rst_A;
output [31:0] bufo_1_Addr_B;
output bufo_1_EN_B;
output [3:0] bufo_1_WEN_B;
output [31:0] bufo_1_Din_B;
input [31:0] bufo_1_Dout_B;
output bufo_1_Clk_B;
output bufo_1_Rst_B;
output [31:0] bufo_2_Addr_A;
output bufo_2_EN_A;
output [3:0] bufo_2_WEN_A;
output [31:0] bufo_2_Din_A;
input [31:0] bufo_2_Dout_A;
output bufo_2_Clk_A;
output bufo_2_Rst_A;
output [31:0] bufo_2_Addr_B;
output bufo_2_EN_B;
output [3:0] bufo_2_WEN_B;
output [31:0] bufo_2_Din_B;
input [31:0] bufo_2_Dout_B;
output bufo_2_Clk_B;
output bufo_2_Rst_B;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg bufw_0_0_EN_A;
reg bufw_0_1_EN_A;
reg bufw_0_2_EN_A;
reg bufw_0_3_EN_A;
reg bufw_0_4_EN_A;
reg bufw_1_0_EN_A;
reg bufw_1_1_EN_A;
reg bufw_1_2_EN_A;
reg bufw_1_3_EN_A;
reg bufw_1_4_EN_A;
reg bufw_2_0_EN_A;
reg bufw_2_1_EN_A;
reg bufw_2_2_EN_A;
reg bufw_2_3_EN_A;
reg bufw_2_4_EN_A;
reg bufw_3_0_EN_A;
reg bufw_3_1_EN_A;
reg bufw_3_2_EN_A;
reg bufw_3_3_EN_A;
reg bufw_3_4_EN_A;
reg bufw_4_0_EN_A;
reg bufw_4_1_EN_A;
reg bufw_4_2_EN_A;
reg bufw_4_3_EN_A;
reg bufw_4_4_EN_A;
reg bufi_0_EN_A;
reg bufi_0_EN_B;
reg bufi_1_EN_A;
reg bufi_1_EN_B;
reg bufi_2_EN_A;
reg bufi_2_EN_B;
reg bufi_3_EN_A;
reg bufi_3_EN_B;
reg bufi_4_EN_A;
reg bufi_4_EN_B;
reg bufi_5_EN_A;
reg bufi_5_EN_B;
reg bufi_6_EN_A;
reg bufi_6_EN_B;
reg bufo_0_EN_A;
reg bufo_0_EN_B;
reg[3:0] bufo_0_WEN_B;
reg bufo_1_EN_A;
reg bufo_1_EN_B;
reg[3:0] bufo_1_WEN_B;
reg bufo_2_EN_A;
reg bufo_2_EN_B;
reg[3:0] bufo_2_WEN_B;
(* fsm_encoding = "none" *) reg [4:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [7:0] indvar_flatten_reg_810;
reg [6:0] p_s_reg_821;
reg [1:0] p_1_reg_833;
wire [0:0] exitcond_flatten_fu_1044_p2;
reg [0:0] exitcond_flatten_reg_1202;
wire ap_CS_fsm_pp0_stage0;
wire ap_block_state2_pp0_stage0_iter0;
wire ap_block_state5_pp0_stage0_iter1;
wire ap_block_state8_pp0_stage0_iter2;
wire ap_block_state11_pp0_stage0_iter3;
wire ap_block_state14_pp0_stage0_iter4;
wire ap_block_state17_pp0_stage0_iter5;
wire ap_block_state20_pp0_stage0_iter6;
wire ap_block_state23_pp0_stage0_iter7;
wire ap_block_state26_pp0_stage0_iter8;
wire ap_block_state29_pp0_stage0_iter9;
wire ap_block_state32_pp0_stage0_iter10;
wire ap_block_state35_pp0_stage0_iter11;
wire ap_block_state38_pp0_stage0_iter12;
wire ap_block_state41_pp0_stage0_iter13;
wire ap_block_state44_pp0_stage0_iter14;
wire ap_block_state47_pp0_stage0_iter15;
wire ap_block_state50_pp0_stage0_iter16;
wire ap_block_state53_pp0_stage0_iter17;
wire ap_block_state56_pp0_stage0_iter18;
wire ap_block_state59_pp0_stage0_iter19;
wire ap_block_state62_pp0_stage0_iter20;
wire ap_block_state65_pp0_stage0_iter21;
wire ap_block_state68_pp0_stage0_iter22;
wire ap_block_state71_pp0_stage0_iter23;
wire ap_block_state74_pp0_stage0_iter24;
wire ap_block_state77_pp0_stage0_iter25;
wire ap_block_state80_pp0_stage0_iter26;
wire ap_block_state83_pp0_stage0_iter27;
wire ap_block_state86_pp0_stage0_iter28;
wire ap_block_state89_pp0_stage0_iter29;
wire ap_block_state92_pp0_stage0_iter30;
wire ap_block_state95_pp0_stage0_iter31;
wire ap_block_state98_pp0_stage0_iter32;
wire ap_block_state101_pp0_stage0_iter33;
wire ap_block_state104_pp0_stage0_iter34;
wire ap_block_state107_pp0_stage0_iter35;
wire ap_block_state110_pp0_stage0_iter36;
wire ap_block_state113_pp0_stage0_iter37;
wire ap_block_state116_pp0_stage0_iter38;
wire ap_block_state119_pp0_stage0_iter39;
wire ap_block_state122_pp0_stage0_iter40;
wire ap_block_state125_pp0_stage0_iter41;
wire ap_block_state128_pp0_stage0_iter42;
wire ap_block_state131_pp0_stage0_iter43;
wire ap_block_state134_pp0_stage0_iter44;
wire ap_block_state137_pp0_stage0_iter45;
wire ap_block_state140_pp0_stage0_iter46;
wire ap_block_state143_pp0_stage0_iter47;
wire ap_block_state146_pp0_stage0_iter48;
wire ap_block_state149_pp0_stage0_iter49;
wire ap_block_state152_pp0_stage0_iter50;
wire ap_block_state155_pp0_stage0_iter51;
wire ap_block_state158_pp0_stage0_iter52;
wire ap_block_state161_pp0_stage0_iter53;
wire ap_block_state164_pp0_stage0_iter54;
wire ap_block_state167_pp0_stage0_iter55;
wire ap_block_state170_pp0_stage0_iter56;
wire ap_block_state173_pp0_stage0_iter57;
wire ap_block_state176_pp0_stage0_iter58;
wire ap_block_state179_pp0_stage0_iter59;
wire ap_block_state182_pp0_stage0_iter60;
wire ap_block_state185_pp0_stage0_iter61;
wire ap_block_state188_pp0_stage0_iter62;
wire ap_block_state191_pp0_stage0_iter63;
wire ap_block_state194_pp0_stage0_iter64;
wire ap_block_state197_pp0_stage0_iter65;
wire ap_block_state200_pp0_stage0_iter66;
wire ap_block_state203_pp0_stage0_iter67;
wire ap_block_state206_pp0_stage0_iter68;
wire ap_block_state209_pp0_stage0_iter69;
wire ap_block_state212_pp0_stage0_iter70;
wire ap_block_state215_pp0_stage0_iter71;
wire ap_block_state218_pp0_stage0_iter72;
wire ap_block_state221_pp0_stage0_iter73;
wire ap_block_state224_pp0_stage0_iter74;
wire ap_block_state227_pp0_stage0_iter75;
wire ap_block_state230_pp0_stage0_iter76;
wire ap_block_state233_pp0_stage0_iter77;
wire ap_block_state236_pp0_stage0_iter78;
wire ap_block_pp0_stage0_flag00011001;
reg [0:0] ap_reg_pp0_iter1_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter2_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter3_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter4_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter5_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter6_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter7_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter8_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter9_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter10_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter11_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter12_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter13_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter14_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter15_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter16_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter17_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter18_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter19_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter20_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter21_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter22_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter23_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter24_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter25_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter26_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter27_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter28_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter29_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter30_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter31_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter32_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter33_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter34_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter35_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter36_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter37_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter38_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter39_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter40_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter41_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter42_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter43_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter44_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter45_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter46_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter47_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter48_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter49_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter50_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter51_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter52_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter53_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter54_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter55_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter56_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter57_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter58_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter59_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter60_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter61_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter62_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter63_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter64_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter65_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter66_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter67_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter68_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter69_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter70_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter71_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter72_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter73_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter74_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter75_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter76_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter77_exitcond_flatten_reg_1202;
reg [0:0] ap_reg_pp0_iter78_exitcond_flatten_reg_1202;
wire [7:0] indvar_flatten_next_fu_1050_p2;
reg [7:0] indvar_flatten_next_reg_1206;
reg ap_enable_reg_pp0_iter0;
wire [6:0] to_b_V_fu_1056_p2;
reg [6:0] to_b_V_reg_1211;
wire [0:0] tmp_1_fu_1062_p2;
reg [0:0] tmp_1_reg_1216;
wire [1:0] p_1_mid2_fu_1068_p3;
reg [1:0] p_1_mid2_reg_1221;
reg [1:0] ap_reg_pp0_iter1_p_1_mid2_reg_1221;
wire [6:0] tmp_mid2_v_fu_1076_p3;
reg [6:0] tmp_mid2_v_reg_1230;
wire ap_CS_fsm_pp0_stage1;
wire ap_block_state3_pp0_stage1_iter0;
wire ap_block_state6_pp0_stage1_iter1;
wire ap_block_state9_pp0_stage1_iter2;
wire ap_block_state12_pp0_stage1_iter3;
wire ap_block_state15_pp0_stage1_iter4;
wire ap_block_state18_pp0_stage1_iter5;
wire ap_block_state21_pp0_stage1_iter6;
wire ap_block_state24_pp0_stage1_iter7;
wire ap_block_state27_pp0_stage1_iter8;
wire ap_block_state30_pp0_stage1_iter9;
wire ap_block_state33_pp0_stage1_iter10;
wire ap_block_state36_pp0_stage1_iter11;
wire ap_block_state39_pp0_stage1_iter12;
wire ap_block_state42_pp0_stage1_iter13;
wire ap_block_state45_pp0_stage1_iter14;
wire ap_block_state48_pp0_stage1_iter15;
wire ap_block_state51_pp0_stage1_iter16;
wire ap_block_state54_pp0_stage1_iter17;
wire ap_block_state57_pp0_stage1_iter18;
wire ap_block_state60_pp0_stage1_iter19;
wire ap_block_state63_pp0_stage1_iter20;
wire ap_block_state66_pp0_stage1_iter21;
wire ap_block_state69_pp0_stage1_iter22;
wire ap_block_state72_pp0_stage1_iter23;
wire ap_block_state75_pp0_stage1_iter24;
wire ap_block_state78_pp0_stage1_iter25;
wire ap_block_state81_pp0_stage1_iter26;
wire ap_block_state84_pp0_stage1_iter27;
wire ap_block_state87_pp0_stage1_iter28;
wire ap_block_state90_pp0_stage1_iter29;
wire ap_block_state93_pp0_stage1_iter30;
wire ap_block_state96_pp0_stage1_iter31;
wire ap_block_state99_pp0_stage1_iter32;
wire ap_block_state102_pp0_stage1_iter33;
wire ap_block_state105_pp0_stage1_iter34;
wire ap_block_state108_pp0_stage1_iter35;
wire ap_block_state111_pp0_stage1_iter36;
wire ap_block_state114_pp0_stage1_iter37;
wire ap_block_state117_pp0_stage1_iter38;
wire ap_block_state120_pp0_stage1_iter39;
wire ap_block_state123_pp0_stage1_iter40;
wire ap_block_state126_pp0_stage1_iter41;
wire ap_block_state129_pp0_stage1_iter42;
wire ap_block_state132_pp0_stage1_iter43;
wire ap_block_state135_pp0_stage1_iter44;
wire ap_block_state138_pp0_stage1_iter45;
wire ap_block_state141_pp0_stage1_iter46;
wire ap_block_state144_pp0_stage1_iter47;
wire ap_block_state147_pp0_stage1_iter48;
wire ap_block_state150_pp0_stage1_iter49;
wire ap_block_state153_pp0_stage1_iter50;
wire ap_block_state156_pp0_stage1_iter51;
wire ap_block_state159_pp0_stage1_iter52;
wire ap_block_state162_pp0_stage1_iter53;
wire ap_block_state165_pp0_stage1_iter54;
wire ap_block_state168_pp0_stage1_iter55;
wire ap_block_state171_pp0_stage1_iter56;
wire ap_block_state174_pp0_stage1_iter57;
wire ap_block_state177_pp0_stage1_iter58;
wire ap_block_state180_pp0_stage1_iter59;
wire ap_block_state183_pp0_stage1_iter60;
wire ap_block_state186_pp0_stage1_iter61;
wire ap_block_state189_pp0_stage1_iter62;
wire ap_block_state192_pp0_stage1_iter63;
wire ap_block_state195_pp0_stage1_iter64;
wire ap_block_state198_pp0_stage1_iter65;
wire ap_block_state201_pp0_stage1_iter66;
wire ap_block_state204_pp0_stage1_iter67;
wire ap_block_state207_pp0_stage1_iter68;
wire ap_block_state210_pp0_stage1_iter69;
wire ap_block_state213_pp0_stage1_iter70;
wire ap_block_state216_pp0_stage1_iter71;
wire ap_block_state219_pp0_stage1_iter72;
wire ap_block_state222_pp0_stage1_iter73;
wire ap_block_state225_pp0_stage1_iter74;
wire ap_block_state228_pp0_stage1_iter75;
wire ap_block_state231_pp0_stage1_iter76;
wire ap_block_state234_pp0_stage1_iter77;
wire ap_block_state237_pp0_stage1_iter78;
wire ap_block_pp0_stage1_flag00011001;
reg [6:0] ap_reg_pp0_iter1_tmp_mid2_v_reg_1230;
wire [2:0] lhs_V_cast1_fu_1092_p1;
reg [2:0] lhs_V_cast1_reg_1273;
wire [1:0] row_b_V_fu_1095_p2;
reg [1:0] row_b_V_reg_1278;
wire [2:0] r_V_1_0_2_fu_1100_p2;
reg [2:0] r_V_1_0_2_reg_1284;
wire [63:0] tmp_mid2_fu_1106_p1;
reg [63:0] tmp_mid2_reg_1289;
wire ap_CS_fsm_pp0_stage2;
wire ap_block_state4_pp0_stage2_iter0;
wire ap_block_state7_pp0_stage2_iter1;
wire ap_block_state10_pp0_stage2_iter2;
wire ap_block_state13_pp0_stage2_iter3;
wire ap_block_state16_pp0_stage2_iter4;
wire ap_block_state19_pp0_stage2_iter5;
wire ap_block_state22_pp0_stage2_iter6;
wire ap_block_state25_pp0_stage2_iter7;
wire ap_block_state28_pp0_stage2_iter8;
wire ap_block_state31_pp0_stage2_iter9;
wire ap_block_state34_pp0_stage2_iter10;
wire ap_block_state37_pp0_stage2_iter11;
wire ap_block_state40_pp0_stage2_iter12;
wire ap_block_state43_pp0_stage2_iter13;
wire ap_block_state46_pp0_stage2_iter14;
wire ap_block_state49_pp0_stage2_iter15;
wire ap_block_state52_pp0_stage2_iter16;
wire ap_block_state55_pp0_stage2_iter17;
wire ap_block_state58_pp0_stage2_iter18;
wire ap_block_state61_pp0_stage2_iter19;
wire ap_block_state64_pp0_stage2_iter20;
wire ap_block_state67_pp0_stage2_iter21;
wire ap_block_state70_pp0_stage2_iter22;
wire ap_block_state73_pp0_stage2_iter23;
wire ap_block_state76_pp0_stage2_iter24;
wire ap_block_state79_pp0_stage2_iter25;
wire ap_block_state82_pp0_stage2_iter26;
wire ap_block_state85_pp0_stage2_iter27;
wire ap_block_state88_pp0_stage2_iter28;
wire ap_block_state91_pp0_stage2_iter29;
wire ap_block_state94_pp0_stage2_iter30;
wire ap_block_state97_pp0_stage2_iter31;
wire ap_block_state100_pp0_stage2_iter32;
wire ap_block_state103_pp0_stage2_iter33;
wire ap_block_state106_pp0_stage2_iter34;
wire ap_block_state109_pp0_stage2_iter35;
wire ap_block_state112_pp0_stage2_iter36;
wire ap_block_state115_pp0_stage2_iter37;
wire ap_block_state118_pp0_stage2_iter38;
wire ap_block_state121_pp0_stage2_iter39;
wire ap_block_state124_pp0_stage2_iter40;
wire ap_block_state127_pp0_stage2_iter41;
wire ap_block_state130_pp0_stage2_iter42;
wire ap_block_state133_pp0_stage2_iter43;
wire ap_block_state136_pp0_stage2_iter44;
wire ap_block_state139_pp0_stage2_iter45;
wire ap_block_state142_pp0_stage2_iter46;
wire ap_block_state145_pp0_stage2_iter47;
wire ap_block_state148_pp0_stage2_iter48;
wire ap_block_state151_pp0_stage2_iter49;
wire ap_block_state154_pp0_stage2_iter50;
wire ap_block_state157_pp0_stage2_iter51;
wire ap_block_state160_pp0_stage2_iter52;
wire ap_block_state163_pp0_stage2_iter53;
wire ap_block_state166_pp0_stage2_iter54;
wire ap_block_state169_pp0_stage2_iter55;
wire ap_block_state172_pp0_stage2_iter56;
wire ap_block_state175_pp0_stage2_iter57;
wire ap_block_state178_pp0_stage2_iter58;
wire ap_block_state181_pp0_stage2_iter59;
wire ap_block_state184_pp0_stage2_iter60;
wire ap_block_state187_pp0_stage2_iter61;
wire ap_block_state190_pp0_stage2_iter62;
wire ap_block_state193_pp0_stage2_iter63;
wire ap_block_state196_pp0_stage2_iter64;
wire ap_block_state199_pp0_stage2_iter65;
wire ap_block_state202_pp0_stage2_iter66;
wire ap_block_state205_pp0_stage2_iter67;
wire ap_block_state208_pp0_stage2_iter68;
wire ap_block_state211_pp0_stage2_iter69;
wire ap_block_state214_pp0_stage2_iter70;
wire ap_block_state217_pp0_stage2_iter71;
wire ap_block_state220_pp0_stage2_iter72;
wire ap_block_state223_pp0_stage2_iter73;
wire ap_block_state226_pp0_stage2_iter74;
wire ap_block_state229_pp0_stage2_iter75;
wire ap_block_state232_pp0_stage2_iter76;
wire ap_block_state235_pp0_stage2_iter77;
wire ap_block_state238_pp0_stage2_iter78;
wire ap_block_pp0_stage2_flag00011001;
reg [31:0] bufi_0_load_reg_1354;
reg [31:0] bufi_1_load_reg_1359;
reg [31:0] bufi_2_load_reg_1365;
reg [31:0] bufi_3_load_reg_1372;
reg [31:0] bufi_4_load_reg_1379;
wire [2:0] r_V_1_0_3_fu_1138_p2;
reg [2:0] r_V_1_0_3_reg_1456;
reg [31:0] bufi_5_load_reg_1461;
reg [31:0] bufi_6_load_reg_1467;
reg [31:0] bufw_0_0_load_reg_1512;
reg [31:0] bufw_0_1_load_reg_1519;
reg [31:0] bufw_0_2_load_reg_1526;
reg [31:0] bufw_0_3_load_reg_1533;
reg [31:0] bufw_0_4_load_reg_1540;
reg [31:0] bufw_1_0_load_reg_1547;
reg [31:0] bufi_0_load_1_reg_1554;
reg ap_enable_reg_pp0_iter1;
reg [31:0] bufw_1_1_load_reg_1559;
reg [31:0] bufi_1_load_1_reg_1566;
reg [31:0] bufw_1_2_load_reg_1572;
reg [31:0] bufi_2_load_1_reg_1579;
reg [31:0] bufw_1_3_load_reg_1586;
reg [31:0] bufi_3_load_1_reg_1592;
reg [31:0] bufi_4_load_1_reg_1599;
reg [31:0] bufi_0_load_2_reg_1606;
reg [31:0] bufi_1_load_2_reg_1611;
reg [31:0] bufi_2_load_2_reg_1617;
reg [31:0] bufi_3_load_2_reg_1624;
reg [31:0] bufi_4_load_2_reg_1631;
reg [31:0] bufi_5_load_1_reg_1673;
reg [31:0] bufi_5_load_2_reg_1679;
reg [31:0] bufi_6_load_1_reg_1685;
reg [31:0] bufi_6_load_2_reg_1690;
reg [31:0] bufw_1_4_load_reg_1735;
reg [31:0] bufw_2_0_load_reg_1742;
reg [31:0] bufw_2_1_load_reg_1749;
reg [31:0] bufw_2_2_load_reg_1756;
reg [31:0] bufw_2_3_load_reg_1763;
reg [31:0] bufw_2_4_load_reg_1770;
reg [31:0] bufw_3_0_load_reg_1777;
reg [31:0] bufi_0_load_3_reg_1784;
reg [31:0] bufw_3_1_load_reg_1789;
reg [31:0] bufi_1_load_3_reg_1795;
reg [31:0] bufi_2_load_3_reg_1801;
reg [31:0] bufi_3_load_3_reg_1808;
reg [31:0] bufi_4_load_3_reg_1815;
reg [31:0] bufi_5_load_3_reg_1857;
reg [31:0] bufi_6_load_3_reg_1863;
reg [31:0] bufw_3_2_load_reg_1868;
reg [31:0] bufw_3_3_load_reg_1875;
reg [31:0] bufw_3_4_load_reg_1882;
reg [31:0] bufw_4_0_load_reg_1889;
reg [31:0] bufi_0_load_4_reg_1896;
reg [31:0] bufw_4_1_load_reg_1901;
reg [31:0] bufi_1_load_4_reg_1908;
reg [31:0] bufw_4_2_load_reg_1914;
reg [31:0] bufi_2_load_4_reg_1921;
reg [31:0] bufw_4_3_load_reg_1928;
reg [31:0] bufi_3_load_4_reg_1935;
reg [31:0] bufw_4_4_load_reg_1942;
reg [31:0] bufi_4_load_4_reg_1949;
reg [31:0] bufi_5_load_4_reg_1956;
reg [31:0] bufi_6_load_4_reg_1962;
wire [8:0] tmp_4_fu_1190_p2;
reg [8:0] tmp_4_reg_1967;
reg [7:0] bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter3_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter4_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter5_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter6_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter7_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter8_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter9_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter10_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter11_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter12_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter13_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter14_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter15_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter16_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter17_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter18_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter19_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter20_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter21_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter22_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter23_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter24_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter25_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter26_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter27_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter28_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter29_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter30_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter31_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter32_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter33_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter34_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter35_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter36_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter37_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter38_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter39_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter40_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter41_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter42_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter43_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter44_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter45_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter46_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter47_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter48_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter49_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter50_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter51_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter52_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter53_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter54_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter55_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter56_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter57_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter58_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter59_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter60_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter61_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter62_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter63_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter64_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter65_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter66_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter67_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter68_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter69_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter70_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter71_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter72_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter73_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter74_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter75_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter76_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter77_bufo_0_addr_reg_1972;
reg [7:0] ap_reg_pp0_iter78_bufo_0_addr_reg_1972;
reg [7:0] bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter3_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter4_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter5_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter6_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter7_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter8_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter9_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter10_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter11_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter12_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter13_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter14_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter15_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter16_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter17_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter18_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter19_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter20_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter21_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter22_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter23_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter24_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter25_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter26_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter27_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter28_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter29_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter30_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter31_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter32_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter33_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter34_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter35_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter36_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter37_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter38_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter39_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter40_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter41_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter42_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter43_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter44_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter45_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter46_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter47_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter48_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter49_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter50_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter51_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter52_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter53_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter54_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter55_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter56_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter57_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter58_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter59_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter60_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter61_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter62_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter63_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter64_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter65_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter66_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter67_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter68_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter69_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter70_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter71_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter72_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter73_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter74_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter75_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter76_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter77_bufo_1_addr_reg_1978;
reg [7:0] ap_reg_pp0_iter78_bufo_1_addr_reg_1978;
reg [7:0] bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter3_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter4_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter5_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter6_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter7_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter8_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter9_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter10_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter11_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter12_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter13_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter14_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter15_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter16_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter17_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter18_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter19_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter20_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter21_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter22_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter23_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter24_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter25_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter26_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter27_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter28_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter29_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter30_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter31_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter32_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter33_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter34_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter35_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter36_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter37_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter38_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter39_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter40_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter41_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter42_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter43_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter44_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter45_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter46_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter47_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter48_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter49_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter50_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter51_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter52_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter53_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter54_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter55_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter56_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter57_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter58_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter59_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter60_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter61_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter62_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter63_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter64_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter65_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter66_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter67_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter68_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter69_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter70_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter71_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter72_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter73_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter74_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter75_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter76_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter77_bufo_2_addr_reg_1984;
reg [7:0] ap_reg_pp0_iter78_bufo_2_addr_reg_1984;
reg [31:0] bufo_0_load_reg_1990;
reg ap_enable_reg_pp0_iter2;
wire [31:0] grp_fu_944_p2;
reg [31:0] tmp_s_reg_1995;
wire [31:0] grp_fu_948_p2;
reg [31:0] tmp_10_0_0_1_reg_2000;
reg [31:0] ap_reg_pp0_iter3_tmp_10_0_0_1_reg_2000;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_0_1_reg_2000;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_0_1_reg_2000;
wire [31:0] grp_fu_952_p2;
reg [31:0] tmp_10_0_0_2_reg_2005;
reg [31:0] ap_reg_pp0_iter3_tmp_10_0_0_2_reg_2005;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_0_2_reg_2005;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_0_2_reg_2005;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_0_2_reg_2005;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_0_2_reg_2005;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_0_2_reg_2005;
wire [31:0] grp_fu_956_p2;
reg [31:0] tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter3_tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_0_3_reg_2010;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_0_3_reg_2010;
wire [31:0] grp_fu_960_p2;
reg [31:0] tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter3_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_0_4_reg_2015;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_0_4_reg_2015;
wire [31:0] grp_fu_964_p2;
reg [31:0] tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter3_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_1_reg_2020;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_1_reg_2020;
wire [31:0] grp_fu_968_p2;
reg [31:0] tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter3_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_1_1_reg_2025;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_1_1_reg_2025;
wire [31:0] grp_fu_972_p2;
reg [31:0] tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter3_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_1_2_reg_2030;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_1_2_reg_2030;
wire [31:0] grp_fu_976_p2;
reg [31:0] tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter3_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_1_3_reg_2035;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_1_3_reg_2035;
reg [31:0] bufo_1_load_reg_2040;
wire [31:0] grp_fu_980_p2;
reg [31:0] tmp_10_1_reg_2045;
wire [31:0] grp_fu_984_p2;
reg [31:0] tmp_10_1_0_1_reg_2050;
reg [31:0] ap_reg_pp0_iter3_tmp_10_1_0_1_reg_2050;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_0_1_reg_2050;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_0_1_reg_2050;
wire [31:0] grp_fu_988_p2;
reg [31:0] tmp_10_1_0_2_reg_2055;
reg [31:0] ap_reg_pp0_iter3_tmp_10_1_0_2_reg_2055;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_0_2_reg_2055;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_0_2_reg_2055;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_0_2_reg_2055;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_0_2_reg_2055;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_0_2_reg_2055;
wire [31:0] grp_fu_992_p2;
reg [31:0] tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter3_tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_0_3_reg_2060;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_0_3_reg_2060;
wire [31:0] grp_fu_996_p2;
reg [31:0] tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter3_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_0_4_reg_2065;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_0_4_reg_2065;
wire [31:0] grp_fu_1000_p2;
reg [31:0] tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter3_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_1_reg_2070;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_1_reg_2070;
wire [31:0] grp_fu_1004_p2;
reg [31:0] tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter3_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_1_1_reg_2075;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_1_1_reg_2075;
wire [31:0] grp_fu_1008_p2;
reg [31:0] tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter3_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_1_2_reg_2080;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_1_2_reg_2080;
reg [31:0] bufo_2_load_reg_2085;
wire [31:0] grp_fu_1012_p2;
reg [31:0] tmp_10_2_reg_2090;
wire [31:0] grp_fu_1016_p2;
reg [31:0] tmp_10_2_0_1_reg_2095;
reg [31:0] ap_reg_pp0_iter3_tmp_10_2_0_1_reg_2095;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_0_1_reg_2095;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_0_1_reg_2095;
wire [31:0] grp_fu_1020_p2;
reg [31:0] tmp_10_2_0_2_reg_2100;
reg [31:0] ap_reg_pp0_iter3_tmp_10_2_0_2_reg_2100;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_0_2_reg_2100;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_0_2_reg_2100;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_0_2_reg_2100;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_0_2_reg_2100;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_0_2_reg_2100;
wire [31:0] grp_fu_1024_p2;
reg [31:0] tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter3_tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_0_3_reg_2105;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_0_3_reg_2105;
wire [31:0] grp_fu_1028_p2;
reg [31:0] tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter3_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_0_4_reg_2110;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_0_4_reg_2110;
wire [31:0] grp_fu_1032_p2;
reg [31:0] tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter3_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_1_reg_2115;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_1_reg_2115;
wire [31:0] grp_fu_1036_p2;
reg [31:0] tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter3_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_1_1_reg_2120;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_1_1_reg_2120;
wire [31:0] grp_fu_1040_p2;
reg [31:0] tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter3_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_1_2_reg_2125;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_1_2_reg_2125;
reg [31:0] tmp_10_0_1_4_reg_2130;
reg ap_enable_reg_pp0_iter3;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_1_4_reg_2130;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_1_4_reg_2130;
reg [31:0] tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_2_reg_2135;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_2_reg_2135;
reg [31:0] tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_2_1_reg_2140;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_2_1_reg_2140;
reg [31:0] tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_2_2_reg_2145;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_2_2_reg_2145;
reg [31:0] tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_2_3_reg_2150;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_2_3_reg_2150;
reg [31:0] tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_2_4_reg_2155;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_2_4_reg_2155;
reg [31:0] tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_3_reg_2160;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_3_reg_2160;
reg [31:0] tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_3_1_reg_2165;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_3_1_reg_2165;
reg [31:0] tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_1_3_reg_2170;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_1_3_reg_2170;
reg [31:0] tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_1_4_reg_2175;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_1_4_reg_2175;
reg [31:0] tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_2_reg_2180;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_2_reg_2180;
reg [31:0] tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_2_1_reg_2185;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_2_1_reg_2185;
reg [31:0] tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_2_2_reg_2190;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_2_2_reg_2190;
reg [31:0] tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_2_3_reg_2195;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_2_3_reg_2195;
reg [31:0] tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_2_4_reg_2200;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_2_4_reg_2200;
reg [31:0] tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_3_reg_2205;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_3_reg_2205;
reg [31:0] tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_3_1_reg_2210;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_3_1_reg_2210;
reg [31:0] tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_1_3_reg_2215;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_1_3_reg_2215;
reg [31:0] tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_1_4_reg_2220;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_1_4_reg_2220;
reg [31:0] tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_2_reg_2225;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_2_reg_2225;
reg [31:0] tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_2_1_reg_2230;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_2_1_reg_2230;
reg [31:0] tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_2_2_reg_2235;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_2_2_reg_2235;
reg [31:0] tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_2_3_reg_2240;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_2_3_reg_2240;
reg [31:0] tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_2_4_reg_2245;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_2_4_reg_2245;
reg [31:0] tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_3_reg_2250;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_3_reg_2250;
reg [31:0] tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter52_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter53_tmp_10_0_3_2_reg_2255;
reg [31:0] ap_reg_pp0_iter54_tmp_10_0_3_2_reg_2255;
reg [31:0] tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter52_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter53_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter54_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter55_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter56_tmp_10_0_3_3_reg_2260;
reg [31:0] ap_reg_pp0_iter57_tmp_10_0_3_3_reg_2260;
reg [31:0] tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter52_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter53_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter54_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter55_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter56_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter57_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter58_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter59_tmp_10_0_3_4_reg_2265;
reg [31:0] ap_reg_pp0_iter60_tmp_10_0_3_4_reg_2265;
reg [31:0] tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter52_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter53_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter54_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter55_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter56_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter57_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter58_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter59_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter60_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter61_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter62_tmp_10_0_4_reg_2270;
reg [31:0] ap_reg_pp0_iter63_tmp_10_0_4_reg_2270;
reg [31:0] tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter52_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter53_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter54_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter55_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter56_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter57_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter58_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter59_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter60_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter61_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter62_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter63_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter64_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter65_tmp_10_0_4_1_reg_2275;
reg [31:0] ap_reg_pp0_iter66_tmp_10_0_4_1_reg_2275;
reg [31:0] tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter52_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter53_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter54_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter55_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter56_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter57_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter58_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter59_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter60_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter61_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter62_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter63_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter64_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter65_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter66_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter67_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter68_tmp_10_0_4_2_reg_2280;
reg [31:0] ap_reg_pp0_iter69_tmp_10_0_4_2_reg_2280;
reg [31:0] tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter52_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter53_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter54_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter55_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter56_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter57_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter58_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter59_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter60_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter61_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter62_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter63_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter64_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter65_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter66_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter67_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter68_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter69_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter70_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter71_tmp_10_0_4_3_reg_2285;
reg [31:0] ap_reg_pp0_iter72_tmp_10_0_4_3_reg_2285;
reg [31:0] tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter4_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter5_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter6_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter7_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter8_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter9_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter10_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter11_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter12_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter13_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter14_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter15_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter16_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter17_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter18_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter19_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter20_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter21_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter22_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter23_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter24_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter25_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter26_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter27_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter28_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter29_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter30_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter31_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter32_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter33_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter34_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter35_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter36_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter37_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter38_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter39_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter40_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter41_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter42_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter43_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter44_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter45_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter46_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter47_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter48_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter49_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter50_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter51_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter52_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter53_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter54_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter55_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter56_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter57_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter58_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter59_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter60_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter61_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter62_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter63_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter64_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter65_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter66_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter67_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter68_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter69_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter70_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter71_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter72_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter73_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter74_tmp_10_0_4_4_reg_2290;
reg [31:0] ap_reg_pp0_iter75_tmp_10_0_4_4_reg_2290;
reg [31:0] tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter52_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter53_tmp_10_1_3_2_reg_2295;
reg [31:0] ap_reg_pp0_iter54_tmp_10_1_3_2_reg_2295;
reg [31:0] tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter52_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter53_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter54_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter55_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter56_tmp_10_1_3_3_reg_2300;
reg [31:0] ap_reg_pp0_iter57_tmp_10_1_3_3_reg_2300;
reg [31:0] tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter52_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter53_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter54_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter55_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter56_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter57_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter58_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter59_tmp_10_1_3_4_reg_2305;
reg [31:0] ap_reg_pp0_iter60_tmp_10_1_3_4_reg_2305;
reg [31:0] tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter52_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter53_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter54_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter55_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter56_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter57_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter58_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter59_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter60_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter61_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter62_tmp_10_1_4_reg_2310;
reg [31:0] ap_reg_pp0_iter63_tmp_10_1_4_reg_2310;
reg [31:0] tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter52_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter53_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter54_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter55_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter56_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter57_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter58_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter59_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter60_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter61_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter62_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter63_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter64_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter65_tmp_10_1_4_1_reg_2315;
reg [31:0] ap_reg_pp0_iter66_tmp_10_1_4_1_reg_2315;
reg [31:0] tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter52_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter53_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter54_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter55_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter56_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter57_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter58_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter59_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter60_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter61_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter62_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter63_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter64_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter65_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter66_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter67_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter68_tmp_10_1_4_2_reg_2320;
reg [31:0] ap_reg_pp0_iter69_tmp_10_1_4_2_reg_2320;
reg [31:0] tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter52_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter53_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter54_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter55_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter56_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter57_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter58_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter59_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter60_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter61_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter62_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter63_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter64_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter65_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter66_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter67_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter68_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter69_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter70_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter71_tmp_10_1_4_3_reg_2325;
reg [31:0] ap_reg_pp0_iter72_tmp_10_1_4_3_reg_2325;
reg [31:0] tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter4_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter5_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter6_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter7_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter8_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter9_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter10_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter11_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter12_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter13_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter14_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter15_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter16_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter17_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter18_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter19_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter20_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter21_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter22_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter23_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter24_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter25_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter26_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter27_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter28_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter29_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter30_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter31_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter32_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter33_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter34_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter35_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter36_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter37_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter38_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter39_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter40_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter41_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter42_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter43_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter44_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter45_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter46_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter47_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter48_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter49_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter50_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter51_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter52_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter53_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter54_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter55_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter56_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter57_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter58_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter59_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter60_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter61_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter62_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter63_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter64_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter65_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter66_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter67_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter68_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter69_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter70_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter71_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter72_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter73_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter74_tmp_10_1_4_4_reg_2330;
reg [31:0] ap_reg_pp0_iter75_tmp_10_1_4_4_reg_2330;
reg [31:0] tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_3_1_reg_2335;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_3_1_reg_2335;
reg [31:0] tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter52_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter53_tmp_10_2_3_2_reg_2340;
reg [31:0] ap_reg_pp0_iter54_tmp_10_2_3_2_reg_2340;
reg [31:0] tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter52_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter53_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter54_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter55_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter56_tmp_10_2_3_3_reg_2345;
reg [31:0] ap_reg_pp0_iter57_tmp_10_2_3_3_reg_2345;
reg [31:0] tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter52_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter53_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter54_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter55_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter56_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter57_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter58_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter59_tmp_10_2_3_4_reg_2350;
reg [31:0] ap_reg_pp0_iter60_tmp_10_2_3_4_reg_2350;
reg [31:0] tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter52_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter53_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter54_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter55_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter56_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter57_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter58_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter59_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter60_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter61_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter62_tmp_10_2_4_reg_2355;
reg [31:0] ap_reg_pp0_iter63_tmp_10_2_4_reg_2355;
reg [31:0] tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter52_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter53_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter54_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter55_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter56_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter57_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter58_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter59_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter60_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter61_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter62_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter63_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter64_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter65_tmp_10_2_4_1_reg_2360;
reg [31:0] ap_reg_pp0_iter66_tmp_10_2_4_1_reg_2360;
reg [31:0] tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter52_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter53_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter54_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter55_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter56_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter57_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter58_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter59_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter60_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter61_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter62_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter63_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter64_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter65_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter66_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter67_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter68_tmp_10_2_4_2_reg_2365;
reg [31:0] ap_reg_pp0_iter69_tmp_10_2_4_2_reg_2365;
reg [31:0] tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter52_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter53_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter54_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter55_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter56_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter57_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter58_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter59_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter60_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter61_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter62_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter63_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter64_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter65_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter66_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter67_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter68_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter69_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter70_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter71_tmp_10_2_4_3_reg_2370;
reg [31:0] ap_reg_pp0_iter72_tmp_10_2_4_3_reg_2370;
reg [31:0] tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter4_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter5_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter6_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter7_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter8_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter9_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter10_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter11_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter12_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter13_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter14_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter15_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter16_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter17_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter18_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter19_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter20_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter21_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter22_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter23_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter24_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter25_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter26_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter27_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter28_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter29_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter30_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter31_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter32_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter33_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter34_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter35_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter36_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter37_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter38_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter39_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter40_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter41_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter42_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter43_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter44_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter45_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter46_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter47_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter48_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter49_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter50_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter51_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter52_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter53_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter54_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter55_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter56_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter57_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter58_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter59_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter60_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter61_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter62_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter63_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter64_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter65_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter66_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter67_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter68_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter69_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter70_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter71_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter72_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter73_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter74_tmp_10_2_4_4_reg_2375;
reg [31:0] ap_reg_pp0_iter75_tmp_10_2_4_4_reg_2375;
wire [31:0] grp_fu_844_p2;
reg [31:0] temp_2_reg_2380;
reg ap_enable_reg_pp0_iter5;
wire [31:0] grp_fu_848_p2;
reg [31:0] temp_2_1_reg_2385;
wire [31:0] grp_fu_852_p2;
reg [31:0] temp_2_2_reg_2390;
wire [31:0] grp_fu_856_p2;
reg [31:0] temp_2_0_0_1_reg_2395;
reg ap_enable_reg_pp0_iter8;
wire [31:0] grp_fu_860_p2;
reg [31:0] temp_2_1_0_1_reg_2400;
wire [31:0] grp_fu_864_p2;
reg [31:0] temp_2_2_0_1_reg_2405;
wire [31:0] grp_fu_868_p2;
reg [31:0] temp_2_0_0_2_reg_2410;
reg ap_enable_reg_pp0_iter11;
wire [31:0] grp_fu_872_p2;
reg [31:0] temp_2_1_0_2_reg_2415;
wire [31:0] grp_fu_876_p2;
reg [31:0] temp_2_2_0_2_reg_2420;
wire [31:0] grp_fu_880_p2;
reg [31:0] temp_2_0_0_3_reg_2425;
reg ap_enable_reg_pp0_iter14;
wire [31:0] grp_fu_884_p2;
reg [31:0] temp_2_1_0_3_reg_2430;
wire [31:0] grp_fu_888_p2;
reg [31:0] temp_2_2_0_3_reg_2435;
wire [31:0] grp_fu_892_p2;
reg [31:0] temp_2_0_0_4_reg_2440;
reg ap_enable_reg_pp0_iter17;
wire [31:0] grp_fu_896_p2;
reg [31:0] temp_2_1_0_4_reg_2445;
wire [31:0] grp_fu_900_p2;
reg [31:0] temp_2_2_0_4_reg_2450;
wire [31:0] grp_fu_904_p2;
reg [31:0] temp_2_0_1_reg_2455;
reg ap_enable_reg_pp0_iter20;
wire [31:0] grp_fu_908_p2;
reg [31:0] temp_2_1_1_reg_2460;
wire [31:0] grp_fu_912_p2;
reg [31:0] temp_2_2_1_reg_2465;
wire [31:0] grp_fu_916_p2;
reg [31:0] temp_2_0_1_1_reg_2470;
reg ap_enable_reg_pp0_iter23;
wire [31:0] grp_fu_920_p2;
reg [31:0] temp_2_1_1_1_reg_2475;
wire [31:0] grp_fu_924_p2;
reg [31:0] temp_2_2_1_1_reg_2480;
wire [31:0] grp_fu_928_p2;
reg [31:0] temp_2_0_1_2_reg_2485;
reg ap_enable_reg_pp0_iter26;
wire [31:0] grp_fu_932_p2;
reg [31:0] temp_2_1_1_2_reg_2490;
wire [31:0] grp_fu_936_p2;
reg [31:0] temp_2_2_1_2_reg_2495;
wire [31:0] grp_fu_940_p2;
reg [31:0] temp_2_0_1_3_reg_2500;
reg ap_enable_reg_pp0_iter29;
reg [31:0] temp_2_1_1_3_reg_2505;
reg ap_enable_reg_pp0_iter30;
reg [31:0] temp_2_2_1_3_reg_2510;
reg [31:0] temp_2_0_1_4_reg_2515;
reg ap_enable_reg_pp0_iter33;
reg [31:0] temp_2_1_1_4_reg_2520;
reg [31:0] temp_2_2_1_4_reg_2525;
reg [31:0] temp_2_0_2_reg_2530;
reg ap_enable_reg_pp0_iter36;
reg [31:0] temp_2_1_2_reg_2535;
reg [31:0] temp_2_2_2_reg_2540;
reg [31:0] temp_2_0_2_1_reg_2545;
reg ap_enable_reg_pp0_iter39;
reg [31:0] temp_2_1_2_1_reg_2550;
reg [31:0] temp_2_2_2_1_reg_2555;
reg [31:0] temp_2_0_2_2_reg_2560;
reg ap_enable_reg_pp0_iter42;
reg [31:0] temp_2_1_2_2_reg_2565;
reg [31:0] temp_2_2_2_2_reg_2570;
reg [31:0] temp_2_0_2_3_reg_2575;
reg ap_enable_reg_pp0_iter45;
reg [31:0] temp_2_1_2_3_reg_2580;
reg [31:0] temp_2_2_2_3_reg_2585;
reg [31:0] temp_2_0_2_4_reg_2590;
reg ap_enable_reg_pp0_iter48;
reg [31:0] temp_2_1_2_4_reg_2595;
reg [31:0] temp_2_2_2_4_reg_2600;
reg [31:0] temp_2_0_3_reg_2605;
reg ap_enable_reg_pp0_iter51;
reg [31:0] temp_2_1_3_reg_2610;
reg [31:0] temp_2_2_3_reg_2615;
reg [31:0] temp_2_0_3_1_reg_2620;
reg ap_enable_reg_pp0_iter54;
reg [31:0] temp_2_1_3_1_reg_2625;
reg [31:0] temp_2_2_3_1_reg_2630;
reg [31:0] temp_2_0_3_2_reg_2635;
reg ap_enable_reg_pp0_iter57;
reg [31:0] temp_2_1_3_2_reg_2640;
reg [31:0] temp_2_2_3_2_reg_2645;
reg [31:0] temp_2_0_3_3_reg_2650;
reg ap_enable_reg_pp0_iter60;
reg [31:0] temp_2_1_3_3_reg_2655;
reg [31:0] temp_2_2_3_3_reg_2660;
reg [31:0] temp_2_0_3_4_reg_2665;
reg ap_enable_reg_pp0_iter63;
reg [31:0] temp_2_1_3_4_reg_2670;
reg [31:0] temp_2_2_3_4_reg_2675;
reg [31:0] temp_2_0_4_reg_2680;
reg ap_enable_reg_pp0_iter66;
reg [31:0] temp_2_1_4_reg_2685;
reg [31:0] temp_2_2_4_reg_2690;
reg [31:0] temp_2_0_4_1_reg_2695;
reg ap_enable_reg_pp0_iter69;
reg [31:0] temp_2_1_4_1_reg_2700;
reg [31:0] temp_2_2_4_1_reg_2705;
reg [31:0] temp_2_0_4_2_reg_2710;
reg ap_enable_reg_pp0_iter72;
reg [31:0] temp_2_1_4_2_reg_2715;
reg [31:0] temp_2_2_4_2_reg_2720;
reg [31:0] temp_2_0_4_3_reg_2725;
reg ap_enable_reg_pp0_iter75;
reg [31:0] temp_2_1_4_3_reg_2730;
reg [31:0] temp_2_2_4_3_reg_2735;
reg [31:0] temp_2_0_4_4_reg_2740;
reg ap_enable_reg_pp0_iter78;
reg [31:0] temp_2_1_4_4_reg_2745;
reg [31:0] temp_2_2_4_4_reg_2750;
wire ap_block_pp0_stage0_flag00011011;
reg ap_condition_pp0_exit_iter0_state2;
wire ap_block_pp0_stage2_flag00011011;
reg ap_enable_reg_pp0_iter4;
reg ap_enable_reg_pp0_iter6;
reg ap_enable_reg_pp0_iter7;
reg ap_enable_reg_pp0_iter9;
reg ap_enable_reg_pp0_iter10;
reg ap_enable_reg_pp0_iter12;
reg ap_enable_reg_pp0_iter13;
reg ap_enable_reg_pp0_iter15;
reg ap_enable_reg_pp0_iter16;
reg ap_enable_reg_pp0_iter18;
reg ap_enable_reg_pp0_iter19;
reg ap_enable_reg_pp0_iter21;
reg ap_enable_reg_pp0_iter22;
reg ap_enable_reg_pp0_iter24;
reg ap_enable_reg_pp0_iter25;
reg ap_enable_reg_pp0_iter27;
reg ap_enable_reg_pp0_iter28;
reg ap_enable_reg_pp0_iter31;
reg ap_enable_reg_pp0_iter32;
reg ap_enable_reg_pp0_iter34;
reg ap_enable_reg_pp0_iter35;
reg ap_enable_reg_pp0_iter37;
reg ap_enable_reg_pp0_iter38;
reg ap_enable_reg_pp0_iter40;
reg ap_enable_reg_pp0_iter41;
reg ap_enable_reg_pp0_iter43;
reg ap_enable_reg_pp0_iter44;
reg ap_enable_reg_pp0_iter46;
reg ap_enable_reg_pp0_iter47;
reg ap_enable_reg_pp0_iter49;
reg ap_enable_reg_pp0_iter50;
reg ap_enable_reg_pp0_iter52;
reg ap_enable_reg_pp0_iter53;
reg ap_enable_reg_pp0_iter55;
reg ap_enable_reg_pp0_iter56;
reg ap_enable_reg_pp0_iter58;
reg ap_enable_reg_pp0_iter59;
reg ap_enable_reg_pp0_iter61;
reg ap_enable_reg_pp0_iter62;
reg ap_enable_reg_pp0_iter64;
reg ap_enable_reg_pp0_iter65;
reg ap_enable_reg_pp0_iter67;
reg ap_enable_reg_pp0_iter68;
reg ap_enable_reg_pp0_iter70;
reg ap_enable_reg_pp0_iter71;
reg ap_enable_reg_pp0_iter73;
reg ap_enable_reg_pp0_iter74;
reg ap_enable_reg_pp0_iter76;
reg ap_enable_reg_pp0_iter77;
reg [7:0] indvar_flatten_phi_fu_814_p4;
wire ap_block_pp0_stage0_flag00000000;
reg [6:0] p_s_phi_fu_825_p4;
reg [1:0] p_1_phi_fu_837_p4;
wire [63:0] tmp_3_fu_1082_p1;
wire ap_block_pp0_stage1_flag00000000;
wire ap_block_pp0_stage2_flag00000000;
wire [63:0] tmp_2_0_1_fu_1118_p1;
wire [63:0] tmp_2_0_2_fu_1128_p1;
wire [63:0] tmp_2_0_3_fu_1143_p1;
wire [63:0] tmp_2_0_4_fu_1160_p1;
wire signed [63:0] tmp_4_cast_fu_1196_p1;
reg [31:0] bufi_0_Addr_A_orig;
reg [31:0] bufi_0_Addr_B_orig;
reg [31:0] bufi_1_Addr_A_orig;
reg [31:0] bufi_1_Addr_B_orig;
reg [31:0] bufi_2_Addr_A_orig;
reg [31:0] bufi_2_Addr_B_orig;
reg [31:0] bufi_3_Addr_A_orig;
reg [31:0] bufi_3_Addr_B_orig;
reg [31:0] bufi_4_Addr_A_orig;
reg [31:0] bufi_4_Addr_B_orig;
reg [31:0] bufi_5_Addr_A_orig;
reg [31:0] bufi_5_Addr_B_orig;
reg [31:0] bufi_6_Addr_A_orig;
reg [31:0] bufi_6_Addr_B_orig;
wire [31:0] bufw_0_0_Addr_A_orig;
wire [31:0] bufw_0_1_Addr_A_orig;
wire [31:0] bufw_0_2_Addr_A_orig;
wire [31:0] bufw_0_3_Addr_A_orig;
wire [31:0] bufw_0_4_Addr_A_orig;
wire [31:0] bufw_1_0_Addr_A_orig;
wire [31:0] bufw_1_1_Addr_A_orig;
wire [31:0] bufw_1_2_Addr_A_orig;
wire [31:0] bufw_1_3_Addr_A_orig;
wire [31:0] bufw_1_4_Addr_A_orig;
wire [31:0] bufw_2_0_Addr_A_orig;
wire [31:0] bufw_2_1_Addr_A_orig;
wire [31:0] bufw_2_2_Addr_A_orig;
wire [31:0] bufw_2_3_Addr_A_orig;
wire [31:0] bufw_2_4_Addr_A_orig;
wire [31:0] bufw_3_0_Addr_A_orig;
wire [31:0] bufw_3_1_Addr_A_orig;
wire [31:0] bufw_3_2_Addr_A_orig;
wire [31:0] bufw_3_3_Addr_A_orig;
wire [31:0] bufw_3_4_Addr_A_orig;
wire [31:0] bufw_4_0_Addr_A_orig;
wire [31:0] bufw_4_1_Addr_A_orig;
wire [31:0] bufw_4_2_Addr_A_orig;
wire [31:0] bufw_4_3_Addr_A_orig;
wire [31:0] bufw_4_4_Addr_A_orig;
wire [31:0] bufo_0_Addr_A_orig;
wire [31:0] bufo_0_Addr_B_orig;
wire [31:0] bufo_1_Addr_A_orig;
wire [31:0] bufo_1_Addr_B_orig;
wire [31:0] bufo_2_Addr_A_orig;
wire [31:0] bufo_2_Addr_B_orig;
reg [31:0] grp_fu_844_p0;
reg [31:0] grp_fu_844_p1;
reg [31:0] grp_fu_848_p0;
reg [31:0] grp_fu_848_p1;
reg [31:0] grp_fu_852_p0;
reg [31:0] grp_fu_852_p1;
reg [31:0] grp_fu_856_p0;
reg [31:0] grp_fu_856_p1;
reg [31:0] grp_fu_860_p0;
reg [31:0] grp_fu_860_p1;
reg [31:0] grp_fu_864_p0;
reg [31:0] grp_fu_864_p1;
reg [31:0] grp_fu_868_p0;
reg [31:0] grp_fu_868_p1;
reg [31:0] grp_fu_872_p0;
reg [31:0] grp_fu_872_p1;
reg [31:0] grp_fu_876_p0;
reg [31:0] grp_fu_876_p1;
reg [31:0] grp_fu_880_p0;
reg [31:0] grp_fu_880_p1;
reg [31:0] grp_fu_884_p0;
reg [31:0] grp_fu_884_p1;
reg [31:0] grp_fu_888_p0;
reg [31:0] grp_fu_888_p1;
reg [31:0] grp_fu_892_p0;
reg [31:0] grp_fu_892_p1;
reg [31:0] grp_fu_896_p0;
reg [31:0] grp_fu_896_p1;
reg [31:0] grp_fu_900_p0;
reg [31:0] grp_fu_900_p1;
reg [31:0] grp_fu_904_p0;
reg [31:0] grp_fu_904_p1;
reg [31:0] grp_fu_908_p0;
reg [31:0] grp_fu_908_p1;
reg [31:0] grp_fu_912_p0;
reg [31:0] grp_fu_912_p1;
reg [31:0] grp_fu_916_p0;
reg [31:0] grp_fu_916_p1;
reg [31:0] grp_fu_920_p0;
reg [31:0] grp_fu_920_p1;
reg [31:0] grp_fu_924_p0;
reg [31:0] grp_fu_924_p1;
reg [31:0] grp_fu_928_p0;
reg [31:0] grp_fu_928_p1;
reg [31:0] grp_fu_932_p0;
reg [31:0] grp_fu_932_p1;
reg [31:0] grp_fu_936_p0;
reg [31:0] grp_fu_936_p1;
reg [31:0] grp_fu_940_p0;
reg [31:0] grp_fu_940_p1;
reg [31:0] grp_fu_944_p0;
reg [31:0] grp_fu_944_p1;
reg [31:0] grp_fu_948_p0;
reg [31:0] grp_fu_948_p1;
reg [31:0] grp_fu_952_p0;
reg [31:0] grp_fu_952_p1;
reg [31:0] grp_fu_956_p0;
reg [31:0] grp_fu_956_p1;
reg [31:0] grp_fu_960_p0;
reg [31:0] grp_fu_960_p1;
reg [31:0] grp_fu_964_p0;
reg [31:0] grp_fu_964_p1;
reg [31:0] grp_fu_968_p0;
reg [31:0] grp_fu_968_p1;
reg [31:0] grp_fu_972_p0;
reg [31:0] grp_fu_972_p1;
reg [31:0] grp_fu_976_p0;
reg [31:0] grp_fu_976_p1;
reg [31:0] grp_fu_980_p0;
reg [31:0] grp_fu_980_p1;
reg [31:0] grp_fu_984_p0;
reg [31:0] grp_fu_984_p1;
reg [31:0] grp_fu_988_p0;
reg [31:0] grp_fu_988_p1;
reg [31:0] grp_fu_992_p0;
reg [31:0] grp_fu_992_p1;
reg [31:0] grp_fu_996_p0;
reg [31:0] grp_fu_996_p1;
reg [31:0] grp_fu_1000_p0;
reg [31:0] grp_fu_1000_p1;
reg [31:0] grp_fu_1004_p0;
reg [31:0] grp_fu_1004_p1;
reg [31:0] grp_fu_1008_p0;
reg [31:0] grp_fu_1008_p1;
reg [31:0] grp_fu_1012_p0;
reg [31:0] grp_fu_1012_p1;
reg [31:0] grp_fu_1016_p0;
reg [31:0] grp_fu_1016_p1;
reg [31:0] grp_fu_1020_p0;
reg [31:0] grp_fu_1020_p1;
reg [31:0] grp_fu_1024_p0;
reg [31:0] grp_fu_1024_p1;
reg [31:0] grp_fu_1028_p0;
reg [31:0] grp_fu_1028_p1;
reg [31:0] grp_fu_1032_p0;
reg [31:0] grp_fu_1032_p1;
reg [31:0] grp_fu_1036_p0;
reg [31:0] grp_fu_1036_p1;
reg [31:0] grp_fu_1040_p0;
reg [31:0] grp_fu_1040_p1;
wire [2:0] r_V_1_0_s_fu_1153_p3;
wire [8:0] tmp_fu_1174_p3;
wire [8:0] tmp_mid2_cast_fu_1171_p1;
wire [8:0] tmp_2_fu_1181_p2;
wire [8:0] tmp_3_cast_fu_1187_p1;
wire ap_CS_fsm_state239;
reg [4:0] ap_NS_fsm;
wire ap_block_pp0_stage1_flag00011011;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 5'd1;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter11 = 1'b0;
#0 ap_enable_reg_pp0_iter14 = 1'b0;
#0 ap_enable_reg_pp0_iter17 = 1'b0;
#0 ap_enable_reg_pp0_iter20 = 1'b0;
#0 ap_enable_reg_pp0_iter23 = 1'b0;
#0 ap_enable_reg_pp0_iter26 = 1'b0;
#0 ap_enable_reg_pp0_iter29 = 1'b0;
#0 ap_enable_reg_pp0_iter30 = 1'b0;
#0 ap_enable_reg_pp0_iter33 = 1'b0;
#0 ap_enable_reg_pp0_iter36 = 1'b0;
#0 ap_enable_reg_pp0_iter39 = 1'b0;
#0 ap_enable_reg_pp0_iter42 = 1'b0;
#0 ap_enable_reg_pp0_iter45 = 1'b0;
#0 ap_enable_reg_pp0_iter48 = 1'b0;
#0 ap_enable_reg_pp0_iter51 = 1'b0;
#0 ap_enable_reg_pp0_iter54 = 1'b0;
#0 ap_enable_reg_pp0_iter57 = 1'b0;
#0 ap_enable_reg_pp0_iter60 = 1'b0;
#0 ap_enable_reg_pp0_iter63 = 1'b0;
#0 ap_enable_reg_pp0_iter66 = 1'b0;
#0 ap_enable_reg_pp0_iter69 = 1'b0;
#0 ap_enable_reg_pp0_iter72 = 1'b0;
#0 ap_enable_reg_pp0_iter75 = 1'b0;
#0 ap_enable_reg_pp0_iter78 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
#0 ap_enable_reg_pp0_iter10 = 1'b0;
#0 ap_enable_reg_pp0_iter12 = 1'b0;
#0 ap_enable_reg_pp0_iter13 = 1'b0;
#0 ap_enable_reg_pp0_iter15 = 1'b0;
#0 ap_enable_reg_pp0_iter16 = 1'b0;
#0 ap_enable_reg_pp0_iter18 = 1'b0;
#0 ap_enable_reg_pp0_iter19 = 1'b0;
#0 ap_enable_reg_pp0_iter21 = 1'b0;
#0 ap_enable_reg_pp0_iter22 = 1'b0;
#0 ap_enable_reg_pp0_iter24 = 1'b0;
#0 ap_enable_reg_pp0_iter25 = 1'b0;
#0 ap_enable_reg_pp0_iter27 = 1'b0;
#0 ap_enable_reg_pp0_iter28 = 1'b0;
#0 ap_enable_reg_pp0_iter31 = 1'b0;
#0 ap_enable_reg_pp0_iter32 = 1'b0;
#0 ap_enable_reg_pp0_iter34 = 1'b0;
#0 ap_enable_reg_pp0_iter35 = 1'b0;
#0 ap_enable_reg_pp0_iter37 = 1'b0;
#0 ap_enable_reg_pp0_iter38 = 1'b0;
#0 ap_enable_reg_pp0_iter40 = 1'b0;
#0 ap_enable_reg_pp0_iter41 = 1'b0;
#0 ap_enable_reg_pp0_iter43 = 1'b0;
#0 ap_enable_reg_pp0_iter44 = 1'b0;
#0 ap_enable_reg_pp0_iter46 = 1'b0;
#0 ap_enable_reg_pp0_iter47 = 1'b0;
#0 ap_enable_reg_pp0_iter49 = 1'b0;
#0 ap_enable_reg_pp0_iter50 = 1'b0;
#0 ap_enable_reg_pp0_iter52 = 1'b0;
#0 ap_enable_reg_pp0_iter53 = 1'b0;
#0 ap_enable_reg_pp0_iter55 = 1'b0;
#0 ap_enable_reg_pp0_iter56 = 1'b0;
#0 ap_enable_reg_pp0_iter58 = 1'b0;
#0 ap_enable_reg_pp0_iter59 = 1'b0;
#0 ap_enable_reg_pp0_iter61 = 1'b0;
#0 ap_enable_reg_pp0_iter62 = 1'b0;
#0 ap_enable_reg_pp0_iter64 = 1'b0;
#0 ap_enable_reg_pp0_iter65 = 1'b0;
#0 ap_enable_reg_pp0_iter67 = 1'b0;
#0 ap_enable_reg_pp0_iter68 = 1'b0;
#0 ap_enable_reg_pp0_iter70 = 1'b0;
#0 ap_enable_reg_pp0_iter71 = 1'b0;
#0 ap_enable_reg_pp0_iter73 = 1'b0;
#0 ap_enable_reg_pp0_iter74 = 1'b0;
#0 ap_enable_reg_pp0_iter76 = 1'b0;
#0 ap_enable_reg_pp0_iter77 = 1'b0;
end
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U1(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_844_p0),
.din1(grp_fu_844_p1),
.ce(1'b1),
.dout(grp_fu_844_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U2(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_848_p0),
.din1(grp_fu_848_p1),
.ce(1'b1),
.dout(grp_fu_848_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U3(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_852_p0),
.din1(grp_fu_852_p1),
.ce(1'b1),
.dout(grp_fu_852_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U4(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_856_p0),
.din1(grp_fu_856_p1),
.ce(1'b1),
.dout(grp_fu_856_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U5(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_860_p0),
.din1(grp_fu_860_p1),
.ce(1'b1),
.dout(grp_fu_860_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U6(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_864_p0),
.din1(grp_fu_864_p1),
.ce(1'b1),
.dout(grp_fu_864_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U7(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_868_p0),
.din1(grp_fu_868_p1),
.ce(1'b1),
.dout(grp_fu_868_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U8(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_872_p0),
.din1(grp_fu_872_p1),
.ce(1'b1),
.dout(grp_fu_872_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U9(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_876_p0),
.din1(grp_fu_876_p1),
.ce(1'b1),
.dout(grp_fu_876_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U10(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_880_p0),
.din1(grp_fu_880_p1),
.ce(1'b1),
.dout(grp_fu_880_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U11(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_884_p0),
.din1(grp_fu_884_p1),
.ce(1'b1),
.dout(grp_fu_884_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U12(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_888_p0),
.din1(grp_fu_888_p1),
.ce(1'b1),
.dout(grp_fu_888_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U13(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_892_p0),
.din1(grp_fu_892_p1),
.ce(1'b1),
.dout(grp_fu_892_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U14(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_896_p0),
.din1(grp_fu_896_p1),
.ce(1'b1),
.dout(grp_fu_896_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U15(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_900_p0),
.din1(grp_fu_900_p1),
.ce(1'b1),
.dout(grp_fu_900_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U16(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_904_p0),
.din1(grp_fu_904_p1),
.ce(1'b1),
.dout(grp_fu_904_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U17(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_908_p0),
.din1(grp_fu_908_p1),
.ce(1'b1),
.dout(grp_fu_908_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U18(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_912_p0),
.din1(grp_fu_912_p1),
.ce(1'b1),
.dout(grp_fu_912_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U19(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_916_p0),
.din1(grp_fu_916_p1),
.ce(1'b1),
.dout(grp_fu_916_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U20(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_920_p0),
.din1(grp_fu_920_p1),
.ce(1'b1),
.dout(grp_fu_920_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U21(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_924_p0),
.din1(grp_fu_924_p1),
.ce(1'b1),
.dout(grp_fu_924_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U22(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_928_p0),
.din1(grp_fu_928_p1),
.ce(1'b1),
.dout(grp_fu_928_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U23(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_932_p0),
.din1(grp_fu_932_p1),
.ce(1'b1),
.dout(grp_fu_932_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U24(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_936_p0),
.din1(grp_fu_936_p1),
.ce(1'b1),
.dout(grp_fu_936_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U25(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_940_p0),
.din1(grp_fu_940_p1),
.ce(1'b1),
.dout(grp_fu_940_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U26(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_944_p0),
.din1(grp_fu_944_p1),
.ce(1'b1),
.dout(grp_fu_944_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U27(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_948_p0),
.din1(grp_fu_948_p1),
.ce(1'b1),
.dout(grp_fu_948_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U28(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_952_p0),
.din1(grp_fu_952_p1),
.ce(1'b1),
.dout(grp_fu_952_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U29(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_956_p0),
.din1(grp_fu_956_p1),
.ce(1'b1),
.dout(grp_fu_956_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U30(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_960_p0),
.din1(grp_fu_960_p1),
.ce(1'b1),
.dout(grp_fu_960_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U31(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_964_p0),
.din1(grp_fu_964_p1),
.ce(1'b1),
.dout(grp_fu_964_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U32(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_968_p0),
.din1(grp_fu_968_p1),
.ce(1'b1),
.dout(grp_fu_968_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U33(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_972_p0),
.din1(grp_fu_972_p1),
.ce(1'b1),
.dout(grp_fu_972_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U34(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_976_p0),
.din1(grp_fu_976_p1),
.ce(1'b1),
.dout(grp_fu_976_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U35(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_980_p0),
.din1(grp_fu_980_p1),
.ce(1'b1),
.dout(grp_fu_980_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U36(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_984_p0),
.din1(grp_fu_984_p1),
.ce(1'b1),
.dout(grp_fu_984_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U37(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_988_p0),
.din1(grp_fu_988_p1),
.ce(1'b1),
.dout(grp_fu_988_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U38(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_992_p0),
.din1(grp_fu_992_p1),
.ce(1'b1),
.dout(grp_fu_992_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U39(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_996_p0),
.din1(grp_fu_996_p1),
.ce(1'b1),
.dout(grp_fu_996_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U40(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1000_p0),
.din1(grp_fu_1000_p1),
.ce(1'b1),
.dout(grp_fu_1000_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U41(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1004_p0),
.din1(grp_fu_1004_p1),
.ce(1'b1),
.dout(grp_fu_1004_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U42(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1008_p0),
.din1(grp_fu_1008_p1),
.ce(1'b1),
.dout(grp_fu_1008_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U43(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1012_p0),
.din1(grp_fu_1012_p1),
.ce(1'b1),
.dout(grp_fu_1012_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U44(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1016_p0),
.din1(grp_fu_1016_p1),
.ce(1'b1),
.dout(grp_fu_1016_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U45(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1020_p0),
.din1(grp_fu_1020_p1),
.ce(1'b1),
.dout(grp_fu_1020_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U46(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1024_p0),
.din1(grp_fu_1024_p1),
.ce(1'b1),
.dout(grp_fu_1024_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U47(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1028_p0),
.din1(grp_fu_1028_p1),
.ce(1'b1),
.dout(grp_fu_1028_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U48(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1032_p0),
.din1(grp_fu_1032_p1),
.ce(1'b1),
.dout(grp_fu_1032_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U49(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1036_p0),
.din1(grp_fu_1036_p1),
.ce(1'b1),
.dout(grp_fu_1036_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U50(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_1040_p0),
.din1(grp_fu_1040_p1),
.ce(1'b1),
.dout(grp_fu_1040_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 ^ 1'b1);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter10 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter11 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter12 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter13 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter14 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter15 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter16 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter17 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter18 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter19 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter20 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter21 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter22 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter23 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter24 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter25 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter26 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter27 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter28 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter29 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter30 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter31 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter31 <= ap_enable_reg_pp0_iter30;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter32 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter32 <= ap_enable_reg_pp0_iter31;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter33 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter33 <= ap_enable_reg_pp0_iter32;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter34 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter34 <= ap_enable_reg_pp0_iter33;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter35 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter35 <= ap_enable_reg_pp0_iter34;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter36 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter36 <= ap_enable_reg_pp0_iter35;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter37 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter37 <= ap_enable_reg_pp0_iter36;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter38 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter38 <= ap_enable_reg_pp0_iter37;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter39 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter39 <= ap_enable_reg_pp0_iter38;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter40 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter40 <= ap_enable_reg_pp0_iter39;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter41 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter41 <= ap_enable_reg_pp0_iter40;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter42 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter42 <= ap_enable_reg_pp0_iter41;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter43 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter43 <= ap_enable_reg_pp0_iter42;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter44 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter44 <= ap_enable_reg_pp0_iter43;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter45 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter45 <= ap_enable_reg_pp0_iter44;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter46 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter46 <= ap_enable_reg_pp0_iter45;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter47 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter47 <= ap_enable_reg_pp0_iter46;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter48 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter48 <= ap_enable_reg_pp0_iter47;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter49 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter49 <= ap_enable_reg_pp0_iter48;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter50 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter50 <= ap_enable_reg_pp0_iter49;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter51 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter51 <= ap_enable_reg_pp0_iter50;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter52 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter52 <= ap_enable_reg_pp0_iter51;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter53 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter53 <= ap_enable_reg_pp0_iter52;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter54 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter54 <= ap_enable_reg_pp0_iter53;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter55 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter55 <= ap_enable_reg_pp0_iter54;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter56 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter56 <= ap_enable_reg_pp0_iter55;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter57 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter57 <= ap_enable_reg_pp0_iter56;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter58 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter58 <= ap_enable_reg_pp0_iter57;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter59 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter59 <= ap_enable_reg_pp0_iter58;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter6 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter60 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter60 <= ap_enable_reg_pp0_iter59;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter61 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter61 <= ap_enable_reg_pp0_iter60;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter62 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter62 <= ap_enable_reg_pp0_iter61;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter63 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter63 <= ap_enable_reg_pp0_iter62;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter64 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter64 <= ap_enable_reg_pp0_iter63;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter65 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter65 <= ap_enable_reg_pp0_iter64;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter66 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter66 <= ap_enable_reg_pp0_iter65;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter67 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter67 <= ap_enable_reg_pp0_iter66;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter68 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter68 <= ap_enable_reg_pp0_iter67;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter69 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter69 <= ap_enable_reg_pp0_iter68;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter7 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter70 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter70 <= ap_enable_reg_pp0_iter69;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter71 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter71 <= ap_enable_reg_pp0_iter70;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter72 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter72 <= ap_enable_reg_pp0_iter71;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter73 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter73 <= ap_enable_reg_pp0_iter72;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter74 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter74 <= ap_enable_reg_pp0_iter73;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter75 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter75 <= ap_enable_reg_pp0_iter74;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter76 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter76 <= ap_enable_reg_pp0_iter75;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter77 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter77 <= ap_enable_reg_pp0_iter76;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter78 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter78 <= ap_enable_reg_pp0_iter77;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter78 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
indvar_flatten_reg_810 <= indvar_flatten_next_reg_1206;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
indvar_flatten_reg_810 <= 8'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
p_1_reg_833 <= row_b_V_reg_1278;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
p_1_reg_833 <= 2'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
p_s_reg_821 <= tmp_mid2_v_reg_1230;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
p_s_reg_821 <= 7'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter10_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter9_bufo_0_addr_reg_1972;
ap_reg_pp0_iter10_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter9_bufo_1_addr_reg_1978;
ap_reg_pp0_iter10_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter9_bufo_2_addr_reg_1984;
ap_reg_pp0_iter10_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter9_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter10_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter9_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter10_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter9_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter10_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter9_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter10_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter9_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter10_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter9_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter10_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter9_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter10_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter9_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter10_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter9_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter10_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter9_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter10_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter9_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter10_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter9_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter10_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter9_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter10_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter9_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter10_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter9_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter10_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter9_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter10_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter9_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter10_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter9_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter10_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter9_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter10_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter9_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter10_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter9_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter10_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter9_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter10_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter9_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter10_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter9_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter10_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter9_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter11_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter10_bufo_0_addr_reg_1972;
ap_reg_pp0_iter11_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter10_bufo_1_addr_reg_1978;
ap_reg_pp0_iter11_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter10_bufo_2_addr_reg_1984;
ap_reg_pp0_iter11_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter10_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter11_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter10_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter11_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter10_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter11_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter10_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter11_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter10_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter11_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter10_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter11_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter10_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter11_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter10_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter11_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter10_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter11_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter10_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter11_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter10_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter11_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter10_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter11_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter10_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter11_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter10_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter11_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter10_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter11_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter10_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter11_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter10_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter11_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter10_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter11_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter10_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter11_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter10_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter11_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter10_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter11_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter10_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter11_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter10_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter11_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter10_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter11_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter10_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter12_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter11_bufo_0_addr_reg_1972;
ap_reg_pp0_iter12_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter11_bufo_1_addr_reg_1978;
ap_reg_pp0_iter12_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter11_bufo_2_addr_reg_1984;
ap_reg_pp0_iter12_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter11_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter12_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter11_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter12_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter11_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter12_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter11_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter12_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter11_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter12_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter11_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter12_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter11_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter12_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter11_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter12_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter11_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter12_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter11_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter12_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter11_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter12_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter11_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter12_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter11_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter12_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter11_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter12_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter11_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter12_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter11_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter12_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter11_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter12_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter11_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter12_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter11_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter12_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter11_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter12_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter11_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter12_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter11_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter12_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter11_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter12_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter11_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter12_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter11_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter13_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter12_bufo_0_addr_reg_1972;
ap_reg_pp0_iter13_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter12_bufo_1_addr_reg_1978;
ap_reg_pp0_iter13_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter12_bufo_2_addr_reg_1984;
ap_reg_pp0_iter13_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter12_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter13_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter12_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter13_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter12_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter13_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter12_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter13_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter12_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter13_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter12_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter13_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter12_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter13_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter12_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter13_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter12_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter13_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter12_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter13_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter12_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter13_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter12_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter13_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter12_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter13_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter12_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter13_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter12_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter13_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter12_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter13_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter12_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter13_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter12_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter13_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter12_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter13_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter12_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter13_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter12_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter13_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter12_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter13_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter12_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter13_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter12_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter13_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter12_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter14_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter13_bufo_0_addr_reg_1972;
ap_reg_pp0_iter14_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter13_bufo_1_addr_reg_1978;
ap_reg_pp0_iter14_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter13_bufo_2_addr_reg_1984;
ap_reg_pp0_iter14_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter13_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter14_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter13_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter14_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter13_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter14_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter13_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter14_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter13_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter14_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter13_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter14_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter13_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter14_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter13_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter14_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter13_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter14_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter13_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter14_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter13_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter14_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter13_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter14_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter13_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter14_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter13_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter14_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter13_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter14_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter13_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter14_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter13_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter14_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter13_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter14_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter13_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter14_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter13_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter14_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter13_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter14_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter13_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter14_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter13_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter14_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter13_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter14_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter13_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter15_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter14_bufo_0_addr_reg_1972;
ap_reg_pp0_iter15_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter14_bufo_1_addr_reg_1978;
ap_reg_pp0_iter15_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter14_bufo_2_addr_reg_1984;
ap_reg_pp0_iter15_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter14_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter15_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter14_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter15_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter14_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter15_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter14_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter15_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter14_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter15_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter14_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter15_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter14_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter15_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter14_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter15_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter14_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter15_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter14_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter15_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter14_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter15_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter14_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter15_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter14_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter15_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter14_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter15_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter14_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter15_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter14_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter15_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter14_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter15_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter14_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter15_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter14_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter15_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter14_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter15_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter14_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter15_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter14_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter15_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter14_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter15_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter14_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter15_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter14_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter16_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter15_bufo_0_addr_reg_1972;
ap_reg_pp0_iter16_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter15_bufo_1_addr_reg_1978;
ap_reg_pp0_iter16_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter15_bufo_2_addr_reg_1984;
ap_reg_pp0_iter16_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter15_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter16_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter15_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter16_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter15_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter16_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter15_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter16_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter15_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter16_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter15_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter16_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter15_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter16_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter15_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter16_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter15_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter16_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter15_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter16_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter15_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter16_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter15_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter16_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter15_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter16_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter15_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter16_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter15_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter16_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter15_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter16_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter15_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter16_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter15_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter16_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter15_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter16_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter15_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter16_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter15_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter16_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter15_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter16_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter15_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter16_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter15_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter16_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter15_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter17_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter16_bufo_0_addr_reg_1972;
ap_reg_pp0_iter17_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter16_bufo_1_addr_reg_1978;
ap_reg_pp0_iter17_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter16_bufo_2_addr_reg_1984;
ap_reg_pp0_iter17_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter16_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter17_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter16_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter17_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter16_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter17_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter16_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter17_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter16_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter17_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter16_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter17_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter16_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter17_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter16_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter17_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter16_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter17_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter16_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter17_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter16_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter17_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter16_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter17_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter16_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter17_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter16_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter17_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter16_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter17_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter16_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter17_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter16_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter17_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter16_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter17_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter16_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter17_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter16_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter17_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter16_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter17_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter16_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter17_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter16_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter17_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter16_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter17_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter16_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter18_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter17_bufo_0_addr_reg_1972;
ap_reg_pp0_iter18_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter17_bufo_1_addr_reg_1978;
ap_reg_pp0_iter18_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter17_bufo_2_addr_reg_1984;
ap_reg_pp0_iter18_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter17_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter18_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter17_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter18_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter17_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter18_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter17_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter18_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter17_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter18_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter17_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter18_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter17_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter18_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter17_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter18_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter17_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter18_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter17_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter18_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter17_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter18_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter17_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter18_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter17_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter18_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter17_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter18_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter17_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter18_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter17_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter18_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter17_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter18_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter17_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter18_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter17_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter18_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter17_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter18_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter17_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter18_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter17_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter18_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter17_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter18_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter17_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter18_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter17_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter19_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter18_bufo_0_addr_reg_1972;
ap_reg_pp0_iter19_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter18_bufo_1_addr_reg_1978;
ap_reg_pp0_iter19_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter18_bufo_2_addr_reg_1984;
ap_reg_pp0_iter19_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter18_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter19_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter18_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter19_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter18_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter19_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter18_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter19_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter18_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter19_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter18_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter19_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter18_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter19_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter18_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter19_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter18_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter19_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter18_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter19_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter18_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter19_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter18_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter19_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter18_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter19_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter18_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter19_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter18_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter19_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter18_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter19_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter18_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter19_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter18_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter19_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter18_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter19_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter18_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter19_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter18_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter19_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter18_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter19_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter18_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter19_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter18_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter19_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter18_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter1_tmp_mid2_v_reg_1230 <= tmp_mid2_v_reg_1230;
ap_reg_pp0_iter20_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter19_bufo_0_addr_reg_1972;
ap_reg_pp0_iter20_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter19_bufo_1_addr_reg_1978;
ap_reg_pp0_iter20_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter19_bufo_2_addr_reg_1984;
ap_reg_pp0_iter20_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter19_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter20_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter19_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter20_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter19_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter20_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter19_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter20_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter19_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter20_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter19_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter20_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter19_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter20_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter19_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter20_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter19_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter20_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter19_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter20_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter19_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter20_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter19_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter20_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter19_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter20_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter19_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter20_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter19_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter20_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter19_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter20_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter19_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter20_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter19_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter20_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter19_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter20_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter19_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter20_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter19_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter20_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter19_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter20_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter19_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter20_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter19_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter20_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter19_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter21_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter20_bufo_0_addr_reg_1972;
ap_reg_pp0_iter21_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter20_bufo_1_addr_reg_1978;
ap_reg_pp0_iter21_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter20_bufo_2_addr_reg_1984;
ap_reg_pp0_iter21_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter20_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter21_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter20_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter21_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter20_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter21_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter20_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter21_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter20_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter21_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter20_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter21_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter20_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter21_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter20_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter21_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter20_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter21_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter20_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter21_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter20_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter21_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter20_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter21_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter20_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter21_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter20_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter21_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter20_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter21_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter20_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter21_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter20_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter21_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter20_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter21_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter20_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter21_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter20_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter21_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter20_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter21_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter20_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter21_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter20_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter21_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter20_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter21_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter20_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter22_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter21_bufo_0_addr_reg_1972;
ap_reg_pp0_iter22_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter21_bufo_1_addr_reg_1978;
ap_reg_pp0_iter22_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter21_bufo_2_addr_reg_1984;
ap_reg_pp0_iter22_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter21_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter22_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter21_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter22_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter21_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter22_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter21_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter22_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter21_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter22_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter21_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter22_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter21_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter22_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter21_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter22_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter21_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter22_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter21_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter22_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter21_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter22_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter21_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter22_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter21_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter22_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter21_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter22_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter21_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter22_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter21_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter22_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter21_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter22_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter21_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter22_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter21_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter22_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter21_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter22_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter21_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter22_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter21_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter22_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter21_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter22_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter21_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter22_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter21_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter23_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter22_bufo_0_addr_reg_1972;
ap_reg_pp0_iter23_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter22_bufo_1_addr_reg_1978;
ap_reg_pp0_iter23_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter22_bufo_2_addr_reg_1984;
ap_reg_pp0_iter23_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter22_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter23_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter22_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter23_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter22_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter23_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter22_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter23_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter22_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter23_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter22_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter23_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter22_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter23_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter22_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter23_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter22_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter23_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter22_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter23_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter22_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter23_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter22_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter23_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter22_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter23_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter22_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter23_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter22_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter23_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter22_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter23_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter22_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter23_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter22_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter23_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter22_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter23_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter22_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter23_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter22_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter23_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter22_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter23_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter22_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter23_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter22_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter23_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter22_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter24_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter23_bufo_0_addr_reg_1972;
ap_reg_pp0_iter24_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter23_bufo_1_addr_reg_1978;
ap_reg_pp0_iter24_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter23_bufo_2_addr_reg_1984;
ap_reg_pp0_iter24_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter23_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter24_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter23_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter24_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter23_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter24_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter23_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter24_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter23_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter24_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter23_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter24_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter23_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter24_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter23_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter24_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter23_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter24_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter23_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter24_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter23_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter24_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter23_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter24_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter23_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter24_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter23_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter24_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter23_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter24_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter23_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter24_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter23_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter24_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter23_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter24_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter23_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter24_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter23_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter24_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter23_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter24_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter23_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter24_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter23_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter24_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter23_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter24_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter23_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter25_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter24_bufo_0_addr_reg_1972;
ap_reg_pp0_iter25_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter24_bufo_1_addr_reg_1978;
ap_reg_pp0_iter25_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter24_bufo_2_addr_reg_1984;
ap_reg_pp0_iter25_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter24_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter25_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter24_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter25_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter24_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter25_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter24_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter25_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter24_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter25_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter24_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter25_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter24_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter25_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter24_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter25_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter24_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter25_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter24_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter25_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter24_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter25_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter24_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter25_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter24_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter25_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter24_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter25_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter24_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter25_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter24_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter25_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter24_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter25_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter24_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter25_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter24_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter25_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter24_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter25_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter24_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter25_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter24_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter25_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter24_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter25_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter24_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter25_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter24_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter26_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter25_bufo_0_addr_reg_1972;
ap_reg_pp0_iter26_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter25_bufo_1_addr_reg_1978;
ap_reg_pp0_iter26_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter25_bufo_2_addr_reg_1984;
ap_reg_pp0_iter26_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter25_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter26_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter25_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter26_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter25_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter26_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter25_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter26_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter25_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter26_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter25_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter26_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter25_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter26_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter25_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter26_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter25_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter26_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter25_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter26_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter25_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter26_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter25_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter26_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter25_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter26_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter25_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter26_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter25_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter26_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter25_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter26_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter25_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter26_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter25_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter26_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter25_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter26_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter25_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter26_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter25_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter26_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter25_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter26_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter25_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter26_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter25_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter26_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter25_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter27_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter26_bufo_0_addr_reg_1972;
ap_reg_pp0_iter27_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter26_bufo_1_addr_reg_1978;
ap_reg_pp0_iter27_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter26_bufo_2_addr_reg_1984;
ap_reg_pp0_iter27_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter26_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter27_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter26_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter27_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter26_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter27_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter26_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter27_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter26_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter27_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter26_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter27_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter26_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter27_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter26_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter27_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter26_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter27_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter26_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter27_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter26_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter27_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter26_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter27_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter26_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter27_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter26_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter27_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter26_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter27_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter26_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter27_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter26_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter27_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter26_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter27_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter26_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter27_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter26_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter27_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter26_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter27_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter26_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter27_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter26_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter27_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter26_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter27_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter26_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter28_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter27_bufo_0_addr_reg_1972;
ap_reg_pp0_iter28_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter27_bufo_1_addr_reg_1978;
ap_reg_pp0_iter28_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter27_bufo_2_addr_reg_1984;
ap_reg_pp0_iter28_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter27_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter28_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter27_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter28_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter27_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter28_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter27_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter28_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter27_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter28_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter27_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter28_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter27_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter28_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter27_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter28_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter27_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter28_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter27_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter28_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter27_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter28_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter27_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter28_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter27_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter28_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter27_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter28_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter27_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter28_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter27_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter28_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter27_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter28_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter27_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter28_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter27_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter28_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter27_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter28_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter27_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter28_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter27_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter28_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter27_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter28_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter27_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter28_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter27_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter29_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter28_bufo_0_addr_reg_1972;
ap_reg_pp0_iter29_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter28_bufo_1_addr_reg_1978;
ap_reg_pp0_iter29_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter28_bufo_2_addr_reg_1984;
ap_reg_pp0_iter29_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter28_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter29_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter28_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter29_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter28_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter29_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter28_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter29_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter28_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter29_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter28_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter29_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter28_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter29_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter28_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter29_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter28_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter29_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter28_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter29_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter28_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter29_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter28_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter29_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter28_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter29_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter28_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter29_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter28_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter29_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter28_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter29_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter28_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter29_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter28_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter29_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter28_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter29_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter28_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter29_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter28_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter29_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter28_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter29_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter28_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter29_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter28_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter29_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter28_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter30_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter29_bufo_0_addr_reg_1972;
ap_reg_pp0_iter30_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter29_bufo_1_addr_reg_1978;
ap_reg_pp0_iter30_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter29_bufo_2_addr_reg_1984;
ap_reg_pp0_iter30_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter29_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter30_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter29_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter30_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter29_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter30_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter29_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter30_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter29_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter30_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter29_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter30_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter29_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter30_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter29_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter30_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter29_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter30_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter29_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter30_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter29_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter30_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter29_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter30_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter29_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter30_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter29_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter30_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter29_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter30_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter29_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter30_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter29_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter30_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter29_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter30_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter29_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter30_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter29_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter30_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter29_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter30_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter29_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter30_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter29_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter30_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter29_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter30_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter29_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter31_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter30_bufo_0_addr_reg_1972;
ap_reg_pp0_iter31_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter30_bufo_1_addr_reg_1978;
ap_reg_pp0_iter31_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter30_bufo_2_addr_reg_1984;
ap_reg_pp0_iter31_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter30_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter31_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter30_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter31_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter30_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter31_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter30_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter31_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter30_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter31_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter30_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter31_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter30_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter31_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter30_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter31_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter30_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter31_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter30_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter31_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter30_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter31_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter30_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter31_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter30_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter31_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter30_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter31_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter30_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter31_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter30_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter31_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter30_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter31_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter30_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter31_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter30_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter31_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter30_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter31_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter30_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter31_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter30_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter31_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter30_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter31_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter30_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter31_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter30_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter32_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter31_bufo_0_addr_reg_1972;
ap_reg_pp0_iter32_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter31_bufo_1_addr_reg_1978;
ap_reg_pp0_iter32_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter31_bufo_2_addr_reg_1984;
ap_reg_pp0_iter32_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter31_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter32_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter31_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter32_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter31_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter32_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter31_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter32_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter31_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter32_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter31_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter32_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter31_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter32_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter31_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter32_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter31_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter32_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter31_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter32_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter31_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter32_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter31_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter32_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter31_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter32_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter31_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter32_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter31_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter32_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter31_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter32_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter31_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter32_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter31_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter32_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter31_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter32_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter31_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter32_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter31_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter32_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter31_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter32_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter31_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter32_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter31_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter32_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter31_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter33_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter32_bufo_0_addr_reg_1972;
ap_reg_pp0_iter33_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter32_bufo_1_addr_reg_1978;
ap_reg_pp0_iter33_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter32_bufo_2_addr_reg_1984;
ap_reg_pp0_iter33_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter32_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter33_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter32_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter33_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter32_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter33_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter32_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter33_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter32_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter33_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter32_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter33_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter32_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter33_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter32_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter33_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter32_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter33_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter32_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter33_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter32_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter33_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter32_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter33_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter32_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter33_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter32_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter33_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter32_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter33_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter32_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter33_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter32_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter33_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter32_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter33_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter32_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter33_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter32_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter33_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter32_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter33_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter32_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter33_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter32_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter33_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter32_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter33_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter32_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter34_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter33_bufo_0_addr_reg_1972;
ap_reg_pp0_iter34_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter33_bufo_1_addr_reg_1978;
ap_reg_pp0_iter34_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter33_bufo_2_addr_reg_1984;
ap_reg_pp0_iter34_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter33_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter34_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter33_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter34_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter33_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter34_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter33_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter34_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter33_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter34_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter33_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter34_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter33_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter34_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter33_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter34_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter33_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter34_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter33_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter34_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter33_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter34_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter33_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter34_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter33_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter34_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter33_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter34_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter33_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter34_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter33_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter34_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter33_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter34_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter33_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter34_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter33_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter34_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter33_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter34_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter33_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter34_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter33_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter34_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter33_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter34_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter33_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter34_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter33_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter35_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter34_bufo_0_addr_reg_1972;
ap_reg_pp0_iter35_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter34_bufo_1_addr_reg_1978;
ap_reg_pp0_iter35_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter34_bufo_2_addr_reg_1984;
ap_reg_pp0_iter35_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter34_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter35_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter34_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter35_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter34_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter35_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter34_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter35_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter34_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter35_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter34_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter35_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter34_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter35_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter34_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter35_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter34_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter35_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter34_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter35_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter34_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter35_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter34_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter35_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter34_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter35_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter34_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter35_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter34_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter35_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter34_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter35_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter34_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter35_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter34_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter35_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter34_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter35_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter34_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter35_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter34_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter35_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter34_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter35_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter34_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter35_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter34_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter35_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter34_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter36_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter35_bufo_0_addr_reg_1972;
ap_reg_pp0_iter36_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter35_bufo_1_addr_reg_1978;
ap_reg_pp0_iter36_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter35_bufo_2_addr_reg_1984;
ap_reg_pp0_iter36_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter35_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter36_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter35_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter36_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter35_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter36_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter35_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter36_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter35_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter36_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter35_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter36_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter35_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter36_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter35_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter36_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter35_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter36_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter35_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter36_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter35_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter36_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter35_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter36_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter35_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter36_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter35_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter36_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter35_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter36_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter35_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter36_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter35_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter36_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter35_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter36_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter35_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter36_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter35_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter36_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter35_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter36_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter35_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter36_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter35_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter36_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter35_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter36_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter35_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter37_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter36_bufo_0_addr_reg_1972;
ap_reg_pp0_iter37_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter36_bufo_1_addr_reg_1978;
ap_reg_pp0_iter37_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter36_bufo_2_addr_reg_1984;
ap_reg_pp0_iter37_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter36_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter37_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter36_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter37_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter36_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter37_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter36_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter37_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter36_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter37_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter36_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter37_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter36_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter37_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter36_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter37_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter36_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter37_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter36_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter37_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter36_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter37_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter36_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter37_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter36_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter37_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter36_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter37_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter36_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter37_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter36_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter37_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter36_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter37_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter36_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter37_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter36_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter37_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter36_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter37_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter36_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter37_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter36_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter37_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter36_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter37_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter36_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter37_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter36_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter38_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter37_bufo_0_addr_reg_1972;
ap_reg_pp0_iter38_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter37_bufo_1_addr_reg_1978;
ap_reg_pp0_iter38_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter37_bufo_2_addr_reg_1984;
ap_reg_pp0_iter38_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter37_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter38_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter37_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter38_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter37_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter38_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter37_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter38_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter37_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter38_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter37_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter38_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter37_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter38_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter37_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter38_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter37_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter38_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter37_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter38_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter37_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter38_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter37_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter38_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter37_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter38_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter37_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter38_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter37_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter38_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter37_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter38_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter37_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter38_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter37_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter38_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter37_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter38_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter37_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter38_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter37_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter38_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter37_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter38_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter37_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter38_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter37_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter38_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter37_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter39_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter38_bufo_0_addr_reg_1972;
ap_reg_pp0_iter39_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter38_bufo_1_addr_reg_1978;
ap_reg_pp0_iter39_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter38_bufo_2_addr_reg_1984;
ap_reg_pp0_iter39_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter38_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter39_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter38_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter39_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter38_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter39_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter38_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter39_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter38_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter39_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter38_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter39_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter38_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter39_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter38_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter39_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter38_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter39_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter38_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter39_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter38_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter39_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter38_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter39_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter38_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter39_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter38_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter39_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter38_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter39_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter38_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter39_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter38_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter39_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter38_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter39_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter38_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter39_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter38_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter39_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter38_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter39_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter38_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter39_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter38_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter39_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter38_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter39_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter38_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter3_bufo_0_addr_reg_1972 <= bufo_0_addr_reg_1972;
ap_reg_pp0_iter3_bufo_1_addr_reg_1978 <= bufo_1_addr_reg_1978;
ap_reg_pp0_iter3_bufo_2_addr_reg_1984 <= bufo_2_addr_reg_1984;
ap_reg_pp0_iter40_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter39_bufo_0_addr_reg_1972;
ap_reg_pp0_iter40_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter39_bufo_1_addr_reg_1978;
ap_reg_pp0_iter40_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter39_bufo_2_addr_reg_1984;
ap_reg_pp0_iter40_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter39_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter40_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter39_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter40_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter39_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter40_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter39_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter40_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter39_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter40_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter39_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter40_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter39_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter40_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter39_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter40_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter39_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter40_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter39_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter40_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter39_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter40_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter39_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter40_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter39_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter40_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter39_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter40_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter39_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter40_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter39_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter40_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter39_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter40_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter39_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter40_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter39_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter40_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter39_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter40_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter39_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter40_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter39_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter40_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter39_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter40_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter39_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter40_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter39_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter41_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter40_bufo_0_addr_reg_1972;
ap_reg_pp0_iter41_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter40_bufo_1_addr_reg_1978;
ap_reg_pp0_iter41_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter40_bufo_2_addr_reg_1984;
ap_reg_pp0_iter41_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter40_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter41_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter40_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter41_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter40_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter41_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter40_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter41_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter40_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter41_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter40_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter41_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter40_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter41_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter40_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter41_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter40_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter41_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter40_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter41_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter40_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter41_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter40_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter41_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter40_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter41_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter40_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter41_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter40_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter41_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter40_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter41_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter40_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter41_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter40_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter41_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter40_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter41_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter40_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter41_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter40_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter41_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter40_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter41_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter40_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter41_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter40_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter41_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter40_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter42_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter41_bufo_0_addr_reg_1972;
ap_reg_pp0_iter42_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter41_bufo_1_addr_reg_1978;
ap_reg_pp0_iter42_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter41_bufo_2_addr_reg_1984;
ap_reg_pp0_iter42_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter41_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter42_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter41_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter42_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter41_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter42_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter41_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter42_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter41_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter42_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter41_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter42_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter41_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter42_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter41_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter42_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter41_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter42_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter41_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter42_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter41_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter42_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter41_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter42_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter41_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter42_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter41_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter42_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter41_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter42_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter41_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter42_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter41_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter42_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter41_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter42_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter41_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter42_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter41_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter42_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter41_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter42_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter41_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter42_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter41_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter42_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter41_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter42_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter41_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter43_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter42_bufo_0_addr_reg_1972;
ap_reg_pp0_iter43_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter42_bufo_1_addr_reg_1978;
ap_reg_pp0_iter43_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter42_bufo_2_addr_reg_1984;
ap_reg_pp0_iter43_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter42_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter43_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter42_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter43_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter42_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter43_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter42_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter43_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter42_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter43_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter42_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter43_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter42_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter43_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter42_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter43_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter42_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter43_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter42_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter43_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter42_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter43_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter42_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter43_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter42_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter43_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter42_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter43_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter42_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter43_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter42_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter43_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter42_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter43_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter42_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter43_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter42_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter43_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter42_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter43_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter42_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter43_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter42_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter43_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter42_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter43_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter42_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter43_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter42_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter44_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter43_bufo_0_addr_reg_1972;
ap_reg_pp0_iter44_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter43_bufo_1_addr_reg_1978;
ap_reg_pp0_iter44_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter43_bufo_2_addr_reg_1984;
ap_reg_pp0_iter44_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter43_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter44_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter43_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter44_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter43_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter44_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter43_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter44_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter43_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter44_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter43_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter44_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter43_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter44_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter43_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter44_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter43_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter44_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter43_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter44_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter43_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter44_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter43_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter44_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter43_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter44_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter43_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter44_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter43_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter44_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter43_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter44_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter43_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter44_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter43_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter44_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter43_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter44_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter43_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter44_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter43_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter44_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter43_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter44_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter43_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter44_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter43_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter44_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter43_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter45_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter44_bufo_0_addr_reg_1972;
ap_reg_pp0_iter45_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter44_bufo_1_addr_reg_1978;
ap_reg_pp0_iter45_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter44_bufo_2_addr_reg_1984;
ap_reg_pp0_iter45_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter44_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter45_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter44_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter45_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter44_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter45_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter44_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter45_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter44_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter45_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter44_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter45_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter44_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter45_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter44_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter45_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter44_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter45_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter44_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter45_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter44_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter45_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter44_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter45_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter44_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter45_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter44_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter45_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter44_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter45_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter44_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter45_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter44_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter45_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter44_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter45_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter44_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter45_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter44_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter45_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter44_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter45_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter44_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter45_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter44_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter45_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter44_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter45_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter44_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter46_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter45_bufo_0_addr_reg_1972;
ap_reg_pp0_iter46_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter45_bufo_1_addr_reg_1978;
ap_reg_pp0_iter46_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter45_bufo_2_addr_reg_1984;
ap_reg_pp0_iter46_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter45_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter46_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter45_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter46_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter45_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter46_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter45_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter46_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter45_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter46_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter45_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter46_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter45_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter46_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter45_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter46_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter45_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter46_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter45_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter46_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter45_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter46_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter45_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter46_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter45_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter46_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter45_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter46_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter45_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter46_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter45_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter46_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter45_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter46_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter45_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter46_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter45_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter46_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter45_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter46_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter45_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter46_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter45_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter46_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter45_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter46_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter45_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter46_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter45_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter47_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter46_bufo_0_addr_reg_1972;
ap_reg_pp0_iter47_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter46_bufo_1_addr_reg_1978;
ap_reg_pp0_iter47_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter46_bufo_2_addr_reg_1984;
ap_reg_pp0_iter47_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter46_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter47_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter46_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter47_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter46_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter47_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter46_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter47_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter46_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter47_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter46_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter47_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter46_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter47_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter46_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter47_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter46_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter47_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter46_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter47_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter46_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter47_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter46_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter47_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter46_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter47_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter46_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter47_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter46_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter47_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter46_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter47_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter46_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter47_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter46_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter47_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter46_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter47_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter46_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter47_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter46_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter47_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter46_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter47_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter46_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter47_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter46_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter47_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter46_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter48_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter47_bufo_0_addr_reg_1972;
ap_reg_pp0_iter48_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter47_bufo_1_addr_reg_1978;
ap_reg_pp0_iter48_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter47_bufo_2_addr_reg_1984;
ap_reg_pp0_iter48_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter47_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter48_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter47_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter48_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter47_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter48_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter47_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter48_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter47_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter48_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter47_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter48_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter47_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter48_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter47_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter48_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter47_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter48_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter47_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter48_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter47_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter48_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter47_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter48_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter47_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter48_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter47_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter48_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter47_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter48_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter47_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter48_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter47_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter48_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter47_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter48_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter47_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter48_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter47_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter48_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter47_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter48_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter47_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter48_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter47_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter48_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter47_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter48_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter47_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter49_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter48_bufo_0_addr_reg_1972;
ap_reg_pp0_iter49_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter48_bufo_1_addr_reg_1978;
ap_reg_pp0_iter49_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter48_bufo_2_addr_reg_1984;
ap_reg_pp0_iter49_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter48_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter49_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter48_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter49_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter48_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter49_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter48_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter49_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter48_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter49_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter48_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter49_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter48_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter49_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter48_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter49_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter48_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter49_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter48_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter49_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter48_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter49_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter48_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter49_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter48_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter49_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter48_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter49_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter48_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter49_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter48_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter49_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter48_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter49_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter48_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter49_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter48_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter49_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter48_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter49_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter48_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter49_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter48_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter49_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter48_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter49_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter48_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter49_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter48_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter4_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter3_bufo_0_addr_reg_1972;
ap_reg_pp0_iter4_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter3_bufo_1_addr_reg_1978;
ap_reg_pp0_iter4_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter3_bufo_2_addr_reg_1984;
ap_reg_pp0_iter4_tmp_10_0_3_2_reg_2255 <= tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter4_tmp_10_0_3_3_reg_2260 <= tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter4_tmp_10_0_3_4_reg_2265 <= tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter4_tmp_10_0_4_1_reg_2275 <= tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter4_tmp_10_0_4_2_reg_2280 <= tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter4_tmp_10_0_4_3_reg_2285 <= tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter4_tmp_10_0_4_4_reg_2290 <= tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter4_tmp_10_0_4_reg_2270 <= tmp_10_0_4_reg_2270;
ap_reg_pp0_iter4_tmp_10_1_3_2_reg_2295 <= tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter4_tmp_10_1_3_3_reg_2300 <= tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter4_tmp_10_1_3_4_reg_2305 <= tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter4_tmp_10_1_4_1_reg_2315 <= tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter4_tmp_10_1_4_2_reg_2320 <= tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter4_tmp_10_1_4_3_reg_2325 <= tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter4_tmp_10_1_4_4_reg_2330 <= tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter4_tmp_10_1_4_reg_2310 <= tmp_10_1_4_reg_2310;
ap_reg_pp0_iter4_tmp_10_2_3_1_reg_2335 <= tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter4_tmp_10_2_3_2_reg_2340 <= tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter4_tmp_10_2_3_3_reg_2345 <= tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter4_tmp_10_2_3_4_reg_2350 <= tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter4_tmp_10_2_4_1_reg_2360 <= tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter4_tmp_10_2_4_2_reg_2365 <= tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter4_tmp_10_2_4_3_reg_2370 <= tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter4_tmp_10_2_4_4_reg_2375 <= tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter4_tmp_10_2_4_reg_2355 <= tmp_10_2_4_reg_2355;
ap_reg_pp0_iter50_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter49_bufo_0_addr_reg_1972;
ap_reg_pp0_iter50_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter49_bufo_1_addr_reg_1978;
ap_reg_pp0_iter50_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter49_bufo_2_addr_reg_1984;
ap_reg_pp0_iter50_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter49_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter50_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter49_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter50_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter49_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter50_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter49_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter50_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter49_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter50_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter49_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter50_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter49_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter50_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter49_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter50_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter49_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter50_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter49_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter50_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter49_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter50_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter49_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter50_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter49_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter50_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter49_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter50_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter49_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter50_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter49_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter50_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter49_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter50_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter49_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter50_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter49_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter50_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter49_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter50_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter49_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter50_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter49_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter50_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter49_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter50_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter49_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter50_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter49_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter51_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter50_bufo_0_addr_reg_1972;
ap_reg_pp0_iter51_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter50_bufo_1_addr_reg_1978;
ap_reg_pp0_iter51_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter50_bufo_2_addr_reg_1984;
ap_reg_pp0_iter51_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter50_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter51_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter50_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter51_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter50_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter51_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter50_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter51_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter50_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter51_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter50_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter51_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter50_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter51_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter50_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter51_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter50_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter51_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter50_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter51_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter50_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter51_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter50_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter51_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter50_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter51_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter50_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter51_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter50_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter51_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter50_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter51_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter50_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter51_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter50_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter51_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter50_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter51_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter50_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter51_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter50_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter51_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter50_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter51_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter50_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter51_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter50_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter51_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter50_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter52_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter51_bufo_0_addr_reg_1972;
ap_reg_pp0_iter52_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter51_bufo_1_addr_reg_1978;
ap_reg_pp0_iter52_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter51_bufo_2_addr_reg_1984;
ap_reg_pp0_iter52_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter51_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter52_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter51_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter52_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter51_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter52_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter51_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter52_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter51_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter52_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter51_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter52_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter51_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter52_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter51_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter52_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter51_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter52_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter51_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter52_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter51_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter52_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter51_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter52_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter51_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter52_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter51_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter52_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter51_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter52_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter51_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter52_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter51_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter52_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter51_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter52_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter51_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter52_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter51_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter52_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter51_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter52_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter51_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter52_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter51_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter52_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter51_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter53_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter52_bufo_0_addr_reg_1972;
ap_reg_pp0_iter53_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter52_bufo_1_addr_reg_1978;
ap_reg_pp0_iter53_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter52_bufo_2_addr_reg_1984;
ap_reg_pp0_iter53_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter52_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter53_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter52_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter53_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter52_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter53_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter52_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter53_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter52_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter53_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter52_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter53_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter52_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter53_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter52_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter53_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter52_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter53_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter52_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter53_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter52_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter53_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter52_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter53_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter52_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter53_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter52_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter53_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter52_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter53_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter52_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter53_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter52_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter53_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter52_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter53_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter52_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter53_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter52_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter53_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter52_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter53_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter52_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter53_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter52_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter53_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter52_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter54_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter53_bufo_0_addr_reg_1972;
ap_reg_pp0_iter54_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter53_bufo_1_addr_reg_1978;
ap_reg_pp0_iter54_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter53_bufo_2_addr_reg_1984;
ap_reg_pp0_iter54_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter53_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter54_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter53_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter54_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter53_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter54_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter53_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter54_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter53_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter54_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter53_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter54_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter53_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter54_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter53_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter54_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter53_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter54_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter53_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter54_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter53_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter54_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter53_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter54_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter53_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter54_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter53_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter54_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter53_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter54_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter53_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter54_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter53_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter54_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter53_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter54_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter53_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter54_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter53_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter54_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter53_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter54_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter53_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter54_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter53_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter54_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter53_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter55_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter54_bufo_0_addr_reg_1972;
ap_reg_pp0_iter55_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter54_bufo_1_addr_reg_1978;
ap_reg_pp0_iter55_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter54_bufo_2_addr_reg_1984;
ap_reg_pp0_iter55_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter54_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter55_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter54_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter55_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter54_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter55_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter54_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter55_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter54_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter55_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter54_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter55_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter54_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter55_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter54_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter55_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter54_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter55_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter54_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter55_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter54_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter55_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter54_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter55_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter54_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter55_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter54_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter55_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter54_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter55_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter54_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter55_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter54_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter55_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter54_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter55_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter54_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter55_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter54_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter55_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter54_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter56_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter55_bufo_0_addr_reg_1972;
ap_reg_pp0_iter56_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter55_bufo_1_addr_reg_1978;
ap_reg_pp0_iter56_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter55_bufo_2_addr_reg_1984;
ap_reg_pp0_iter56_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter55_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter56_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter55_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter56_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter55_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter56_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter55_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter56_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter55_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter56_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter55_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter56_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter55_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter56_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter55_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter56_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter55_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter56_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter55_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter56_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter55_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter56_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter55_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter56_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter55_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter56_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter55_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter56_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter55_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter56_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter55_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter56_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter55_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter56_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter55_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter56_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter55_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter56_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter55_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter56_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter55_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter57_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter56_bufo_0_addr_reg_1972;
ap_reg_pp0_iter57_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter56_bufo_1_addr_reg_1978;
ap_reg_pp0_iter57_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter56_bufo_2_addr_reg_1984;
ap_reg_pp0_iter57_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter56_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter57_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter56_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter57_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter56_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter57_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter56_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter57_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter56_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter57_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter56_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter57_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter56_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter57_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter56_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter57_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter56_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter57_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter56_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter57_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter56_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter57_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter56_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter57_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter56_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter57_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter56_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter57_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter56_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter57_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter56_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter57_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter56_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter57_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter56_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter57_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter56_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter57_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter56_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter57_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter56_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter58_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter57_bufo_0_addr_reg_1972;
ap_reg_pp0_iter58_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter57_bufo_1_addr_reg_1978;
ap_reg_pp0_iter58_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter57_bufo_2_addr_reg_1984;
ap_reg_pp0_iter58_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter57_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter58_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter57_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter58_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter57_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter58_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter57_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter58_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter57_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter58_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter57_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter58_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter57_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter58_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter57_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter58_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter57_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter58_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter57_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter58_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter57_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter58_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter57_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter58_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter57_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter58_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter57_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter58_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter57_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter58_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter57_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter58_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter57_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter58_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter57_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter59_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter58_bufo_0_addr_reg_1972;
ap_reg_pp0_iter59_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter58_bufo_1_addr_reg_1978;
ap_reg_pp0_iter59_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter58_bufo_2_addr_reg_1984;
ap_reg_pp0_iter59_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter58_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter59_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter58_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter59_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter58_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter59_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter58_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter59_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter58_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter59_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter58_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter59_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter58_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter59_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter58_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter59_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter58_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter59_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter58_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter59_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter58_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter59_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter58_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter59_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter58_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter59_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter58_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter59_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter58_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter59_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter58_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter59_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter58_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter59_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter58_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter5_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter4_bufo_0_addr_reg_1972;
ap_reg_pp0_iter5_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter4_bufo_1_addr_reg_1978;
ap_reg_pp0_iter5_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter4_bufo_2_addr_reg_1984;
ap_reg_pp0_iter5_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter4_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter5_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter4_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter5_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter4_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter5_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter4_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter5_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter4_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter5_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter4_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter5_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter4_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter5_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter4_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter5_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter4_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter5_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter4_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter5_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter4_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter5_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter4_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter5_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter4_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter5_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter4_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter5_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter4_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter5_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter4_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter5_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter4_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter5_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter4_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter5_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter4_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter5_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter4_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter5_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter4_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter5_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter4_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter5_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter4_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter5_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter4_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter5_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter4_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter60_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter59_bufo_0_addr_reg_1972;
ap_reg_pp0_iter60_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter59_bufo_1_addr_reg_1978;
ap_reg_pp0_iter60_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter59_bufo_2_addr_reg_1984;
ap_reg_pp0_iter60_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter59_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter60_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter59_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter60_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter59_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter60_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter59_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter60_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter59_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter60_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter59_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter60_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter59_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter60_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter59_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter60_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter59_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter60_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter59_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter60_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter59_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter60_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter59_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter60_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter59_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter60_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter59_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter60_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter59_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter60_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter59_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter60_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter59_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter60_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter59_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter61_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter60_bufo_0_addr_reg_1972;
ap_reg_pp0_iter61_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter60_bufo_1_addr_reg_1978;
ap_reg_pp0_iter61_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter60_bufo_2_addr_reg_1984;
ap_reg_pp0_iter61_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter60_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter61_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter60_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter61_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter60_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter61_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter60_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter61_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter60_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter61_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter60_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter61_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter60_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter61_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter60_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter61_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter60_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter61_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter60_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter61_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter60_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter61_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter60_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter61_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter60_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter61_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter60_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter61_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter60_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter62_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter61_bufo_0_addr_reg_1972;
ap_reg_pp0_iter62_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter61_bufo_1_addr_reg_1978;
ap_reg_pp0_iter62_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter61_bufo_2_addr_reg_1984;
ap_reg_pp0_iter62_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter61_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter62_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter61_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter62_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter61_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter62_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter61_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter62_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter61_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter62_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter61_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter62_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter61_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter62_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter61_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter62_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter61_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter62_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter61_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter62_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter61_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter62_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter61_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter62_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter61_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter62_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter61_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter62_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter61_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter63_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter62_bufo_0_addr_reg_1972;
ap_reg_pp0_iter63_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter62_bufo_1_addr_reg_1978;
ap_reg_pp0_iter63_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter62_bufo_2_addr_reg_1984;
ap_reg_pp0_iter63_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter62_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter63_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter62_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter63_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter62_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter63_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter62_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter63_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter62_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter63_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter62_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter63_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter62_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter63_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter62_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter63_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter62_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter63_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter62_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter63_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter62_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter63_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter62_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter63_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter62_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter63_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter62_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter63_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter62_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter64_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter63_bufo_0_addr_reg_1972;
ap_reg_pp0_iter64_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter63_bufo_1_addr_reg_1978;
ap_reg_pp0_iter64_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter63_bufo_2_addr_reg_1984;
ap_reg_pp0_iter64_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter63_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter64_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter63_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter64_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter63_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter64_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter63_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter64_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter63_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter64_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter63_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter64_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter63_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter64_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter63_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter64_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter63_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter64_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter63_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter64_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter63_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter64_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter63_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter65_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter64_bufo_0_addr_reg_1972;
ap_reg_pp0_iter65_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter64_bufo_1_addr_reg_1978;
ap_reg_pp0_iter65_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter64_bufo_2_addr_reg_1984;
ap_reg_pp0_iter65_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter64_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter65_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter64_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter65_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter64_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter65_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter64_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter65_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter64_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter65_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter64_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter65_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter64_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter65_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter64_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter65_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter64_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter65_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter64_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter65_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter64_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter65_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter64_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter66_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter65_bufo_0_addr_reg_1972;
ap_reg_pp0_iter66_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter65_bufo_1_addr_reg_1978;
ap_reg_pp0_iter66_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter65_bufo_2_addr_reg_1984;
ap_reg_pp0_iter66_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter65_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter66_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter65_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter66_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter65_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter66_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter65_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter66_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter65_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter66_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter65_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter66_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter65_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter66_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter65_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter66_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter65_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter66_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter65_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter66_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter65_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter66_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter65_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter67_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter66_bufo_0_addr_reg_1972;
ap_reg_pp0_iter67_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter66_bufo_1_addr_reg_1978;
ap_reg_pp0_iter67_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter66_bufo_2_addr_reg_1984;
ap_reg_pp0_iter67_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter66_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter67_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter66_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter67_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter66_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter67_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter66_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter67_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter66_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter67_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter66_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter67_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter66_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter67_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter66_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter67_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter66_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter68_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter67_bufo_0_addr_reg_1972;
ap_reg_pp0_iter68_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter67_bufo_1_addr_reg_1978;
ap_reg_pp0_iter68_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter67_bufo_2_addr_reg_1984;
ap_reg_pp0_iter68_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter67_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter68_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter67_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter68_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter67_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter68_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter67_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter68_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter67_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter68_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter67_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter68_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter67_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter68_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter67_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter68_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter67_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter69_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter68_bufo_0_addr_reg_1972;
ap_reg_pp0_iter69_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter68_bufo_1_addr_reg_1978;
ap_reg_pp0_iter69_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter68_bufo_2_addr_reg_1984;
ap_reg_pp0_iter69_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter68_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter69_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter68_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter69_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter68_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter69_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter68_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter69_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter68_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter69_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter68_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter69_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter68_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter69_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter68_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter69_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter68_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter6_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter5_bufo_0_addr_reg_1972;
ap_reg_pp0_iter6_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter5_bufo_1_addr_reg_1978;
ap_reg_pp0_iter6_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter5_bufo_2_addr_reg_1984;
ap_reg_pp0_iter6_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter5_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter6_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter5_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter6_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter5_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter6_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter5_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter6_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter5_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter6_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter5_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter6_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter5_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter6_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter5_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter6_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter5_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter6_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter5_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter6_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter5_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter6_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter5_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter6_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter5_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter6_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter5_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter6_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter5_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter6_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter5_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter6_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter5_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter6_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter5_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter6_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter5_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter6_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter5_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter6_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter5_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter6_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter5_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter6_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter5_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter6_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter5_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter6_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter5_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter70_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter69_bufo_0_addr_reg_1972;
ap_reg_pp0_iter70_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter69_bufo_1_addr_reg_1978;
ap_reg_pp0_iter70_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter69_bufo_2_addr_reg_1984;
ap_reg_pp0_iter70_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter69_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter70_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter69_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter70_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter69_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter70_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter69_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter70_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter69_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter70_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter69_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter71_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter70_bufo_0_addr_reg_1972;
ap_reg_pp0_iter71_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter70_bufo_1_addr_reg_1978;
ap_reg_pp0_iter71_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter70_bufo_2_addr_reg_1984;
ap_reg_pp0_iter71_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter70_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter71_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter70_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter71_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter70_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter71_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter70_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter71_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter70_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter71_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter70_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter72_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter71_bufo_0_addr_reg_1972;
ap_reg_pp0_iter72_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter71_bufo_1_addr_reg_1978;
ap_reg_pp0_iter72_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter71_bufo_2_addr_reg_1984;
ap_reg_pp0_iter72_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter71_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter72_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter71_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter72_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter71_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter72_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter71_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter72_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter71_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter72_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter71_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter73_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter72_bufo_0_addr_reg_1972;
ap_reg_pp0_iter73_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter72_bufo_1_addr_reg_1978;
ap_reg_pp0_iter73_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter72_bufo_2_addr_reg_1984;
ap_reg_pp0_iter73_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter72_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter73_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter72_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter73_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter72_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter74_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter73_bufo_0_addr_reg_1972;
ap_reg_pp0_iter74_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter73_bufo_1_addr_reg_1978;
ap_reg_pp0_iter74_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter73_bufo_2_addr_reg_1984;
ap_reg_pp0_iter74_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter73_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter74_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter73_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter74_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter73_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter75_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter74_bufo_0_addr_reg_1972;
ap_reg_pp0_iter75_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter74_bufo_1_addr_reg_1978;
ap_reg_pp0_iter75_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter74_bufo_2_addr_reg_1984;
ap_reg_pp0_iter75_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter74_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter75_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter74_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter75_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter74_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter76_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter75_bufo_0_addr_reg_1972;
ap_reg_pp0_iter76_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter75_bufo_1_addr_reg_1978;
ap_reg_pp0_iter76_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter75_bufo_2_addr_reg_1984;
ap_reg_pp0_iter77_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter76_bufo_0_addr_reg_1972;
ap_reg_pp0_iter77_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter76_bufo_1_addr_reg_1978;
ap_reg_pp0_iter77_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter76_bufo_2_addr_reg_1984;
ap_reg_pp0_iter78_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter77_bufo_0_addr_reg_1972;
ap_reg_pp0_iter78_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter77_bufo_1_addr_reg_1978;
ap_reg_pp0_iter78_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter77_bufo_2_addr_reg_1984;
ap_reg_pp0_iter7_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter6_bufo_0_addr_reg_1972;
ap_reg_pp0_iter7_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter6_bufo_1_addr_reg_1978;
ap_reg_pp0_iter7_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter6_bufo_2_addr_reg_1984;
ap_reg_pp0_iter7_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter6_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter7_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter6_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter7_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter6_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter7_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter6_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter7_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter6_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter7_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter6_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter7_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter6_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter7_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter6_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter7_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter6_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter7_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter6_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter7_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter6_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter7_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter6_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter7_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter6_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter7_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter6_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter7_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter6_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter7_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter6_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter7_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter6_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter7_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter6_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter7_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter6_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter7_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter6_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter7_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter6_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter7_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter6_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter7_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter6_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter7_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter6_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter7_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter6_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter8_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter7_bufo_0_addr_reg_1972;
ap_reg_pp0_iter8_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter7_bufo_1_addr_reg_1978;
ap_reg_pp0_iter8_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter7_bufo_2_addr_reg_1984;
ap_reg_pp0_iter8_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter7_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter8_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter7_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter8_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter7_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter8_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter7_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter8_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter7_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter8_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter7_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter8_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter7_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter8_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter7_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter8_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter7_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter8_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter7_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter8_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter7_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter8_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter7_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter8_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter7_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter8_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter7_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter8_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter7_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter8_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter7_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter8_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter7_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter8_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter7_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter8_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter7_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter8_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter7_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter8_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter7_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter8_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter7_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter8_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter7_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter8_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter7_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter8_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter7_tmp_10_2_4_reg_2355;
ap_reg_pp0_iter9_bufo_0_addr_reg_1972 <= ap_reg_pp0_iter8_bufo_0_addr_reg_1972;
ap_reg_pp0_iter9_bufo_1_addr_reg_1978 <= ap_reg_pp0_iter8_bufo_1_addr_reg_1978;
ap_reg_pp0_iter9_bufo_2_addr_reg_1984 <= ap_reg_pp0_iter8_bufo_2_addr_reg_1984;
ap_reg_pp0_iter9_tmp_10_0_3_2_reg_2255 <= ap_reg_pp0_iter8_tmp_10_0_3_2_reg_2255;
ap_reg_pp0_iter9_tmp_10_0_3_3_reg_2260 <= ap_reg_pp0_iter8_tmp_10_0_3_3_reg_2260;
ap_reg_pp0_iter9_tmp_10_0_3_4_reg_2265 <= ap_reg_pp0_iter8_tmp_10_0_3_4_reg_2265;
ap_reg_pp0_iter9_tmp_10_0_4_1_reg_2275 <= ap_reg_pp0_iter8_tmp_10_0_4_1_reg_2275;
ap_reg_pp0_iter9_tmp_10_0_4_2_reg_2280 <= ap_reg_pp0_iter8_tmp_10_0_4_2_reg_2280;
ap_reg_pp0_iter9_tmp_10_0_4_3_reg_2285 <= ap_reg_pp0_iter8_tmp_10_0_4_3_reg_2285;
ap_reg_pp0_iter9_tmp_10_0_4_4_reg_2290 <= ap_reg_pp0_iter8_tmp_10_0_4_4_reg_2290;
ap_reg_pp0_iter9_tmp_10_0_4_reg_2270 <= ap_reg_pp0_iter8_tmp_10_0_4_reg_2270;
ap_reg_pp0_iter9_tmp_10_1_3_2_reg_2295 <= ap_reg_pp0_iter8_tmp_10_1_3_2_reg_2295;
ap_reg_pp0_iter9_tmp_10_1_3_3_reg_2300 <= ap_reg_pp0_iter8_tmp_10_1_3_3_reg_2300;
ap_reg_pp0_iter9_tmp_10_1_3_4_reg_2305 <= ap_reg_pp0_iter8_tmp_10_1_3_4_reg_2305;
ap_reg_pp0_iter9_tmp_10_1_4_1_reg_2315 <= ap_reg_pp0_iter8_tmp_10_1_4_1_reg_2315;
ap_reg_pp0_iter9_tmp_10_1_4_2_reg_2320 <= ap_reg_pp0_iter8_tmp_10_1_4_2_reg_2320;
ap_reg_pp0_iter9_tmp_10_1_4_3_reg_2325 <= ap_reg_pp0_iter8_tmp_10_1_4_3_reg_2325;
ap_reg_pp0_iter9_tmp_10_1_4_4_reg_2330 <= ap_reg_pp0_iter8_tmp_10_1_4_4_reg_2330;
ap_reg_pp0_iter9_tmp_10_1_4_reg_2310 <= ap_reg_pp0_iter8_tmp_10_1_4_reg_2310;
ap_reg_pp0_iter9_tmp_10_2_3_1_reg_2335 <= ap_reg_pp0_iter8_tmp_10_2_3_1_reg_2335;
ap_reg_pp0_iter9_tmp_10_2_3_2_reg_2340 <= ap_reg_pp0_iter8_tmp_10_2_3_2_reg_2340;
ap_reg_pp0_iter9_tmp_10_2_3_3_reg_2345 <= ap_reg_pp0_iter8_tmp_10_2_3_3_reg_2345;
ap_reg_pp0_iter9_tmp_10_2_3_4_reg_2350 <= ap_reg_pp0_iter8_tmp_10_2_3_4_reg_2350;
ap_reg_pp0_iter9_tmp_10_2_4_1_reg_2360 <= ap_reg_pp0_iter8_tmp_10_2_4_1_reg_2360;
ap_reg_pp0_iter9_tmp_10_2_4_2_reg_2365 <= ap_reg_pp0_iter8_tmp_10_2_4_2_reg_2365;
ap_reg_pp0_iter9_tmp_10_2_4_3_reg_2370 <= ap_reg_pp0_iter8_tmp_10_2_4_3_reg_2370;
ap_reg_pp0_iter9_tmp_10_2_4_4_reg_2375 <= ap_reg_pp0_iter8_tmp_10_2_4_4_reg_2375;
ap_reg_pp0_iter9_tmp_10_2_4_reg_2355 <= ap_reg_pp0_iter8_tmp_10_2_4_reg_2355;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter10_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter9_exitcond_flatten_reg_1202;
ap_reg_pp0_iter10_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter9_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter10_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter9_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter10_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter9_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter10_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter9_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter10_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter9_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter10_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter9_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter10_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter9_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter10_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter9_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter10_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter9_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter10_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter9_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter10_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter9_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter10_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter9_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter10_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter9_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter10_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter9_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter10_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter9_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter10_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter9_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter10_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter9_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter10_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter9_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter10_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter9_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter10_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter9_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter10_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter9_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter10_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter9_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter10_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter9_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter10_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter9_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter10_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter9_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter11_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter10_exitcond_flatten_reg_1202;
ap_reg_pp0_iter11_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter10_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter11_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter10_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter11_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter10_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter11_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter10_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter11_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter10_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter11_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter10_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter11_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter10_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter11_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter10_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter11_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter10_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter11_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter10_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter11_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter10_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter11_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter10_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter11_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter10_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter11_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter10_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter11_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter10_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter11_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter10_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter11_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter10_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter11_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter10_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter11_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter10_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter11_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter10_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter11_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter10_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter11_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter10_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter11_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter10_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter11_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter10_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter11_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter10_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter12_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter11_exitcond_flatten_reg_1202;
ap_reg_pp0_iter12_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter11_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter12_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter11_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter12_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter11_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter12_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter11_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter12_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter11_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter12_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter11_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter12_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter11_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter12_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter11_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter12_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter11_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter12_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter11_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter12_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter11_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter12_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter11_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter12_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter11_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter12_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter11_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter12_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter11_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter12_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter11_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter12_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter11_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter12_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter11_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter12_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter11_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter12_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter11_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter12_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter11_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter12_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter11_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter12_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter11_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter12_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter11_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter12_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter11_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter13_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter12_exitcond_flatten_reg_1202;
ap_reg_pp0_iter13_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter12_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter13_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter12_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter13_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter12_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter13_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter12_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter13_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter12_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter13_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter12_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter13_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter12_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter13_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter12_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter13_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter12_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter13_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter12_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter13_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter12_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter13_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter12_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter13_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter12_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter13_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter12_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter13_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter12_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter13_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter12_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter13_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter12_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter13_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter12_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter13_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter12_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter13_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter12_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter13_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter12_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter13_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter12_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter13_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter12_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter13_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter12_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter13_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter12_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter14_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter13_exitcond_flatten_reg_1202;
ap_reg_pp0_iter14_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter13_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter14_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter13_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter14_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter13_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter14_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter13_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter14_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter13_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter14_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter13_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter14_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter13_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter14_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter13_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter14_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter13_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter14_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter13_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter14_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter13_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter14_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter13_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter14_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter13_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter14_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter13_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter14_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter13_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter14_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter13_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter14_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter13_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter14_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter13_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter14_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter13_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter14_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter13_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter14_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter13_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter14_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter13_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter14_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter13_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter14_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter13_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter14_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter13_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter15_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter14_exitcond_flatten_reg_1202;
ap_reg_pp0_iter15_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter14_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter15_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter14_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter15_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter14_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter15_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter14_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter15_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter14_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter15_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter14_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter15_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter14_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter15_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter14_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter15_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter14_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter15_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter14_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter15_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter14_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter15_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter14_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter15_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter14_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter15_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter14_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter15_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter14_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter15_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter14_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter15_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter14_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter15_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter14_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter15_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter14_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter15_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter14_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter15_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter14_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter15_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter14_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter15_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter14_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter15_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter14_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter15_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter14_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter16_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter15_exitcond_flatten_reg_1202;
ap_reg_pp0_iter16_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter15_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter16_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter15_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter16_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter15_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter16_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter15_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter16_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter15_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter16_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter15_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter16_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter15_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter16_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter15_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter16_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter15_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter16_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter15_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter16_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter15_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter16_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter15_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter16_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter15_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter16_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter15_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter16_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter15_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter16_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter15_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter16_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter15_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter16_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter15_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter16_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter15_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter16_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter15_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter16_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter15_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter16_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter15_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter16_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter15_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter16_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter15_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter16_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter15_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter17_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter16_exitcond_flatten_reg_1202;
ap_reg_pp0_iter17_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter16_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter17_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter16_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter17_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter16_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter17_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter16_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter17_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter16_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter17_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter16_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter17_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter16_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter17_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter16_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter17_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter16_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter17_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter16_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter17_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter16_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter17_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter16_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter17_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter16_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter17_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter16_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter17_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter16_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter17_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter16_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter17_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter16_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter17_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter16_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter17_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter16_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter17_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter16_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter17_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter16_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter17_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter16_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter17_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter16_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter17_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter16_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter17_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter16_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter18_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter17_exitcond_flatten_reg_1202;
ap_reg_pp0_iter18_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter17_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter18_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter17_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter18_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter17_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter18_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter17_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter18_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter17_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter18_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter17_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter18_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter17_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter18_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter17_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter18_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter17_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter18_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter17_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter18_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter17_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter18_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter17_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter18_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter17_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter18_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter17_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter18_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter17_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter18_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter17_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter18_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter17_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter18_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter17_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter18_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter17_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter18_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter17_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter18_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter17_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter18_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter17_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter18_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter17_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter18_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter17_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter18_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter17_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter19_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter18_exitcond_flatten_reg_1202;
ap_reg_pp0_iter19_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter18_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter19_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter18_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter19_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter18_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter19_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter18_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter19_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter18_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter19_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter18_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter19_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter18_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter19_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter18_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter19_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter18_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter19_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter18_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter19_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter18_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter19_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter18_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter19_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter18_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter19_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter18_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter19_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter18_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter19_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter18_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter19_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter18_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter19_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter18_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter19_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter18_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter19_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter18_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter19_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter18_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter19_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter18_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter19_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter18_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter19_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter18_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter19_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter18_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter1_exitcond_flatten_reg_1202 <= exitcond_flatten_reg_1202;
ap_reg_pp0_iter1_p_1_mid2_reg_1221 <= p_1_mid2_reg_1221;
ap_reg_pp0_iter20_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter19_exitcond_flatten_reg_1202;
ap_reg_pp0_iter20_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter19_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter20_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter19_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter20_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter19_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter20_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter19_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter20_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter19_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter20_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter19_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter20_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter19_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter20_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter19_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter20_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter19_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter20_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter19_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter20_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter19_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter20_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter19_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter20_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter19_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter20_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter19_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter20_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter19_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter20_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter19_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter20_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter19_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter20_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter19_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter20_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter19_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter20_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter19_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter20_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter19_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter20_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter19_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter20_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter19_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter20_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter19_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter20_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter19_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter21_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter20_exitcond_flatten_reg_1202;
ap_reg_pp0_iter21_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter20_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter21_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter20_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter21_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter20_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter21_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter20_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter21_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter20_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter21_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter20_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter21_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter20_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter21_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter20_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter21_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter20_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter21_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter20_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter21_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter20_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter21_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter20_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter21_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter20_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter21_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter20_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter21_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter20_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter21_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter20_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter21_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter20_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter21_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter20_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter21_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter20_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter21_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter20_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter21_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter20_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter21_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter20_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter21_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter20_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter21_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter20_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter21_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter20_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter22_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter21_exitcond_flatten_reg_1202;
ap_reg_pp0_iter22_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter21_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter22_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter21_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter22_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter21_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter22_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter21_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter22_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter21_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter22_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter21_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter22_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter21_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter22_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter21_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter22_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter21_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter22_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter21_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter22_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter21_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter22_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter21_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter22_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter21_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter22_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter21_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter22_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter21_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter22_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter21_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter22_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter21_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter22_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter21_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter22_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter21_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter22_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter21_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter22_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter21_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter22_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter21_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter22_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter21_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter22_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter21_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter22_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter21_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter23_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter22_exitcond_flatten_reg_1202;
ap_reg_pp0_iter23_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter22_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter23_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter22_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter23_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter22_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter23_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter22_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter23_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter22_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter23_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter22_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter23_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter22_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter23_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter22_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter23_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter22_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter23_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter22_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter23_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter22_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter23_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter22_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter23_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter22_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter23_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter22_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter23_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter22_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter23_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter22_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter23_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter22_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter23_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter22_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter23_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter22_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter23_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter22_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter23_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter22_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter23_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter22_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter23_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter22_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter23_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter22_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter23_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter22_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter24_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter23_exitcond_flatten_reg_1202;
ap_reg_pp0_iter24_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter23_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter24_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter23_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter24_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter23_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter24_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter23_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter24_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter23_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter24_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter23_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter24_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter23_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter24_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter23_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter24_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter23_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter24_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter23_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter24_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter23_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter24_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter23_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter24_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter23_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter24_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter23_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter24_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter23_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter24_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter23_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter24_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter23_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter24_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter23_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter24_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter23_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter24_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter23_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter24_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter23_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter24_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter23_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter24_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter23_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter24_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter23_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter24_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter23_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter25_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter24_exitcond_flatten_reg_1202;
ap_reg_pp0_iter25_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter24_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter25_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter24_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter25_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter24_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter25_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter24_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter25_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter24_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter25_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter24_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter25_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter24_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter25_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter24_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter25_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter24_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter25_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter24_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter25_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter24_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter25_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter24_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter25_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter24_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter25_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter24_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter25_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter24_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter25_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter24_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter25_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter24_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter25_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter24_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter25_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter24_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter25_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter24_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter25_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter24_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter25_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter24_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter25_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter24_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter25_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter24_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter25_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter24_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter26_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter25_exitcond_flatten_reg_1202;
ap_reg_pp0_iter26_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter25_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter26_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter25_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter26_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter25_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter26_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter25_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter26_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter25_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter26_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter25_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter26_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter25_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter26_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter25_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter26_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter25_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter26_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter25_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter26_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter25_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter26_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter25_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter26_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter25_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter26_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter25_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter26_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter25_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter26_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter25_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter26_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter25_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter26_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter25_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter26_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter25_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter26_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter25_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter26_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter25_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter26_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter25_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter26_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter25_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter26_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter25_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter26_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter25_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter27_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter26_exitcond_flatten_reg_1202;
ap_reg_pp0_iter27_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter26_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter27_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter26_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter27_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter26_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter27_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter26_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter27_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter26_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter27_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter26_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter27_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter26_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter27_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter26_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter27_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter26_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter27_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter26_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter27_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter26_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter27_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter26_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter27_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter26_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter27_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter26_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter27_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter26_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter27_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter26_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter27_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter26_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter27_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter26_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter27_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter26_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter27_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter26_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter27_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter26_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter27_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter26_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter27_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter26_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter27_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter26_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter27_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter26_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter28_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter27_exitcond_flatten_reg_1202;
ap_reg_pp0_iter28_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter27_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter28_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter27_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter28_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter27_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter28_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter27_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter28_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter27_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter28_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter27_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter28_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter27_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter28_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter27_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter28_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter27_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter28_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter27_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter28_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter27_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter28_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter27_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter28_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter27_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter28_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter27_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter28_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter27_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter28_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter27_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter28_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter27_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter28_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter27_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter28_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter27_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter28_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter27_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter28_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter27_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter28_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter27_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter28_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter27_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter29_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter28_exitcond_flatten_reg_1202;
ap_reg_pp0_iter29_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter28_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter29_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter28_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter29_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter28_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter29_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter28_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter29_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter28_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter29_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter28_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter29_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter28_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter29_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter28_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter29_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter28_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter29_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter28_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter29_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter28_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter29_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter28_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter29_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter28_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter29_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter28_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter29_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter28_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter29_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter28_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter29_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter28_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter29_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter28_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter29_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter28_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter29_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter28_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter29_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter28_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter29_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter28_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter29_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter28_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter2_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter1_exitcond_flatten_reg_1202;
ap_reg_pp0_iter30_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter29_exitcond_flatten_reg_1202;
ap_reg_pp0_iter30_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter29_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter30_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter29_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter30_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter29_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter30_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter29_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter30_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter29_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter30_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter29_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter30_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter29_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter30_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter29_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter30_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter29_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter30_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter29_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter30_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter29_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter30_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter29_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter30_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter29_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter30_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter29_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter30_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter29_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter30_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter29_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter30_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter29_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter30_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter29_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter30_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter29_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter30_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter29_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter30_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter29_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter30_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter29_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter30_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter29_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter31_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter30_exitcond_flatten_reg_1202;
ap_reg_pp0_iter31_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter30_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter31_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter30_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter31_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter30_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter31_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter30_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter31_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter30_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter31_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter30_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter31_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter30_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter31_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter30_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter31_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter30_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter31_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter30_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter31_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter30_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter31_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter30_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter31_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter30_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter31_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter30_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter31_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter30_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter31_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter30_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter31_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter30_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter31_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter30_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter31_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter30_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter31_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter30_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter32_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter31_exitcond_flatten_reg_1202;
ap_reg_pp0_iter32_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter31_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter32_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter31_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter32_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter31_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter32_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter31_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter32_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter31_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter32_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter31_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter32_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter31_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter32_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter31_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter32_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter31_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter32_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter31_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter32_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter31_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter32_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter31_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter32_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter31_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter32_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter31_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter32_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter31_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter32_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter31_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter32_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter31_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter32_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter31_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter32_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter31_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter32_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter31_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter33_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter32_exitcond_flatten_reg_1202;
ap_reg_pp0_iter33_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter32_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter33_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter32_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter33_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter32_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter33_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter32_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter33_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter32_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter33_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter32_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter33_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter32_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter33_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter32_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter33_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter32_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter33_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter32_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter33_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter32_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter33_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter32_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter33_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter32_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter33_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter32_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter33_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter32_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter33_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter32_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter33_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter32_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter33_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter32_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter33_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter32_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter33_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter32_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter34_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter33_exitcond_flatten_reg_1202;
ap_reg_pp0_iter34_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter33_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter34_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter33_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter34_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter33_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter34_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter33_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter34_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter33_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter34_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter33_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter34_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter33_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter34_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter33_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter34_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter33_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter34_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter33_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter34_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter33_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter34_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter33_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter34_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter33_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter34_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter33_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter34_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter33_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter34_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter33_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter34_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter33_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter35_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter34_exitcond_flatten_reg_1202;
ap_reg_pp0_iter35_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter34_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter35_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter34_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter35_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter34_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter35_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter34_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter35_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter34_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter35_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter34_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter35_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter34_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter35_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter34_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter35_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter34_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter35_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter34_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter35_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter34_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter35_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter34_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter35_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter34_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter35_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter34_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter35_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter34_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter35_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter34_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter35_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter34_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter36_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter35_exitcond_flatten_reg_1202;
ap_reg_pp0_iter36_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter35_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter36_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter35_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter36_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter35_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter36_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter35_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter36_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter35_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter36_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter35_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter36_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter35_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter36_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter35_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter36_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter35_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter36_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter35_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter36_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter35_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter36_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter35_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter36_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter35_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter36_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter35_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter36_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter35_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter36_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter35_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter36_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter35_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter37_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter36_exitcond_flatten_reg_1202;
ap_reg_pp0_iter37_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter36_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter37_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter36_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter37_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter36_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter37_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter36_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter37_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter36_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter37_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter36_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter37_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter36_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter37_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter36_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter37_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter36_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter37_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter36_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter37_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter36_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter37_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter36_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter37_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter36_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter37_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter36_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter38_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter37_exitcond_flatten_reg_1202;
ap_reg_pp0_iter38_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter37_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter38_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter37_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter38_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter37_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter38_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter37_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter38_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter37_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter38_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter37_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter38_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter37_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter38_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter37_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter38_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter37_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter38_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter37_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter38_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter37_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter38_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter37_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter38_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter37_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter38_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter37_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter39_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter38_exitcond_flatten_reg_1202;
ap_reg_pp0_iter39_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter38_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter39_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter38_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter39_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter38_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter39_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter38_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter39_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter38_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter39_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter38_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter39_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter38_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter39_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter38_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter39_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter38_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter39_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter38_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter39_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter38_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter39_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter38_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter39_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter38_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter39_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter38_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter3_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter2_exitcond_flatten_reg_1202;
ap_reg_pp0_iter40_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter39_exitcond_flatten_reg_1202;
ap_reg_pp0_iter40_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter39_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter40_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter39_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter40_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter39_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter40_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter39_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter40_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter39_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter40_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter39_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter40_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter39_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter40_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter39_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter40_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter39_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter40_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter39_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter40_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter39_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter41_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter40_exitcond_flatten_reg_1202;
ap_reg_pp0_iter41_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter40_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter41_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter40_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter41_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter40_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter41_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter40_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter41_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter40_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter41_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter40_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter41_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter40_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter41_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter40_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter41_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter40_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter41_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter40_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter41_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter40_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter42_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter41_exitcond_flatten_reg_1202;
ap_reg_pp0_iter42_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter41_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter42_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter41_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter42_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter41_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter42_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter41_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter42_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter41_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter42_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter41_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter42_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter41_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter42_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter41_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter42_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter41_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter42_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter41_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter42_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter41_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter43_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter42_exitcond_flatten_reg_1202;
ap_reg_pp0_iter43_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter42_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter43_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter42_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter43_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter42_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter43_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter42_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter43_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter42_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter43_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter42_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter43_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter42_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter43_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter42_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter44_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter43_exitcond_flatten_reg_1202;
ap_reg_pp0_iter44_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter43_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter44_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter43_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter44_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter43_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter44_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter43_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter44_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter43_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter44_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter43_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter44_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter43_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter44_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter43_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter45_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter44_exitcond_flatten_reg_1202;
ap_reg_pp0_iter45_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter44_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter45_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter44_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter45_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter44_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter45_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter44_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter45_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter44_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter45_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter44_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter45_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter44_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter45_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter44_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter46_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter45_exitcond_flatten_reg_1202;
ap_reg_pp0_iter46_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter45_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter46_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter45_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter46_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter45_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter46_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter45_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter46_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter45_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter47_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter46_exitcond_flatten_reg_1202;
ap_reg_pp0_iter47_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter46_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter47_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter46_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter47_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter46_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter47_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter46_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter47_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter46_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter48_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter47_exitcond_flatten_reg_1202;
ap_reg_pp0_iter48_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter47_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter48_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter47_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter48_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter47_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter48_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter47_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter48_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter47_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter49_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter48_exitcond_flatten_reg_1202;
ap_reg_pp0_iter49_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter48_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter49_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter48_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter4_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter3_exitcond_flatten_reg_1202;
ap_reg_pp0_iter4_tmp_10_0_1_4_reg_2130 <= tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter4_tmp_10_0_2_1_reg_2140 <= tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter4_tmp_10_0_2_2_reg_2145 <= tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter4_tmp_10_0_2_3_reg_2150 <= tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter4_tmp_10_0_2_4_reg_2155 <= tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter4_tmp_10_0_2_reg_2135 <= tmp_10_0_2_reg_2135;
ap_reg_pp0_iter4_tmp_10_0_3_1_reg_2165 <= tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter4_tmp_10_0_3_reg_2160 <= tmp_10_0_3_reg_2160;
ap_reg_pp0_iter4_tmp_10_1_1_3_reg_2170 <= tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter4_tmp_10_1_1_4_reg_2175 <= tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter4_tmp_10_1_2_1_reg_2185 <= tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter4_tmp_10_1_2_2_reg_2190 <= tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter4_tmp_10_1_2_3_reg_2195 <= tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter4_tmp_10_1_2_4_reg_2200 <= tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter4_tmp_10_1_2_reg_2180 <= tmp_10_1_2_reg_2180;
ap_reg_pp0_iter4_tmp_10_1_3_1_reg_2210 <= tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter4_tmp_10_1_3_reg_2205 <= tmp_10_1_3_reg_2205;
ap_reg_pp0_iter4_tmp_10_2_1_3_reg_2215 <= tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter4_tmp_10_2_1_4_reg_2220 <= tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter4_tmp_10_2_2_1_reg_2230 <= tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter4_tmp_10_2_2_2_reg_2235 <= tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter4_tmp_10_2_2_3_reg_2240 <= tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter4_tmp_10_2_2_4_reg_2245 <= tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter4_tmp_10_2_2_reg_2225 <= tmp_10_2_2_reg_2225;
ap_reg_pp0_iter4_tmp_10_2_3_reg_2250 <= tmp_10_2_3_reg_2250;
ap_reg_pp0_iter50_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter49_exitcond_flatten_reg_1202;
ap_reg_pp0_iter50_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter49_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter50_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter49_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter51_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter50_exitcond_flatten_reg_1202;
ap_reg_pp0_iter51_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter50_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter51_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter50_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter52_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter51_exitcond_flatten_reg_1202;
ap_reg_pp0_iter53_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter52_exitcond_flatten_reg_1202;
ap_reg_pp0_iter54_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter53_exitcond_flatten_reg_1202;
ap_reg_pp0_iter55_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter54_exitcond_flatten_reg_1202;
ap_reg_pp0_iter56_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter55_exitcond_flatten_reg_1202;
ap_reg_pp0_iter57_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter56_exitcond_flatten_reg_1202;
ap_reg_pp0_iter58_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter57_exitcond_flatten_reg_1202;
ap_reg_pp0_iter59_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter58_exitcond_flatten_reg_1202;
ap_reg_pp0_iter5_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter4_exitcond_flatten_reg_1202;
ap_reg_pp0_iter5_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter4_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter5_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter4_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter5_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter4_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter5_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter4_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter5_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter4_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter5_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter4_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter5_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter4_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter5_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter4_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter5_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter4_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter5_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter4_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter5_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter4_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter5_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter4_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter5_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter4_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter5_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter4_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter5_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter4_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter5_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter4_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter5_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter4_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter5_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter4_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter5_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter4_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter5_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter4_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter5_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter4_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter5_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter4_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter5_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter4_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter5_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter4_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter5_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter4_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter60_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter59_exitcond_flatten_reg_1202;
ap_reg_pp0_iter61_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter60_exitcond_flatten_reg_1202;
ap_reg_pp0_iter62_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter61_exitcond_flatten_reg_1202;
ap_reg_pp0_iter63_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter62_exitcond_flatten_reg_1202;
ap_reg_pp0_iter64_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter63_exitcond_flatten_reg_1202;
ap_reg_pp0_iter65_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter64_exitcond_flatten_reg_1202;
ap_reg_pp0_iter66_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter65_exitcond_flatten_reg_1202;
ap_reg_pp0_iter67_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter66_exitcond_flatten_reg_1202;
ap_reg_pp0_iter68_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter67_exitcond_flatten_reg_1202;
ap_reg_pp0_iter69_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter68_exitcond_flatten_reg_1202;
ap_reg_pp0_iter6_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter5_exitcond_flatten_reg_1202;
ap_reg_pp0_iter6_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter5_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter6_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter5_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter6_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter5_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter6_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter5_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter6_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter5_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter6_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter5_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter6_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter5_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter6_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter5_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter6_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter5_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter6_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter5_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter6_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter5_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter6_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter5_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter6_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter5_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter6_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter5_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter6_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter5_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter6_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter5_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter6_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter5_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter6_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter5_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter6_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter5_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter6_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter5_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter6_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter5_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter6_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter5_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter6_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter5_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter6_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter5_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter6_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter5_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter70_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter69_exitcond_flatten_reg_1202;
ap_reg_pp0_iter71_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter70_exitcond_flatten_reg_1202;
ap_reg_pp0_iter72_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter71_exitcond_flatten_reg_1202;
ap_reg_pp0_iter73_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter72_exitcond_flatten_reg_1202;
ap_reg_pp0_iter74_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter73_exitcond_flatten_reg_1202;
ap_reg_pp0_iter75_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter74_exitcond_flatten_reg_1202;
ap_reg_pp0_iter76_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter75_exitcond_flatten_reg_1202;
ap_reg_pp0_iter77_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter76_exitcond_flatten_reg_1202;
ap_reg_pp0_iter78_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter77_exitcond_flatten_reg_1202;
ap_reg_pp0_iter7_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter6_exitcond_flatten_reg_1202;
ap_reg_pp0_iter7_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter6_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter7_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter6_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter7_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter6_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter7_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter6_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter7_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter6_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter7_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter6_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter7_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter6_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter7_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter6_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter7_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter6_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter7_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter6_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter7_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter6_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter7_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter6_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter7_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter6_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter7_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter6_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter7_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter6_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter7_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter6_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter7_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter6_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter7_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter6_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter7_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter6_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter7_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter6_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter7_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter6_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter7_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter6_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter7_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter6_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter7_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter6_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter7_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter6_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter8_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter7_exitcond_flatten_reg_1202;
ap_reg_pp0_iter8_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter7_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter8_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter7_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter8_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter7_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter8_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter7_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter8_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter7_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter8_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter7_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter8_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter7_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter8_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter7_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter8_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter7_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter8_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter7_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter8_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter7_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter8_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter7_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter8_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter7_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter8_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter7_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter8_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter7_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter8_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter7_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter8_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter7_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter8_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter7_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter8_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter7_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter8_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter7_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter8_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter7_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter8_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter7_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter8_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter7_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter8_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter7_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter8_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter7_tmp_10_2_3_reg_2250;
ap_reg_pp0_iter9_exitcond_flatten_reg_1202 <= ap_reg_pp0_iter8_exitcond_flatten_reg_1202;
ap_reg_pp0_iter9_tmp_10_0_1_4_reg_2130 <= ap_reg_pp0_iter8_tmp_10_0_1_4_reg_2130;
ap_reg_pp0_iter9_tmp_10_0_2_1_reg_2140 <= ap_reg_pp0_iter8_tmp_10_0_2_1_reg_2140;
ap_reg_pp0_iter9_tmp_10_0_2_2_reg_2145 <= ap_reg_pp0_iter8_tmp_10_0_2_2_reg_2145;
ap_reg_pp0_iter9_tmp_10_0_2_3_reg_2150 <= ap_reg_pp0_iter8_tmp_10_0_2_3_reg_2150;
ap_reg_pp0_iter9_tmp_10_0_2_4_reg_2155 <= ap_reg_pp0_iter8_tmp_10_0_2_4_reg_2155;
ap_reg_pp0_iter9_tmp_10_0_2_reg_2135 <= ap_reg_pp0_iter8_tmp_10_0_2_reg_2135;
ap_reg_pp0_iter9_tmp_10_0_3_1_reg_2165 <= ap_reg_pp0_iter8_tmp_10_0_3_1_reg_2165;
ap_reg_pp0_iter9_tmp_10_0_3_reg_2160 <= ap_reg_pp0_iter8_tmp_10_0_3_reg_2160;
ap_reg_pp0_iter9_tmp_10_1_1_3_reg_2170 <= ap_reg_pp0_iter8_tmp_10_1_1_3_reg_2170;
ap_reg_pp0_iter9_tmp_10_1_1_4_reg_2175 <= ap_reg_pp0_iter8_tmp_10_1_1_4_reg_2175;
ap_reg_pp0_iter9_tmp_10_1_2_1_reg_2185 <= ap_reg_pp0_iter8_tmp_10_1_2_1_reg_2185;
ap_reg_pp0_iter9_tmp_10_1_2_2_reg_2190 <= ap_reg_pp0_iter8_tmp_10_1_2_2_reg_2190;
ap_reg_pp0_iter9_tmp_10_1_2_3_reg_2195 <= ap_reg_pp0_iter8_tmp_10_1_2_3_reg_2195;
ap_reg_pp0_iter9_tmp_10_1_2_4_reg_2200 <= ap_reg_pp0_iter8_tmp_10_1_2_4_reg_2200;
ap_reg_pp0_iter9_tmp_10_1_2_reg_2180 <= ap_reg_pp0_iter8_tmp_10_1_2_reg_2180;
ap_reg_pp0_iter9_tmp_10_1_3_1_reg_2210 <= ap_reg_pp0_iter8_tmp_10_1_3_1_reg_2210;
ap_reg_pp0_iter9_tmp_10_1_3_reg_2205 <= ap_reg_pp0_iter8_tmp_10_1_3_reg_2205;
ap_reg_pp0_iter9_tmp_10_2_1_3_reg_2215 <= ap_reg_pp0_iter8_tmp_10_2_1_3_reg_2215;
ap_reg_pp0_iter9_tmp_10_2_1_4_reg_2220 <= ap_reg_pp0_iter8_tmp_10_2_1_4_reg_2220;
ap_reg_pp0_iter9_tmp_10_2_2_1_reg_2230 <= ap_reg_pp0_iter8_tmp_10_2_2_1_reg_2230;
ap_reg_pp0_iter9_tmp_10_2_2_2_reg_2235 <= ap_reg_pp0_iter8_tmp_10_2_2_2_reg_2235;
ap_reg_pp0_iter9_tmp_10_2_2_3_reg_2240 <= ap_reg_pp0_iter8_tmp_10_2_2_3_reg_2240;
ap_reg_pp0_iter9_tmp_10_2_2_4_reg_2245 <= ap_reg_pp0_iter8_tmp_10_2_2_4_reg_2245;
ap_reg_pp0_iter9_tmp_10_2_2_reg_2225 <= ap_reg_pp0_iter8_tmp_10_2_2_reg_2225;
ap_reg_pp0_iter9_tmp_10_2_3_reg_2250 <= ap_reg_pp0_iter8_tmp_10_2_3_reg_2250;
exitcond_flatten_reg_1202 <= exitcond_flatten_fu_1044_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter10_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter9_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter10_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter9_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter10_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter9_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter10_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter9_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter10_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter9_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter10_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter9_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter10_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter9_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter10_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter9_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter10_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter9_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter10_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter9_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter10_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter9_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter10_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter9_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter10_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter9_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter10_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter9_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter10_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter9_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter10_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter9_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter11_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter10_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter11_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter10_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter11_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter10_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter11_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter10_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter11_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter10_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter11_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter10_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter11_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter10_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter11_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter10_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter11_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter10_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter11_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter10_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter11_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter10_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter11_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter10_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter11_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter10_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter11_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter10_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter11_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter10_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter11_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter10_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter12_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter11_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter12_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter11_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter12_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter11_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter12_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter11_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter12_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter11_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter12_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter11_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter12_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter11_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter12_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter11_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter12_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter11_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter12_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter11_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter12_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter11_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter12_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter11_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter12_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter11_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter13_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter12_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter13_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter12_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter13_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter12_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter13_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter12_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter13_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter12_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter13_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter12_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter13_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter12_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter13_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter12_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter13_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter12_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter13_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter12_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter13_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter12_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter13_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter12_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter13_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter12_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter14_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter13_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter14_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter13_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter14_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter13_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter14_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter13_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter14_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter13_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter14_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter13_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter14_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter13_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter14_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter13_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter14_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter13_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter14_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter13_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter14_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter13_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter14_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter13_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter14_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter13_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter15_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter14_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter15_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter14_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter15_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter14_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter15_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter14_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter15_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter14_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter15_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter14_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter15_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter14_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter15_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter14_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter15_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter14_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter15_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter14_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter16_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter15_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter16_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter15_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter16_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter15_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter16_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter15_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter16_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter15_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter16_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter15_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter16_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter15_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter16_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter15_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter16_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter15_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter16_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter15_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter17_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter16_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter17_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter16_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter17_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter16_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter17_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter16_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter17_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter16_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter17_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter16_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter17_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter16_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter17_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter16_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter17_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter16_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter17_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter16_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter18_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter17_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter18_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter17_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter18_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter17_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter18_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter17_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter18_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter17_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter18_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter17_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter18_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter17_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter19_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter18_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter19_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter18_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter19_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter18_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter19_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter18_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter19_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter18_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter19_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter18_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter19_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter18_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter20_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter19_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter20_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter19_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter20_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter19_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter20_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter19_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter20_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter19_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter20_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter19_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter20_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter19_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter21_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter20_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter21_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter20_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter21_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter20_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter21_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter20_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter22_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter21_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter22_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter21_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter22_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter21_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter22_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter21_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter23_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter22_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter23_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter22_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter23_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter22_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter23_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter22_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter24_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter23_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter25_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter24_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter26_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter25_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter3_tmp_10_0_0_1_reg_2000 <= tmp_10_0_0_1_reg_2000;
ap_reg_pp0_iter3_tmp_10_0_0_2_reg_2005 <= tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter3_tmp_10_0_0_3_reg_2010 <= tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter3_tmp_10_0_0_4_reg_2015 <= tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter3_tmp_10_0_1_1_reg_2025 <= tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter3_tmp_10_0_1_2_reg_2030 <= tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter3_tmp_10_0_1_3_reg_2035 <= tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter3_tmp_10_0_1_reg_2020 <= tmp_10_0_1_reg_2020;
ap_reg_pp0_iter3_tmp_10_1_0_1_reg_2050 <= tmp_10_1_0_1_reg_2050;
ap_reg_pp0_iter3_tmp_10_1_0_2_reg_2055 <= tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter3_tmp_10_1_0_3_reg_2060 <= tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter3_tmp_10_1_0_4_reg_2065 <= tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter3_tmp_10_1_1_1_reg_2075 <= tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter3_tmp_10_1_1_2_reg_2080 <= tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter3_tmp_10_1_1_reg_2070 <= tmp_10_1_1_reg_2070;
ap_reg_pp0_iter3_tmp_10_2_0_1_reg_2095 <= tmp_10_2_0_1_reg_2095;
ap_reg_pp0_iter3_tmp_10_2_0_2_reg_2100 <= tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter3_tmp_10_2_0_3_reg_2105 <= tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter3_tmp_10_2_0_4_reg_2110 <= tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter3_tmp_10_2_1_1_reg_2120 <= tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter3_tmp_10_2_1_2_reg_2125 <= tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter3_tmp_10_2_1_reg_2115 <= tmp_10_2_1_reg_2115;
ap_reg_pp0_iter4_tmp_10_0_0_1_reg_2000 <= ap_reg_pp0_iter3_tmp_10_0_0_1_reg_2000;
ap_reg_pp0_iter4_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter3_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter4_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter3_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter4_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter3_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter4_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter3_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter4_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter3_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter4_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter3_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter4_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter3_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter4_tmp_10_1_0_1_reg_2050 <= ap_reg_pp0_iter3_tmp_10_1_0_1_reg_2050;
ap_reg_pp0_iter4_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter3_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter4_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter3_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter4_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter3_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter4_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter3_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter4_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter3_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter4_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter3_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter4_tmp_10_2_0_1_reg_2095 <= ap_reg_pp0_iter3_tmp_10_2_0_1_reg_2095;
ap_reg_pp0_iter4_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter3_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter4_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter3_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter4_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter3_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter4_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter3_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter4_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter3_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter4_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter3_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter5_tmp_10_0_0_1_reg_2000 <= ap_reg_pp0_iter4_tmp_10_0_0_1_reg_2000;
ap_reg_pp0_iter5_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter4_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter5_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter4_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter5_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter4_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter5_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter4_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter5_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter4_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter5_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter4_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter5_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter4_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter5_tmp_10_1_0_1_reg_2050 <= ap_reg_pp0_iter4_tmp_10_1_0_1_reg_2050;
ap_reg_pp0_iter5_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter4_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter5_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter4_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter5_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter4_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter5_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter4_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter5_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter4_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter5_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter4_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter5_tmp_10_2_0_1_reg_2095 <= ap_reg_pp0_iter4_tmp_10_2_0_1_reg_2095;
ap_reg_pp0_iter5_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter4_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter5_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter4_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter5_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter4_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter5_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter4_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter5_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter4_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter5_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter4_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter6_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter5_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter6_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter5_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter6_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter5_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter6_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter5_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter6_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter5_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter6_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter5_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter6_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter5_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter6_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter5_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter6_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter5_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter6_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter5_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter6_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter5_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter6_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter5_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter6_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter5_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter6_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter5_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter6_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter5_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter6_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter5_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter6_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter5_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter6_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter5_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter6_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter5_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter7_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter6_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter7_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter6_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter7_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter6_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter7_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter6_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter7_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter6_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter7_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter6_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter7_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter6_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter7_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter6_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter7_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter6_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter7_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter6_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter7_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter6_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter7_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter6_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter7_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter6_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter7_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter6_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter7_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter6_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter7_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter6_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter7_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter6_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter7_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter6_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter7_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter6_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter8_tmp_10_0_0_2_reg_2005 <= ap_reg_pp0_iter7_tmp_10_0_0_2_reg_2005;
ap_reg_pp0_iter8_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter7_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter8_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter7_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter8_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter7_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter8_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter7_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter8_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter7_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter8_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter7_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter8_tmp_10_1_0_2_reg_2055 <= ap_reg_pp0_iter7_tmp_10_1_0_2_reg_2055;
ap_reg_pp0_iter8_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter7_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter8_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter7_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter8_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter7_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter8_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter7_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter8_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter7_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter8_tmp_10_2_0_2_reg_2100 <= ap_reg_pp0_iter7_tmp_10_2_0_2_reg_2100;
ap_reg_pp0_iter8_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter7_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter8_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter7_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter8_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter7_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter8_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter7_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter8_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter7_tmp_10_2_1_reg_2115;
ap_reg_pp0_iter9_tmp_10_0_0_3_reg_2010 <= ap_reg_pp0_iter8_tmp_10_0_0_3_reg_2010;
ap_reg_pp0_iter9_tmp_10_0_0_4_reg_2015 <= ap_reg_pp0_iter8_tmp_10_0_0_4_reg_2015;
ap_reg_pp0_iter9_tmp_10_0_1_1_reg_2025 <= ap_reg_pp0_iter8_tmp_10_0_1_1_reg_2025;
ap_reg_pp0_iter9_tmp_10_0_1_2_reg_2030 <= ap_reg_pp0_iter8_tmp_10_0_1_2_reg_2030;
ap_reg_pp0_iter9_tmp_10_0_1_3_reg_2035 <= ap_reg_pp0_iter8_tmp_10_0_1_3_reg_2035;
ap_reg_pp0_iter9_tmp_10_0_1_reg_2020 <= ap_reg_pp0_iter8_tmp_10_0_1_reg_2020;
ap_reg_pp0_iter9_tmp_10_1_0_3_reg_2060 <= ap_reg_pp0_iter8_tmp_10_1_0_3_reg_2060;
ap_reg_pp0_iter9_tmp_10_1_0_4_reg_2065 <= ap_reg_pp0_iter8_tmp_10_1_0_4_reg_2065;
ap_reg_pp0_iter9_tmp_10_1_1_1_reg_2075 <= ap_reg_pp0_iter8_tmp_10_1_1_1_reg_2075;
ap_reg_pp0_iter9_tmp_10_1_1_2_reg_2080 <= ap_reg_pp0_iter8_tmp_10_1_1_2_reg_2080;
ap_reg_pp0_iter9_tmp_10_1_1_reg_2070 <= ap_reg_pp0_iter8_tmp_10_1_1_reg_2070;
ap_reg_pp0_iter9_tmp_10_2_0_3_reg_2105 <= ap_reg_pp0_iter8_tmp_10_2_0_3_reg_2105;
ap_reg_pp0_iter9_tmp_10_2_0_4_reg_2110 <= ap_reg_pp0_iter8_tmp_10_2_0_4_reg_2110;
ap_reg_pp0_iter9_tmp_10_2_1_1_reg_2120 <= ap_reg_pp0_iter8_tmp_10_2_1_1_reg_2120;
ap_reg_pp0_iter9_tmp_10_2_1_2_reg_2125 <= ap_reg_pp0_iter8_tmp_10_2_1_2_reg_2125;
ap_reg_pp0_iter9_tmp_10_2_1_reg_2115 <= ap_reg_pp0_iter8_tmp_10_2_1_reg_2115;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufi_0_load_1_reg_1554 <= bufi_0_Dout_B;
bufi_0_load_2_reg_1606 <= bufi_0_Dout_A;
bufi_1_load_1_reg_1566 <= bufi_1_Dout_B;
bufi_1_load_2_reg_1611 <= bufi_1_Dout_A;
bufi_2_load_1_reg_1579 <= bufi_2_Dout_B;
bufi_2_load_2_reg_1617 <= bufi_2_Dout_A;
bufi_3_load_1_reg_1592 <= bufi_3_Dout_B;
bufi_3_load_2_reg_1624 <= bufi_3_Dout_A;
bufi_4_load_1_reg_1599 <= bufi_4_Dout_B;
bufi_4_load_2_reg_1631 <= bufi_4_Dout_A;
bufi_5_load_1_reg_1673 <= bufi_5_Dout_B;
bufi_5_load_2_reg_1679 <= bufi_5_Dout_A;
bufi_6_load_1_reg_1685 <= bufi_6_Dout_B;
bufi_6_load_2_reg_1690 <= bufi_6_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 == 1'd0))) begin
bufi_0_load_3_reg_1784 <= bufi_0_Dout_A;
bufi_1_load_3_reg_1795 <= bufi_1_Dout_A;
bufi_2_load_3_reg_1801 <= bufi_2_Dout_A;
bufi_3_load_3_reg_1808 <= bufi_3_Dout_A;
bufi_4_load_3_reg_1815 <= bufi_4_Dout_A;
bufi_5_load_3_reg_1857 <= bufi_5_Dout_A;
bufi_6_load_3_reg_1863 <= bufi_6_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 == 1'd0))) begin
bufi_0_load_4_reg_1896 <= bufi_0_Dout_B;
bufi_1_load_4_reg_1908 <= bufi_1_Dout_B;
bufi_2_load_4_reg_1921 <= bufi_2_Dout_B;
bufi_3_load_4_reg_1935 <= bufi_3_Dout_B;
bufi_4_load_4_reg_1949 <= bufi_4_Dout_B;
bufi_5_load_4_reg_1956 <= bufi_5_Dout_B;
bufi_6_load_4_reg_1962 <= bufi_6_Dout_B;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufi_0_load_reg_1354 <= bufi_0_Dout_A;
bufi_1_load_reg_1359 <= bufi_1_Dout_A;
bufi_2_load_reg_1365 <= bufi_2_Dout_A;
bufi_3_load_reg_1372 <= bufi_3_Dout_A;
bufi_4_load_reg_1379 <= bufi_4_Dout_A;
bufi_5_load_reg_1461 <= bufi_5_Dout_A;
bufi_6_load_reg_1467 <= bufi_6_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten_reg_1202 == 1'd0))) begin
bufo_0_addr_reg_1972 <= tmp_4_cast_fu_1196_p1;
bufo_1_addr_reg_1978 <= tmp_4_cast_fu_1196_p1;
bufo_2_addr_reg_1984 <= tmp_4_cast_fu_1196_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
bufo_0_load_reg_1990 <= bufo_0_Dout_A;
bufo_1_load_reg_2040 <= bufo_1_Dout_A;
bufo_2_load_reg_2085 <= bufo_2_Dout_A;
tmp_10_0_0_1_reg_2000 <= grp_fu_948_p2;
tmp_10_0_0_2_reg_2005 <= grp_fu_952_p2;
tmp_10_0_0_3_reg_2010 <= grp_fu_956_p2;
tmp_10_0_0_4_reg_2015 <= grp_fu_960_p2;
tmp_10_0_1_1_reg_2025 <= grp_fu_968_p2;
tmp_10_0_1_2_reg_2030 <= grp_fu_972_p2;
tmp_10_0_1_3_reg_2035 <= grp_fu_976_p2;
tmp_10_0_1_reg_2020 <= grp_fu_964_p2;
tmp_10_1_0_1_reg_2050 <= grp_fu_984_p2;
tmp_10_1_0_2_reg_2055 <= grp_fu_988_p2;
tmp_10_1_0_3_reg_2060 <= grp_fu_992_p2;
tmp_10_1_0_4_reg_2065 <= grp_fu_996_p2;
tmp_10_1_1_1_reg_2075 <= grp_fu_1004_p2;
tmp_10_1_1_2_reg_2080 <= grp_fu_1008_p2;
tmp_10_1_1_reg_2070 <= grp_fu_1000_p2;
tmp_10_1_reg_2045 <= grp_fu_980_p2;
tmp_10_2_0_1_reg_2095 <= grp_fu_1016_p2;
tmp_10_2_0_2_reg_2100 <= grp_fu_1020_p2;
tmp_10_2_0_3_reg_2105 <= grp_fu_1024_p2;
tmp_10_2_0_4_reg_2110 <= grp_fu_1028_p2;
tmp_10_2_1_1_reg_2120 <= grp_fu_1036_p2;
tmp_10_2_1_2_reg_2125 <= grp_fu_1040_p2;
tmp_10_2_1_reg_2115 <= grp_fu_1032_p2;
tmp_10_2_reg_2090 <= grp_fu_1012_p2;
tmp_s_reg_1995 <= grp_fu_944_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_reg_1202 == 1'd0))) begin
bufw_0_0_load_reg_1512 <= bufw_0_0_Dout_A;
bufw_0_1_load_reg_1519 <= bufw_0_1_Dout_A;
bufw_0_2_load_reg_1526 <= bufw_0_2_Dout_A;
bufw_0_3_load_reg_1533 <= bufw_0_3_Dout_A;
bufw_0_4_load_reg_1540 <= bufw_0_4_Dout_A;
bufw_1_0_load_reg_1547 <= bufw_1_0_Dout_A;
bufw_1_1_load_reg_1559 <= bufw_1_1_Dout_A;
bufw_1_2_load_reg_1572 <= bufw_1_2_Dout_A;
bufw_1_3_load_reg_1586 <= bufw_1_3_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 == 1'd0))) begin
bufw_1_4_load_reg_1735 <= bufw_1_4_Dout_A;
bufw_2_0_load_reg_1742 <= bufw_2_0_Dout_A;
bufw_2_1_load_reg_1749 <= bufw_2_1_Dout_A;
bufw_2_2_load_reg_1756 <= bufw_2_2_Dout_A;
bufw_2_3_load_reg_1763 <= bufw_2_3_Dout_A;
bufw_2_4_load_reg_1770 <= bufw_2_4_Dout_A;
bufw_3_0_load_reg_1777 <= bufw_3_0_Dout_A;
bufw_3_1_load_reg_1789 <= bufw_3_1_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 == 1'd0))) begin
bufw_3_2_load_reg_1868 <= bufw_3_2_Dout_A;
bufw_3_3_load_reg_1875 <= bufw_3_3_Dout_A;
bufw_3_4_load_reg_1882 <= bufw_3_4_Dout_A;
bufw_4_0_load_reg_1889 <= bufw_4_0_Dout_A;
bufw_4_1_load_reg_1901 <= bufw_4_1_Dout_A;
bufw_4_2_load_reg_1914 <= bufw_4_2_Dout_A;
bufw_4_3_load_reg_1928 <= bufw_4_3_Dout_A;
bufw_4_4_load_reg_1942 <= bufw_4_4_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
indvar_flatten_next_reg_1206 <= indvar_flatten_next_fu_1050_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (exitcond_flatten_reg_1202 == 1'd0))) begin
lhs_V_cast1_reg_1273[1 : 0] <= lhs_V_cast1_fu_1092_p1[1 : 0];
r_V_1_0_2_reg_1284 <= r_V_1_0_2_fu_1100_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (exitcond_flatten_fu_1044_p2 == 1'd0))) begin
p_1_mid2_reg_1221 <= p_1_mid2_fu_1068_p3;
tmp_1_reg_1216 <= tmp_1_fu_1062_p2;
to_b_V_reg_1211 <= to_b_V_fu_1056_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
r_V_1_0_3_reg_1456 <= r_V_1_0_3_fu_1138_p2;
tmp_mid2_reg_1289[6 : 0] <= tmp_mid2_fu_1106_p1[6 : 0];
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (exitcond_flatten_reg_1202 == 1'd0))) begin
row_b_V_reg_1278 <= row_b_V_fu_1095_p2;
tmp_mid2_v_reg_1230 <= tmp_mid2_v_fu_1076_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_reg_pp0_iter8_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_0_1_reg_2395 <= grp_fu_856_p2;
temp_2_1_0_1_reg_2400 <= grp_fu_860_p2;
temp_2_2_0_1_reg_2405 <= grp_fu_864_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter11) & (ap_reg_pp0_iter11_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_0_2_reg_2410 <= grp_fu_868_p2;
temp_2_1_0_2_reg_2415 <= grp_fu_872_p2;
temp_2_2_0_2_reg_2420 <= grp_fu_876_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter14) & (ap_reg_pp0_iter14_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_0_3_reg_2425 <= grp_fu_880_p2;
temp_2_1_0_3_reg_2430 <= grp_fu_884_p2;
temp_2_2_0_3_reg_2435 <= grp_fu_888_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter17) & (ap_reg_pp0_iter17_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_0_4_reg_2440 <= grp_fu_892_p2;
temp_2_1_0_4_reg_2445 <= grp_fu_896_p2;
temp_2_2_0_4_reg_2450 <= grp_fu_900_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter23) & (ap_reg_pp0_iter23_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_1_1_reg_2470 <= grp_fu_916_p2;
temp_2_1_1_1_reg_2475 <= grp_fu_920_p2;
temp_2_2_1_1_reg_2480 <= grp_fu_924_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter26) & (ap_reg_pp0_iter26_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_1_2_reg_2485 <= grp_fu_928_p2;
temp_2_1_1_2_reg_2490 <= grp_fu_932_p2;
temp_2_2_1_2_reg_2495 <= grp_fu_936_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter29) & (ap_reg_pp0_iter29_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_1_3_reg_2500 <= grp_fu_940_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter33) & (ap_reg_pp0_iter32_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_1_4_reg_2515 <= grp_fu_852_p2;
temp_2_1_1_4_reg_2520 <= grp_fu_856_p2;
temp_2_2_1_4_reg_2525 <= grp_fu_860_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter20) & (ap_reg_pp0_iter20_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_1_reg_2455 <= grp_fu_904_p2;
temp_2_1_1_reg_2460 <= grp_fu_908_p2;
temp_2_2_1_reg_2465 <= grp_fu_912_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter39) & (ap_reg_pp0_iter38_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_2_1_reg_2545 <= grp_fu_876_p2;
temp_2_1_2_1_reg_2550 <= grp_fu_880_p2;
temp_2_2_2_1_reg_2555 <= grp_fu_884_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter42) & (ap_reg_pp0_iter41_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_2_2_reg_2560 <= grp_fu_888_p2;
temp_2_1_2_2_reg_2565 <= grp_fu_892_p2;
temp_2_2_2_2_reg_2570 <= grp_fu_896_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter45) & (ap_reg_pp0_iter44_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_2_3_reg_2575 <= grp_fu_900_p2;
temp_2_1_2_3_reg_2580 <= grp_fu_904_p2;
temp_2_2_2_3_reg_2585 <= grp_fu_908_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter48) & (ap_reg_pp0_iter47_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_2_4_reg_2590 <= grp_fu_912_p2;
temp_2_1_2_4_reg_2595 <= grp_fu_916_p2;
temp_2_2_2_4_reg_2600 <= grp_fu_920_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter36) & (ap_reg_pp0_iter35_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_2_reg_2530 <= grp_fu_864_p2;
temp_2_1_2_reg_2535 <= grp_fu_868_p2;
temp_2_2_2_reg_2540 <= grp_fu_872_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter54) & (ap_reg_pp0_iter53_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_3_1_reg_2620 <= grp_fu_936_p2;
temp_2_1_3_1_reg_2625 <= grp_fu_940_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter57) & (ap_reg_pp0_iter57_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_3_2_reg_2635 <= grp_fu_848_p2;
temp_2_1_3_2_reg_2640 <= grp_fu_852_p2;
temp_2_2_3_2_reg_2645 <= grp_fu_856_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter60) & (ap_reg_pp0_iter60_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_3_3_reg_2650 <= grp_fu_860_p2;
temp_2_1_3_3_reg_2655 <= grp_fu_864_p2;
temp_2_2_3_3_reg_2660 <= grp_fu_868_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter63) & (ap_reg_pp0_iter63_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_3_4_reg_2665 <= grp_fu_872_p2;
temp_2_1_3_4_reg_2670 <= grp_fu_876_p2;
temp_2_2_3_4_reg_2675 <= grp_fu_880_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter51) & (ap_reg_pp0_iter50_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_3_reg_2605 <= grp_fu_924_p2;
temp_2_1_3_reg_2610 <= grp_fu_928_p2;
temp_2_2_3_reg_2615 <= grp_fu_932_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter69) & (ap_reg_pp0_iter69_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_4_1_reg_2695 <= grp_fu_896_p2;
temp_2_1_4_1_reg_2700 <= grp_fu_900_p2;
temp_2_2_4_1_reg_2705 <= grp_fu_904_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter72) & (ap_reg_pp0_iter72_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_4_2_reg_2710 <= grp_fu_908_p2;
temp_2_1_4_2_reg_2715 <= grp_fu_912_p2;
temp_2_2_4_2_reg_2720 <= grp_fu_916_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter75) & (ap_reg_pp0_iter75_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_4_3_reg_2725 <= grp_fu_920_p2;
temp_2_1_4_3_reg_2730 <= grp_fu_924_p2;
temp_2_2_4_3_reg_2735 <= grp_fu_928_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter78) & (ap_reg_pp0_iter78_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_4_4_reg_2740 <= grp_fu_932_p2;
temp_2_1_4_4_reg_2745 <= grp_fu_936_p2;
temp_2_2_4_4_reg_2750 <= grp_fu_940_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter66) & (ap_reg_pp0_iter66_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_0_4_reg_2680 <= grp_fu_884_p2;
temp_2_1_4_reg_2685 <= grp_fu_888_p2;
temp_2_2_4_reg_2690 <= grp_fu_892_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_reg_pp0_iter29_exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter30))) begin
temp_2_1_1_3_reg_2505 <= grp_fu_844_p2;
temp_2_2_1_3_reg_2510 <= grp_fu_848_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_reg_pp0_iter5_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_1_reg_2385 <= grp_fu_848_p2;
temp_2_2_reg_2390 <= grp_fu_852_p2;
temp_2_reg_2380 <= grp_fu_844_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter54) & (ap_reg_pp0_iter54_exitcond_flatten_reg_1202 == 1'd0))) begin
temp_2_2_3_1_reg_2630 <= grp_fu_844_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
tmp_10_0_1_4_reg_2130 <= grp_fu_944_p2;
tmp_10_0_2_1_reg_2140 <= grp_fu_952_p2;
tmp_10_0_2_2_reg_2145 <= grp_fu_956_p2;
tmp_10_0_2_3_reg_2150 <= grp_fu_960_p2;
tmp_10_0_2_4_reg_2155 <= grp_fu_964_p2;
tmp_10_0_2_reg_2135 <= grp_fu_948_p2;
tmp_10_0_3_1_reg_2165 <= grp_fu_972_p2;
tmp_10_0_3_reg_2160 <= grp_fu_968_p2;
tmp_10_1_1_3_reg_2170 <= grp_fu_976_p2;
tmp_10_1_1_4_reg_2175 <= grp_fu_980_p2;
tmp_10_1_2_1_reg_2185 <= grp_fu_988_p2;
tmp_10_1_2_2_reg_2190 <= grp_fu_992_p2;
tmp_10_1_2_3_reg_2195 <= grp_fu_996_p2;
tmp_10_1_2_4_reg_2200 <= grp_fu_1000_p2;
tmp_10_1_2_reg_2180 <= grp_fu_984_p2;
tmp_10_1_3_1_reg_2210 <= grp_fu_1008_p2;
tmp_10_1_3_reg_2205 <= grp_fu_1004_p2;
tmp_10_2_1_3_reg_2215 <= grp_fu_1012_p2;
tmp_10_2_1_4_reg_2220 <= grp_fu_1016_p2;
tmp_10_2_2_1_reg_2230 <= grp_fu_1024_p2;
tmp_10_2_2_2_reg_2235 <= grp_fu_1028_p2;
tmp_10_2_2_3_reg_2240 <= grp_fu_1032_p2;
tmp_10_2_2_4_reg_2245 <= grp_fu_1036_p2;
tmp_10_2_2_reg_2225 <= grp_fu_1020_p2;
tmp_10_2_3_reg_2250 <= grp_fu_1040_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_reg_pp0_iter3_exitcond_flatten_reg_1202 == 1'd0))) begin
tmp_10_0_3_2_reg_2255 <= grp_fu_944_p2;
tmp_10_0_3_3_reg_2260 <= grp_fu_948_p2;
tmp_10_0_3_4_reg_2265 <= grp_fu_952_p2;
tmp_10_0_4_1_reg_2275 <= grp_fu_960_p2;
tmp_10_0_4_2_reg_2280 <= grp_fu_964_p2;
tmp_10_0_4_3_reg_2285 <= grp_fu_968_p2;
tmp_10_0_4_4_reg_2290 <= grp_fu_972_p2;
tmp_10_0_4_reg_2270 <= grp_fu_956_p2;
tmp_10_1_3_2_reg_2295 <= grp_fu_976_p2;
tmp_10_1_3_3_reg_2300 <= grp_fu_980_p2;
tmp_10_1_3_4_reg_2305 <= grp_fu_984_p2;
tmp_10_1_4_1_reg_2315 <= grp_fu_992_p2;
tmp_10_1_4_2_reg_2320 <= grp_fu_996_p2;
tmp_10_1_4_3_reg_2325 <= grp_fu_1000_p2;
tmp_10_1_4_4_reg_2330 <= grp_fu_1004_p2;
tmp_10_1_4_reg_2310 <= grp_fu_988_p2;
tmp_10_2_3_1_reg_2335 <= grp_fu_1008_p2;
tmp_10_2_3_2_reg_2340 <= grp_fu_1012_p2;
tmp_10_2_3_3_reg_2345 <= grp_fu_1016_p2;
tmp_10_2_3_4_reg_2350 <= grp_fu_1020_p2;
tmp_10_2_4_1_reg_2360 <= grp_fu_1028_p2;
tmp_10_2_4_2_reg_2365 <= grp_fu_1032_p2;
tmp_10_2_4_3_reg_2370 <= grp_fu_1036_p2;
tmp_10_2_4_4_reg_2375 <= grp_fu_1040_p2;
tmp_10_2_4_reg_2355 <= grp_fu_1024_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten_reg_1202 == 1'd0))) begin
tmp_4_reg_1967 <= tmp_4_fu_1190_p2;
end
end
always @ (*) begin
if ((exitcond_flatten_fu_1044_p2 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state2 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state2 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state239)) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9) & (1'b0 == ap_enable_reg_pp0_iter10) & (1'b0 == ap_enable_reg_pp0_iter11) & (1'b0 == ap_enable_reg_pp0_iter12) & (1'b0 == ap_enable_reg_pp0_iter13) & (1'b0 == ap_enable_reg_pp0_iter14) & (1'b0 == ap_enable_reg_pp0_iter15) & (1'b0 == ap_enable_reg_pp0_iter16) & (1'b0 == ap_enable_reg_pp0_iter17) & (1'b0 == ap_enable_reg_pp0_iter18) & (1'b0 == ap_enable_reg_pp0_iter19) & (1'b0 == ap_enable_reg_pp0_iter20) & (1'b0 == ap_enable_reg_pp0_iter21) & (1'b0 == ap_enable_reg_pp0_iter22) & (1'b0 == ap_enable_reg_pp0_iter23) & (1'b0 == ap_enable_reg_pp0_iter24) & (1'b0 == ap_enable_reg_pp0_iter25) & (1'b0 == ap_enable_reg_pp0_iter26) & (1'b0 == ap_enable_reg_pp0_iter27) & (1'b0 == ap_enable_reg_pp0_iter28) & (1'b0 == ap_enable_reg_pp0_iter29) & (1'b0 == ap_enable_reg_pp0_iter30) & (1'b0 == ap_enable_reg_pp0_iter31) & (1'b0 == ap_enable_reg_pp0_iter32) & (1'b0 == ap_enable_reg_pp0_iter33) & (1'b0 == ap_enable_reg_pp0_iter34) & (1'b0 == ap_enable_reg_pp0_iter35) & (1'b0 == ap_enable_reg_pp0_iter36) & (1'b0 == ap_enable_reg_pp0_iter37) & (1'b0 == ap_enable_reg_pp0_iter38) & (1'b0 == ap_enable_reg_pp0_iter39) & (1'b0 == ap_enable_reg_pp0_iter40) & (1'b0 == ap_enable_reg_pp0_iter41) & (1'b0 == ap_enable_reg_pp0_iter42) & (1'b0 == ap_enable_reg_pp0_iter43) & (1'b0 == ap_enable_reg_pp0_iter44) & (1'b0 == ap_enable_reg_pp0_iter45) & (1'b0 == ap_enable_reg_pp0_iter46) & (1'b0 == ap_enable_reg_pp0_iter47) & (1'b0 == ap_enable_reg_pp0_iter48) & (1'b0 == ap_enable_reg_pp0_iter49) & (1'b0 == ap_enable_reg_pp0_iter50) & (1'b0 == ap_enable_reg_pp0_iter51) & (1'b0 == ap_enable_reg_pp0_iter52) & (1'b0 == ap_enable_reg_pp0_iter53) & (1'b0 == ap_enable_reg_pp0_iter54) & (1'b0 == ap_enable_reg_pp0_iter55) & (1'b0 == ap_enable_reg_pp0_iter56) & (1'b0 == ap_enable_reg_pp0_iter57) & (1'b0 == ap_enable_reg_pp0_iter58) & (1'b0 == ap_enable_reg_pp0_iter59) & (1'b0 == ap_enable_reg_pp0_iter60) & (1'b0 == ap_enable_reg_pp0_iter61) & (1'b0 == ap_enable_reg_pp0_iter62) & (1'b0 == ap_enable_reg_pp0_iter63) & (1'b0 == ap_enable_reg_pp0_iter64) & (1'b0 == ap_enable_reg_pp0_iter65) & (1'b0 == ap_enable_reg_pp0_iter66) & (1'b0 == ap_enable_reg_pp0_iter67) & (1'b0 == ap_enable_reg_pp0_iter68) & (1'b0 == ap_enable_reg_pp0_iter69) & (1'b0 == ap_enable_reg_pp0_iter70) & (1'b0 == ap_enable_reg_pp0_iter71) & (1'b0 == ap_enable_reg_pp0_iter72) & (1'b0 == ap_enable_reg_pp0_iter73) & (1'b0 == ap_enable_reg_pp0_iter74) & (1'b0 == ap_enable_reg_pp0_iter75) & (1'b0 == ap_enable_reg_pp0_iter76) & (1'b0 == ap_enable_reg_pp0_iter77) & (1'b0 == ap_enable_reg_pp0_iter78))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state239)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
bufi_0_Addr_A_orig = tmp_2_0_3_fu_1143_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_0_Addr_A_orig = tmp_2_0_2_fu_1128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_0_Addr_A_orig = tmp_3_fu_1082_p1;
end else begin
bufi_0_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_0_Addr_B_orig = tmp_2_0_4_fu_1160_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_0_Addr_B_orig = tmp_2_0_1_fu_1118_p1;
end else begin
bufi_0_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_0_EN_A = 1'b1;
end else begin
bufi_0_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_0_EN_B = 1'b1;
end else begin
bufi_0_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
bufi_1_Addr_A_orig = tmp_2_0_3_fu_1143_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_1_Addr_A_orig = tmp_2_0_2_fu_1128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_1_Addr_A_orig = tmp_3_fu_1082_p1;
end else begin
bufi_1_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_1_Addr_B_orig = tmp_2_0_4_fu_1160_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_1_Addr_B_orig = tmp_2_0_1_fu_1118_p1;
end else begin
bufi_1_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_1_EN_A = 1'b1;
end else begin
bufi_1_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_1_EN_B = 1'b1;
end else begin
bufi_1_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
bufi_2_Addr_A_orig = tmp_2_0_3_fu_1143_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_2_Addr_A_orig = tmp_2_0_2_fu_1128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_2_Addr_A_orig = tmp_3_fu_1082_p1;
end else begin
bufi_2_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_2_Addr_B_orig = tmp_2_0_4_fu_1160_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_2_Addr_B_orig = tmp_2_0_1_fu_1118_p1;
end else begin
bufi_2_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_2_EN_A = 1'b1;
end else begin
bufi_2_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_2_EN_B = 1'b1;
end else begin
bufi_2_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
bufi_3_Addr_A_orig = tmp_2_0_3_fu_1143_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_3_Addr_A_orig = tmp_2_0_2_fu_1128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_3_Addr_A_orig = tmp_3_fu_1082_p1;
end else begin
bufi_3_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_3_Addr_B_orig = tmp_2_0_4_fu_1160_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_3_Addr_B_orig = tmp_2_0_1_fu_1118_p1;
end else begin
bufi_3_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_3_EN_A = 1'b1;
end else begin
bufi_3_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_3_EN_B = 1'b1;
end else begin
bufi_3_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
bufi_4_Addr_A_orig = tmp_2_0_3_fu_1143_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_4_Addr_A_orig = tmp_2_0_2_fu_1128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_4_Addr_A_orig = tmp_3_fu_1082_p1;
end else begin
bufi_4_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_4_Addr_B_orig = tmp_2_0_4_fu_1160_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_4_Addr_B_orig = tmp_2_0_1_fu_1118_p1;
end else begin
bufi_4_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_4_EN_A = 1'b1;
end else begin
bufi_4_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_4_EN_B = 1'b1;
end else begin
bufi_4_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
bufi_5_Addr_A_orig = tmp_2_0_3_fu_1143_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_5_Addr_A_orig = tmp_2_0_2_fu_1128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_5_Addr_A_orig = tmp_3_fu_1082_p1;
end else begin
bufi_5_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_5_Addr_B_orig = tmp_2_0_4_fu_1160_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_5_Addr_B_orig = tmp_2_0_1_fu_1118_p1;
end else begin
bufi_5_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_5_EN_A = 1'b1;
end else begin
bufi_5_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_5_EN_B = 1'b1;
end else begin
bufi_5_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
bufi_6_Addr_A_orig = tmp_2_0_3_fu_1143_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_6_Addr_A_orig = tmp_2_0_2_fu_1128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_6_Addr_A_orig = tmp_3_fu_1082_p1;
end else begin
bufi_6_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufi_6_Addr_B_orig = tmp_2_0_4_fu_1160_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufi_6_Addr_B_orig = tmp_2_0_1_fu_1118_p1;
end else begin
bufi_6_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_6_EN_A = 1'b1;
end else begin
bufi_6_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1)))) begin
bufi_6_EN_B = 1'b1;
end else begin
bufi_6_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
bufo_0_EN_A = 1'b1;
end else begin
bufo_0_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter78))) begin
bufo_0_EN_B = 1'b1;
end else begin
bufo_0_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter78) & (ap_reg_pp0_iter78_exitcond_flatten_reg_1202 == 1'd0))) begin
bufo_0_WEN_B = 4'd15;
end else begin
bufo_0_WEN_B = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
bufo_1_EN_A = 1'b1;
end else begin
bufo_1_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter78))) begin
bufo_1_EN_B = 1'b1;
end else begin
bufo_1_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter78) & (ap_reg_pp0_iter78_exitcond_flatten_reg_1202 == 1'd0))) begin
bufo_1_WEN_B = 4'd15;
end else begin
bufo_1_WEN_B = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
bufo_2_EN_A = 1'b1;
end else begin
bufo_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter78))) begin
bufo_2_EN_B = 1'b1;
end else begin
bufo_2_EN_B = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter78) & (ap_reg_pp0_iter78_exitcond_flatten_reg_1202 == 1'd0))) begin
bufo_2_WEN_B = 4'd15;
end else begin
bufo_2_WEN_B = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_0_0_EN_A = 1'b1;
end else begin
bufw_0_0_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_0_1_EN_A = 1'b1;
end else begin
bufw_0_1_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_0_2_EN_A = 1'b1;
end else begin
bufw_0_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_0_3_EN_A = 1'b1;
end else begin
bufw_0_3_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_0_4_EN_A = 1'b1;
end else begin
bufw_0_4_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_1_0_EN_A = 1'b1;
end else begin
bufw_1_0_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_1_1_EN_A = 1'b1;
end else begin
bufw_1_1_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_1_2_EN_A = 1'b1;
end else begin
bufw_1_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
bufw_1_3_EN_A = 1'b1;
end else begin
bufw_1_3_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_1_4_EN_A = 1'b1;
end else begin
bufw_1_4_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_2_0_EN_A = 1'b1;
end else begin
bufw_2_0_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_2_1_EN_A = 1'b1;
end else begin
bufw_2_1_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_2_2_EN_A = 1'b1;
end else begin
bufw_2_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_2_3_EN_A = 1'b1;
end else begin
bufw_2_3_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_2_4_EN_A = 1'b1;
end else begin
bufw_2_4_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_3_0_EN_A = 1'b1;
end else begin
bufw_3_0_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_3_1_EN_A = 1'b1;
end else begin
bufw_3_1_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_3_2_EN_A = 1'b1;
end else begin
bufw_3_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_3_3_EN_A = 1'b1;
end else begin
bufw_3_3_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_3_4_EN_A = 1'b1;
end else begin
bufw_3_4_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_4_0_EN_A = 1'b1;
end else begin
bufw_4_0_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_4_1_EN_A = 1'b1;
end else begin
bufw_4_1_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_4_2_EN_A = 1'b1;
end else begin
bufw_4_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_4_3_EN_A = 1'b1;
end else begin
bufw_4_3_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
bufw_4_4_EN_A = 1'b1;
end else begin
bufw_4_4_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1000_p0 = bufw_4_3_load_reg_1928;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1000_p0 = bufw_2_4_load_reg_1770;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1000_p0 = bufw_1_0_load_reg_1547;
end else begin
grp_fu_1000_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1000_p1 = bufi_4_load_4_reg_1949;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1000_p1 = bufi_5_load_2_reg_1679;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1000_p1 = bufi_1_load_1_reg_1566;
end else begin
grp_fu_1000_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1004_p0 = bufw_4_4_load_reg_1942;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1004_p0 = bufw_3_0_load_reg_1777;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1004_p0 = bufw_1_1_load_reg_1559;
end else begin
grp_fu_1004_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1004_p1 = bufi_5_load_4_reg_1956;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1004_p1 = bufi_1_load_3_reg_1795;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1004_p1 = bufi_2_load_1_reg_1579;
end else begin
grp_fu_1004_p1 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
grp_fu_1008_p0 = bufw_3_1_load_reg_1789;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1008_p0 = bufw_1_2_load_reg_1572;
end else begin
grp_fu_1008_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1008_p1 = bufi_3_load_3_reg_1808;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1008_p1 = bufi_2_load_3_reg_1801;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1008_p1 = bufi_3_load_1_reg_1592;
end else begin
grp_fu_1008_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1012_p0 = bufw_3_2_load_reg_1868;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1012_p0 = bufw_1_3_load_reg_1586;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1012_p0 = bufw_0_0_load_reg_1512;
end else begin
grp_fu_1012_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1012_p1 = bufi_4_load_3_reg_1815;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1012_p1 = bufi_5_load_1_reg_1673;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1012_p1 = bufi_2_load_reg_1365;
end else begin
grp_fu_1012_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1016_p0 = bufw_3_3_load_reg_1875;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1016_p0 = bufw_1_4_load_reg_1735;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1016_p0 = bufw_0_1_load_reg_1519;
end else begin
grp_fu_1016_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1016_p1 = bufi_5_load_3_reg_1857;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1016_p1 = bufi_6_load_1_reg_1685;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1016_p1 = bufi_3_load_reg_1372;
end else begin
grp_fu_1016_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1020_p0 = bufw_3_4_load_reg_1882;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1020_p0 = bufw_2_0_load_reg_1742;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1020_p0 = bufw_0_2_load_reg_1526;
end else begin
grp_fu_1020_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1020_p1 = bufi_6_load_3_reg_1863;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1020_p1 = bufi_2_load_2_reg_1617;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1020_p1 = bufi_4_load_reg_1379;
end else begin
grp_fu_1020_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1024_p0 = bufw_4_0_load_reg_1889;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1024_p0 = bufw_2_1_load_reg_1749;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1024_p0 = bufw_0_3_load_reg_1533;
end else begin
grp_fu_1024_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1024_p1 = bufi_2_load_4_reg_1921;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1024_p1 = bufi_3_load_2_reg_1624;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1024_p1 = bufi_5_load_reg_1461;
end else begin
grp_fu_1024_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1028_p0 = bufw_4_1_load_reg_1901;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1028_p0 = bufw_2_2_load_reg_1756;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1028_p0 = bufw_0_4_load_reg_1540;
end else begin
grp_fu_1028_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1028_p1 = bufi_3_load_4_reg_1935;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1028_p1 = bufi_4_load_2_reg_1631;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1028_p1 = bufi_6_load_reg_1467;
end else begin
grp_fu_1028_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1032_p0 = bufw_4_2_load_reg_1914;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1032_p0 = bufw_2_3_load_reg_1763;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1032_p0 = bufw_1_0_load_reg_1547;
end else begin
grp_fu_1032_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1032_p1 = bufi_4_load_4_reg_1949;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1032_p1 = bufi_5_load_2_reg_1679;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1032_p1 = bufi_2_load_1_reg_1579;
end else begin
grp_fu_1032_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1036_p0 = bufw_4_3_load_reg_1928;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1036_p0 = bufw_2_4_load_reg_1770;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1036_p0 = bufw_1_1_load_reg_1559;
end else begin
grp_fu_1036_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1036_p1 = bufi_5_load_4_reg_1956;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1036_p1 = bufi_6_load_2_reg_1690;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1036_p1 = bufi_3_load_1_reg_1592;
end else begin
grp_fu_1036_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1040_p0 = bufw_4_4_load_reg_1942;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1040_p0 = bufw_3_0_load_reg_1777;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1040_p0 = bufw_1_2_load_reg_1572;
end else begin
grp_fu_1040_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_1040_p1 = bufi_6_load_4_reg_1962;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_1040_p1 = bufi_2_load_3_reg_1801;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_1040_p1 = bufi_4_load_1_reg_1599;
end else begin
grp_fu_1040_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter51) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_844_p0 = temp_2_2_3_reg_2615;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter27))) begin
grp_fu_844_p0 = temp_2_1_1_2_reg_2490;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_844_p0 = bufo_0_load_reg_1990;
end else begin
grp_fu_844_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter51) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_844_p1 = ap_reg_pp0_iter51_tmp_10_2_3_1_reg_2335;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter27))) begin
grp_fu_844_p1 = ap_reg_pp0_iter27_tmp_10_1_1_3_reg_2170;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_844_p1 = tmp_s_reg_1995;
end else begin
grp_fu_844_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter54) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_848_p0 = temp_2_0_3_1_reg_2620;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter27))) begin
grp_fu_848_p0 = temp_2_2_1_2_reg_2495;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_848_p0 = bufo_1_load_reg_2040;
end else begin
grp_fu_848_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter54) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_848_p1 = ap_reg_pp0_iter54_tmp_10_0_3_2_reg_2255;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter27))) begin
grp_fu_848_p1 = ap_reg_pp0_iter27_tmp_10_2_1_3_reg_2215;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_848_p1 = tmp_10_1_reg_2045;
end else begin
grp_fu_848_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter54) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_852_p0 = temp_2_1_3_1_reg_2625;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter30) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_852_p0 = temp_2_0_1_3_reg_2500;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_852_p0 = bufo_2_load_reg_2085;
end else begin
grp_fu_852_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter54) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_852_p1 = ap_reg_pp0_iter54_tmp_10_1_3_2_reg_2295;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter30) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_852_p1 = ap_reg_pp0_iter30_tmp_10_0_1_4_reg_2130;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_852_p1 = tmp_10_2_reg_2090;
end else begin
grp_fu_852_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter54) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_856_p0 = temp_2_2_3_1_reg_2630;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter30) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_856_p0 = temp_2_1_1_3_reg_2505;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_856_p0 = temp_2_reg_2380;
end else begin
grp_fu_856_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter54) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_856_p1 = ap_reg_pp0_iter54_tmp_10_2_3_2_reg_2340;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter30) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_856_p1 = ap_reg_pp0_iter30_tmp_10_1_1_4_reg_2175;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_856_p1 = ap_reg_pp0_iter5_tmp_10_0_0_1_reg_2000;
end else begin
grp_fu_856_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter57) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_860_p0 = temp_2_0_3_2_reg_2635;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter30) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_860_p0 = temp_2_2_1_3_reg_2510;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_860_p0 = temp_2_1_reg_2385;
end else begin
grp_fu_860_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter57) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_860_p1 = ap_reg_pp0_iter57_tmp_10_0_3_3_reg_2260;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter30) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_860_p1 = ap_reg_pp0_iter30_tmp_10_2_1_4_reg_2220;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_860_p1 = ap_reg_pp0_iter5_tmp_10_1_0_1_reg_2050;
end else begin
grp_fu_860_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter57) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_864_p0 = temp_2_1_3_2_reg_2640;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter33) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_864_p0 = temp_2_0_1_4_reg_2515;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_864_p0 = temp_2_2_reg_2390;
end else begin
grp_fu_864_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter57) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_864_p1 = ap_reg_pp0_iter57_tmp_10_1_3_3_reg_2300;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter33) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_864_p1 = ap_reg_pp0_iter33_tmp_10_0_2_reg_2135;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_864_p1 = ap_reg_pp0_iter5_tmp_10_2_0_1_reg_2095;
end else begin
grp_fu_864_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter57) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_868_p0 = temp_2_2_3_2_reg_2645;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter33) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_868_p0 = temp_2_1_1_4_reg_2520;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
grp_fu_868_p0 = temp_2_0_0_1_reg_2395;
end else begin
grp_fu_868_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter57) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_868_p1 = ap_reg_pp0_iter57_tmp_10_2_3_3_reg_2345;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter33) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_868_p1 = ap_reg_pp0_iter33_tmp_10_1_2_reg_2180;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
grp_fu_868_p1 = ap_reg_pp0_iter8_tmp_10_0_0_2_reg_2005;
end else begin
grp_fu_868_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter60) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_872_p0 = temp_2_0_3_3_reg_2650;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter33) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_872_p0 = temp_2_2_1_4_reg_2525;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
grp_fu_872_p0 = temp_2_1_0_1_reg_2400;
end else begin
grp_fu_872_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter60) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_872_p1 = ap_reg_pp0_iter60_tmp_10_0_3_4_reg_2265;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter33) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_872_p1 = ap_reg_pp0_iter33_tmp_10_2_2_reg_2225;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
grp_fu_872_p1 = ap_reg_pp0_iter8_tmp_10_1_0_2_reg_2055;
end else begin
grp_fu_872_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter60) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_876_p0 = temp_2_1_3_3_reg_2655;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter36) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_876_p0 = temp_2_0_2_reg_2530;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
grp_fu_876_p0 = temp_2_2_0_1_reg_2405;
end else begin
grp_fu_876_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter60) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_876_p1 = ap_reg_pp0_iter60_tmp_10_1_3_4_reg_2305;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter36) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_876_p1 = ap_reg_pp0_iter36_tmp_10_0_2_1_reg_2140;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
grp_fu_876_p1 = ap_reg_pp0_iter8_tmp_10_2_0_2_reg_2100;
end else begin
grp_fu_876_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter60) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_880_p0 = temp_2_2_3_3_reg_2660;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter36) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_880_p0 = temp_2_1_2_reg_2535;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter12))) begin
grp_fu_880_p0 = temp_2_0_0_2_reg_2410;
end else begin
grp_fu_880_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter60) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_880_p1 = ap_reg_pp0_iter60_tmp_10_2_3_4_reg_2350;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter36) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_880_p1 = ap_reg_pp0_iter36_tmp_10_1_2_1_reg_2185;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter12))) begin
grp_fu_880_p1 = ap_reg_pp0_iter11_tmp_10_0_0_3_reg_2010;
end else begin
grp_fu_880_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter63) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_884_p0 = temp_2_0_3_4_reg_2665;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter36) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_884_p0 = temp_2_2_2_reg_2540;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter12))) begin
grp_fu_884_p0 = temp_2_1_0_2_reg_2415;
end else begin
grp_fu_884_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter63) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_884_p1 = ap_reg_pp0_iter63_tmp_10_0_4_reg_2270;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter36) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_884_p1 = ap_reg_pp0_iter36_tmp_10_2_2_1_reg_2230;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter12))) begin
grp_fu_884_p1 = ap_reg_pp0_iter11_tmp_10_1_0_3_reg_2060;
end else begin
grp_fu_884_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter63) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_888_p0 = temp_2_1_3_4_reg_2670;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter39) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_888_p0 = temp_2_0_2_1_reg_2545;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter12))) begin
grp_fu_888_p0 = temp_2_2_0_2_reg_2420;
end else begin
grp_fu_888_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter63) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_888_p1 = ap_reg_pp0_iter63_tmp_10_1_4_reg_2310;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter39) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_888_p1 = ap_reg_pp0_iter39_tmp_10_0_2_2_reg_2145;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter12))) begin
grp_fu_888_p1 = ap_reg_pp0_iter11_tmp_10_2_0_3_reg_2105;
end else begin
grp_fu_888_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter63) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_892_p0 = temp_2_2_3_4_reg_2675;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter39) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_892_p0 = temp_2_1_2_1_reg_2550;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter15))) begin
grp_fu_892_p0 = temp_2_0_0_3_reg_2425;
end else begin
grp_fu_892_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter63) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_892_p1 = ap_reg_pp0_iter63_tmp_10_2_4_reg_2355;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter39) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_892_p1 = ap_reg_pp0_iter39_tmp_10_1_2_2_reg_2190;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter15))) begin
grp_fu_892_p1 = ap_reg_pp0_iter14_tmp_10_0_0_4_reg_2015;
end else begin
grp_fu_892_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter66) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_896_p0 = temp_2_0_4_reg_2680;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter39) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_896_p0 = temp_2_2_2_1_reg_2555;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter15))) begin
grp_fu_896_p0 = temp_2_1_0_3_reg_2430;
end else begin
grp_fu_896_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter66) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_896_p1 = ap_reg_pp0_iter66_tmp_10_0_4_1_reg_2275;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter39) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_896_p1 = ap_reg_pp0_iter39_tmp_10_2_2_2_reg_2235;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter15))) begin
grp_fu_896_p1 = ap_reg_pp0_iter14_tmp_10_1_0_4_reg_2065;
end else begin
grp_fu_896_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter66) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_900_p0 = temp_2_1_4_reg_2685;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter42) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_900_p0 = temp_2_0_2_2_reg_2560;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter15))) begin
grp_fu_900_p0 = temp_2_2_0_3_reg_2435;
end else begin
grp_fu_900_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter66) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_900_p1 = ap_reg_pp0_iter66_tmp_10_1_4_1_reg_2315;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter42) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_900_p1 = ap_reg_pp0_iter42_tmp_10_0_2_3_reg_2150;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter15))) begin
grp_fu_900_p1 = ap_reg_pp0_iter14_tmp_10_2_0_4_reg_2110;
end else begin
grp_fu_900_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter66) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_904_p0 = temp_2_2_4_reg_2690;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter42) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_904_p0 = temp_2_1_2_2_reg_2565;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter18))) begin
grp_fu_904_p0 = temp_2_0_0_4_reg_2440;
end else begin
grp_fu_904_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter66) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_904_p1 = ap_reg_pp0_iter66_tmp_10_2_4_1_reg_2360;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter42) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_904_p1 = ap_reg_pp0_iter42_tmp_10_1_2_3_reg_2195;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter18))) begin
grp_fu_904_p1 = ap_reg_pp0_iter17_tmp_10_0_1_reg_2020;
end else begin
grp_fu_904_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter69) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_908_p0 = temp_2_0_4_1_reg_2695;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter42) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_908_p0 = temp_2_2_2_2_reg_2570;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter18))) begin
grp_fu_908_p0 = temp_2_1_0_4_reg_2445;
end else begin
grp_fu_908_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter69) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_908_p1 = ap_reg_pp0_iter69_tmp_10_0_4_2_reg_2280;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter42) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_908_p1 = ap_reg_pp0_iter42_tmp_10_2_2_3_reg_2240;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter18))) begin
grp_fu_908_p1 = ap_reg_pp0_iter17_tmp_10_1_1_reg_2070;
end else begin
grp_fu_908_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter69) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_912_p0 = temp_2_1_4_1_reg_2700;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter45) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_912_p0 = temp_2_0_2_3_reg_2575;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter18))) begin
grp_fu_912_p0 = temp_2_2_0_4_reg_2450;
end else begin
grp_fu_912_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter69) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_912_p1 = ap_reg_pp0_iter69_tmp_10_1_4_2_reg_2320;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter45) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_912_p1 = ap_reg_pp0_iter45_tmp_10_0_2_4_reg_2155;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter18))) begin
grp_fu_912_p1 = ap_reg_pp0_iter17_tmp_10_2_1_reg_2115;
end else begin
grp_fu_912_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter69) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_916_p0 = temp_2_2_4_1_reg_2705;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter45) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_916_p0 = temp_2_1_2_3_reg_2580;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter21))) begin
grp_fu_916_p0 = temp_2_0_1_reg_2455;
end else begin
grp_fu_916_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter69) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_916_p1 = ap_reg_pp0_iter69_tmp_10_2_4_2_reg_2365;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter45) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_916_p1 = ap_reg_pp0_iter45_tmp_10_1_2_4_reg_2200;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter21))) begin
grp_fu_916_p1 = ap_reg_pp0_iter20_tmp_10_0_1_1_reg_2025;
end else begin
grp_fu_916_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter72) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_920_p0 = temp_2_0_4_2_reg_2710;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter45) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_920_p0 = temp_2_2_2_3_reg_2585;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter21))) begin
grp_fu_920_p0 = temp_2_1_1_reg_2460;
end else begin
grp_fu_920_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter72) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_920_p1 = ap_reg_pp0_iter72_tmp_10_0_4_3_reg_2285;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter45) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_920_p1 = ap_reg_pp0_iter45_tmp_10_2_2_4_reg_2245;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter21))) begin
grp_fu_920_p1 = ap_reg_pp0_iter20_tmp_10_1_1_1_reg_2075;
end else begin
grp_fu_920_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter72) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_924_p0 = temp_2_1_4_2_reg_2715;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter48) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_924_p0 = temp_2_0_2_4_reg_2590;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter21))) begin
grp_fu_924_p0 = temp_2_2_1_reg_2465;
end else begin
grp_fu_924_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter72) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_924_p1 = ap_reg_pp0_iter72_tmp_10_1_4_3_reg_2325;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter48) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_924_p1 = ap_reg_pp0_iter48_tmp_10_0_3_reg_2160;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter21))) begin
grp_fu_924_p1 = ap_reg_pp0_iter20_tmp_10_2_1_1_reg_2120;
end else begin
grp_fu_924_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter72) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_928_p0 = temp_2_2_4_2_reg_2720;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter48) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_928_p0 = temp_2_1_2_4_reg_2595;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter24))) begin
grp_fu_928_p0 = temp_2_0_1_1_reg_2470;
end else begin
grp_fu_928_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter72) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_928_p1 = ap_reg_pp0_iter72_tmp_10_2_4_3_reg_2370;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter48) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_928_p1 = ap_reg_pp0_iter48_tmp_10_1_3_reg_2205;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter24))) begin
grp_fu_928_p1 = ap_reg_pp0_iter23_tmp_10_0_1_2_reg_2030;
end else begin
grp_fu_928_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter75) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_932_p0 = temp_2_0_4_3_reg_2725;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter48) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_932_p0 = temp_2_2_2_4_reg_2600;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter24))) begin
grp_fu_932_p0 = temp_2_1_1_1_reg_2475;
end else begin
grp_fu_932_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter75) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_932_p1 = ap_reg_pp0_iter75_tmp_10_0_4_4_reg_2290;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter48) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_932_p1 = ap_reg_pp0_iter48_tmp_10_2_3_reg_2250;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter24))) begin
grp_fu_932_p1 = ap_reg_pp0_iter23_tmp_10_1_1_2_reg_2080;
end else begin
grp_fu_932_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter75) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_936_p0 = temp_2_1_4_3_reg_2730;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter51) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_936_p0 = temp_2_0_3_reg_2605;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter24))) begin
grp_fu_936_p0 = temp_2_2_1_1_reg_2480;
end else begin
grp_fu_936_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter75) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_936_p1 = ap_reg_pp0_iter75_tmp_10_1_4_4_reg_2330;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter51) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_936_p1 = ap_reg_pp0_iter51_tmp_10_0_3_1_reg_2165;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter24))) begin
grp_fu_936_p1 = ap_reg_pp0_iter23_tmp_10_2_1_2_reg_2125;
end else begin
grp_fu_936_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter75) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_940_p0 = temp_2_2_4_3_reg_2735;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter51) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_940_p0 = temp_2_1_3_reg_2610;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter27))) begin
grp_fu_940_p0 = temp_2_0_1_2_reg_2485;
end else begin
grp_fu_940_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter75) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_940_p1 = ap_reg_pp0_iter75_tmp_10_2_4_4_reg_2375;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter51) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_940_p1 = ap_reg_pp0_iter51_tmp_10_1_3_1_reg_2210;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter27))) begin
grp_fu_940_p1 = ap_reg_pp0_iter26_tmp_10_0_1_3_reg_2035;
end else begin
grp_fu_940_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_944_p0 = bufw_3_2_load_reg_1868;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_944_p0 = bufw_1_4_load_reg_1735;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_944_p0 = bufw_0_0_load_reg_1512;
end else begin
grp_fu_944_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_944_p1 = bufi_2_load_3_reg_1801;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_944_p1 = bufi_4_load_1_reg_1599;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_944_p1 = bufi_0_load_reg_1354;
end else begin
grp_fu_944_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_948_p0 = bufw_3_3_load_reg_1875;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_948_p0 = bufw_2_0_load_reg_1742;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_948_p0 = bufw_0_1_load_reg_1519;
end else begin
grp_fu_948_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_948_p1 = bufi_3_load_3_reg_1808;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_948_p1 = bufi_0_load_2_reg_1606;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_948_p1 = bufi_1_load_reg_1359;
end else begin
grp_fu_948_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_952_p0 = bufw_3_4_load_reg_1882;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_952_p0 = bufw_2_1_load_reg_1749;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_952_p0 = bufw_0_2_load_reg_1526;
end else begin
grp_fu_952_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_952_p1 = bufi_4_load_3_reg_1815;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_952_p1 = bufi_1_load_2_reg_1611;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_952_p1 = bufi_2_load_reg_1365;
end else begin
grp_fu_952_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_956_p0 = bufw_4_0_load_reg_1889;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_956_p0 = bufw_2_2_load_reg_1756;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_956_p0 = bufw_0_3_load_reg_1533;
end else begin
grp_fu_956_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_956_p1 = bufi_0_load_4_reg_1896;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_956_p1 = bufi_2_load_2_reg_1617;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_956_p1 = bufi_3_load_reg_1372;
end else begin
grp_fu_956_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_960_p0 = bufw_4_1_load_reg_1901;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_960_p0 = bufw_2_3_load_reg_1763;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_960_p0 = bufw_0_4_load_reg_1540;
end else begin
grp_fu_960_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_960_p1 = bufi_1_load_4_reg_1908;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_960_p1 = bufi_3_load_2_reg_1624;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_960_p1 = bufi_4_load_reg_1379;
end else begin
grp_fu_960_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_964_p0 = bufw_4_2_load_reg_1914;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_964_p0 = bufw_2_4_load_reg_1770;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_964_p0 = bufw_1_0_load_reg_1547;
end else begin
grp_fu_964_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_964_p1 = bufi_2_load_4_reg_1921;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_964_p1 = bufi_4_load_2_reg_1631;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_964_p1 = bufi_0_load_1_reg_1554;
end else begin
grp_fu_964_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_968_p0 = bufw_4_3_load_reg_1928;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_968_p0 = bufw_3_0_load_reg_1777;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_968_p0 = bufw_1_1_load_reg_1559;
end else begin
grp_fu_968_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_968_p1 = bufi_3_load_4_reg_1935;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_968_p1 = bufi_0_load_3_reg_1784;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_968_p1 = bufi_1_load_1_reg_1566;
end else begin
grp_fu_968_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_972_p0 = bufw_4_4_load_reg_1942;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_972_p0 = bufw_3_1_load_reg_1789;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_972_p0 = bufw_1_2_load_reg_1572;
end else begin
grp_fu_972_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_972_p1 = bufi_4_load_4_reg_1949;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_972_p1 = bufi_1_load_3_reg_1795;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_972_p1 = bufi_2_load_1_reg_1579;
end else begin
grp_fu_972_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_976_p0 = bufw_3_2_load_reg_1868;
end else if ((((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0)))) begin
grp_fu_976_p0 = bufw_1_3_load_reg_1586;
end else begin
grp_fu_976_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_976_p1 = bufi_3_load_3_reg_1808;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_976_p1 = bufi_4_load_1_reg_1599;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_976_p1 = bufi_3_load_1_reg_1592;
end else begin
grp_fu_976_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_980_p0 = bufw_3_3_load_reg_1875;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_980_p0 = bufw_1_4_load_reg_1735;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_980_p0 = bufw_0_0_load_reg_1512;
end else begin
grp_fu_980_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_980_p1 = bufi_4_load_3_reg_1815;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_980_p1 = bufi_5_load_1_reg_1673;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_980_p1 = bufi_1_load_reg_1359;
end else begin
grp_fu_980_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_984_p0 = bufw_3_4_load_reg_1882;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_984_p0 = bufw_2_0_load_reg_1742;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_984_p0 = bufw_0_1_load_reg_1519;
end else begin
grp_fu_984_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_984_p1 = bufi_5_load_3_reg_1857;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_984_p1 = bufi_1_load_2_reg_1611;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_984_p1 = bufi_2_load_reg_1365;
end else begin
grp_fu_984_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_988_p0 = bufw_4_0_load_reg_1889;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_988_p0 = bufw_2_1_load_reg_1749;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_988_p0 = bufw_0_2_load_reg_1526;
end else begin
grp_fu_988_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_988_p1 = bufi_1_load_4_reg_1908;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_988_p1 = bufi_2_load_2_reg_1617;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_988_p1 = bufi_3_load_reg_1372;
end else begin
grp_fu_988_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_992_p0 = bufw_4_1_load_reg_1901;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_992_p0 = bufw_2_2_load_reg_1756;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_992_p0 = bufw_0_3_load_reg_1533;
end else begin
grp_fu_992_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_992_p1 = bufi_2_load_4_reg_1921;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_992_p1 = bufi_3_load_2_reg_1624;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_992_p1 = bufi_4_load_reg_1379;
end else begin
grp_fu_992_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_996_p0 = bufw_4_2_load_reg_1914;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_996_p0 = bufw_2_3_load_reg_1763;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_996_p0 = bufw_0_4_load_reg_1540;
end else begin
grp_fu_996_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_996_p1 = bufi_3_load_4_reg_1935;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_996_p1 = bufi_4_load_2_reg_1631;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_996_p1 = bufi_5_load_reg_1461;
end else begin
grp_fu_996_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
indvar_flatten_phi_fu_814_p4 = indvar_flatten_next_reg_1206;
end else begin
indvar_flatten_phi_fu_814_p4 = indvar_flatten_reg_810;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
p_1_phi_fu_837_p4 = row_b_V_reg_1278;
end else begin
p_1_phi_fu_837_p4 = p_1_reg_833;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_flatten_reg_1202 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
p_s_phi_fu_825_p4 = tmp_mid2_v_reg_1230;
end else begin
p_s_phi_fu_825_p4 = p_s_reg_821;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_pp0_stage0 : begin
if (((ap_block_pp0_stage0_flag00011011 == 1'b0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (exitcond_flatten_fu_1044_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (exitcond_flatten_fu_1044_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin
ap_NS_fsm = ap_ST_fsm_state239;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage1 : begin
if ((ap_block_pp0_stage1_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end
end
ap_ST_fsm_pp0_stage2 : begin
if (((ap_block_pp0_stage2_flag00011011 == 1'b0) & ~((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter78) & (ap_block_pp0_stage2_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter77 == 1'b0)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter78) & (ap_block_pp0_stage2_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter77 == 1'b0))) begin
ap_NS_fsm = ap_ST_fsm_state239;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end
end
ap_ST_fsm_state239 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state239 = ap_CS_fsm[32'd4];
assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_state100_pp0_stage2_iter32 = ~(1'b1 == 1'b1);
assign ap_block_state101_pp0_stage0_iter33 = ~(1'b1 == 1'b1);
assign ap_block_state102_pp0_stage1_iter33 = ~(1'b1 == 1'b1);
assign ap_block_state103_pp0_stage2_iter33 = ~(1'b1 == 1'b1);
assign ap_block_state104_pp0_stage0_iter34 = ~(1'b1 == 1'b1);
assign ap_block_state105_pp0_stage1_iter34 = ~(1'b1 == 1'b1);
assign ap_block_state106_pp0_stage2_iter34 = ~(1'b1 == 1'b1);
assign ap_block_state107_pp0_stage0_iter35 = ~(1'b1 == 1'b1);
assign ap_block_state108_pp0_stage1_iter35 = ~(1'b1 == 1'b1);
assign ap_block_state109_pp0_stage2_iter35 = ~(1'b1 == 1'b1);
assign ap_block_state10_pp0_stage2_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state110_pp0_stage0_iter36 = ~(1'b1 == 1'b1);
assign ap_block_state111_pp0_stage1_iter36 = ~(1'b1 == 1'b1);
assign ap_block_state112_pp0_stage2_iter36 = ~(1'b1 == 1'b1);
assign ap_block_state113_pp0_stage0_iter37 = ~(1'b1 == 1'b1);
assign ap_block_state114_pp0_stage1_iter37 = ~(1'b1 == 1'b1);
assign ap_block_state115_pp0_stage2_iter37 = ~(1'b1 == 1'b1);
assign ap_block_state116_pp0_stage0_iter38 = ~(1'b1 == 1'b1);
assign ap_block_state117_pp0_stage1_iter38 = ~(1'b1 == 1'b1);
assign ap_block_state118_pp0_stage2_iter38 = ~(1'b1 == 1'b1);
assign ap_block_state119_pp0_stage0_iter39 = ~(1'b1 == 1'b1);
assign ap_block_state11_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state120_pp0_stage1_iter39 = ~(1'b1 == 1'b1);
assign ap_block_state121_pp0_stage2_iter39 = ~(1'b1 == 1'b1);
assign ap_block_state122_pp0_stage0_iter40 = ~(1'b1 == 1'b1);
assign ap_block_state123_pp0_stage1_iter40 = ~(1'b1 == 1'b1);
assign ap_block_state124_pp0_stage2_iter40 = ~(1'b1 == 1'b1);
assign ap_block_state125_pp0_stage0_iter41 = ~(1'b1 == 1'b1);
assign ap_block_state126_pp0_stage1_iter41 = ~(1'b1 == 1'b1);
assign ap_block_state127_pp0_stage2_iter41 = ~(1'b1 == 1'b1);
assign ap_block_state128_pp0_stage0_iter42 = ~(1'b1 == 1'b1);
assign ap_block_state129_pp0_stage1_iter42 = ~(1'b1 == 1'b1);
assign ap_block_state12_pp0_stage1_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state130_pp0_stage2_iter42 = ~(1'b1 == 1'b1);
assign ap_block_state131_pp0_stage0_iter43 = ~(1'b1 == 1'b1);
assign ap_block_state132_pp0_stage1_iter43 = ~(1'b1 == 1'b1);
assign ap_block_state133_pp0_stage2_iter43 = ~(1'b1 == 1'b1);
assign ap_block_state134_pp0_stage0_iter44 = ~(1'b1 == 1'b1);
assign ap_block_state135_pp0_stage1_iter44 = ~(1'b1 == 1'b1);
assign ap_block_state136_pp0_stage2_iter44 = ~(1'b1 == 1'b1);
assign ap_block_state137_pp0_stage0_iter45 = ~(1'b1 == 1'b1);
assign ap_block_state138_pp0_stage1_iter45 = ~(1'b1 == 1'b1);
assign ap_block_state139_pp0_stage2_iter45 = ~(1'b1 == 1'b1);
assign ap_block_state13_pp0_stage2_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state140_pp0_stage0_iter46 = ~(1'b1 == 1'b1);
assign ap_block_state141_pp0_stage1_iter46 = ~(1'b1 == 1'b1);
assign ap_block_state142_pp0_stage2_iter46 = ~(1'b1 == 1'b1);
assign ap_block_state143_pp0_stage0_iter47 = ~(1'b1 == 1'b1);
assign ap_block_state144_pp0_stage1_iter47 = ~(1'b1 == 1'b1);
assign ap_block_state145_pp0_stage2_iter47 = ~(1'b1 == 1'b1);
assign ap_block_state146_pp0_stage0_iter48 = ~(1'b1 == 1'b1);
assign ap_block_state147_pp0_stage1_iter48 = ~(1'b1 == 1'b1);
assign ap_block_state148_pp0_stage2_iter48 = ~(1'b1 == 1'b1);
assign ap_block_state149_pp0_stage0_iter49 = ~(1'b1 == 1'b1);
assign ap_block_state14_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state150_pp0_stage1_iter49 = ~(1'b1 == 1'b1);
assign ap_block_state151_pp0_stage2_iter49 = ~(1'b1 == 1'b1);
assign ap_block_state152_pp0_stage0_iter50 = ~(1'b1 == 1'b1);
assign ap_block_state153_pp0_stage1_iter50 = ~(1'b1 == 1'b1);
assign ap_block_state154_pp0_stage2_iter50 = ~(1'b1 == 1'b1);
assign ap_block_state155_pp0_stage0_iter51 = ~(1'b1 == 1'b1);
assign ap_block_state156_pp0_stage1_iter51 = ~(1'b1 == 1'b1);
assign ap_block_state157_pp0_stage2_iter51 = ~(1'b1 == 1'b1);
assign ap_block_state158_pp0_stage0_iter52 = ~(1'b1 == 1'b1);
assign ap_block_state159_pp0_stage1_iter52 = ~(1'b1 == 1'b1);
assign ap_block_state15_pp0_stage1_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state160_pp0_stage2_iter52 = ~(1'b1 == 1'b1);
assign ap_block_state161_pp0_stage0_iter53 = ~(1'b1 == 1'b1);
assign ap_block_state162_pp0_stage1_iter53 = ~(1'b1 == 1'b1);
assign ap_block_state163_pp0_stage2_iter53 = ~(1'b1 == 1'b1);
assign ap_block_state164_pp0_stage0_iter54 = ~(1'b1 == 1'b1);
assign ap_block_state165_pp0_stage1_iter54 = ~(1'b1 == 1'b1);
assign ap_block_state166_pp0_stage2_iter54 = ~(1'b1 == 1'b1);
assign ap_block_state167_pp0_stage0_iter55 = ~(1'b1 == 1'b1);
assign ap_block_state168_pp0_stage1_iter55 = ~(1'b1 == 1'b1);
assign ap_block_state169_pp0_stage2_iter55 = ~(1'b1 == 1'b1);
assign ap_block_state16_pp0_stage2_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state170_pp0_stage0_iter56 = ~(1'b1 == 1'b1);
assign ap_block_state171_pp0_stage1_iter56 = ~(1'b1 == 1'b1);
assign ap_block_state172_pp0_stage2_iter56 = ~(1'b1 == 1'b1);
assign ap_block_state173_pp0_stage0_iter57 = ~(1'b1 == 1'b1);
assign ap_block_state174_pp0_stage1_iter57 = ~(1'b1 == 1'b1);
assign ap_block_state175_pp0_stage2_iter57 = ~(1'b1 == 1'b1);
assign ap_block_state176_pp0_stage0_iter58 = ~(1'b1 == 1'b1);
assign ap_block_state177_pp0_stage1_iter58 = ~(1'b1 == 1'b1);
assign ap_block_state178_pp0_stage2_iter58 = ~(1'b1 == 1'b1);
assign ap_block_state179_pp0_stage0_iter59 = ~(1'b1 == 1'b1);
assign ap_block_state17_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state180_pp0_stage1_iter59 = ~(1'b1 == 1'b1);
assign ap_block_state181_pp0_stage2_iter59 = ~(1'b1 == 1'b1);
assign ap_block_state182_pp0_stage0_iter60 = ~(1'b1 == 1'b1);
assign ap_block_state183_pp0_stage1_iter60 = ~(1'b1 == 1'b1);
assign ap_block_state184_pp0_stage2_iter60 = ~(1'b1 == 1'b1);
assign ap_block_state185_pp0_stage0_iter61 = ~(1'b1 == 1'b1);
assign ap_block_state186_pp0_stage1_iter61 = ~(1'b1 == 1'b1);
assign ap_block_state187_pp0_stage2_iter61 = ~(1'b1 == 1'b1);
assign ap_block_state188_pp0_stage0_iter62 = ~(1'b1 == 1'b1);
assign ap_block_state189_pp0_stage1_iter62 = ~(1'b1 == 1'b1);
assign ap_block_state18_pp0_stage1_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state190_pp0_stage2_iter62 = ~(1'b1 == 1'b1);
assign ap_block_state191_pp0_stage0_iter63 = ~(1'b1 == 1'b1);
assign ap_block_state192_pp0_stage1_iter63 = ~(1'b1 == 1'b1);
assign ap_block_state193_pp0_stage2_iter63 = ~(1'b1 == 1'b1);
assign ap_block_state194_pp0_stage0_iter64 = ~(1'b1 == 1'b1);
assign ap_block_state195_pp0_stage1_iter64 = ~(1'b1 == 1'b1);
assign ap_block_state196_pp0_stage2_iter64 = ~(1'b1 == 1'b1);
assign ap_block_state197_pp0_stage0_iter65 = ~(1'b1 == 1'b1);
assign ap_block_state198_pp0_stage1_iter65 = ~(1'b1 == 1'b1);
assign ap_block_state199_pp0_stage2_iter65 = ~(1'b1 == 1'b1);
assign ap_block_state19_pp0_stage2_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state200_pp0_stage0_iter66 = ~(1'b1 == 1'b1);
assign ap_block_state201_pp0_stage1_iter66 = ~(1'b1 == 1'b1);
assign ap_block_state202_pp0_stage2_iter66 = ~(1'b1 == 1'b1);
assign ap_block_state203_pp0_stage0_iter67 = ~(1'b1 == 1'b1);
assign ap_block_state204_pp0_stage1_iter67 = ~(1'b1 == 1'b1);
assign ap_block_state205_pp0_stage2_iter67 = ~(1'b1 == 1'b1);
assign ap_block_state206_pp0_stage0_iter68 = ~(1'b1 == 1'b1);
assign ap_block_state207_pp0_stage1_iter68 = ~(1'b1 == 1'b1);
assign ap_block_state208_pp0_stage2_iter68 = ~(1'b1 == 1'b1);
assign ap_block_state209_pp0_stage0_iter69 = ~(1'b1 == 1'b1);
assign ap_block_state20_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state210_pp0_stage1_iter69 = ~(1'b1 == 1'b1);
assign ap_block_state211_pp0_stage2_iter69 = ~(1'b1 == 1'b1);
assign ap_block_state212_pp0_stage0_iter70 = ~(1'b1 == 1'b1);
assign ap_block_state213_pp0_stage1_iter70 = ~(1'b1 == 1'b1);
assign ap_block_state214_pp0_stage2_iter70 = ~(1'b1 == 1'b1);
assign ap_block_state215_pp0_stage0_iter71 = ~(1'b1 == 1'b1);
assign ap_block_state216_pp0_stage1_iter71 = ~(1'b1 == 1'b1);
assign ap_block_state217_pp0_stage2_iter71 = ~(1'b1 == 1'b1);
assign ap_block_state218_pp0_stage0_iter72 = ~(1'b1 == 1'b1);
assign ap_block_state219_pp0_stage1_iter72 = ~(1'b1 == 1'b1);
assign ap_block_state21_pp0_stage1_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state220_pp0_stage2_iter72 = ~(1'b1 == 1'b1);
assign ap_block_state221_pp0_stage0_iter73 = ~(1'b1 == 1'b1);
assign ap_block_state222_pp0_stage1_iter73 = ~(1'b1 == 1'b1);
assign ap_block_state223_pp0_stage2_iter73 = ~(1'b1 == 1'b1);
assign ap_block_state224_pp0_stage0_iter74 = ~(1'b1 == 1'b1);
assign ap_block_state225_pp0_stage1_iter74 = ~(1'b1 == 1'b1);
assign ap_block_state226_pp0_stage2_iter74 = ~(1'b1 == 1'b1);
assign ap_block_state227_pp0_stage0_iter75 = ~(1'b1 == 1'b1);
assign ap_block_state228_pp0_stage1_iter75 = ~(1'b1 == 1'b1);
assign ap_block_state229_pp0_stage2_iter75 = ~(1'b1 == 1'b1);
assign ap_block_state22_pp0_stage2_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state230_pp0_stage0_iter76 = ~(1'b1 == 1'b1);
assign ap_block_state231_pp0_stage1_iter76 = ~(1'b1 == 1'b1);
assign ap_block_state232_pp0_stage2_iter76 = ~(1'b1 == 1'b1);
assign ap_block_state233_pp0_stage0_iter77 = ~(1'b1 == 1'b1);
assign ap_block_state234_pp0_stage1_iter77 = ~(1'b1 == 1'b1);
assign ap_block_state235_pp0_stage2_iter77 = ~(1'b1 == 1'b1);
assign ap_block_state236_pp0_stage0_iter78 = ~(1'b1 == 1'b1);
assign ap_block_state237_pp0_stage1_iter78 = ~(1'b1 == 1'b1);
assign ap_block_state238_pp0_stage2_iter78 = ~(1'b1 == 1'b1);
assign ap_block_state23_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state24_pp0_stage1_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state25_pp0_stage2_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state26_pp0_stage0_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state27_pp0_stage1_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state28_pp0_stage2_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state29_pp0_stage0_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state30_pp0_stage1_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state31_pp0_stage2_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state32_pp0_stage0_iter10 = ~(1'b1 == 1'b1);
assign ap_block_state33_pp0_stage1_iter10 = ~(1'b1 == 1'b1);
assign ap_block_state34_pp0_stage2_iter10 = ~(1'b1 == 1'b1);
assign ap_block_state35_pp0_stage0_iter11 = ~(1'b1 == 1'b1);
assign ap_block_state36_pp0_stage1_iter11 = ~(1'b1 == 1'b1);
assign ap_block_state37_pp0_stage2_iter11 = ~(1'b1 == 1'b1);
assign ap_block_state38_pp0_stage0_iter12 = ~(1'b1 == 1'b1);
assign ap_block_state39_pp0_stage1_iter12 = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state40_pp0_stage2_iter12 = ~(1'b1 == 1'b1);
assign ap_block_state41_pp0_stage0_iter13 = ~(1'b1 == 1'b1);
assign ap_block_state42_pp0_stage1_iter13 = ~(1'b1 == 1'b1);
assign ap_block_state43_pp0_stage2_iter13 = ~(1'b1 == 1'b1);
assign ap_block_state44_pp0_stage0_iter14 = ~(1'b1 == 1'b1);
assign ap_block_state45_pp0_stage1_iter14 = ~(1'b1 == 1'b1);
assign ap_block_state46_pp0_stage2_iter14 = ~(1'b1 == 1'b1);
assign ap_block_state47_pp0_stage0_iter15 = ~(1'b1 == 1'b1);
assign ap_block_state48_pp0_stage1_iter15 = ~(1'b1 == 1'b1);
assign ap_block_state49_pp0_stage2_iter15 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state50_pp0_stage0_iter16 = ~(1'b1 == 1'b1);
assign ap_block_state51_pp0_stage1_iter16 = ~(1'b1 == 1'b1);
assign ap_block_state52_pp0_stage2_iter16 = ~(1'b1 == 1'b1);
assign ap_block_state53_pp0_stage0_iter17 = ~(1'b1 == 1'b1);
assign ap_block_state54_pp0_stage1_iter17 = ~(1'b1 == 1'b1);
assign ap_block_state55_pp0_stage2_iter17 = ~(1'b1 == 1'b1);
assign ap_block_state56_pp0_stage0_iter18 = ~(1'b1 == 1'b1);
assign ap_block_state57_pp0_stage1_iter18 = ~(1'b1 == 1'b1);
assign ap_block_state58_pp0_stage2_iter18 = ~(1'b1 == 1'b1);
assign ap_block_state59_pp0_stage0_iter19 = ~(1'b1 == 1'b1);
assign ap_block_state5_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state60_pp0_stage1_iter19 = ~(1'b1 == 1'b1);
assign ap_block_state61_pp0_stage2_iter19 = ~(1'b1 == 1'b1);
assign ap_block_state62_pp0_stage0_iter20 = ~(1'b1 == 1'b1);
assign ap_block_state63_pp0_stage1_iter20 = ~(1'b1 == 1'b1);
assign ap_block_state64_pp0_stage2_iter20 = ~(1'b1 == 1'b1);
assign ap_block_state65_pp0_stage0_iter21 = ~(1'b1 == 1'b1);
assign ap_block_state66_pp0_stage1_iter21 = ~(1'b1 == 1'b1);
assign ap_block_state67_pp0_stage2_iter21 = ~(1'b1 == 1'b1);
assign ap_block_state68_pp0_stage0_iter22 = ~(1'b1 == 1'b1);
assign ap_block_state69_pp0_stage1_iter22 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage1_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state70_pp0_stage2_iter22 = ~(1'b1 == 1'b1);
assign ap_block_state71_pp0_stage0_iter23 = ~(1'b1 == 1'b1);
assign ap_block_state72_pp0_stage1_iter23 = ~(1'b1 == 1'b1);
assign ap_block_state73_pp0_stage2_iter23 = ~(1'b1 == 1'b1);
assign ap_block_state74_pp0_stage0_iter24 = ~(1'b1 == 1'b1);
assign ap_block_state75_pp0_stage1_iter24 = ~(1'b1 == 1'b1);
assign ap_block_state76_pp0_stage2_iter24 = ~(1'b1 == 1'b1);
assign ap_block_state77_pp0_stage0_iter25 = ~(1'b1 == 1'b1);
assign ap_block_state78_pp0_stage1_iter25 = ~(1'b1 == 1'b1);
assign ap_block_state79_pp0_stage2_iter25 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage2_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state80_pp0_stage0_iter26 = ~(1'b1 == 1'b1);
assign ap_block_state81_pp0_stage1_iter26 = ~(1'b1 == 1'b1);
assign ap_block_state82_pp0_stage2_iter26 = ~(1'b1 == 1'b1);
assign ap_block_state83_pp0_stage0_iter27 = ~(1'b1 == 1'b1);
assign ap_block_state84_pp0_stage1_iter27 = ~(1'b1 == 1'b1);
assign ap_block_state85_pp0_stage2_iter27 = ~(1'b1 == 1'b1);
assign ap_block_state86_pp0_stage0_iter28 = ~(1'b1 == 1'b1);
assign ap_block_state87_pp0_stage1_iter28 = ~(1'b1 == 1'b1);
assign ap_block_state88_pp0_stage2_iter28 = ~(1'b1 == 1'b1);
assign ap_block_state89_pp0_stage0_iter29 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state90_pp0_stage1_iter29 = ~(1'b1 == 1'b1);
assign ap_block_state91_pp0_stage2_iter29 = ~(1'b1 == 1'b1);
assign ap_block_state92_pp0_stage0_iter30 = ~(1'b1 == 1'b1);
assign ap_block_state93_pp0_stage1_iter30 = ~(1'b1 == 1'b1);
assign ap_block_state94_pp0_stage2_iter30 = ~(1'b1 == 1'b1);
assign ap_block_state95_pp0_stage0_iter31 = ~(1'b1 == 1'b1);
assign ap_block_state96_pp0_stage1_iter31 = ~(1'b1 == 1'b1);
assign ap_block_state97_pp0_stage2_iter31 = ~(1'b1 == 1'b1);
assign ap_block_state98_pp0_stage0_iter32 = ~(1'b1 == 1'b1);
assign ap_block_state99_pp0_stage1_iter32 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage1_iter2 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign bufi_0_Addr_A = bufi_0_Addr_A_orig << 32'd2;
assign bufi_0_Addr_B = bufi_0_Addr_B_orig << 32'd2;
assign bufi_0_Clk_A = ap_clk;
assign bufi_0_Clk_B = ap_clk;
assign bufi_0_Din_A = 32'd0;
assign bufi_0_Din_B = 32'd0;
assign bufi_0_Rst_A = ap_rst;
assign bufi_0_Rst_B = ap_rst;
assign bufi_0_WEN_A = 4'd0;
assign bufi_0_WEN_B = 4'd0;
assign bufi_1_Addr_A = bufi_1_Addr_A_orig << 32'd2;
assign bufi_1_Addr_B = bufi_1_Addr_B_orig << 32'd2;
assign bufi_1_Clk_A = ap_clk;
assign bufi_1_Clk_B = ap_clk;
assign bufi_1_Din_A = 32'd0;
assign bufi_1_Din_B = 32'd0;
assign bufi_1_Rst_A = ap_rst;
assign bufi_1_Rst_B = ap_rst;
assign bufi_1_WEN_A = 4'd0;
assign bufi_1_WEN_B = 4'd0;
assign bufi_2_Addr_A = bufi_2_Addr_A_orig << 32'd2;
assign bufi_2_Addr_B = bufi_2_Addr_B_orig << 32'd2;
assign bufi_2_Clk_A = ap_clk;
assign bufi_2_Clk_B = ap_clk;
assign bufi_2_Din_A = 32'd0;
assign bufi_2_Din_B = 32'd0;
assign bufi_2_Rst_A = ap_rst;
assign bufi_2_Rst_B = ap_rst;
assign bufi_2_WEN_A = 4'd0;
assign bufi_2_WEN_B = 4'd0;
assign bufi_3_Addr_A = bufi_3_Addr_A_orig << 32'd2;
assign bufi_3_Addr_B = bufi_3_Addr_B_orig << 32'd2;
assign bufi_3_Clk_A = ap_clk;
assign bufi_3_Clk_B = ap_clk;
assign bufi_3_Din_A = 32'd0;
assign bufi_3_Din_B = 32'd0;
assign bufi_3_Rst_A = ap_rst;
assign bufi_3_Rst_B = ap_rst;
assign bufi_3_WEN_A = 4'd0;
assign bufi_3_WEN_B = 4'd0;
assign bufi_4_Addr_A = bufi_4_Addr_A_orig << 32'd2;
assign bufi_4_Addr_B = bufi_4_Addr_B_orig << 32'd2;
assign bufi_4_Clk_A = ap_clk;
assign bufi_4_Clk_B = ap_clk;
assign bufi_4_Din_A = 32'd0;
assign bufi_4_Din_B = 32'd0;
assign bufi_4_Rst_A = ap_rst;
assign bufi_4_Rst_B = ap_rst;
assign bufi_4_WEN_A = 4'd0;
assign bufi_4_WEN_B = 4'd0;
assign bufi_5_Addr_A = bufi_5_Addr_A_orig << 32'd2;
assign bufi_5_Addr_B = bufi_5_Addr_B_orig << 32'd2;
assign bufi_5_Clk_A = ap_clk;
assign bufi_5_Clk_B = ap_clk;
assign bufi_5_Din_A = 32'd0;
assign bufi_5_Din_B = 32'd0;
assign bufi_5_Rst_A = ap_rst;
assign bufi_5_Rst_B = ap_rst;
assign bufi_5_WEN_A = 4'd0;
assign bufi_5_WEN_B = 4'd0;
assign bufi_6_Addr_A = bufi_6_Addr_A_orig << 32'd2;
assign bufi_6_Addr_B = bufi_6_Addr_B_orig << 32'd2;
assign bufi_6_Clk_A = ap_clk;
assign bufi_6_Clk_B = ap_clk;
assign bufi_6_Din_A = 32'd0;
assign bufi_6_Din_B = 32'd0;
assign bufi_6_Rst_A = ap_rst;
assign bufi_6_Rst_B = ap_rst;
assign bufi_6_WEN_A = 4'd0;
assign bufi_6_WEN_B = 4'd0;
assign bufo_0_Addr_A = bufo_0_Addr_A_orig << 32'd2;
assign bufo_0_Addr_A_orig = tmp_4_cast_fu_1196_p1;
assign bufo_0_Addr_B = bufo_0_Addr_B_orig << 32'd2;
assign bufo_0_Addr_B_orig = ap_reg_pp0_iter78_bufo_0_addr_reg_1972;
assign bufo_0_Clk_A = ap_clk;
assign bufo_0_Clk_B = ap_clk;
assign bufo_0_Din_A = 32'd0;
assign bufo_0_Din_B = temp_2_0_4_4_reg_2740;
assign bufo_0_Rst_A = ap_rst;
assign bufo_0_Rst_B = ap_rst;
assign bufo_0_WEN_A = 4'd0;
assign bufo_1_Addr_A = bufo_1_Addr_A_orig << 32'd2;
assign bufo_1_Addr_A_orig = tmp_4_cast_fu_1196_p1;
assign bufo_1_Addr_B = bufo_1_Addr_B_orig << 32'd2;
assign bufo_1_Addr_B_orig = ap_reg_pp0_iter78_bufo_1_addr_reg_1978;
assign bufo_1_Clk_A = ap_clk;
assign bufo_1_Clk_B = ap_clk;
assign bufo_1_Din_A = 32'd0;
assign bufo_1_Din_B = temp_2_1_4_4_reg_2745;
assign bufo_1_Rst_A = ap_rst;
assign bufo_1_Rst_B = ap_rst;
assign bufo_1_WEN_A = 4'd0;
assign bufo_2_Addr_A = bufo_2_Addr_A_orig << 32'd2;
assign bufo_2_Addr_A_orig = tmp_4_cast_fu_1196_p1;
assign bufo_2_Addr_B = bufo_2_Addr_B_orig << 32'd2;
assign bufo_2_Addr_B_orig = ap_reg_pp0_iter78_bufo_2_addr_reg_1984;
assign bufo_2_Clk_A = ap_clk;
assign bufo_2_Clk_B = ap_clk;
assign bufo_2_Din_A = 32'd0;
assign bufo_2_Din_B = temp_2_2_4_4_reg_2750;
assign bufo_2_Rst_A = ap_rst;
assign bufo_2_Rst_B = ap_rst;
assign bufo_2_WEN_A = 4'd0;
assign bufw_0_0_Addr_A = bufw_0_0_Addr_A_orig << 32'd2;
assign bufw_0_0_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_0_0_Clk_A = ap_clk;
assign bufw_0_0_Din_A = 32'd0;
assign bufw_0_0_Rst_A = ap_rst;
assign bufw_0_0_WEN_A = 4'd0;
assign bufw_0_1_Addr_A = bufw_0_1_Addr_A_orig << 32'd2;
assign bufw_0_1_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_0_1_Clk_A = ap_clk;
assign bufw_0_1_Din_A = 32'd0;
assign bufw_0_1_Rst_A = ap_rst;
assign bufw_0_1_WEN_A = 4'd0;
assign bufw_0_2_Addr_A = bufw_0_2_Addr_A_orig << 32'd2;
assign bufw_0_2_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_0_2_Clk_A = ap_clk;
assign bufw_0_2_Din_A = 32'd0;
assign bufw_0_2_Rst_A = ap_rst;
assign bufw_0_2_WEN_A = 4'd0;
assign bufw_0_3_Addr_A = bufw_0_3_Addr_A_orig << 32'd2;
assign bufw_0_3_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_0_3_Clk_A = ap_clk;
assign bufw_0_3_Din_A = 32'd0;
assign bufw_0_3_Rst_A = ap_rst;
assign bufw_0_3_WEN_A = 4'd0;
assign bufw_0_4_Addr_A = bufw_0_4_Addr_A_orig << 32'd2;
assign bufw_0_4_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_0_4_Clk_A = ap_clk;
assign bufw_0_4_Din_A = 32'd0;
assign bufw_0_4_Rst_A = ap_rst;
assign bufw_0_4_WEN_A = 4'd0;
assign bufw_1_0_Addr_A = bufw_1_0_Addr_A_orig << 32'd2;
assign bufw_1_0_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_1_0_Clk_A = ap_clk;
assign bufw_1_0_Din_A = 32'd0;
assign bufw_1_0_Rst_A = ap_rst;
assign bufw_1_0_WEN_A = 4'd0;
assign bufw_1_1_Addr_A = bufw_1_1_Addr_A_orig << 32'd2;
assign bufw_1_1_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_1_1_Clk_A = ap_clk;
assign bufw_1_1_Din_A = 32'd0;
assign bufw_1_1_Rst_A = ap_rst;
assign bufw_1_1_WEN_A = 4'd0;
assign bufw_1_2_Addr_A = bufw_1_2_Addr_A_orig << 32'd2;
assign bufw_1_2_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_1_2_Clk_A = ap_clk;
assign bufw_1_2_Din_A = 32'd0;
assign bufw_1_2_Rst_A = ap_rst;
assign bufw_1_2_WEN_A = 4'd0;
assign bufw_1_3_Addr_A = bufw_1_3_Addr_A_orig << 32'd2;
assign bufw_1_3_Addr_A_orig = tmp_mid2_fu_1106_p1;
assign bufw_1_3_Clk_A = ap_clk;
assign bufw_1_3_Din_A = 32'd0;
assign bufw_1_3_Rst_A = ap_rst;
assign bufw_1_3_WEN_A = 4'd0;
assign bufw_1_4_Addr_A = bufw_1_4_Addr_A_orig << 32'd2;
assign bufw_1_4_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_1_4_Clk_A = ap_clk;
assign bufw_1_4_Din_A = 32'd0;
assign bufw_1_4_Rst_A = ap_rst;
assign bufw_1_4_WEN_A = 4'd0;
assign bufw_2_0_Addr_A = bufw_2_0_Addr_A_orig << 32'd2;
assign bufw_2_0_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_2_0_Clk_A = ap_clk;
assign bufw_2_0_Din_A = 32'd0;
assign bufw_2_0_Rst_A = ap_rst;
assign bufw_2_0_WEN_A = 4'd0;
assign bufw_2_1_Addr_A = bufw_2_1_Addr_A_orig << 32'd2;
assign bufw_2_1_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_2_1_Clk_A = ap_clk;
assign bufw_2_1_Din_A = 32'd0;
assign bufw_2_1_Rst_A = ap_rst;
assign bufw_2_1_WEN_A = 4'd0;
assign bufw_2_2_Addr_A = bufw_2_2_Addr_A_orig << 32'd2;
assign bufw_2_2_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_2_2_Clk_A = ap_clk;
assign bufw_2_2_Din_A = 32'd0;
assign bufw_2_2_Rst_A = ap_rst;
assign bufw_2_2_WEN_A = 4'd0;
assign bufw_2_3_Addr_A = bufw_2_3_Addr_A_orig << 32'd2;
assign bufw_2_3_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_2_3_Clk_A = ap_clk;
assign bufw_2_3_Din_A = 32'd0;
assign bufw_2_3_Rst_A = ap_rst;
assign bufw_2_3_WEN_A = 4'd0;
assign bufw_2_4_Addr_A = bufw_2_4_Addr_A_orig << 32'd2;
assign bufw_2_4_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_2_4_Clk_A = ap_clk;
assign bufw_2_4_Din_A = 32'd0;
assign bufw_2_4_Rst_A = ap_rst;
assign bufw_2_4_WEN_A = 4'd0;
assign bufw_3_0_Addr_A = bufw_3_0_Addr_A_orig << 32'd2;
assign bufw_3_0_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_3_0_Clk_A = ap_clk;
assign bufw_3_0_Din_A = 32'd0;
assign bufw_3_0_Rst_A = ap_rst;
assign bufw_3_0_WEN_A = 4'd0;
assign bufw_3_1_Addr_A = bufw_3_1_Addr_A_orig << 32'd2;
assign bufw_3_1_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_3_1_Clk_A = ap_clk;
assign bufw_3_1_Din_A = 32'd0;
assign bufw_3_1_Rst_A = ap_rst;
assign bufw_3_1_WEN_A = 4'd0;
assign bufw_3_2_Addr_A = bufw_3_2_Addr_A_orig << 32'd2;
assign bufw_3_2_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_3_2_Clk_A = ap_clk;
assign bufw_3_2_Din_A = 32'd0;
assign bufw_3_2_Rst_A = ap_rst;
assign bufw_3_2_WEN_A = 4'd0;
assign bufw_3_3_Addr_A = bufw_3_3_Addr_A_orig << 32'd2;
assign bufw_3_3_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_3_3_Clk_A = ap_clk;
assign bufw_3_3_Din_A = 32'd0;
assign bufw_3_3_Rst_A = ap_rst;
assign bufw_3_3_WEN_A = 4'd0;
assign bufw_3_4_Addr_A = bufw_3_4_Addr_A_orig << 32'd2;
assign bufw_3_4_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_3_4_Clk_A = ap_clk;
assign bufw_3_4_Din_A = 32'd0;
assign bufw_3_4_Rst_A = ap_rst;
assign bufw_3_4_WEN_A = 4'd0;
assign bufw_4_0_Addr_A = bufw_4_0_Addr_A_orig << 32'd2;
assign bufw_4_0_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_4_0_Clk_A = ap_clk;
assign bufw_4_0_Din_A = 32'd0;
assign bufw_4_0_Rst_A = ap_rst;
assign bufw_4_0_WEN_A = 4'd0;
assign bufw_4_1_Addr_A = bufw_4_1_Addr_A_orig << 32'd2;
assign bufw_4_1_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_4_1_Clk_A = ap_clk;
assign bufw_4_1_Din_A = 32'd0;
assign bufw_4_1_Rst_A = ap_rst;
assign bufw_4_1_WEN_A = 4'd0;
assign bufw_4_2_Addr_A = bufw_4_2_Addr_A_orig << 32'd2;
assign bufw_4_2_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_4_2_Clk_A = ap_clk;
assign bufw_4_2_Din_A = 32'd0;
assign bufw_4_2_Rst_A = ap_rst;
assign bufw_4_2_WEN_A = 4'd0;
assign bufw_4_3_Addr_A = bufw_4_3_Addr_A_orig << 32'd2;
assign bufw_4_3_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_4_3_Clk_A = ap_clk;
assign bufw_4_3_Din_A = 32'd0;
assign bufw_4_3_Rst_A = ap_rst;
assign bufw_4_3_WEN_A = 4'd0;
assign bufw_4_4_Addr_A = bufw_4_4_Addr_A_orig << 32'd2;
assign bufw_4_4_Addr_A_orig = tmp_mid2_reg_1289;
assign bufw_4_4_Clk_A = ap_clk;
assign bufw_4_4_Din_A = 32'd0;
assign bufw_4_4_Rst_A = ap_rst;
assign bufw_4_4_WEN_A = 4'd0;
assign exitcond_flatten_fu_1044_p2 = ((indvar_flatten_phi_fu_814_p4 == 8'd192) ? 1'b1 : 1'b0);
assign indvar_flatten_next_fu_1050_p2 = (indvar_flatten_phi_fu_814_p4 + 8'd1);
assign lhs_V_cast1_fu_1092_p1 = p_1_mid2_reg_1221;
assign p_1_mid2_fu_1068_p3 = ((tmp_1_fu_1062_p2[0:0] === 1'b1) ? 2'd0 : p_1_phi_fu_837_p4);
assign r_V_1_0_2_fu_1100_p2 = (lhs_V_cast1_fu_1092_p1 + 3'd2);
assign r_V_1_0_3_fu_1138_p2 = (lhs_V_cast1_reg_1273 + 3'd3);
assign r_V_1_0_s_fu_1153_p3 = {{1'd1}, {ap_reg_pp0_iter1_p_1_mid2_reg_1221}};
assign row_b_V_fu_1095_p2 = (p_1_mid2_reg_1221 + 2'd1);
assign tmp_1_fu_1062_p2 = ((p_1_phi_fu_837_p4 == 2'd3) ? 1'b1 : 1'b0);
assign tmp_2_0_1_fu_1118_p1 = row_b_V_reg_1278;
assign tmp_2_0_2_fu_1128_p1 = r_V_1_0_2_reg_1284;
assign tmp_2_0_3_fu_1143_p1 = r_V_1_0_3_reg_1456;
assign tmp_2_0_4_fu_1160_p1 = r_V_1_0_s_fu_1153_p3;
assign tmp_2_fu_1181_p2 = (tmp_fu_1174_p3 - tmp_mid2_cast_fu_1171_p1);
assign tmp_3_cast_fu_1187_p1 = ap_reg_pp0_iter1_p_1_mid2_reg_1221;
assign tmp_3_fu_1082_p1 = p_1_mid2_reg_1221;
assign tmp_4_cast_fu_1196_p1 = $signed(tmp_4_reg_1967);
assign tmp_4_fu_1190_p2 = (tmp_2_fu_1181_p2 + tmp_3_cast_fu_1187_p1);
assign tmp_fu_1174_p3 = {{ap_reg_pp0_iter1_tmp_mid2_v_reg_1230}, {2'd0}};
assign tmp_mid2_cast_fu_1171_p1 = ap_reg_pp0_iter1_tmp_mid2_v_reg_1230;
assign tmp_mid2_fu_1106_p1 = tmp_mid2_v_reg_1230;
assign tmp_mid2_v_fu_1076_p3 = ((tmp_1_reg_1216[0:0] === 1'b1) ? to_b_V_reg_1211 : p_s_reg_821);
assign to_b_V_fu_1056_p2 = (p_s_phi_fu_825_p4 + 7'd1);
always @ (posedge ap_clk) begin
lhs_V_cast1_reg_1273[2] <= 1'b0;
tmp_mid2_reg_1289[63:7] <= 57'b000000000000000000000000000000000000000000000000000000000;
end
endmodule //convolve_kernel
|
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [17:0] sw,
output wire [8:0] ledg,
output wire [17:0] ledr,
output wire [6:0] hex0,
output wire [6:0] hex1,
output wire [6:0] hex2,
output wire [6:0] hex3,
output wire [6:0] hex4,
output wire [6:0] hex5,
output wire [6:0] hex6,
output wire [6:0] hex7,
output wire [35:0] gpio,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy0_rx_clk,
input wire [3:0] phy0_rxd,
input wire phy0_rx_ctl,
output wire phy0_tx_clk,
output wire [3:0] phy0_txd,
output wire phy0_tx_ctl,
output wire phy0_reset_n,
input wire phy0_int_n,
input wire phy1_rx_clk,
input wire [3:0] phy1_rxd,
input wire phy1_rx_ctl,
output wire phy1_tx_clk,
output wire [3:0] phy1_txd,
output wire phy1_tx_ctl,
output wire phy1_reset_n,
input wire phy1_int_n
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
if (rst) begin
led_reg <= 0;
end
end
// place dest IP onto 7 segment displays
reg [31:0] dest_ip_reg = 0;
always @(posedge clk) begin
if (tx_udp_hdr_valid) begin
dest_ip_reg <= tx_udp_ip_dest_ip;
end
if (rst) begin
dest_ip_reg <= 0;
end
end
hex_display #(
.INVERT(1)
)
hex_display_0 (
.in(dest_ip_reg[3:0]),
.enable(1),
.out(hex0)
);
hex_display #(
.INVERT(1)
)
hex_display_1 (
.in(dest_ip_reg[7:4]),
.enable(1),
.out(hex1)
);
hex_display #(
.INVERT(1)
)
hex_display_2 (
.in(dest_ip_reg[11:8]),
.enable(1),
.out(hex2)
);
hex_display #(
.INVERT(1)
)
hex_display_3 (
.in(dest_ip_reg[15:12]),
.enable(1),
.out(hex3)
);
hex_display #(
.INVERT(1)
)
hex_display_4 (
.in(dest_ip_reg[19:16]),
.enable(1),
.out(hex4)
);
hex_display #(
.INVERT(1)
)
hex_display_5 (
.in(dest_ip_reg[23:20]),
.enable(1),
.out(hex5)
);
hex_display #(
.INVERT(1)
)
hex_display_6 (
.in(dest_ip_reg[27:24]),
.enable(1),
.out(hex6)
);
hex_display #(
.INVERT(1)
)
hex_display_7 (
.in(dest_ip_reg[31:28]),
.enable(1),
.out(hex7)
);
//assign led = sw;
assign ledg = led_reg;
assign ledr = sw;
assign phy0_reset_n = ~rst;
assign phy1_reset_n = ~rst;
assign gpio = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy0_rx_clk),
.rgmii_rxd(phy0_rxd),
.rgmii_rx_ctl(phy0_rx_ctl),
.rgmii_tx_clk(phy0_tx_clk),
.rgmii_txd(phy0_txd),
.rgmii_tx_ctl(phy0_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Alex Solomatnikov.
interface hex2ram_if
(
input bit trigger
);
string instance_path = $sformatf("%m");
string testfile = "";
bit has_testfile = |($value$plusargs("testfile=%s", testfile));
bit armed = 1'b1;
bit armed_trigger;
initial begin
$display("successfully bound hex2ram_if to %s", instance_path);
armed = has_testfile && 1'b1;
end
assign armed_trigger = armed && trigger;
always @(posedge armed_trigger) begin
$display("%m(%0t): saw deassertion of reset", $time);
end
endinterface : hex2ram_if
module t
(
clk
);
input clk /*verilator clocker*/;
bit reset;
wire success;
SimpleTestHarness testHarness
(
.clk(clk),
.reset(reset),
.io_success(success)
);
integer cyc=0;
always @ (posedge clk) begin
cyc = cyc + 1;
if (cyc<10) begin
reset <= '0;
end
else if (cyc<20) begin
reset <= '1;
end
else if (cyc<30) begin
reset <= '0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset));
module testharness_ext
(
input W0_clk,
input [24:0] W0_addr,
input W0_en,
input [127:0] W0_data,
input [0:0] W0_mask,
input R0_clk,
input [24:0] R0_addr,
input R0_en,
output [127:0] R0_data
);
reg [24:0] reg_R0_addr;
wire [127:0] R0_rdata_mask;
reg [127:0] ram [33554431:0];
wire [127:0] W0_wdata_mask;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask;
end
assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;;
assign R0_rdata_mask = 0;
assign W0_wdata_mask = 0;
endmodule
module SimpleTestHarness
(
input clk,
input reset,
output io_success);
wire [24:0] testharness_ext_R0_addr;
wire testharness_ext_R0_en;
wire testharness_ext_R0_clk;
wire [127:0] testharness_ext_R0_data;
wire [24:0] testharness_ext_W0_addr;
wire testharness_ext_W0_en;
wire testharness_ext_W0_clk;
wire [127:0] testharness_ext_W0_data;
wire [0:0] testharness_ext_W0_mask;
testharness_ext testharness_ext
(
.R0_addr(testharness_ext_R0_addr),
.R0_en(testharness_ext_R0_en),
.R0_clk(testharness_ext_R0_clk),
.R0_data(testharness_ext_R0_data),
.W0_addr(testharness_ext_W0_addr),
.W0_en(testharness_ext_W0_en),
.W0_clk(testharness_ext_W0_clk),
.W0_data(testharness_ext_W0_data),
.W0_mask(testharness_ext_W0_mask)
);
endmodule
|
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