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stringlengths 938
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//=======================================================
// ROM selection arbiter
//=======================================================
module romsel(
// Selection
input [3:0] selector_i,
// Output
output [7:0] d_o,
// Inputs
input [7:0] d0_i,
input [7:0] d1_i,
input [7:0] d2_i,
input [7:0] d3_i,
input [7:0] d4_i,
input [7:0] d5_i,
input [7:0] d6_i,
input [7:0] d7_i,
input [7:0] d8_i,
input [7:0] d9_i,
input [7:0] d10_i,
input [7:0] d11_i,
input [7:0] d12_i,
input [7:0] d13_i,
input [7:0] d14_i,
input [7:0] d15_i
);
assign d_o =
(selector_i == 4'd1) ? d1_i :
(selector_i == 4'd2) ? d2_i :
(selector_i == 4'd3) ? d3_i :
(selector_i == 4'd4) ? d4_i :
(selector_i == 4'd5) ? d5_i :
(selector_i == 4'd6) ? d6_i :
(selector_i == 4'd7) ? d7_i :
(selector_i == 4'd8) ? d8_i :
(selector_i == 4'd9) ? d9_i :
(selector_i == 4'd10) ? d10_i :
(selector_i == 4'd11) ? d11_i :
(selector_i == 4'd12) ? d12_i :
(selector_i == 4'd13) ? d13_i :
(selector_i == 4'd14) ? d14_i :
(selector_i == 4'd15) ? d15_i :
d0_i;
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description :
// / /
// /__/ /\ Filename : MUXF9.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/unified/chen/g2ltw/g2ltw.pl
// Revision: 1.0
// 09/26/12 - 680234 - ncsim compile error
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MUXF9
`ifdef XIL_TIMING //Simprim
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I0,
input I1,
input S
);
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module lr_old(clk, raddr,waddr, data_in, data_out, we, reset);
input clk;
input [13:2] raddr;
input [13:2] waddr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input reset;
RAMB16_S4_2_altera localram0(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[3:0]),
.wren (we[0]),
.q (data_out[3:0])
);
defparam localram0.init_file = "cm_new_aipv4_00.mif";
//defparam localram0.init_file = "lm_cm_00.mif";
//defparam localram0.init_file = "cm_final_00.mif";
RAMB16_S4_2_altera localram1(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[7:4]),
.wren (we[0]),
.q (data_out[7:4])
);
//defparam localram1.init_file = "lm_cm_01.mif";
defparam localram1.init_file = "cm_new_aipv4_01.mif";
//defparam localram1.init_file = "cm_final_01.mif";
RAMB16_S4_2_altera localram2(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[11:8]),
.wren (we[1]),
.q (data_out[11:8])
);
//defparam localram2.init_file = "lm_cm_02.mif";
defparam localram2.init_file = "cm_new_aipv4_02.mif";
//defparam localram2.init_file = "cm_final_02.mif";
RAMB16_S4_2_altera localram3(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[15:12]),
.wren (we[1]),
.q (data_out[15:12])
);
//defparam localram3.init_file = "lm_cm_03.mif";
defparam localram3.init_file = "cm_new_aipv4_03.mif";
//defparam localram3.init_file = "cm_final_03.mif";
RAMB16_S4_2_altera localram4(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[19:16]),
.wren (we[2]),
.q (data_out[19:16])
);
//defparam localram4.init_file = "lm_cm_04.mif";
defparam localram4.init_file = "cm_new_aipv4_04.mif";
//defparam localram4.init_file = "cm_final_04.mif";
RAMB16_S4_2_altera localram5(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[23:20]),
.wren (we[2]),
.q (data_out[23:20])
);
//defparam localram5.init_file = "lm_cm_05.mif";
defparam localram5.init_file = "cm_new_aipv4_05.mif";
//defparam localram5.init_file = "cm_final_05.mif";
RAMB16_S4_2_altera localram6(
// .aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[27:24]),
.wren (we[3]),
.q (data_out[27:24])
);
//defparam localram6.init_file = "lm_cm_06.mif";
defparam localram6.init_file = "cm_new_aipv4_06.mif";
//defparam localram6.init_file = "cm_final_06.mif";
RAMB16_S4_2_altera localram7(
// .aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[31:28]),
.wren (we[3]),
.q (data_out[31:28])
);
//defparam localram7.init_file = "lm_cm_07.mif";
defparam localram7.init_file = "cm_new_aipv4_07.mif";
//defparam localram7.init_file = "cm_final_07.mif";
endmodule
|
module konamicoder (
digit_0,
digit_1,
digit_2,
digit_3,
state
);
output [6:0] digit_0;
output [6:0] digit_1;
output [6:0] digit_2;
output [6:0] digit_3;
input [3:0] state;
wire [6:0] digit_0;
wire [6:0] digit_1;
wire [6:0] digit_2;
wire [6:0] digit_3;
// Least-significant bit is segment 'A', most significant is 'G'
parameter char_u = 7'b0111110;
parameter char_p = 7'b1110011;
parameter char_d = 7'b1011110;
parameter char_n = 7'b1010100;
parameter char_l = 7'b0111000;
parameter char_f = 7'b1110001;
parameter char_r = 7'b1010000;
parameter char_h = 7'b1110100;
parameter char_0 = 7'b0111111;
parameter char_1 = 7'b0000110;
parameter char_2 = 7'b1011011;
parameter char_9 = 7'b1101111;
parameter char_ = 7'b1000000;
assign digit_0 =
(state == 4'd0) ? char_ :
(state == 4'd1) ? char_u :
(state == 4'd2) ? char_u :
(state == 4'd3) ? char_d :
(state == 4'd4) ? char_d :
(state == 4'd5) ? char_l :
(state == 4'd6) ? char_r :
(state == 4'd7) ? char_l :
(state == 4'd8) ? char_r :
(state == 4'd9) ? char_9 : char_0;
assign digit_1 =
(state == 4'd0) ? char_ :
(state == 4'd1) ? char_p :
(state == 4'd2) ? char_p :
(state == 4'd3) ? char_n :
(state == 4'd4) ? char_n :
(state == 4'd5) ? char_f :
(state == 4'd6) ? char_h :
(state == 4'd7) ? char_f :
(state == 4'd8) ? char_h :
(state == 4'd9) ? char_9 : char_0;
assign digit_2 =
(state == 4'd0) ? char_ :
(state == 4'd1) ? char_ :
(state == 4'd2) ? char_ :
(state == 4'd3) ? char_ :
(state == 4'd4) ? char_ :
(state == 4'd5) ? char_ :
(state == 4'd6) ? char_ :
(state == 4'd7) ? char_ :
(state == 4'd8) ? char_ :
(state == 4'd9) ? char_9 : char_0;
assign digit_3 =
(state == 4'd0) ? char_ :
(state == 4'd1) ? char_1 :
(state == 4'd2) ? char_2 :
(state == 4'd3) ? char_1 :
(state == 4'd4) ? char_2 :
(state == 4'd5) ? char_1 :
(state == 4'd6) ? char_1 :
(state == 4'd7) ? char_2 :
(state == 4'd8) ? char_2 :
(state == 4'd9) ? char_9 : char_0;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_dwr,
src_adc_dsync,
src_adc_ddata,
src_adc_dovf,
dst_adc_dwr,
dst_adc_dsync,
dst_adc_ddata,
dst_adc_dovf
);
localparam RP_ID = 8'hA1;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_dwr;
input src_adc_dsync;
input [31:0] src_adc_ddata;
output src_adc_dovf;
output dst_adc_dwr;
output dst_adc_dsync;
output [31:0] dst_adc_ddata;
input dst_adc_dovf;
reg dst_adc_dwr;
reg dst_adc_dsync;
reg [31:0] dst_adc_ddata;
reg src_adc_dovf;
reg [31:0] status = 0;
reg [31:0] adc_pn_data = 0;
reg [ 3:0] mode;
reg [ 3:0] channel_sel;
wire adc_dvalid;
wire [31:0] adc_pn_data_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
// prbs function
function [31:0] pn;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[14] ^ din[13];
dout[30] = din[13] ^ din[12];
dout[29] = din[12] ^ din[11];
dout[28] = din[11] ^ din[10];
dout[27] = din[10] ^ din[9];
dout[26] = din[9] ^ din[8];
dout[25] = din[8] ^ din[7];
dout[24] = din[7] ^ din[6];
dout[23] = din[6] ^ din[5];
dout[22] = din[5] ^ din[4];
dout[21] = din[4] ^ din[3];
dout[20] = din[3] ^ din[2];
dout[19] = din[2] ^ din[1];
dout[18] = din[1] ^ din[0];
dout[17] = din[0] ^ din[14] ^ din[13];
dout[16] = din[14] ^ din[12];
dout[15] = din[13] ^ din[11];
dout[14] = din[12] ^ din[10];
dout[13] = din[11] ^ din[9];
dout[12] = din[10] ^ din[8];
dout[11] = din[9] ^ din[7];
dout[10] = din[8] ^ din[6];
dout[9] = din[7] ^ din[5];
dout[8] = din[6] ^ din[4];
dout[7] = din[5] ^ din[3];
dout[6] = din[4] ^ din[2];
dout[5] = din[3] ^ din[1];
dout[4] = din[2] ^ din[0];
dout[3] = din[1] ^ din[14] ^ din[13];
dout[2] = din[0] ^ din[13] ^ din[12];
dout[1] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[0] = din[13] ^ din[11] ^ din[12] ^ din[10];
pn = dout;
end
endfunction
assign adc_dvalid = src_adc_dwr & src_adc_dsync;
always @(posedge clk) begin
channel_sel <= control[3:0];
mode <= control[7:4];
end
// prbs generation
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_pn_data <= pn(adc_pn_data_s);
end
end
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? src_adc_ddata : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(32)
) i_pn_mon (
.adc_clk(clk),
.adc_valid_in(adc_dvalid),
.adc_data_in(src_adc_ddata),
.adc_data_pn(adc_pn_data),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// rx path are passed through on test mode
always @(posedge clk) begin
dst_adc_dwr <= src_adc_dwr;
dst_adc_dsync <= src_adc_dsync;
dst_adc_ddata <= src_adc_ddata;
src_adc_dovf <= dst_adc_dovf;
end
// setup status bits for gpio_out
always @(posedge clk) begin
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board periphal devices *
* on the DE2-35 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2_35 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
parameter VID_INPUT_CONTROL = 16'h0040;
parameter VID_CHROMA_GAIN_1 = 16'h2df4;
parameter VID_CHROMA_GAIN_2 = 16'h2e00;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7181 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
defparam
Auto_Init_Video_ROM.INPUT_CONTROL = VID_INPUT_CONTROL,
Auto_Init_Video_ROM.CHROMA_GAIN_1 = VID_CHROMA_GAIN_1,
Auto_Init_Video_ROM.CHROMA_GAIN_2 = VID_CHROMA_GAIN_2;
endmodule
|
/* Generated by Yosys 0.9+3981 (git sha1 9dd8133, gcc 10.1.0 -fPIC -Os) */
module gcd(clk, req_msg, req_rdy, req_val, reset, resp_msg, resp_rdy, resp_val);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
wire _327_;
wire _328_;
wire _329_;
wire _330_;
wire _331_;
wire _332_;
wire _333_;
wire _334_;
wire _335_;
wire _336_;
wire _337_;
wire _338_;
wire _339_;
wire _340_;
wire _341_;
wire _342_;
wire _343_;
wire _344_;
wire _345_;
wire _346_;
wire _347_;
wire _348_;
wire _349_;
wire _350_;
wire _351_;
wire _352_;
wire _353_;
wire _354_;
wire _355_;
wire _356_;
wire _357_;
wire _358_;
wire _359_;
wire _360_;
wire _361_;
wire _362_;
wire _363_;
wire _364_;
wire _365_;
wire _366_;
wire _367_;
wire _368_;
wire _369_;
wire _370_;
wire _371_;
wire _372_;
wire _373_;
wire _374_;
wire _375_;
wire _376_;
wire _377_;
wire _378_;
wire _379_;
wire _380_;
wire _381_;
wire _382_;
wire _383_;
wire _384_;
wire _385_;
wire _386_;
wire _387_;
wire _388_;
wire _389_;
wire _390_;
wire _391_;
wire _392_;
wire _393_;
wire _394_;
wire _395_;
wire _396_;
input clk;
wire \ctrl.curr_state__0[0] ;
wire \ctrl.curr_state__0[1] ;
wire \dpath.a_lt_b$in0[0] ;
wire \dpath.a_lt_b$in0[10] ;
wire \dpath.a_lt_b$in0[11] ;
wire \dpath.a_lt_b$in0[12] ;
wire \dpath.a_lt_b$in0[13] ;
wire \dpath.a_lt_b$in0[14] ;
wire \dpath.a_lt_b$in0[15] ;
wire \dpath.a_lt_b$in0[1] ;
wire \dpath.a_lt_b$in0[2] ;
wire \dpath.a_lt_b$in0[3] ;
wire \dpath.a_lt_b$in0[4] ;
wire \dpath.a_lt_b$in0[5] ;
wire \dpath.a_lt_b$in0[6] ;
wire \dpath.a_lt_b$in0[7] ;
wire \dpath.a_lt_b$in0[8] ;
wire \dpath.a_lt_b$in0[9] ;
wire \dpath.a_lt_b$in1[0] ;
wire \dpath.a_lt_b$in1[10] ;
wire \dpath.a_lt_b$in1[11] ;
wire \dpath.a_lt_b$in1[12] ;
wire \dpath.a_lt_b$in1[13] ;
wire \dpath.a_lt_b$in1[14] ;
wire \dpath.a_lt_b$in1[15] ;
wire \dpath.a_lt_b$in1[1] ;
wire \dpath.a_lt_b$in1[2] ;
wire \dpath.a_lt_b$in1[3] ;
wire \dpath.a_lt_b$in1[4] ;
wire \dpath.a_lt_b$in1[5] ;
wire \dpath.a_lt_b$in1[6] ;
wire \dpath.a_lt_b$in1[7] ;
wire \dpath.a_lt_b$in1[8] ;
wire \dpath.a_lt_b$in1[9] ;
input [31:0] req_msg;
output req_rdy;
input req_val;
input reset;
output [15:0] resp_msg;
input resp_rdy;
output resp_val;
INV_X1 _397_ (
.A(\dpath.a_lt_b$in0[2] ),
.ZN(_034_)
);
NAND2_X1 _398_ (
.A1(_034_),
.A2(\dpath.a_lt_b$in1[2] ),
.ZN(_035_)
);
INV_X1 _399_ (
.A(\dpath.a_lt_b$in1[2] ),
.ZN(_036_)
);
NAND2_X2 _400_ (
.A1(_036_),
.A2(\dpath.a_lt_b$in0[2] ),
.ZN(_037_)
);
NAND2_X2 _401_ (
.A1(_035_),
.A2(_037_),
.ZN(_038_)
);
INV_X1 _402_ (
.A(\dpath.a_lt_b$in0[3] ),
.ZN(_039_)
);
NAND2_X1 _403_ (
.A1(_039_),
.A2(\dpath.a_lt_b$in1[3] ),
.ZN(_040_)
);
INV_X1 _404_ (
.A(\dpath.a_lt_b$in1[3] ),
.ZN(_041_)
);
NAND2_X1 _405_ (
.A1(_041_),
.A2(\dpath.a_lt_b$in0[3] ),
.ZN(_042_)
);
NAND2_X2 _406_ (
.A1(_040_),
.A2(_042_),
.ZN(_043_)
);
NOR2_X4 _407_ (
.A1(_038_),
.A2(_043_),
.ZN(_044_)
);
INV_X1 _408_ (
.A(\dpath.a_lt_b$in1[1] ),
.ZN(_045_)
);
NAND2_X1 _409_ (
.A1(_045_),
.A2(\dpath.a_lt_b$in0[1] ),
.ZN(_046_)
);
NOR2_X1 _410_ (
.A1(_045_),
.A2(\dpath.a_lt_b$in0[1] ),
.ZN(_047_)
);
INV_X1 _411_ (
.A(_047_),
.ZN(_048_)
);
INV_X1 _412_ (
.A(\dpath.a_lt_b$in0[0] ),
.ZN(_049_)
);
NOR2_X1 _413_ (
.A1(_049_),
.A2(\dpath.a_lt_b$in1[0] ),
.ZN(_050_)
);
NAND2_X1 _414_ (
.A1(_048_),
.A2(_050_),
.ZN(_051_)
);
NAND3_X1 _415_ (
.A1(_044_),
.A2(_046_),
.A3(_051_),
.ZN(_052_)
);
NAND3_X1 _416_ (
.A1(_042_),
.A2(_034_),
.A3(\dpath.a_lt_b$in1[2] ),
.ZN(_053_)
);
NAND3_X1 _417_ (
.A1(_052_),
.A2(_040_),
.A3(_053_),
.ZN(_054_)
);
INV_X1 _418_ (
.A(\dpath.a_lt_b$in0[7] ),
.ZN(_055_)
);
NAND2_X1 _419_ (
.A1(_055_),
.A2(\dpath.a_lt_b$in1[7] ),
.ZN(_056_)
);
INV_X1 _420_ (
.A(\dpath.a_lt_b$in1[7] ),
.ZN(_057_)
);
NAND2_X1 _421_ (
.A1(_057_),
.A2(\dpath.a_lt_b$in0[7] ),
.ZN(_058_)
);
NAND2_X2 _422_ (
.A1(_056_),
.A2(_058_),
.ZN(_059_)
);
INV_X1 _423_ (
.A(\dpath.a_lt_b$in0[6] ),
.ZN(_060_)
);
NAND2_X1 _424_ (
.A1(_060_),
.A2(\dpath.a_lt_b$in1[6] ),
.ZN(_061_)
);
INV_X1 _425_ (
.A(\dpath.a_lt_b$in1[6] ),
.ZN(_062_)
);
NAND2_X2 _426_ (
.A1(_062_),
.A2(\dpath.a_lt_b$in0[6] ),
.ZN(_063_)
);
NAND2_X2 _427_ (
.A1(_061_),
.A2(_063_),
.ZN(_064_)
);
NOR2_X2 _428_ (
.A1(_059_),
.A2(_064_),
.ZN(_065_)
);
INV_X1 _429_ (
.A(_065_),
.ZN(_066_)
);
INV_X1 _430_ (
.A(\dpath.a_lt_b$in1[4] ),
.ZN(_067_)
);
NOR2_X1 _431_ (
.A1(_067_),
.A2(\dpath.a_lt_b$in0[4] ),
.ZN(_068_)
);
INV_X2 _432_ (
.A(\dpath.a_lt_b$in0[4] ),
.ZN(_069_)
);
NOR2_X1 _433_ (
.A1(_069_),
.A2(\dpath.a_lt_b$in1[4] ),
.ZN(_070_)
);
NOR2_X1 _434_ (
.A1(_068_),
.A2(_070_),
.ZN(_071_)
);
INV_X1 _435_ (
.A(\dpath.a_lt_b$in1[5] ),
.ZN(_072_)
);
NOR2_X1 _436_ (
.A1(_072_),
.A2(\dpath.a_lt_b$in0[5] ),
.ZN(_073_)
);
INV_X2 _437_ (
.A(\dpath.a_lt_b$in0[5] ),
.ZN(_074_)
);
NOR2_X1 _438_ (
.A1(_074_),
.A2(\dpath.a_lt_b$in1[5] ),
.ZN(_075_)
);
NOR2_X1 _439_ (
.A1(_073_),
.A2(_075_),
.ZN(_076_)
);
NAND2_X1 _440_ (
.A1(_071_),
.A2(_076_),
.ZN(_077_)
);
NOR2_X4 _441_ (
.A1(_066_),
.A2(_077_),
.ZN(_078_)
);
NAND2_X1 _442_ (
.A1(_054_),
.A2(_078_),
.ZN(_079_)
);
OAI21_X1 _443_ (
.A(_056_),
.B1(_059_),
.B2(_061_),
.ZN(_080_)
);
INV_X1 _444_ (
.A(_080_),
.ZN(_081_)
);
INV_X1 _445_ (
.A(_068_),
.ZN(_082_)
);
INV_X1 _446_ (
.A(_073_),
.ZN(_083_)
);
NAND2_X1 _447_ (
.A1(_082_),
.A2(_083_),
.ZN(_084_)
);
INV_X1 _448_ (
.A(_075_),
.ZN(_085_)
);
NAND3_X1 _449_ (
.A1(_065_),
.A2(_084_),
.A3(_085_),
.ZN(_086_)
);
NAND3_X1 _450_ (
.A1(_079_),
.A2(_081_),
.A3(_086_),
.ZN(_087_)
);
INV_X2 _451_ (
.A(\dpath.a_lt_b$in0[10] ),
.ZN(_088_)
);
NOR2_X2 _452_ (
.A1(_088_),
.A2(\dpath.a_lt_b$in1[10] ),
.ZN(_089_)
);
INV_X2 _453_ (
.A(_089_),
.ZN(_090_)
);
NAND2_X1 _454_ (
.A1(_088_),
.A2(\dpath.a_lt_b$in1[10] ),
.ZN(_091_)
);
AND2_X2 _455_ (
.A1(_090_),
.A2(_091_),
.ZN(_092_)
);
INV_X1 _456_ (
.A(\dpath.a_lt_b$in0[11] ),
.ZN(_093_)
);
NOR2_X2 _457_ (
.A1(_093_),
.A2(\dpath.a_lt_b$in1[11] ),
.ZN(_094_)
);
INV_X2 _458_ (
.A(\dpath.a_lt_b$in1[11] ),
.ZN(_095_)
);
NOR2_X2 _459_ (
.A1(_095_),
.A2(\dpath.a_lt_b$in0[11] ),
.ZN(_096_)
);
NOR2_X4 _460_ (
.A1(_094_),
.A2(_096_),
.ZN(_097_)
);
NAND2_X2 _461_ (
.A1(_092_),
.A2(_097_),
.ZN(_098_)
);
INV_X1 _462_ (
.A(\dpath.a_lt_b$in1[8] ),
.ZN(_099_)
);
NOR2_X2 _463_ (
.A1(_099_),
.A2(\dpath.a_lt_b$in0[8] ),
.ZN(_100_)
);
INV_X2 _464_ (
.A(\dpath.a_lt_b$in0[8] ),
.ZN(_101_)
);
NOR2_X2 _465_ (
.A1(_101_),
.A2(\dpath.a_lt_b$in1[8] ),
.ZN(_102_)
);
NOR2_X4 _466_ (
.A1(_100_),
.A2(_102_),
.ZN(_103_)
);
INV_X1 _467_ (
.A(_103_),
.ZN(_104_)
);
INV_X1 _468_ (
.A(\dpath.a_lt_b$in1[9] ),
.ZN(_105_)
);
NOR2_X2 _469_ (
.A1(_105_),
.A2(\dpath.a_lt_b$in0[9] ),
.ZN(_106_)
);
INV_X1 _470_ (
.A(\dpath.a_lt_b$in0[9] ),
.ZN(_107_)
);
NOR2_X2 _471_ (
.A1(_107_),
.A2(\dpath.a_lt_b$in1[9] ),
.ZN(_108_)
);
NOR2_X4 _472_ (
.A1(_106_),
.A2(_108_),
.ZN(_109_)
);
INV_X2 _473_ (
.A(_109_),
.ZN(_110_)
);
NOR3_X4 _474_ (
.A1(_098_),
.A2(_104_),
.A3(_110_),
.ZN(_111_)
);
INV_X2 _475_ (
.A(\dpath.a_lt_b$in1[14] ),
.ZN(_112_)
);
NOR2_X1 _476_ (
.A1(_112_),
.A2(\dpath.a_lt_b$in0[14] ),
.ZN(_113_)
);
INV_X1 _477_ (
.A(_113_),
.ZN(_114_)
);
NAND2_X1 _478_ (
.A1(_112_),
.A2(\dpath.a_lt_b$in0[14] ),
.ZN(_115_)
);
NAND2_X1 _479_ (
.A1(_114_),
.A2(_115_),
.ZN(_116_)
);
INV_X2 _480_ (
.A(\dpath.a_lt_b$in1[15] ),
.ZN(_117_)
);
NOR2_X1 _481_ (
.A1(_117_),
.A2(\dpath.a_lt_b$in0[15] ),
.ZN(_118_)
);
INV_X2 _482_ (
.A(_118_),
.ZN(_119_)
);
NAND2_X1 _483_ (
.A1(_117_),
.A2(\dpath.a_lt_b$in0[15] ),
.ZN(_120_)
);
NAND2_X2 _484_ (
.A1(_119_),
.A2(_120_),
.ZN(_121_)
);
NOR2_X2 _485_ (
.A1(_116_),
.A2(_121_),
.ZN(_122_)
);
INV_X2 _486_ (
.A(\dpath.a_lt_b$in1[13] ),
.ZN(_123_)
);
NOR2_X1 _487_ (
.A1(_123_),
.A2(\dpath.a_lt_b$in0[13] ),
.ZN(_124_)
);
INV_X1 _488_ (
.A(_124_),
.ZN(_125_)
);
NAND2_X1 _489_ (
.A1(_123_),
.A2(\dpath.a_lt_b$in0[13] ),
.ZN(_126_)
);
NAND2_X1 _490_ (
.A1(_125_),
.A2(_126_),
.ZN(_127_)
);
INV_X2 _491_ (
.A(\dpath.a_lt_b$in1[12] ),
.ZN(_128_)
);
NOR2_X1 _492_ (
.A1(_128_),
.A2(\dpath.a_lt_b$in0[12] ),
.ZN(_129_)
);
INV_X2 _493_ (
.A(_129_),
.ZN(_130_)
);
NAND2_X2 _494_ (
.A1(_128_),
.A2(\dpath.a_lt_b$in0[12] ),
.ZN(_131_)
);
NAND2_X2 _495_ (
.A1(_130_),
.A2(_131_),
.ZN(_132_)
);
NOR2_X2 _496_ (
.A1(_127_),
.A2(_132_),
.ZN(_133_)
);
NAND2_X1 _497_ (
.A1(_122_),
.A2(_133_),
.ZN(_134_)
);
INV_X1 _498_ (
.A(_134_),
.ZN(_135_)
);
AND2_X4 _499_ (
.A1(_111_),
.A2(_135_),
.ZN(_136_)
);
NAND2_X2 _500_ (
.A1(_087_),
.A2(_136_),
.ZN(_137_)
);
INV_X1 _501_ (
.A(_108_),
.ZN(_138_)
);
OAI21_X1 _502_ (
.A(_138_),
.B1(_100_),
.B2(_106_),
.ZN(_139_)
);
OAI21_X1 _503_ (
.A(_091_),
.B1(\dpath.a_lt_b$in0[11] ),
.B2(_095_),
.ZN(_140_)
);
INV_X1 _504_ (
.A(_140_),
.ZN(_141_)
);
OAI22_X1 _505_ (
.A1(_098_),
.A2(_139_),
.B1(_141_),
.B2(_094_),
.ZN(_142_)
);
NAND2_X1 _506_ (
.A1(_142_),
.A2(_135_),
.ZN(_143_)
);
NAND2_X1 _507_ (
.A1(_125_),
.A2(_130_),
.ZN(_144_)
);
NAND3_X1 _508_ (
.A1(_122_),
.A2(_126_),
.A3(_144_),
.ZN(_145_)
);
OAI21_X1 _509_ (
.A(_119_),
.B1(_121_),
.B2(_114_),
.ZN(_146_)
);
INV_X1 _510_ (
.A(_146_),
.ZN(_147_)
);
NAND3_X1 _511_ (
.A1(_143_),
.A2(_145_),
.A3(_147_),
.ZN(_148_)
);
INV_X1 _512_ (
.A(_148_),
.ZN(_149_)
);
NAND2_X4 _513_ (
.A1(_137_),
.A2(_149_),
.ZN(_150_)
);
BUF_X2 _514_ (
.A(\ctrl.curr_state__0[0] ),
.Z(_151_)
);
INV_X2 _515_ (
.A(_151_),
.ZN(_152_)
);
BUF_X2 _516_ (
.A(\ctrl.curr_state__0[1] ),
.Z(_153_)
);
NOR2_X1 _517_ (
.A1(_152_),
.A2(_153_),
.ZN(_154_)
);
INV_X1 _518_ (
.A(\dpath.a_lt_b$in1[0] ),
.ZN(_155_)
);
NOR2_X2 _519_ (
.A1(_155_),
.A2(\dpath.a_lt_b$in0[0] ),
.ZN(_156_)
);
OR2_X1 _520_ (
.A1(_050_),
.A2(_156_),
.ZN(resp_msg[0])
);
NAND2_X1 _521_ (
.A1(_048_),
.A2(_046_),
.ZN(_157_)
);
NOR2_X1 _522_ (
.A1(resp_msg[0]),
.A2(_157_),
.ZN(_158_)
);
NAND4_X4 _523_ (
.A1(_136_),
.A2(_044_),
.A3(_078_),
.A4(_158_),
.ZN(_159_)
);
NAND3_X2 _524_ (
.A1(_150_),
.A2(_154_),
.A3(_159_),
.ZN(_160_)
);
OR2_X1 _525_ (
.A1(_160_),
.A2(_155_),
.ZN(_161_)
);
INV_X1 _526_ (
.A(_154_),
.ZN(_162_)
);
AOI21_X4 _527_ (
.A(_162_),
.B1(_150_),
.B2(_159_),
.ZN(_163_)
);
BUF_X8 _528_ (
.A(_163_),
.Z(_164_)
);
NAND2_X1 _529_ (
.A1(_164_),
.A2(resp_msg[0]),
.ZN(_165_)
);
BUF_X1 _530_ (
.A(_153_),
.Z(_166_)
);
NAND2_X1 _531_ (
.A1(\dpath.a_lt_b$in0[0] ),
.A2(_166_),
.ZN(_167_)
);
NOR2_X1 _532_ (
.A1(_153_),
.A2(_151_),
.ZN(_168_)
);
BUF_X1 _533_ (
.A(_168_),
.Z(req_rdy)
);
NAND2_X1 _534_ (
.A1(req_rdy),
.A2(req_msg[16]),
.ZN(_169_)
);
NAND4_X1 _535_ (
.A1(_161_),
.A2(_165_),
.A3(_167_),
.A4(_169_),
.ZN(_002_)
);
XOR2_X1 _536_ (
.A(_157_),
.B(_156_),
.Z(resp_msg[1])
);
NAND2_X2 _537_ (
.A1(_164_),
.A2(resp_msg[1]),
.ZN(_170_)
);
NAND4_X1 _538_ (
.A1(_150_),
.A2(\dpath.a_lt_b$in1[1] ),
.A3(_154_),
.A4(_159_),
.ZN(_171_)
);
CLKBUF_X1 _539_ (
.A(_152_),
.Z(_172_)
);
AOI21_X1 _540_ (
.A(_166_),
.B1(_172_),
.B2(req_msg[17]),
.ZN(_173_)
);
NAND3_X2 _541_ (
.A1(_170_),
.A2(_171_),
.A3(_173_),
.ZN(_174_)
);
INV_X1 _542_ (
.A(\dpath.a_lt_b$in0[1] ),
.ZN(_175_)
);
NAND2_X1 _543_ (
.A1(_175_),
.A2(_166_),
.ZN(_176_)
);
NAND2_X2 _544_ (
.A1(_174_),
.A2(_176_),
.ZN(_177_)
);
INV_X2 _545_ (
.A(_177_),
.ZN(_003_)
);
NAND2_X1 _546_ (
.A1(_034_),
.A2(_166_),
.ZN(_178_)
);
OAI21_X1 _547_ (
.A(_046_),
.B1(_047_),
.B2(_156_),
.ZN(_179_)
);
XNOR2_X1 _548_ (
.A(_179_),
.B(_038_),
.ZN(resp_msg[2])
);
NAND2_X1 _549_ (
.A1(_163_),
.A2(resp_msg[2]),
.ZN(_180_)
);
CLKBUF_X1 _550_ (
.A(_153_),
.Z(_181_)
);
AOI21_X1 _551_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[18]),
.ZN(_182_)
);
NAND2_X1 _552_ (
.A1(_180_),
.A2(_182_),
.ZN(_183_)
);
NOR2_X1 _553_ (
.A1(_160_),
.A2(_036_),
.ZN(_184_)
);
OAI21_X1 _554_ (
.A(_178_),
.B1(_183_),
.B2(_184_),
.ZN(_185_)
);
INV_X1 _555_ (
.A(_185_),
.ZN(_004_)
);
NAND3_X1 _556_ (
.A1(_179_),
.A2(_035_),
.A3(_037_),
.ZN(_186_)
);
NAND2_X1 _557_ (
.A1(_186_),
.A2(_037_),
.ZN(_187_)
);
XNOR2_X1 _558_ (
.A(_187_),
.B(_043_),
.ZN(resp_msg[3])
);
NAND2_X1 _559_ (
.A1(_163_),
.A2(resp_msg[3]),
.ZN(_188_)
);
NAND4_X1 _560_ (
.A1(_150_),
.A2(\dpath.a_lt_b$in1[3] ),
.A3(_154_),
.A4(_159_),
.ZN(_189_)
);
AOI21_X1 _561_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[19]),
.ZN(_190_)
);
NAND3_X1 _562_ (
.A1(_188_),
.A2(_189_),
.A3(_190_),
.ZN(_191_)
);
NAND2_X1 _563_ (
.A1(_039_),
.A2(_166_),
.ZN(_192_)
);
NAND2_X1 _564_ (
.A1(_191_),
.A2(_192_),
.ZN(_193_)
);
INV_X1 _565_ (
.A(_193_),
.ZN(_005_)
);
NAND2_X2 _566_ (
.A1(_179_),
.A2(_044_),
.ZN(_194_)
);
INV_X1 _567_ (
.A(_040_),
.ZN(_195_)
);
OAI21_X1 _568_ (
.A(_042_),
.B1(_195_),
.B2(_037_),
.ZN(_196_)
);
INV_X1 _569_ (
.A(_196_),
.ZN(_197_)
);
NAND2_X2 _570_ (
.A1(_194_),
.A2(_197_),
.ZN(_198_)
);
XOR2_X1 _571_ (
.A(_198_),
.B(_071_),
.Z(resp_msg[4])
);
NAND2_X1 _572_ (
.A1(_163_),
.A2(resp_msg[4]),
.ZN(_199_)
);
NAND4_X1 _573_ (
.A1(_150_),
.A2(\dpath.a_lt_b$in1[4] ),
.A3(_154_),
.A4(_159_),
.ZN(_200_)
);
AOI21_X1 _574_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[20]),
.ZN(_201_)
);
NAND3_X1 _575_ (
.A1(_199_),
.A2(_200_),
.A3(_201_),
.ZN(_202_)
);
NAND2_X1 _576_ (
.A1(_069_),
.A2(_166_),
.ZN(_203_)
);
NAND2_X1 _577_ (
.A1(_202_),
.A2(_203_),
.ZN(_204_)
);
INV_X1 _578_ (
.A(_204_),
.ZN(_006_)
);
AOI21_X1 _579_ (
.A(_070_),
.B1(_198_),
.B2(_082_),
.ZN(_205_)
);
XNOR2_X1 _580_ (
.A(_205_),
.B(_076_),
.ZN(resp_msg[5])
);
NAND2_X1 _581_ (
.A1(_163_),
.A2(resp_msg[5]),
.ZN(_206_)
);
NAND4_X1 _582_ (
.A1(_150_),
.A2(\dpath.a_lt_b$in1[5] ),
.A3(_154_),
.A4(_159_),
.ZN(_207_)
);
AOI21_X1 _583_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[21]),
.ZN(_208_)
);
NAND3_X1 _584_ (
.A1(_206_),
.A2(_207_),
.A3(_208_),
.ZN(_209_)
);
NAND2_X1 _585_ (
.A1(_074_),
.A2(_166_),
.ZN(_210_)
);
NAND2_X1 _586_ (
.A1(_209_),
.A2(_210_),
.ZN(_211_)
);
INV_X1 _587_ (
.A(_211_),
.ZN(_007_)
);
AOI21_X1 _588_ (
.A(_077_),
.B1(_194_),
.B2(_197_),
.ZN(_212_)
);
NAND2_X1 _589_ (
.A1(_083_),
.A2(_070_),
.ZN(_213_)
);
NAND2_X1 _590_ (
.A1(_213_),
.A2(_085_),
.ZN(_214_)
);
NOR2_X1 _591_ (
.A1(_212_),
.A2(_214_),
.ZN(_215_)
);
XOR2_X1 _592_ (
.A(_215_),
.B(_064_),
.Z(resp_msg[6])
);
NAND2_X1 _593_ (
.A1(_163_),
.A2(resp_msg[6]),
.ZN(_216_)
);
NAND4_X1 _594_ (
.A1(_150_),
.A2(\dpath.a_lt_b$in1[6] ),
.A3(_154_),
.A4(_159_),
.ZN(_217_)
);
AOI21_X1 _595_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[22]),
.ZN(_218_)
);
NAND3_X1 _596_ (
.A1(_216_),
.A2(_217_),
.A3(_218_),
.ZN(_219_)
);
NAND2_X1 _597_ (
.A1(_060_),
.A2(_166_),
.ZN(_220_)
);
NAND2_X1 _598_ (
.A1(_219_),
.A2(_220_),
.ZN(_221_)
);
INV_X1 _599_ (
.A(_221_),
.ZN(_008_)
);
INV_X1 _600_ (
.A(_153_),
.ZN(_222_)
);
NOR2_X1 _601_ (
.A1(_222_),
.A2(\dpath.a_lt_b$in0[7] ),
.ZN(_223_)
);
AOI21_X1 _602_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[23]),
.ZN(_224_)
);
OAI21_X1 _603_ (
.A(_224_),
.B1(_160_),
.B2(_057_),
.ZN(_225_)
);
INV_X1 _604_ (
.A(_225_),
.ZN(_226_)
);
OAI21_X1 _605_ (
.A(_063_),
.B1(_215_),
.B2(_064_),
.ZN(_227_)
);
XNOR2_X1 _606_ (
.A(_227_),
.B(_059_),
.ZN(resp_msg[7])
);
NAND2_X1 _607_ (
.A1(_164_),
.A2(resp_msg[7]),
.ZN(_228_)
);
AOI21_X2 _608_ (
.A(_223_),
.B1(_226_),
.B2(_228_),
.ZN(_009_)
);
NAND2_X1 _609_ (
.A1(_198_),
.A2(_078_),
.ZN(_229_)
);
INV_X1 _610_ (
.A(_056_),
.ZN(_230_)
);
OAI21_X1 _611_ (
.A(_058_),
.B1(_230_),
.B2(_063_),
.ZN(_231_)
);
AOI21_X1 _612_ (
.A(_231_),
.B1(_065_),
.B2(_214_),
.ZN(_232_)
);
NAND2_X2 _613_ (
.A1(_229_),
.A2(_232_),
.ZN(_233_)
);
XNOR2_X1 _614_ (
.A(_233_),
.B(_104_),
.ZN(resp_msg[8])
);
NAND2_X1 _615_ (
.A1(_163_),
.A2(resp_msg[8]),
.ZN(_234_)
);
NAND4_X1 _616_ (
.A1(_150_),
.A2(\dpath.a_lt_b$in1[8] ),
.A3(_154_),
.A4(_159_),
.ZN(_235_)
);
AOI21_X1 _617_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[24]),
.ZN(_236_)
);
NAND3_X1 _618_ (
.A1(_234_),
.A2(_235_),
.A3(_236_),
.ZN(_237_)
);
NAND2_X1 _619_ (
.A1(_101_),
.A2(_166_),
.ZN(_238_)
);
NAND2_X1 _620_ (
.A1(_237_),
.A2(_238_),
.ZN(_239_)
);
INV_X1 _621_ (
.A(_239_),
.ZN(_010_)
);
NOR2_X1 _622_ (
.A1(_222_),
.A2(\dpath.a_lt_b$in0[9] ),
.ZN(_240_)
);
AOI21_X1 _623_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[25]),
.ZN(_241_)
);
OAI21_X1 _624_ (
.A(_241_),
.B1(_160_),
.B2(_105_),
.ZN(_242_)
);
INV_X1 _625_ (
.A(_242_),
.ZN(_243_)
);
AOI21_X1 _626_ (
.A(_102_),
.B1(_233_),
.B2(_103_),
.ZN(_244_)
);
XNOR2_X1 _627_ (
.A(_244_),
.B(_109_),
.ZN(resp_msg[9])
);
NAND2_X1 _628_ (
.A1(_164_),
.A2(resp_msg[9]),
.ZN(_245_)
);
AOI21_X2 _629_ (
.A(_240_),
.B1(_243_),
.B2(_245_),
.ZN(_011_)
);
NOR2_X1 _630_ (
.A1(_222_),
.A2(\dpath.a_lt_b$in0[10] ),
.ZN(_246_)
);
AOI21_X1 _631_ (
.A(_181_),
.B1(_152_),
.B2(req_msg[26]),
.ZN(_247_)
);
INV_X1 _632_ (
.A(\dpath.a_lt_b$in1[10] ),
.ZN(_248_)
);
OAI21_X1 _633_ (
.A(_247_),
.B1(_160_),
.B2(_248_),
.ZN(_249_)
);
INV_X1 _634_ (
.A(_249_),
.ZN(_250_)
);
NAND3_X1 _635_ (
.A1(_233_),
.A2(_103_),
.A3(_109_),
.ZN(_251_)
);
INV_X1 _636_ (
.A(_106_),
.ZN(_252_)
);
AOI21_X1 _637_ (
.A(_108_),
.B1(_252_),
.B2(_102_),
.ZN(_253_)
);
NAND2_X1 _638_ (
.A1(_251_),
.A2(_253_),
.ZN(_254_)
);
XOR2_X2 _639_ (
.A(_254_),
.B(_092_),
.Z(resp_msg[10])
);
NAND2_X1 _640_ (
.A1(_164_),
.A2(resp_msg[10]),
.ZN(_255_)
);
AOI21_X2 _641_ (
.A(_246_),
.B1(_250_),
.B2(_255_),
.ZN(_012_)
);
NOR2_X1 _642_ (
.A1(_222_),
.A2(\dpath.a_lt_b$in0[11] ),
.ZN(_256_)
);
AOI21_X1 _643_ (
.A(_153_),
.B1(_152_),
.B2(req_msg[27]),
.ZN(_257_)
);
OAI21_X1 _644_ (
.A(_257_),
.B1(_160_),
.B2(_095_),
.ZN(_258_)
);
INV_X1 _645_ (
.A(_258_),
.ZN(_259_)
);
AOI21_X1 _646_ (
.A(_089_),
.B1(_254_),
.B2(_091_),
.ZN(_260_)
);
XNOR2_X2 _647_ (
.A(_260_),
.B(_097_),
.ZN(resp_msg[11])
);
NAND2_X1 _648_ (
.A1(resp_msg[11]),
.A2(_164_),
.ZN(_261_)
);
AOI21_X2 _649_ (
.A(_256_),
.B1(_259_),
.B2(_261_),
.ZN(_013_)
);
NOR2_X1 _650_ (
.A1(_222_),
.A2(\dpath.a_lt_b$in0[12] ),
.ZN(_262_)
);
AOI21_X1 _651_ (
.A(_153_),
.B1(_152_),
.B2(req_msg[28]),
.ZN(_263_)
);
OAI21_X1 _652_ (
.A(_263_),
.B1(_160_),
.B2(_128_),
.ZN(_264_)
);
INV_X1 _653_ (
.A(_264_),
.ZN(_265_)
);
NAND2_X1 _654_ (
.A1(_233_),
.A2(_111_),
.ZN(_266_)
);
NOR2_X1 _655_ (
.A1(_098_),
.A2(_253_),
.ZN(_267_)
);
NOR2_X1 _656_ (
.A1(_090_),
.A2(_096_),
.ZN(_268_)
);
NOR3_X1 _657_ (
.A1(_267_),
.A2(_094_),
.A3(_268_),
.ZN(_269_)
);
NAND2_X2 _658_ (
.A1(_266_),
.A2(_269_),
.ZN(_270_)
);
XNOR2_X1 _659_ (
.A(_270_),
.B(_132_),
.ZN(resp_msg[12])
);
NAND2_X1 _660_ (
.A1(_164_),
.A2(resp_msg[12]),
.ZN(_271_)
);
AOI21_X2 _661_ (
.A(_262_),
.B1(_265_),
.B2(_271_),
.ZN(_014_)
);
NOR2_X1 _662_ (
.A1(_222_),
.A2(\dpath.a_lt_b$in0[13] ),
.ZN(_272_)
);
AOI21_X1 _663_ (
.A(_153_),
.B1(_152_),
.B2(req_msg[29]),
.ZN(_273_)
);
OAI21_X1 _664_ (
.A(_273_),
.B1(_160_),
.B2(_123_),
.ZN(_274_)
);
INV_X1 _665_ (
.A(_274_),
.ZN(_275_)
);
NAND3_X1 _666_ (
.A1(_270_),
.A2(_130_),
.A3(_131_),
.ZN(_276_)
);
NAND2_X1 _667_ (
.A1(_276_),
.A2(_131_),
.ZN(_277_)
);
XNOR2_X1 _668_ (
.A(_277_),
.B(_127_),
.ZN(resp_msg[13])
);
NAND2_X1 _669_ (
.A1(resp_msg[13]),
.A2(_164_),
.ZN(_278_)
);
AOI21_X2 _670_ (
.A(_272_),
.B1(_275_),
.B2(_278_),
.ZN(_015_)
);
NOR2_X1 _671_ (
.A1(_222_),
.A2(\dpath.a_lt_b$in0[14] ),
.ZN(_279_)
);
AOI21_X1 _672_ (
.A(_153_),
.B1(_152_),
.B2(req_msg[30]),
.ZN(_280_)
);
OAI21_X1 _673_ (
.A(_280_),
.B1(_160_),
.B2(_112_),
.ZN(_281_)
);
INV_X1 _674_ (
.A(_281_),
.ZN(_282_)
);
NAND2_X1 _675_ (
.A1(_270_),
.A2(_133_),
.ZN(_283_)
);
OAI21_X1 _676_ (
.A(_126_),
.B1(_124_),
.B2(_131_),
.ZN(_284_)
);
INV_X1 _677_ (
.A(_284_),
.ZN(_285_)
);
NAND2_X1 _678_ (
.A1(_283_),
.A2(_285_),
.ZN(_286_)
);
XNOR2_X1 _679_ (
.A(_286_),
.B(_116_),
.ZN(resp_msg[14])
);
NAND2_X1 _680_ (
.A1(resp_msg[14]),
.A2(_164_),
.ZN(_287_)
);
AOI21_X2 _681_ (
.A(_279_),
.B1(_282_),
.B2(_287_),
.ZN(_016_)
);
NOR2_X1 _682_ (
.A1(_222_),
.A2(\dpath.a_lt_b$in0[15] ),
.ZN(_288_)
);
INV_X1 _683_ (
.A(_116_),
.ZN(_289_)
);
NAND2_X1 _684_ (
.A1(_286_),
.A2(_289_),
.ZN(_290_)
);
NAND2_X1 _685_ (
.A1(_290_),
.A2(_115_),
.ZN(_291_)
);
INV_X1 _686_ (
.A(_121_),
.ZN(_292_)
);
NAND2_X1 _687_ (
.A1(_291_),
.A2(_292_),
.ZN(_293_)
);
NAND3_X1 _688_ (
.A1(_290_),
.A2(_115_),
.A3(_121_),
.ZN(_294_)
);
NAND3_X1 _689_ (
.A1(_293_),
.A2(_294_),
.A3(_164_),
.ZN(_295_)
);
NAND4_X1 _690_ (
.A1(_150_),
.A2(\dpath.a_lt_b$in1[15] ),
.A3(_154_),
.A4(_159_),
.ZN(_296_)
);
AOI21_X1 _691_ (
.A(_181_),
.B1(_172_),
.B2(req_msg[31]),
.ZN(_297_)
);
NAND2_X1 _692_ (
.A1(_296_),
.A2(_297_),
.ZN(_298_)
);
INV_X1 _693_ (
.A(_298_),
.ZN(_299_)
);
AOI21_X2 _694_ (
.A(_288_),
.B1(_295_),
.B2(_299_),
.ZN(_017_)
);
NAND2_X4 _695_ (
.A1(_150_),
.A2(_159_),
.ZN(_300_)
);
AOI21_X4 _696_ (
.A(_153_),
.B1(_300_),
.B2(_151_),
.ZN(_301_)
);
BUF_X8 _697_ (
.A(_301_),
.Z(_302_)
);
BUF_X1 _698_ (
.A(_168_),
.Z(_303_)
);
NAND2_X1 _699_ (
.A1(_303_),
.A2(req_msg[0]),
.ZN(_304_)
);
OAI21_X1 _700_ (
.A(_304_),
.B1(_049_),
.B2(req_rdy),
.ZN(_305_)
);
NAND2_X1 _701_ (
.A1(_302_),
.A2(_305_),
.ZN(_306_)
);
BUF_X4 _702_ (
.A(_301_),
.Z(_307_)
);
OAI21_X1 _703_ (
.A(_306_),
.B1(_155_),
.B2(_307_),
.ZN(_018_)
);
NAND2_X1 _704_ (
.A1(_303_),
.A2(req_msg[1]),
.ZN(_308_)
);
OAI21_X1 _705_ (
.A(_308_),
.B1(_175_),
.B2(req_rdy),
.ZN(_309_)
);
NAND2_X1 _706_ (
.A1(_302_),
.A2(_309_),
.ZN(_310_)
);
OAI21_X1 _707_ (
.A(_310_),
.B1(_045_),
.B2(_307_),
.ZN(_019_)
);
NAND2_X1 _708_ (
.A1(_303_),
.A2(req_msg[2]),
.ZN(_311_)
);
OAI21_X1 _709_ (
.A(_311_),
.B1(_034_),
.B2(req_rdy),
.ZN(_312_)
);
NAND2_X1 _710_ (
.A1(_302_),
.A2(_312_),
.ZN(_313_)
);
OAI21_X1 _711_ (
.A(_313_),
.B1(_036_),
.B2(_307_),
.ZN(_020_)
);
NAND2_X1 _712_ (
.A1(_303_),
.A2(req_msg[3]),
.ZN(_314_)
);
OAI21_X1 _713_ (
.A(_314_),
.B1(_039_),
.B2(req_rdy),
.ZN(_315_)
);
NAND2_X1 _714_ (
.A1(_302_),
.A2(_315_),
.ZN(_316_)
);
OAI21_X1 _715_ (
.A(_316_),
.B1(_041_),
.B2(_307_),
.ZN(_021_)
);
BUF_X8 _716_ (
.A(_301_),
.Z(_317_)
);
NAND2_X1 _717_ (
.A1(_303_),
.A2(req_msg[4]),
.ZN(_318_)
);
OAI21_X1 _718_ (
.A(_318_),
.B1(_069_),
.B2(req_rdy),
.ZN(_319_)
);
NAND2_X1 _719_ (
.A1(_317_),
.A2(_319_),
.ZN(_320_)
);
OAI21_X1 _720_ (
.A(_320_),
.B1(_067_),
.B2(_307_),
.ZN(_022_)
);
NAND2_X1 _721_ (
.A1(_303_),
.A2(req_msg[5]),
.ZN(_321_)
);
OAI21_X1 _722_ (
.A(_321_),
.B1(_074_),
.B2(req_rdy),
.ZN(_322_)
);
NAND2_X1 _723_ (
.A1(_317_),
.A2(_322_),
.ZN(_323_)
);
OAI21_X1 _724_ (
.A(_323_),
.B1(_072_),
.B2(_307_),
.ZN(_023_)
);
BUF_X1 _725_ (
.A(_168_),
.Z(_324_)
);
NAND2_X1 _726_ (
.A1(_324_),
.A2(req_msg[6]),
.ZN(_325_)
);
OAI21_X1 _727_ (
.A(_325_),
.B1(_060_),
.B2(req_rdy),
.ZN(_326_)
);
NAND2_X1 _728_ (
.A1(_317_),
.A2(_326_),
.ZN(_327_)
);
OAI21_X1 _729_ (
.A(_327_),
.B1(_062_),
.B2(_307_),
.ZN(_024_)
);
NAND2_X1 _730_ (
.A1(_324_),
.A2(req_msg[7]),
.ZN(_328_)
);
OAI21_X1 _731_ (
.A(_328_),
.B1(_055_),
.B2(req_rdy),
.ZN(_329_)
);
NAND2_X1 _732_ (
.A1(_317_),
.A2(_329_),
.ZN(_330_)
);
OAI21_X1 _733_ (
.A(_330_),
.B1(_057_),
.B2(_307_),
.ZN(_025_)
);
NAND2_X1 _734_ (
.A1(_324_),
.A2(req_msg[8]),
.ZN(_331_)
);
OAI21_X1 _735_ (
.A(_331_),
.B1(_101_),
.B2(_303_),
.ZN(_332_)
);
NAND2_X1 _736_ (
.A1(_317_),
.A2(_332_),
.ZN(_333_)
);
OAI21_X1 _737_ (
.A(_333_),
.B1(_099_),
.B2(_307_),
.ZN(_026_)
);
NAND2_X1 _738_ (
.A1(_324_),
.A2(req_msg[9]),
.ZN(_334_)
);
OAI21_X1 _739_ (
.A(_334_),
.B1(_107_),
.B2(_303_),
.ZN(_335_)
);
NAND2_X1 _740_ (
.A1(_317_),
.A2(_335_),
.ZN(_336_)
);
OAI21_X1 _741_ (
.A(_336_),
.B1(_105_),
.B2(_307_),
.ZN(_027_)
);
NAND2_X1 _742_ (
.A1(_324_),
.A2(req_msg[10]),
.ZN(_337_)
);
OAI21_X1 _743_ (
.A(_337_),
.B1(_088_),
.B2(_303_),
.ZN(_338_)
);
NAND2_X1 _744_ (
.A1(_317_),
.A2(_338_),
.ZN(_339_)
);
OAI21_X1 _745_ (
.A(_339_),
.B1(_248_),
.B2(_302_),
.ZN(_028_)
);
NAND2_X1 _746_ (
.A1(_324_),
.A2(req_msg[11]),
.ZN(_340_)
);
OAI21_X1 _747_ (
.A(_340_),
.B1(_093_),
.B2(_303_),
.ZN(_341_)
);
NAND2_X1 _748_ (
.A1(_317_),
.A2(_341_),
.ZN(_342_)
);
OAI21_X1 _749_ (
.A(_342_),
.B1(_095_),
.B2(_302_),
.ZN(_029_)
);
MUX2_X1 _750_ (
.A(\dpath.a_lt_b$in0[12] ),
.B(req_msg[12]),
.S(_324_),
.Z(_343_)
);
NAND2_X1 _751_ (
.A1(_317_),
.A2(_343_),
.ZN(_344_)
);
OAI21_X1 _752_ (
.A(_344_),
.B1(_128_),
.B2(_302_),
.ZN(_030_)
);
MUX2_X1 _753_ (
.A(\dpath.a_lt_b$in0[13] ),
.B(req_msg[13]),
.S(_324_),
.Z(_345_)
);
NAND2_X1 _754_ (
.A1(_317_),
.A2(_345_),
.ZN(_346_)
);
OAI21_X1 _755_ (
.A(_346_),
.B1(_123_),
.B2(_302_),
.ZN(_031_)
);
MUX2_X1 _756_ (
.A(\dpath.a_lt_b$in0[14] ),
.B(req_msg[14]),
.S(_324_),
.Z(_347_)
);
NAND2_X1 _757_ (
.A1(_301_),
.A2(_347_),
.ZN(_348_)
);
OAI21_X1 _758_ (
.A(_348_),
.B1(_112_),
.B2(_302_),
.ZN(_032_)
);
MUX2_X1 _759_ (
.A(\dpath.a_lt_b$in0[15] ),
.B(req_msg[15]),
.S(_324_),
.Z(_349_)
);
NAND2_X1 _760_ (
.A1(_301_),
.A2(_349_),
.ZN(_350_)
);
OAI21_X1 _761_ (
.A(_350_),
.B1(_117_),
.B2(_302_),
.ZN(_033_)
);
NAND2_X1 _762_ (
.A1(_300_),
.A2(_154_),
.ZN(_351_)
);
NOR4_X1 _763_ (
.A1(\dpath.a_lt_b$in1[4] ),
.A2(\dpath.a_lt_b$in1[5] ),
.A3(\dpath.a_lt_b$in1[6] ),
.A4(\dpath.a_lt_b$in1[7] ),
.ZN(_352_)
);
NOR4_X1 _764_ (
.A1(\dpath.a_lt_b$in1[0] ),
.A2(\dpath.a_lt_b$in1[1] ),
.A3(\dpath.a_lt_b$in1[2] ),
.A4(\dpath.a_lt_b$in1[3] ),
.ZN(_353_)
);
NOR4_X1 _765_ (
.A1(\dpath.a_lt_b$in1[12] ),
.A2(\dpath.a_lt_b$in1[13] ),
.A3(\dpath.a_lt_b$in1[14] ),
.A4(\dpath.a_lt_b$in1[15] ),
.ZN(_354_)
);
NOR4_X1 _766_ (
.A1(\dpath.a_lt_b$in1[8] ),
.A2(\dpath.a_lt_b$in1[9] ),
.A3(\dpath.a_lt_b$in1[10] ),
.A4(\dpath.a_lt_b$in1[11] ),
.ZN(_355_)
);
NAND4_X1 _767_ (
.A1(_352_),
.A2(_353_),
.A3(_354_),
.A4(_355_),
.ZN(_356_)
);
OR2_X1 _768_ (
.A1(_351_),
.A2(_356_),
.ZN(_357_)
);
NOR2_X1 _769_ (
.A1(_222_),
.A2(_151_),
.ZN(resp_val)
);
NOR2_X1 _770_ (
.A1(_151_),
.A2(req_val),
.ZN(_358_)
);
NOR3_X1 _771_ (
.A1(resp_val),
.A2(_358_),
.A3(reset),
.ZN(_359_)
);
AND2_X1 _772_ (
.A1(_357_),
.A2(_359_),
.ZN(_000_)
);
AOI21_X1 _773_ (
.A(reset),
.B1(resp_val),
.B2(resp_rdy),
.ZN(_360_)
);
INV_X1 _774_ (
.A(_357_),
.ZN(_361_)
);
OAI21_X1 _775_ (
.A(_360_),
.B1(_361_),
.B2(_166_),
.ZN(_362_)
);
INV_X1 _776_ (
.A(_362_),
.ZN(_001_)
);
AND2_X1 _777_ (
.A1(_293_),
.A2(_294_),
.ZN(resp_msg[15])
);
DFF_X1 _778_ (
.CK(clk),
.D(_000_),
.Q(\ctrl.curr_state__0[0] ),
.QN(_363_)
);
DFF_X1 _779_ (
.CK(clk),
.D(_001_),
.Q(\ctrl.curr_state__0[1] ),
.QN(_364_)
);
DFF_X1 _780_ (
.CK(clk),
.D(_002_),
.Q(\dpath.a_lt_b$in0[0] ),
.QN(_365_)
);
DFF_X1 _781_ (
.CK(clk),
.D(_003_),
.Q(\dpath.a_lt_b$in0[1] ),
.QN(_366_)
);
DFF_X1 _782_ (
.CK(clk),
.D(_004_),
.Q(\dpath.a_lt_b$in0[2] ),
.QN(_367_)
);
DFF_X1 _783_ (
.CK(clk),
.D(_005_),
.Q(\dpath.a_lt_b$in0[3] ),
.QN(_368_)
);
DFF_X1 _784_ (
.CK(clk),
.D(_006_),
.Q(\dpath.a_lt_b$in0[4] ),
.QN(_369_)
);
DFF_X1 _785_ (
.CK(clk),
.D(_007_),
.Q(\dpath.a_lt_b$in0[5] ),
.QN(_370_)
);
DFF_X1 _786_ (
.CK(clk),
.D(_008_),
.Q(\dpath.a_lt_b$in0[6] ),
.QN(_371_)
);
DFF_X1 _787_ (
.CK(clk),
.D(_009_),
.Q(\dpath.a_lt_b$in0[7] ),
.QN(_372_)
);
DFF_X1 _788_ (
.CK(clk),
.D(_010_),
.Q(\dpath.a_lt_b$in0[8] ),
.QN(_373_)
);
DFF_X1 _789_ (
.CK(clk),
.D(_011_),
.Q(\dpath.a_lt_b$in0[9] ),
.QN(_374_)
);
DFF_X1 _790_ (
.CK(clk),
.D(_012_),
.Q(\dpath.a_lt_b$in0[10] ),
.QN(_375_)
);
DFF_X1 _791_ (
.CK(clk),
.D(_013_),
.Q(\dpath.a_lt_b$in0[11] ),
.QN(_376_)
);
DFF_X1 _792_ (
.CK(clk),
.D(_014_),
.Q(\dpath.a_lt_b$in0[12] ),
.QN(_377_)
);
DFF_X1 _793_ (
.CK(clk),
.D(_015_),
.Q(\dpath.a_lt_b$in0[13] ),
.QN(_378_)
);
DFF_X1 _794_ (
.CK(clk),
.D(_016_),
.Q(\dpath.a_lt_b$in0[14] ),
.QN(_379_)
);
DFF_X1 _795_ (
.CK(clk),
.D(_017_),
.Q(\dpath.a_lt_b$in0[15] ),
.QN(_380_)
);
DFF_X1 _796_ (
.CK(clk),
.D(_018_),
.Q(\dpath.a_lt_b$in1[0] ),
.QN(_381_)
);
DFF_X1 _797_ (
.CK(clk),
.D(_019_),
.Q(\dpath.a_lt_b$in1[1] ),
.QN(_382_)
);
DFF_X1 _798_ (
.CK(clk),
.D(_020_),
.Q(\dpath.a_lt_b$in1[2] ),
.QN(_383_)
);
DFF_X1 _799_ (
.CK(clk),
.D(_021_),
.Q(\dpath.a_lt_b$in1[3] ),
.QN(_384_)
);
DFF_X1 _800_ (
.CK(clk),
.D(_022_),
.Q(\dpath.a_lt_b$in1[4] ),
.QN(_385_)
);
DFF_X1 _801_ (
.CK(clk),
.D(_023_),
.Q(\dpath.a_lt_b$in1[5] ),
.QN(_386_)
);
DFF_X1 _802_ (
.CK(clk),
.D(_024_),
.Q(\dpath.a_lt_b$in1[6] ),
.QN(_387_)
);
DFF_X1 _803_ (
.CK(clk),
.D(_025_),
.Q(\dpath.a_lt_b$in1[7] ),
.QN(_388_)
);
DFF_X1 _804_ (
.CK(clk),
.D(_026_),
.Q(\dpath.a_lt_b$in1[8] ),
.QN(_389_)
);
DFF_X1 _805_ (
.CK(clk),
.D(_027_),
.Q(\dpath.a_lt_b$in1[9] ),
.QN(_390_)
);
DFF_X1 _806_ (
.CK(clk),
.D(_028_),
.Q(\dpath.a_lt_b$in1[10] ),
.QN(_391_)
);
DFF_X1 _807_ (
.CK(clk),
.D(_029_),
.Q(\dpath.a_lt_b$in1[11] ),
.QN(_392_)
);
DFF_X1 _808_ (
.CK(clk),
.D(_030_),
.Q(\dpath.a_lt_b$in1[12] ),
.QN(_393_)
);
DFF_X1 _809_ (
.CK(clk),
.D(_031_),
.Q(\dpath.a_lt_b$in1[13] ),
.QN(_394_)
);
DFF_X1 _810_ (
.CK(clk),
.D(_032_),
.Q(\dpath.a_lt_b$in1[14] ),
.QN(_395_)
);
DFF_X1 _811_ (
.CK(clk),
.D(_033_),
.Q(\dpath.a_lt_b$in1[15] ),
.QN(_396_)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_SYMBOL_V
`define SKY130_FD_SC_HS__O211A_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_SYMBOL_V
`define SKY130_FD_SC_MS__FILL_DIODE_SYMBOL_V
/**
* fill_diode: Fill diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fill_diode ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_SYMBOL_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : ram_2p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Dual Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
module ram_frame_row_32x480 (
clka ,
cena_i ,
oena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
oenb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=9;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input oena_i; // data output enable, low active
input wena_i; // write enable, low active
input [Addr_Width-1:0] addra_i; // address input
input [Word_Width-1:0] dataa_i; // data input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input oenb_i; // data output enable, low active
input wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
output [Word_Width-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if(!cena_i && !wena_i)
mem_array[addra_i] <= dataa_i;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = oena_i ? 'bz : dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = oenb_i ? 'bz : datab_r;
endmodule |
/* Generated by Yosys 0.9+2406 (git sha1 aafaeb66, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
module edge_enhance(clk, enable_feature, in_blank, in_hsync, in_vsync, in_red, in_green, in_blue, out_blank, out_hsync, out_vsync, out_red, out_green, out_blue);
reg [7:0] _0_;
reg [7:0] _1_;
input clk;
input enable_feature;
wire \i_line_delay_2%126 ;
wire \i_line_delay_2%127 ;
wire \i_line_delay_2%128 ;
wire [7:0] \i_line_delay_2%129 ;
wire [7:0] \i_line_delay_2%130 ;
wire [7:0] \i_line_delay_2%131 ;
input in_blank;
input [7:0] in_blue;
input [7:0] in_green;
input in_hsync;
input [7:0] in_red;
input in_vsync;
output out_blank;
output [7:0] out_blue;
output [7:0] out_green;
output out_hsync;
output [7:0] out_red;
output out_vsync;
always @(posedge clk)
_0_ <= \i_line_delay_2%130 ;
always @(posedge clk)
_1_ <= \i_line_delay_2%131 ;
line_delay i_line_delay_2 (
.clk(clk),
.in_blank(1'hz),
.in_blue(8'hxx),
.in_green(8'hxx),
.in_hsync(1'hz),
.in_red(8'hzz),
.in_vsync(1'hz),
.out_blank(\i_line_delay_2%126 ),
.out_blue(\i_line_delay_2%131 ),
.out_green(\i_line_delay_2%130 ),
.out_hsync(\i_line_delay_2%127 ),
.out_red(\i_line_delay_2%129 ),
.out_vsync(\i_line_delay_2%128 )
);
assign out_blank = 1'hz;
assign out_hsync = 1'hz;
assign out_vsync = 1'hz;
assign out_red = 8'hzz;
assign out_green = _0_;
assign out_blue = _1_;
endmodule
module hdmi_design(clk100, sw, hdmi_rx_scl, hdmi_rx_clk_n, hdmi_rx_clk_p, hdmi_rx_n, hdmi_rx_p, hdmi_tx_hpd, led, debug_pmod, hdmi_rx_cec, hdmi_rx_hpa, hdmi_rx_sda, hdmi_rx_txen, hdmi_tx_cec, hdmi_tx_clk_n, hdmi_tx_clk_p, hdmi_tx_rscl, hdmi_tx_rsda, hdmi_tx_p, hdmi_tx_n, rs232_tx);
input clk100;
output [7:0] debug_pmod;
inout hdmi_rx_cec;
input hdmi_rx_clk_n;
input hdmi_rx_clk_p;
output hdmi_rx_hpa;
input [2:0] hdmi_rx_n;
input [2:0] hdmi_rx_p;
input hdmi_rx_scl;
inout hdmi_rx_sda;
output hdmi_rx_txen;
inout hdmi_tx_cec;
output hdmi_tx_clk_n;
output hdmi_tx_clk_p;
input hdmi_tx_hpd;
output [2:0] hdmi_tx_n;
output [2:0] hdmi_tx_p;
inout hdmi_tx_rscl;
inout hdmi_tx_rsda;
output [7:0] led;
output rs232_tx;
input [7:0] sw;
assign hdmi_rx_cec = 1'hz;
assign hdmi_rx_sda = 1'hz;
assign hdmi_tx_cec = 1'hz;
assign hdmi_tx_rscl = 1'hz;
assign hdmi_tx_rsda = 1'hz;
assign led = 8'hzz;
assign debug_pmod = 8'hzz;
assign hdmi_rx_hpa = 1'hz;
assign hdmi_rx_txen = 1'hz;
assign hdmi_tx_clk_n = 1'hz;
assign hdmi_tx_clk_p = 1'hz;
assign hdmi_tx_p = 3'hz;
assign hdmi_tx_n = 3'hz;
assign rs232_tx = 1'hz;
endmodule
module line_delay(clk, in_blank, in_hsync, in_vsync, in_red, in_green, in_blue, out_blank, out_hsync, out_vsync, out_red, out_green, out_blue);
wire [8:0] _0_;
reg [7:0] _1_;
reg [7:0] _2_;
wire [13823:0] _3_;
wire [26:0] _4_;
wire [8:0] _5_;
input clk;
input in_blank;
input [7:0] in_blue;
input [7:0] in_green;
input in_hsync;
input [7:0] in_red;
input in_vsync;
output out_blank;
output [7:0] out_blue;
output [7:0] out_green;
output out_hsync;
output [7:0] out_red;
output out_vsync;
reg [26:0] \$mem$\208 [511:0];
assign _5_ = 9'h1ff - 9'h1ff;
assign _0_ = 9'h1ff - 9'h1ff;
always @(posedge clk)
_1_ <= _4_[18:11];
always @(posedge clk)
_2_ <= _4_[10:3];
reg [26:0] \208 [511:0];
initial begin
\208 [0] = 27'h0000000;
\208 [1] = 27'h0000000;
\208 [2] = 27'h0000000;
\208 [3] = 27'h0000000;
\208 [4] = 27'h0000000;
\208 [5] = 27'h0000000;
\208 [6] = 27'h0000000;
\208 [7] = 27'h0000000;
\208 [8] = 27'h0000000;
\208 [9] = 27'h0000000;
\208 [10] = 27'h0000000;
\208 [11] = 27'h0000000;
\208 [12] = 27'h0000000;
\208 [13] = 27'h0000000;
\208 [14] = 27'h0000000;
\208 [15] = 27'h0000000;
\208 [16] = 27'h0000000;
\208 [17] = 27'h0000000;
\208 [18] = 27'h0000000;
\208 [19] = 27'h0000000;
\208 [20] = 27'h0000000;
\208 [21] = 27'h0000000;
\208 [22] = 27'h0000000;
\208 [23] = 27'h0000000;
\208 [24] = 27'h0000000;
\208 [25] = 27'h0000000;
\208 [26] = 27'h0000000;
\208 [27] = 27'h0000000;
\208 [28] = 27'h0000000;
\208 [29] = 27'h0000000;
\208 [30] = 27'h0000000;
\208 [31] = 27'h0000000;
\208 [32] = 27'h0000000;
\208 [33] = 27'h0000000;
\208 [34] = 27'h0000000;
\208 [35] = 27'h0000000;
\208 [36] = 27'h0000000;
\208 [37] = 27'h0000000;
\208 [38] = 27'h0000000;
\208 [39] = 27'h0000000;
\208 [40] = 27'h0000000;
\208 [41] = 27'h0000000;
\208 [42] = 27'h0000000;
\208 [43] = 27'h0000000;
\208 [44] = 27'h0000000;
\208 [45] = 27'h0000000;
\208 [46] = 27'h0000000;
\208 [47] = 27'h0000000;
\208 [48] = 27'h0000000;
\208 [49] = 27'h0000000;
\208 [50] = 27'h0000000;
\208 [51] = 27'h0000000;
\208 [52] = 27'h0000000;
\208 [53] = 27'h0000000;
\208 [54] = 27'h0000000;
\208 [55] = 27'h0000000;
\208 [56] = 27'h0000000;
\208 [57] = 27'h0000000;
\208 [58] = 27'h0000000;
\208 [59] = 27'h0000000;
\208 [60] = 27'h0000000;
\208 [61] = 27'h0000000;
\208 [62] = 27'h0000000;
\208 [63] = 27'h0000000;
\208 [64] = 27'h0000000;
\208 [65] = 27'h0000000;
\208 [66] = 27'h0000000;
\208 [67] = 27'h0000000;
\208 [68] = 27'h0000000;
\208 [69] = 27'h0000000;
\208 [70] = 27'h0000000;
\208 [71] = 27'h0000000;
\208 [72] = 27'h0000000;
\208 [73] = 27'h0000000;
\208 [74] = 27'h0000000;
\208 [75] = 27'h0000000;
\208 [76] = 27'h0000000;
\208 [77] = 27'h0000000;
\208 [78] = 27'h0000000;
\208 [79] = 27'h0000000;
\208 [80] = 27'h0000000;
\208 [81] = 27'h0000000;
\208 [82] = 27'h0000000;
\208 [83] = 27'h0000000;
\208 [84] = 27'h0000000;
\208 [85] = 27'h0000000;
\208 [86] = 27'h0000000;
\208 [87] = 27'h0000000;
\208 [88] = 27'h0000000;
\208 [89] = 27'h0000000;
\208 [90] = 27'h0000000;
\208 [91] = 27'h0000000;
\208 [92] = 27'h0000000;
\208 [93] = 27'h0000000;
\208 [94] = 27'h0000000;
\208 [95] = 27'h0000000;
\208 [96] = 27'h0000000;
\208 [97] = 27'h0000000;
\208 [98] = 27'h0000000;
\208 [99] = 27'h0000000;
\208 [100] = 27'h0000000;
\208 [101] = 27'h0000000;
\208 [102] = 27'h0000000;
\208 [103] = 27'h0000000;
\208 [104] = 27'h0000000;
\208 [105] = 27'h0000000;
\208 [106] = 27'h0000000;
\208 [107] = 27'h0000000;
\208 [108] = 27'h0000000;
\208 [109] = 27'h0000000;
\208 [110] = 27'h0000000;
\208 [111] = 27'h0000000;
\208 [112] = 27'h0000000;
\208 [113] = 27'h0000000;
\208 [114] = 27'h0000000;
\208 [115] = 27'h0000000;
\208 [116] = 27'h0000000;
\208 [117] = 27'h0000000;
\208 [118] = 27'h0000000;
\208 [119] = 27'h0000000;
\208 [120] = 27'h0000000;
\208 [121] = 27'h0000000;
\208 [122] = 27'h0000000;
\208 [123] = 27'h0000000;
\208 [124] = 27'h0000000;
\208 [125] = 27'h0000000;
\208 [126] = 27'h0000000;
\208 [127] = 27'h0000000;
\208 [128] = 27'h0000000;
\208 [129] = 27'h0000000;
\208 [130] = 27'h0000000;
\208 [131] = 27'h0000000;
\208 [132] = 27'h0000000;
\208 [133] = 27'h0000000;
\208 [134] = 27'h0000000;
\208 [135] = 27'h0000000;
\208 [136] = 27'h0000000;
\208 [137] = 27'h0000000;
\208 [138] = 27'h0000000;
\208 [139] = 27'h0000000;
\208 [140] = 27'h0000000;
\208 [141] = 27'h0000000;
\208 [142] = 27'h0000000;
\208 [143] = 27'h0000000;
\208 [144] = 27'h0000000;
\208 [145] = 27'h0000000;
\208 [146] = 27'h0000000;
\208 [147] = 27'h0000000;
\208 [148] = 27'h0000000;
\208 [149] = 27'h0000000;
\208 [150] = 27'h0000000;
\208 [151] = 27'h0000000;
\208 [152] = 27'h0000000;
\208 [153] = 27'h0000000;
\208 [154] = 27'h0000000;
\208 [155] = 27'h0000000;
\208 [156] = 27'h0000000;
\208 [157] = 27'h0000000;
\208 [158] = 27'h0000000;
\208 [159] = 27'h0000000;
\208 [160] = 27'h0000000;
\208 [161] = 27'h0000000;
\208 [162] = 27'h0000000;
\208 [163] = 27'h0000000;
\208 [164] = 27'h0000000;
\208 [165] = 27'h0000000;
\208 [166] = 27'h0000000;
\208 [167] = 27'h0000000;
\208 [168] = 27'h0000000;
\208 [169] = 27'h0000000;
\208 [170] = 27'h0000000;
\208 [171] = 27'h0000000;
\208 [172] = 27'h0000000;
\208 [173] = 27'h0000000;
\208 [174] = 27'h0000000;
\208 [175] = 27'h0000000;
\208 [176] = 27'h0000000;
\208 [177] = 27'h0000000;
\208 [178] = 27'h0000000;
\208 [179] = 27'h0000000;
\208 [180] = 27'h0000000;
\208 [181] = 27'h0000000;
\208 [182] = 27'h0000000;
\208 [183] = 27'h0000000;
\208 [184] = 27'h0000000;
\208 [185] = 27'h0000000;
\208 [186] = 27'h0000000;
\208 [187] = 27'h0000000;
\208 [188] = 27'h0000000;
\208 [189] = 27'h0000000;
\208 [190] = 27'h0000000;
\208 [191] = 27'h0000000;
\208 [192] = 27'h0000000;
\208 [193] = 27'h0000000;
\208 [194] = 27'h0000000;
\208 [195] = 27'h0000000;
\208 [196] = 27'h0000000;
\208 [197] = 27'h0000000;
\208 [198] = 27'h0000000;
\208 [199] = 27'h0000000;
\208 [200] = 27'h0000000;
\208 [201] = 27'h0000000;
\208 [202] = 27'h0000000;
\208 [203] = 27'h0000000;
\208 [204] = 27'h0000000;
\208 [205] = 27'h0000000;
\208 [206] = 27'h0000000;
\208 [207] = 27'h0000000;
\208 [208] = 27'h0000000;
\208 [209] = 27'h0000000;
\208 [210] = 27'h0000000;
\208 [211] = 27'h0000000;
\208 [212] = 27'h0000000;
\208 [213] = 27'h0000000;
\208 [214] = 27'h0000000;
\208 [215] = 27'h0000000;
\208 [216] = 27'h0000000;
\208 [217] = 27'h0000000;
\208 [218] = 27'h0000000;
\208 [219] = 27'h0000000;
\208 [220] = 27'h0000000;
\208 [221] = 27'h0000000;
\208 [222] = 27'h0000000;
\208 [223] = 27'h0000000;
\208 [224] = 27'h0000000;
\208 [225] = 27'h0000000;
\208 [226] = 27'h0000000;
\208 [227] = 27'h0000000;
\208 [228] = 27'h0000000;
\208 [229] = 27'h0000000;
\208 [230] = 27'h0000000;
\208 [231] = 27'h0000000;
\208 [232] = 27'h0000000;
\208 [233] = 27'h0000000;
\208 [234] = 27'h0000000;
\208 [235] = 27'h0000000;
\208 [236] = 27'h0000000;
\208 [237] = 27'h0000000;
\208 [238] = 27'h0000000;
\208 [239] = 27'h0000000;
\208 [240] = 27'h0000000;
\208 [241] = 27'h0000000;
\208 [242] = 27'h0000000;
\208 [243] = 27'h0000000;
\208 [244] = 27'h0000000;
\208 [245] = 27'h0000000;
\208 [246] = 27'h0000000;
\208 [247] = 27'h0000000;
\208 [248] = 27'h0000000;
\208 [249] = 27'h0000000;
\208 [250] = 27'h0000000;
\208 [251] = 27'h0000000;
\208 [252] = 27'h0000000;
\208 [253] = 27'h0000000;
\208 [254] = 27'h0000000;
\208 [255] = 27'h0000000;
\208 [256] = 27'h0000000;
\208 [257] = 27'h0000000;
\208 [258] = 27'h0000000;
\208 [259] = 27'h0000000;
\208 [260] = 27'h0000000;
\208 [261] = 27'h0000000;
\208 [262] = 27'h0000000;
\208 [263] = 27'h0000000;
\208 [264] = 27'h0000000;
\208 [265] = 27'h0000000;
\208 [266] = 27'h0000000;
\208 [267] = 27'h0000000;
\208 [268] = 27'h0000000;
\208 [269] = 27'h0000000;
\208 [270] = 27'h0000000;
\208 [271] = 27'h0000000;
\208 [272] = 27'h0000000;
\208 [273] = 27'h0000000;
\208 [274] = 27'h0000000;
\208 [275] = 27'h0000000;
\208 [276] = 27'h0000000;
\208 [277] = 27'h0000000;
\208 [278] = 27'h0000000;
\208 [279] = 27'h0000000;
\208 [280] = 27'h0000000;
\208 [281] = 27'h0000000;
\208 [282] = 27'h0000000;
\208 [283] = 27'h0000000;
\208 [284] = 27'h0000000;
\208 [285] = 27'h0000000;
\208 [286] = 27'h0000000;
\208 [287] = 27'h0000000;
\208 [288] = 27'h0000000;
\208 [289] = 27'h0000000;
\208 [290] = 27'h0000000;
\208 [291] = 27'h0000000;
\208 [292] = 27'h0000000;
\208 [293] = 27'h0000000;
\208 [294] = 27'h0000000;
\208 [295] = 27'h0000000;
\208 [296] = 27'h0000000;
\208 [297] = 27'h0000000;
\208 [298] = 27'h0000000;
\208 [299] = 27'h0000000;
\208 [300] = 27'h0000000;
\208 [301] = 27'h0000000;
\208 [302] = 27'h0000000;
\208 [303] = 27'h0000000;
\208 [304] = 27'h0000000;
\208 [305] = 27'h0000000;
\208 [306] = 27'h0000000;
\208 [307] = 27'h0000000;
\208 [308] = 27'h0000000;
\208 [309] = 27'h0000000;
\208 [310] = 27'h0000000;
\208 [311] = 27'h0000000;
\208 [312] = 27'h0000000;
\208 [313] = 27'h0000000;
\208 [314] = 27'h0000000;
\208 [315] = 27'h0000000;
\208 [316] = 27'h0000000;
\208 [317] = 27'h0000000;
\208 [318] = 27'h0000000;
\208 [319] = 27'h0000000;
\208 [320] = 27'h0000000;
\208 [321] = 27'h0000000;
\208 [322] = 27'h0000000;
\208 [323] = 27'h0000000;
\208 [324] = 27'h0000000;
\208 [325] = 27'h0000000;
\208 [326] = 27'h0000000;
\208 [327] = 27'h0000000;
\208 [328] = 27'h0000000;
\208 [329] = 27'h0000000;
\208 [330] = 27'h0000000;
\208 [331] = 27'h0000000;
\208 [332] = 27'h0000000;
\208 [333] = 27'h0000000;
\208 [334] = 27'h0000000;
\208 [335] = 27'h0000000;
\208 [336] = 27'h0000000;
\208 [337] = 27'h0000000;
\208 [338] = 27'h0000000;
\208 [339] = 27'h0000000;
\208 [340] = 27'h0000000;
\208 [341] = 27'h0000000;
\208 [342] = 27'h0000000;
\208 [343] = 27'h0000000;
\208 [344] = 27'h0000000;
\208 [345] = 27'h0000000;
\208 [346] = 27'h0000000;
\208 [347] = 27'h0000000;
\208 [348] = 27'h0000000;
\208 [349] = 27'h0000000;
\208 [350] = 27'h0000000;
\208 [351] = 27'h0000000;
\208 [352] = 27'h0000000;
\208 [353] = 27'h0000000;
\208 [354] = 27'h0000000;
\208 [355] = 27'h0000000;
\208 [356] = 27'h0000000;
\208 [357] = 27'h0000000;
\208 [358] = 27'h0000000;
\208 [359] = 27'h0000000;
\208 [360] = 27'h0000000;
\208 [361] = 27'h0000000;
\208 [362] = 27'h0000000;
\208 [363] = 27'h0000000;
\208 [364] = 27'h0000000;
\208 [365] = 27'h0000000;
\208 [366] = 27'h0000000;
\208 [367] = 27'h0000000;
\208 [368] = 27'h0000000;
\208 [369] = 27'h0000000;
\208 [370] = 27'h0000000;
\208 [371] = 27'h0000000;
\208 [372] = 27'h0000000;
\208 [373] = 27'h0000000;
\208 [374] = 27'h0000000;
\208 [375] = 27'h0000000;
\208 [376] = 27'h0000000;
\208 [377] = 27'h0000000;
\208 [378] = 27'h0000000;
\208 [379] = 27'h0000000;
\208 [380] = 27'h0000000;
\208 [381] = 27'h0000000;
\208 [382] = 27'h0000000;
\208 [383] = 27'h0000000;
\208 [384] = 27'h0000000;
\208 [385] = 27'h0000000;
\208 [386] = 27'h0000000;
\208 [387] = 27'h0000000;
\208 [388] = 27'h0000000;
\208 [389] = 27'h0000000;
\208 [390] = 27'h0000000;
\208 [391] = 27'h0000000;
\208 [392] = 27'h0000000;
\208 [393] = 27'h0000000;
\208 [394] = 27'h0000000;
\208 [395] = 27'h0000000;
\208 [396] = 27'h0000000;
\208 [397] = 27'h0000000;
\208 [398] = 27'h0000000;
\208 [399] = 27'h0000000;
\208 [400] = 27'h0000000;
\208 [401] = 27'h0000000;
\208 [402] = 27'h0000000;
\208 [403] = 27'h0000000;
\208 [404] = 27'h0000000;
\208 [405] = 27'h0000000;
\208 [406] = 27'h0000000;
\208 [407] = 27'h0000000;
\208 [408] = 27'h0000000;
\208 [409] = 27'h0000000;
\208 [410] = 27'h0000000;
\208 [411] = 27'h0000000;
\208 [412] = 27'h0000000;
\208 [413] = 27'h0000000;
\208 [414] = 27'h0000000;
\208 [415] = 27'h0000000;
\208 [416] = 27'h0000000;
\208 [417] = 27'h0000000;
\208 [418] = 27'h0000000;
\208 [419] = 27'h0000000;
\208 [420] = 27'h0000000;
\208 [421] = 27'h0000000;
\208 [422] = 27'h0000000;
\208 [423] = 27'h0000000;
\208 [424] = 27'h0000000;
\208 [425] = 27'h0000000;
\208 [426] = 27'h0000000;
\208 [427] = 27'h0000000;
\208 [428] = 27'h0000000;
\208 [429] = 27'h0000000;
\208 [430] = 27'h0000000;
\208 [431] = 27'h0000000;
\208 [432] = 27'h0000000;
\208 [433] = 27'h0000000;
\208 [434] = 27'h0000000;
\208 [435] = 27'h0000000;
\208 [436] = 27'h0000000;
\208 [437] = 27'h0000000;
\208 [438] = 27'h0000000;
\208 [439] = 27'h0000000;
\208 [440] = 27'h0000000;
\208 [441] = 27'h0000000;
\208 [442] = 27'h0000000;
\208 [443] = 27'h0000000;
\208 [444] = 27'h0000000;
\208 [445] = 27'h0000000;
\208 [446] = 27'h0000000;
\208 [447] = 27'h0000000;
\208 [448] = 27'h0000000;
\208 [449] = 27'h0000000;
\208 [450] = 27'h0000000;
\208 [451] = 27'h0000000;
\208 [452] = 27'h0000000;
\208 [453] = 27'h0000000;
\208 [454] = 27'h0000000;
\208 [455] = 27'h0000000;
\208 [456] = 27'h0000000;
\208 [457] = 27'h0000000;
\208 [458] = 27'h0000000;
\208 [459] = 27'h0000000;
\208 [460] = 27'h0000000;
\208 [461] = 27'h0000000;
\208 [462] = 27'h0000000;
\208 [463] = 27'h0000000;
\208 [464] = 27'h0000000;
\208 [465] = 27'h0000000;
\208 [466] = 27'h0000000;
\208 [467] = 27'h0000000;
\208 [468] = 27'h0000000;
\208 [469] = 27'h0000000;
\208 [470] = 27'h0000000;
\208 [471] = 27'h0000000;
\208 [472] = 27'h0000000;
\208 [473] = 27'h0000000;
\208 [474] = 27'h0000000;
\208 [475] = 27'h0000000;
\208 [476] = 27'h0000000;
\208 [477] = 27'h0000000;
\208 [478] = 27'h0000000;
\208 [479] = 27'h0000000;
\208 [480] = 27'h0000000;
\208 [481] = 27'h0000000;
\208 [482] = 27'h0000000;
\208 [483] = 27'h0000000;
\208 [484] = 27'h0000000;
\208 [485] = 27'h0000000;
\208 [486] = 27'h0000000;
\208 [487] = 27'h0000000;
\208 [488] = 27'h0000000;
\208 [489] = 27'h0000000;
\208 [490] = 27'h0000000;
\208 [491] = 27'h0000000;
\208 [492] = 27'h0000000;
\208 [493] = 27'h0000000;
\208 [494] = 27'h0000000;
\208 [495] = 27'h0000000;
\208 [496] = 27'h0000000;
\208 [497] = 27'h0000000;
\208 [498] = 27'h0000000;
\208 [499] = 27'h0000000;
\208 [500] = 27'h0000000;
\208 [501] = 27'h0000000;
\208 [502] = 27'h0000000;
\208 [503] = 27'h0000000;
\208 [504] = 27'h0000000;
\208 [505] = 27'h0000000;
\208 [506] = 27'h0000000;
\208 [507] = 27'h0000000;
\208 [508] = 27'h0000000;
\208 [509] = 27'h0000000;
\208 [510] = 27'h0000000;
\208 [511] = 27'h0000000;
end
always @(posedge clk) begin
\208 [_0_] <= 27'h0000000;
end
assign _4_ = \208 [_5_];
assign out_blank = 1'hz;
assign out_hsync = 1'hz;
assign out_vsync = 1'hz;
assign out_red = 8'hzz;
assign out_green = _1_;
assign out_blue = _2_;
endmodule
module pixel_processing(clk, in_blank, in_hsync, in_vsync, in_red, in_green, in_blue, is_interlaced, is_second_field, audio_channel, audio_de, audio_sample, switches, out_blank, out_hsync, out_vsync, out_red, out_green, out_blue);
input [2:0] audio_channel;
input audio_de;
input [23:0] audio_sample;
input clk;
input in_blank;
input [7:0] in_blue;
input [7:0] in_green;
input in_hsync;
input [7:0] in_red;
input in_vsync;
input is_interlaced;
input is_second_field;
output out_blank;
output [7:0] out_blue;
output [7:0] out_green;
output out_hsync;
output [7:0] out_red;
output out_vsync;
input [7:0] switches;
assign out_blank = 1'hz;
assign out_hsync = 1'hz;
assign out_vsync = 1'hz;
assign out_red = 8'hzz;
assign out_green = 8'hzz;
assign out_blue = 8'hzz;
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 1
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2013.4" *)
(* CHECK_LICENSE_TYPE = "zynq_1_auto_pc_15,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "zynq_1_auto_pc_15,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zynq_1_auto_pc_15 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module fetch(IR_load_mux,new_IR_multi,equ,pr2_IR ,pr3_IR ,pr4_IR, pr5_IR,fromPipe2_PCim, fromPipe2_970, fromPipe3RFOut, fromPipe3PCInc, fromPipe4_Aluout, fromPipe5Mem, PCWrite, PCOut, IROut, incPCOut, clk, reset);
output [15:0] PCOut, IROut, incPCOut;
input [15:0]new_IR_multi;
wire [15:0] next_IR;//read from instruction memory
input IR_load_mux;
input [15:0] fromPipe2_PCim, fromPipe2_970, fromPipe3RFOut, fromPipe3PCInc, fromPipe4_Aluout, fromPipe5Mem;
input [15:0] pr2_IR ,pr3_IR ,pr4_IR, pr5_IR;
wire [ 2:0] fromForwarding;
input PCWrite, clk, reset;
input equ;
wire [15:0] PCWriteWire;
pc_forwarding f_u(.clk(clk),.equ(equ),.pr2_IR(pr2_IR),.pr3_IR(pr3_IR),.pr4_IR(pr4_IR),.pr5_IR(pr5_IR),.pc_mux_select(fromForwarding)) ;
mux16x8 PCWriteSelect(.data0(incPCOut), .data1(fromPipe3RFOut), .data2(fromPipe5Mem), .data3(fromPipe2_PCim), .data4(fromPipe3PCInc), .data5(fromPipe2_970), .data6(fromPipe4_Aluout), .data7(16'b0), .selectInput(fromForwarding), .out(PCWriteWire));
register16 PCReg(.clk(clk), .out(PCOut), .in(PCWriteWire), .write(PCWrite), .reset(reset));
plus_one PlusOne(.in(PCOut), .out(incPCOut));
instr_mem InstructionMemory(.readAdd(PCOut), .out(next_IR));
mux16x2 IR_write_select(.data0(next_IR), .data1(new_IR_multi), .selectInput(IR_load_mux), .out(IROut));
endmodule
module pc_forwarding(clk,equ,pr2_IR,pr3_IR,pr4_IR,pr5_IR,pc_mux_select);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
parameter rb=3'd1;
parameter c=3'd2;
parameter m= 3'd3;
parameter one = 3'd4;
parameter h = 3'd5;
parameter a = 3'd6;
output reg [2:0] pc_mux_select;
input [15:0] pr2_IR,pr3_IR,pr4_IR,pr5_IR;
input equ,clk;
wire [5:0] op2,op3,op4,op5;
wire[2:0] pr2RA,pr2RB,pr4RC,pr5RA;
assign op2={pr2_IR[15:12],pr2_IR[1:0]};
assign op3={pr3_IR[15:12],pr3_IR[1:0]};
assign op4={pr4_IR[15:12],pr4_IR[1:0]};
assign op5={pr5_IR[15:12],pr5_IR[1:0]};
assign pr2RA = pr2_IR[11:9];
assign pr2RB = pr2_IR[8:6];
assign pr4RC = pr2_IR[5:3];
assign pr5RA = pr5_IR[11:9];
always @(negedge clk)
begin
if((op5[5:2]==LW||op5[5:2]==LM)&&pr5RA==3'b111)
pc_mux_select=c;//from mem
else if(op2[5:2]==LHI&&pr2RA==3'b111)
pc_mux_select=h;//970 from pr2
else if((op4==ADD||op4==NDU||op4==ADC||op4==ADZ||op4==NDC||op4==NDC||op4==NDZ)&&(pr4RC==3'b111))
pc_mux_select=a;//ALU_out in pr4
else if(op4[5:2]==ADI&&pr2RB==3'b111)
pc_mux_select=a;//ALU_out in pr4
else if(equ==1&&op3[5:2]==BEQ)
pc_mux_select=one;//pc+Im6, in pr3
else if(op3[5:2]==JLR)
pc_mux_select=rb;//from RFout2 of pr3
else if(op2[5:2]==JAL)
pc_mux_select=m;//PC+Im6 , in pr2
else
pc_mux_select=0;
end//always
endmodule
|
module opicorv32_control_wrap (
irq,
decoded_imm_uj,
decoded_imm,
decoded_rs2,
decoded_rs1,
decoded_rd,
pcpi_int_rd,
pcpi_int_wr,
pcpi_int_wait,
pcpi_int_ready,
mem_done,
mem_rdata_word,
is_lui_auipc_jal,
is_lb_lh_lw_lbu_lhu,
is_slli_srli_srai,
is_jalr_addi_slti_sltiu_xori_ori_andi,
is_sb_sh_sw,
is_sll_srl_sra,
is_lui_auipc_jal_jalr_addi_add,
is_slti_blt_slt,
is_sltiu_bltu_sltu,
is_beq_bne_blt_bge_bltu_bgeu,
is_lbu_lhu_lw,
is_alu_reg_imm,
is_alu_reg_reg,
is_compare,
is_rdcycle_rdcycleh_rdinstr_rdinstrh,
instr_lui,
instr_auipc,
instr_jal,
instr_jalr,
instr_beq,
instr_bne,
instr_blt,
instr_bge,
instr_bltu,
instr_bgeu,
instr_lb,
instr_lh,
instr_lw,
instr_lbu,
instr_lhu,
instr_sb,
instr_sh,
instr_sw,
instr_addi,
instr_slti,
instr_sltiu,
instr_xori,
instr_ori,
instr_andi,
instr_slli,
instr_srli,
instr_srai,
instr_add,
instr_sub,
instr_sll,
instr_slt,
instr_sltu,
instr_xor,
instr_srl,
instr_sra,
instr_or,
instr_and,
instr_rdcycle,
instr_rdcycleh,
instr_rdinstr,
instr_rdinstrh,
instr_getq,
instr_setq,
instr_retirq,
instr_maskirq,
instr_waitirq,
instr_timer,
instr_trap,
resetn,
clk,
next_pc,
reg_op1,
reg_op2,
trap,
mem_do_rinst,
mem_do_wdata,
mem_do_rdata,
mem_wordsize,
mem_do_prefetch,
pcpi_valid,
decoder_trigger,
decoder_trigger_q,
decoder_pseudo_trigger,
eoi,
ascii_state
);
input [31:0] irq;
input [31:0] decoded_imm_uj;
input [31:0] decoded_imm;
input [5:0] decoded_rs2;
input [5:0] decoded_rs1;
input [5:0] decoded_rd;
input [31:0] pcpi_int_rd;
input pcpi_int_wr;
input pcpi_int_wait;
input pcpi_int_ready;
input mem_done;
input [31:0] mem_rdata_word;
input is_lui_auipc_jal;
input is_lb_lh_lw_lbu_lhu;
input is_slli_srli_srai;
input is_jalr_addi_slti_sltiu_xori_ori_andi;
input is_sb_sh_sw;
input is_sll_srl_sra;
input is_lui_auipc_jal_jalr_addi_add;
input is_slti_blt_slt;
input is_sltiu_bltu_sltu;
input is_beq_bne_blt_bge_bltu_bgeu;
input is_lbu_lhu_lw;
input is_alu_reg_imm;
input is_alu_reg_reg;
input is_compare;
input is_rdcycle_rdcycleh_rdinstr_rdinstrh;
input instr_lui;
input instr_auipc;
input instr_jal;
input instr_jalr;
input instr_beq;
input instr_bne;
input instr_blt;
input instr_bge;
input instr_bltu;
input instr_bgeu;
input instr_lb;
input instr_lh;
input instr_lw;
input instr_lbu;
input instr_lhu;
input instr_sb;
input instr_sh;
input instr_sw;
input instr_addi;
input instr_slti;
input instr_sltiu;
input instr_xori;
input instr_ori;
input instr_andi;
input instr_slli;
input instr_srli;
input instr_srai;
input instr_add;
input instr_sub;
input instr_sll;
input instr_slt;
input instr_sltu;
input instr_xor;
input instr_srl;
input instr_sra;
input instr_or;
input instr_and;
input instr_rdcycle;
input instr_rdcycleh;
input instr_rdinstr;
input instr_rdinstrh;
input instr_getq;
input instr_setq;
input instr_retirq;
input instr_maskirq;
input instr_waitirq;
input instr_timer;
input instr_trap;
input resetn;
input clk;
output [31:0] next_pc;
output [31:0] reg_op1;
output [31:0] reg_op2;
output trap;
output mem_do_rinst;
output mem_do_wdata;
output mem_do_rdata;
output [1:0] mem_wordsize;
output mem_do_prefetch;
output pcpi_valid;
output decoder_trigger;
output decoder_trigger_q;
output decoder_pseudo_trigger;
output [31:0] eoi;
output [127:0] ascii_state;
/* signal declarations */
wire [127:0] _5562;
wire [127:0] _5547;
wire [127:0] compare_ascii_state;
wire [127:0] _5564;
wire [31:0] _5565;
wire [31:0] _5548;
wire [31:0] compare_eoi;
wire [31:0] _5567;
wire _5568;
wire _5549;
wire compare_decoder_pseudo_trigger;
wire _5570;
wire _5571;
wire _5550;
wire compare_decoder_trigger_q;
wire _5573;
wire _5574;
wire _5551;
wire compare_decoder_trigger;
wire _5576;
wire _5577;
wire _5552;
wire compare_pcpi_valid;
wire _5579;
wire _5580;
wire _5553;
wire compare_mem_do_prefetch;
wire _5582;
wire [1:0] _5583;
wire [1:0] _5554;
wire [1:0] compare_mem_wordsize;
wire [1:0] _5585;
wire _5586;
wire _5555;
wire compare_mem_do_rdata;
wire _5588;
wire _5589;
wire _5556;
wire compare_mem_do_wdata;
wire _5591;
wire _5592;
wire _5557;
wire compare_mem_do_rinst;
wire _5594;
wire _5595;
wire _5558;
wire compare_trap;
wire _5597;
wire [31:0] _5598;
wire [31:0] _5559;
wire [31:0] compare_reg_op2;
wire [31:0] _5600;
wire [31:0] _5601;
wire [31:0] _5560;
wire [31:0] compare_reg_op1;
wire [31:0] _5603;
wire [266:0] _5542;
wire [31:0] _5604;
wire [14:0] _5544;
wire [47:0] _5543;
wire [266:0] _5546;
wire [31:0] _5561;
wire [31:0] compare_next_pc;
wire [31:0] _5606;
/* logic */
assign _5562 = _5542[266:139];
assign _5547 = _5546[266:139];
assign compare_ascii_state = _5547 ^ _5562;
assign _5564 = compare_ascii_state ^ _5562;
assign _5565 = _5542[138:107];
assign _5548 = _5546[138:107];
assign compare_eoi = _5548 ^ _5565;
assign _5567 = compare_eoi ^ _5565;
assign _5568 = _5542[106:106];
assign _5549 = _5546[106:106];
assign compare_decoder_pseudo_trigger = _5549 ^ _5568;
assign _5570 = compare_decoder_pseudo_trigger ^ _5568;
assign _5571 = _5542[105:105];
assign _5550 = _5546[105:105];
assign compare_decoder_trigger_q = _5550 ^ _5571;
assign _5573 = compare_decoder_trigger_q ^ _5571;
assign _5574 = _5542[104:104];
assign _5551 = _5546[104:104];
assign compare_decoder_trigger = _5551 ^ _5574;
assign _5576 = compare_decoder_trigger ^ _5574;
assign _5577 = _5542[103:103];
assign _5552 = _5546[103:103];
assign compare_pcpi_valid = _5552 ^ _5577;
assign _5579 = compare_pcpi_valid ^ _5577;
assign _5580 = _5542[102:102];
assign _5553 = _5546[102:102];
assign compare_mem_do_prefetch = _5553 ^ _5580;
assign _5582 = compare_mem_do_prefetch ^ _5580;
assign _5583 = _5542[101:100];
assign _5554 = _5546[101:100];
assign compare_mem_wordsize = _5554 ^ _5583;
assign _5585 = compare_mem_wordsize ^ _5583;
assign _5586 = _5542[99:99];
assign _5555 = _5546[99:99];
assign compare_mem_do_rdata = _5555 ^ _5586;
assign _5588 = compare_mem_do_rdata ^ _5586;
assign _5589 = _5542[98:98];
assign _5556 = _5546[98:98];
assign compare_mem_do_wdata = _5556 ^ _5589;
assign _5591 = compare_mem_do_wdata ^ _5589;
assign _5592 = _5542[97:97];
assign _5557 = _5546[97:97];
assign compare_mem_do_rinst = _5557 ^ _5592;
assign _5594 = compare_mem_do_rinst ^ _5592;
assign _5595 = _5542[96:96];
assign _5558 = _5546[96:96];
assign compare_trap = _5558 ^ _5595;
assign _5597 = compare_trap ^ _5595;
assign _5598 = _5542[95:64];
assign _5559 = _5546[95:64];
assign compare_reg_op2 = _5559 ^ _5598;
assign _5600 = compare_reg_op2 ^ _5598;
assign _5601 = _5542[63:32];
assign _5560 = _5546[63:32];
assign compare_reg_op1 = _5560 ^ _5601;
assign _5603 = compare_reg_op1 ^ _5601;
picorv32_control
#( .ENABLE_COUNTERS(1), .ENABLE_REGS_16_31(1), .ENABLE_REGS_DUALPORT(1), .LATCHED_MEM_RDATA(0), .ENABLE_PCPI(0), .ENABLE_MUL(1), .ENABLE_IRQ(1), .ENABLE_IRQ_QREGS(1), .ENABLE_IRQ_TIMER(1), .MASKED_IRQ(0), .LATCHED_IRQ(-1), .PROGADDR_RESET(0), .PROGADDR_IRQ(16), .irqregs_offset(32), .regfile_size(36), .regindex_bits(6) )
the_picorv32_control
( .instr_lui(instr_lui), .instr_auipc(instr_auipc), .instr_jal(instr_jal), .instr_jalr(instr_jalr), .instr_beq(instr_beq), .instr_bne(instr_bne), .instr_blt(instr_blt), .instr_bge(instr_bge), .instr_bltu(instr_bltu), .instr_bgeu(instr_bgeu), .instr_lb(instr_lb), .instr_lh(instr_lh), .instr_lw(instr_lw), .instr_lbu(instr_lbu), .instr_lhu(instr_lhu), .instr_sb(instr_sb), .instr_sh(instr_sh), .instr_sw(instr_sw), .instr_addi(instr_addi), .instr_slti(instr_slti), .instr_sltiu(instr_sltiu), .instr_xori(instr_xori), .instr_ori(instr_ori), .instr_andi(instr_andi), .instr_slli(instr_slli), .instr_srli(instr_srli), .instr_srai(instr_srai), .instr_add(instr_add), .instr_sub(instr_sub), .instr_sll(instr_sll), .instr_slt(instr_slt), .instr_sltu(instr_sltu), .instr_xor(instr_xor), .instr_srl(instr_srl), .instr_sra(instr_sra), .instr_or(instr_or), .instr_and(instr_and), .instr_rdcycle(instr_rdcycle), .instr_rdcycleh(instr_rdcycleh), .instr_rdinstr(instr_rdinstr), .instr_rdinstrh(instr_rdinstrh), .instr_getq(instr_getq), .instr_setq(instr_setq), .instr_retirq(instr_retirq), .instr_maskirq(instr_maskirq), .instr_waitirq(instr_waitirq), .instr_timer(instr_timer), .instr_trap(instr_trap), .is_lui_auipc_jal(is_lui_auipc_jal), .is_lb_lh_lw_lbu_lhu(is_lb_lh_lw_lbu_lhu), .is_slli_srli_srai(is_slli_srli_srai), .is_jalr_addi_slti_sltiu_xori_ori_andi(is_jalr_addi_slti_sltiu_xori_ori_andi), .is_sb_sh_sw(is_sb_sh_sw), .is_sll_srl_sra(is_sll_srl_sra), .is_lui_auipc_jal_jalr_addi_add(is_lui_auipc_jal_jalr_addi_add), .is_slti_blt_slt(is_slti_blt_slt), .is_sltiu_bltu_sltu(is_sltiu_bltu_sltu), .is_beq_bne_blt_bge_bltu_bgeu(is_beq_bne_blt_bge_bltu_bgeu), .is_lbu_lhu_lw(is_lbu_lhu_lw), .is_alu_reg_imm(is_alu_reg_imm), .is_alu_reg_reg(is_alu_reg_reg), .is_compare(is_compare), .is_rdcycle_rdcycleh_rdinstr_rdinstrh(is_rdcycle_rdcycleh_rdinstr_rdinstrh), .clk(clk), .resetn(resetn), .mem_rdata_word(mem_rdata_word), .mem_done(mem_done), .pcpi_int_ready(pcpi_int_ready), .pcpi_int_wait(pcpi_int_wait), .pcpi_int_wr(pcpi_int_wr), .pcpi_int_rd(pcpi_int_rd), .decoded_rd(decoded_rd), .decoded_rs1(decoded_rs1), .decoded_rs2(decoded_rs2), .decoded_imm(decoded_imm), .decoded_imm_uj(decoded_imm_uj), .irq(irq), .ascii_state(_5542[266:139]), .eoi(_5542[138:107]), .decoder_pseudo_trigger(_5542[106:106]), .decoder_trigger_q(_5542[105:105]), .decoder_trigger(_5542[104:104]), .pcpi_valid(_5542[103:103]), .mem_do_prefetch(_5542[102:102]), .mem_wordsize(_5542[101:100]), .mem_do_rdata(_5542[99:99]), .mem_do_wdata(_5542[98:98]), .mem_do_rinst(_5542[97:97]), .trap(_5542[96:96]), .reg_op2(_5542[95:64]), .reg_op1(_5542[63:32]), .next_pc(_5542[31:0]) );
assign _5604 = _5542[31:0];
assign _5544 = { is_rdcycle_rdcycleh_rdinstr_rdinstrh, is_compare, is_alu_reg_reg, is_alu_reg_imm, is_lbu_lhu_lw, is_beq_bne_blt_bge_bltu_bgeu, is_sltiu_bltu_sltu, is_slti_blt_slt, is_lui_auipc_jal_jalr_addi_add, is_sll_srl_sra, is_sb_sh_sw, is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai, is_lb_lh_lw_lbu_lhu, is_lui_auipc_jal };
assign _5543 = { instr_trap, instr_timer, instr_waitirq, instr_maskirq, instr_retirq, instr_setq, instr_getq, instr_rdinstrh, instr_rdinstr, instr_rdcycleh, instr_rdcycle, instr_and, instr_or, instr_sra, instr_srl, instr_xor, instr_sltu, instr_slt, instr_sll, instr_sub, instr_add, instr_srai, instr_srli, instr_slli, instr_andi, instr_ori, instr_xori, instr_sltiu, instr_slti, instr_addi, instr_sw, instr_sh, instr_sb, instr_lhu, instr_lbu, instr_lw, instr_lh, instr_lb, instr_bgeu, instr_bltu, instr_bge, instr_blt, instr_bne, instr_beq, instr_jalr, instr_jal, instr_auipc, instr_lui };
opicorv32_control
the_opicorv32_control
( .clk(clk), .resetn(resetn), .instr(_5543), .is(_5544), .mem_rdata_word(mem_rdata_word), .mem_done(mem_done), .pcpi_int_ready(pcpi_int_ready), .pcpi_int_wait(pcpi_int_wait), .pcpi_int_wr(pcpi_int_wr), .pcpi_int_rd(pcpi_int_rd), .decoded_rd(decoded_rd), .decoded_rs1(decoded_rs1), .decoded_rs2(decoded_rs2), .decoded_imm(decoded_imm), .decoded_imm_uj(decoded_imm_uj), .irq(irq), .ascii_state(_5546[266:139]), .eoi(_5546[138:107]), .decoder_pseudo_trigger(_5546[106:106]), .decoder_trigger_q(_5546[105:105]), .decoder_trigger(_5546[104:104]), .pcpi_valid(_5546[103:103]), .mem_do_prefetch(_5546[102:102]), .mem_wordsize(_5546[101:100]), .mem_do_rdata(_5546[99:99]), .mem_do_wdata(_5546[98:98]), .mem_do_rinst(_5546[97:97]), .trap(_5546[96:96]), .reg_op2(_5546[95:64]), .reg_op1(_5546[63:32]), .next_pc(_5546[31:0]) );
assign _5561 = _5546[31:0];
assign compare_next_pc = _5561 ^ _5604;
assign _5606 = compare_next_pc ^ _5604;
/* aliases */
/* output assignments */
assign next_pc = _5606;
assign reg_op1 = _5603;
assign reg_op2 = _5600;
assign trap = _5597;
assign mem_do_rinst = _5594;
assign mem_do_wdata = _5591;
assign mem_do_rdata = _5588;
assign mem_wordsize = _5585;
assign mem_do_prefetch = _5582;
assign pcpi_valid = _5579;
assign decoder_trigger = _5576;
assign decoder_trigger_q = _5573;
assign decoder_pseudo_trigger = _5570;
assign eoi = _5567;
assign ascii_state = _5564;
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:42:40 06/01/2015
// Design Name:
// Module Name: scancode_to_speccy
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module scancode_to_speccy (
input wire clk, // el mismo clk de ps/2
input wire rst,
input wire scan_received,
input wire [7:0] scan,
input wire extended,
input wire released,
input wire kbclean,
//------------------------
input wire [7:0] sp_row,
output wire [4:0] sp_col,
output wire user_reset,
output wire master_reset,
output wire user_nmi,
output wire joyup,
output wire joydown,
output wire joyleft,
output wire joyright,
output wire joyfire,
output wire [4:0] user_toggles,
//------------------------
input wire [7:0] din,
output reg [7:0] dout,
input wire cpuwrite,
input wire cpuread,
input wire rewind
);
// las 40 teclas del Spectrum. Se inicializan a "no pulsadas".
reg [4:0] row[0:7];
initial begin
row[0] = 5'b11111;
row[1] = 5'b11111;
row[2] = 5'b11111;
row[3] = 5'b11111;
row[4] = 5'b11111;
row[5] = 5'b11111;
row[6] = 5'b11111;
row[7] = 5'b11111;
end
// El gran mapa de teclado y sus registros de acceso
reg [7:0] keymap[0:16383]; // 16K x 8 bits
reg [13:0] addr = 14'h0000;
reg [13:0] cpuaddr = 14'h0000; // Dirección E/S desde la CPU. Se autoincrementa en cada acceso
initial begin
$readmemh ("keyb_es_hex.txt", keymap);
end
reg [2:0] keyrow1 = 3'h0;
reg [4:0] keycol1 = 5'h00;
reg [2:0] keyrow2 = 3'h0;
reg [4:0] keycol2 = 5'h00;
reg [2:0] keymodifiers = 3'b000;
reg [2:0] signalstate = 3'b000;
reg [4:0] joystate = 5'b00000;
reg [4:0] togglestate = 5'h00;
reg rmaster_reset = 1'b0, ruser_reset = 1'b0, ruser_nmi = 1'b0;
reg rjoyup = 1'b0, rjoydown = 1'b0, rjoyleft = 1'b0, rjoyright = 1'b0, rjoyfire = 1'b0;
reg [4:0] ruser_toggles = 5'h00;
assign joyup = rjoyup;
assign joydown = rjoydown;
assign joyleft = rjoyleft;
assign joyright = rjoyright;
assign joyfire = rjoyfire;
assign master_reset = rmaster_reset;
assign user_reset = ruser_reset;
assign user_nmi = ruser_nmi;
assign user_toggles = ruser_toggles;
// Asi funciona la matriz de teclado cuando se piden semifilas
// desde la CPU.
// Un always @* hubiera quedado más claro en la descripción
// pero por algun motivo, el XST no lo ha admitido en este caso
assign sp_col = ((sp_row[0] == 1'b0)? row[0] : 5'b11111) &
((sp_row[1] == 1'b0)? row[1] : 5'b11111) &
((sp_row[2] == 1'b0)? row[2] : 5'b11111) &
((sp_row[3] == 1'b0)? row[3] : 5'b11111) &
((sp_row[4] == 1'b0)? row[4] : 5'b11111) &
((sp_row[5] == 1'b0)? row[5] : 5'b11111) &
((sp_row[6] == 1'b0)? row[6] : 5'b11111) &
((sp_row[7] == 1'b0)? row[7] : 5'b11111);
reg [2:0] modifiers = 3'b000;
reg [3:0] keycount = 4'b0000;
parameter
CLEANMATRIX = 4'd0,
IDLE = 4'd1,
ADDR0PUT = 4'd2,
ADDR1PUT = 4'd3,
ADDR2PUT = 4'd4,
ADDR3PUT = 4'd5,
TRANSLATE1 = 4'd6,
TRANSLATE2 = 4'd7,
TRANSLATE3 = 4'd8,
CPUTIME = 4'd9,
CPUREAD = 4'd10,
CPUWRITE = 4'd11,
CPUINCADD = 4'd12,
UPDCOUNTERS1= 4'd13,
UPDCOUNTERS2= 4'd14;
reg [3:0] state = CLEANMATRIX;
reg key_is_pending = 1'b0;
always @(posedge clk) begin
if (scan_received == 1'b1)
key_is_pending <= 1'b1;
if (rst == 1'b1 || (kbclean == 1'b1 && state == IDLE && key_is_pending == 1'b0))
state <= CLEANMATRIX;
else begin
case (state)
CLEANMATRIX: begin
modifiers <= 3'b000;
keycount <= 4'b0000;
row[0] <= 5'b11111;
row[1] <= 5'b11111;
row[2] <= 5'b11111;
row[3] <= 5'b11111;
row[4] <= 5'b11111;
row[5] <= 5'b11111;
row[6] <= 5'b11111;
row[7] <= 5'b11111;
if (cpuread == 1'b1 || cpuwrite == 1'b1 || rewind == 1'b1)
state <= CPUTIME;
else
state <= IDLE;
end
IDLE: begin
if (key_is_pending == 1'b1) begin
addr <= {modifiers, extended, scan, 2'b00}; // 1 scan tiene 8 bits + 1 bit para indicar scan extendido + 3 bits para el modificador usado
state <= ADDR0PUT;
key_is_pending <= 1'b0;
end
else if (cpuread == 1'b1 || cpuwrite == 1'b1 || rewind == 1'b1)
state <= CPUTIME;
end
ADDR0PUT: begin
{keyrow1,keycol1} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b01};
state <= ADDR1PUT;
end
ADDR1PUT: begin
{keyrow2,keycol2} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b10};
state <= ADDR2PUT;
end
ADDR2PUT: begin
{signalstate,joystate} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b11};
state <= ADDR3PUT;
end
ADDR3PUT: begin
{keymodifiers,togglestate} <= keymap[addr];
state <= TRANSLATE1;
end
TRANSLATE1: begin
// Actualiza las 8 semifilas del teclado con la primera tecla
if (~released) begin
row[keyrow1] <= row[keyrow1] & ~keycol1;
end
else begin
row[keyrow1] <= row[keyrow1] | keycol1;
end
state <= TRANSLATE2;
end
TRANSLATE2: begin
// Actualiza las 8 semifilas del teclado con la segunda tecla
if (~released) begin
row[keyrow2] <= row[keyrow2] & ~keycol2;
end
else begin
row[keyrow2] <= row[keyrow2] | keycol2;
end
state <= TRANSLATE3;
end
TRANSLATE3: begin
// Actualiza modificadores
if (~released)
modifiers <= modifiers | keymodifiers;
else
modifiers <= modifiers & ~keymodifiers;
// Y de la misma forma tendria que actualizar el joystick, resets y los user_toogles
if (~released)
{rjoyup,rjoydown,rjoyleft,rjoyright,rjoyfire} <= {rjoyup,rjoydown,rjoyleft,rjoyright,rjoyfire} | joystate;
else
{rjoyup,rjoydown,rjoyleft,rjoyright,rjoyfire} <= {rjoyup,rjoydown,rjoyleft,rjoyright,rjoyfire} & ~joystate;
if (~released)
{rmaster_reset,ruser_reset,ruser_nmi} <= {rmaster_reset,ruser_reset,ruser_nmi} | signalstate;
else
{rmaster_reset,ruser_reset,ruser_nmi} <= {rmaster_reset,ruser_reset,ruser_nmi} & ~signalstate;
if (~released)
ruser_toggles <= ruser_toggles | togglestate;
else
ruser_toggles <= ruser_toggles & ~togglestate;
state <= IDLE;
end
CPUTIME: begin
if (rewind == 1'b1) begin
cpuaddr <= 14'h0000;
state <= IDLE;
end
else if (cpuread == 1'b1) begin
addr <= cpuaddr;
state <= CPUREAD;
end
else if (cpuwrite == 1'b1) begin
addr <= cpuaddr;
state <= CPUWRITE;
end
else
state <= IDLE;
end
CPUREAD: begin // CPU wants to read from keymap
dout <= keymap[addr];
state <= CPUINCADD;
end
CPUWRITE: begin
keymap[addr] <= din;
state <= CPUINCADD;
end
CPUINCADD: begin
if (cpuread == 1'b0 && cpuwrite == 1'b0) begin
cpuaddr <= cpuaddr + 1;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
module keyboard_pressed_status (
input wire clk,
input wire rst,
input wire scan_received,
input wire [7:0] scancode,
input wire extended,
input wire released,
output reg kbclean
);
parameter
RESETTING = 2'd0,
UPDATING = 2'd1,
SCANNING = 2'd2;
reg keybstat_ne[0:255]; // non extended keymap
reg keybstat_ex[0:255]; // extended keymap
reg [7:0] addrscan = 8'h00; // keymap bit address
reg keypressed_ne = 1'b0; // there is at least one key pressed
reg keypressed_ex = 1'b0; // there is at least one extended key pressed
reg [1:0] state = RESETTING;
integer i;
initial begin
kbclean = 1'b1;
for (i=0;i<256;i=i+1) begin
keybstat_ne[i] = 1'b0;
keybstat_ex[i] = 1'b0;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
state <= RESETTING;
addrscan <= 8'h00;
end
else begin
case (state)
RESETTING:
begin
if (addrscan == 8'hFF) begin
addrscan <= 8'h00;
state <= SCANNING;
kbclean <= 1'b1;
end
else begin
keybstat_ne[addrscan] <= 1'b0;
keybstat_ex[addrscan] <= 1'b0;
addrscan <= addrscan + 8'd1;
end
end
UPDATING:
begin
state <= SCANNING;
addrscan <= 8'h00;
kbclean <= 1'b0;
keypressed_ne <= 1'b0;
keypressed_ex <= 1'b0;
if (extended == 1'b0)
keybstat_ne[scancode] <= ~released;
else
keybstat_ex[scancode] <= ~released;
end
SCANNING:
begin
if (scan_received == 1'b1)
state <= UPDATING;
addrscan <= addrscan + 8'd1;
if (addrscan == 8'hFF) begin
kbclean <= ~(keypressed_ne | keypressed_ex);
keypressed_ne <= 1'b0;
keypressed_ex <= 1'b0;
end
else begin
keypressed_ne <= keypressed_ne | keybstat_ne[addrscan];
keypressed_ex <= keypressed_ex | keybstat_ex[addrscan];
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXTN_PP_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_8_V
`define SKY130_FD_SC_HDLL__NOR2_8_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_8_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ed_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:26:55 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ed_e.v,v 1.1 2006/04/10 15:42:10 wig Exp $
// $Date: 2006/04/10 15:42:10 $
// $Log: inst_ed_e.v,v $
// Revision 1.1 2006/04/10 15:42:10 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ed_e
//
// No user `defines in this module
module inst_ed_e
//
// Generated module inst_ed
//
(
p_mix_c_addr_12_0_gi,
p_mix_c_bus_in_31_0_gi
);
// Generated Module Inputs:
input [12:0] p_mix_c_addr_12_0_gi;
input [31:0] p_mix_c_bus_in_31_0_gi;
// Generated Wires:
wire [12:0] p_mix_c_addr_12_0_gi;
wire [31:0] p_mix_c_bus_in_31_0_gi;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [12:0] c_addr; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] c_bus_in; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign c_addr = p_mix_c_addr_12_0_gi; // __I_I_BUS_PORT
assign c_bus_in = p_mix_c_bus_in_31_0_gi; // __I_I_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_eda
inst_eda_e inst_eda (
);
// End of Generated Instance Port Map for inst_eda
// Generated Instance Port Map for inst_edb
inst_edb_e inst_edb (
.c_add(c_addr),
.c_bus_in(c_bus_in) // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
// End of Generated Instance Port Map for inst_edb
endmodule
//
// End of Generated Module rtl of inst_ed_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:19:56 05/01/2013
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module max_short(
input [15:0] x,
input [15:0] y,
output [15:0] z
);
assign z = ( y > x) ? y : x;
endmodule
module max_byte(
input [7:0] x,
input [7:0] y,
output [7:0] z
);
assign z = ( y > x) ? y : x;
endmodule
module max_nibble(
input [3:0] x,
input [3:0] y,
output [3:0] z
);
assign z = ( y > x) ? y : x;
endmodule
module fiveminusmax0(
input [3:0] i,
output [3:0] o
);
wire [4:0] fiveminus;
assign fiveminus = 5'd5 - {1'b0,i};
assign o = ( !fiveminus[4]) ? fiveminus[3:0] : 4'b0;
endmodule
module unit(
input [1:0] select_ms,
input [3:0] L, /* -6 <= L,U <= 7 */
input [3:0] U,
input [3:0] Y, /* 0 <= Y,Z <= 13 */
input [3:0] Z,
output [3:0] Lp,
output [3:0] Up,
output [3:0] Yp,
output [3:0] Zp
);
/*
fy = max( 0, 5-y)
fz = max( 0, 5-z)
sb = L+fy
sc = U+fz
sd = max( ms+6,sb,sc) , ms+6 in {2,5,7}
d = sd - 6
L' = d-U
U' = d-L
Y' = sd-sb
Z' = sd-sc
*/
wire [3:0] fy;
fiveminusmax0 gen_fy( .i(Y), .o(fy));
wire [3:0] fz;
fiveminusmax0 gen_fz( .i(Z), .o(fz));
wire [3:0] ms_plus_6;
assign ms_plus_6 = ( select_ms == 2'b00) ? 4'd2 : (( select_ms == 2'b01) ? 4'd5 : 4'd7);
wire [3:0] sb;
wire [3:0] sc;
wire [3:0] sd;
wire [3:0] d;
wire [3:0] sb_max_sc;
wire dummyy;
wire dummyz;
assign sb = L + fy;
assign sc = U + fz;
assign sb_max_sc = ( sb > sc) ? sb : sc;
assign sd = ( sb_max_sc > ms_plus_6) ? sb_max_sc : ms_plus_6;
assign d = sd - 4'd6;
assign Lp = d - U;
assign Up = d - L;
assign {dummyy,Yp} = {sd[3],sd} - {sb[3],sb};
assign {dummyz,Zp} = {sd[3],sd} - {sc[3],sc};
endmodule
module unitfull(
input [1:0] select_ms,
input [7:0] Hmm,
input [7:0] Hmc,
input [7:0] Hcm,
input [7:0] Ecm,
input [7:0] Fmc,
output [7:0] Hcc,
output [7:0] Ecc,
output [7:0] Fcc
);
/*
Hcc = max( Hmm + ms, Ecc, Fcc)
Ecc = max( Hcm - 6, Ecm - 1)
Fcc = max( Hmc - 6, Fmc - 1)
*/
wire [7:0] Hcc0;
wire [7:0] Ecc0;
wire [7:0] Ecc1;
wire [7:0] Fcc0;
wire [7:0] Fcc1;
wire [7:0] ms;
assign ms = ( select_ms == 2'b00) ? -8'd4 : (( select_ms == 2'b01) ? -8'd1 : 8'd1);
assign Hcc0 = Hmm + ms;
assign Ecc0 = Hcm - 8'd6;
assign Ecc1 = Ecm - 8'd1;
assign Fcc0 = Hmc - 8'd6;
assign Fcc1 = Fmc - 8'd1;
wire [7:0] Ecc_max_Fcc;
assign Ecc_max_Fcc = ( Ecc > Fcc) ? Ecc : Fcc;
assign Hcc = ( Hcc0 > Ecc_max_Fcc) ? Hcc0 : Ecc_max_Fcc;
assign Ecc = ( Ecc0 > Ecc1) ? Ecc0 : Ecc1;
assign Fcc = ( Fcc0 > Fcc1) ? Fcc0 : Fcc1;
endmodule
module top(
input USER_CLOCK,
output [3:0] z
);
wire clk;
clockdrv clockdrv
(// Clock in ports
.CLK_IN1(USER_CLOCK), // IN
// Clock out ports
.CLK_OUT1(clk)); // OUT
reg [41:0] state;
assign z = state[27:24];
always @(posedge clk)
begin
state = state + 1;
end
//wire [15:0] short1;
//wire [15:0] short0;
//assign { short1, short0} = state;
//wire [15:0] short_max;
//max_short max_short( .x(short0), .y(short1), .z(short_max));
wire [3:0] L;
wire [3:0] U;
wire [3:0] Y;
wire [3:0] Z;
wire [3:0] Lp;
wire [3:0] Up;
wire [3:0] Yp;
wire [3:0] Zp;
wire [1:0] select_ms;
unit unit( .select_ms(select_ms), .L(L), .U(U), .Y(Y), .Z(Z), .Lp(Lp), .Up(Up), .Yp(Yp), .Zp(Zp));
//wire [7:0] Hmm;
//wire [7:0] Hmc;
//wire [7:0] Hcm;
//wire [7:0] Ecm;
//wire [7:0] Fmc;
//wire [7:0] Hcc;
//wire [7:0] Ecc;
//wire [7:0] Fcc;
//unitfull unit( .select_ms(select_ms), .Hmm(Hmm), .Hmc(Hmc), .Hcm(Hcm), .Ecm(Ecm), .Fmc(Fmc), .Hcc(Hcc), .Ecc(Ecc), .Fcc(Fcc));
//wire [7:0] byte1;
//wire [7:0] byte0;
//assign {byte1, byte0} = state[15:0];
//wire [7:0] byte_max;
//max_byte max_byte( .x(byte0), .y(byte1), .z(byte_max));
//wire [3:0] nibble2;
//wire [3:0] nibble1;
//wire [3:0] nibble0;
//assign nibble2 = 4'd5;
//assign {nibble1,nibble0} = state[7:0];
//wire [3:0] nibble_max;
// wire [3:0] yy;
//max_nibble max_nibble( .x(nibble0), .y(nibble1), .z(nibble_max));
// assign yy = ( y > nibble2) ? y : nibble2;
wire [35:0] CONTROL0;
wire [35:0] CONTROL1;
wire [31:0] combout0;
wire [31:0] combout1;
wire [31:0] combin0;
wire [31:0] combin1;
assign {select_ms,L,U,Y,Z} = combin0[17:0];
assign combout0 = {16'b0,Lp,Up,Yp,Zp};
assign combout1 = 32'b0;
//assign {Hmc,Hcm,Ecm,Fmc} = combin0;
//assign {select_ms,Hmm} = combin1[9:0];
//assign combout0 = { 8'b0, Hcc, Ecc, Fcc};
//assign combout1 = 32'b0;
//assign {select_ms,Hmm,Hmc,Hcm,Ecm,Fmc} = state[41:0];
//wire [31:0] trig0;
//assign trig0 = { L, U, Y, Z, Lp, Up, Yp, Zp};
//assign trig0 = { 8'b0, Hcc, Ecc, Fcc};
icon2 icon2 (
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
);
vio vio0 (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.ASYNC_IN(combout0), // IN BUS [31:0]
.ASYNC_OUT(combin0) // OUT BUS [31:0]
);
vio vio1 (
.CONTROL(CONTROL1), // INOUT BUS [35:0]
.ASYNC_IN(combout1), // IN BUS [31:0]
.ASYNC_OUT(combin1) // OUT BUS [31:0]
);
endmodule
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive CYCLONEII_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive CYCLONEII_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive CYCLONEII_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module cycloneii_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
CYCLONEII_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** cycloneii_mux21
module cycloneii_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** cycloneii_mux41
module cycloneii_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** cycloneii_and1
module cycloneii_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** cycloneii_and16
module cycloneii_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** cycloneii_bmux21
module cycloneii_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneii_b17mux21
module cycloneii_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneii_nmux21
module cycloneii_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** cycloneii_b5mux21
module cycloneii_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter start_delay = 1;
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module cycloneii_ram_block
(
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0, clk1,
ena0, ena1,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_data_in_clear = "none";
parameter port_b_address_clear = "none";
parameter port_b_read_enable_write_enable_clear = "none";
parameter port_b_byte_enable_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_read_enable_write_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter power_up_uninitialized = "false";
parameter lpm_type = "cycloneii_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2560'b0;
parameter port_a_byte_size = 0;
parameter port_a_disable_ce_on_input_registers = "off";
parameter port_a_disable_ce_on_output_registers = "off";
parameter port_b_byte_size = 0;
parameter port_b_disable_ce_on_input_registers = "off";
parameter port_b_disable_ce_on_output_registers = "off";
parameter safe_write = "err_on_2clk";
parameter init_file_restructured = "unused";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_data_in_clear = "none";
parameter port_a_address_clear = "none";
parameter port_a_write_enable_clear = "none";
parameter port_a_byte_enable_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbrewe;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
tri0 portawe_int;
assign portawe_int = portawe;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbrewe_int;
assign portbrewe_int = portbrewe;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri0 portaaddrstall_int;
assign portaaddrstall_int = portaaddrstall;
tri0 portbaddrstall_int;
assign portbaddrstall_int = portbaddrstall;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr,rewe_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in,rewe_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire rewe_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a, active_b;
wire active_a_in, active_b_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
`ifdef QUARTUS_MEMORY_PLI
$memory_connect(mem);
`endif
ram_type = (ram_block_type == "M-RAM" || ram_block_type == "m-ram" || ram_block_type == "MegaRAM" ||
(ram_block_type == "auto" && mixed_port_feed_through_mode == "dont_care" && port_b_read_enable_write_enable_clock == "clock0"));
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {mem_init1,mem_init0};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = (port_a_data_in_clear == "none") ? 1'b0 : clr0_int;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = (port_b_data_in_clear == "none") ? 1'b0 : (
(port_b_data_in_clear == "clear0") ? clr0_int : clr1_int);
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = (port_a_byte_enable_clear == "none") ? 1'b0 : clr0_int;
assign byteena_b_clr_in = (port_b_byte_enable_clear == "none") ? 1'b0 : (
(port_b_byte_enable_clear == "clear0") ? clr0_int : clr1_int);
assign we_a_clr_in = (port_a_write_enable_clear == "none") ? 1'b0 : clr0_int;
assign rewe_b_clr_in = (port_b_read_enable_write_enable_clear == "none") ? 1'b0 : (
(port_b_read_enable_write_enable_clear == "clear0") ? clr0_int : clr1_int);
assign active_a_in = ena0_int || (port_a_disable_ce_on_input_registers == "on");
assign active_b_in = ((port_b_read_enable_write_enable_clock == "clock0") ? ena0_int : ena1_int) ||
(port_b_disable_ce_on_input_registers == "on");
// Store clock enable value for SEAB/MEAB
// port A active
cycloneii_ram_register active_port_a (
.d(active_a_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a),.aclrout()
);
defparam active_port_a.width = 1;
assign active_write_a = active_a && (byteena_a_reg !== 'b0);
// port B active
cycloneii_ram_register active_port_b (
.d(active_b_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b),.aclrout()
);
defparam active_port_b.width = 1;
assign active_write_b = active_b && (byteena_b_reg !== 'b0);
// ------- A input registers -------
// write enable
cycloneii_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_in),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// address
cycloneii_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall_int),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
cycloneii_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
cycloneii_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// read/write enable
cycloneii_ram_register rewe_b_register (
.d(portbrewe_int),
.clk(clk_b_in),
.aclr(rewe_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(rewe_b_reg),
.aclrout(rewe_b_clr)
);
defparam rewe_b_register.width = 1;
defparam rewe_b_register.preset = mode_is_dp;
// address
cycloneii_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall_int),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
cycloneii_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
cycloneii_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Write pulse generation
cycloneii_ram_pulse_generator wpgen_a (
.clk(ram_type ? clk_a_in : ~clk_a_in),
.ena(active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
cycloneii_ram_pulse_generator wpgen_b (
.clk(ram_type ? clk_b_in : ~clk_b_in),
.ena(active_write_b & mode_is_bdp & rewe_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
// Read pulse generation
cycloneii_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a & ~we_a_reg),
.pulse(read_pulse_a),
.cycle()
);
cycloneii_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena(active_b & (mode_is_dp ? rewe_b_reg : ~rewe_b_reg)),
.pulse(read_pulse_b),
.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
)
begin
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime)
read_data_latch = mem[addr_prime_reg];
if (read_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Same port feed through
cycloneii_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a & ~mode_is_dp & we_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
cycloneii_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b & mode_is_bdp & rewe_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
dataout_a = datain_prime_reg ^ mask_vector_prime;
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
dataout_a = datain_sec_reg ^ mask_vector_sec;
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a & ~we_a_reg)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge rewe_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
mem_invalidate = 1'b1;
else if (active_b & (mode_is_dp & rewe_b_reg || mode_is_bdp & ~rewe_b_reg))
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge rewe_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
ena0_int || (port_a_disable_ce_on_output_registers == "on") :
ena1_int || (port_a_disable_ce_on_output_registers == "on") ;
cycloneii_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
ena0_int || (port_b_disable_ce_on_output_registers == "on") :
ena1_int || (port_b_disable_ce_on_output_registers == "on") ;
cycloneii_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // cycloneii_ram_block
//--------------------------------------------------------------------
//
// Module Name : cycloneii_jtag
//
// Description : CycloneII JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "cycloneii_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneii_crcblock
//
// Description : CycloneII CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneii_crcblock";
endmodule
//---------------------------------------------------------------------
//
// Module Name : cycloneii_asmiblock
//
// Description : CycloneII ASMIBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_asmiblock
(
dclkin,
scein,
sdoin,
data0out,
oe
);
input dclkin;
input scein;
input sdoin;
input oe;
output data0out;
parameter lpm_type = "cycloneii_asmiblock";
endmodule // cycloneii_asmiblock
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
cout_tmp = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneii_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg clk_last_valid_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
tmp_cout = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'bx)
begin
$display("Warning : Invalid transition to 'X' detected on CycloneII PLL input clk. This edge will be ignored.");
$display("Time: %0t Instance: %m", $time);
end
else if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if ((first_rising_edge == 0) && (clk_last_valid_value !== clk))
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
end
clk_last_value = clk;
if (clk !== 1'bx)
clk_last_valid_value = clk;
end
assign cout = tmp_cout;
endmodule // cycloneii_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0, C1, C2, C3, C4 and
// C5 output counters of the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneii_scale_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cycloneii_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // cycloneii_pll_reg
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_pll
//
// Description : Timing simulation model for the CycloneII PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 6 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad, clkloss and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module cycloneii_pll (inclk,
ena,
clkswitch,
areset,
pfdena,
testclearlock,
clk,
locked,
testupout,
testdownout,
sbdin,
sbdout
);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clk0";
parameter feedback_source = "clk0";
parameter qualify_conf_done = "off";
parameter test_input_comp_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter inclk0_input_frequency = 10000;
parameter inclk1_input_frequency = 10000;
parameter gate_lock_signal = "no";
parameter gate_lock_counter = 1;
parameter self_reset_on_gated_loss_lock = "off";
parameter valid_lock_multiplier = 1;
parameter invalid_lock_multiplier = 5;
parameter switch_over_type = "manual";
parameter switch_over_on_lossclk = "off";
parameter switch_over_on_gated_lock = "off";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "on";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter spread_frequency = 0;
parameter use_dc_coupling = "false";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 1;
parameter clk0_divide_by = 1;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 1;
parameter clk1_divide_by = 1;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 1;
parameter clk2_divide_by = 1;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 1;
parameter clk3_divide_by = 1;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 1;
parameter clk4_divide_by = 1;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter clk5_output_frequency = 0;
parameter clk5_multiply_by = 1;
parameter clk5_divide_by = 1;
parameter clk5_phase_shift = "0";
parameter clk5_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
parameter ss = 0;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter c5_high = 1;
parameter c5_low = 1;
parameter c5_initial = 1;
parameter c5_mode = "bypass";
parameter c5_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "c0";
parameter clk1_counter = "c1";
parameter clk2_counter = "c2";
parameter clk3_counter = "c3";
parameter clk4_counter = "c4";
parameter clk5_counter = "c5";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter c5_use_casc_in = "off";
parameter m_test_source = 5;
parameter c0_test_source = 5;
parameter c1_test_source = 5;
parameter c2_test_source = 5;
parameter c3_test_source = 5;
parameter c4_test_source = 5;
parameter c5_test_source = 5;
// LVDS mode parameters
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter charge_pump_current = 52;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 16;
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "cycloneii_pll";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter sim_gate_lock_device_behavior = "off";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter family_name = "CycloneII";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input [1:0] inclk;
input ena;
input clkswitch;
input areset;
input pfdena;
input testclearlock;
input sbdin;
// OUTPUT PORTS
output [2:0] clk;
output locked;
output sbdout;
// lvds specific output ports
// test ports
output testupout;
output testdownout;
// BUFFER INPUTS
wire inclk0_ipd;
wire inclk1_ipd;
wire ena_ipd;
wire fbin_ipd;
wire clkswitch_ipd;
wire areset_ipd;
wire pfdena_ipd;
wire scanclk_ipd;
wire scanread_ipd;
wire scanwrite_ipd;
wire scandata_ipd;
wire sbdin_ipd;
buf (inclk0_ipd, inclk[0]);
buf (inclk1_ipd, inclk[1]);
buf (ena_ipd, ena);
buf (fbin_ipd, 1'b0);
buf (clkswitch_ipd, clkswitch);
buf (areset_ipd, areset);
buf (pfdena_ipd, pfdena);
buf (scanclk_ipd, 1'b0);
buf (scanread_ipd, 1'b0);
buf (scanwrite_ipd, 1'b0);
buf (scandata_ipd, 1'b0);
buf (sbdin_ipd, sbdin);
// TIMING CHECKS
specify
(sbdin => sbdout) = (0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer c0_count;
integer c0_initial_count;
integer c1_count;
integer c1_initial_count;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
time next_vco_sched_time;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg pll_about_to_lock;
reg locked_tmp;
reg c0_got_first_rising_edge;
reg c1_got_first_rising_edge;
reg vco_c0_last_value;
reg vco_c1_last_value;
reg areset_ipd_last_value;
reg ena_ipd_last_value;
reg pfdena_ipd_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:5];
reg [31:0] c_low_val[0:5];
reg [8*6:1] c_mode_val[0:5];
reg [31:0] c_initial_val[0:5];
integer c_ph_val[0:5];
// temporary registers for reprogramming
integer c_ph_val_tmp[0:5];
reg [31:0] c_high_val_tmp[0:5];
reg [31:0] c_low_val_tmp[0:5];
reg [8*6:1] c_mode_val_tmp[0:5];
// hold registers for reprogramming
integer c_ph_val_hold[0:5];
reg [31:0] c_high_val_hold[0:5];
reg [31:0] c_low_val_hold[0:5];
reg [8*6:1] c_mode_val_hold[0:5];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:5];
reg [31:0] c_low_val_old[0:5];
reg [8*6:1] c_mode_val_old[0:5];
integer c_ph_val_old[0:5];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [31:0] m_hi;
reg [31:0] m_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:5];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c5;
reg inclk_c0_from_vco;
reg inclk_c1_from_vco;
reg inclk_c2_from_vco;
reg inclk_c3_from_vco;
reg inclk_c4_from_vco;
reg inclk_c5_from_vco;
reg inclk_m_from_vco;
wire inclk_m;
wire [5:0] clk_tmp;
wire ena_pll;
wire n_cntr_inclk;
reg vco_c0;
reg vco_c1;
wire [5:0] clk_out;
wire sclkout0;
wire sclkout1;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
wire c5_clk;
reg first_schedule;
wire enable0_tmp;
wire enable1_tmp;
wire enable_0;
wire enable_1;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
wire sbdout_tmp;
// for external feedback mode
reg [31:0] ext_fbk_cntr_high;
reg [31:0] ext_fbk_cntr_low;
reg [31:0] ext_fbk_cntr_modulus;
reg [8*2:1] ext_fbk_cntr;
reg [8*6:1] ext_fbk_cntr_mode;
integer ext_fbk_cntr_ph;
integer ext_fbk_cntr_initial;
integer ext_fbk_cntr_index;
// variables for clk_switch
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg clkloss_tmp;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandone_tmp;
reg scandone_tmp_last_value;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
reg scanread_reg;
reg scanwrite_reg;
reg scanwrite_enabled;
reg scanwrite_last_value;
reg [173:0] scan_data;
reg [173:0] tmp_scan_data;
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg c5_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// LOCAL_PARAMETERS_BEGIN
parameter GPP_SCAN_CHAIN = 174;
parameter FAST_SCAN_CHAIN = 75;
// primary clk is always inclk0
parameter prim_clk = "inclk0";
parameter GATE_LOCK_CYCLES = 7;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_m2;
integer i_n2;
integer i_ss;
integer i_c_high[0:5];
integer i_c_low[0:5];
integer i_c_initial[0:5];
integer i_c_ph[0:5];
reg [8*6:1] i_c_mode[0:5];
integer i_vco_min;
integer i_vco_max;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk5_counter;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg [9*8:1] loop_filter_r_arr[0:39];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_is_disabled;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_primary_clock;
reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_feedback_source;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_sim_gate_lock_device_behavior;
integer current_clock;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg ic5_use_casc_in;
reg op_mode;
reg init;
reg tap0_is_active;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = numerator;
den = denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
if ((m_value == 0) || (d_value == 0))
begin
fraction_num = numerator;
fraction_div = denominator;
end
else
begin
fraction_num = m_value;
fraction_div = d_value;
end
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
if ((2 * refclk) > (refclk * max_modulus *2 / m_mod))
slowest_clk = 2 * refclk;
else
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
integer R;
begin
R = (clk_divide * M)/(clk_mult * N);
output_counter_value = R;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
integer counter_l, tmp_counter_low;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
tmp_counter_low = output_counter_value - counter_h;
if (tmp_counter_low == 0)
counter_l = 1;
else counter_l = tmp_counter_low;
counter_low = counter_l;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360 * n)) + 0.5;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for cycloneii lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_input_frequency;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
$display ("Time: %0t Instance: %m", $time);
display_msg = 1;
end
endfunction
initial
begin
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_qualify_conf_done = alpha_tolower(qualify_conf_done);
l_compensate_clock = alpha_tolower(compensate_clock);
l_primary_clock = alpha_tolower(prim_clk);
l_gate_lock_signal = alpha_tolower(gate_lock_signal);
l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_switch_over_type = alpha_tolower(switch_over_type);
l_feedback_source = alpha_tolower(feedback_source);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_sim_gate_lock_device_behavior = alpha_tolower(sim_gate_lock_device_behavior);
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 57;
loop_filter_c_arr[1] = 16;
loop_filter_c_arr[2] = 36;
loop_filter_c_arr[3] = 5;
fpll_loop_filter_c_arr[0] = 18;
fpll_loop_filter_c_arr[1] = 13;
fpll_loop_filter_c_arr[2] = 8;
fpll_loop_filter_c_arr[3] = 2;
charge_pump_curr_arr[0] = 6;
charge_pump_curr_arr[1] = 12;
charge_pump_curr_arr[2] = 30;
charge_pump_curr_arr[3] = 36;
charge_pump_curr_arr[4] = 52;
charge_pump_curr_arr[5] = 57;
charge_pump_curr_arr[6] = 72;
charge_pump_curr_arr[7] = 77;
charge_pump_curr_arr[8] = 92;
charge_pump_curr_arr[9] = 96;
charge_pump_curr_arr[10] = 110;
charge_pump_curr_arr[11] = 114;
charge_pump_curr_arr[12] = 127;
charge_pump_curr_arr[13] = 131;
charge_pump_curr_arr[14] = 144;
charge_pump_curr_arr[15] = 148;
loop_filter_r_arr[0] = " 1.000000";
loop_filter_r_arr[1] = " 1.500000";
loop_filter_r_arr[2] = " 2.000000";
loop_filter_r_arr[3] = " 2.500000";
loop_filter_r_arr[4] = " 3.000000";
loop_filter_r_arr[5] = " 3.500000";
loop_filter_r_arr[6] = " 4.000000";
loop_filter_r_arr[7] = " 4.500000";
loop_filter_r_arr[8] = " 5.000000";
loop_filter_r_arr[9] = " 5.500000";
loop_filter_r_arr[10] = " 6.000000";
loop_filter_r_arr[11] = " 6.500000";
loop_filter_r_arr[12] = " 7.000000";
loop_filter_r_arr[13] = " 7.500000";
loop_filter_r_arr[14] = " 8.000000";
loop_filter_r_arr[15] = " 8.500000";
loop_filter_r_arr[16] = " 9.000000";
loop_filter_r_arr[17] = " 9.500000";
loop_filter_r_arr[18] = "10.000000";
loop_filter_r_arr[19] = "10.500000";
loop_filter_r_arr[20] = "11.000000";
loop_filter_r_arr[21] = "11.500000";
loop_filter_r_arr[22] = "12.000000";
loop_filter_r_arr[23] = "12.500000";
loop_filter_r_arr[24] = "13.000000";
loop_filter_r_arr[25] = "13.500000";
loop_filter_r_arr[26] = "14.000000";
loop_filter_r_arr[27] = "14.500000";
loop_filter_r_arr[28] = "15.000000";
loop_filter_r_arr[29] = "15.500000";
loop_filter_r_arr[30] = "16.000000";
loop_filter_r_arr[31] = "16.500000";
loop_filter_r_arr[32] = "17.000000";
loop_filter_r_arr[33] = "17.500000";
loop_filter_r_arr[34] = "18.000000";
loop_filter_r_arr[35] = "18.500000";
loop_filter_r_arr[36] = "19.000000";
loop_filter_r_arr[37] = "19.500000";
loop_filter_r_arr[38] = "20.000000";
loop_filter_r_arr[39] = "20.500000";
if (m == 0)
begin
i_clk5_counter = "c5" ;
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
// VCO feedback loop settings for external feedback mode
// first find which counter is used for feedback
if (l_operation_mode == "external_feedback")
begin
op_mode = 1;
if (l_feedback_source == "clk0")
ext_fbk_cntr = i_clk0_counter;
else if (l_feedback_source == "clk1")
ext_fbk_cntr = i_clk1_counter;
else if (l_feedback_source == "clk2")
ext_fbk_cntr = i_clk2_counter;
else if (l_feedback_source == "clk3")
ext_fbk_cntr = i_clk3_counter;
else if (l_feedback_source == "clk4")
ext_fbk_cntr = i_clk4_counter;
else if (l_feedback_source == "clk5")
ext_fbk_cntr = i_clk5_counter;
else ext_fbk_cntr = "c0";
if (ext_fbk_cntr == "c0")
ext_fbk_cntr_index = 0;
else if (ext_fbk_cntr == "c1")
ext_fbk_cntr_index = 1;
else if (ext_fbk_cntr == "c2")
ext_fbk_cntr_index = 2;
else if (ext_fbk_cntr == "c3")
ext_fbk_cntr_index = 3;
else if (ext_fbk_cntr == "c4")
ext_fbk_cntr_index = 4;
else if (ext_fbk_cntr == "c5")
ext_fbk_cntr_index = 5;
end
else
begin
op_mode = 0;
ext_fbk_cntr_index = 0;
end
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
// convert user parameters to advanced
if (((l_pll_type == "fast") || (l_pll_type == "lvds")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high[5] = counter_high (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[5] = counter_low (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[5] = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode[5] = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[5] = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
// in external feedback mode, need to adjust M value to take
// into consideration the external feedback counter value
if (l_operation_mode == "external_feedback")
begin
// if there is a negative phase shift, m_initial can only be 1
if (max_neg_abs > 0)
i_m_initial = 1;
if (i_c_mode[ext_fbk_cntr_index] == "bypass")
output_count = 1;
else
output_count = i_c_high[ext_fbk_cntr_index] + i_c_low[ext_fbk_cntr_index];
new_divisor = gcd(i_m, output_count);
i_m = i_m / new_divisor;
i_n = output_count / new_divisor;
end
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_high[5] = c5_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_low[5] = c5_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_initial[5] = c5_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_mode[5] = translate_string(alpha_tolower(c5_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_c_ph[5] = c5_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
refclk_period = inclk0_input_frequency * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
c0_got_first_rising_edge = 0;
c1_got_first_rising_edge = 0;
vco_c0_last_value = 0;
c0_count = 2;
c0_initial_count = 1;
c1_count = 2;
c1_initial_count = 1;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
cycle_to_adjust = 0;
m_delay = 0;
vco_c0 = 0;
vco_c1 = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
ena_ipd_last_value = 0;
inclk_out_of_range = 0;
scandone_tmp = 0;
schedule_vco_last_value = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
m_val[1] = m2;
n_val[1] = n2;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 6; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
i = 0;
j = 0;
inclk_last_value = 0;
ext_fbk_cntr_ph = 0;
ext_fbk_cntr_initial = 1;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
if (l_primary_clock == "inclk0")
current_clock = 0;
else current_clock = 1;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast")
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch_ipd === 1'b1)
begin
current_clock = 1;
active_clock = 1;
end
clkloss_tmp = 0;
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
switch_over_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
scanread_active_edge = 0;
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
begin
scan_chain_length = FAST_SCAN_CHAIN;
num_output_cntrs = 4;
end
else
begin
scan_chain_length = GPP_SCAN_CHAIN;
num_output_cntrs = 6;
end
scanread_reg = 0;
scanwrite_reg = 0;
scanwrite_enabled = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
// initialize the scan_chain contents
// CP/LF bits
scan_data[11:0] = 12'b0;
for (i = 0; i <= 3; i = i + 1)
begin
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
begin
if (fpll_loop_filter_c_arr[i] == loop_filter_c)
scan_data[11:10] = i;
end
else begin
if (loop_filter_c_arr[i] == loop_filter_c)
scan_data[11:10] = i;
end
end
for (i = 0; i <= 15; i = i + 1)
begin
if (charge_pump_curr_arr[i] == charge_pump_current)
scan_data[3:0] = i;
end
for (i = 0; i <= 39; i = i + 1)
begin
if (loop_filter_r_arr[i] == loop_filter_r)
begin
if ((i >= 16) && (i <= 23))
scan_data[9:4] = i+8;
else if ((i >= 24) && (i <= 31))
scan_data[9:4] = i+16;
else if (i >= 32)
scan_data[9:4] = i+24;
else
scan_data[9:4] = i;
end
end
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
scan_data[21:12] = 10'b0; // M, C3-C0 ph
// C0-C3 high
scan_data[25:22] = c_high_val[0];
scan_data[35:32] = c_high_val[1];
scan_data[45:42] = c_high_val[2];
scan_data[55:52] = c_high_val[3];
// C0-C3 low
scan_data[30:27] = c_low_val[0];
scan_data[40:37] = c_low_val[1];
scan_data[50:47] = c_low_val[2];
scan_data[60:57] = c_low_val[3];
// C0-C3 mode
for (i = 0; i < 4; i = i + 1)
begin
if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
begin
scan_data[26 + (10*i)] = 1;
if (c_mode_val[i] == " off")
scan_data[31 + (10*i)] = 1;
else
scan_data[31 + (10*i)] = 0;
end
else begin
scan_data[26 + (10*i)] = 0;
if (c_mode_val[i] == " odd")
scan_data[31 + (10*i)] = 1;
else
scan_data[31 + (10*i)] = 0;
end
end
// M
if (m_mode_val[0] == "bypass")
begin
scan_data[66] = 1;
scan_data[71] = 0;
scan_data[65:62] = 4'b0;
scan_data[70:67] = 4'b0;
end
else begin
scan_data[66] = 0; // set BYPASS bit to 0
scan_data[70:67] = m_val[0]/2; // set M low
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[65:62] = scan_data[70:67];
scan_data[71] = 0;
end
else begin // M is odd : M high = low + 1
scan_data[65:62] = (m_val[0]/2) + 1;
scan_data[71] = 1;
end
end
// N
scan_data[73:72] = n_val[0];
if (n_mode_val[0] == "bypass")
begin
scan_data[74] = 1;
scan_data[73:72] = 2'b0;
end
end
else begin // PLL type is enhanced/auto
scan_data[25:12] = 14'b0;
// C5-C0 high
scan_data[33:26] = c_high_val[5];
scan_data[51:44] = c_high_val[4];
scan_data[69:62] = c_high_val[3];
scan_data[87:80] = c_high_val[2];
scan_data[105:98] = c_high_val[1];
scan_data[123:116] = c_high_val[0];
// C5-C0 low
scan_data[42:35] = c_low_val[5];
scan_data[60:53] = c_low_val[4];
scan_data[78:71] = c_low_val[3];
scan_data[96:89] = c_low_val[2];
scan_data[114:107] = c_low_val[1];
scan_data[132:125] = c_low_val[0];
for (i = 5; i >= 0; i = i - 1)
begin
if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
begin
scan_data[124 - (18*i)] = 1;
if (c_mode_val[i] == " off")
scan_data[133 - (18*i)] = 1;
else
scan_data[133 - (18*i)] = 0;
end
else begin
scan_data[124 - (18*i)] = 0;
if (c_mode_val[i] == " odd")
scan_data[133 - (18*i)] = 1;
else
scan_data[133 - (18*i)] = 0;
end
end
scan_data[142:134] = m_val[0];
scan_data[143] = 0;
scan_data[152:144] = m_val[1];
scan_data[153] = 0;
if (m_mode_val[0] == "bypass")
begin
scan_data[143] = 1;
scan_data[142:134] = 9'b0;
end
if (m_mode_val[1] == "bypass")
begin
scan_data[153] = 1;
scan_data[152:144] = 9'b0;
end
scan_data[162:154] = n_val[0];
scan_data[172:164] = n_val[1];
if (n_mode_val[0] == "bypass")
begin
scan_data[163] = 1;
scan_data[162:154] = 9'b0;
end
if (n_mode_val[1] == "bypass")
begin
scan_data[173] = 1;
scan_data[172:164] = 9'b0;
end
end
// now save this counter's parameters
ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
ext_fbk_cntr_initial = c_initial_val[ext_fbk_cntr_index];
ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
no_warn = 1'b0;
// check if pll is in test mode
if (m_test_source == 1 || c0_test_source == 1 || c0_test_source == 2 || c1_test_source == 1 || c1_test_source == 2 || c2_test_source == 1 || c2_test_source == 2)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_is_disabled = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
if (c5_use_casc_in == "on")
ic5_use_casc_in = 1;
else
ic5_use_casc_in = 0;
tap0_is_active = 1;
next_vco_sched_time = 0;
end
always @(clkswitch_ipd)
begin
if (clkswitch_ipd === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if (clkswitch_ipd === 1'b1)
begin
current_clock = 1;
active_clock = 1;
inclk_n = inclk1_ipd;
end
else if (clkswitch_ipd === 1'b0)
begin
current_clock = 0;
active_clock = 0;
inclk_n = inclk0_ipd;
end
end
end
always @(inclk0_ipd or inclk1_ipd)
begin
// save the inclk event value
if (inclk0_ipd !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk0_ipd;
end
if (inclk1_ipd !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk1_ipd;
end
// check if either input clk is bad
if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk0_ipd !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk0_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk0_ipd;
end
end
else inclk_n = inclk0_ipd;
end
if ((inclk1_ipd !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk1_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk1_ipd;
end
end
else inclk_n = inclk1_ipd;
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && l_pll_type !== "fast" && l_pll_type !== "lvds" && (clkswitch_ipd !== 1'b1) && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
end
if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
begin
if (primary_clk_is_bad)
clkloss_tmp = 1;
else
clkloss_tmp = 0;
end
else clkloss_tmp = clkswitch_ipd;
inclk0_last_value = inclk0_ipd;
inclk1_last_value = inclk1_ipd;
other_clock_last_value = other_clock_value;
end
cycloneii_pll_reg ena_reg ( .clk(!inclk_n),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(1'b1),
.q(pllena_reg));
and (test_mode_inclk, inclk_n, pllena_reg);
assign n_cntr_inclk = inclk_n;
assign ena_pll = ena_ipd;
assign inclk_m = (m_test_source == 1) ? refclk : (m_test_source == 2) ? 1'b0 : (m_test_source == 3) ? 1'b0 : op_mode == 1 ? (l_feedback_source == "clk0" ? clk_tmp[0] :
l_feedback_source == "clk1" ? clk_tmp[1] :
l_feedback_source == "clk2" ? clk_tmp[2] :
l_feedback_source == "clk3" ? clk_tmp[3] :
l_feedback_source == "clk4" ? clk_tmp[4] :
l_feedback_source == "clk5" ? clk_tmp[5] : 1'b0) :
inclk_m_from_vco;
cycloneii_m_cntr m1 (.clk(inclk_m),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
cycloneii_n_cntr n1 (.clk(n_cntr_inclk),
.reset(areset_ipd),
.cout(refclk),
.modulus(n_val[0]));
always @(vco_out[0])
begin
// now schedule the other taps with the appropriate phase-shift
for (k = 1; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(phase_shift[k]) vco_out[0];
end
end
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (!pll_is_disabled) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_tap[x] !== vco_tap_last_value[x])
begin
if (c_ph_val[0] == x)
begin
inclk_c0_from_vco <= vco_tap[x];
end
if (c_ph_val[1] == x)
begin
inclk_c1_from_vco <= vco_tap[x];
end
if (c_ph_val[2] == x)
inclk_c2_from_vco <= vco_tap[x];
if (c_ph_val[3] == x)
inclk_c3_from_vco <= vco_tap[x];
if (c_ph_val[4] == x)
inclk_c4_from_vco <= vco_tap[x];
if (c_ph_val[5] == x)
inclk_c5_from_vco <= vco_tap[x];
if (m_ph_val == x)
inclk_m_from_vco <= vco_tap[x];
end
end
if (scanwrite_enabled === 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y <= 5; y = y + 1)
begin
if (c_ph_val[y] == x)
c_ph_val[y] <= c_ph_val_tmp[y];
end
if (m_ph_val == x)
m_ph_val <= m_ph_val_tmp;
end
end
end
// reset all counter phase tap values to POF programmed values
if (areset_ipd === 1'b1)
begin
m_ph_val <= m_ph_val_orig;
m_ph_val_tmp <= m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
begin
c_ph_val[i] <= c_ph_val_orig[i];
c_ph_val_tmp[i] <= c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
assign inclk_c0 = (c0_test_source == 1) ? refclk : (c0_test_source == 2) ? fbclk : (c0_test_source == 3) ? 1'b0 : inclk_c0_from_vco;
cycloneii_scale_cntr c0 (.clk(inclk_c0),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
always @(posedge c0_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[0] <= c_high_val_tmp[0];
c_mode_val[0] <= c_mode_val_tmp[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge c0_clk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val[0] <= c_low_val_tmp[0];
end
end
assign inclk_c1 = (c1_test_source == 1) ? refclk : (c1_test_source == 2) ? fbclk : (c1_test_source == 3) ? 1'b0 : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
cycloneii_scale_cntr c1 (.clk(inclk_c1),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge c1_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[1] <= c_high_val_tmp[1];
c_mode_val[1] <= c_mode_val_tmp[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge c1_clk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val[1] <= c_low_val_tmp[1];
end
end
assign inclk_c2 = (c2_test_source == 1) ? refclk : (c2_test_source == 2) ? fbclk : (c2_test_source == 3) ? 1'b0 : (ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
cycloneii_scale_cntr c2 (.clk(inclk_c2),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge c2_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[2] <= c_high_val_tmp[2];
c_mode_val[2] <= c_mode_val_tmp[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge c2_clk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val[2] <= c_low_val_tmp[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? n_cntr_inclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
cycloneii_scale_cntr c3 (.clk(inclk_c3),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge c3_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[3] <= c_high_val_tmp[3];
c_mode_val[3] <= c_mode_val_tmp[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge c3_clk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val[3] <= c_low_val_tmp[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? n_cntr_inclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
cycloneii_scale_cntr c4 (.clk(inclk_c4),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge c4_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[4] <= c_high_val_tmp[4];
c_mode_val[4] <= c_mode_val_tmp[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge c4_clk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val[4] <= c_low_val_tmp[4];
end
end
assign inclk_c5 = ((c5_test_source == 0) ? n_cntr_inclk : (ic5_use_casc_in == 1) ? c4_clk : inclk_c5_from_vco);
cycloneii_scale_cntr c5 (.clk(inclk_c5),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c5_clk),
.high(c_high_val[5]),
.low(c_low_val[5]),
.initial_value(c_initial_val[5]),
.mode(c_mode_val[5]),
.ph_tap(c_ph_val[5]));
always @(posedge c5_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[5] <= c_high_val_tmp[5];
c_mode_val[5] <= c_mode_val_tmp[5];
c5_rising_edge_transfer_done = 1;
end
end
always @(negedge c5_clk)
begin
if (c5_rising_edge_transfer_done)
begin
c_low_val[5] <= c_low_val_tmp[5];
end
end
always @ (inclk_n or ena_pll or areset_ipd)
begin
if (areset_ipd == 1'b1 || ena_pll == 1'b0)
begin
gate_count = 0;
gate_out = 0;
end
else if (inclk_n == 1'b1 && inclk_last_value != inclk_n)
begin
gate_count = gate_count + 1;
if (l_sim_gate_lock_device_behavior == "on")
begin
if (gate_count == gate_lock_counter)
gate_out = 1;
end
else begin
if (gate_count == GATE_LOCK_CYCLES)
gate_out = 1;
end
end
inclk_last_value = inclk_n;
end
assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
always @(posedge scanread_ipd)
begin
scanread_active_edge = $time;
end
always @ (scanclk_ipd)
begin
if (scanclk_ipd === 1'b0 && scanclk_last_value === 1'b1)
begin
// enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end
if (scanread_reg === 1'b1)
gated_scanclk <= scanclk_ipd && scanread_reg;
else
gated_scanclk <= 1'b1;
if (scanclk_ipd === 1'b1 && scanclk_last_value === 1'b0)
begin
// register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk)
scanclk_period = $time - scanclk_last_rising_edge;
else begin
got_first_scanclk = 1;
end
// reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd == 1'b0 && scanread_reg == 1'b1)
begin
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
end
scanclk_last_rising_edge = $time;
end
scanclk_last_value = scanclk_ipd;
end
always @(posedge gated_scanclk)
begin
if ($time > 0)
begin
if (!got_first_gated_scanclk)
begin
got_first_gated_scanclk = 1;
// if ($time - scanread_active_edge < scanclk_period)
// begin
// scanread_setup_violation = 1;
// $display("Warning : SCANREAD must go high at least one cycle before SCANDATA is read in.");
// $display ("Time: %0t Instance: %m", $time);
// end
end
for (j = scan_chain_length-1; j >= 1; j = j - 1)
begin
scan_data[j] = scan_data[j - 1];
end
scan_data[0] <= scandata_ipd;
end
end
assign scandataout_tmp = (l_pll_type == "fast" || l_pll_type == "lvds") ? scan_data[FAST_SCAN_CHAIN-1] : scan_data[GPP_SCAN_CHAIN-1];
always @(posedge scandone_tmp)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : %s PLL Reprogramming completed with the following values (Values in parantheses are original values) : ", family_name);
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
$display(" M ph_tap = %0d (%0d) ", m_ph_val, m_ph_val_old);
if (ss > 0)
begin
$display(" M2 modulus = %0d (%0d) ", m_val[1], m_val_old[1]);
$display(" N2 modulus = %0d (%0d) ", n_val[1], n_val_old[1]);
end
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s), C%0d phase tap = %0d (%0d)", i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i], i, c_ph_val[i], c_ph_val_old[i]);
end
// display Charge pump and loop filter values
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
always @(scanwrite_enabled)
begin
if (scanwrite_enabled === 1'b0 && scanwrite_last_value === 1'b1)
begin
// falling edge : deassert scandone
scandone_tmp <= #(1.5*scanclk_period) 1'b0;
// reset counter transfer flags
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
end
if (scanwrite_enabled === 1'b1 && scanwrite_last_value !== scanwrite_enabled)
begin
$display ("NOTE : %s PLL Reprogramming initiated ....", family_name);
$display ("Time: %0t Instance: %m", $time);
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// make temp. copy of scan_data for processing
tmp_scan_data = scan_data;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
// CP
// Bits 0-3 : all values are legal
cp_curr_val = charge_pump_curr_arr[scan_data[3:0]];
// LF Resistance : bits 4-9
// values from 010000 - 010111, 100000 - 100111,
// 110000- 110111 are illegal
if (((tmp_scan_data[9:4] >= 6'b010000) && (tmp_scan_data[9:4] <= 6'b010111)) ||
((tmp_scan_data[9:4] >= 6'b100000) && (tmp_scan_data[9:4] <= 6'b100111)) ||
((tmp_scan_data[9:4] >= 6'b110000) && (tmp_scan_data[9:4] <= 6'b110111)))
begin
$display ("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
reconfig_err = 1;
end
else begin
i = scan_data[9:4];
if (i >= 56 )
i = i - 24;
else if ((i >= 40) && (i <= 47))
i = i - 16;
else if ((i >= 24) && (i <= 31))
i = i - 8;
lfr_val = loop_filter_r_arr[i];
end
// LF Capacitance : bits 10,11 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
lfc_val = fpll_loop_filter_c_arr[scan_data[11:10]];
else
lfc_val = loop_filter_c_arr[scan_data[11:10]];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
m_ph_val_old = m_ph_val;
for (i=0; i<=5; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_ph_val_old[i] = c_ph_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// first the M counter phase : bit order same for fast and GPP
if (scan_data[12] == 1'b0)
begin
// do nothing
end
else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b1)
begin
m_ph_val_tmp = m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7)
m_ph_val_tmp = 0;
end
else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b0)
begin
m_ph_val_tmp = m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0)
m_ph_val_tmp = 7;
end
else
begin
$display ("Warning : Illegal bit settings for M counter phase tap. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
reconfig_err = 1;
end
// read the fast PLL bits.
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
// C3-C0 phase bits
for (i = 3; i >= 0; i=i-1)
begin
if (tmp_scan_data[14] == 1'b0)
begin
// do nothing
end
else if (tmp_scan_data[14] === 1'b1)
begin
if (tmp_scan_data[15] === 1'b1)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
if (c_ph_val_tmp[i] > 7)
c_ph_val_tmp[i] = 0;
end
else if (tmp_scan_data[15] === 1'b0)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
if (c_ph_val_tmp[i] < 0)
c_ph_val_tmp[i] = 7;
end
end
tmp_scan_data = tmp_scan_data >> 2;
end
// C0-C3 counter moduli
tmp_scan_data = scan_data;
for (i = 0; i < 4; i=i+1)
begin
if (tmp_scan_data[26] == 1'b1)
begin
c_mode_val_tmp[i] = "bypass";
if (tmp_scan_data[31] === 1'b1)
begin
c_mode_val_tmp[i] = " off";
$display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
$display ("Time: %0t Instance: %m", $time);
end
end
else if (tmp_scan_data[31] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
if (tmp_scan_data[25:22] === 4'b0000)
c_high_val_tmp[i] = 5'b10000;
else
c_high_val_tmp[i] = {1'b0, tmp_scan_data[25:22]};
if (tmp_scan_data[30:27] === 4'b0000)
c_low_val_tmp[i] = 5'b10000;
else
c_low_val_tmp[i] = {1'b0, tmp_scan_data[30:27]};
tmp_scan_data = tmp_scan_data >> 10;
end
// M
error = 0;
// some temporary storage
if (scan_data[65:62] == 4'b0000)
m_hi = 5'b10000;
else
m_hi = {1'b0, scan_data[65:62]};
if (scan_data[70:67] == 4'b0000)
m_lo = 5'b10000;
else
m_lo = {1'b0, scan_data[70:67]};
m_val_tmp[0] = m_hi + m_lo;
if (scan_data[66] === 1'b1)
begin
if (scan_data[71] === 1'b1)
begin
// this will turn off the M counter : error
reconfig_err = 1;
error = 1;
$display ("The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
// M counter is being bypassed
if (m_mode_val[0] !== "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" M", 4);
end
m_val_tmp[0] = 32'b1;
m_mode_val[0] = "bypass";
end
end
else begin
if (m_mode_val[0] === "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" M", 1);
end
m_mode_val[0] = "";
if (scan_data[71] === 1'b1)
begin
// odd : check for duty cycle, if not 50% -- error
if (m_hi - m_lo !== 1)
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
end
else begin // even mode
if (m_hi !== m_lo)
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
end
end
// N
error = 0;
n_val[0] = {1'b0, scan_data[73:72]};
if (scan_data[74] !== 1'b1)
begin
if (scan_data[73:72] == 2'b01)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
d_msg = display_msg(" N", 2);
end
else if (scan_data[73:72] == 2'b00)
n_val[0] = 3'b100;
if (error == 1'b0)
begin
if (n_mode_val[0] === "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" N", 1);
end
n_mode_val[0] = "";
end
end
else if (scan_data[74] == 1'b1) // bypass
begin
if (scan_data[72] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
d_msg = display_msg(" N", 3);
end
else begin
if (n_mode_val[0] != "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" N", 4);
end
n_val[0] = 2'b01;
n_mode_val[0] = "bypass";
end
end
end
else begin // pll type is auto or enhanced
for (i = 0; i < 6; i=i+1)
begin
if (tmp_scan_data[124] == 1'b1)
begin
c_mode_val_tmp[i] = "bypass";
if (tmp_scan_data[133] === 1'b1)
begin
c_mode_val_tmp[i] = " off";
$display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
$display ("Time: %0t Instance: %m", $time);
end
end
else if (tmp_scan_data[133] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
if (tmp_scan_data[123:116] === 8'b00000000)
c_high_val_tmp[i] = 9'b100000000;
else
c_high_val_tmp[i] = {1'b0, tmp_scan_data[123:116]};
if (tmp_scan_data[132:125] === 8'b00000000)
c_low_val_tmp[i] = 9'b100000000;
else
c_low_val_tmp[i] = {1'b0, tmp_scan_data[132:125]};
tmp_scan_data = tmp_scan_data << 18;
end
// the phase_taps
tmp_scan_data = scan_data;
for (i = 0; i < 6; i=i+1)
begin
if (tmp_scan_data[14] == 1'b0)
begin
// do nothing
end
else if (tmp_scan_data[14] === 1'b1)
begin
if (tmp_scan_data[15] === 1'b1)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
if (c_ph_val_tmp[i] > 7)
c_ph_val_tmp[i] = 0;
end
else if (tmp_scan_data[15] === 1'b0)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
if (c_ph_val_tmp[i] < 0)
c_ph_val_tmp[i] = 7;
end
end
tmp_scan_data = tmp_scan_data >> 2;
end
ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
// cntrs M/M2
tmp_scan_data = scan_data;
for (i=0; i<2; i=i+1)
begin
if (i == 0 || (i == 1 && ss > 0))
begin
error = 0;
m_val_tmp[i] = {1'b0, tmp_scan_data[142:134]};
if (tmp_scan_data[143] !== 1'b1)
begin
if (tmp_scan_data[142:134] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" M", 2);
else
d_msg = display_msg("M2", 2);
end
else if (tmp_scan_data[142:134] == 9'b000000000)
m_val_tmp[i] = 10'b1000000000;
if (error == 1'b0)
begin
if (m_mode_val[i] === "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" M", 1);
else
d_msg = display_msg("M2", 1);
end
m_mode_val[i] = "";
end
end
else if (tmp_scan_data[143] == 1'b1)
begin
if (tmp_scan_data[134] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" M", 3);
else
d_msg = display_msg("M2", 3);
end
else begin
if (m_mode_val[i] !== "bypass")
begin
// Mode is switched: give warning
if (i == 0)
d_msg = display_msg(" M", 4);
else
d_msg = display_msg("M2", 4);
end
m_val_tmp[i] = 10'b0000000001;
m_mode_val[i] = "bypass";
end
end
end
tmp_scan_data = tmp_scan_data >> 10;
end
if (ss > 0)
begin
if (m_mode_val[0] != m_mode_val[1])
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for M/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
end
// cntrs N/N2
tmp_scan_data = scan_data;
for (i=0; i<2; i=i+1)
begin
if (i == 0 || (i == 1 && ss > 0))
begin
error = 0;
n_val[i] = 0;
n_val[i] = {1'b0, tmp_scan_data[162:154]};
if (tmp_scan_data[163] !== 1'b1)
begin
if (tmp_scan_data[162:154] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" N", 2);
else
d_msg = display_msg("N2", 2);
end
else if (tmp_scan_data[162:154] == 9'b000000000)
n_val[i] = 10'b1000000000;
if (error == 1'b0)
begin
if (n_mode_val[i] === "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" N", 1);
else
d_msg = display_msg("N2", 1);
end
n_mode_val[i] = "";
end
end
else if (tmp_scan_data[163] == 1'b1) // bypass
begin
if (tmp_scan_data[154] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" N", 3);
else
d_msg = display_msg("N2", 3);
end
else begin
if (n_mode_val[i] != "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" N", 4);
else
d_msg = display_msg("N2", 4);
end
n_val[i] = 10'b0000000001;
n_mode_val[i] = "bypass";
end
end
end
tmp_scan_data = tmp_scan_data >> 10;
end
if (ss > 0)
begin
if (n_mode_val[0] != n_mode_val[1])
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for N/N2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
end
end
slowest_clk_old = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
refclk_period, m_val[0]);
slowest_clk_new = slowest_clk ( c_high_val_tmp[0]+c_low_val_tmp[0], c_mode_val_tmp[0],
c_high_val_tmp[1]+c_low_val_tmp[1], c_mode_val_tmp[1],
c_high_val_tmp[2]+c_low_val_tmp[2], c_mode_val_tmp[2],
c_high_val_tmp[3]+c_low_val_tmp[3], c_mode_val_tmp[3],
c_high_val_tmp[4]+c_low_val_tmp[4], c_mode_val_tmp[4],
c_high_val_tmp[5]+c_low_val_tmp[5], c_mode_val_tmp[5],
refclk_period, m_val_tmp[0]);
quiet_time = (slowest_clk_new > slowest_clk_old) ? slowest_clk_new : slowest_clk_old;
// get quiet time in terms of scanclk cycles
my_rem = quiet_time % scanclk_period;
scanclk_cycles = quiet_time/scanclk_period;
if (my_rem != 0)
scanclk_cycles = scanclk_cycles + 1;
scandone_tmp <= #((scanclk_cycles+0.5) * scanclk_period) 1'b1;
end
scanwrite_last_value = scanwrite_enabled;
end
always @(schedule_vco or areset_ipd or ena_pll)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset_ipd === 1'b1 && areset_ipd_last_value !== areset_ipd)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
pll_is_in_reset = 1;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// areset deasserted : note time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
pll_is_in_reset = 0;
if ((ena_pll === 1'b1) && (stop_vco !== 1'b1) && (next_vco_sched_time <= $time))
schedule_vco = ~ schedule_vco;
end
// if ena was deasserted
if (ena_pll == 1'b0 && ena_ipd_last_value !== ena_pll)
begin
$display (" Note : %s PLL is disabled", family_name);
$display ("Time: %0t Instance: %m", $time);
pll_is_disabled = 1;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
if (ena_pll == 1'b1 && ena_ipd_last_value !== ena_pll)
begin
$display (" Note : %s PLL is enabled", family_name);
$display ("Time: %0t Instance: %m", $time);
pll_is_disabled = 0;
if ((areset_ipd !== 1'b1) && (stop_vco !== 1'b1) && (next_vco_sched_time < $time))
schedule_vco = ~ schedule_vco;
end
// illegal value on areset_ipd
if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)
begin
// reset lock parameters
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
if ( ($time == 0 && first_schedule == 1'b1) || (schedule_vco !== schedule_vco_last_value && (stop_vco !== 1'b1) && (ena_pll === 1'b1) && (areset_ipd !== 1'b1)) )
begin
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
if (op_mode == 1)
begin
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
loop_xplier = m_val[0] * (ext_fbk_cntr_modulus);
loop_ph = ext_fbk_cntr_ph;
loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * ext_fbk_cntr_modulus);
end
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
if (op_mode == 1)
begin
pull_back_M = (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
while (pull_back_M > refclk_period)
pull_back_M = pull_back_M - refclk_period;
end
else begin
pull_back_M = initial_delay + fbk_phase;
end
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
if (op_mode == 1)
begin
fbk_delay = pull_back_M;
if (l_simulation_type == "timing")
fbk_delay = fbk_delay + pll_compensation_delay;
end
else begin
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule tap 0
vco_out[0] <= #(sched_time) vco_val;
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule tap 0
vco_out[0] <= #(sched_time) vco_val;
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
next_vco_sched_time = $time + sched_time;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_ipd_last_value = areset_ipd;
ena_ipd_last_value = ena_pll;
schedule_vco_last_value = schedule_vco;
end
always @(pfdena_ipd)
begin
if (pfdena_ipd === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : %s PFDENA was deasserted", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_ipd_last_value = pfdena_ipd;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((vco_max != 0 && vco_min != 0) && (pfdena_ipd === 1'b1) &&
((refclk_period/loop_xplier > vco_max) ||
(refclk_period/loop_xplier < vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
inclk_out_of_range = 0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (scanwrite_enabled === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked === 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : %s PLL lost lock due to loss of input clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
else if (!pll_is_locked && ($time - refclk_time > 2 * refclk_period) && pfdena_ipd === 1'b1)
begin
inclk_out_of_range = 1;
end
fbclk_time = $time;
end
if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
// considered in phase
if (cycles_to_lock == valid_lock_multiplier - 1)
pll_about_to_lock <= 1;
if (cycles_to_lock == valid_lock_multiplier)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == invalid_lock_multiplier)
begin
pll_is_locked = 0;
locked_tmp = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : i_clk0_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : i_clk1_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : i_clk2_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : i_clk3_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : i_clk4_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[5] = i_clk5_counter == "c0" ? c0_clk : i_clk5_counter == "c1" ? c1_clk : i_clk5_counter == "c2" ? c2_clk : i_clk5_counter == "c3" ? c3_clk : i_clk5_counter == "c4" ? c4_clk : i_clk5_counter == "c5" ? c5_clk : 1'b0;
assign clk_out[0] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[0] : 1'bx;
assign clk_out[1] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[1] : 1'bx;
assign clk_out[2] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[2] : 1'bx;
assign clk_out[3] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[3] : 1'bx;
assign clk_out[4] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[4] : 1'bx;
assign clk_out[5] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[5] : 1'bx;
assign sbdout_tmp = sbdin_ipd;
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (sbdout, 1'b1, sbdout_tmp);
endmodule // cycloneii_pll
//------------------------------------------------------------------
//
// Module Name : cycloneii_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // cycloneii_routing_wire
//------------------------------------------------------------------
//
// Module Name : cycloneii_lcell_ff
//
// Description : Cyclone II LCELL_FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_lcell_ff (
datain,
clk,
aclr,
sclr,
sload,
sdata,
ena,
devclrn,
devpor,
regout
);
parameter x_on_violation = "on";
parameter lpm_type = "cycloneii_lcell_ff";
input datain;
input clk;
input aclr;
input sclr;
input sload;
input sdata;
input ena;
input devclrn;
input devpor;
output regout;
tri1 devclrn;
tri1 devpor;
reg regout_tmp;
wire reset;
reg datain_viol;
reg sclr_viol;
reg sload_viol;
reg sdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire datain_in;
wire clk_in;
wire aclr_in;
wire sclr_in;
wire sload_in;
wire sdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (datain_in, datain);
buf (clk_in, clk);
buf (aclr_in, aclr);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (sdata_in, sdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && (!aclr_in) && (ena_in);
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, sdata, 0, 0, sdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: regout_tmp)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
regout_tmp = 'b0;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (datain_viol or sclr_viol or sload_viol or ena_viol or sdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (sdata_in or aclr_in or devclrn or devpor)
begin
if (devpor == 'b0)
regout_tmp <= 'b0;
else if (devclrn == 'b0)
regout_tmp <= 'b0;
else if (aclr_in == 'b1)
regout_tmp <= 'b0;
end
always @ (clk_in or posedge aclr_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
regout_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || aclr_in === 'b1)
regout_tmp <= 'b0;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
regout_tmp <= 'b0 ;
else if (sload_in === 'b1)
regout_tmp <= sdata_in;
else
regout_tmp <= datain_in;
end
end
clk_last_value = clk_in;
end
and (regout, regout_tmp, 'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_lcell_comb
//
// Description : Cyclone II LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter lpm_type = "cycloneii_lcell_comb";
reg cout_tmp;
reg combout_tmp;
reg [1:0] isum_lutc_input;
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire cin_in;
buf (dataa_in, dataa);
buf (datab_in, datab);
buf (datac_in, datac);
buf (datad_in, datad);
buf (cin_in, cin);
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
endspecify
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
$display ("Time: %0t Instance: %m", $time);
isum_lutc_input = 2;
end
end
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
begin
if (isum_lutc_input == 0) // datac
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
datac_in, datad_in);
end
else if (isum_lutc_input == 1) // cin
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
cin_in, datad_in);
end
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
end
and (combout, combout_tmp, 1'b1) ;
and (cout, cout_tmp, 1'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// CYCLONEII ASYNCH IO Atom
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneii_asynch_io (datain, oe, regin,
differentialin, differentialout,
padio, combout, regout);
input datain, oe;
input regin;
input differentialin;
output differentialout;
output combout;
output regout;
inout padio;
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter use_differential_input = "false";
reg prev_value;
reg tmp_padio, tmp_combout;
reg buf_control;
wire differentialout_tmp;
wire tmp_combout_differentialin_or_pad;
wire datain_in;
wire differentialin_in;
wire oe_in;
buf(differentialin_in, differentialin);
buf(oe_in, oe);
buf(datain_in, datain);
tri padio_tmp;
specify
(padio => differentialout) = (0,0);
(differentialin => combout) = (0,0);
(padio => combout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
(regin => regout) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
tmp_padio = 'bz;
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if ( operation_mode == "input")
begin
if (padio === 1'bz)
tmp_combout = prev_value;
else
begin
prev_value = padio;
tmp_combout = padio;
end
tmp_padio = 1'bz;
end
else
begin
if ( operation_mode == "output" || operation_mode == "bidir")
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 1'b0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in === 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // output of tri is 'Z'
begin
if ( operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
end
else // open drain_output = false;
begin
tmp_padio = datain_in;
prev_value = datain_in;
end
end
else if ( oe_in == 0 )
begin
if (operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
else // oe == 'X'
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end // bidir or output
if ( operation_mode == "output")
tmp_combout = 1'bz;
else
tmp_combout = padio;
end
end
else // bus hold is false
begin
buf_control = 'b0;
if ( operation_mode == "input")
begin
tmp_combout = padio;
end
else if (operation_mode == "output" || operation_mode == "bidir")
begin
if ( operation_mode == "bidir")
tmp_combout = padio;
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in === 1'bx)
tmp_padio = 1'bx;
else
tmp_padio = 1'bz;
end
else
tmp_padio = datain_in;
end
else if ( oe_in == 0 )
tmp_padio = 1'bz;
else
tmp_padio = 1'bx;
end
else
begin
$display ("Error: Invalid operation_mode specified in cycloneii io atom!\n");
$display ("Time: %0t Instance: %m", $time);
end
end
end
assign differentialout_tmp = (operation_mode == "input" || operation_mode == "bidir") ? padio : 1'bx;
assign tmp_combout_differentialin_or_pad = (use_differential_input == "true") ? differentialin_in : tmp_combout;
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (combout, tmp_combout_differentialin_or_pad, 'b0);
pmos (padio, padio_tmp, 'b0);
and (regout, regin, 1'b1);
pmos (differentialout, differentialout_tmp, 'b0);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// CYCLONEII IO Atom
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneii_io (datain, oe, outclk, outclkena, inclk, inclkena, areset, sreset,
devclrn, devpor, devoe, linkin,
differentialin, differentialout,
padio, combout, regout, linkout);
parameter operation_mode = "input";
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter output_register_mode = "none";
parameter output_async_reset = "none";
parameter output_sync_reset = "none";
parameter output_power_up = "low";
parameter tie_off_output_clock_enable = "false";
parameter oe_register_mode = "none";
parameter oe_async_reset = "none";
parameter oe_sync_reset = "none";
parameter oe_power_up = "low";
parameter tie_off_oe_clock_enable = "false";
parameter input_register_mode = "none";
parameter input_async_reset = "none";
parameter input_sync_reset = "none";
parameter input_power_up = "low";
parameter lpm_type = "cycloneii_io";
parameter use_differential_input = "false";
inout padio;
input datain, oe;
input outclk, outclkena, inclk, inclkena, areset, sreset;
input devclrn, devpor, devoe;
input linkin;
input differentialin;
output differentialout;
output combout, regout;
output linkout;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire out_reg_clk_ena, oe_reg_clk_ena;
wire tmp_oe_reg_out, tmp_input_reg_out, tmp_output_reg_out;
wire inreg_sreset_is_used, outreg_sreset_is_used, oereg_sreset_is_used;
wire inreg_sreset, outreg_sreset, oereg_sreset;
wire in_reg_aclr, in_reg_apreset;
wire oe_reg_aclr, oe_reg_apreset, oe_reg_sel;
wire out_reg_aclr, out_reg_apreset, out_reg_sel;
wire input_reg_pu_low, output_reg_pu_low, oe_reg_pu_low;
wire inreg_D, outreg_D, oereg_D;
wire tmp_datain, tmp_oe;
wire iareset, isreset;
wire pad_or_differentialin;
assign pad_or_differentialin = (use_differential_input == "true") ? differentialin : padio;
assign input_reg_pu_low = ( input_power_up == "low") ? 'b0 : 'b1;
assign output_reg_pu_low = ( output_power_up == "low") ? 'b0 : 'b1;
assign oe_reg_pu_low = ( oe_power_up == "low") ? 'b0 : 'b1;
assign out_reg_sel = (output_register_mode == "register" ) ? 'b1 : 'b0;
assign oe_reg_sel = ( oe_register_mode == "register" ) ? 'b1 : 'b0;
assign iareset = ( areset === 'b0 || areset === 'b1 ) ? !areset : 'b1;
assign isreset = ( sreset === 'b0 || sreset === 'b1 ) ? sreset : 'b0;
// output register signals
assign out_reg_aclr = (output_async_reset == "clear") ? iareset : 'b1;
assign out_reg_apreset = ( output_async_reset == "preset") ? iareset : 'b1;
assign outreg_sreset_is_used = ( output_sync_reset == "none") ? 'b0 : 'b1;
assign outreg_sreset = (output_sync_reset == "clear") ? 'b0 : 'b1;
// oe register signals
assign oe_reg_aclr = ( oe_async_reset == "clear") ? iareset : 'b1;
assign oe_reg_apreset = ( oe_async_reset == "preset") ? iareset : 'b1;
assign oereg_sreset_is_used = ( oe_sync_reset == "none") ? 'b0 : 'b1;
assign oereg_sreset = (oe_sync_reset == "clear") ? 'b0 : 'b1;
// input register signals
assign in_reg_aclr = ( input_async_reset == "clear") ? iareset : 'b1;
assign in_reg_apreset = ( input_async_reset == "preset") ? iareset : 'b1;
assign inreg_sreset_is_used = ( input_sync_reset == "none") ? 'b0 : 'b1;
assign inreg_sreset = (input_sync_reset == "clear") ? 'b0 : 'b1;
// oe and output register clock enable signals
assign out_reg_clk_ena = ( tie_off_output_clock_enable == "true") ? 'b1 : outclkena;
assign oe_reg_clk_ena = ( tie_off_oe_clock_enable == "true") ? 'b1 : outclkena;
// input reg
cycloneii_mux21 inreg_D_mux (.MO (inreg_D),
.A (pad_or_differentialin),
.B (inreg_sreset),
.S (isreset && inreg_sreset_is_used));
cycloneii_dffe input_reg (.Q (tmp_input_reg_out),
.CLK (inclk),
.ENA (inclkena),
.D (inreg_D),
.CLRN (in_reg_aclr && devclrn && (input_reg_pu_low || devpor)),
.PRN (in_reg_apreset && (!input_reg_pu_low || devpor)));
//output reg
cycloneii_mux21 outreg_D_mux (.MO (outreg_D),
.A (datain),
.B (outreg_sreset),
.S (isreset && outreg_sreset_is_used));
cycloneii_dffe output_reg (.Q (tmp_output_reg_out),
.CLK (outclk),
.ENA (out_reg_clk_ena),
.D (outreg_D),
.CLRN (out_reg_aclr && devclrn && (output_reg_pu_low || devpor)),
.PRN (out_reg_apreset && (!output_reg_pu_low || devpor)));
//oe reg
cycloneii_mux21 oereg_D_mux (.MO (oereg_D),
.A (oe),
.B (oereg_sreset),
.S (isreset && oereg_sreset_is_used));
cycloneii_dffe oe_reg (.Q (tmp_oe_reg_out),
.CLK (outclk),
.ENA (oe_reg_clk_ena),
.D (oereg_D),
.CLRN (oe_reg_aclr && devclrn && (oe_reg_pu_low || devpor)),
.PRN (oe_reg_apreset && (!oe_reg_pu_low || devpor)));
// asynchronous block
assign tmp_oe = (oe_reg_sel == 'b1) ? tmp_oe_reg_out : oe;
assign tmp_datain = ((operation_mode == "output" || operation_mode == "bidir") && out_reg_sel == 'b1 ) ? tmp_output_reg_out : datain;
cycloneii_asynch_io asynch_inst(.datain(tmp_datain),
.oe(tmp_oe),
.regin(tmp_input_reg_out),
.differentialin(differentialin),
.differentialout(differentialout),
.padio(padio),
.combout(combout),
.regout(regout));
defparam asynch_inst.operation_mode = operation_mode;
defparam asynch_inst.bus_hold = bus_hold;
defparam asynch_inst.open_drain_output = open_drain_output;
defparam asynch_inst.use_differential_input = use_differential_input;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_clk_delay_ctrl
//
// Description : Cycloneii CLK DELAY CTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clk_delay_ctrl (
clk,
delayctrlin,
disablecalibration,
pllcalibrateclkdelayedin,
devpor,
devclrn,
clkout
);
input clk;
input [5:0] delayctrlin;
input disablecalibration;
input pllcalibrateclkdelayedin;
input devpor;
input devclrn;
output clkout;
parameter behavioral_sim_delay = 0;
parameter delay_chain = "54"; // or "1362ps"
parameter delay_chain_mode = "static";
parameter uses_calibration = "false";
parameter use_new_style_dq_detection = "false";
parameter tan_delay_under_delay_ctrl_signal = "unused";
parameter delay_ctrl_sim_delay_15_0 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_31_16 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_47_32 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_63_48 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter lpm_type = "cycloneii_clk_delay_ctrl";
tri1 devclrn;
tri1 devpor;
// BUFFERED BUS INPUTS
wire [5:0] delayctrl_in;
// TMP OUTPUTS
wire clk_out_w;
wire clk_after_calib_mux_w;
reg clk_after_dly_chain_r;
integer dqs_dynamic_dly_index_i;
integer dqs_dynamic_dly_i;
// Dynamic Delay Table
reg [31:0] dly_table_r [0:63];
reg [2047:0] delay_ctrl_sim_delay_all_r;
reg [31:0] a_val_r;
integer i;
integer j;
// FUNCTIONS
// INTERNAL NETS AND VARIABLES
// TIMING HOOKS
wire clk_in;
wire delayctrl_in5;
wire delayctrl_in4;
wire delayctrl_in3;
wire delayctrl_in2;
wire delayctrl_in1;
wire delayctrl_in0;
wire disablecalibration_in;
wire pllcalibrateclkdelayed_in;
buf (clk_in, clk);
buf (delayctrl_in5, delayctrlin[5]);
buf (delayctrl_in4, delayctrlin[4]);
buf (delayctrl_in3, delayctrlin[3]);
buf (delayctrl_in2, delayctrlin[2]);
buf (delayctrl_in1, delayctrlin[1]);
buf (delayctrl_in0, delayctrlin[0]);
buf (disablecalibration_in, disablecalibration);
buf (pllcalibrateclkdelayed_in, pllcalibrateclkdelayedin);
assign delayctrl_in = {delayctrl_in5, delayctrl_in4, delayctrl_in3,
delayctrl_in2,delayctrl_in1,delayctrl_in0};
specify
(clk => clkout) = (0,0);
(disablecalibration => clkout) = (0,0);
(pllcalibrateclkdelayedin => clkout) = (0,0);
endspecify
// MODEL
initial
begin
delay_ctrl_sim_delay_all_r = {delay_ctrl_sim_delay_63_48, delay_ctrl_sim_delay_47_32, delay_ctrl_sim_delay_31_16, delay_ctrl_sim_delay_15_0};
// dly_table_r = delay_ctrl_sim_delay_all_r;
for (i=0; i<64; i=i+1)
begin
// dly_table_r[i] = delay_ctrl_sim_delay_all_r[32*i+31 : 32*i];
for (j=0; j<32; j=j+1)
a_val_r[j] = delay_ctrl_sim_delay_all_r[32*i+j];
dly_table_r[i] = a_val_r;
end
`ifdef CYCLONEII_CLK_DELAY_CTRL_DEBUG
$display("DEBUG: CLK_DELAY_CTRL instance %m has dynamic delay table ...");
for (i=0; i<64; i=i+1)
$display("%0d", dly_table_r[i]);
`endif
end
// generate dynamic delay value
initial
begin
dqs_dynamic_dly_index_i = 0;
dqs_dynamic_dly_i = 0;
end
always @(delayctrl_in)
begin
dqs_dynamic_dly_index_i = delayctrl_in;
if (dqs_dynamic_dly_index_i >= 0 && dqs_dynamic_dly_index_i < 64)
dqs_dynamic_dly_i = dly_table_r[dqs_dynamic_dly_index_i];
end
// generating post delay chain clock
always @(clk_in)
begin
if (delay_chain_mode == "dynamic")
clk_after_dly_chain_r <= #(dqs_dynamic_dly_i) clk_in;
else if (delay_chain_mode == "static")
clk_after_dly_chain_r <= #(behavioral_sim_delay) clk_in;
end
// generating post calib mux clock
assign clk_after_calib_mux_w = (uses_calibration == "true" && disablecalibration_in === 1'b0) ?
pllcalibrateclkdelayed_in : clk_after_dly_chain_r;
// final clock
assign clk_out_w = (delay_chain_mode == "none") ? clk_in : clk_after_calib_mux_w;
and (clkout, clk_out_w, 1'b1);
endmodule
//-----------------------------------------------------------------------------
//
// Module Name : cycloneii_clk_delay_cal_ctrl
//
// Description : Cycloneii CLK DELAY CALIBRATION CTRL Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clk_delay_cal_ctrl(
pllcalibrateclk, plldataclk, delayctrlin, disablecalibration,
devclrn, devpor,
calibratedata, pllcalibrateclkdelayedout);
input pllcalibrateclk;
input plldataclk;
input [5:0] delayctrlin;
input disablecalibration;
input devclrn;
input devpor;
output calibratedata;
output pllcalibrateclkdelayedout;
parameter delay_ctrl_sim_delay_15_0 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_31_16 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_47_32 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_63_48 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter lpm_type = "cycloneii_clk_delay_cal_ctrl";
tri1 devclrn;
tri1 devpor;
// BUFFERED BUS INPUTS
wire [5:0] delayctrl_in;
// TIMING HOOKS
wire plldataclk_in;
wire pllcalibrateclk_in;
wire delayctrl_in5;
wire delayctrl_in4;
wire delayctrl_in3;
wire delayctrl_in2;
wire delayctrl_in1;
wire delayctrl_in0;
wire disablecalibration_in;
buf (plldataclk_in, plldataclk);
buf (pllcalibrateclk_in, pllcalibrateclk);
buf (delayctrl_in5, delayctrlin[5]);
buf (delayctrl_in4, delayctrlin[4]);
buf (delayctrl_in3, delayctrlin[3]);
buf (delayctrl_in2, delayctrlin[2]);
buf (delayctrl_in1, delayctrlin[1]);
buf (delayctrl_in0, delayctrlin[0]);
buf (disablecalibration_in, disablecalibration);
// TMP OUTPUTS
wire cal_clk_out_w;
wire cal_data_out_w;
reg clk_after_dly_chain_r;
reg cal_clk_by2_r;
reg cal_data_by2_r;
reg cal_clk_prev;
reg cal_data_prev;
integer dqs_dynamic_dly_index_i;
integer dqs_dynamic_dly_i;
// Dynamic Delay Table
reg [31:0] dly_table_r [0:63];
reg [2047:0] delay_ctrl_sim_delay_all_r;
reg [31:0] a_val_r;
integer i;
integer j;
// FUNCTIONS
// INTERNAL NETS AND VARIABLES
assign delayctrl_in = {delayctrl_in5, delayctrl_in4, delayctrl_in3,
delayctrl_in2,delayctrl_in1,delayctrl_in0};
specify
(plldataclk => calibratedata) = (0,0);
(disablecalibration => calibratedata) = (0,0);
(pllcalibrateclk => pllcalibrateclkdelayedout) = (0,0);
(disablecalibration => pllcalibrateclkdelayedout) = (0,0);
endspecify
// MODEL
initial
begin
delay_ctrl_sim_delay_all_r = {delay_ctrl_sim_delay_63_48, delay_ctrl_sim_delay_47_32, delay_ctrl_sim_delay_31_16, delay_ctrl_sim_delay_15_0};
for (i=0; i<64; i=i+1)
begin
for (j=0; j<32; j=j+1)
a_val_r[j] = delay_ctrl_sim_delay_all_r[32*i+j];
dly_table_r[i] = a_val_r;
end
`ifdef CYCLONEII_CLK_DELAY_CTRL_DEBUG
$display("DEBUG: CLK_DELAY_CAL_CTRL instance %m has dynamic delay table ...");
for (i=0; i<64; i=i+1)
$display("%0d", dly_table_r[i]);
`endif
end
// generate dynamic delay value
initial
begin
dqs_dynamic_dly_index_i = 0;
dqs_dynamic_dly_i = 0;
end
always @(delayctrl_in)
begin
dqs_dynamic_dly_index_i = delayctrl_in;
if (dqs_dynamic_dly_index_i >= 0 && dqs_dynamic_dly_index_i < 64)
dqs_dynamic_dly_i = dly_table_r[dqs_dynamic_dly_index_i];
end
// generate divided by 2 clocks
initial
begin
cal_clk_by2_r = 1'b0;
end
always @(pllcalibrateclk_in or posedge disablecalibration_in or negedge devclrn or negedge devpor)
begin
if (disablecalibration_in === 1'b1 || devclrn === 1'b0 || devpor === 1'b0)
begin
cal_clk_prev <= 1'bx;
cal_clk_by2_r <= 1'b0;
end
else
begin
cal_clk_prev <= pllcalibrateclk_in;
if (pllcalibrateclk_in === 1'b1 && cal_clk_prev === 1'b0)
cal_clk_by2_r <= ~cal_clk_by2_r;
end
end
initial
begin
cal_data_by2_r = 1'b0;
end
always @(plldataclk_in or posedge disablecalibration_in or negedge devclrn or negedge devpor)
begin
if (disablecalibration_in === 1'b1 || devclrn === 1'b0 || devpor === 1'b0)
begin
cal_data_prev <= 1'bx;
cal_data_by2_r <= 1'b0;
end
else
begin
cal_data_prev <= plldataclk_in;
if (plldataclk_in === 1'b1 && cal_data_prev === 1'b0)
cal_data_by2_r <= ~cal_data_by2_r;
end
end
// generating post delay chain clock
always @(cal_clk_by2_r)
begin
clk_after_dly_chain_r <= #(dqs_dynamic_dly_i) cal_clk_by2_r;
end
// final clocks
assign cal_clk_out_w = clk_after_dly_chain_r;
assign cal_data_out_w = cal_data_by2_r;
and (calibratedata, cal_data_out_w, 1'b1);
and (pllcalibrateclkdelayedout, cal_clk_out_w, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
reg clk_last_value;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
wire d_in;
wire clk_in;
buf (d_in, d);
buf (clk_in, clk);
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
clk_last_value = clk_in;
end
always @ (clk_in or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_last_value === 'b0) & (clk_in === 1'b1) & (ena == 1'b1))
q_tmp <= d_in;
clk_last_value = clk_in;
end
and (q, q_tmp, 'b1);
endmodule // cycloneii_ena_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_clkctrl
//
// Description : Cycloneii CLKCTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clkctrl (
inclk,
clkselect,
ena,
devpor,
devclrn,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
input ena;
input devpor;
input devclrn;
output outclk;
tri1 devclrn;
tri1 devpor;
parameter clock_type = "auto";
parameter ena_register_mode = "falling edge";
parameter lpm_type = "cycloneii_clkctrl";
wire clkmux_out; // output of CLK mux
wire cereg_out; // output of ENA register
wire ena_out; // choice of registered ENA or none.
wire inclk3_ipd;
wire inclk2_ipd;
wire inclk1_ipd;
wire inclk0_ipd;
wire clkselect1_ipd;
wire clkselect0_ipd;
wire ena_ipd;
buf (inclk3_ipd, inclk[3]);
buf (inclk2_ipd, inclk[2]);
buf (inclk1_ipd, inclk[1]);
buf (inclk0_ipd, inclk[0]);
buf (clkselect1_ipd, clkselect[1]);
buf (clkselect0_ipd, clkselect[0]);
buf (ena_ipd, ena);
cycloneii_mux41 clk_mux (.MO(clkmux_out),
.IN0(inclk0_ipd),
.IN1(inclk1_ipd),
.IN2(inclk2_ipd),
.IN3(inclk3_ipd),
.S({clkselect1_ipd, clkselect0_ipd}));
cycloneii_ena_reg extena0_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(devpor),
.q(cereg_out)
);
assign ena_out = (ena_register_mode == "falling edge") ? cereg_out : ena_ipd;
and (outclk, ena_out, clkmux_out);
endmodule
//---------------------------------------------------------------------
//
// Module Name : cycloneii_mac_data_reg
//
// Description : Simulation model for the data input register of
// Cyclone II MAC_MULT
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_data_reg (clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tmp;
wire [17:0] dataout_wire;
// INTERNAL VARIABLES
wire [17:0] data_ipd;
wire enable;
wire no_clr;
reg d_viol;
reg ena_viol;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
// BUFFER INPUTS
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
buf (data_ipd[0], data[0]);
buf (data_ipd[1], data[1]);
buf (data_ipd[2], data[2]);
buf (data_ipd[3], data[3]);
buf (data_ipd[4], data[4]);
buf (data_ipd[5], data[5]);
buf (data_ipd[6], data[6]);
buf (data_ipd[7], data[7]);
buf (data_ipd[8], data[8]);
buf (data_ipd[9], data[9]);
buf (data_ipd[10], data[10]);
buf (data_ipd[11], data[11]);
buf (data_ipd[12], data[12]);
buf (data_ipd[13], data[13]);
buf (data_ipd[14], data[14]);
buf (data_ipd[15], data[15]);
buf (data_ipd[16], data[16]);
buf (data_ipd[17], data[17]);
assign enable = (!aclr_ipd) && (ena_ipd);
assign no_clr = (!aclr_ipd);
// TIMING PATHS
specify
$setuphold (posedge clk &&& enable, data, 0, 0, d_viol);
$setuphold (posedge clk &&& no_clr, ena, 0, 0, ena_viol);
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
(posedge aclr => (dataout +: 1'b0)) = (0, 0);
endspecify
initial
begin
clk_last_value <= 'b0;
dataout_tmp <= 18'b0;
end
always @(clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
dataout_tmp <= 'bX;
end
else if (aclr_ipd == 1'b1)
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk_ipd === 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd === 1'b1)
dataout_tmp <= data_ipd;
end
clk_last_value <= clk_ipd;
end // always
assign dataout_wire = dataout_tmp;
and (dataout[0], dataout_wire[0], 1'b1);
and (dataout[1], dataout_wire[1], 1'b1);
and (dataout[2], dataout_wire[2], 1'b1);
and (dataout[3], dataout_wire[3], 1'b1);
and (dataout[4], dataout_wire[4], 1'b1);
and (dataout[5], dataout_wire[5], 1'b1);
and (dataout[6], dataout_wire[6], 1'b1);
and (dataout[7], dataout_wire[7], 1'b1);
and (dataout[8], dataout_wire[8], 1'b1);
and (dataout[9], dataout_wire[9], 1'b1);
and (dataout[10], dataout_wire[10], 1'b1);
and (dataout[11], dataout_wire[11], 1'b1);
and (dataout[12], dataout_wire[12], 1'b1);
and (dataout[13], dataout_wire[13], 1'b1);
and (dataout[14], dataout_wire[14], 1'b1);
and (dataout[15], dataout_wire[15], 1'b1);
and (dataout[16], dataout_wire[16], 1'b1);
and (dataout[17], dataout_wire[17], 1'b1);
endmodule //cycloneii_mac_data_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_sign_reg
//
// Description : Simulation model for the sign input register of
// Cyclone II MAC_MULT
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUPs
tri1 aclr, ena;
wire d_ipd;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
buf (d_ipd, d);
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
assign enable = (!aclr_ipd) && (ena_ipd);
specify
$setuphold (posedge clk &&& enable, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& enable, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge aclr => (q +: 1'b0)) = 0 ;
endspecify
initial
begin
clk_last_value <= 'b0;
q_tmp <= 'b0;
end
always @ (clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
q_tmp <= 'bX;
end
else
begin
if (aclr_ipd == 1'b1)
q_tmp <= 0;
else if ((clk_ipd == 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd == 1'b1)
q_tmp <= d_ipd;
end
clk_last_value <= clk_ipd;
end
and (q, q_tmp, 'b1);
endmodule // cycloneii_mac_sign_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_mult_internal
//
// Description : Cyclone II MAC_MULT_INTERNAL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_mult_internal
(
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
// OUTPUT
output [dataout_width-1:0] dataout;
// Internal variables
wire [17:0] dataa_ipd;
wire [17:0] datab_ipd;
wire signa_ipd;
wire signb_ipd;
wire [dataout_width-1:0] dataout_tmp;
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
reg [17:0] i_ones; // padding with 1's for input negation
// Input buffers
buf (signa_ipd, signa);
buf (signb_ipd, signb);
buf dataa_buf [dataa_width-1:0] (dataa_ipd[dataa_width-1:0], dataa);
buf datab_buf [datab_width-1:0] (datab_ipd[datab_width-1:0], datab);
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// get signs of a and b, and get absolute values since Verilog '*' operator
// is an unsigned multiplication
assign ia_is_positive = ~signa_ipd | ~dataa_ipd[dataa_width-1];
assign ib_is_positive = ~signb_ipd | ~datab_ipd[datab_width-1];
assign iabsa = ia_is_positive == 1 ? dataa_ipd[dataa_width-1:0] : -(dataa_ipd | (i_ones << dataa_width));
assign iabsb = ib_is_positive == 1 ? datab_ipd[datab_width-1:0] : -(datab_ipd | (i_ones << datab_width));
// multiply a * b
assign iabsresult = iabsa * iabsb;
assign dataout_tmp = (ia_is_positive ^ ib_is_positive) == 1 ? -iabsresult : iabsresult;
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_mult
//
// Description : Cyclone II MAC_MULT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_mult
(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneii_mac_mult";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width + datab_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
tri1 devclrn;
tri1 devpor;
wire [dataout_width-1:0] dataout_tmp;
wire [17:0] idataa_reg; // optional register for dataa input
wire [17:0] idatab_reg; // optional register for datab input
wire [17:0] dataa_pad; // padded dataa input
wire [17:0] datab_pad; // padded datab input
wire isigna_reg; // optional register for signa input
wire isignb_reg; // optional register for signb input
wire [17:0] idataa_int; // dataa as seen by the multiplier input
wire [17:0] idatab_int; // datab as seen by the multiplier input
wire isigna_int; // signa as seen by the multiplier input
wire isignb_int; // signb as seen by the multiplier input
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
wire dataa_use_reg; // equivalent to dataa_clock parameter
wire datab_use_reg; // equivalent to datab_clock parameter
wire signa_use_reg; // equivalent to signa_clock parameter
wire signb_use_reg; // equivalent to signb_clock parameter
reg [17:0] i_ones; // padding with 1's for input negation
wire reg_aclr;
assign reg_aclr = (!devpor) || (!devclrn) || (aclr);
// optional registering parameters
assign dataa_use_reg = (dataa_clock != "none") ? 1'b1 : 1'b0;
assign datab_use_reg = (datab_clock != "none") ? 1'b1 : 1'b0;
assign signa_use_reg = (signa_clock != "none") ? 1'b1 : 1'b0;
assign signb_use_reg = (signb_clock != "none") ? 1'b1 : 1'b0;
assign dataa_pad = ((18-dataa_width) == 0) ? dataa : {{(18-dataa_width){1'b0}},dataa};
assign datab_pad = ((18-datab_width) == 0) ? datab : {{(18-datab_width){1'b0}},datab};
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// Optional input registers for dataa,b and signa,b
cycloneii_mac_data_reg dataa_reg (
.clk(clk),
.data(dataa_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idataa_reg)
);
defparam dataa_reg.data_width = dataa_width;
cycloneii_mac_data_reg datab_reg (
.clk(clk),
.data(datab_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idatab_reg)
);
defparam datab_reg.data_width = datab_width;
cycloneii_mac_sign_reg signa_reg (
.clk(clk),
.d(signa),
.ena(ena),
.aclr(reg_aclr),
.q(isigna_reg)
);
cycloneii_mac_sign_reg signb_reg (
.clk(clk),
.d(signb),
.ena(ena),
.aclr(reg_aclr),
.q(isignb_reg)
);
// mux input sources from direct inputs or optional registers
assign idataa_int = dataa_use_reg == 1'b1 ? idataa_reg : dataa;
assign idatab_int = datab_use_reg == 1'b1 ? idatab_reg : datab;
assign isigna_int = signa_use_reg == 1'b1 ? isigna_reg : signa;
assign isignb_int = signb_use_reg == 1'b1 ? isignb_reg : signb;
cycloneii_mac_mult_internal mac_multiply (
.dataa(idataa_int[dataa_width-1:0]),
.datab(idatab_int[datab_width-1:0]),
.signa(isigna_int),
.signb(isignb_int),
.dataout(dataout)
);
defparam mac_multiply.dataa_width = dataa_width;
defparam mac_multiply.datab_width = datab_width;
defparam mac_multiply.dataout_width = dataout_width;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_out
//
// Description : Cyclone II MAC_OUT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_out
(
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneii_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
tri1 devclrn;
tri1 devpor;
wire [dataa_width-1:0] dataa_ipd; // internal dataa
wire clk_ipd; // internal clk
wire aclr_ipd; // internal aclr
wire ena_ipd; // internal ena
// internal variable
wire [dataout_width-1:0] dataout_tmp;
reg [dataa_width-1:0] idataout_reg; // optional register for dataout output
wire use_reg; // equivalent to dataout_clock parameter
wire enable;
wire no_aclr;
// Input buffers
buf (clk_ipd, clk);
buf (aclr_ipd, aclr);
buf (ena_ipd, ena);
buf dataa_buf [dataa_width-1:0] (dataa_ipd, dataa);
// optional registering parameter
assign use_reg = (output_clock != "none") ? 1 : 0;
assign enable = (!aclr) && (ena) && use_reg;
assign no_aclr = (!aclr) && use_reg;
specify
if (use_reg)
(posedge clk => (dataout +: dataout_tmp)) = 0;
(posedge aclr => (dataout +: 1'b0)) = 0;
ifnone
(dataa *> dataout) = (0, 0);
$setuphold (posedge clk &&& enable, dataa, 0, 0);
$setuphold (posedge clk &&& no_aclr, ena, 0, 0);
endspecify
initial
begin
// initial values for optional register
idataout_reg = 0;
end
// Optional input registers for dataa,b and signa,b
always @ (posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (devclrn == 0 || devpor == 0 || aclr_ipd == 1)
begin
idataout_reg <= 0;
end
else if (ena_ipd == 1)
begin
idataout_reg <= dataa_ipd;
end
end
// mux input sources from direct inputs or optional registers
assign dataout_tmp = use_reg == 1 ? idataout_reg : dataa_ipd;
// accelerate outputs
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
|
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_reset_controller/altera_tse_reset_synchronizer.v#7 $
// $Revision: #7 $
// $Date: 2010/04/27 $
// $Author: jyeap $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
// -----------------------------------------------
(* ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \" set_false_path -to [get_pins -compatibility_mode -nocase *altera_tse_reset_synchronizer_chain*|aclr]; set_false_path -to [get_pins -compatibility_mode -nocase *altera_tse_reset_synchronizer_chain*|clrn] \"" *) (*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
end
else begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
end
end
assign reset_out = altera_tse_reset_synchronizer_chain[0];
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
end
assign reset_out = altera_tse_reset_synchronizer_chain[0];
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFBBP_PP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_PP_BLACKBOX_V
|
// part of NeoGS project (c) 2007-2009 NedoPC
//
// ZXBUS interface module
// Features:
// I. provides IORQGE generation via zxblkiorq_n output on addresses $xxB3, $xxBB and $xx33
// II. Asynchronously outs data_reg_in or data_bit and command bit to zxbus
// III. Asynchronouly latches in data_reg_out and command_reg_out from zxbus
// IV. Synchronously updates data_bit and command_bit according to zxbus activity,
// or sets it to *_bit_in value when *_bit_wr is 1
// V. Generates nmi_n negative 8-clock pulse when $010xxxxx is written to $xx33 port.
// Initiates internal reset when $100xxxxx is written to $xx33 port
// Toggles LED when $001xxxxx is written
// VI. Manages zx-dma
//
module zxbus(
zxid, // zxbus DATA BUS in/out [7:0]
zxa, // zxbus ADDRESS 7-0 in [7:0]
zxa14,zxa15, // zxbus ADDRESS 14,15
zxiorq_n,zxmreq_n, // zxbus /IORQ,/MREQ
zxrd_n,zxwr_n, // zxbus /RD, /WR
zxcsrom_n, // zxbus /CSROM
zxblkiorq_n, // active low - signals to generate IORQGE
zxblkrom_n, // active low - signals to block onboard zx ROM
zxgenwait_n, // active low - signals to generate /WAIT to ZXBUS
zxbusin, // controls 74hct245 buffer direction (1 - input from bus, 0 - output to zx)
zxbusena_n, // 74hct245 buffer enable signal
// ports related
command_reg_out, // output data of command register (asynchronous)
data_reg_out, // output data of data register (asynchronous)
data_reg_in, // input data of data register (asynchronous)
data_bit, // data bit out (synchronous to cpu_clock)
command_bit, // command bit out (synchronous to cpu_clock)
data_bit_in, // input data to be written to data bit
command_bit_in, // input data to be written to command bit
data_bit_wr, // write strobe (positive), which writes data from data_bit_in to data_bit (sync to cpu_clock)
command_bit_wr, // write strobe (positive), which writes data from command_bit_in to command_bit (sync to cpu_clock)
//
// DMA related
dma_on, // input, must be 1 for DMA to operate
wait_ena, // input, asynchronously resets wait trigger (signal synchronous to cpu_clock of NGS)
dmaread, // for use in dma_zx module
dmawrite, //
dma_data_written, // output, stores data last written by ZX
dma_data_toberead, // input, shows data for ZX to read
rst_from_zx_n, // reset out to NGS z80 indicating board must be reset
nmi_n, // nmi out to NGS z80 (2^NMI_CNT_SIZE cpu_clock periods low pulse) - synchronous!
led_toggle,
rst_n, // chip-wide reset input (some critical init)
cpu_clock // NGS Z80 CPU clock in (clk_fpga on schematics)
);
parameter NMI_CNT_SIZE = 2;
localparam GSCOM = 8'hBB;
localparam GSSTAT = GSCOM;
localparam GSDAT = 8'hB3;
localparam GSCTR = 8'h33;
// INPUTS/OUTPUTS of module
inout wire [7:0] zxid;
input [7:0] zxa;
input zxa14,zxa15;
input zxiorq_n,zxmreq_n;
input zxrd_n,zxwr_n;
input zxcsrom_n;
output reg zxblkiorq_n,zxblkrom_n,zxbusin,zxbusena_n,zxgenwait_n;
output reg [7:0] command_reg_out;
output reg [7:0] data_reg_out;
input [7:0] data_reg_in;
output reg data_bit;
output reg command_bit;
input data_bit_in;
input command_bit_in;
input data_bit_wr;
input command_bit_wr;
input dma_on;
output dmaread; // =1 when dma enabled and ZX reads from 0000-3fff and ROM is ON (csrom_n active)
output dmawrite; // =1 when dma enabled and ZX writes to 0000-3fff (no ROM dependent)
input wait_ena;
output reg [7:0] dma_data_written;
input [7:0] dma_data_toberead;
output reg rst_from_zx_n;
output reg nmi_n;
output reg led_toggle;
input cpu_clock;
input rst_n;
// internal regs and wires
wire [7:0] dbin; // input data from zx data bus
reg [7:0] dbout; // output to the zx data bus
wire [7:0] zxlowaddr; // low address on ZX address bus
wire zxdataport; // =1 when data port address selected ($B3)
wire zxcommport; // =1 when command port address selected ($BB)
wire zxrstport; // =1 when reset/nmi port address selected ($33)
wire zxiord_n; // = iorq_n | rd_n
wire zxiowr_n; // = iorq_n | wr_n
wire dmaread; // =1 when dma enabled and ZX reads from 0000-3fff and ROM is ON (csrom_n active)
wire dmawrite; // =1 when dma enabled and ZX writes to 0000-3fff (no ROM dependent)
wire romaddr; // =1 when rom address is on zxbus
reg [2:0] rddataport; // for data_bit
reg [2:0] wrdataport; // synchronous of and
reg [2:0] wrcommport; // control command_bit
reg async_rst_toggle; // asynchronous toggles on writes to port $33
reg async_nmi_toggle;
reg async_led_toggle;
reg [2:0] sync_rst_toggle; // syncing toggles in and detect edges
reg [2:0] sync_nmi_toggle; // generate z80res or nmi on every edge
reg [2:0] sync_led_toggle; // LED toggle on every edge
reg prezxrst1,prezxrst2; // reset out (rst_from_zx_n) must have some negation delay when rst_n asserts
reg [NMI_CNT_SIZE:0] nmi_counter; // counter to make 2^NMI_CNT_SIZE cpu_clock's pulses, plus stopbit
// actual code
//---------------------------------------------------------------------------
// zx data bus control
assign dbin[7:0] = zxid;
// control tri-state in-outs of internal zx data bus (zxid)
/* always @*
begin
if( (!zxbusin) && (!zxbusena_n) )
zxid <= dbout[7:0];
else
zxid <= 8'bZZZZZZZZ;
end
*/
assign zxid = ( !zxbusin && !zxbusena_n ) ? dbout : 8'bZZZZ_ZZZZ;
// control both state of zxid and state of external '245 buffer
always @*
begin
if( ((!zxiord_n) && ( zxdataport || zxcommport )) || dmaread )
zxbusin = 1'b0;
else
zxbusin = 1'b1;
if( ( ((!zxiowr_n) || (!zxiord_n) ) && ( zxdataport || zxcommport || zxrstport )) || dmaread || dmawrite )
zxbusena_n <= 1'b0;
else
zxbusena_n <= 1'b1;
end
// control data to be out on the bus
always @*
begin
if( dmaread )
dbout = dma_data_toberead;
else
case( {zxdataport,zxcommport} )
3'b10: dbout <= data_reg_in;
3'b01: dbout <= { data_bit, 6'bXXXXXX, command_bit };
default: dbout <= 8'hXX;
endcase
end
// +
// zx address decoder, IORQGE generator
assign zxdataport = (zxa == GSDAT); // =1 when $B3
assign zxcommport = (zxa == GSCOM); // =1 when $BB
assign zxrstport = (zxa == GSCTR); // =1 when $33
always @*
begin
if( zxdataport || zxcommport || zxrstport ) // address if any of ports is on bus
zxblkiorq_n <= 1'b0; // generate IORQGE!
else
zxblkiorq_n <= 1'b1;
end
// +
// zx DMA related things
// zx ROM address decoder
assign romaddr = ( {zxa15,zxa14}==2'b00 );
// block zx rom access if dma is on
always @*
begin
if( romaddr && dma_on )
zxblkrom_n = 1'b0;
else
zxblkrom_n = 1'b1;
end
// control /WAIT pin of ZXBUS
always @*
begin
if( dma_on && romaddr && (!zxmreq_n) ) // on write cycles, /WAIT is accepted at the same clock edge
zxgenwait_n = ~wait_ena; // the Z80 begins /WR, so we can't use /WR (and then /RD)
else // for /WAIT strobing
zxgenwait_n = 1'b1;
end
// zx to dma write and read pulses
assign dmaread = dma_on & romaddr & (~zxmreq_n) & (~zxrd_n) & (~zxcsrom_n);
assign dmawrite = dma_on & romaddr & (~zxmreq_n) & (~zxwr_n);
// store data
always @(negedge dmawrite) dma_data_written <= dbin; // probably GLITCHES here!!!
// +
// I/O RD and WR strobes
assign zxiord_n = zxiorq_n | zxrd_n;
assign zxiowr_n = zxiorq_n | zxwr_n;
// +
// write from zxbus to the data register
always @(posedge zxiowr_n)
begin
if( zxdataport )
begin
data_reg_out <= dbin;
end
end
// +
// write from zxbus to the command register
always @(posedge zxiowr_n)
begin
if( zxcommport )
begin
command_reg_out <= dbin;
end
end
// +
// SYNCHRONOUS PART
// ---------------------------------------------------
// synchronous control of port writes and reads
always @(posedge cpu_clock) // sync in read and write states
begin
rddataport[2:0] <= { rddataport[1:0], zxdataport&(~zxiord_n) };
wrdataport[2:0] <= { wrdataport[1:0], zxdataport&(~zxiowr_n) };
wrcommport[2:0] <= { wrcommport[1:0], zxcommport&(~zxiowr_n) };
end
// data_bit
wire data_bit_local_clr = (rddataport[2:1]==2'b10);
wire data_bit_local_set = (wrdataport[2:1]==2'b10);
/* always @(posedge cpu_clock)
begin
if( rddataport[2:1]==2'b10 )
begin
data_bit <= 1'b0; // clear on data port reading by ZX (after end of cycle)
end
else if( wrdataport[2:1]==2'b10 )
begin
data_bit <= 1'b1; // set on data port writing by ZX
end
else if( data_bit_wr==1'b1 )
begin
data_bit <= data_bit_in; // or load from internal NGS operation
end
end
*/
always@(posedge cpu_clock)
case( { data_bit_local_clr, data_bit_local_set, data_bit_wr } )
// usual cases
3'b100: data_bit <= 1'b0; // clear on data port reading by ZX (after end of cycle)
3'b010: data_bit <= 1'b1; // set on data port writing by ZX
3'b001: data_bit <= data_bit_in; // or load from internal NGS operation
// combinational cases
3'b101: begin
if( data_bit_in==1'b0 )
data_bit <= 1'b0;
// else if data_bit_in==1'b1 -- leave unchanged
end
3'b011: begin
if( data_bit_in==1'b1 )
data_bit <= 1'b1;
// else if data_bit_in==1'b0 -- leave unchanged
end
// default: unchanged
endcase
// command bit
wire command_bit_local_set = (wrcommport[2:1]==2'b10);
/*
always @(posedge cpu_clock)
begin
if( wrcommport[2:1]==2'b10 )
begin
command_bit <= 1'b1; // set on command port writing by ZX
end
else if( command_bit_wr==1'b1 )
begin
command_bit <= command_bit_in; // or load from internal NGS operation
end
end
*/
always @(posedge cpu_clock)
case( { command_bit_local_set, command_bit_wr } )
2'b10: command_bit <= 1'b1;
2'b01: command_bit <= command_bit_in;
2'b11: begin
if( command_bit_in==1'b1 )
command_bit <= 1'b1;
end
endcase
///////////////////////////////
// handle reset/nmi port $33 //
///////////////////////////////
always @(negedge rst_n,posedge zxiowr_n)
begin
if( !rst_n )
begin
async_rst_toggle <= 1'b0;
async_nmi_toggle <= 1'b0;
async_led_toggle <= 1'b0;
end
else if( zxrstport )
begin
if( dbin[7:5]==3'b100 )
async_rst_toggle <= ~async_rst_toggle;
if( dbin[7:5]==3'b010 )
async_nmi_toggle <= ~async_nmi_toggle;
if( dbin[7:5]==3'b001 )
async_led_toggle <= ~async_led_toggle;
end
end
// +
always @(negedge rst_n, posedge cpu_clock)
begin
if( !rst_n )
begin
sync_rst_toggle[2:0] <= 3'd0;
sync_nmi_toggle[2:0] <= 3'd0;
sync_led_toggle[2:0] <= 3'd0;
nmi_counter[NMI_CNT_SIZE:0] <= 32'hFFFFFFFF;
prezxrst1 <= 1'b1;
nmi_n <= 1'b1;
led_toggle <= 1'b0;
end
else // rst_n=1
begin
sync_rst_toggle[2:0] <= { sync_rst_toggle[1:0], async_rst_toggle };
sync_nmi_toggle[2:0] <= { sync_nmi_toggle[1:0], async_nmi_toggle };
sync_led_toggle[2:0] <= { sync_led_toggle[1:0], async_led_toggle };
if( sync_rst_toggle[2] != sync_rst_toggle[1] )
begin
prezxrst1 <= 1'b0;
end
if( sync_nmi_toggle[2] != sync_nmi_toggle[1] )
begin
nmi_counter[NMI_CNT_SIZE:0] <= 0;
end
else
begin
if( !nmi_counter[NMI_CNT_SIZE] )
nmi_counter <= nmi_counter + 1;
end
nmi_n <= nmi_counter[NMI_CNT_SIZE];
if( sync_led_toggle[2] != sync_led_toggle[1] )
led_toggle <= 1'b1;
else
led_toggle <= 1'b0;
end
end
// +
always @(posedge cpu_clock)
begin
prezxrst2 <= prezxrst1;
rst_from_zx_n <= prezxrst2;
end
// +
endmodule
|
/**
* The Hack CPU (Central Processing unit), consisting of an ALU,
* two registers named A and D, and a program counter named PC.
* The CPU is designed to fetch and execute instructions written in
* the Hack machine language.
* In particular, functions as follows:
* Executes the inputted instruction according to the Hack machine
* language specification.
* The D and A in the language specification
* refer to CPU-resident registers,
* while M refers to the external memory location addressed by A,
* i.e. to Memory[A].
* The inM input holds the value of this location.
*
* If the current instruction needs
* to write a value to M, the value is placed in outM, the address
* of the target location is placed in the addressM output, and the
* writeM control bit is asserted. (When writeM==0, any value may
* appear in outM).
* The outM and writeM outputs are combinational:
* they are affected instantaneously by the execution of the current
* instruction. The addressM and pc outputs are clocked: although they
* are affected by the execution of the current instruction, they commit
* to their new values only in the next time step. If reset==1 then the
* CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
* than to the address resulting from executing the current instruction.
*
*
* IN inM[16], // M value input (M = contents of RAM[A])
* instruction[16], // Instruction for execution
* reset; // Signals whether to re-start the current
* // program (reset==1) or continue executing
* // the current program (reset==0).
*
* OUT outM[16], // M value output
* writeM, // Write to M?
* addressM[15], // Address in data memory (of M)
* pc[15]; // address of next instruction
*/
module cpu (
input clk,
input reset,
input [15:0] instruction,
input [15:0] inM,
output [15:0] outM,
output [14:0] addressM,
output writeM,
output [14:0] pc,
output [15:0] areg,
output [15:0] dreg
);
// Fastest = 2
//parameter SPEED = 32'd2500000;
parameter SPEED = 32'd5;
reg [15:0] r_outM = 16'b0;
reg [14:0] r_addressM = 15'b0;
reg r_writeM = 0;
reg pc_inc = 0;
reg pc_load = 0;
reg [15:0] pc_in = 0;
wire [15:0] pc_out;
reg [15:0] alu_y = 16'b0;
wire [15:0] alu_out;
wire alu_zr, alu_ng;
assign pc = pc_out[14:0];
assign outM = r_outM;
assign writeM = r_writeM;
assign addressM = r_addressM;
reg [15:0] DRegister = 16'b0;
reg [15:0] ARegister = 16'b0;
assign dreg = DRegister;
assign areg = ARegister;
program_counter program_counter_inst (
.clk(clk),
.reset(reset),
.inc(pc_inc),
.load(pc_load),
.in(pc_in),
.out(pc_out)
);
alu alu_inst(
.x(DRegister),
.y(alu_y),
.zx(instruction[11]),
.nx(instruction[10]),
.zy(instruction[9]),
.ny(instruction[8]),
.f(instruction[7]),
.no(instruction[6]),
.out(alu_out),
.zr(alu_zr),
.ng(alu_ng)
);
// Cpu speed, timer compare must be at least 2
// as three clock cycles are needed per instuction.
reg [31:0] timer = 32'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
timer <= 32'b0;
end else begin
if (timer == SPEED) begin
timer <= 32'd0;
end else begin
timer <= timer + 32'b1;
end
end
end
always @(*) begin
if (timer == 3'd0) begin
// If d3 (instruction[3]) == 1 then write the output of the alu to M (RAM).
if (instruction[15] == 1 && instruction[3] == 1) begin
r_writeM = 1'b1;
end else begin
r_writeM = 1'b0;
end
// Jump instructions
pc_load = 1'b0;
if (instruction[15] == 1) begin
case (instruction[2:0])
3'b001: if (!alu_ng && !alu_zr) pc_load = 1'b1; // JGT alu_out > 0
3'b010: if (alu_zr) pc_load = 1'b1; // JEQ alu_out == 0
3'b011: if (!alu_ng || alu_zr) pc_load = 1'b1; // JGE alu_out >= 0
3'b100: if (alu_ng) pc_load = 1'b1; // JLT alu_out < 0
3'b101: if (!alu_zr) pc_load = 1'b1; // JNE alu_out != 0
3'b110: if (alu_ng || alu_zr) pc_load = 1'b1; // JLE alu_out <= 0
3'b111: pc_load = 1'b1; // JMP
default: pc_load = 1'b0;
endcase
end
pc_inc = 1'b1;
end else begin
pc_inc = 1'b0;
pc_load = 1'b0;
r_writeM = 1'b0;
end
r_addressM = ARegister[14:0];
pc_in = ARegister;
r_outM = alu_out;
end
always @(posedge clk) begin
// Alu_y input: If bit[12], the "a" bit is 1 then use M (inM) otherwise use A register content.
if (instruction[15] == 1 && instruction[12] == 1) begin
alu_y = inM;
end else begin
alu_y = ARegister;
end
end
always @(posedge clk) begin
if (timer == 3'd0) begin
if (instruction[15] == 0) begin
// A instruction
ARegister = {1'b0, instruction[14:0]};
end else begin
// C instruction
if (instruction[5] == 1) begin
ARegister = alu_out;
end
// If bit[4] "d2" is 1 then store ALU out (outM) in the D register
if (instruction[4] == 1) begin
DRegister = alu_out;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S4S_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLYMETAL6S4S_BEHAVIORAL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s4s (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S4S_BEHAVIORAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:37:25 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
// Design : design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
/*------------------------------------------------------------------------------
Purpose
One stage of multicycle division.
------------------------------------------------------------------------------*/
module mips_div_stage #(
parameter WIDTH=32,
parameter STAGE=4
)
(
input[WIDTH-1:0] a,
input[WIDTH-1:0] b,
input[WIDTH-1:0] remainder_in,
output[WIDTH-1:0] quotient_out,
output[WIDTH-1:0] remainder_out
);
wire[WIDTH:0] result_temp[WIDTH:0];
wire[(WIDTH*2)-1:0] qr[WIDTH:0];
wire[WIDTH:0] divisor;
assign qr[WIDTH]={remainder_in,a[WIDTH-1:0]};
assign divisor={1'b0,b[WIDTH-1:0]};
generate
genvar gi;
for(gi=WIDTH;gi>(WIDTH-STAGE);gi=gi-1)
begin:gen
assign result_temp[gi-1]= qr[gi][(WIDTH*2)-1:WIDTH-1]-divisor;
assign qr[gi-1]= result_temp[gi-1][WIDTH] ? {qr[gi][(WIDTH*2)-2:0],1'd0} :
{result_temp[gi-1][WIDTH-1:0],qr[gi][WIDTH-2:0],1'd1};
end
endgenerate
assign quotient_out[WIDTH-1:0]= qr[WIDTH-STAGE][WIDTH-1:0];
assign remainder_out[WIDTH-1:0]= qr[WIDTH-STAGE][(2*WIDTH)-1:WIDTH];
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_pipe_lane.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_pipe_lane.v //
// Description : Implements the PIPE interface PIPELINE for all per lane //
// interface signals //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_pipe_lane.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_pipe_lane #
(
parameter TCQ = 100,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
) (
output wire [ 1:0] pipe_rx_char_is_k_o ,// Pipelined PIPE Rx Char Is K
output wire [31:0] pipe_rx_data_o ,// Pipelined PIPE Rx Data
output wire pipe_rx_valid_o ,// Pipelined PIPE Rx Valid
output wire pipe_rx_data_valid_o ,// Pipelined PIPE Rx Data Valid
output wire [ 2:0] pipe_rx_status_o ,// Pipelined PIPE Rx Status
output wire pipe_rx_phy_status_o ,// Pipelined PIPE Rx Phy Status
output wire pipe_rx_elec_idle_o ,// Pipelined PIPE Rx Electrical Idle
output wire pipe_rx_eqdone_o ,// Pipelined PIPE Rx Eq
output wire pipe_rx_eqlpadaptdone_o ,// Pipelined PIPE Rx Eq
output wire pipe_rx_eqlplffssel_o ,// Pipelined PIPE Rx Eq
output wire [17:0] pipe_rx_eqlpnewtxcoefforpreset_o,// Pipelined PIPE Rx Eq
output wire pipe_rx_startblock_o ,// Pipelined PIPE Rx Start Block
output wire [ 1:0] pipe_rx_syncheader_o ,// Pipelined PIPE Rx Sync Header
output wire pipe_rx_slide_o ,// Pipelined PIPE Rx Slide
output wire pipe_rx_syncdone_o ,// Pipelined PIPE Rx Sync done
input wire pipe_rx_polarity_i ,// PIPE Rx Polarity
input wire [ 1:0] pipe_rx_eqcontrol_i ,// PIPE Rx Eq control
input wire [ 5:0] pipe_rx_eqlplffs_i ,// PIPE Rx Eq
input wire [ 3:0] pipe_rx_eqlptxpreset_i ,// PIPE Rx Eq
input wire [ 2:0] pipe_rx_eqpreset_i ,// PIPE Rx Eq
output wire [17:0] pipe_tx_eqcoeff_o ,// Pipelined Tx Eq Coefficient
output wire pipe_tx_eqdone_o ,// Pipelined Tx Eq Done
input wire pipe_tx_compliance_i ,// PIPE Tx Compliance
input wire [ 1:0] pipe_tx_char_is_k_i ,// PIPE Tx Char Is K
input wire [31:0] pipe_tx_data_i ,// PIPE Tx Data
input wire pipe_tx_elec_idle_i ,// PIPE Tx Electrical Idle
input wire [ 1:0] pipe_tx_powerdown_i ,// PIPE Tx Powerdown
input wire pipe_tx_datavalid_i ,// PIPE Tx Data Valid
input wire pipe_tx_startblock_i ,// PIPE Tx Start Block
input wire [ 1:0] pipe_tx_syncheader_i ,// PIPE Tx Sync Header
input wire [ 1:0] pipe_tx_eqcontrol_i ,// PIPE Tx Eq Control
input wire [ 5:0] pipe_tx_eqdeemph_i ,// PIPE Tx Eq Deemphesis
input wire [ 3:0] pipe_tx_eqpreset_i ,// PIPE Tx Preset
input wire [ 1:0] pipe_rx_char_is_k_i ,// PIPE Rx Char Is K
input wire [31:0] pipe_rx_data_i ,// PIPE Rx Data
input wire pipe_rx_valid_i ,// PIPE Rx Valid
input wire pipe_rx_data_valid_i ,// PIPE Rx Data Valid
input wire [ 2:0] pipe_rx_status_i ,// PIPE Rx Status
input wire pipe_rx_phy_status_i ,// PIPE Rx Phy Status
input wire pipe_rx_elec_idle_i ,// PIPE Rx Electrical Idle
input wire pipe_rx_eqdone_i ,// PIPE Rx Eq
input wire pipe_rx_eqlpadaptdone_i ,// PIPE Rx Eq
input wire pipe_rx_eqlplffssel_i ,// PIPE Rx Eq
input wire [17:0] pipe_rx_eqlpnewtxcoefforpreset_i,// PIPE Rx Eq
input wire pipe_rx_startblock_i ,// PIPE Rx Start Block
input wire [ 1:0] pipe_rx_syncheader_i ,// PIPE Rx Sync Header
input wire pipe_rx_slide_i ,// PIPE Rx Slide
input wire pipe_rx_syncdone_i ,// PIPE Rx Sync done
output wire pipe_rx_polarity_o ,// Pipelined PIPE Rx Polarity
output wire [ 1:0] pipe_rx_eqcontrol_o ,// Pipelined PIPE Rx Eq control
output wire [ 5:0] pipe_rx_eqlplffs_o ,// Pipelined PIPE Rx Eq
output wire [ 3:0] pipe_rx_eqlptxpreset_o ,// Pipelined PIPE Rx Eq
output wire [ 2:0] pipe_rx_eqpreset_o ,// Pipelined PIPE Rx Eq
input wire [17:0] pipe_tx_eqcoeff_i ,// PIPE Tx Eq Coefficient
input wire pipe_tx_eqdone_i ,// PIPE Tx Eq Done
output wire pipe_tx_compliance_o ,// Pipelined PIPE Tx Compliance
output wire [ 1:0] pipe_tx_char_is_k_o ,// Pipelined PIPE Tx Char Is K
output wire [31:0] pipe_tx_data_o ,// Pipelined PIPE Tx Data
output wire pipe_tx_elec_idle_o ,// Pipelined PIPE Tx Electrical Idle
output wire [ 1:0] pipe_tx_powerdown_o ,// Pipelined PIPE Tx Powerdown
output wire pipe_tx_datavalid_o ,// Pipelined PIPE Tx Data Valid
output wire pipe_tx_startblock_o ,// Pipelined PIPE Tx Start Block
output wire [ 1:0] pipe_tx_syncheader_o ,// Pipelined PIPE Tx Sync Header
output wire [ 1:0] pipe_tx_eqcontrol_o ,// Pipelined PIPE Tx Eq Control
output wire [ 5:0] pipe_tx_eqdeemph_o ,// Pipelined PIPE Tx Eq Deemphesis
output wire [ 3:0] pipe_tx_eqpreset_o ,// Pipelined PIPE Tx Preset
input wire pipe_clk ,// PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [31:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_data_valid_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_eqdone_q ;
reg pipe_rx_eqlpadaptdone_q ;
reg pipe_rx_eqlplffssel_q ;
reg [17:0] pipe_rx_eqlpnewtxcoefforpreset_q ;
reg pipe_rx_startblock_q ;
reg [ 1:0] pipe_rx_syncheader_q ;
reg pipe_rx_slide_q ;
reg pipe_rx_syncdone_q ;
reg pipe_rx_polarity_q ;
reg [ 1:0] pipe_rx_eqcontrol_q ;
reg [ 5:0] pipe_rx_eqlplffs_q ;
reg [ 3:0] pipe_rx_eqlptxpreset_q ;
reg [ 2:0] pipe_rx_eqpreset_q ;
reg [17:0] pipe_tx_eqcoeff_q ;
reg pipe_tx_eqdone_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [31:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
reg pipe_tx_datavalid_q ;
reg pipe_tx_startblock_q ;
reg [ 1:0] pipe_tx_syncheader_q ;
reg [ 1:0] pipe_tx_eqcontrol_q ;
reg [ 5:0] pipe_tx_eqdeemph_q ;
reg [ 3:0] pipe_tx_eqpreset_q ;
reg [ 1:0] pipe_rx_char_is_k_qq ;
reg [31:0] pipe_rx_data_qq ;
reg pipe_rx_valid_qq ;
reg pipe_rx_data_valid_qq ;
reg [ 2:0] pipe_rx_status_qq ;
reg pipe_rx_phy_status_qq ;
reg pipe_rx_elec_idle_qq ;
reg pipe_rx_eqdone_qq ;
reg pipe_rx_eqlpadaptdone_qq ;
reg pipe_rx_eqlplffssel_qq ;
reg [17:0] pipe_rx_eqlpnewtxcoefforpreset_qq ;
reg pipe_rx_startblock_qq ;
reg [ 1:0] pipe_rx_syncheader_qq ;
reg pipe_rx_slide_qq ;
reg pipe_rx_syncdone_qq ;
reg pipe_rx_polarity_qq ;
reg [ 1:0] pipe_rx_eqcontrol_qq ;
reg [ 5:0] pipe_rx_eqlplffs_qq ;
reg [ 3:0] pipe_rx_eqlptxpreset_qq ;
reg [ 2:0] pipe_rx_eqpreset_qq ;
reg [17:0] pipe_tx_eqcoeff_qq ;
reg pipe_tx_eqdone_qq ;
reg pipe_tx_compliance_qq ;
reg [ 1:0] pipe_tx_char_is_k_qq ;
reg [31:0] pipe_tx_data_qq ;
reg pipe_tx_elec_idle_qq ;
reg [ 1:0] pipe_tx_powerdown_qq ;
reg pipe_tx_datavalid_qq ;
reg pipe_tx_startblock_qq ;
reg [ 1:0] pipe_tx_syncheader_qq ;
reg [ 1:0] pipe_tx_eqcontrol_qq ;
reg [ 5:0] pipe_tx_eqdeemph_qq ;
reg [ 3:0] pipe_tx_eqpreset_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i ;
assign pipe_rx_data_o = pipe_rx_data_i ;
assign pipe_rx_valid_o = pipe_rx_valid_i ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_i ;
assign pipe_rx_status_o = pipe_rx_status_i ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_i ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_i ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_i ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_i ;
assign pipe_rx_startblock_o = pipe_rx_startblock_i ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_i ;
assign pipe_rx_slide_o = pipe_rx_slide_i ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_i ;
assign pipe_rx_polarity_o = pipe_rx_polarity_i ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_i ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_i ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_i ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_i ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_i ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_i ;
assign pipe_tx_compliance_o = pipe_tx_compliance_i ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i ;
assign pipe_tx_data_o = pipe_tx_data_i ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_i ;
assign pipe_tx_startblock_o = pipe_tx_startblock_i ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_i ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_i ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_i ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_i ;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_rx_char_is_k_q <= #TCQ 2'b00;
pipe_rx_data_q <= #TCQ 32'h00000000;
pipe_rx_valid_q <= #TCQ 1'b0;
pipe_rx_data_valid_q <= #TCQ 1'b0;
pipe_rx_status_q <= #TCQ 2'b00;
pipe_rx_phy_status_q <= #TCQ 1'b0;
pipe_rx_elec_idle_q <= #TCQ 1'b1;
pipe_rx_eqdone_q <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_q <= #TCQ 1'b0;
pipe_rx_eqlplffssel_q <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ 17'b00000000000000000;
pipe_rx_startblock_q <= #TCQ 1'b0;
pipe_rx_syncheader_q <= #TCQ 2'b00;
pipe_rx_slide_q <= #TCQ 1'b0;
pipe_rx_syncdone_q <= #TCQ 1'b0;
pipe_rx_polarity_q <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_q <= #TCQ 1'b0;
pipe_rx_eqlplffs_q <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_q <= #TCQ 2'b00;
pipe_rx_eqpreset_q <= #TCQ 6'b000000;
pipe_tx_eqcoeff_q <= #TCQ 4'h0;
pipe_tx_eqdone_q <= #TCQ 3'b000;
pipe_tx_compliance_q <= #TCQ 1'b0;
pipe_tx_char_is_k_q <= #TCQ 2'b00;
pipe_tx_data_q <= #TCQ 32'h00000000;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b00;
pipe_tx_datavalid_q <= #TCQ 1'b0;
pipe_tx_startblock_q <= #TCQ 1'b0;
pipe_tx_syncheader_q <= #TCQ 2'b00;
pipe_tx_eqcontrol_q <= #TCQ 2'b00;
pipe_tx_eqdeemph_q <= #TCQ 6'b000000;
pipe_tx_eqpreset_q <= #TCQ 4'h0;
end
else
begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i ;
pipe_rx_data_q <= #TCQ pipe_rx_data_i ;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i ;
pipe_rx_data_valid_q <= #TCQ pipe_rx_data_valid_i ;
pipe_rx_status_q <= #TCQ pipe_rx_status_i ;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i ;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i ;
pipe_rx_eqdone_q <= #TCQ pipe_rx_eqdone_i ;
pipe_rx_eqlpadaptdone_q <= #TCQ pipe_rx_eqlpadaptdone_i ;
pipe_rx_eqlplffssel_q <= #TCQ pipe_rx_eqlplffssel_i ;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ pipe_rx_eqlpnewtxcoefforpreset_i ;
pipe_rx_startblock_q <= #TCQ pipe_rx_startblock_i ;
pipe_rx_syncheader_q <= #TCQ pipe_rx_syncheader_i ;
pipe_rx_slide_q <= #TCQ pipe_rx_slide_i ;
pipe_rx_syncdone_q <= #TCQ pipe_rx_syncdone_i ;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i ;
pipe_rx_eqcontrol_q <= #TCQ pipe_rx_eqcontrol_i ;
pipe_rx_eqlplffs_q <= #TCQ pipe_rx_eqlplffs_i ;
pipe_rx_eqlptxpreset_q <= #TCQ pipe_rx_eqlptxpreset_i ;
pipe_rx_eqpreset_q <= #TCQ pipe_rx_eqpreset_i ;
pipe_tx_eqcoeff_q <= #TCQ pipe_tx_eqcoeff_i ;
pipe_tx_eqdone_q <= #TCQ pipe_tx_eqdone_i ;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i ;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i ;
pipe_tx_data_q <= #TCQ pipe_tx_data_i ;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i ;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i ;
pipe_tx_datavalid_q <= #TCQ pipe_tx_datavalid_i ;
pipe_tx_startblock_q <= #TCQ pipe_tx_startblock_i ;
pipe_tx_syncheader_q <= #TCQ pipe_tx_syncheader_i ;
pipe_tx_eqcontrol_q <= #TCQ pipe_tx_eqcontrol_i ;
pipe_tx_eqdeemph_q <= #TCQ pipe_tx_eqdeemph_i ;
pipe_tx_eqpreset_q <= #TCQ pipe_tx_eqpreset_i ;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q ;
assign pipe_rx_data_o = pipe_rx_data_q ;
assign pipe_rx_valid_o = pipe_rx_valid_q ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_q ;
assign pipe_rx_status_o = pipe_rx_status_q ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_q ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_q ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_q ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_q ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_q ;
assign pipe_rx_startblock_o = pipe_rx_startblock_q ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_q ;
assign pipe_rx_slide_o = pipe_rx_slide_q ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_q ;
assign pipe_rx_polarity_o = pipe_rx_polarity_q ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_q ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_q ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_q ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_q ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_q ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_q ;
assign pipe_tx_compliance_o = pipe_tx_compliance_q ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q ;
assign pipe_tx_data_o = pipe_tx_data_q ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_q ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_q ;
assign pipe_tx_startblock_o = pipe_tx_startblock_q ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_q ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_q ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_q ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_q ;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_rx_char_is_k_q <= #TCQ 2'b00;
pipe_rx_data_q <= #TCQ 32'h00000000;
pipe_rx_valid_q <= #TCQ 1'b0;
pipe_rx_data_valid_q <= #TCQ 1'b0;
pipe_rx_status_q <= #TCQ 2'b00;
pipe_rx_phy_status_q <= #TCQ 1'b0;
pipe_rx_elec_idle_q <= #TCQ 1'b1;
pipe_rx_eqdone_q <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_q <= #TCQ 1'b0;
pipe_rx_eqlplffssel_q <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ 17'b00000000000000000;
pipe_rx_startblock_q <= #TCQ 1'b0;
pipe_rx_syncheader_q <= #TCQ 2'b00;
pipe_rx_slide_q <= #TCQ 1'b0;
pipe_rx_syncdone_q <= #TCQ 1'b0;
pipe_rx_polarity_q <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_q <= #TCQ 1'b0;
pipe_rx_eqlplffs_q <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_q <= #TCQ 2'b00;
pipe_rx_eqpreset_q <= #TCQ 6'b000000;
pipe_tx_eqcoeff_q <= #TCQ 4'h0;
pipe_tx_eqdone_q <= #TCQ 3'b000;
pipe_tx_compliance_q <= #TCQ 1'b0;
pipe_tx_char_is_k_q <= #TCQ 2'b00;
pipe_tx_data_q <= #TCQ 32'h00000000;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b00;
pipe_tx_datavalid_q <= #TCQ 1'b0;
pipe_tx_startblock_q <= #TCQ 1'b0;
pipe_tx_syncheader_q <= #TCQ 2'b00;
pipe_tx_eqcontrol_q <= #TCQ 2'b00;
pipe_tx_eqdeemph_q <= #TCQ 6'b000000;
pipe_tx_eqpreset_q <= #TCQ 4'h0;
pipe_rx_char_is_k_qq <= #TCQ 2'b00;
pipe_rx_data_qq <= #TCQ 32'h00000000;
pipe_rx_valid_qq <= #TCQ 1'b0;
pipe_rx_data_valid_qq <= #TCQ 1'b0;
pipe_rx_status_qq <= #TCQ 2'b00;
pipe_rx_phy_status_qq <= #TCQ 1'b0;
pipe_rx_elec_idle_qq <= #TCQ 1'b1;
pipe_rx_eqdone_qq <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_qq <= #TCQ 1'b0;
pipe_rx_eqlplffssel_qq <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_qq<= #TCQ 17'b00000000000000000;
pipe_rx_startblock_qq <= #TCQ 1'b0;
pipe_rx_syncheader_qq <= #TCQ 2'b00;
pipe_rx_slide_qq <= #TCQ 1'b0;
pipe_rx_syncdone_qq <= #TCQ 1'b0;
pipe_rx_polarity_qq <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_qq <= #TCQ 1'b0;
pipe_rx_eqlplffs_qq <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_qq <= #TCQ 2'b00;
pipe_rx_eqpreset_qq <= #TCQ 6'b000000;
pipe_tx_eqcoeff_qq <= #TCQ 4'h0;
pipe_tx_eqdone_qq <= #TCQ 3'b000;
pipe_tx_compliance_qq <= #TCQ 1'b0;
pipe_tx_char_is_k_qq <= #TCQ 2'b00;
pipe_tx_data_qq <= #TCQ 32'h00000000;
pipe_tx_elec_idle_qq <= #TCQ 1'b1;
pipe_tx_powerdown_qq <= #TCQ 2'b00;
pipe_tx_datavalid_qq <= #TCQ 1'b0;
pipe_tx_startblock_qq <= #TCQ 1'b0;
pipe_tx_syncheader_qq <= #TCQ 2'b00;
pipe_tx_eqcontrol_qq <= #TCQ 2'b00;
pipe_tx_eqdeemph_qq <= #TCQ 6'b000000;
pipe_tx_eqpreset_qq <= #TCQ 4'h0;
end
else
begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i ;
pipe_rx_data_q <= #TCQ pipe_rx_data_i ;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i ;
pipe_rx_data_valid_q <= #TCQ pipe_rx_data_valid_i ;
pipe_rx_status_q <= #TCQ pipe_rx_status_i ;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i ;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i ;
pipe_rx_eqdone_q <= #TCQ pipe_rx_eqdone_i ;
pipe_rx_eqlpadaptdone_q <= #TCQ pipe_rx_eqlpadaptdone_i ;
pipe_rx_eqlplffssel_q <= #TCQ pipe_rx_eqlplffssel_i ;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ pipe_rx_eqlpnewtxcoefforpreset_i ;
pipe_rx_startblock_q <= #TCQ pipe_rx_startblock_i ;
pipe_rx_syncheader_q <= #TCQ pipe_rx_syncheader_i ;
pipe_rx_slide_q <= #TCQ pipe_rx_slide_i ;
pipe_rx_syncdone_q <= #TCQ pipe_rx_syncdone_i ;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i ;
pipe_rx_eqcontrol_q <= #TCQ pipe_rx_eqcontrol_i ;
pipe_rx_eqlplffs_q <= #TCQ pipe_rx_eqlplffs_i ;
pipe_rx_eqlptxpreset_q <= #TCQ pipe_rx_eqlptxpreset_i ;
pipe_rx_eqpreset_q <= #TCQ pipe_rx_eqpreset_i ;
pipe_tx_eqcoeff_q <= #TCQ pipe_tx_eqcoeff_i ;
pipe_tx_eqdone_q <= #TCQ pipe_tx_eqdone_i ;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i ;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i ;
pipe_tx_data_q <= #TCQ pipe_tx_data_i ;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i ;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i ;
pipe_tx_datavalid_q <= #TCQ pipe_tx_datavalid_i ;
pipe_tx_startblock_q <= #TCQ pipe_tx_startblock_i ;
pipe_tx_syncheader_q <= #TCQ pipe_tx_syncheader_i ;
pipe_tx_eqcontrol_q <= #TCQ pipe_tx_eqcontrol_i ;
pipe_tx_eqdeemph_q <= #TCQ pipe_tx_eqdeemph_i ;
pipe_tx_eqpreset_q <= #TCQ pipe_tx_eqpreset_i ;
pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q ;
pipe_rx_data_qq <= #TCQ pipe_rx_data_q ;
pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q ;
pipe_rx_data_valid_qq <= #TCQ pipe_rx_data_valid_q ;
pipe_rx_status_qq <= #TCQ pipe_rx_status_q ;
pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q ;
pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q ;
pipe_rx_eqdone_qq <= #TCQ pipe_rx_eqdone_q ;
pipe_rx_eqlpadaptdone_qq <= #TCQ pipe_rx_eqlpadaptdone_q ;
pipe_rx_eqlplffssel_qq <= #TCQ pipe_rx_eqlplffssel_q ;
pipe_rx_eqlpnewtxcoefforpreset_qq<= #TCQ pipe_rx_eqlpnewtxcoefforpreset_q ;
pipe_rx_startblock_qq <= #TCQ pipe_rx_startblock_q ;
pipe_rx_syncheader_qq <= #TCQ pipe_rx_syncheader_q ;
pipe_rx_slide_qq <= #TCQ pipe_rx_slide_q ;
pipe_rx_syncdone_qq <= #TCQ pipe_rx_syncdone_q ;
pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q ;
pipe_rx_eqcontrol_qq <= #TCQ pipe_rx_eqcontrol_q ;
pipe_rx_eqlplffs_qq <= #TCQ pipe_rx_eqlplffs_q ;
pipe_rx_eqlptxpreset_qq <= #TCQ pipe_rx_eqlptxpreset_q ;
pipe_rx_eqpreset_qq <= #TCQ pipe_rx_eqpreset_q ;
pipe_tx_eqcoeff_qq <= #TCQ pipe_tx_eqcoeff_q ;
pipe_tx_eqdone_qq <= #TCQ pipe_tx_eqdone_q ;
pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q ;
pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q ;
pipe_tx_data_qq <= #TCQ pipe_tx_data_q ;
pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q ;
pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q ;
pipe_tx_datavalid_qq <= #TCQ pipe_tx_datavalid_q ;
pipe_tx_startblock_qq <= #TCQ pipe_tx_startblock_q ;
pipe_tx_syncheader_qq <= #TCQ pipe_tx_syncheader_q ;
pipe_tx_eqcontrol_qq <= #TCQ pipe_tx_eqcontrol_q ;
pipe_tx_eqdeemph_qq <= #TCQ pipe_tx_eqdeemph_q ;
pipe_tx_eqpreset_qq <= #TCQ pipe_tx_eqpreset_q ;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq ;
assign pipe_rx_data_o = pipe_rx_data_qq ;
assign pipe_rx_valid_o = pipe_rx_valid_qq ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_qq ;
assign pipe_rx_status_o = pipe_rx_status_qq ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_qq ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_qq ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_qq ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_qq ;
assign pipe_rx_startblock_o = pipe_rx_startblock_qq ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_qq ;
assign pipe_rx_slide_o = pipe_rx_slide_qq ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_qq ;
assign pipe_rx_polarity_o = pipe_rx_polarity_qq ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_qq ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_qq ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_qq ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_qq ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_qq ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_qq ;
assign pipe_tx_compliance_o = pipe_tx_compliance_qq ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq ;
assign pipe_tx_data_o = pipe_tx_data_qq ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_qq ;
assign pipe_tx_startblock_o = pipe_tx_startblock_qq ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_qq ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_qq ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_qq ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_qq ;
end // if (PIPE_PIPELINE_STAGES == 2)
// Default to zero pipeline stages if PIPE_PIPELINE_STAGES != 0,1,2
else begin
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i ;
assign pipe_rx_data_o = pipe_rx_data_i ;
assign pipe_rx_valid_o = pipe_rx_valid_i ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_i ;
assign pipe_rx_status_o = pipe_rx_status_i ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_i ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_i ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_i ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_i ;
assign pipe_rx_startblock_o = pipe_rx_startblock_i ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_i ;
assign pipe_rx_slide_o = pipe_rx_slide_i ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_i ;
assign pipe_rx_polarity_o = pipe_rx_polarity_i ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_i ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_i ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_i ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_i ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_i ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_i ;
assign pipe_tx_compliance_o = pipe_tx_compliance_i ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i ;
assign pipe_tx_data_o = pipe_tx_data_i ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_i ;
assign pipe_tx_startblock_o = pipe_tx_startblock_i ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_i ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_i ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_i ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_i ;
end
endgenerate
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_qspi_media_2(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [7:0] io_ctrl_dla_cssck,
input [7:0] io_ctrl_dla_sckcs,
input [7:0] io_ctrl_dla_intercs,
input [7:0] io_ctrl_dla_interxfr,
input io_ctrl_cs_id,
input io_ctrl_cs_dflt_0,
output io_link_tx_ready,
input io_link_tx_valid,
input [7:0] io_link_tx_bits,
output io_link_rx_valid,
output [7:0] io_link_rx_bits,
input [7:0] io_link_cnt,
input [1:0] io_link_fmt_proto,
input io_link_fmt_endian,
input io_link_fmt_iodir,
input io_link_cs_set,
input io_link_cs_clear,
input io_link_cs_hold,
output io_link_active
);
wire phy_clock;
wire phy_reset;
wire phy_io_port_sck;
wire phy_io_port_dq_0_i;
wire phy_io_port_dq_0_o;
wire phy_io_port_dq_0_oe;
wire phy_io_port_dq_1_i;
wire phy_io_port_dq_1_o;
wire phy_io_port_dq_1_oe;
wire phy_io_port_dq_2_i;
wire phy_io_port_dq_2_o;
wire phy_io_port_dq_2_oe;
wire phy_io_port_dq_3_i;
wire phy_io_port_dq_3_o;
wire phy_io_port_dq_3_oe;
wire phy_io_port_cs_0;
wire [11:0] phy_io_ctrl_sck_div;
wire phy_io_ctrl_sck_pol;
wire phy_io_ctrl_sck_pha;
wire [1:0] phy_io_ctrl_fmt_proto;
wire phy_io_ctrl_fmt_endian;
wire phy_io_ctrl_fmt_iodir;
wire phy_io_op_ready;
wire phy_io_op_valid;
wire phy_io_op_bits_fn;
wire phy_io_op_bits_stb;
wire [7:0] phy_io_op_bits_cnt;
wire [7:0] phy_io_op_bits_data;
wire phy_io_rx_valid;
wire [7:0] phy_io_rx_bits;
reg cs_id;
reg [31:0] GEN_5;
reg cs_dflt_0;
reg [31:0] GEN_52;
reg cs_set;
reg [31:0] GEN_53;
wire [1:0] GEN_48;
wire [1:0] T_162;
wire [1:0] GEN_49;
wire [1:0] T_163;
wire T_164;
wire cs_active_0;
wire cs_update;
reg clear;
reg [31:0] GEN_54;
reg cs_assert;
reg [31:0] GEN_55;
wire T_175;
wire T_176;
wire cs_deassert;
wire T_177;
wire T_178;
wire continuous;
reg [1:0] state;
reg [31:0] GEN_56;
wire T_182;
wire [1:0] GEN_0;
wire [7:0] GEN_1;
wire [1:0] GEN_2;
wire T_184;
wire T_186;
wire [1:0] GEN_3;
wire GEN_4;
wire GEN_6;
wire GEN_7;
wire [1:0] GEN_8;
wire [7:0] GEN_9;
wire [1:0] GEN_10;
wire GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire T_188;
wire T_189;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire [7:0] GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire T_194;
wire T_195;
wire [7:0] GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire [7:0] GEN_26;
wire [1:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire T_198;
wire T_200;
wire T_201;
wire [1:0] GEN_36;
wire GEN_37;
wire [7:0] GEN_38;
wire [1:0] GEN_39;
wire T_202;
wire [1:0] GEN_50;
wire [1:0] T_206;
wire [1:0] GEN_51;
wire [1:0] T_207;
wire T_208;
wire T_213_0;
wire GEN_40;
wire [1:0] GEN_41;
wire [7:0] GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire [1:0] GEN_47;
sirv_qspi_physical_2 phy (
.clock(phy_clock),
.reset(phy_reset),
.io_port_sck(phy_io_port_sck),
.io_port_dq_0_i(phy_io_port_dq_0_i),
.io_port_dq_0_o(phy_io_port_dq_0_o),
.io_port_dq_0_oe(phy_io_port_dq_0_oe),
.io_port_dq_1_i(phy_io_port_dq_1_i),
.io_port_dq_1_o(phy_io_port_dq_1_o),
.io_port_dq_1_oe(phy_io_port_dq_1_oe),
.io_port_dq_2_i(phy_io_port_dq_2_i),
.io_port_dq_2_o(phy_io_port_dq_2_o),
.io_port_dq_2_oe(phy_io_port_dq_2_oe),
.io_port_dq_3_i(phy_io_port_dq_3_i),
.io_port_dq_3_o(phy_io_port_dq_3_o),
.io_port_dq_3_oe(phy_io_port_dq_3_oe),
.io_port_cs_0(phy_io_port_cs_0),
.io_ctrl_sck_div(phy_io_ctrl_sck_div),
.io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
.io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
.io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
.io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
.io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
.io_op_ready(phy_io_op_ready),
.io_op_valid(phy_io_op_valid),
.io_op_bits_fn(phy_io_op_bits_fn),
.io_op_bits_stb(phy_io_op_bits_stb),
.io_op_bits_cnt(phy_io_op_bits_cnt),
.io_op_bits_data(phy_io_op_bits_data),
.io_rx_valid(phy_io_rx_valid),
.io_rx_bits(phy_io_rx_bits)
);
assign io_port_sck = phy_io_port_sck;
assign io_port_dq_0_o = phy_io_port_dq_0_o;
assign io_port_dq_0_oe = phy_io_port_dq_0_oe;
assign io_port_dq_1_o = phy_io_port_dq_1_o;
assign io_port_dq_1_oe = phy_io_port_dq_1_oe;
assign io_port_dq_2_o = phy_io_port_dq_2_o;
assign io_port_dq_2_oe = phy_io_port_dq_2_oe;
assign io_port_dq_3_o = phy_io_port_dq_3_o;
assign io_port_dq_3_oe = phy_io_port_dq_3_oe;
assign io_port_cs_0 = cs_dflt_0;
assign io_link_tx_ready = GEN_31;
assign io_link_rx_valid = phy_io_rx_valid;
assign io_link_rx_bits = phy_io_rx_bits;
assign io_link_active = cs_assert;
assign phy_clock = clock;
assign phy_reset = reset;
assign phy_io_port_dq_0_i = io_port_dq_0_i;
assign phy_io_port_dq_1_i = io_port_dq_1_i;
assign phy_io_port_dq_2_i = io_port_dq_2_i;
assign phy_io_port_dq_3_i = io_port_dq_3_i;
assign phy_io_ctrl_sck_div = io_ctrl_sck_div;
assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol;
assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha;
assign phy_io_ctrl_fmt_proto = io_link_fmt_proto;
assign phy_io_ctrl_fmt_endian = io_link_fmt_endian;
assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir;
assign phy_io_op_valid = GEN_37;
assign phy_io_op_bits_fn = GEN_28;
assign phy_io_op_bits_stb = GEN_43;
assign phy_io_op_bits_cnt = GEN_42;
assign phy_io_op_bits_data = io_link_tx_bits;
assign GEN_48 = {{1'd0}, io_link_cs_set};
assign T_162 = GEN_48 << io_ctrl_cs_id;
assign GEN_49 = {{1'd0}, io_ctrl_cs_dflt_0};
assign T_163 = GEN_49 ^ T_162;
assign T_164 = T_163[0];
assign cs_active_0 = T_164;
assign cs_update = cs_active_0 != cs_dflt_0;
assign T_175 = io_link_cs_hold == 1'h0;
assign T_176 = cs_update & T_175;
assign cs_deassert = clear | T_176;
assign T_177 = io_link_cs_clear & cs_assert;
assign T_178 = clear | T_177;
assign continuous = io_ctrl_dla_interxfr == 8'h0;
assign T_182 = 2'h0 == state;
assign GEN_0 = phy_io_op_ready ? 2'h2 : state;
assign GEN_1 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt;
assign GEN_2 = cs_deassert ? GEN_0 : state;
assign T_184 = cs_deassert == 1'h0;
assign T_186 = phy_io_op_ready & phy_io_op_valid;
assign GEN_3 = T_186 ? 2'h1 : GEN_2;
assign GEN_4 = T_184 ? 1'h0 : 1'h1;
assign GEN_6 = T_184 ? io_link_tx_valid : 1'h1;
assign GEN_7 = T_184 ? phy_io_op_ready : 1'h0;
assign GEN_8 = T_184 ? GEN_3 : GEN_2;
assign GEN_9 = cs_assert ? GEN_1 : io_link_cnt;
assign GEN_10 = cs_assert ? GEN_8 : state;
assign GEN_11 = cs_assert ? GEN_4 : 1'h1;
assign GEN_12 = cs_assert ? T_184 : 1'h0;
assign GEN_13 = cs_assert ? GEN_6 : 1'h1;
assign GEN_14 = cs_assert ? GEN_7 : 1'h0;
assign T_188 = cs_assert == 1'h0;
assign T_189 = T_188 & io_link_tx_valid;
assign GEN_15 = phy_io_op_ready ? 1'h1 : cs_assert;
assign GEN_16 = phy_io_op_ready ? io_link_cs_set : cs_set;
assign GEN_17 = phy_io_op_ready ? cs_active_0 : cs_dflt_0;
assign GEN_18 = T_189 ? io_ctrl_dla_cssck : GEN_9;
assign GEN_19 = T_189 ? GEN_15 : cs_assert;
assign GEN_20 = T_189 ? GEN_16 : cs_set;
assign GEN_21 = T_189 ? GEN_17 : cs_dflt_0;
assign T_194 = io_link_tx_valid == 1'h0;
assign T_195 = T_188 & T_194;
assign GEN_22 = T_195 ? 8'h0 : GEN_18;
assign GEN_23 = T_195 ? 1'h1 : GEN_12;
assign GEN_24 = T_195 ? io_ctrl_cs_id : cs_id;
assign GEN_25 = T_195 ? io_ctrl_cs_dflt_0 : GEN_21;
assign GEN_26 = T_182 ? GEN_22 : io_link_cnt;
assign GEN_27 = T_182 ? GEN_10 : state;
assign GEN_28 = T_182 ? GEN_11 : 1'h1;
assign GEN_29 = T_182 ? GEN_23 : 1'h0;
assign GEN_30 = T_182 ? GEN_13 : 1'h1;
assign GEN_31 = T_182 ? GEN_14 : 1'h0;
assign GEN_32 = T_182 ? GEN_19 : cs_assert;
assign GEN_33 = T_182 ? GEN_20 : cs_set;
assign GEN_34 = T_182 ? GEN_25 : cs_dflt_0;
assign GEN_35 = T_182 ? GEN_24 : cs_id;
assign T_198 = 2'h1 == state;
assign T_200 = continuous == 1'h0;
assign T_201 = phy_io_op_ready | continuous;
assign GEN_36 = T_201 ? 2'h0 : GEN_27;
assign GEN_37 = T_198 ? T_200 : GEN_30;
assign GEN_38 = T_198 ? io_ctrl_dla_interxfr : GEN_26;
assign GEN_39 = T_198 ? GEN_36 : GEN_27;
assign T_202 = 2'h2 == state;
assign GEN_50 = {{1'd0}, cs_set};
assign T_206 = GEN_50 << cs_id;
assign GEN_51 = {{1'd0}, cs_dflt_0};
assign T_207 = GEN_51 ^ T_206;
assign T_208 = T_207[0];
assign T_213_0 = T_208;
assign GEN_40 = phy_io_op_ready ? T_213_0 : GEN_34;
assign GEN_41 = phy_io_op_ready ? 2'h0 : GEN_39;
assign GEN_42 = T_202 ? io_ctrl_dla_intercs : GEN_38;
assign GEN_43 = T_202 ? 1'h1 : GEN_29;
assign GEN_44 = T_202 ? 1'h0 : GEN_32;
assign GEN_45 = T_202 ? 1'h0 : T_178;
assign GEN_46 = T_202 ? GEN_40 : GEN_34;
assign GEN_47 = T_202 ? GEN_41 : GEN_39;
always @(posedge clock or posedge reset)
if(reset) begin
cs_id <= 2'b0;
cs_dflt_0 <= 1'b1;
cs_set <= 1'b0;
end
else begin//{
if (T_182) begin
if (T_195) begin
cs_id <= io_ctrl_cs_id;
end
end
if (T_202) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= T_213_0;
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_set <= io_link_cs_set;
end
end
end
end//}
always @(posedge clock or posedge reset)
if (reset) begin
clear <= 1'h0;
end else begin
if (T_202) begin
clear <= 1'h0;
end else begin
clear <= T_178;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_assert <= 1'h0;
end else begin
if (T_202) begin
cs_assert <= 1'h0;
end else begin
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_assert <= 1'h1;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (T_202) begin
if (phy_io_op_ready) begin
state <= 2'h0;
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_2_V
`define SKY130_FD_SC_HD__NOR3_2_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_2_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: CoarseDelay.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module CoarseDelay (
address,
clock,
q);
input [2:0] address;
input clock;
output [63:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "CDly"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "CoarseDelay.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
// Retrieval info: PRIVATE: WidthData NUMERIC "64"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "CoarseDelay.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CDly"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL address[2..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_a 0 0 64 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Import Maps.
Require Import Smallstep.
Require Import Types.
(* ################################################################# *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core
calculus embodying the key concept of _functional abstraction_,
which shows up in pretty much every real-world programming
language in some form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous chapter
when formalizing this calculus (syntax, small-step semantics,
typing rules) and its main properties (progress and preservation).
The new technical challenges arise from the mechanisms of
_variable binding_ and _substitution_. It which will take some
work to deal with these. *)
(* ================================================================= *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_:
booleans, numbers, strings, etc. The exact choice of base types
doesn't matter much -- the construction of the language and its
theoretical properties work out the same no matter what we
choose -- so for the sake of brevity let's take just [Bool] for
the moment. At the end of the chapter we'll see how to add more
base types, and in later chapters we'll enrich the pure STLC with
other useful constructs like pairs, records, subtyping, and
mutable state.
Starting from boolean constants and conditionals, we add three
things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out first in informal BNF notation -- we'll
formalize it below). *)
(**
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol in a function abstraction [\x:T1.t2] is generally
written as a Greek letter "lambda" (hence the name of the
calculus). The variable [x] is called the _parameter_ to the
function; the term [t2] is its _body_. The annotation [:T1]
specifies the type of arguments that the function can be applied
to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (As in Coq, a two-argument function is really
a one-argument function whose body is also a one-argument
function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
As in Coq, application associates to the left -- i.e., this
expression is parsed as [((\x:Bool. \y:Bool. x) false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
The STLC doesn't provide any primitive syntax for defining _named_
functions -- all functions are "anonymous." We'll see in chapter
[MoreStlc] that it is easy to add named functions to what we've
got -- indeed, the fundamental naming and binding mechanisms are
exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool]
(i.e., [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool] *)
(* ================================================================= *)
(** ** Syntax *)
(** We begin by formalizing the syntax of the STLC. *)
Module STLC.
(* ----------------------------------------------------------------- *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ----------------------------------------------------------------- *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ================================================================= *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin,
as always, by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ----------------------------------------------------------------- *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T. t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T. t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge Gallina,
makes the first choice -- for example,
Compute (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(** Finally, we must consider what constitutes a _complete_ program.
Intuitively, a "complete program" must not refer to any undefined
variables. We'll see shortly how to define the _free_ variables
in a STLC term. A complete program is _closed_ -- that is, it
contains no free variables.
Having made the choice not to reduce under abstractions, we don't
need to worry about whether variables are values, since we'll
always be reducing programs "from the outside in," and that means
the [step] relation will always be working with closed terms. *)
(* ----------------------------------------------------------------- *)
(** *** Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term. This
operation is used below to define the operational semantics of
function application, where we will need to substitute the
argument term for the function parameter in the function's body.
For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given term [s]
for occurrences of some variable [x] in another term [t]. In
informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)]
yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)]
yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11. t12) = \x:T11. t12
[x:=s](\y:T11. t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
*)
(** ... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if beq_id x x' then s else t
| tabs x' T t1 =>
tabs x' T (if beq_id x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x] that include
binders for all of the variables they mention), we can avoid this
extra complexity here, but it must be dealt with when formalizing
richer languages. *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors and prove that the relation you've defined coincides
with the function given above. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
(* FILL IN HERE *)
.
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the
same pattern as the ones we have seen before. Intuitively, to
reduce a function application, we first reduce its left-hand
side (the function) until it becomes an abstraction; then we
reduce its right-hand side (the argument) until it is also a
value; and finally we substitute the argument for the bound
variable in the body of the abstraction. This last rule, written
informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ----------------------------------------------------------------- *)
(** *** Examples *)
(** Example:
((\x:Bool->Bool. x) (\x:Bool. x)) ==>* (\x:Bool. x)
i.e.,
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x)))
==>* (\x:Bool. x)
i.e.,
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) (\x:Bool. if x then false
else true)) true)
==>* false
i.e.,
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((\x:Bool -> Bool. x) ((\x:Bool. if x then false
else true) true))
==>* false
i.e.,
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** We can use the [normalize] tactic defined in the [Types] chapter
to simplify these proofs. *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof. normalize. Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
Lemma step_example5_with_normalize :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Typing *)
(** Next we consider the typing relation of the STLC. *)
(* ----------------------------------------------------------------- *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place _typing judgment_, informally
written [Gamma |- t \in T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition context := partial_map ty.
(* ----------------------------------------------------------------- *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
update Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* ----------------------------------------------------------------- *)
(** *** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using update_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply] (or [...]). *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->B. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x \in T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End STLC.
(** $Date: 2016-05-26 17:51:14 -0400 (Thu, 26 May 2016) $ *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:19:54 04/26/2017
// Design Name:
// Module Name: decrypt_dumb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypt_dumb(
input [63:0] message,
input [63:0] DESkey,
output reg [63:0] decrypted,
output done,
input clk,
input reset,
input enable,
input ack
);
// 8 of 8 bits
reg [63:0] rand;
initial begin
rand = {8'd238, 8'd107, 8'd12, 8'd79, 8'd36, 8'd116, 8'd4, 8'd112};
end
reg [7:0] firstBit, secondBit, thirdBit;
// 8 of 3 bits
reg [23:0] randIdx;
reg [2:0] state;
localparam
INITIAL = 3'd1,
DECRYPT = 3'd2,
DONE = 3'd4;
always @ (posedge clk, posedge reset)
begin
if(reset)
begin
state <= INITIAL;
randIdx = 24'd0;
end
else
begin
case (state)
INITIAL:
begin : STATE_INITIAL
if (enable)
state <= DECRYPT;
end
DECRYPT:
begin: STATE_DECRYPT
integer i;
for (i = 0; i < 8; i = i + 1) begin
firstBit[i] = (DESkey[8*i+2 +: 2] ^ DESkey[8*i+6 +: 2]) > 2'd1;
secondBit[i] = (DESkey[8*i +: 2] ^ DESkey[8*i+4 +: 2]) > 2'd1;
thirdBit[i] = (DESkey[8*i +: 4] ^ DESkey[8*i+4 +: 4]) > 3'd3;
randIdx[3 * i +: 3] = {firstBit[i], secondBit[i], thirdBit[i]};
decrypted[8 * i +: 8] <= message[8 * i +: 8] ^ rand[randIdx[3 * i +: 3] +: 8];
end
state <= DONE;
end
DONE:
begin: STATE_DONE
if (ack)
state <= INITIAL;
end
endcase
end
end
assign done = state == DONE;
endmodule
|
`include "defines.vh"
/**
* @module lru_counter
* @author sabertazimi
* @email [email protected]
* @brief least recent use algorithm hardware implementation (counter implementation)
* @param DATA_WIDTH data width
* @input clk clock signal
* @input rst reset signal
* @input en enable signal
* @input hit hit flag
* @input hit_line hit line number
* @output lru_line lease recently used line number
*/
module lru_counter
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input en,
input hit,
input [`BTB_LINE_SIZE-1:0] hit_line,
output [`BTB_LINE_SIZE-1:0] lru_line
);
wire [`BTB_LINE_SIZE-1:0] access_line;
wire rst0, rst1, rst2, rst3, rst4, rst5, rst6, rst7;
wire [`BTB_LINE_SIZE-1:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7;
assign access_line = hit ? hit_line : lru_line;
assign rst0 = (access_line == 3'd0);
assign rst1 = (access_line == 3'd1);
assign rst2 = (access_line == 3'd2);
assign rst3 = (access_line == 3'd3);
assign rst4 = (access_line == 3'd4);
assign rst5 = (access_line == 3'd5);
assign rst6 = (access_line == 3'd6);
assign rst7 = (access_line == 3'd7);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter0 (
.clk(clk),
.rst(rst || rst0),
.en(en),
.count(cnt0)
);
latch_counter # (
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter1 (
.clk(clk),
.rst(rst || rst1),
.en(en),
.count(cnt1)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter2 (
.clk(clk),
.rst(rst || rst2),
.en(en),
.count(cnt2)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter3 (
.clk(clk),
.rst(rst || rst3),
.en(en),
.count(cnt3)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter4 (
.clk(clk),
.rst(rst || rst4),
.en(en),
.count(cnt4)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter5 (
.clk(clk),
.rst(rst || rst5),
.en(en),
.count(cnt5)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter6 (
.clk(clk),
.rst(rst || rst6),
.en(en),
.count(cnt6)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter7 (
.clk(clk),
.rst(rst || rst7),
.en(en),
.count(cnt7)
);
max_comparator max_comparator (
.cnt0(cnt0),
.cnt1(cnt1),
.cnt2(cnt2),
.cnt3(cnt3),
.cnt4(cnt4),
.cnt5(cnt5),
.cnt6(cnt6),
.cnt7(cnt7),
.lru_line(lru_line)
);
endmodule // lru_counter
|
// file: SysMon_tb.v
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// System Monitor wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// System Monitor wizard. Input clock is generated in this testbench.
//----------------------------------------------------------------------------
// This testbench does not implement checking of averaging and calibration
// Bipolar signals are applied with Vn = 0
`timescale 1ps/1ps
`define wait_eoc @(negedge EOC_TB)
`define wait_eos @(posedge EOS_TB)
`define wait_drdy @(negedge DRDY_TB)
`define wait_done @(posedge BUSY_TB)
`define wait_busy @(negedge BUSY_TB)
module SysMon_tb ();
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam time PER1 = 20*ONE_NS;
// Declare the input clock signals
reg DCLK_TB = 1;
wire [6:0] DADDR_TB;
wire DEN_TB;
wire DWE_TB;
wire [15:0] DI_TB;
wire [15:0] DO_TB;
wire DRDY_TB;
wire [2:0] ALM_unused;
wire FLOAT_VCCAUX_ALARM;
wire FLOAT_VCCINT_ALARM;
wire FLOAT_USER_TEMP_ALARM;
wire BUSY_TB;
wire [4:0] CHANNEL_TB;
wire EOC_TB;
wire EOS_TB;
wire JTAGBUSY_TB;
wire JTAGLOCKED_TB;
wire JTAGMODIFIED_TB;
// Input clock generation
always begin
DCLK_TB = #(PER1/2) ~DCLK_TB;
end
assign DADDR_TB = {2'b00, CHANNEL_TB};
assign DI_TB = 16'b0000000000000000;
assign DWE_TB = 1'b0;
assign DEN_TB = EOC_TB;
// Start of the testbench
initial
begin
$display ("Single channel avereraging is enabled");
$display ("This TB does not verify averaging");
$display ("Please increase the simulation duration to see complete waveform") ;
//// Single Channel setup
/////////////////////////////////////////////////////////////
//// Single Channel Mode - Temperature channel selected ////
/////////////////////////////////////////////////////////////
/// Channel selected is Temp. channel
`wait_done;
`wait_eoc;
$display("EOC is asserted");
if (CHANNEL_TB == 0) begin
$display ("Monitored Temperature");
end
else begin
$display ("Temperature is not monitored");
$display ("ERROR !!!");
$finish;
end
`wait_drdy;
$display ("DRDY is asserted. Valid data is on the DO bus");
$display ("Averaging Complete") ;
$finish;
`wait_eoc;
$display ("EOC is asserted.");
if( CHANNEL_TB == 0) begin
$display ("Monitored Temperature.");
end
else begin
$display ("USER TEMP is not monitored.");
$display ("ERROR !!!");
$finish;
end
`wait_drdy;
$display ("DRDY is asserted. Valid data is on the DO bus");
$display ("Averaging Complete") ;
$finish;
end
// Instantiation of the example design
//---------------------------------------------------------
SysMon_exdes dut (
.DADDR_IN(DADDR_TB[6:0]),
.DCLK_IN(DCLK_TB),
.DEN_IN(DEN_TB),
.DI_IN(DI_TB[15:0]),
.DWE_IN(DWE_TB),
.BUSY_OUT(BUSY_TB),
.CHANNEL_OUT(CHANNEL_TB[4:0]),
.DO_OUT(DO_TB[15:0]),
.DRDY_OUT(DRDY_TB),
.EOC_OUT(EOC_TB),
.EOS_OUT(EOS_TB),
.JTAGBUSY_OUT(JTAGBUSY_TB),
.JTAGLOCKED_OUT(JTAGLOCKED_TB),
.JTAGMODIFIED_OUT(JTAGMODIFIED_TB),
.VP_IN(1'b0),
.VN_IN(1'b0)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cmp_dram.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////
module cmp_dram( /*AUTOARG*/
// Inouts
DRAM0_CB, DRAM0_DQ, DRAM0_DQS, DRAM1_CB, DRAM1_DQ, DRAM1_DQS,
DRAM2_CB, DRAM2_DQ, DRAM2_DQS, DRAM3_CB, DRAM3_DQ, DRAM3_DQS,
DRAM02_SDA, DRAM13_SDA,
// Inputs
dram_gclk, cmp_grst, XXWP, XXSA, DRAM_FAIL_PART, DRAM_FAIL_OVER,
DRAM3_WE_L, DRAM3_RST_L, DRAM3_RAS_L, DRAM3_CS_L, DRAM3_CK_P,
DRAM3_CK_N, DRAM3_CKE, DRAM3_CAS_L, DRAM3_BA, DRAM3_ADDR,
DRAM2_WE_L, DRAM2_RST_L, DRAM2_RAS_L, DRAM2_CS_L, DRAM2_CK_P,
DRAM2_CK_N, DRAM2_CKE, DRAM2_CAS_L, DRAM2_BA, DRAM2_ADDR,
DRAM1_WE_L, DRAM1_RST_L, DRAM1_RAS_L, DRAM1_CS_L, DRAM1_CK_P,
DRAM1_CK_N, DRAM1_CKE, DRAM1_CAS_L, DRAM1_BA, DRAM1_ADDR,
DRAM0_WE_L, DRAM0_RST_L, DRAM0_RAS_L, DRAM0_CS_L, DRAM0_CK_P,
DRAM0_CK_N, DRAM0_CKE, DRAM0_CAS_L, DRAM0_BA, DRAM0_ADDR,
DRAM02_SCL, DRAM13_SCL
);
inout [15:0] DRAM0_CB; // To/From mem0 of ch_mem.v
inout [127:0] DRAM0_DQ; // To/From mem0 of ch_mem.v, ...
inout [35:0] DRAM0_DQS; // To/From mem0 of ch_mem.v
inout [15:0] DRAM1_CB; // To/From mem1 of ch_mem.v
inout [127:0] DRAM1_DQ; // To/From mem1 of ch_mem.v, ...
inout [35:0] DRAM1_DQS; // To/From mem1 of ch_mem.v
inout [15:0] DRAM2_CB; // To/From mem2 of ch_mem.v
inout [127:0] DRAM2_DQ; // To/From mem2 of ch_mem.v, ...
inout [35:0] DRAM2_DQS; // To/From mem2 of ch_mem.v
inout [15:0] DRAM3_CB; // To/From mem3 of ch_mem.v
inout [127:0] DRAM3_DQ; // To/From mem3 of ch_mem.v, ...
inout [35:0] DRAM3_DQS; // To/From mem3 of ch_mem.v
inout DRAM02_SDA;
inout DRAM13_SDA;
input DRAM02_SCL;
input DRAM13_SCL;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [14:0] DRAM0_ADDR; // To mem0 of ch_mem.v, ...
input [2:0] DRAM0_BA; // To mem0 of ch_mem.v, ...
input DRAM0_CAS_L; // To mem0 of ch_mem.v, ...
input DRAM0_CKE; // To mem0 of ch_mem.v, ...
input [3:0] DRAM0_CK_N; // To mem0 of ch_mem.v
input [3:0] DRAM0_CK_P; // To mem0 of ch_mem.v
input [3:0] DRAM0_CS_L; // To mem0 of ch_mem.v, ...
input DRAM0_RAS_L; // To mem0 of ch_mem.v, ...
input DRAM0_RST_L; // To mem0 of ch_mem.v, ...
input DRAM0_WE_L; // To mem0 of ch_mem.v, ...
input [14:0] DRAM1_ADDR; // To mem1 of ch_mem.v, ...
input [2:0] DRAM1_BA; // To mem1 of ch_mem.v, ...
input DRAM1_CAS_L; // To mem1 of ch_mem.v, ...
input DRAM1_CKE; // To mem1 of ch_mem.v, ...
input [3:0] DRAM1_CK_N; // To mem1 of ch_mem.v
input [3:0] DRAM1_CK_P; // To mem1 of ch_mem.v
input [3:0] DRAM1_CS_L; // To mem1 of ch_mem.v, ...
input DRAM1_RAS_L; // To mem1 of ch_mem.v, ...
input DRAM1_RST_L; // To mem1 of ch_mem.v, ...
input DRAM1_WE_L; // To mem1 of ch_mem.v, ...
input [14:0] DRAM2_ADDR; // To mem2 of ch_mem.v, ...
input [2:0] DRAM2_BA; // To mem2 of ch_mem.v, ...
input DRAM2_CAS_L; // To mem2 of ch_mem.v, ...
input DRAM2_CKE; // To mem2 of ch_mem.v, ...
input [3:0] DRAM2_CK_N; // To mem2 of ch_mem.v
input [3:0] DRAM2_CK_P; // To mem2 of ch_mem.v
input [3:0] DRAM2_CS_L; // To mem2 of ch_mem.v, ...
input DRAM2_RAS_L; // To mem2 of ch_mem.v, ...
input DRAM2_RST_L; // To mem2 of ch_mem.v, ...
input DRAM2_WE_L; // To mem2 of ch_mem.v, ...
input [14:0] DRAM3_ADDR; // To mem3 of ch_mem.v, ...
input [2:0] DRAM3_BA; // To mem3 of ch_mem.v, ...
input DRAM3_CAS_L; // To mem3 of ch_mem.v, ...
input DRAM3_CKE; // To mem3 of ch_mem.v, ...
input [3:0] DRAM3_CK_N; // To mem3 of ch_mem.v
input [3:0] DRAM3_CK_P; // To mem3 of ch_mem.v
input [3:0] DRAM3_CS_L; // To mem3 of ch_mem.v, ...
input DRAM3_RAS_L; // To mem3 of ch_mem.v, ...
input DRAM3_RST_L; // To mem3 of ch_mem.v, ...
input DRAM3_WE_L; // To mem3 of ch_mem.v, ...
input DRAM_FAIL_OVER; // To dimm_if_mon0 of dimm_if_mon.v, ...
input [5:0] DRAM_FAIL_PART; // To dimm_if_mon0 of dimm_if_mon.v, ...
input [2:0] XXSA; // To mem0 of ch_mem.v, ...
input XXWP; // To mem0 of ch_mem.v, ...
input cmp_grst; // To cmp_dram_mon of cmp_dram_mon.v
input dram_gclk; // To cmp_dram_mon of cmp_dram_mon.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire DRAM01; // To/From mem0 of ch_mem.v
wire DRAM23; // To/From mem1 of ch_mem.v
wire DRAM45; // To/From mem2 of ch_mem.v
wire DRAM67; // To/From mem3 of ch_mem.v
// End of automatics
// Local regs
wire DRAM0_ENB_ERROR;
wire DRAM1_ENB_ERROR;
wire DRAM2_ENB_ERROR;
wire DRAM3_ENB_ERROR;
wire DRAM0_FAIL_OVER;
wire DRAM1_FAIL_OVER;
wire DRAM2_FAIL_OVER;
wire DRAM3_FAIL_OVER;
wire [5:0] DRAM0_FAIL_PART;
wire [5:0] DRAM1_FAIL_PART;
wire [5:0] DRAM2_FAIL_PART;
wire [5:0] DRAM3_FAIL_PART;
integer am_id00, am_id01, am_id02, am_id03, am_id04, am_id05, am_id06;
integer am_id07, am_id08, am_id09, am_id10, am_id11, am_id12, am_id13;
integer am_id14, am_id15, am_id16, am_id17, am_id18, am_id19, am_id20;
integer am_id21, am_id22, am_id23, am_id24, am_id25, am_id26, am_id27;
integer am_id28, am_id29, am_id30, am_id31, am_id32, am_id33, am_id34;
integer am_id35;
integer bm_id00, bm_id01, bm_id02, bm_id03, bm_id04, bm_id05, bm_id06;
integer bm_id07, bm_id08, bm_id09, bm_id10, bm_id11, bm_id12, bm_id13;
integer bm_id14, bm_id15, bm_id16, bm_id17, bm_id18, bm_id19, bm_id20;
integer bm_id21, bm_id22, bm_id23, bm_id24, bm_id25, bm_id26, bm_id27;
integer bm_id28, bm_id29, bm_id30, bm_id31, bm_id32, bm_id33, bm_id34;
integer bm_id35;
integer cm_id00, cm_id01, cm_id02, cm_id03, cm_id04, cm_id05, cm_id06;
integer cm_id07, cm_id08, cm_id09, cm_id10, cm_id11, cm_id12, cm_id13;
integer cm_id14, cm_id15, cm_id16, cm_id17, cm_id18, cm_id19, cm_id20;
integer cm_id21, cm_id22, cm_id23, cm_id24, cm_id25, cm_id26, cm_id27;
integer cm_id28, cm_id29, cm_id30, cm_id31, cm_id32, cm_id33, cm_id34;
integer cm_id35;
integer dm_id00, dm_id01, dm_id02, dm_id03, dm_id04, dm_id05, dm_id06;
integer dm_id07, dm_id08, dm_id09, dm_id10, dm_id11, dm_id12, dm_id13;
integer dm_id14, dm_id15, dm_id16, dm_id17, dm_id18, dm_id19, dm_id20;
integer dm_id21, dm_id22, dm_id23, dm_id24, dm_id25, dm_id26, dm_id27;
integer dm_id28, dm_id29, dm_id30, dm_id31, dm_id32, dm_id33, dm_id34;
integer dm_id35;
integer sam_id00, sam_id01, sam_id02, sam_id03, sam_id04, sam_id05, sam_id06;
integer sam_id07, sam_id08, sam_id09, sam_id10, sam_id11, sam_id12, sam_id13;
integer sam_id14, sam_id15, sam_id16, sam_id17, sam_id18, sam_id19, sam_id20;
integer sam_id21, sam_id22, sam_id23, sam_id24, sam_id25, sam_id26, sam_id27;
integer sam_id28, sam_id29, sam_id30, sam_id31, sam_id32, sam_id33, sam_id34;
integer sam_id35;
integer sbm_id00, sbm_id01, sbm_id02, sbm_id03, sbm_id04, sbm_id05, sbm_id06;
integer sbm_id07, sbm_id08, sbm_id09, sbm_id10, sbm_id11, sbm_id12, sbm_id13;
integer sbm_id14, sbm_id15, sbm_id16, sbm_id17, sbm_id18, sbm_id19, sbm_id20;
integer sbm_id21, sbm_id22, sbm_id23, sbm_id24, sbm_id25, sbm_id26, sbm_id27;
integer sbm_id28, sbm_id29, sbm_id30, sbm_id31, sbm_id32, sbm_id33, sbm_id34;
integer sbm_id35;
integer scm_id00, scm_id01, scm_id02, scm_id03, scm_id04, scm_id05, scm_id06;
integer scm_id07, scm_id08, scm_id09, scm_id10, scm_id11, scm_id12, scm_id13;
integer scm_id14, scm_id15, scm_id16, scm_id17, scm_id18, scm_id19, scm_id20;
integer scm_id21, scm_id22, scm_id23, scm_id24, scm_id25, scm_id26, scm_id27;
integer scm_id28, scm_id29, scm_id30, scm_id31, scm_id32, scm_id33, scm_id34;
integer scm_id35;
integer sdm_id00, sdm_id01, sdm_id02, sdm_id03, sdm_id04, sdm_id05, sdm_id06;
integer sdm_id07, sdm_id08, sdm_id09, sdm_id10, sdm_id11, sdm_id12, sdm_id13;
integer sdm_id14, sdm_id15, sdm_id16, sdm_id17, sdm_id18, sdm_id19, sdm_id20;
integer sdm_id21, sdm_id22, sdm_id23, sdm_id24, sdm_id25, sdm_id26, sdm_id27;
integer sdm_id28, sdm_id29, sdm_id30, sdm_id31, sdm_id32, sdm_id33, sdm_id34;
integer sdm_id35;
integer ram_id00, ram_id01, ram_id02, ram_id03, ram_id04, ram_id05, ram_id06;
integer ram_id07, ram_id08, ram_id09, ram_id10, ram_id11, ram_id12, ram_id13;
integer ram_id14, ram_id15, ram_id16, ram_id17, ram_id18, ram_id19, ram_id20;
integer ram_id21, ram_id22, ram_id23, ram_id24, ram_id25, ram_id26, ram_id27;
integer ram_id28, ram_id29, ram_id30, ram_id31, ram_id32, ram_id33, ram_id34;
integer ram_id35;
integer rbm_id00, rbm_id01, rbm_id02, rbm_id03, rbm_id04, rbm_id05, rbm_id06;
integer rbm_id07, rbm_id08, rbm_id09, rbm_id10, rbm_id11, rbm_id12, rbm_id13;
integer rbm_id14, rbm_id15, rbm_id16, rbm_id17, rbm_id18, rbm_id19, rbm_id20;
integer rbm_id21, rbm_id22, rbm_id23, rbm_id24, rbm_id25, rbm_id26, rbm_id27;
integer rbm_id28, rbm_id29, rbm_id30, rbm_id31, rbm_id32, rbm_id33, rbm_id34;
integer rbm_id35;
integer rcm_id00, rcm_id01, rcm_id02, rcm_id03, rcm_id04, rcm_id05, rcm_id06;
integer rcm_id07, rcm_id08, rcm_id09, rcm_id10, rcm_id11, rcm_id12, rcm_id13;
integer rcm_id14, rcm_id15, rcm_id16, rcm_id17, rcm_id18, rcm_id19, rcm_id20;
integer rcm_id21, rcm_id22, rcm_id23, rcm_id24, rcm_id25, rcm_id26, rcm_id27;
integer rcm_id28, rcm_id29, rcm_id30, rcm_id31, rcm_id32, rcm_id33, rcm_id34;
integer rcm_id35;
integer rdm_id00, rdm_id01, rdm_id02, rdm_id03, rdm_id04, rdm_id05, rdm_id06;
integer rdm_id07, rdm_id08, rdm_id09, rdm_id10, rdm_id11, rdm_id12, rdm_id13;
integer rdm_id14, rdm_id15, rdm_id16, rdm_id17, rdm_id18, rdm_id19, rdm_id20;
integer rdm_id21, rdm_id22, rdm_id23, rdm_id24, rdm_id25, rdm_id26, rdm_id27;
integer rdm_id28, rdm_id29, rdm_id30, rdm_id31, rdm_id32, rdm_id33, rdm_id34;
integer rdm_id35;
integer rsam_id00, rsam_id01, rsam_id02, rsam_id03, rsam_id04, rsam_id05, rsam_id06;
integer rsam_id07, rsam_id08, rsam_id09, rsam_id10, rsam_id11, rsam_id12, rsam_id13;
integer rsam_id14, rsam_id15, rsam_id16, rsam_id17, rsam_id18, rsam_id19, rsam_id20;
integer rsam_id21, rsam_id22, rsam_id23, rsam_id24, rsam_id25, rsam_id26, rsam_id27;
integer rsam_id28, rsam_id29, rsam_id30, rsam_id31, rsam_id32, rsam_id33, rsam_id34;
integer rsam_id35;
integer rsbm_id00, rsbm_id01, rsbm_id02, rsbm_id03, rsbm_id04, rsbm_id05, rsbm_id06;
integer rsbm_id07, rsbm_id08, rsbm_id09, rsbm_id10, rsbm_id11, rsbm_id12, rsbm_id13;
integer rsbm_id14, rsbm_id15, rsbm_id16, rsbm_id17, rsbm_id18, rsbm_id19, rsbm_id20;
integer rsbm_id21, rsbm_id22, rsbm_id23, rsbm_id24, rsbm_id25, rsbm_id26, rsbm_id27;
integer rsbm_id28, rsbm_id29, rsbm_id30, rsbm_id31, rsbm_id32, rsbm_id33, rsbm_id34;
integer rsbm_id35;
integer rscm_id00, rscm_id01, rscm_id02, rscm_id03, rscm_id04, rscm_id05, rscm_id06;
integer rscm_id07, rscm_id08, rscm_id09, rscm_id10, rscm_id11, rscm_id12, rscm_id13;
integer rscm_id14, rscm_id15, rscm_id16, rscm_id17, rscm_id18, rscm_id19, rscm_id20;
integer rscm_id21, rscm_id22, rscm_id23, rscm_id24, rscm_id25, rscm_id26, rscm_id27;
integer rscm_id28, rscm_id29, rscm_id30, rscm_id31, rscm_id32, rscm_id33, rscm_id34;
integer rscm_id35;
integer rsdm_id00, rsdm_id01, rsdm_id02, rsdm_id03, rsdm_id04, rsdm_id05, rsdm_id06;
integer rsdm_id07, rsdm_id08, rsdm_id09, rsdm_id10, rsdm_id11, rsdm_id12, rsdm_id13;
integer rsdm_id14, rsdm_id15, rsdm_id16, rsdm_id17, rsdm_id18, rsdm_id19, rsdm_id20;
integer rsdm_id21, rsdm_id22, rsdm_id23, rsdm_id24, rsdm_id25, rsdm_id26, rsdm_id27;
integer rsdm_id28, rsdm_id29, rsdm_id30, rsdm_id31, rsdm_id32, rsdm_id33, rsdm_id34;
integer rsdm_id35;
integer avid0, avid1, avid2, avid3, avid4;
integer bvid0, bvid1, bvid2, bvid3, bvid4;
integer cvid0, cvid1, cvid2, cvid3, cvid4;
integer dvid0, dvid1, dvid2, dvid3, dvid4;
integer savid0, savid1, savid2, savid3, savid4;
integer sbvid0, sbvid1, sbvid2, sbvid3, sbvid4;
integer scvid0, scvid1, scvid2, scvid3, scvid4;
integer sdvid0, sdvid1, sdvid2, sdvid3, sdvid4;
integer ravid0, ravid1, ravid2, ravid3, ravid4;
integer rbvid0, rbvid1, rbvid2, rbvid3, rbvid4;
integer rcvid0, rcvid1, rcvid2, rcvid3, rcvid4;
integer rdvid0, rdvid1, rdvid2, rdvid3, rdvid4;
integer rsavid0, rsavid1, rsavid2, rsavid3, rsavid4;
integer rsbvid0, rsbvid1, rsbvid2, rsbvid3, rsbvid4;
integer rscvid0, rscvid1, rscvid2, rscvid3, rscvid4;
integer rsdvid0, rsdvid1, rsdvid2, rsdvid3, rsdvid4;
integer vid5, vid6;
integer svid5, svid6;
integer rvid5, rvid6;
integer rsvid5, rsvid6;
integer success;
reg [3:0] cas_latency;
`ifdef DENALI_ON
initial begin
/////////////////////////////////////////
// Create Denali System Memory
/////////////////////////
// RANK 0, Stack 0
// Channel 0
#10 // wait for mem.image.
am_id00 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U00");
am_id01 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U01");
am_id02 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U02");
am_id03 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U03");
am_id04 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U04");
am_id05 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U05");
am_id06 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U06");
am_id07 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U07");
am_id08 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U08");
am_id09 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U09");
am_id10 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U10");
am_id11 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U11");
am_id12 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U12");
am_id13 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U13");
am_id14 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U14");
am_id15 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U15");
am_id16 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U16");
am_id17 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U17");
am_id18 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U00");
am_id19 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U01");
am_id20 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U02");
am_id21 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U03");
am_id22 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U04");
am_id23 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U05");
am_id24 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U06");
am_id25 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U07");
am_id26 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U08");
am_id27 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U09");
am_id28 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U10");
am_id29 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U11");
am_id30 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U12");
am_id31 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U13");
am_id32 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U14");
am_id33 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U15");
am_id34 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U16");
am_id35 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U17");
// Channel 1
bm_id00 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U00");
bm_id01 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U01");
bm_id02 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U02");
bm_id03 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U03");
bm_id04 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U04");
bm_id05 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U05");
bm_id06 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U06");
bm_id07 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U07");
bm_id08 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U08");
bm_id09 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U09");
bm_id10 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U10");
bm_id11 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U11");
bm_id12 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U12");
bm_id13 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U13");
bm_id14 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U14");
bm_id15 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U15");
bm_id16 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U16");
bm_id17 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U17");
bm_id18 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U00");
bm_id19 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U01");
bm_id20 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U02");
bm_id21 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U03");
bm_id22 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U04");
bm_id23 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U05");
bm_id24 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U06");
bm_id25 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U07");
bm_id26 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U08");
bm_id27 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U09");
bm_id28 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U10");
bm_id29 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U11");
bm_id30 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U12");
bm_id31 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U13");
bm_id32 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U14");
bm_id33 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U15");
bm_id34 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U16");
bm_id35 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U17");
// Channe 2
cm_id00 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U00");
cm_id01 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U01");
cm_id02 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U02");
cm_id03 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U03");
cm_id04 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U04");
cm_id05 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U05");
cm_id06 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U06");
cm_id07 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U07");
cm_id08 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U08");
cm_id09 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U09");
cm_id10 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U10");
cm_id11 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U11");
cm_id12 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U12");
cm_id13 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U13");
cm_id14 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U14");
cm_id15 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U15");
cm_id16 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U16");
cm_id17 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U17");
cm_id18 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U00");
cm_id19 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U01");
cm_id20 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U02");
cm_id21 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U03");
cm_id22 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U04");
cm_id23 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U05");
cm_id24 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U06");
cm_id25 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U07");
cm_id26 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U08");
cm_id27 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U09");
cm_id28 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U10");
cm_id29 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U11");
cm_id30 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U12");
cm_id31 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U13");
cm_id32 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U14");
cm_id33 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U15");
cm_id34 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U16");
cm_id35 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U17");
// channel 3
dm_id00 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U00");
dm_id01 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U01");
dm_id02 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U02");
dm_id03 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U03");
dm_id04 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U04");
dm_id05 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U05");
dm_id06 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U06");
dm_id07 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U07");
dm_id08 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U08");
dm_id09 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U09");
dm_id10 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U10");
dm_id11 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U11");
dm_id12 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U12");
dm_id13 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U13");
dm_id14 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U14");
dm_id15 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U15");
dm_id16 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U16");
dm_id17 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U17");
dm_id18 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U00");
dm_id19 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U01");
dm_id20 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U02");
dm_id21 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U03");
dm_id22 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U04");
dm_id23 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U05");
dm_id24 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U06");
dm_id25 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U07");
dm_id26 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U08");
dm_id27 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U09");
dm_id28 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U10");
dm_id29 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U11");
dm_id30 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U12");
dm_id31 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U13");
dm_id32 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U14");
dm_id33 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U15");
dm_id34 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U16");
dm_id35 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U17");
//////////////////////////////////////
//workaround: for nested width problem
// Channel 0
avid4 = $mmcreatesysmem("sysmem","a_dimm144",36,1,1);
success=$mmaddtosysmem(avid4,am_id13,0,0,0);
success=$mmaddtosysmem(avid4,am_id04,1,0,0);
success=$mmaddtosysmem(avid4,am_id31,2,0,0);
success=$mmaddtosysmem(avid4,am_id22,3,0,0);
success=$mmaddtosysmem(avid4,am_id17,4,0,0);
success=$mmaddtosysmem(avid4,am_id16,5,0,0);
success=$mmaddtosysmem(avid4,am_id15,6,0,0);
success=$mmaddtosysmem(avid4,am_id14,7,0,0);
success=$mmaddtosysmem(avid4,am_id12,8,0,0);
success=$mmaddtosysmem(avid4,am_id11,9,0,0);
success=$mmaddtosysmem(avid4,am_id10,10,0,0);
success=$mmaddtosysmem(avid4,am_id09,11,0,0);
success=$mmaddtosysmem(avid4,am_id08,12,0,0);
success=$mmaddtosysmem(avid4,am_id07,13,0,0);
success=$mmaddtosysmem(avid4,am_id06,14,0,0);
success=$mmaddtosysmem(avid4,am_id05,15,0,0);
success=$mmaddtosysmem(avid4,am_id03,16,0,0);
success=$mmaddtosysmem(avid4,am_id02,17,0,0);
success=$mmaddtosysmem(avid4,am_id01,18,0,0);
success=$mmaddtosysmem(avid4,am_id00,19,0,0);
success=$mmaddtosysmem(avid4,am_id35,20,0,0);
success=$mmaddtosysmem(avid4,am_id34,21,0,0);
success=$mmaddtosysmem(avid4,am_id33,22,0,0);
success=$mmaddtosysmem(avid4,am_id32,23,0,0);
success=$mmaddtosysmem(avid4,am_id30,24,0,0);
success=$mmaddtosysmem(avid4,am_id29,25,0,0);
success=$mmaddtosysmem(avid4,am_id28,26,0,0);
success=$mmaddtosysmem(avid4,am_id27,27,0,0);
success=$mmaddtosysmem(avid4,am_id26,28,0,0);
success=$mmaddtosysmem(avid4,am_id25,29,0,0);
success=$mmaddtosysmem(avid4,am_id24,30,0,0);
success=$mmaddtosysmem(avid4,am_id23,31,0,0);
success=$mmaddtosysmem(avid4,am_id21,32,0,0);
success=$mmaddtosysmem(avid4,am_id20,33,0,0);
success=$mmaddtosysmem(avid4,am_id19,34,0,0);
success=$mmaddtosysmem(avid4,am_id18,35,0,0);
// Channel 1
bvid4 = $mmcreatesysmem("sysmem","b_dimm144",36,1,1);
success=$mmaddtosysmem(bvid4,bm_id13,0,0,0);
success=$mmaddtosysmem(bvid4,bm_id04,1,0,0);
success=$mmaddtosysmem(bvid4,bm_id31,2,0,0);
success=$mmaddtosysmem(bvid4,bm_id22,3,0,0);
success=$mmaddtosysmem(bvid4,bm_id17,4,0,0);
success=$mmaddtosysmem(bvid4,bm_id16,5,0,0);
success=$mmaddtosysmem(bvid4,bm_id15,6,0,0);
success=$mmaddtosysmem(bvid4,bm_id14,7,0,0);
success=$mmaddtosysmem(bvid4,bm_id12,8,0,0);
success=$mmaddtosysmem(bvid4,bm_id11,9,0,0);
success=$mmaddtosysmem(bvid4,bm_id10,10,0,0);
success=$mmaddtosysmem(bvid4,bm_id09,11,0,0);
success=$mmaddtosysmem(bvid4,bm_id08,12,0,0);
success=$mmaddtosysmem(bvid4,bm_id07,13,0,0);
success=$mmaddtosysmem(bvid4,bm_id06,14,0,0);
success=$mmaddtosysmem(bvid4,bm_id05,15,0,0);
success=$mmaddtosysmem(bvid4,bm_id03,16,0,0);
success=$mmaddtosysmem(bvid4,bm_id02,17,0,0);
success=$mmaddtosysmem(bvid4,bm_id01,18,0,0);
success=$mmaddtosysmem(bvid4,bm_id00,19,0,0);
success=$mmaddtosysmem(bvid4,bm_id35,20,0,0);
success=$mmaddtosysmem(bvid4,bm_id34,21,0,0);
success=$mmaddtosysmem(bvid4,bm_id33,22,0,0);
success=$mmaddtosysmem(bvid4,bm_id32,23,0,0);
success=$mmaddtosysmem(bvid4,bm_id30,24,0,0);
success=$mmaddtosysmem(bvid4,bm_id29,25,0,0);
success=$mmaddtosysmem(bvid4,bm_id28,26,0,0);
success=$mmaddtosysmem(bvid4,bm_id27,27,0,0);
success=$mmaddtosysmem(bvid4,bm_id26,28,0,0);
success=$mmaddtosysmem(bvid4,bm_id25,29,0,0);
success=$mmaddtosysmem(bvid4,bm_id24,30,0,0);
success=$mmaddtosysmem(bvid4,bm_id23,31,0,0);
success=$mmaddtosysmem(bvid4,bm_id21,32,0,0);
success=$mmaddtosysmem(bvid4,bm_id20,33,0,0);
success=$mmaddtosysmem(bvid4,bm_id19,34,0,0);
success=$mmaddtosysmem(bvid4,bm_id18,35,0,0);
// Channel 2
cvid4 = $mmcreatesysmem("sysmem","c_dimm144",36,1,1);
success=$mmaddtosysmem(cvid4,cm_id13,0,0,0);
success=$mmaddtosysmem(cvid4,cm_id04,1,0,0);
success=$mmaddtosysmem(cvid4,cm_id31,2,0,0);
success=$mmaddtosysmem(cvid4,cm_id22,3,0,0);
success=$mmaddtosysmem(cvid4,cm_id17,4,0,0);
success=$mmaddtosysmem(cvid4,cm_id16,5,0,0);
success=$mmaddtosysmem(cvid4,cm_id15,6,0,0);
success=$mmaddtosysmem(cvid4,cm_id14,7,0,0);
success=$mmaddtosysmem(cvid4,cm_id12,8,0,0);
success=$mmaddtosysmem(cvid4,cm_id11,9,0,0);
success=$mmaddtosysmem(cvid4,cm_id10,10,0,0);
success=$mmaddtosysmem(cvid4,cm_id09,11,0,0);
success=$mmaddtosysmem(cvid4,cm_id08,12,0,0);
success=$mmaddtosysmem(cvid4,cm_id07,13,0,0);
success=$mmaddtosysmem(cvid4,cm_id06,14,0,0);
success=$mmaddtosysmem(cvid4,cm_id05,15,0,0);
success=$mmaddtosysmem(cvid4,cm_id03,16,0,0);
success=$mmaddtosysmem(cvid4,cm_id02,17,0,0);
success=$mmaddtosysmem(cvid4,cm_id01,18,0,0);
success=$mmaddtosysmem(cvid4,cm_id00,19,0,0);
success=$mmaddtosysmem(cvid4,cm_id35,20,0,0);
success=$mmaddtosysmem(cvid4,cm_id34,21,0,0);
success=$mmaddtosysmem(cvid4,cm_id33,22,0,0);
success=$mmaddtosysmem(cvid4,cm_id32,23,0,0);
success=$mmaddtosysmem(cvid4,cm_id30,24,0,0);
success=$mmaddtosysmem(cvid4,cm_id29,25,0,0);
success=$mmaddtosysmem(cvid4,cm_id28,26,0,0);
success=$mmaddtosysmem(cvid4,cm_id27,27,0,0);
success=$mmaddtosysmem(cvid4,cm_id26,28,0,0);
success=$mmaddtosysmem(cvid4,cm_id25,29,0,0);
success=$mmaddtosysmem(cvid4,cm_id24,30,0,0);
success=$mmaddtosysmem(cvid4,cm_id23,31,0,0);
success=$mmaddtosysmem(cvid4,cm_id21,32,0,0);
success=$mmaddtosysmem(cvid4,cm_id20,33,0,0);
success=$mmaddtosysmem(cvid4,cm_id19,34,0,0);
success=$mmaddtosysmem(cvid4,cm_id18,35,0,0);
// Channel 3
dvid4 = $mmcreatesysmem("sysmem","d_dimm144",36,1,1);
success=$mmaddtosysmem(dvid4,dm_id13,0,0,0);
success=$mmaddtosysmem(dvid4,dm_id04,1,0,0);
success=$mmaddtosysmem(dvid4,dm_id31,2,0,0);
success=$mmaddtosysmem(dvid4,dm_id22,3,0,0);
success=$mmaddtosysmem(dvid4,dm_id17,4,0,0);
success=$mmaddtosysmem(dvid4,dm_id16,5,0,0);
success=$mmaddtosysmem(dvid4,dm_id15,6,0,0);
success=$mmaddtosysmem(dvid4,dm_id14,7,0,0);
success=$mmaddtosysmem(dvid4,dm_id12,8,0,0);
success=$mmaddtosysmem(dvid4,dm_id11,9,0,0);
success=$mmaddtosysmem(dvid4,dm_id10,10,0,0);
success=$mmaddtosysmem(dvid4,dm_id09,11,0,0);
success=$mmaddtosysmem(dvid4,dm_id08,12,0,0);
success=$mmaddtosysmem(dvid4,dm_id07,13,0,0);
success=$mmaddtosysmem(dvid4,dm_id06,14,0,0);
success=$mmaddtosysmem(dvid4,dm_id05,15,0,0);
success=$mmaddtosysmem(dvid4,dm_id03,16,0,0);
success=$mmaddtosysmem(dvid4,dm_id02,17,0,0);
success=$mmaddtosysmem(dvid4,dm_id01,18,0,0);
success=$mmaddtosysmem(dvid4,dm_id00,19,0,0);
success=$mmaddtosysmem(dvid4,dm_id35,20,0,0);
success=$mmaddtosysmem(dvid4,dm_id34,21,0,0);
success=$mmaddtosysmem(dvid4,dm_id33,22,0,0);
success=$mmaddtosysmem(dvid4,dm_id32,23,0,0);
success=$mmaddtosysmem(dvid4,dm_id30,24,0,0);
success=$mmaddtosysmem(dvid4,dm_id29,25,0,0);
success=$mmaddtosysmem(dvid4,dm_id28,26,0,0);
success=$mmaddtosysmem(dvid4,dm_id27,27,0,0);
success=$mmaddtosysmem(dvid4,dm_id26,28,0,0);
success=$mmaddtosysmem(dvid4,dm_id25,29,0,0);
success=$mmaddtosysmem(dvid4,dm_id24,30,0,0);
success=$mmaddtosysmem(dvid4,dm_id23,31,0,0);
success=$mmaddtosysmem(dvid4,dm_id21,32,0,0);
success=$mmaddtosysmem(dvid4,dm_id20,33,0,0);
success=$mmaddtosysmem(dvid4,dm_id19,34,0,0);
success=$mmaddtosysmem(dvid4,dm_id18,35,0,0);
`ifdef STACK_DIMM
//////////////////////
// RANK 0, STACK 1
// Channel 0
sam_id00 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U00");
sam_id01 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U01");
sam_id02 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U02");
sam_id03 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U03");
sam_id04 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U04");
sam_id05 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U05");
sam_id06 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U06");
sam_id07 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U07");
sam_id08 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U08");
sam_id09 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U09");
sam_id10 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U10");
sam_id11 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U11");
sam_id12 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U12");
sam_id13 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U13");
sam_id14 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U14");
sam_id15 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U15");
sam_id16 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U16");
sam_id17 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U17");
sam_id18 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U00");
sam_id19 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U01");
sam_id20 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U02");
sam_id21 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U03");
sam_id22 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U04");
sam_id23 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U05");
sam_id24 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U06");
sam_id25 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U07");
sam_id26 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U08");
sam_id27 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U09");
sam_id28 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U10");
sam_id29 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U11");
sam_id30 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U12");
sam_id31 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U13");
sam_id32 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U14");
sam_id33 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U15");
sam_id34 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U16");
sam_id35 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U17");
// Channel 1
sbm_id00 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U00");
sbm_id01 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U01");
sbm_id02 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U02");
sbm_id03 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U03");
sbm_id04 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U04");
sbm_id05 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U05");
sbm_id06 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U06");
sbm_id07 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U07");
sbm_id08 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U08");
sbm_id09 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U09");
sbm_id10 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U10");
sbm_id11 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U11");
sbm_id12 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U12");
sbm_id13 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U13");
sbm_id14 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U14");
sbm_id15 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U15");
sbm_id16 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U16");
sbm_id17 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U17");
sbm_id18 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U00");
sbm_id19 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U01");
sbm_id20 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U02");
sbm_id21 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U03");
sbm_id22 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U04");
sbm_id23 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U05");
sbm_id24 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U06");
sbm_id25 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U07");
sbm_id26 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U08");
sbm_id27 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U09");
sbm_id28 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U10");
sbm_id29 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U11");
sbm_id30 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U12");
sbm_id31 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U13");
sbm_id32 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U14");
sbm_id33 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U15");
sbm_id34 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U16");
sbm_id35 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U17");
// Channel 2
scm_id00 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U00");
scm_id01 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U01");
scm_id02 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U02");
scm_id03 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U03");
scm_id04 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U04");
scm_id05 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U05");
scm_id06 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U06");
scm_id07 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U07");
scm_id08 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U08");
scm_id09 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U09");
scm_id10 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U10");
scm_id11 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U11");
scm_id12 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U12");
scm_id13 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U13");
scm_id14 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U14");
scm_id15 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U15");
scm_id16 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U16");
scm_id17 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U17");
scm_id18 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U00");
scm_id19 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U01");
scm_id20 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U02");
scm_id21 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U03");
scm_id22 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U04");
scm_id23 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U05");
scm_id24 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U06");
scm_id25 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U07");
scm_id26 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U08");
scm_id27 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U09");
scm_id28 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U10");
scm_id29 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U11");
scm_id30 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U12");
scm_id31 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U13");
scm_id32 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U14");
scm_id33 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U15");
scm_id34 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U16");
scm_id35 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U17");
// Channel 3
sdm_id00 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U00");
sdm_id01 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U01");
sdm_id02 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U02");
sdm_id03 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U03");
sdm_id04 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U04");
sdm_id05 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U05");
sdm_id06 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U06");
sdm_id07 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U07");
sdm_id08 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U08");
sdm_id09 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U09");
sdm_id10 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U10");
sdm_id11 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U11");
sdm_id12 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U12");
sdm_id13 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U13");
sdm_id14 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U14");
sdm_id15 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U15");
sdm_id16 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U16");
sdm_id17 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U17");
sdm_id18 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U00");
sdm_id19 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U01");
sdm_id20 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U02");
sdm_id21 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U03");
sdm_id22 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U04");
sdm_id23 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U05");
sdm_id24 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U06");
sdm_id25 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U07");
sdm_id26 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U08");
sdm_id27 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U09");
sdm_id28 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U10");
sdm_id29 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U11");
sdm_id30 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U12");
sdm_id31 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U13");
sdm_id32 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U14");
sdm_id33 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U15");
sdm_id34 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U16");
sdm_id35 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U17");
//////////////////////////////////////
//workaround: for nested width problem
// Channel 0
savid4 = $mmcreatesysmem("sysmem","sa_dimm144",36,1,1);
success=$mmaddtosysmem(savid4,sam_id13,0,0,0);
success=$mmaddtosysmem(savid4,sam_id04,1,0,0);
success=$mmaddtosysmem(savid4,sam_id31,2,0,0);
success=$mmaddtosysmem(savid4,sam_id22,3,0,0);
success=$mmaddtosysmem(savid4,sam_id17,4,0,0);
success=$mmaddtosysmem(savid4,sam_id16,5,0,0);
success=$mmaddtosysmem(savid4,sam_id15,6,0,0);
success=$mmaddtosysmem(savid4,sam_id14,7,0,0);
success=$mmaddtosysmem(savid4,sam_id12,8,0,0);
success=$mmaddtosysmem(savid4,sam_id11,9,0,0);
success=$mmaddtosysmem(savid4,sam_id10,10,0,0);
success=$mmaddtosysmem(savid4,sam_id09,11,0,0);
success=$mmaddtosysmem(savid4,sam_id08,12,0,0);
success=$mmaddtosysmem(savid4,sam_id07,13,0,0);
success=$mmaddtosysmem(savid4,sam_id06,14,0,0);
success=$mmaddtosysmem(savid4,sam_id05,15,0,0);
success=$mmaddtosysmem(savid4,sam_id03,16,0,0);
success=$mmaddtosysmem(savid4,sam_id02,17,0,0);
success=$mmaddtosysmem(savid4,sam_id01,18,0,0);
success=$mmaddtosysmem(savid4,sam_id00,19,0,0);
success=$mmaddtosysmem(savid4,sam_id35,20,0,0);
success=$mmaddtosysmem(savid4,sam_id34,21,0,0);
success=$mmaddtosysmem(savid4,sam_id33,22,0,0);
success=$mmaddtosysmem(savid4,sam_id32,23,0,0);
success=$mmaddtosysmem(savid4,sam_id30,24,0,0);
success=$mmaddtosysmem(savid4,sam_id29,25,0,0);
success=$mmaddtosysmem(savid4,sam_id28,26,0,0);
success=$mmaddtosysmem(savid4,sam_id27,27,0,0);
success=$mmaddtosysmem(savid4,sam_id26,28,0,0);
success=$mmaddtosysmem(savid4,sam_id25,29,0,0);
success=$mmaddtosysmem(savid4,sam_id24,30,0,0);
success=$mmaddtosysmem(savid4,sam_id23,31,0,0);
success=$mmaddtosysmem(savid4,sam_id21,32,0,0);
success=$mmaddtosysmem(savid4,sam_id20,33,0,0);
success=$mmaddtosysmem(savid4,sam_id19,34,0,0);
success=$mmaddtosysmem(savid4,sam_id18,35,0,0);
// Channel 1
sbvid4 = $mmcreatesysmem("sysmem","sb_dimm144",36,1,1);
success=$mmaddtosysmem(sbvid4,sbm_id13,0,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id04,1,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id31,2,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id22,3,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id17,4,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id16,5,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id15,6,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id14,7,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id12,8,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id11,9,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id10,10,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id09,11,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id08,12,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id07,13,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id06,14,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id05,15,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id03,16,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id02,17,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id01,18,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id00,19,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id35,20,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id34,21,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id33,22,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id32,23,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id30,24,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id29,25,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id28,26,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id27,27,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id26,28,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id25,29,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id24,30,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id23,31,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id21,32,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id20,33,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id19,34,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id18,35,0,0);
// Channel 2
scvid4 = $mmcreatesysmem("sysmem","sc_dimm144",36,1,1);
success=$mmaddtosysmem(scvid4,scm_id13,0,0,0);
success=$mmaddtosysmem(scvid4,scm_id04,1,0,0);
success=$mmaddtosysmem(scvid4,scm_id31,2,0,0);
success=$mmaddtosysmem(scvid4,scm_id22,3,0,0);
success=$mmaddtosysmem(scvid4,scm_id17,4,0,0);
success=$mmaddtosysmem(scvid4,scm_id16,5,0,0);
success=$mmaddtosysmem(scvid4,scm_id15,6,0,0);
success=$mmaddtosysmem(scvid4,scm_id14,7,0,0);
success=$mmaddtosysmem(scvid4,scm_id12,8,0,0);
success=$mmaddtosysmem(scvid4,scm_id11,9,0,0);
success=$mmaddtosysmem(scvid4,scm_id10,10,0,0);
success=$mmaddtosysmem(scvid4,scm_id09,11,0,0);
success=$mmaddtosysmem(scvid4,scm_id08,12,0,0);
success=$mmaddtosysmem(scvid4,scm_id07,13,0,0);
success=$mmaddtosysmem(scvid4,scm_id06,14,0,0);
success=$mmaddtosysmem(scvid4,scm_id05,15,0,0);
success=$mmaddtosysmem(scvid4,scm_id03,16,0,0);
success=$mmaddtosysmem(scvid4,scm_id02,17,0,0);
success=$mmaddtosysmem(scvid4,scm_id01,18,0,0);
success=$mmaddtosysmem(scvid4,scm_id00,19,0,0);
success=$mmaddtosysmem(scvid4,scm_id35,20,0,0);
success=$mmaddtosysmem(scvid4,scm_id34,21,0,0);
success=$mmaddtosysmem(scvid4,scm_id33,22,0,0);
success=$mmaddtosysmem(scvid4,scm_id32,23,0,0);
success=$mmaddtosysmem(scvid4,scm_id30,24,0,0);
success=$mmaddtosysmem(scvid4,scm_id29,25,0,0);
success=$mmaddtosysmem(scvid4,scm_id28,26,0,0);
success=$mmaddtosysmem(scvid4,scm_id27,27,0,0);
success=$mmaddtosysmem(scvid4,scm_id26,28,0,0);
success=$mmaddtosysmem(scvid4,scm_id25,29,0,0);
success=$mmaddtosysmem(scvid4,scm_id24,30,0,0);
success=$mmaddtosysmem(scvid4,scm_id23,31,0,0);
success=$mmaddtosysmem(scvid4,scm_id21,32,0,0);
success=$mmaddtosysmem(scvid4,scm_id20,33,0,0);
success=$mmaddtosysmem(scvid4,scm_id19,34,0,0);
success=$mmaddtosysmem(scvid4,scm_id18,35,0,0);
// Channel 3
sdvid4 = $mmcreatesysmem("sysmem","sd_dimm144",36,1,1);
success=$mmaddtosysmem(sdvid4,sdm_id13,0,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id04,1,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id31,2,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id22,3,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id17,4,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id16,5,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id15,6,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id14,7,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id12,8,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id11,9,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id10,10,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id09,11,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id08,12,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id07,13,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id06,14,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id05,15,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id03,16,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id02,17,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id01,18,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id00,19,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id35,20,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id34,21,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id33,22,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id32,23,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id30,24,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id29,25,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id28,26,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id27,27,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id26,28,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id25,29,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id24,30,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id23,31,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id21,32,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id20,33,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id19,34,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id18,35,0,0);
`endif
`ifdef RANK_DIMM
/////////////////////////
// RANK 1, Stack 0
// Channel 0
ram_id00 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U00");
ram_id01 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U01");
ram_id02 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U02");
ram_id03 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U03");
ram_id04 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U04");
ram_id05 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U05");
ram_id06 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U06");
ram_id07 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U07");
ram_id08 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U08");
ram_id09 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U09");
ram_id10 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U10");
ram_id11 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U11");
ram_id12 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U12");
ram_id13 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U13");
ram_id14 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U14");
ram_id15 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U15");
ram_id16 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U16");
ram_id17 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U17");
ram_id18 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U00");
ram_id19 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U01");
ram_id20 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U02");
ram_id21 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U03");
ram_id22 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U04");
ram_id23 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U05");
ram_id24 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U06");
ram_id25 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U07");
ram_id26 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U08");
ram_id27 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U09");
ram_id28 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U10");
ram_id29 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U11");
ram_id30 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U12");
ram_id31 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U13");
ram_id32 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U14");
ram_id33 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U15");
ram_id34 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U16");
ram_id35 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U17");
// Channel 1
rbm_id00 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U00");
rbm_id01 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U01");
rbm_id02 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U02");
rbm_id03 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U03");
rbm_id04 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U04");
rbm_id05 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U05");
rbm_id06 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U06");
rbm_id07 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U07");
rbm_id08 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U08");
rbm_id09 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U09");
rbm_id10 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U10");
rbm_id11 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U11");
rbm_id12 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U12");
rbm_id13 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U13");
rbm_id14 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U14");
rbm_id15 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U15");
rbm_id16 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U16");
rbm_id17 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U17");
rbm_id18 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U00");
rbm_id19 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U01");
rbm_id20 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U02");
rbm_id21 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U03");
rbm_id22 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U04");
rbm_id23 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U05");
rbm_id24 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U06");
rbm_id25 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U07");
rbm_id26 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U08");
rbm_id27 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U09");
rbm_id28 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U10");
rbm_id29 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U11");
rbm_id30 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U12");
rbm_id31 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U13");
rbm_id32 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U14");
rbm_id33 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U15");
rbm_id34 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U16");
rbm_id35 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U17");
// Channe 2
rcm_id00 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U00");
rcm_id01 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U01");
rcm_id02 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U02");
rcm_id03 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U03");
rcm_id04 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U04");
rcm_id05 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U05");
rcm_id06 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U06");
rcm_id07 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U07");
rcm_id08 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U08");
rcm_id09 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U09");
rcm_id10 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U10");
rcm_id11 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U11");
rcm_id12 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U12");
rcm_id13 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U13");
rcm_id14 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U14");
rcm_id15 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U15");
rcm_id16 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U16");
rcm_id17 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U17");
rcm_id18 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U00");
rcm_id19 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U01");
rcm_id20 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U02");
rcm_id21 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U03");
rcm_id22 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U04");
rcm_id23 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U05");
rcm_id24 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U06");
rcm_id25 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U07");
rcm_id26 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U08");
rcm_id27 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U09");
rcm_id28 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U10");
rcm_id29 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U11");
rcm_id30 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U12");
rcm_id31 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U13");
rcm_id32 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U14");
rcm_id33 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U15");
rcm_id34 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U16");
rcm_id35 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U17");
// channel 3
rdm_id00 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U00");
rdm_id01 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U01");
rdm_id02 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U02");
rdm_id03 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U03");
rdm_id04 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U04");
rdm_id05 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U05");
rdm_id06 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U06");
rdm_id07 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U07");
rdm_id08 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U08");
rdm_id09 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U09");
rdm_id10 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U10");
rdm_id11 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U11");
rdm_id12 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U12");
rdm_id13 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U13");
rdm_id14 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U14");
rdm_id15 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U15");
rdm_id16 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U16");
rdm_id17 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U17");
rdm_id18 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U00");
rdm_id19 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U01");
rdm_id20 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U02");
rdm_id21 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U03");
rdm_id22 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U04");
rdm_id23 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U05");
rdm_id24 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U06");
rdm_id25 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U07");
rdm_id26 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U08");
rdm_id27 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U09");
rdm_id28 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U10");
rdm_id29 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U11");
rdm_id30 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U12");
rdm_id31 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U13");
rdm_id32 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U14");
rdm_id33 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U15");
rdm_id34 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U16");
rdm_id35 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U17");
//////////////////////////////////////
//workaround: for nested width problem
// Channel 0
ravid4 = $mmcreatesysmem("sysmem","ra_dimm144",36,1,1);
success=$mmaddtosysmem(ravid4,ram_id13,0,0,0);
success=$mmaddtosysmem(ravid4,ram_id04,1,0,0);
success=$mmaddtosysmem(ravid4,ram_id31,2,0,0);
success=$mmaddtosysmem(ravid4,ram_id22,3,0,0);
success=$mmaddtosysmem(ravid4,ram_id17,4,0,0);
success=$mmaddtosysmem(ravid4,ram_id16,5,0,0);
success=$mmaddtosysmem(ravid4,ram_id15,6,0,0);
success=$mmaddtosysmem(ravid4,ram_id14,7,0,0);
success=$mmaddtosysmem(ravid4,ram_id12,8,0,0);
success=$mmaddtosysmem(ravid4,ram_id11,9,0,0);
success=$mmaddtosysmem(ravid4,ram_id10,10,0,0);
success=$mmaddtosysmem(ravid4,ram_id09,11,0,0);
success=$mmaddtosysmem(ravid4,ram_id08,12,0,0);
success=$mmaddtosysmem(ravid4,ram_id07,13,0,0);
success=$mmaddtosysmem(ravid4,ram_id06,14,0,0);
success=$mmaddtosysmem(ravid4,ram_id05,15,0,0);
success=$mmaddtosysmem(ravid4,ram_id03,16,0,0);
success=$mmaddtosysmem(ravid4,ram_id02,17,0,0);
success=$mmaddtosysmem(ravid4,ram_id01,18,0,0);
success=$mmaddtosysmem(ravid4,ram_id00,19,0,0);
success=$mmaddtosysmem(ravid4,ram_id35,20,0,0);
success=$mmaddtosysmem(ravid4,ram_id34,21,0,0);
success=$mmaddtosysmem(ravid4,ram_id33,22,0,0);
success=$mmaddtosysmem(ravid4,ram_id32,23,0,0);
success=$mmaddtosysmem(ravid4,ram_id30,24,0,0);
success=$mmaddtosysmem(ravid4,ram_id29,25,0,0);
success=$mmaddtosysmem(ravid4,ram_id28,26,0,0);
success=$mmaddtosysmem(ravid4,ram_id27,27,0,0);
success=$mmaddtosysmem(ravid4,ram_id26,28,0,0);
success=$mmaddtosysmem(ravid4,ram_id25,29,0,0);
success=$mmaddtosysmem(ravid4,ram_id24,30,0,0);
success=$mmaddtosysmem(ravid4,ram_id23,31,0,0);
success=$mmaddtosysmem(ravid4,ram_id21,32,0,0);
success=$mmaddtosysmem(ravid4,ram_id20,33,0,0);
success=$mmaddtosysmem(ravid4,ram_id19,34,0,0);
success=$mmaddtosysmem(ravid4,ram_id18,35,0,0);
// Channel 1
rbvid4 = $mmcreatesysmem("sysmem","rb_dimm144",36,1,1);
success=$mmaddtosysmem(rbvid4,rbm_id13,0,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id04,1,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id31,2,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id22,3,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id17,4,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id16,5,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id15,6,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id14,7,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id12,8,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id11,9,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id10,10,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id09,11,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id08,12,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id07,13,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id06,14,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id05,15,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id03,16,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id02,17,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id01,18,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id00,19,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id35,20,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id34,21,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id33,22,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id32,23,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id30,24,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id29,25,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id28,26,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id27,27,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id26,28,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id25,29,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id24,30,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id23,31,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id21,32,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id20,33,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id19,34,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id18,35,0,0);
// Channel 2
rcvid4 = $mmcreatesysmem("sysmem","rc_dimm144",36,1,1);
success=$mmaddtosysmem(rcvid4,rcm_id13,0,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id04,1,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id31,2,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id22,3,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id17,4,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id16,5,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id15,6,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id14,7,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id12,8,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id11,9,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id10,10,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id09,11,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id08,12,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id07,13,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id06,14,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id05,15,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id03,16,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id02,17,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id01,18,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id00,19,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id35,20,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id34,21,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id33,22,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id32,23,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id30,24,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id29,25,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id28,26,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id27,27,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id26,28,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id25,29,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id24,30,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id23,31,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id21,32,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id20,33,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id19,34,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id18,35,0,0);
// Channel 3
rdvid4 = $mmcreatesysmem("sysmem","rd_dimm144",36,1,1);
success=$mmaddtosysmem(rdvid4,rdm_id13,0,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id04,1,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id31,2,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id22,3,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id17,4,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id16,5,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id15,6,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id14,7,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id12,8,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id11,9,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id10,10,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id09,11,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id08,12,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id07,13,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id06,14,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id05,15,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id03,16,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id02,17,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id01,18,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id00,19,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id35,20,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id34,21,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id33,22,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id32,23,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id30,24,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id29,25,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id28,26,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id27,27,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id26,28,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id25,29,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id24,30,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id23,31,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id21,32,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id20,33,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id19,34,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id18,35,0,0);
`ifdef STACK_DIMM
//////////////////////
// RANK 1, STACK 1
// Channel 0
rsam_id00 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U00");
rsam_id01 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U01");
rsam_id02 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U02");
rsam_id03 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U03");
rsam_id04 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U04");
rsam_id05 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U05");
rsam_id06 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U06");
rsam_id07 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U07");
rsam_id08 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U08");
rsam_id09 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U09");
rsam_id10 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U10");
rsam_id11 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U11");
rsam_id12 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U12");
rsam_id13 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U13");
rsam_id14 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U14");
rsam_id15 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U15");
rsam_id16 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U16");
rsam_id17 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U17");
rsam_id18 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U00");
rsam_id19 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U01");
rsam_id20 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U02");
rsam_id21 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U03");
rsam_id22 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U04");
rsam_id23 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U05");
rsam_id24 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U06");
rsam_id25 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U07");
rsam_id26 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U08");
rsam_id27 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U09");
rsam_id28 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U10");
rsam_id29 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U11");
rsam_id30 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U12");
rsam_id31 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U13");
rsam_id32 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U14");
rsam_id33 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U15");
rsam_id34 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U16");
rsam_id35 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U17");
// Channel 1
rsbm_id00 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U00");
rsbm_id01 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U01");
rsbm_id02 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U02");
rsbm_id03 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U03");
rsbm_id04 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U04");
rsbm_id05 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U05");
rsbm_id06 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U06");
rsbm_id07 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U07");
rsbm_id08 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U08");
rsbm_id09 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U09");
rsbm_id10 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U10");
rsbm_id11 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U11");
rsbm_id12 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U12");
rsbm_id13 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U13");
rsbm_id14 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U14");
rsbm_id15 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U15");
rsbm_id16 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U16");
rsbm_id17 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U17");
rsbm_id18 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U00");
rsbm_id19 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U01");
rsbm_id20 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U02");
rsbm_id21 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U03");
rsbm_id22 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U04");
rsbm_id23 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U05");
rsbm_id24 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U06");
rsbm_id25 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U07");
rsbm_id26 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U08");
rsbm_id27 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U09");
rsbm_id28 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U10");
rsbm_id29 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U11");
rsbm_id30 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U12");
rsbm_id31 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U13");
rsbm_id32 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U14");
rsbm_id33 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U15");
rsbm_id34 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U16");
rsbm_id35 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U17");
// Channel 2
rscm_id00 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U00");
rscm_id01 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U01");
rscm_id02 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U02");
rscm_id03 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U03");
rscm_id04 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U04");
rscm_id05 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U05");
rscm_id06 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U06");
rscm_id07 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U07");
rscm_id08 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U08");
rscm_id09 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U09");
rscm_id10 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U10");
rscm_id11 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U11");
rscm_id12 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U12");
rscm_id13 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U13");
rscm_id14 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U14");
rscm_id15 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U15");
rscm_id16 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U16");
rscm_id17 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U17");
rscm_id18 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U00");
rscm_id19 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U01");
rscm_id20 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U02");
rscm_id21 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U03");
rscm_id22 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U04");
rscm_id23 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U05");
rscm_id24 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U06");
rscm_id25 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U07");
rscm_id26 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U08");
rscm_id27 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U09");
rscm_id28 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U10");
rscm_id29 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U11");
rscm_id30 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U12");
rscm_id31 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U13");
rscm_id32 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U14");
rscm_id33 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U15");
rscm_id34 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U16");
rscm_id35 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U17");
// Channel 3
rsdm_id00 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U00");
rsdm_id01 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U01");
rsdm_id02 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U02");
rsdm_id03 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U03");
rsdm_id04 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U04");
rsdm_id05 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U05");
rsdm_id06 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U06");
rsdm_id07 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U07");
rsdm_id08 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U08");
rsdm_id09 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U09");
rsdm_id10 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U10");
rsdm_id11 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U11");
rsdm_id12 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U12");
rsdm_id13 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U13");
rsdm_id14 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U14");
rsdm_id15 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U15");
rsdm_id16 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U16");
rsdm_id17 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U17");
rsdm_id18 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U00");
rsdm_id19 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U01");
rsdm_id20 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U02");
rsdm_id21 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U03");
rsdm_id22 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U04");
rsdm_id23 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U05");
rsdm_id24 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U06");
rsdm_id25 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U07");
rsdm_id26 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U08");
rsdm_id27 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U09");
rsdm_id28 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U10");
rsdm_id29 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U11");
rsdm_id30 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U12");
rsdm_id31 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U13");
rsdm_id32 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U14");
rsdm_id33 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U15");
rsdm_id34 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U16");
rsdm_id35 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U17");
//////////////////////////////////////
//workaround: for nested width problem
// Channel 0
rsavid4 = $mmcreatesysmem("sysmem","rsa_dimm144",36,1,1);
success=$mmaddtosysmem(rsavid4,rsam_id13,0,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id04,1,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id31,2,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id22,3,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id17,4,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id16,5,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id15,6,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id14,7,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id12,8,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id11,9,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id10,10,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id09,11,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id08,12,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id07,13,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id06,14,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id05,15,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id03,16,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id02,17,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id01,18,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id00,19,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id35,20,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id34,21,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id33,22,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id32,23,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id30,24,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id29,25,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id28,26,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id27,27,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id26,28,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id25,29,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id24,30,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id23,31,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id21,32,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id20,33,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id19,34,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id18,35,0,0);
// Channel 1
rsbvid4 = $mmcreatesysmem("sysmem","rsb_dimm144",36,1,1);
success=$mmaddtosysmem(rsbvid4,rsbm_id13,0,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id04,1,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id31,2,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id22,3,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id17,4,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id16,5,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id15,6,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id14,7,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id12,8,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id11,9,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id10,10,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id09,11,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id08,12,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id07,13,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id06,14,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id05,15,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id03,16,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id02,17,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id01,18,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id00,19,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id35,20,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id34,21,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id33,22,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id32,23,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id30,24,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id29,25,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id28,26,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id27,27,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id26,28,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id25,29,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id24,30,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id23,31,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id21,32,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id20,33,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id19,34,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id18,35,0,0);
// Channel 2
rscvid4 = $mmcreatesysmem("sysmem","rsc_dimm144",36,1,1);
success=$mmaddtosysmem(rscvid4,rscm_id13,0,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id04,1,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id31,2,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id22,3,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id17,4,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id16,5,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id15,6,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id14,7,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id12,8,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id11,9,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id10,10,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id09,11,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id08,12,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id07,13,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id06,14,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id05,15,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id03,16,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id02,17,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id01,18,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id00,19,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id35,20,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id34,21,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id33,22,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id32,23,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id30,24,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id29,25,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id28,26,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id27,27,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id26,28,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id25,29,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id24,30,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id23,31,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id21,32,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id20,33,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id19,34,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id18,35,0,0);
// Channel 3
rsdvid4 = $mmcreatesysmem("sysmem","rsd_dimm144",36,1,1);
success=$mmaddtosysmem(rsdvid4,rsdm_id13,0,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id04,1,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id31,2,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id22,3,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id17,4,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id16,5,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id15,6,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id14,7,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id12,8,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id11,9,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id10,10,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id09,11,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id08,12,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id07,13,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id06,14,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id05,15,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id03,16,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id02,17,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id01,18,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id00,19,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id35,20,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id34,21,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id33,22,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id32,23,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id30,24,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id29,25,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id28,26,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id27,27,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id26,28,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id25,29,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id24,30,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id23,31,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id21,32,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id20,33,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id19,34,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id18,35,0,0);
`endif // ifdef STACK_DIMM
`endif // ifdef RANK_DIMM
if($test$plusargs("RANK_DIMM")) begin
if($test$plusargs("STACK_DIMM")) begin
//////////////////////////////////////
//Ranked and Stacked Syatem Memory
rsvid5 = $mmcreatesysmem("sysmem","rank_stack_unsc",1,16,1);
success=$mmaddtosysmem(rsvid5,avid4,0,0,0);
success=$mmaddtosysmem(rsvid5,savid4,0,1,0);
success=$mmaddtosysmem(rsvid5,ravid4,0,2,0);
success=$mmaddtosysmem(rsvid5,rsavid4,0,3,0);
success=$mmaddtosysmem(rsvid5,bvid4,0,4,0);
success=$mmaddtosysmem(rsvid5,sbvid4,0,5,0);
success=$mmaddtosysmem(rsvid5,rbvid4,0,6,0);
success=$mmaddtosysmem(rsvid5,rsbvid4,0,7,0);
success=$mmaddtosysmem(rsvid5,cvid4,0,8,0);
success=$mmaddtosysmem(rsvid5,scvid4,0,9,0);
success=$mmaddtosysmem(rsvid5,rcvid4,0,10,0);
success=$mmaddtosysmem(rsvid5,rscvid4,0,11,0);
success=$mmaddtosysmem(rsvid5,dvid4,0,12,0);
success=$mmaddtosysmem(rsvid5,sdvid4,0,13,0);
success=$mmaddtosysmem(rsvid5,rdvid4,0,14,0);
success=$mmaddtosysmem(rsvid5,rsdvid4,0,15,0);
// adding a DRAM bank bit and changing RAS to 15
// debugging with rank
//svid6 = $mmaddressmap("rank_stack_sc",rsvid5,"29 28 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 27 26 25 31 30 1 0");
// added the Col width bit as 25, DRAM bank now 8 => 26,27,28, STACK,RANK 29,30, L2 Bank 31 32
// correct
svid6 = $mmaddressmap("rank_stack_sc",rsvid5,"30 29 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 28 27 26 32 31 1 0");
//svid6 = $mmaddressmap("rank_stack_sc",rsvid5,"28 27 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 26 25 30 29 1 0");
//svid6 = $mmaddressmap("rank_stack_sc",rsvid5,"26 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 24 23 28 27 2 1 0");
end
else begin
//////////////////////////////////////
//Unranked and Stacked Syatem Memory
rvid5 = $mmcreatesysmem("sysmem","rank_unsc",1,8,1);
success=$mmaddtosysmem(rvid5,avid4,0,0,0);
success=$mmaddtosysmem(rvid5,ravid4,0,1,0);
success=$mmaddtosysmem(rvid5,bvid4,0,2,0);
success=$mmaddtosysmem(rvid5,rbvid4,0,3,0);
success=$mmaddtosysmem(rvid5,cvid4,0,4,0);
success=$mmaddtosysmem(rvid5,rcvid4,0,5,0);
success=$mmaddtosysmem(rvid5,dvid4,0,6,0);
success=$mmaddtosysmem(rvid5,rdvid4,0,7,0);
// adding a DRAM bank bit and changing RAS to 15
svid6 = $mmaddressmap("rank_sc",rvid5,"29 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 28 27 26 31 30 1 0");
//svid6 = $mmaddressmap("rank_sc",rvid5,"27 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 26 25 29 28 1 0");
//svid6 = $mmaddressmap("rank_sc",rvid5,"25 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 24 23 27 26 2 1 0");
end
end
else if($test$plusargs("STACK_DIMM")) begin
//////////////////////////////////////
//Unranked and Stacked Syatem Memory
svid5 = $mmcreatesysmem("sysmem","stack_unsc",1,8,1);
success=$mmaddtosysmem(svid5,avid4,0,0,0);
success=$mmaddtosysmem(svid5,savid4,0,1,0);
success=$mmaddtosysmem(svid5,bvid4,0,2,0);
success=$mmaddtosysmem(svid5,sbvid4,0,3,0);
success=$mmaddtosysmem(svid5,cvid4,0,4,0);
success=$mmaddtosysmem(svid5,scvid4,0,5,0);
success=$mmaddtosysmem(svid5,dvid4,0,6,0);
success=$mmaddtosysmem(svid5,sdvid4,0,7,0);
// adding a DRAM bank bit and changing RAS to 15
svid6 = $mmaddressmap("stack_sc",svid5,"29 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 28 27 26 31 30 1 0");
//svid6 = $mmaddressmap("stack_sc",svid5,"27 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 26 25 29 28 1 0");
//svid6 = $mmaddressmap("stack_sc",svid5,"22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 24 23 27 26 2 1 0");
end
else begin
//////////////////////////////////////
//Unranked and Unstacked Syatem Memory
vid5 = $mmcreatesysmem("sysmem","single_unsc",1,4,1);
success=$mmaddtosysmem(vid5,avid4,0,0,0);
success=$mmaddtosysmem(vid5,bvid4,0,1,0);
success=$mmaddtosysmem(vid5,cvid4,0,2,0);
success=$mmaddtosysmem(vid5,dvid4,0,3,0);
// adding a DRAM bank bit and changing RAS to 15
// as discussed with sunil
// 28,27,26 => DRAM Bank , 30,29 => L2 Bank
vid6 = $mmaddressmap("single_sc",vid5,"25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 28 27 26 30 29 1 0");
//vid6 = $mmaddressmap("single_sc",vid5,"24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 26 25 28 27 1 0");
//vid6 = $mmaddressmap("single_sc",vid5,"22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 24 23 26 25 2 1 0");
end // NOT STACK_DIMM
end
//////////////////////////////
// Pre Load the denali memory
initial begin
if($test$plusargs("RANK_DIMM")) begin
if($test$plusargs("STACK_DIMM")) begin
`ifdef DRAM_SAT
#12 success = $mmload("rank_stack_sc", "./denali.data");
`else
#12 success = $mmload("rank_stack_sc", "./denali.image");
`endif
//$display("%0d: After loading denali.dat to memory variable success = %d\n", $time, success);
end
else begin
#12 success = $mmload("rank_sc", "./denali.data");
end
end
else if($test$plusargs("STACK_DIMM")) begin
#12 success = $mmload("stack_sc", "./denali.data");
end
else begin
#12 success = $mmload("single_sc", "./denali.data");
end
end
////////////////////////////////
// Enable denali error Injection
initial begin
#1
if($test$plusargs("DENALI_ERROR")) begin
if($test$plusargs("RANK_DIMM")) begin
if($test$plusargs("STACK_DIMM")) begin
success = $mmerrinject(rsavid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rsbvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rscvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rsdvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
end
success = $mmerrinject(ravid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rbvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rcvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rdvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
end
if($test$plusargs("STACK_DIMM")) begin
success = $mmerrinject(savid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(sbvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(scvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(sdvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
end
success = $mmerrinject(avid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(bvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(cvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(dvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
end
end
`endif // DENALI_ON
/*
ch_mem AUTO_TEMPLATE (
// Outputs
.XXDQ (DRAM@_DQ[127:0]),
.XXCB (DRAM@_CB[15:0]),
.XXDQS (DRAM@_DQS[35:0]),
.XXSDA (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"),
// Inputs
.XXRAS_L (DRAM@_RAS_L),
.XXCAS_L (DRAM@_CAS_L),
.XXWE_L (DRAM@_WE_L),
.XXCS_L (DRAM@_CS_L[3:0]),
.XXRESET_L (DRAM@_RST_L),
.XXADDR (DRAM@_ADDR[14:0]),
.XXBA (DRAM@_BA[2:0]),
.XXCLK_L (DRAM@_CK_N[3:0]),
.XXCLK (DRAM@_CK_P[3:0]),
.XXCKE (DRAM@_CKE),
.XXSCL (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"));
*/
ch_mem mem0 (/*AUTOINST*/
// Inouts
.XXSDA (DRAM01), // Templated
.XXDQ (DRAM0_DQ[127:0]), // Templated
.XXCB (DRAM0_CB[15:0]), // Templated
.XXDQS (DRAM0_DQS[35:0]), // Templated
// Inputs
.XXRAS_L (DRAM0_RAS_L), // Templated
.XXCAS_L (DRAM0_CAS_L), // Templated
.XXWE_L (DRAM0_WE_L), // Templated
.XXCS_L (DRAM0_CS_L[3:0]), // Templated
.XXRESET_L (DRAM0_RST_L), // Templated
.XXADDR (DRAM0_ADDR[14:0]), // Templated
.XXBA (DRAM0_BA[2:0]), // Templated
.XXSA (XXSA[2:0]),
.XXSCL (DRAM01), // Templated
.XXWP (XXWP),
.XXCLK (DRAM0_CK_P[3:0]), // Templated
.XXCLK_L (DRAM0_CK_N[3:0]), // Templated
.XXCKE (DRAM0_CKE)); // Templated
ch_mem mem1 (/*AUTOINST*/
// Inouts
.XXSDA (DRAM23), // Templated
.XXDQ (DRAM1_DQ[127:0]), // Templated
.XXCB (DRAM1_CB[15:0]), // Templated
.XXDQS (DRAM1_DQS[35:0]), // Templated
// Inputs
.XXRAS_L (DRAM1_RAS_L), // Templated
.XXCAS_L (DRAM1_CAS_L), // Templated
.XXWE_L (DRAM1_WE_L), // Templated
.XXCS_L (DRAM1_CS_L[3:0]), // Templated
.XXRESET_L (DRAM1_RST_L), // Templated
.XXADDR (DRAM1_ADDR[14:0]), // Templated
.XXBA (DRAM1_BA[2:0]), // Templated
.XXSA (XXSA[2:0]),
.XXSCL (DRAM23), // Templated
.XXWP (XXWP),
.XXCLK (DRAM1_CK_P[3:0]), // Templated
.XXCLK_L (DRAM1_CK_N[3:0]), // Templated
.XXCKE (DRAM1_CKE)); // Templated
/*
ch_mem AUTO_TEMPLATE (
// Outputs
.XXDQ (DRAM@_DQ[127:0]),
.XXCB (DRAM@_CB[15:0]),
.XXDQS (DRAM@_DQS[35:0]),
.XXSDA (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"),
// Inputs
.XXRAS_L (DRAM@_RAS_L),
.XXCAS_L (DRAM@_CAS_L),
.XXWE_L (DRAM@_WE_L),
.XXCS_L (DRAM@_CS_L[3:0]),
.XXRESET_L (DRAM@_RST_L),
.XXADDR (DRAM@_ADDR[14:0]),
.XXBA (DRAM@_BA[2:0]),
.XXCLK_L (DRAM@_CK_N[3:0]),
.XXCLK (DRAM@_CK_P[3:0]),
.XXCKE (DRAM@_CKE),
.XXSCL (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"));
*/
ch_mem mem2 (/*AUTOINST*/
// Inouts
.XXSDA (DRAM45), // Templated
.XXDQ (DRAM2_DQ[127:0]), // Templated
.XXCB (DRAM2_CB[15:0]), // Templated
.XXDQS (DRAM2_DQS[35:0]), // Templated
// Inputs
.XXRAS_L (DRAM2_RAS_L), // Templated
.XXCAS_L (DRAM2_CAS_L), // Templated
.XXWE_L (DRAM2_WE_L), // Templated
.XXCS_L (DRAM2_CS_L[3:0]), // Templated
.XXRESET_L (DRAM2_RST_L), // Templated
.XXADDR (DRAM2_ADDR[14:0]), // Templated
.XXBA (DRAM2_BA[2:0]), // Templated
.XXSA (XXSA[2:0]),
.XXSCL (DRAM45), // Templated
.XXWP (XXWP),
.XXCLK (DRAM2_CK_P[3:0]), // Templated
.XXCLK_L (DRAM2_CK_N[3:0]), // Templated
.XXCKE (DRAM2_CKE)); // Templated
/*
ch_mem AUTO_TEMPLATE (
// Outputs
.XXDQ (DRAM@_DQ[127:0]),
.XXCB (DRAM@_CB[15:0]),
.XXDQS (DRAM@_DQS[35:0]),
.XXSDA (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"),
// Inputs
.XXRAS_L (DRAM@_RAS_L),
.XXCAS_L (DRAM@_CAS_L),
.XXWE_L (DRAM@_WE_L),
.XXCS_L (DRAM@_CS_L[3:0]),
.XXRESET_L (DRAM@_RST_L),
.XXADDR (DRAM@_ADDR[14:0]),
.XXBA (DRAM@_BA[2:0]),
.XXCLK_L (DRAM@_CK_N[3:0]),
.XXCLK (DRAM@_CK_P[3:0]),
.XXCKE (DRAM@_CKE),
.XXSCL (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"));
*/
ch_mem mem3 (/*AUTOINST*/
// Inouts
.XXSDA (DRAM67), // Templated
.XXDQ (DRAM3_DQ[127:0]), // Templated
.XXCB (DRAM3_CB[15:0]), // Templated
.XXDQS (DRAM3_DQS[35:0]), // Templated
// Inputs
.XXRAS_L (DRAM3_RAS_L), // Templated
.XXCAS_L (DRAM3_CAS_L), // Templated
.XXWE_L (DRAM3_WE_L), // Templated
.XXCS_L (DRAM3_CS_L[3:0]), // Templated
.XXRESET_L (DRAM3_RST_L), // Templated
.XXADDR (DRAM3_ADDR[14:0]), // Templated
.XXBA (DRAM3_BA[2:0]), // Templated
.XXSA (XXSA[2:0]),
.XXSCL (DRAM67), // Templated
.XXWP (XXWP),
.XXCLK (DRAM3_CK_P[3:0]), // Templated
.XXCLK_L (DRAM3_CK_N[3:0]), // Templated
.XXCKE (DRAM3_CKE)); // Templated
// don't include DRAM monitors when compiling for MSS SAT environment
`ifdef MSS_SAT
`else
/* cmp_dram_mon AUTO_TEMPLATE (
.clk (dram_gclk),
.dram_pad0_cs_l(DRAM0_CS_L[1:0]),
.dram_pad1_cs_l(DRAM1_CS_L[1:0]),
.dram_pad2_cs_l(DRAM2_CS_L[1:0]),
.dram_pad3_cs_l(DRAM3_CS_L[1:0]),
.rst_l(cmp_grst));
*/
cmp_dram_mon cmp_dram_mon (/*AUTOINST*/
// Inputs
.clk (dram_gclk), // Templated
.dram_pad0_cs_l(DRAM0_CS_L[1:0]), // Templated
.dram_pad1_cs_l(DRAM1_CS_L[1:0]), // Templated
.dram_pad2_cs_l(DRAM2_CS_L[1:0]), // Templated
.dram_pad3_cs_l(DRAM3_CS_L[1:0]), // Templated
.rst_l (cmp_grst)); // Templated
/* dimm_if_mon AUTO_TEMPLATE (
.clk (dram_gclk),
.DRAM_CK ({4{DRAM@_CK_P[3], DRAM@_CK_N[3]}}),
.DRAM_CKE (DRAM@_CKE),
.DRAM_RST_L (DRAM@_RST_L),
.DRAM_CS_L (DRAM@_CS_L[1:0]),
.DRAM_BA (DRAM@_BA[2:0]),
.DRAM_ADDR (DRAM@_ADDR[14:0]),
.DRAM_RAS_L (DRAM@_RAS_L),
.DRAM_CAS_L (DRAM@_CAS_L),
.DRAM_WE_L (DRAM@_WE_L),
.DRAM_DQ (DRAM@_DQ[127:0]),
.DRAM_CB (DRAM@_CB[15:0]),
.DRAM_DQS (DRAM@_DQS[35:0]),
.DRAM_ENB_ERROR (DRAM@_ENB_ERROR));
.DRAM_FAIL_OVER (DRAM@_FAIL_OVER));
.DRAM_FAIL_PART (DRAM@_FAIL_PART));
*/
dimm_if_mon dimm_if_mon0 (/*AUTOINST*/
// Inouts
.DRAM_DQ (DRAM0_DQ[127:0]), // Templated
// Inputs
.clk (dram_gclk), // Templated
.DRAM_CK ({4{DRAM0_CK_P[3], DRAM0_CK_N[3]}}), // Templated
.DRAM_CKE (DRAM0_CKE), // Templated
.DRAM_RST_L(DRAM0_RST_L), // Templated
.DRAM_CS_L (DRAM0_CS_L[1:0]), // Templated
.DRAM_BA (DRAM0_BA[2:0]), // Templated
.DRAM_ADDR (DRAM0_ADDR[14:0]), // Templated
.DRAM_RAS_L(DRAM0_RAS_L), // Templated
.DRAM_CAS_L(DRAM0_CAS_L), // Templated
.DRAM_WE_L (DRAM0_WE_L), // Templated
.DRAM_CB (DRAM0_CB[15:0]), // Templated
.DRAM_DQS (DRAM0_DQS[35:0]), // Templated
.DRAM_ENB_ERROR(DRAM0_ENB_ERROR), // Templated
.DRAM_FAIL_OVER(DRAM_FAIL_OVER),
.DRAM_FAIL_PART(DRAM_FAIL_PART[5:0]));
dimm_if_mon dimm_if_mon1 (/*AUTOINST*/
// Inouts
.DRAM_DQ (DRAM1_DQ[127:0]), // Templated
// Inputs
.clk (dram_gclk), // Templated
.DRAM_CK ({4{DRAM1_CK_P[3], DRAM1_CK_N[3]}}), // Templated
.DRAM_CKE (DRAM1_CKE), // Templated
.DRAM_RST_L(DRAM1_RST_L), // Templated
.DRAM_CS_L (DRAM1_CS_L[1:0]), // Templated
.DRAM_BA (DRAM1_BA[2:0]), // Templated
.DRAM_ADDR (DRAM1_ADDR[14:0]), // Templated
.DRAM_RAS_L(DRAM1_RAS_L), // Templated
.DRAM_CAS_L(DRAM1_CAS_L), // Templated
.DRAM_WE_L (DRAM1_WE_L), // Templated
.DRAM_CB (DRAM1_CB[15:0]), // Templated
.DRAM_DQS (DRAM1_DQS[35:0]), // Templated
.DRAM_ENB_ERROR(DRAM1_ENB_ERROR), // Templated
.DRAM_FAIL_OVER(DRAM_FAIL_OVER),
.DRAM_FAIL_PART(DRAM_FAIL_PART[5:0]));
dimm_if_mon dimm_if_mon2 (/*AUTOINST*/
// Inouts
.DRAM_DQ (DRAM2_DQ[127:0]), // Templated
// Inputs
.clk (dram_gclk), // Templated
.DRAM_CK ({4{DRAM2_CK_P[3], DRAM2_CK_N[3]}}), // Templated
.DRAM_CKE (DRAM2_CKE), // Templated
.DRAM_RST_L(DRAM2_RST_L), // Templated
.DRAM_CS_L (DRAM2_CS_L[1:0]), // Templated
.DRAM_BA (DRAM2_BA[2:0]), // Templated
.DRAM_ADDR (DRAM2_ADDR[14:0]), // Templated
.DRAM_RAS_L(DRAM2_RAS_L), // Templated
.DRAM_CAS_L(DRAM2_CAS_L), // Templated
.DRAM_WE_L (DRAM2_WE_L), // Templated
.DRAM_CB (DRAM2_CB[15:0]), // Templated
.DRAM_DQS (DRAM2_DQS[35:0]), // Templated
.DRAM_ENB_ERROR(DRAM2_ENB_ERROR), // Templated
.DRAM_FAIL_OVER(DRAM_FAIL_OVER),
.DRAM_FAIL_PART(DRAM_FAIL_PART[5:0]));
dimm_if_mon dimm_if_mon3 (/*AUTOINST*/
// Inouts
.DRAM_DQ (DRAM3_DQ[127:0]), // Templated
// Inputs
.clk (dram_gclk), // Templated
.DRAM_CK ({4{DRAM3_CK_P[3], DRAM3_CK_N[3]}}), // Templated
.DRAM_CKE (DRAM3_CKE), // Templated
.DRAM_RST_L(DRAM3_RST_L), // Templated
.DRAM_CS_L (DRAM3_CS_L[1:0]), // Templated
.DRAM_BA (DRAM3_BA[2:0]), // Templated
.DRAM_ADDR (DRAM3_ADDR[14:0]), // Templated
.DRAM_RAS_L(DRAM3_RAS_L), // Templated
.DRAM_CAS_L(DRAM3_CAS_L), // Templated
.DRAM_WE_L (DRAM3_WE_L), // Templated
.DRAM_CB (DRAM3_CB[15:0]), // Templated
.DRAM_DQS (DRAM3_DQS[35:0]), // Templated
.DRAM_ENB_ERROR(DRAM3_ENB_ERROR), // Templated
.DRAM_FAIL_OVER(DRAM_FAIL_OVER),
.DRAM_FAIL_PART(DRAM_FAIL_PART[5:0]));
`endif
initial begin
if ( $test$plusargs("CMP_DRAM_ENB_ERROR") ) begin
force `TOP_MOD.cmp_dram.DRAM0_ENB_ERROR = 1'b1;
force `TOP_MOD.cmp_dram.DRAM1_ENB_ERROR = 1'b1;
force `TOP_MOD.cmp_dram.DRAM2_ENB_ERROR = 1'b1;
force `TOP_MOD.cmp_dram.DRAM3_ENB_ERROR = 1'b1;
end
/*
DRAM0_FAIL_OVER = 1'b0;
DRAM1_FAIL_OVER = 1'b0;
DRAM2_FAIL_OVER = 1'b0;
DRAM3_FAIL_OVER = 1'b0;
DRAM0_FAIL_PART = 6'h0;
DRAM1_FAIL_PART = 6'h0;
DRAM2_FAIL_PART = 6'h0;
DRAM3_FAIL_PART = 6'h0;
*/
end
`ifdef DENALI_ON
//////////////////////////////////
// Task to enable error injection
//
task enb_errors;
input [3:0] ch;
input [17:0] comp;
input [31:0] seed;
input [3:0] bits;
integer m_id;
integer status;
begin
$display("%0d: Enabling error injection:- ch[%0d], component[%0d]\n", $time, ch, comp);
if (ch[0]) begin
if (comp[0]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U00");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[1]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U01");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[2]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U02");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[3]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U03");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[4]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U04");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[5]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U05");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[6]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U06");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[7]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U07");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[8]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U08");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[9]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U09");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[10]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U10");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[11]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U11");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[12]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U12");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[13]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U13");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[14]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U14");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[15]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U15");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[16]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U16");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[17]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U17");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
end
if (ch[1]) begin
if (comp[0]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U00");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[1]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U01");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[2]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U02");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[3]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U03");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[4]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U04");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[5]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U05");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[6]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U06");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[7]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U07");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[8]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U08");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[9]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U09");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[10]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U10");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[11]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U11");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[12]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U12");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[13]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U13");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[14]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U14");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[15]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U15");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[16]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U16");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[17]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U17");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
end
if (ch[2]) begin
if (comp[0]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U00");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[1]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U01");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[2]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U02");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[3]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U03");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[4]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U04");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[5]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U05");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[6]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U06");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[7]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U07");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[8]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U08");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[9]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U09");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[10]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U10");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[11]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U11");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[12]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U12");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[13]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U13");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[14]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U14");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[15]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U15");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[16]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U16");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[17]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U17");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
end
if (ch[3]) begin
if (comp[0]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U00");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[1]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U01");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[2]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U02");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[3]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U03");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[4]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U04");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[5]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U05");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[6]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U06");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[7]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U07");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[8]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U08");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[9]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U09");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[10]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U10");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[11]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U11");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[12]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U12");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[13]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U13");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[14]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U14");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[15]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U15");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[16]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U16");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[17]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U17");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
end
end
endtask
`endif // DENALI_ON
`ifdef GATE_SIM_DRAM
reg dram_i2c_enabled;
initial
begin
if ($test$plusargs("LO_STACK_RANK_BIT")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_bank_low_sel_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_bank_low_sel_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_bank_low_sel_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_bank_low_sel_u_dffrl_async_ns_0_.q = 1'b1 ;
end
end
initial
begin
if (!$test$plusargs("no_dram_slam_init")) begin
dram_i2c_enabled = 1'b0;
if ( ($test$plusargs("RANK_DIMM")) && ($test$plusargs("STACK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
end
else if ( ($test$plusargs("RANK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
end
else if ( ($test$plusargs("STACK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
end
if ($test$plusargs("DRAM_SCRUB")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_data_scrub_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_data_scrub_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_data_scrub_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_data_scrub_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_11_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_10_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_9_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_8_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_7_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_6_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_5_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_4_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_3_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_2_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_11_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_10_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_9_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_8_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_7_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_6_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_5_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_4_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_3_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_2_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_11_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_10_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_9_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_8_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_7_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_6_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_5_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_4_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_3_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_2_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_11_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_10_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_9_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_8_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_7_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_6_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_5_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_4_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_3_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_2_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_0_.q = 1'b0 ;
end
if ($test$plusargs("DIMM_SIZE_1G")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
end
else if ($test$plusargs("DIMM_SIZE_512")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
end
else if ($test$plusargs("DIMM_SIZE_256")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
end
else begin
// use default = 2G b
end
if ($test$plusargs("2CHANNEL_01")) begin
#1300000 force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ch_enabled_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ch_enabled_u_dffrl_async_ns_0_.q = 1'b1 ;
end
else if ($test$plusargs("2CHANNEL_23")) begin
#1300000 force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ch_enabled_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ch_enabled_u_dffrl_async_ns_0_.q = 1'b1 ;
end
end // of no_dram_slam_init
end
initial
begin
if (! $value$plusargs("force_cas_latency=%d", cas_latency)) begin
cas_latency = 3 ;
end
end
always @(posedge `DCTLPATH0.dram_rclk)
begin
if($test$plusargs("NO_BYPASS_POR_WAIT")) begin
if($test$plusargs("BYPASS_WMR_WAIT")) begin
// if warm reset and waiting for 200 us clocks
if({`DCTLPATH0.ch0_que_pos [4],
`DCTLPATH0.ch0_que_pos [3],
`DCTLPATH0.ch0_que_pos [2],
`DCTLPATH0.ch0_que_pos [1],
`DCTLPATH0.ch0_que_pos [0]} == 5'he)
begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
end else begin
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
end
end
end else begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_pad_clk_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_pad_clk_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_pad_clk_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_pad_clk_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_cke_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_cke_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_cke_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_cke_enable_u_dffrl_ns_0_.q = 1'b1 ;
if({`DCTLPATH0.ch0_que_pos [4],
`DCTLPATH0.ch0_que_pos [3],
`DCTLPATH0.ch0_que_pos [2],
`DCTLPATH0.ch0_que_pos [1],
`DCTLPATH0.ch0_que_pos [0]} == 5'h0)
begin
if(`DCTLPATH0.dramctl0_dram_dctl_dram_que_que_hw_selfrsh == 1'b0 )
begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_init = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_init = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_init = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_init = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
end
end
if({`DCTLPATH0.ch0_que_pos [4],
`DCTLPATH0.ch0_que_pos [3],
`DCTLPATH0.ch0_que_pos [2],
`DCTLPATH0.ch0_que_pos [1],
`DCTLPATH0.ch0_que_pos [0]} == 5'h1)
begin
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_init;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_init;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_init;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_init;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
end
// if warm reset and waiting for 200 us clocks
if({`DCTLPATH0.ch0_que_pos [4],
`DCTLPATH0.ch0_que_pos [3],
`DCTLPATH0.ch0_que_pos [2],
`DCTLPATH0.ch0_que_pos [1],
`DCTLPATH0.ch0_que_pos [0]} == 5'he)
begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
end else begin
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
end
end
end // always
`else // ifdef GATE_SIM_DRAM
//////////////////////////////////////
// These are hacks, remove them later
reg [5:0] dv_cnt;
reg [5:0] rtw_dly_reg;
initial
begin
if (!$value$plusargs("SYSTEM_DV_MATCH=%d", dv_cnt)) begin
dv_cnt = 2 ;
end
case(dv_cnt)
3 : rtw_dly_reg = 1;
4 : rtw_dly_reg = 2;
default : rtw_dly_reg = 0;
endcase
if ($test$plusargs("SYSTEM_DV_MATCH")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_data_del_cnt = dv_cnt;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_data_del_cnt = dv_cnt;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_data_del_cnt = dv_cnt;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_data_del_cnt = dv_cnt;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.rtw_dly_reg = rtw_dly_reg;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.rtw_dly_reg = rtw_dly_reg;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.rtw_dly_reg = rtw_dly_reg;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.rtw_dly_reg = rtw_dly_reg;
end
end
reg dram_i2c_enabled;
// set the corresponding registers to achieve this
initial
begin
if ($test$plusargs("LO_STACK_RANK_BIT")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_addr_bank_low_sel = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_addr_bank_low_sel = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_addr_bank_low_sel = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_addr_bank_low_sel = 1'b1;
end
end
initial
begin
// This is included to keep the DRAM SAT tests transperent to the
// no_slam_init related changes. no_slam_init is now in dram.config,
// so by default there is no slamming, but we need slamming in rank,stack/etc
// regressions, so add this SLAM_INIT_CMP, so as to nothing changes for SAT
`ifdef DRAM_SAT
if ($test$plusargs("SLAM_INIT_CMP")) begin
`else
if (!$test$plusargs("no_dram_slam_init")) begin
`endif // ifdef DRAM_SAT
dram_i2c_enabled = 1'b0;
if ( ($test$plusargs("RANK_DIMM")) && ($test$plusargs("STACK_DIMM")) &&
($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h4;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h4;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h4;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h4;
end
else if ( ($test$plusargs("RANK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
end
else if ( ($test$plusargs("STACK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
end
if ($test$plusargs("DRAM_SCRUB")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_data_scrub_enabled = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_data_scrub_enabled = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_data_scrub_enabled = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_data_scrub_enabled = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[20:9] =12'h10;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[20:9] =12'h10;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[20:9] =12'h10;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[20:9] =12'h10;
end
if ($test$plusargs("DIMM_SIZE_1G")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
end
else if ($test$plusargs("DIMM_SIZE_512")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
end
else if ($test$plusargs("DIMM_SIZE_256")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'hd;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'hd;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'hd;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'hd;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
end
else begin
// use default = 2G b
end
`ifdef TWO_CH_DELAY_LONG_VERSION
`define TWO_CHANNEL_DELAY #1300000
`else
`define TWO_CHANNEL_DELAY #600000
`endif
if ($test$plusargs("2CHANNEL_01")) begin
`TWO_CHANNEL_DELAY
//force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_channel_disabled = 1'b1;
//force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_channel_disabled = 1'b1;
force `DRAM_PATH2.que_channel_disabled = 1'b1;
force `DRAM_PATH3.que_channel_disabled = 1'b1;
end
else if ($test$plusargs("2CHANNEL_23")) begin
`TWO_CHANNEL_DELAY
//force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_channel_disabled = 1'b1;
//force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_channel_disabled = 1'b1;
force `DRAM_PATH0.que_channel_disabled = 1'b1;
force `DRAM_PATH1.que_channel_disabled = 1'b1;
end
else if ($test$plusargs("2CHANNEL_03")) begin
`TWO_CHANNEL_DELAY
//force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_channel_disabled = 1'b1;
//force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_channel_disabled = 1'b1;
force `DRAM_PATH2.que_channel_disabled = 1'b1;
force `DRAM_PATH1.que_channel_disabled = 1'b1;
end
else if ($test$plusargs("2CHANNEL_21") || $test$plusargs("2CHANNEL_12") ) begin
`TWO_CHANNEL_DELAY
//force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_channel_disabled = 1'b1;
//force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_channel_disabled = 1'b1;
force `DRAM_PATH0.que_channel_disabled = 1'b1;
force `DRAM_PATH3.que_channel_disabled = 1'b1;
end
end // no_slam_init
end
initial
begin
if (! $value$plusargs("force_cas_latency=%d", cas_latency)) begin
cas_latency = 3 ;
end
end
// This is env fix so that logic does not have to wait 200us on POR
always @(posedge `DCTLPATH0.dramctl0.dram_dctl.dram_que.clk)
begin
if($test$plusargs("NO_BYPASS_POR_WAIT")) begin
if($test$plusargs("BYPASS_WMR_WAIT")) begin
// if warm reset and waiting for 200 us clocks
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_pos == 5'he)
begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
end else begin
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
end
end
end else begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.dram_io_clk_enable = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.dram_io_clk_enable = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.dram_io_clk_enable = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.dram_io_clk_enable = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_cke_reg = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_cke_reg = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_cke_reg = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_cke_reg = 1'b1;
// If I2C read disabled or enabled and rd_done then init
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_pos == 5'h0)
begin
// when warm reset then dont force
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_hw_selfrsh == 1'b0 )
begin
// If we need to change the default parameters and issue que_init from diag
if (!$test$plusargs("QUE_INIT_FROM_DIAG")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_init = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_init = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_init = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_init = 1'b1;
end
if($test$plusargs("force_cas_latency")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.mode_reg[6:4] = cas_latency;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.mode_reg[6:4] = cas_latency;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.mode_reg[6:4] = cas_latency;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.mode_reg[6:4] = cas_latency;
// In DRAM SAT register update is done, this is only for cmp
`ifdef DRAM_SAT
`else
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.rp_reg = cas_latency;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.rp_reg = cas_latency;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.rp_reg = cas_latency;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.rp_reg = cas_latency;
`endif
//force `DCTLPATH0.dramctl0.dram_dctl.dram_que.dal_reg = 4'hc;
//force `DCTLPATH0.dramctl1.dram_dctl.dram_que.dal_reg = 4'hc;
//force `DCTLPATH1.dramctl0.dram_dctl.dram_que.dal_reg = 4'hc;
//force `DCTLPATH1.dramctl1.dram_dctl.dram_que.dal_reg = 4'hc;
end
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
end
end
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_pos == 5'h1)
begin
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_init;
release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_init;
release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_init;
release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_init;
//release `DCTLPATH0.dramctl0.dram_dctl.dram_que.dram_io_clk_enable;
//release `DCTLPATH0.dramctl1.dram_dctl.dram_que.dram_io_clk_enable;
//release `DCTLPATH1.dramctl0.dram_dctl.dram_que.dram_io_clk_enable;
//release `DCTLPATH1.dramctl1.dram_dctl.dram_que.dram_io_clk_enable;
//release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_cke_reg;
//release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_cke_reg;
//release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_cke_reg;
//release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_cke_reg;
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
end
// if warm reset and waiting for 200 us clocks
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_pos == 5'he)
begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
end else begin
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
end
end // NO_BYPASS_POR_WAIT
end // end always
// Added for bumping up the scrub counter
always @(posedge `DCTLPATH0.dramctl0.dram_dctl.dram_que.clk)
begin
if ($test$plusargs("SCRB_ADDR_BUMPUP")) begin
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_write_req == 1'b1)
begin
// If CAS is 2 ( que_scrb_cas_addr = 3) , bump it to 1fc
//if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr == 9'h2)
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr == 9'h1)
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr = 9'h1fe;
// If RAS is 2 ( que_scrb_ras_addr = 3) , bump it to 7ffc
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_ras_addr == 15'h2)
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_ras_addr = 15'h7ffe;
end
else
begin
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr;
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_ras_addr;
end
end // testplus arg
end // end always
//`ifdef WARM_RESET
initial
begin
if($test$plusargs("WARM_RESET")) begin
if($test$plusargs("POWER_THROTTLE")) begin
#6000000;
end
#300000;
#1905670;
//force `DCTLPATH0.dram_arst_l = 1'b1; This is not changed for warm reset.
force `DCTLPATH0.clspine_dram_selfrsh = 1'b1; // set refresh = 1 for warm refresh
#2000;
force `DCTLPATH0.jbus_grst_l = 1'b0;
force `DCTLPATH0.cmp_grst_l = 1'b0;
#2000;
//force `DCTLPATH0.clspine_dram_selfrsh = 1'b1; // set refresh = 1 for warm refresh
#1000000;
//#250000;
force `DCTLPATH0.dram_grst_l = 1'b0;
#700000;
force `DCTLPATH0.jbus_grst_l = 1'b1;
force `DCTLPATH0.cmp_grst_l = 1'b1;
force `DCTLPATH0.dram_grst_l = 1'b1;
#2000;
force `DCTLPATH0.clspine_dram_selfrsh = 1'b0; // set refresh = 1 for warm refresh
#700000;
release `DCTLPATH0.jbus_grst_l;
release `DCTLPATH0.cmp_grst_l;
release `DCTLPATH0.dram_grst_l;
end
end
//`endif
`endif // ifdef GATE_SIM_DRAM
endmodule //
// Local Variables:
// verilog-library-directories:("." "../../../design/sys/iop/rtl" "../../../design/sys/iop/dram/rtl""../../../design/sys/iop/pad_ddr02/rtl" "../../../design/sys/iop/pad_ddr13/rtl")
// verilog-library-extensions:(".v" ".h")
// End:
|
(** * Imp: Simple Imperative Programs *)
(* $Date: 2012-09-08 20:51:57 -0400 (Sat, 08 Sep 2012) $ *)
(** In this chapter, we begin a new direction that will
continue for the rest of the course. Up to now we've been mostly
studying Coq itself, but from now on we'll mostly be using Coq to
formalize other things.
Our first case study is a _simple imperative programming language_
called Imp. Here is a familiar mathematical function written in
Imp.
Z ::= X;
Y ::= 1;
WHILE not (Z = 0) DO
Y ::= Y * Z;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, the best-known logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
aexp ::= nat
| aexp '+' aexp
| aexp '-' aexp
| aexp '*' aexp
bexp ::= true
| false
| aexp '=' aexp
| aexp '<=' aexp
| bexp 'and' bexp
| 'not' bexp
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations: informal
ones for communicating between humans and formal ones for carrying
out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (e : aexp) : nat :=
match e with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (e : bexp) : bool :=
match e with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall e,
aeval (optimize_0plus e) = aeval e.
Proof.
intros e. induction e.
Case "ANum". reflexivity.
Case "APlus". destruct e1.
SCase "e1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHe2.
SSCase "n <> 0". simpl. rewrite IHe2. reflexivity.
SCase "e1 = APlus e1_1 e1_2".
simpl. simpl in IHe1. rewrite IHe1.
rewrite IHe2. reflexivity.
SCase "e1 = AMinus e1_1 e1_2".
simpl. simpl in IHe1. rewrite IHe1.
rewrite IHe2. reflexivity.
SCase "e1 = AMult e1_1 e1_2".
simpl. simpl in IHe1. rewrite IHe1.
rewrite IHe2. reflexivity.
Case "AMinus".
simpl. rewrite IHe1. rewrite IHe2. reflexivity.
Case "AMult".
simpl. rewrite IHe1. rewrite IHe2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
then [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not. *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** A similar tactical is [try]: If [T] is a tactic, then [try T]
is a tactic that is just like [T] except that, if [T] fails,
[try T] _successfully_ does nothing at all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but we'll
see below that [try] is very useful for doing automated proofs
in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its simplest and most commonly used form, the [;] tactical
takes 2 tactics as argument: [T;T'] first performs the tactic [T]
and then performs the tactic [T'] on _each subgoal_ generated by
[T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
(* ... which are discharged similarly *)
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* then do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall e,
aeval (optimize_0plus e) = aeval e.
Proof.
intros e.
induction e;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHe1; rewrite IHe2; reflexivity).
(* The remaining cases -- ANum and APlus -- are more
interesting... *)
Case "ANum". reflexivity.
Case "APlus".
destruct e1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHe1; rewrite IHe1;
rewrite IHe2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "e1 = ANum n". destruct n;
simpl; rewrite IHe2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a
tactic like [induction] to take care of many similar cases all at
once. Naturally, this practice has an analog in informal
proofs. *)
(** Here is an informal proof of this theorem that
matches the structure of the formal one:
_Theorem_: For all arithmetic expressions [e],
aeval (optimize_0plus e) = aeval e.
_Proof_: By induction on [e]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [e = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [e = APlus e1 e2] for some [e1] and [e2]. We
must show
aeval (optimize_0plus (APlus e1 e2))
= aeval (APlus e1 e2).
Consider the possible forms of [e1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [e1]; in these cases, the result follows directly from the
IH.
The interesting case is when [e1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus e1 e2) = optimize_0plus e2
and the IH for [e2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [e = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall e,
aeval (optimize_0plus e) = aeval e.
Proof.
intros e.
induction e;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHe1; rewrite IHe2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when e = APlus e1 e2. *)
Case "APlus".
destruct e1; try (simpl; simpl in IHe1; rewrite IHe1;
rewrite IHe2; reflexivity).
SCase "e1 = ANum n". destruct n;
simpl; rewrite IHe2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, and which is sometimes also useful.
If [T], [T1], ..., [Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
The form [T;T'] is used most often in practice. *)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [e] is a variable of type [aexp], then doing
aexp_cases (induction e) Case
will perform an induction on [e] (the same as if we had just typed
[induction e]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall e,
aeval (optimize_0plus e) = aeval e.
Proof.
intros e.
aexp_cases (induction e) Case;
try (simpl; rewrite IHe1; rewrite IHe2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct e1) SCase;
try (simpl; simpl in IHe1; rewrite IHe1; rewrite IHe2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHe2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (e:bexp) : bexp :=
match e with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 => BEq (optimize_0plus a1) (optimize_0plus a2)
| BLe a1 a2 => BLe (optimize_0plus a1) (optimize_0plus a2)
| BNot b1 => BNot (optimize_0plus_b b1)
| BAnd b1 b2 => BAnd (optimize_0plus_b b1) (optimize_0plus_b b2)
end.
Theorem optimize_0plus_b_sound: forall e,
beval (optimize_0plus_b e) = beval e.
Proof.
intros e.
induction e;
try reflexivity;
try (simpl; rewrite 2! optimize_0plus_sound; reflexivity);
try (simpl; rewrite IHe; reflexivity);
try (simpl; rewrite IHe1; rewrite IHe2; reflexivity).
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
(* FILL IN HERE *)
*)
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Andrew Appel calls this the "Santa Claus tactic." We'll see
examples of its use below. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c].
We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation, one that we
will see is often more flexible, is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** We can make the proof quite a bit shorter by making more
aggressive use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
Inductive bevalR : bexp -> bool -> Prop :=
| E_BTrue : bevalR BTrue true
| E_BFalse : bevalR BFalse false
| E_BEq : forall (e1 e2 : aexp) (n1 n2 : nat),
aevalR e1 n1 -> aevalR e2 n2 ->
bevalR (BEq e1 e2) (beq_nat n1 n2)
| E_BLe : forall (e1 e2 : aexp) (n1 n2 : nat),
aevalR e1 n1 -> aevalR e2 n2 ->
bevalR (BLe e1 e2) (ble_nat n1 n2)
| E_BNot : forall (e : bexp) (b : bool),
bevalR e b -> bevalR (BNot e) (negb b)
| E_BAnd : forall (e1 e2 : bexp) (b1 b2 : bool),
bevalR e1 b1 -> bevalR e2 b2 ->
bevalR (BAnd e1 e2) (andb b1 b2).
Theorem beval_iff_bevalR : forall e b,
(bevalR e b) <-> beval e = b.
Proof.
split.
Case "->".
intros H.
induction H.
SCase "E_BTrue".
reflexivity.
SCase "E_BFalse".
reflexivity.
SCase "E_BEq".
simpl.
rewrite aeval_iff_aevalR in H. rewrite H.
rewrite aeval_iff_aevalR in H0. rewrite H0.
reflexivity.
SCase "E_BLe".
simpl.
rewrite aeval_iff_aevalR in H. rewrite H.
rewrite aeval_iff_aevalR in H0. rewrite H0.
reflexivity.
SCase "E_BNot".
simpl.
rewrite IHbevalR.
reflexivity.
SCase "E_BAnd".
simpl.
rewrite IHbevalR1.
rewrite IHbevalR2.
reflexivity.
Case "<-".
generalize dependent b.
induction e.
SCase "BTrue".
intros b H.
rewrite <- H. simpl. apply E_BTrue.
SCase "BFalse".
intros b H.
rewrite <- H. simpl. apply E_BFalse.
SCase "BEq".
intros b H.
rewrite <- H. simpl. apply E_BEq.
apply aeval_iff_aevalR. reflexivity.
apply aeval_iff_aevalR. reflexivity.
SCase "BLe".
intros b H.
rewrite <- H. simpl. apply E_BLe.
apply aeval_iff_aevalR. reflexivity.
apply aeval_iff_aevalR. reflexivity.
SCase "BNot".
intros b H.
rewrite <- H. simpl. apply E_BNot.
apply IHe. reflexivity.
SCase "BAnd".
intros b H.
rewrite <- H. simpl. apply E_BAnd.
apply IHe1. reflexivity.
apply IHe2. reflexivity.
Qed.
(** [] *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computational mechanism.
However, there are circumstances where relational definitions of
evaluation are greatly preferable to functional ones, as we'll see
shortly. *)
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient write the rules for
[aevalR] and similar relations in the more readable "graphical"
form of _inference rules_, where the premises above the line
justify the conclusion below the line. For example, the
constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
Formally, there is nothing very deep about inference rules: they
are just implications. You can read the rule name on the right as
the name of the constructor and read each of the linebreaks
between the premises above the line and the line itself as [->].
All the variables mentioned in the rule ([e1], [n1], etc.) are
implicitly bound by universal quantifiers at the beginning. The
whole collection of rules is understood as being wrapped in an
[Inductive] declaration (informally, this is either elided or else
indicated by saying something like "Let [aevalR] be the smallest
relation closed under the following rules...").
For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
End AExp.
(* ####################################################### *)
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers.
(We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. *)
Inductive id : Type :=
Id : nat -> id.
Definition beq_id X1 X2 :=
match (X1, X2) with
(Id n1, Id n2) => beq_nat n1 n2
end.
(** After we "wrap" numbers as identifiers in this way, it is
convenient to recapitulate a few properties of numbers as
analogous properties of identifiers, so that we can work with
identifiers in definitions and proofs abstractly, without
unwrapping them to expose the underlying numbers. Since all we
need to know about identifiers is whether they are the same or
different, just a few basic facts are all we need. *)
Theorem beq_id_refl : forall X,
true = beq_id X X.
Proof.
intros. destruct X.
apply beq_nat_refl. Qed.
(** **** Exercise: 1 star, optional (beq_id_eq) *)
(** For this and the following exercises, do not use induction, but
rather apply similar results already proved for natural numbers.
Some of the tactics mentioned above may prove useful. *)
Theorem beq_id_eq : forall i1 i2,
true = beq_id i1 i2 -> i1 = i2.
Proof.
intros. destruct i1. destruct i2. unfold beq_id in H.
apply beq_nat_eq in H. rewrite H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (beq_id_false_not_eq) *)
Theorem beq_id_false_not_eq : forall i1 i2,
beq_id i1 i2 = false -> i1 <> i2.
Proof.
intros. destruct i1. destruct i2. unfold beq_id in H.
apply beq_nat_false in H. intros C. apply H. inversion C. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (not_eq_beq_id_false) *)
Theorem not_eq_beq_id_false : forall i1 i2,
i1 <> i2 -> beq_id i1 i2 = false.
Proof.
intros. destruct i1. destruct i2. unfold beq_id.
rewrite beq_nat_false_iff. intros C. apply H. rewrite C. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (beq_id_sym) *)
Theorem beq_id_sym: forall i1 i2,
beq_id i1 i2 = beq_id i2 i1.
Proof.
intros. destruct i1. destruct i2. unfold beq_id. apply beq_nat_sym.
Qed.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of all the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them. *)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (X:id) (n : nat) : state :=
fun X' => if beq_id X X' then n else st X'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n X st,
(update st X n) X = n.
Proof.
intros. unfold update. rewrite <- beq_id_refl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall V2 V1 n st,
beq_id V2 V1 = false ->
(update st V2 n) V1 = (st V1).
Proof.
intros. unfold update. rewrite H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
intros. unfold update. simpl. unfold empty_state. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, recommended (update_shadow) *)
Theorem update_shadow : forall x1 x2 k1 k2 (f : state),
(update (update f k2 x1) k2 x2) k1 = (update f k2 x2) k1.
Proof.
intros. unfold update. destruct (beq_id k2 k1).
reflexivity. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall x1 k1 k2 (f : state),
f k1 = x1 ->
(update f k1 x1) k2 = f k2.
Proof.
intros. unfold update. remember (beq_id k1 k2) as t. destruct t.
apply beq_id_eq in Heqt. rewrite <- H. rewrite Heqt. reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall x1 x2 k1 k2 k3 f,
beq_id k2 k1 = false ->
(update (update f k2 x1) k1 x2) k3 = (update (update f k1 x2) k2 x1) k3.
Proof.
intros. unfold update.
remember (beq_id k1 k3) as t. destruct t.
Case "true = beq_id k1 k3".
remember (beq_id k2 k3) as u. destruct u.
SCase "true = beq_id k2 k3".
apply beq_id_eq in Heqt. apply beq_id_eq in Hequ. subst.
rewrite <- beq_id_refl in H. inversion H.
SCase "false = beq_id k2 k3".
reflexivity.
Case "false = beq_id k1 k3".
remember (beq_id k2 k3) as u. destruct u.
SCase "true = beq_id k2 k3".
reflexivity.
SCase "false = beq_id k2 k3".
reflexivity.
Qed.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (e : aexp) : nat :=
match e with
| ANum n => n
| AId X => st X (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (e : bexp) : bool :=
match e with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (or _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands are described by the following BNF
grammar:
com ::= 'SKIP'
| X '::=' aexp
| com ';' com
| 'WHILE' bexp 'DO' com 'END'
| 'IFB' bexp 'THEN' com 'ELSE' com 'FI'
For example, here's the factorial function in Imp.
Z ::= X;
Y ::= 1;
WHILE not (Z = 0) DO
Y ::= Y * Z;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;
Y ::= ANum 1;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;
X ::= AMinus (AId X) (ANum 1).
(** Loops: *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;
Z ::= ANum 5 ;
subtract_slowly.
(** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(** Factorial again (broken up into smaller pieces this time, for
convenience when we come back to proving things about it
later). *)
Definition fact_body : com :=
Y ::= AMult (AId Y) (AId Z) ;
Z ::= AMinus (AId Z) (ANum 1).
Definition fact_loop : com :=
WHILE BNot (BEq (AId Z) (ANum 0)) DO
fact_body
END.
Definition fact_com : com :=
Z ::= AId X ;
Y ::= ANum 1 ;
fact_loop.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky ... *)
(* #################################### *)
(** ** Evaluation Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b1 DO c1 END)
else st
end.
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the full version of
the [ceval_fun] function applied to the [loop] program above would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks, which make everything much more complicated
(see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] and [bevalR] above. *)
(** This is an important change. Besides freeing us from the
hacks that would be needed to define an evaluation function, it
gives us a lot more flexibility in the definition. For example,
if we added concurrency features to the language, we'd want the
definition of evaluation to be non-deterministic -- i.e., not only
would it not be total, it would not even be a partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation,
that is [c / st || st'] means that executing program [c] in a
starting state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
X := a1 / st || (update st X n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b1 DO c1 END / st || st
beval st b1 = true
c1 / st || st'
WHILE b1 DO c1 END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b1 DO c1 END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
(X ::= a1) / st || (update st X n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ; c2) / st || st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
c1 / st || st' ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
c2 / st || st' ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0; Y ::= ANum 1; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
apply E_Seq with (update empty_state X 0).
Case "X ::= ANum 0".
apply E_Ass. reflexivity.
Case "Y ::= ANum 1; Z ::= ANum 2".
apply E_Seq with (update (update empty_state X 0) Y 1).
SCase "Y ::= ANum 1".
apply E_Ass. reflexivity.
SCase "Z ::= ANum 2".
apply E_Ass. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(Y ::= ANum 0;
WHILE BNot (BEq (AId X) (ANum 0)) DO
Y ::= APlus (AId Y) (AId X);
X ::= AMinus (AId X) (ANum 1)
END).
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
remember (update (update empty_state X 2) Y 0) as st1.
apply E_Seq with st1.
Case "Y ::= ANum 0".
subst. apply E_Ass. reflexivity.
Case "LOOP".
remember (update (update st1 Y 2) X 1) as st2.
apply E_WhileLoop with st2.
SCase "TEST".
subst. reflexivity.
SCase "BODY".
apply E_Seq with (update st1 Y 2).
SSCase "Y ::= APlus (AId Y) (AId X)".
apply E_Ass. subst. reflexivity.
SSCase "X ::= AMinus (AId X) (ANum 1)".
subst. apply E_Ass. reflexivity.
SCase "LOOP".
remember (update (update st2 Y 3) X 0) as st3.
apply E_WhileLoop with st3.
SSCase "TEST".
subst. reflexivity.
SSCase "BODY".
apply E_Seq with (update st2 Y 3).
SSSCase "Y ::= APlus (AId Y) (AId X)".
apply E_Ass. subst. reflexivity.
SSSCase "X ::= AMinus (AId X) (ANum 1)".
subst. apply E_Ass. reflexivity.
SSCase "END".
apply E_WhileEnd. subst. reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to true".
reflexivity.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to false".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. This section
explores some examples. *)
(** ** Basic Examples *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars, recommended (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
Theorem XtimesYinZ_spec : forall st n m st',
st X = n ->
st Y = m ->
XtimesYinZ / st || st' ->
st' Z = n * m.
Proof.
intros st n m st' HX HY Heval.
inversion Heval. subst. clear Heval. simpl.
apply update_eq.
Qed.
(** [] *)
(** **** Exercise: 3 stars, recommended (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
ceval_cases (induction contra) Case;
inversion Heqloopdef; subst.
Case "E_WhileEnd".
inversion H.
Case "E_WhileLoop".
apply IHcontra2. reflexivity.
Qed.
(** [] *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** **** Exercise: 3 stars, optional (no_whilesR) *)
(** The [no_whiles] property yields [true] on just those programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
| nw_skip : no_whilesR SKIP
| nw_ass : forall X e, no_whilesR (X ::= e)
| nw_seq : forall c1 c2, no_whilesR c1 -> no_whilesR c2 ->
no_whilesR (c1 ; c2)
| nw_if : forall b ct cf, no_whilesR ct -> no_whilesR cf ->
no_whilesR (IFB b THEN ct ELSE cf FI).
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
split.
Case "->".
intros H.
com_cases (induction c) SCase;
try constructor;
try apply IHc1; try apply IHc2;
try (inversion H; rewrite H1; apply andb_prop in H1; inversion H1);
try apply H0; try apply H2;
try inversion H.
Case "<-".
intros H.
induction H;
try reflexivity;
try (simpl; rewrite andb_true_iff; split; assumption).
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(* FILL IN HERE *)
(** [] *)
(** ** Proving a Program Correct (Optional) *)
(** Recall the factorial program: *)
Print fact_body. Print fact_loop. Print fact_com.
(** Here is an alternative "mathematical" definition of the factorial
function: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** We would like to show that they agree -- if we start [fact_com] in
a state where variable [X] contains some number [x], then it will
terminate in a state where variable [Y] contains the factorial of
[x].
To show this, we rely on the critical idea of a _loop
invariant_. *)
Definition fact_invariant (x:nat) (st:state) :=
(st Y) * (real_fact (st Z)) = real_fact x.
Theorem fact_body_preserves_invariant: forall st st' x,
fact_invariant x st ->
st Z <> 0 ->
fact_body / st || st' ->
fact_invariant x st'.
Proof.
unfold fact_invariant, fact_body.
intros st st' x Hm HZnz He.
inversion He; subst; clear He.
inversion H1; subst; clear H1.
inversion H4; subst; clear H4.
unfold update. simpl.
(* Show that st Z = S z' for some z' *)
destruct (st Z) as [| z'].
apply ex_falso_quodlibet. apply HZnz. reflexivity.
rewrite <- Hm. rewrite <- mult_assoc.
replace (S z' - 1) with z' by omega.
reflexivity. Qed.
Theorem fact_loop_preserves_invariant : forall st st' x,
fact_invariant x st ->
fact_loop / st || st' ->
fact_invariant x st'.
Proof.
intros st st' x H Hce.
remember fact_loop as c.
ceval_cases (induction Hce) Case;
inversion Heqc; subst; clear Heqc.
Case "E_WhileEnd".
(* trivial when the loop doesn't run... *)
assumption.
Case "E_WhileLoop".
(* if the loop does run, we know that fact_body preserves
fact_invariant -- we just need to assemble the pieces *)
apply IHHce2.
apply fact_body_preserves_invariant with st;
try assumption.
intros Contra. simpl in H0; subst.
rewrite Contra in H0. inversion H0.
reflexivity. Qed.
Theorem guard_false_after_loop: forall b c st st',
(WHILE b DO c END) / st || st' ->
beval st' b = false.
Proof.
intros b c st st' Hce.
remember (WHILE b DO c END) as cloop.
ceval_cases (induction Hce) Case;
inversion Heqcloop; subst; clear Heqcloop.
Case "E_WhileEnd".
assumption.
Case "E_WhileLoop".
apply IHHce2. reflexivity. Qed.
(** Patching it all together... *)
Theorem fact_com_correct : forall st st' x,
st X = x ->
fact_com / st || st' ->
st' Y = real_fact x.
Proof.
intros st st' x HX Hce.
inversion Hce; subst; clear Hce.
inversion H1; subst; clear H1.
inversion H4; subst; clear H4.
inversion H1; subst; clear H1.
rename st' into st''. simpl in H5.
(* The invariant is true before the loop runs... *)
remember (update (update st Z (st X)) Y 1) as st'.
assert (fact_invariant (st X) st').
subst. unfold fact_invariant, update. simpl. omega.
(* ...so when the loop is done running, the invariant
is maintained *)
assert (fact_invariant (st X) st'').
apply fact_loop_preserves_invariant with st'; assumption.
unfold fact_invariant in H0.
(* Finally, if the loop terminated, then Z is 0; so Y must be
factorial of X *)
apply guard_false_after_loop in H5. simpl in H5.
destruct (st'' Z).
Case "st'' Z = 0". simpl in H0. omega.
Case "st'' Z > 0 (impossible)". inversion H5.
Qed.
(** One might wonder whether all this work with poking at states and
unfolding definitions could be ameliorated with some more powerful
lemmas and/or more uniform reasoning principles... Indeed, this is
exactly the topic of the upcoming [Hoare] chapter! *)
(** **** Exercise: 4 stars, optional (subtract_slowly_spec) *)
(** Prove a specification for subtract_slowly, using the above
specification of [fact_com] and the invariant below as
guides. *)
Definition ss_invariant (x:nat) (z:nat) (st:state) :=
minus (st Z) (st X) = minus z x.
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** **** Exercise: 4 stars, recommended (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions, and to prove its
correctness.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad X]: Load the identifier [X] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply.
*)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense it is
immaterial, since our compiler will never emit such a malformed
program. However, when you do the correctness proof you may find
some choices makes the proof easier than others. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
match prog with
| [] => stack
| SPush n :: is =>
s_execute st (n :: stack) is
| SLoad X :: is =>
s_execute st (st X :: stack) is
| SPlus :: is =>
match stack with
| n2 :: n1 :: ns =>
s_execute st (n1 + n2 :: ns) is
| _ => s_execute st stack is
end
| SMinus :: is =>
match stack with
| n2 :: n1 :: ns =>
s_execute st (n1 - n2 :: ns) is
| _ => s_execute st stack is
end
| SMult :: is =>
match stack with
| n2 :: n1 :: ns =>
s_execute st (n1 * n2 :: ns) is
| _ => s_execute st stack is
end
end.
Example s_execute1 :
s_execute empty_state []
[SPush 5, SPush 3, SPush 1, SMinus]
= [2, 5].
Proof. reflexivity. Qed.
Example s_execute2 :
s_execute (update empty_state X 3) [3,4]
[SPush 4, SLoad X, SMult, SPlus]
= [15, 4].
Proof. reflexivity. Qed.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
match e with
| ANum n => [SPush n]
| AId X => [SLoad X]
| APlus e1 e2 => (s_compile e1) ++ (s_compile e2) ++ [SPlus]
| AMinus e1 e2 => (s_compile e1) ++ (s_compile e2) ++ [SMinus]
| AMult e1 e2 => (s_compile e1) ++ (s_compile e2) ++ [SMult]
end.
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X, SPush 2, SLoad Y, SMult, SMinus].
Proof. reflexivity. Qed.
(** Finally, prove the following theorem, stating that the [compile]
function behaves correctly. You will need to start by stating a
more general lemma to get a usable induction hypothesis. *)
Lemma s_execute_cons :
forall (st : state) (stack : list nat) (i : sinstr) (is : list sinstr),
s_execute st stack (i :: is) =
s_execute st (s_execute st stack [i]) is.
Proof.
intros.
destruct i;
try reflexivity;
try (destruct stack as [| h t];
try reflexivity;
try (destruct t;
reflexivity)).
Qed.
Lemma s_execute_app :
forall (st : state) (stack : list nat) (i1 i2 : list sinstr),
s_execute st stack (i1 ++ i2) =
s_execute st (s_execute st stack i1) i2.
Proof.
intros. generalize dependent stack.
induction i1 as [| i is].
Case "i1 = []".
intros stack.
reflexivity.
Case "i1 = i :: is".
intros stack.
destruct i2 as [| i' is'].
SCase "i2 = []".
rewrite <- app_nil_end. reflexivity.
SCase "i2 = i' :: is'".
replace ((i :: is) ++ i' :: is') with (i :: is ++ i' :: is').
rewrite s_execute_cons. rewrite IHis.
rewrite <- s_execute_cons. reflexivity.
reflexivity.
Qed.
Lemma s_compile_correct_gen :
forall (st : state) (e : aexp) (stack : list nat),
s_execute st stack (s_compile e) = aeval st e :: stack.
Proof.
intros. generalize dependent stack.
aexp_cases (induction e) Case;
intros; simpl;
try reflexivity;
try (rewrite s_execute_app; rewrite IHe1;
rewrite s_execute_app; rewrite IHe2;
reflexivity).
Qed.
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [aeval st e].
Proof.
intros. apply s_compile_correct_gen.
Qed.
(** [] *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_TB_V
`define SKY130_FD_SC_MS__A222OI_TB_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a222oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A1 = 1'b1;
#240 A2 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 C1 = 1'b1;
#320 C2 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A1 = 1'b0;
#440 A2 = 1'b0;
#460 B1 = 1'b0;
#480 B2 = 1'b0;
#500 C1 = 1'b0;
#520 C2 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 C2 = 1'b1;
#720 C1 = 1'b1;
#740 B2 = 1'b1;
#760 B1 = 1'b1;
#780 A2 = 1'b1;
#800 A1 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 C2 = 1'bx;
#920 C1 = 1'bx;
#940 B2 = 1'bx;
#960 B1 = 1'bx;
#980 A2 = 1'bx;
#1000 A1 = 1'bx;
end
sky130_fd_sc_ms__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_rml_cwp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_rml_cwp
// Description: Register management logic. Contains CWP, CANSAVE, CANRESTORE
// and other window management registers. Generates RF related traps
// and switches the global registers to alternate globals. All the registers
// are written in the W stage (there is no bypassing so they must
// swap out) and will either get a new value generated by a window management
// Instruction or by a WRPS instruction. The following traps can be generated:
// Fill: restore with canrestore == 0
// clean_window: save with cleanwin-canrestore == 0
// spill: flushw with cansave != nwindows -2 or
// save with cansave == 0
// It is assumed that the contents of the new window will get squashed
// on a clean_window or fill trap so the save or restore gets executed
// normally. Spill traps or WRCWPs mean that all 16 windowed registers
// must be saved and restored (a 4 cycle operation).
*/
module sparc_exu_rml_cwp (/*AUTOARG*/
// Outputs
rml_ecl_cwp_d, rml_ecl_cwp_e, exu_tlu_cwp0_w, exu_tlu_cwp1_w,
exu_tlu_cwp2_w, exu_tlu_cwp3_w, rml_irf_cwpswap_tid_e, old_cwp_e,
new_cwp_e, swap_locals_ins, swap_outs, exu_tlu_spill,
exu_tlu_spill_wtype, exu_tlu_spill_other, exu_tlu_spill_tid,
rml_ecl_swap_done, exu_tlu_cwp_cmplt, exu_tlu_cwp_cmplt_tid,
exu_tlu_cwp_retry, oddwin_w,
// Inputs
clk, se, reset, rst_tri_en, rml_ecl_wtype_e, rml_ecl_other_e,
exu_tlu_spill_e, tlu_exu_cwpccr_update_m, tlu_exu_cwp_retry_m,
tlu_exu_cwp_m, thr_d, ecl_rml_thr_m, ecl_rml_thr_w, tid_e,
next_cwp_w, next_cwp_e, cwp_wen_w, save_e, restore_e,
ifu_exu_flushw_e, ecl_rml_cwp_wen_e, full_swap_e, rml_kill_w
) ;
input clk;
input se;
input reset;
input rst_tri_en;
input [2:0] rml_ecl_wtype_e;
input rml_ecl_other_e;
input exu_tlu_spill_e;
input tlu_exu_cwpccr_update_m;
input tlu_exu_cwp_retry_m;
input [2:0] tlu_exu_cwp_m; // for switching cwp on return from trap
input [3:0] thr_d;
input [3:0] ecl_rml_thr_m;
input [3:0] ecl_rml_thr_w;
input [1:0] tid_e;
input [2:0] next_cwp_w;
input [2:0] next_cwp_e;
input cwp_wen_w;
input save_e;
input restore_e;
input ifu_exu_flushw_e;
input ecl_rml_cwp_wen_e;
input full_swap_e;
input rml_kill_w;
output [2:0] rml_ecl_cwp_d;
output [2:0] rml_ecl_cwp_e;
output [2:0] exu_tlu_cwp0_w;
output [2:0] exu_tlu_cwp1_w;
output [2:0] exu_tlu_cwp2_w;
output [2:0] exu_tlu_cwp3_w;
output [1:0] rml_irf_cwpswap_tid_e;
output [2:0] old_cwp_e;
output [2:0] new_cwp_e;
output swap_locals_ins;
output swap_outs;
output exu_tlu_spill;
output [2:0] exu_tlu_spill_wtype;
output exu_tlu_spill_other;
output [1:0] exu_tlu_spill_tid;
output [3:0] rml_ecl_swap_done;
output exu_tlu_cwp_cmplt;
output [1:0] exu_tlu_cwp_cmplt_tid;
output exu_tlu_cwp_retry;
output [3:0] oddwin_w;
wire can_swap;
wire swapping;
wire just_swapped;
wire full_swap_m;
wire full_swap_w;
wire [3:0] swap_done_next_cycle;
wire [3:0] swap_sel_input;
wire [3:0] swap_sel_tlu;
wire [3:0] swap_keep_value;
wire [2:0] trap_old_cwp_m;
wire tlu_cwp_no_change;
wire [2:0] tlu_cwp_xor;
wire cwp_cmplt_next;
wire [1:0] cwp_cmplt_tid_next;
wire cwp_retry_next;
wire cwp_fastcmplt_m;
wire cwp_fastcmplt_w;
wire cwpccr_update_w;
wire valid_tlu_swap_w;
wire [2:0] tlu_exu_cwp_w;
wire tlu_exu_cwp_retry_w;
wire [3:0] swap_thr;
wire [1:0] swap_tid;
wire [3:0] swap_req_vec;
wire kill_swap_slot_w;
wire [3:0] thr_e;
wire [1:0] swap_slot0_state;
wire [1:0] swap_slot1_state;
wire [1:0] swap_slot2_state;
wire [1:0] swap_slot3_state;
wire [1:0] swap_slot0_state_valid;
wire [1:0] swap_slot1_state_valid;
wire [1:0] swap_slot2_state_valid;
wire [1:0] swap_slot3_state_valid;
wire [1:0] next_slot0_state;
wire [1:0] next_slot1_state;
wire [1:0] next_slot2_state;
wire [1:0] next_slot3_state;
wire [3:0] swap_keep_state;
wire [3:0] swap_next_state;
wire [1:0] swap_state;
wire [3:0] next_swap_thr;
wire [12:0] swap_data;
wire [12:0] tlu_swap_data;
wire [12:0] swap_input_data;
wire [12:0] next_slot0_data;
wire [12:0] next_slot1_data;
wire [12:0] next_slot2_data;
wire [12:0] next_slot3_data;
wire [12:0] swap_slot0_data;
wire [12:0] swap_slot1_data;
wire [12:0] swap_slot2_data;
wire [12:0] swap_slot3_data;
wire new_cwp_sel_swap;
wire [2:0] old_swap_cwp;
wire [2:0] new_swap_cwp;
// wires for cwp register
wire [2:0] cwp_thr0;
wire [2:0] cwp_thr1;
wire [2:0] cwp_thr2;
wire [2:0] cwp_thr3;
wire [2:0] cwp_thr0_next;
wire [2:0] cwp_thr1_next;
wire [2:0] cwp_thr2_next;
wire [2:0] cwp_thr3_next;
wire cwp_wen_thr0_w;
wire cwp_wen_thr1_w;
wire cwp_wen_thr2_w;
wire cwp_wen_thr3_w;
wire [3:0] cwp_wen_tlu_w;
wire [3:0] cwp_wen_spill;
wire [2:0] spill_cwp;
wire [3:0] cwp_wen_l;
wire [2:0] old_cwp_w;
wire spill_next;
wire [1:0] spill_tid_next;
wire spill_other_next;
wire [2:0] spill_wtype_next;
// decode thr_e
assign thr_e[0] = ~tid_e[1] & ~tid_e[0];
assign thr_e[1] = ~tid_e[1] & tid_e[0];
assign thr_e[2] = tid_e[1] & ~tid_e[0];
assign thr_e[3] = tid_e[1] & tid_e[0];
/////////////////////////////////
// CWP output to IRF
/////////////////////////////////
// Output current_d thr on saves or restores
mux2ds #(2) irf_thr_mux(.dout(rml_irf_cwpswap_tid_e[1:0]),
.in0(tid_e[1:0]),
.in1(swap_tid[1:0]),
.sel0(~can_swap),
.sel1(can_swap));
// Output cwp_e for save, restore, flushw
// and swap_cwp from queue for swap restores (default)
// Need to have an incremented cwp for swap of outs
assign old_swap_cwp[2:0] = swap_data[2:0];
assign new_swap_cwp[2:0] = swap_data[5:3];
assign new_cwp_sel_swap = can_swap;
assign new_cwp_e[2:0] = (new_cwp_sel_swap)? new_swap_cwp[2:0]: next_cwp_e[2:0];
assign old_cwp_e[2:0] = (new_cwp_sel_swap)? old_swap_cwp[2:0]: rml_ecl_cwp_e[2:0];
/////////////////////////////////
// CWP register
/////////////////////////////////
assign exu_tlu_cwp0_w[2:0] = cwp_thr0[2:0];
assign exu_tlu_cwp1_w[2:0] = cwp_thr1[2:0];
assign exu_tlu_cwp2_w[2:0] = cwp_thr2[2:0];
assign exu_tlu_cwp3_w[2:0] = cwp_thr3[2:0];
mux4ds #(3) mux_cwp_old_w(.dout(old_cwp_w[2:0]), .sel0(ecl_rml_thr_w[0]),
.sel1(ecl_rml_thr_w[1]), .sel2(ecl_rml_thr_w[2]),
.sel3(ecl_rml_thr_w[3]), .in0(cwp_thr0[2:0]),
.in1(cwp_thr1[2:0]), .in2(cwp_thr2[2:0]),
.in3(cwp_thr3[2:0]));
// Output selection for reg
mux4ds #(3) mux_cwp_out_d(.dout(rml_ecl_cwp_d[2:0]), .sel0(thr_d[0]),
.sel1(thr_d[1]), .sel2(thr_d[2]),
.sel3(thr_d[3]), .in0(cwp_thr0[2:0]),
.in1(cwp_thr1[2:0]), .in2(cwp_thr2[2:0]),
.in3(cwp_thr3[2:0]));
mux4ds #(3) mux_cwp_out_e(.dout(rml_ecl_cwp_e[2:0]), .sel0(thr_e[0]),
.sel1(thr_e[1]), .sel2(thr_e[2]),
.sel3(thr_e[3]), .in0(cwp_thr0[2:0]),
.in1(cwp_thr1[2:0]), .in2(cwp_thr2[2:0]),
.in3(cwp_thr3[2:0]));
mux4ds #(3) mux_cwp_trap(.dout(trap_old_cwp_m[2:0]), .sel0(ecl_rml_thr_m[0]),
.sel1(ecl_rml_thr_m[1]), .sel2(ecl_rml_thr_m[2]),
.sel3(ecl_rml_thr_m[3]), .in0(cwp_thr0[2:0]),
.in1(cwp_thr1[2:0]), .in2(cwp_thr2[2:0]),
.in3(cwp_thr3[2:0]));
//////////////////////////////////////
// Storage of cwp
//////////////////////////////////////
// enable input for each thread
assign cwp_wen_spill[3:0] = swap_thr[3:0] & {4{spill_next}};
assign cwp_wen_thr0_w = ((ecl_rml_thr_w[0] & cwp_wen_w)) & ~cwp_wen_spill[0];
assign cwp_wen_thr1_w = ((ecl_rml_thr_w[1] & cwp_wen_w)) & ~cwp_wen_spill[1];
assign cwp_wen_thr2_w = ((ecl_rml_thr_w[2] & cwp_wen_w)) & ~cwp_wen_spill[2];
assign cwp_wen_thr3_w = ((ecl_rml_thr_w[3] & cwp_wen_w)) & ~cwp_wen_spill[3];
assign cwp_wen_tlu_w[3:0] = ecl_rml_thr_w[3:0] & {4{valid_tlu_swap_w}} & ~cwp_wen_spill &
{~cwp_wen_thr3_w,~cwp_wen_thr2_w,~cwp_wen_thr1_w,~cwp_wen_thr0_w};
assign cwp_wen_l[3:0] = ~(cwp_wen_tlu_w[3:0] | cwp_wen_spill[3:0] |
{cwp_wen_thr3_w,cwp_wen_thr2_w, cwp_wen_thr1_w,cwp_wen_thr0_w});
// oddwin_w is the new value of cwp[0]
assign oddwin_w[3:0] = {cwp_thr3_next[0],cwp_thr2_next[0],cwp_thr1_next[0],cwp_thr0_next[0]};
// mux between new and current value
mux4ds #(3) cwp_next0_mux(.dout(cwp_thr0_next[2:0]),
.in0(cwp_thr0[2:0]),
.in1(next_cwp_w[2:0]),
.in2(tlu_exu_cwp_w[2:0]),
.in3(spill_cwp[2:0]),
.sel0(cwp_wen_l[0]),
.sel1(cwp_wen_thr0_w),
.sel2(cwp_wen_tlu_w[0]),
.sel3(cwp_wen_spill[0]));
mux4ds #(3) cwp_next1_mux(.dout(cwp_thr1_next[2:0]),
.in0(cwp_thr1[2:0]),
.in1(next_cwp_w[2:0]),
.in2(tlu_exu_cwp_w[2:0]),
.in3(spill_cwp[2:0]),
.sel0(cwp_wen_l[1]),
.sel1(cwp_wen_thr1_w),
.sel2(cwp_wen_tlu_w[1]),
.sel3(cwp_wen_spill[1]));
mux4ds #(3) cwp_next2_mux(.dout(cwp_thr2_next[2:0]),
.in0(cwp_thr2[2:0]),
.in1(next_cwp_w[2:0]),
.in2(tlu_exu_cwp_w[2:0]),
.in3(spill_cwp[2:0]),
.sel0(cwp_wen_l[2]),
.sel1(cwp_wen_thr2_w),
.sel2(cwp_wen_tlu_w[2]),
.sel3(cwp_wen_spill[2]));
mux4ds #(3) cwp_next3_mux(.dout(cwp_thr3_next[2:0]),
.in0(cwp_thr3[2:0]),
.in1(next_cwp_w[2:0]),
.in2(tlu_exu_cwp_w[2:0]),
.in3(spill_cwp[2:0]),
.sel0(cwp_wen_l[3]),
.sel1(cwp_wen_thr3_w),
.sel2(cwp_wen_tlu_w[3]),
.sel3(cwp_wen_spill[3]));
// store new value
dff_s #(3) dff_cwp_thr0(.din(cwp_thr0_next[2:0]), .clk(clk), .q(cwp_thr0[2:0]),
.se(se), .si(), .so());
dff_s #(3) dff_cwp_thr1(.din(cwp_thr1_next[2:0]), .clk(clk), .q(cwp_thr1[2:0]),
.se(se), .si(), .so());
dff_s #(3) dff_cwp_thr2(.din(cwp_thr2_next[2:0]), .clk(clk), .q(cwp_thr2[2:0]),
.se(se), .si(), .so());
dff_s #(3) dff_cwp_thr3(.din(cwp_thr3_next[2:0]), .clk(clk), .q(cwp_thr3[2:0]),
.se(se), .si(), .so());
////////////////////////////////////////////
// Queue for full window swaps
////////////////////////////////////////////
// A full swap of the current window requires a 2 cycle operation.
// Each cycle must make sure that
// there isn't another instruction trying to save or restore on top of it.
// The same thread also cannot issue a swap to irf in back-to-back cycles.
// Data is stored as follows:
// 2:0 - CWP
// 5:3 - NewCWP
// 6 - !WRCWP/SPILL
// 7 - Trap return
// 8 - OTHER (for spill trap)
// 11:9- WTYPE (for spill trap)
// 12 - Retry (for trap return)
dff_s full_swap_e2m(.din(full_swap_e), .clk(clk), .q(full_swap_m), .se(se), .si(), .so());
dff_s full_swap_m2w(.din(full_swap_m), .clk(clk), .q(full_swap_w), .se(se), .si(), .so());
assign swap_input_data = {1'b0, rml_ecl_wtype_e[2:0], rml_ecl_other_e, 1'b0, exu_tlu_spill_e,
next_cwp_e[2:0],rml_ecl_cwp_e[2:0]};
assign tlu_swap_data = {tlu_exu_cwp_retry_w, 4'b0, 1'b1, 1'b0, tlu_exu_cwp_w[2:0], old_cwp_w[2:0]};
assign swap_sel_input[3:0] = thr_e[3:0] & {4{full_swap_e}};
assign swap_sel_tlu[3:0] = ecl_rml_thr_w[3:0] & {4{cwpccr_update_w}}
& ~swap_sel_input[3:0];
assign swap_keep_value[3:0] = ~(swap_sel_tlu[3:0] | swap_sel_input[3:0]);
assign swap_keep_state[3:0] = ~(swap_sel_tlu[3:0] | swap_sel_input[3:0]) &
~(swap_thr[3:0] & {4{can_swap}});
assign swap_next_state[3:0] = ~(swap_sel_tlu[3:0] | swap_sel_input[3:0])
& (swap_thr[3:0] & {4{can_swap}});
mux3ds #(13) slot0_data_mux(.dout(next_slot0_data[12:0]),
.in0(swap_input_data[12:0]),
.in1(tlu_swap_data[12:0]),
.in2(swap_slot0_data[12:0]),
.sel0(swap_sel_input[0]),
.sel1(swap_sel_tlu[0]),
.sel2(swap_keep_value[0]));
mux3ds #(13) slot1_data_mux(.dout(next_slot1_data[12:0]),
.in0(swap_input_data[12:0]),
.in1(tlu_swap_data[12:0]),
.in2(swap_slot1_data[12:0]),
.sel0(swap_sel_input[1]),
.sel1(swap_sel_tlu[1]),
.sel2(swap_keep_value[1]));
mux3ds #(13) slot2_data_mux(.dout(next_slot2_data[12:0]),
.in0(swap_input_data[12:0]),
.in1(tlu_swap_data[12:0]),
.in2(swap_slot2_data[12:0]),
.sel0(swap_sel_input[2]),
.sel1(swap_sel_tlu[2]),
.sel2(swap_keep_value[2]));
mux3ds #(13) slot3_data_mux(.dout(next_slot3_data[12:0]),
.in0(swap_input_data[12:0]),
.in1(tlu_swap_data[12:0]),
.in2(swap_slot3_data[12:0]),
.sel0(swap_sel_input[3]),
.sel1(swap_sel_tlu[3]),
.sel2(swap_keep_value[3]));
// Muxes for slot state.
// There are 2 possible states:
// No swap done (01)
// Swap locals/ins done (10)
mux4ds #(2) slot0_state_mux(.dout(next_slot0_state[1:0]),
.in0(2'b10),
.in1({1'b0, valid_tlu_swap_w}),
.in2(swap_slot0_state_valid[1:0]),
.in3({swap_slot0_state_valid[0], 1'b0}),
.sel0(swap_sel_input[0]),
.sel1(swap_sel_tlu[0]),
.sel2(swap_keep_state[0]),
.sel3(swap_next_state[0]));
mux4ds #(2) slot1_state_mux(.dout(next_slot1_state[1:0]),
.in0(2'b10),
.in1({1'b0, valid_tlu_swap_w}),
.in2(swap_slot1_state_valid[1:0]),
.in3({swap_slot1_state_valid[0], 1'b0}),
.sel0(swap_sel_input[1]),
.sel1(swap_sel_tlu[1]),
.sel2(swap_keep_state[1]),
.sel3(swap_next_state[1]));
mux4ds #(2) slot2_state_mux(.dout(next_slot2_state[1:0]),
.in0(2'b10),
.in1({1'b0, valid_tlu_swap_w}),
.in2(swap_slot2_state_valid[1:0]),
.in3({swap_slot2_state_valid[0], 1'b0}),
.sel0(swap_sel_input[2]),
.sel1(swap_sel_tlu[2]),
.sel2(swap_keep_state[2]),
.sel3(swap_next_state[2]));
mux4ds #(2) slot3_state_mux(.dout(next_slot3_state[1:0]),
.in0(2'b10),
.in1({1'b0, valid_tlu_swap_w}),
.in2(swap_slot3_state_valid[1:0]),
.in3({swap_slot3_state_valid[0], 1'b0}),
.sel0(swap_sel_input[3]),
.sel1(swap_sel_tlu[3]),
.sel2(swap_keep_state[3]),
.sel3(swap_next_state[3]));
// The kill is only assessed in w1 because back to back swaps are not allowed.
// This means that a swap cannot start in the M or W stage.
assign kill_swap_slot_w = rml_kill_w & full_swap_w;
assign swap_slot0_state_valid[1:0] = {(swap_slot0_state[1] & ~(kill_swap_slot_w & ecl_rml_thr_w[0])),
(swap_slot0_state[0])};
assign swap_slot1_state_valid[1:0] = {(swap_slot1_state[1] & ~(kill_swap_slot_w & ecl_rml_thr_w[1])),
(swap_slot1_state[0])};
assign swap_slot2_state_valid[1:0] = {(swap_slot2_state[1] & ~(kill_swap_slot_w & ecl_rml_thr_w[2])),
(swap_slot2_state[0])};
assign swap_slot3_state_valid[1:0] = {(swap_slot3_state[1] & ~(kill_swap_slot_w & ecl_rml_thr_w[3])),
(swap_slot3_state[0])};
// Flops for cwp_swap data
dffr_s #(15) slot0_data_dff(.din({next_slot0_state[1:0], next_slot0_data[12:0]}), .clk(clk),
.q({swap_slot0_state[1:0], swap_slot0_data[12:0]}), .rst(reset),
.se(se), .si(), .so());
dffr_s #(15) slot1_data_dff(.din({next_slot1_state[1:0], next_slot1_data[12:0]}), .clk(clk),
.q({swap_slot1_state[1:0], swap_slot1_data[12:0]}), .rst(reset),
.se(se), .si(), .so());
dffr_s #(15) slot2_data_dff(.din({next_slot2_state[1:0], next_slot2_data[12:0]}), .clk(clk),
.q({swap_slot2_state[1:0], swap_slot2_data[12:0]}), .rst(reset),
.se(se), .si(), .so());
dffr_s #(15) slot3_data_dff(.din({next_slot3_state[1:0], next_slot3_data[12:0]}), .clk(clk),
.q({swap_slot3_state[1:0], swap_slot3_data[12:0]}), .rst(reset),
.se(se), .si(), .so());
////////////////////////////
// Control for queue output
// ==========================
// The queue results go into a flop
// so that they can meet timing.
////////////////////////////
assign swap_req_vec[0] = (swap_slot0_state[1] | swap_slot0_state[0]);
assign swap_req_vec[1] = (swap_slot1_state[1] | swap_slot1_state[0]);
assign swap_req_vec[2] = (swap_slot2_state[1] | swap_slot2_state[0]);
assign swap_req_vec[3] = (swap_slot3_state[1] | swap_slot3_state[0]);
sparc_exu_rndrob cwp_output_queue(// Outputs
.grant_vec(next_swap_thr[3:0]),
// Inputs
.clk(clk),
.reset(reset),
.se(se),
.req_vec(swap_req_vec[3:0]),
.advance(can_swap));
dff_s #(4) dff_swap_thr(.din(next_swap_thr[3:0]), .clk(clk), .q(swap_thr[3:0]),
.se(se), .si(), .so());
assign swap_tid[1] = swap_thr[3] | swap_thr[2];
assign swap_tid[0] = swap_thr[3] | swap_thr[1];
// make selects one hot
wire [3:0] swap_sel;
assign swap_sel[0] = ~(swap_thr[1] | swap_thr[2] | swap_thr[3]) | rst_tri_en;
assign swap_sel[3:1] = swap_thr[3:1] & {3{~rst_tri_en}};
mux4ds #(15) cwp_output_mux(.dout({swap_state[1:0], swap_data[12:0]}),
.in0({swap_slot0_state[1:0], swap_slot0_data[12:0]}),
.in1({swap_slot1_state[1:0], swap_slot1_data[12:0]}),
.in2({swap_slot2_state[1:0], swap_slot2_data[12:0]}),
.in3({swap_slot3_state[1:0], swap_slot3_data[12:0]}),
.sel0(swap_sel[0]),
.sel1(swap_sel[1]),
.sel2(swap_sel[2]),
.sel3(swap_sel[3]));
// To prevent back to back swap requests on the same thread, the queue cannot swap
// 2 cycles in a row. Also swaps can't start in M or W to allow flush to be checked
dffr_s can_swap_flop(.din(swapping), .clk(clk), .q(just_swapped), .rst(reset), .se(se), .si(), .so());
assign can_swap = ~(save_e | restore_e | ifu_exu_flushw_e | ecl_rml_cwp_wen_e | just_swapped);
assign swap_locals_ins = can_swap & swap_state[0];
assign swap_outs = can_swap & swap_state[1];
assign swapping = (can_swap & |swap_state[1:0]) | full_swap_e | full_swap_m;
///////////////////////////////////
// Signals for completion of swaps
///////////////////////////////////
assign spill_next = swap_data[6] & ~swap_data[7] & swap_outs;
assign spill_tid_next[1:0] = swap_tid[1:0];
//assign exu_tlu_spill_ttype[8:0] = {3'b010, swap_data[8], swap_data[11:9], 2'b00};
assign spill_other_next = swap_data[8];
assign spill_wtype_next[2:0] = swap_data[11:9];
dff_s #(7) spill_dff(.din({spill_next,spill_tid_next[1:0], spill_other_next, spill_wtype_next[2:0]}),
.q({exu_tlu_spill,exu_tlu_spill_tid[1:0], exu_tlu_spill_other, exu_tlu_spill_wtype[2:0]}),
.clk(clk), .se(se), .si(), .so());
assign spill_cwp[2:0] = swap_data[5:3];
/* -----\/----- EXCLUDED -----\/-----
dff_s #(3) spill_cwp_dff(.din(swap_data[5:3]), .clk(clk), .q(spill_cwp[2:0]),
.se(se), .si(), .so());
-----/\----- EXCLUDED -----/\----- */
assign swap_done_next_cycle[3] = (swap_outs & ~swap_data[6] & ~swap_data[7] &
swap_tid[1] & swap_tid[0]);
assign swap_done_next_cycle[2] = (swap_outs & ~swap_data[6] & ~swap_data[7] &
swap_tid[1] & ~swap_tid[0]);
assign swap_done_next_cycle[1] = (swap_outs & ~swap_data[6] & ~swap_data[7] &
~swap_tid[1] & swap_tid[0]);
assign swap_done_next_cycle[0] = (swap_outs & ~swap_data[6] & ~swap_data[7] &
~swap_tid[1] & ~swap_tid[0]);
dff_s #(4) swap_done_dff(.din(swap_done_next_cycle[3:0]), .clk(clk),
.q(rml_ecl_swap_done[3:0]), .se(se), .si(), .so());
dff_s #(4) cwp_cmplt_dff(.din({cwp_cmplt_next, cwp_cmplt_tid_next[1:0], cwp_retry_next}),
.q({exu_tlu_cwp_cmplt,exu_tlu_cwp_cmplt_tid[1:0], exu_tlu_cwp_retry}),
.clk(clk), .si(), .so(), .se(se));
assign cwp_cmplt_next = swap_outs & swap_data[7];
assign cwp_cmplt_tid_next[1:0] = swap_tid[1:0];
assign cwp_retry_next = swap_data[12];
assign tlu_cwp_xor[2:0] = trap_old_cwp_m[2:0] ^ tlu_exu_cwp_m[2:0];
assign tlu_cwp_no_change = ~(tlu_cwp_xor[2] | tlu_cwp_xor[1] | tlu_cwp_xor[0]);
assign cwp_fastcmplt_m = tlu_exu_cwpccr_update_m & tlu_cwp_no_change;
dff_s fastcmplt_dff(.din(cwp_fastcmplt_m), .clk(clk),
.q(cwp_fastcmplt_w), .se(se), .si(), .so());
///////////////////////////////////////////////////////////
// Pipe along tlu_exu_done/retry so inst_vld can be caught
///////////////////////////////////////////////////////////
dff_s #(5) tlu_data_dff(.q({cwpccr_update_w,tlu_exu_cwp_w[2:0],tlu_exu_cwp_retry_w}),
.din({tlu_exu_cwpccr_update_m,tlu_exu_cwp_m[2:0],tlu_exu_cwp_retry_m}),
.clk(clk), .se(se), .si(), .so());
assign valid_tlu_swap_w = cwpccr_update_w & ~rml_kill_w & ~cwp_fastcmplt_w;
endmodule // sparc_exu_rml_cwp
|
`timescale 1 ns / 1 ps
module PWM_Analyzer_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input wire pwm,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
wire [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
wire [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
wire [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
// slv_reg0 <= 0; /**** Assign to these registers below in user logic ****/
// slv_reg1 <= 0;
// slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0 /**** Assigned to below in user logic ****/
// slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1 /**** Assigned to below in user logic ****/
// slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2 /**** Assigned to below in user logic ****/
// slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
// slv_reg0 <= slv_reg0;
// slv_reg1 <= slv_reg1;
// slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
reg pwm_delay, pwm_clean;
always @ (posedge S_AXI_ACLK) begin
pwm_delay <= pwm;
pwm_clean <= pwm_delay;
end
assign slv_reg0[31] = 1'b0;
assign slv_reg1[31] = 1'b0;
wire reset;
assign reset = ~S_AXI_ARESETN;
pulseLength pulse_length (
.clk(S_AXI_ACLK),
.reset(reset),
.pw_low(slv_reg0[30:0]),
.pw_high(slv_reg1[30:0]),
.pwm_per(slv_reg2),
.pwm(pwm_clean)
);
// User logic ends
endmodule
|
module top(
//SMIMS SDK signals
input SDK_CLK, //48MHz
input SDK_RSTN,
input [7:0] SDK_FIFO_CH,
output SDK_FIFO_RD,
input [15:0] SDK_FIFO_DI,
input SDK_FIFO_Empty,
input SDK_FIFO_AlmostEmpty,
output SDK_FIFO_WR,
output [15:0] SDK_FIFO_DO,
input SDK_FIFO_Full,
input SDK_FIFO_AlmostFull,
output SDK_Interrupt,
//UART signals, but not be used now
input core0_UART_RXD,
output core0_UART_TXD,
//GPIO signals
output [7:0] GPIO_o, //mapping to gpio pin on the board
output [7:0] LED, //mapping to LED on the board
input [1:0] GPIO_i //mapping to button on the board
);
wire [5:0] state;
assign LED[0] = GPIO_o[0];
assign LED[1] = GPIO_o[1];
assign LED[2] = GPIO_o[2];
assign LED[3] = GPIO_o[3];
assign LED[4] = GPIO_o[4];
assign LED[5] = GPIO_o[5];
assign LED[6] = GPIO_o[6];
assign LED[7] = GPIO_o[7];
//assign LED = {3'b0, state}; //Using LED to debug
//UART signals
wire core0_tf_push_o;
wire [7:0] core0_print_data_o;
//openRISC signas
wire [15:0] core_id;
wire [7:0] openRISC_RSTN;
wire [7:0] openRISC_STALL;
wire [7:0] openRISC_ram_we;
wire [15:0] openRISC_ram_addr;
wire [31:0] openRISC_data_o;
reg [31:0] openRISC_data_i,_openRISC_data_i;
wire [31:0] openRISC_pc_0;
wire [31:0] openRISC_pc_1;
wire [31:0] openRISC_pc_2;
wire [31:0] openRISC_pc_3;
wire [31:0] openRISC_pc_4;
wire [31:0] openRISC_pc_5;
wire [31:0] openRISC_pc_6;
wire [31:0] openRISC_pc_7;
wire [31:0] openRISC_RAM_DATA_O_0, openRISC_RAM_DATA_O_1, openRISC_RAM_DATA_O_2, openRISC_RAM_DATA_O_3;
wire [31:0] openRISC_RAM_DATA_O_4, openRISC_RAM_DATA_O_5, openRISC_RAM_DATA_O_6, openRISC_RAM_DATA_O_7;
always@(posedge SDK_CLK or negedge SDK_RSTN)
begin
if(~SDK_RSTN)
openRISC_data_i <= 32'd0;
else
openRISC_data_i <= _openRISC_data_i;
end
always@* begin
case(core_id[3:0])
4'd0: _openRISC_data_i = openRISC_RAM_DATA_O_0;
4'd1: _openRISC_data_i = openRISC_RAM_DATA_O_1;
4'd2: _openRISC_data_i = openRISC_RAM_DATA_O_2;
4'd3: _openRISC_data_i = openRISC_RAM_DATA_O_3;
4'd4: _openRISC_data_i = openRISC_RAM_DATA_O_4;
4'd5: _openRISC_data_i = openRISC_RAM_DATA_O_5;
4'd6: _openRISC_data_i = openRISC_RAM_DATA_O_6;
4'd7: _openRISC_data_i = openRISC_RAM_DATA_O_7;
default: _openRISC_data_i = openRISC_RAM_DATA_O_0;
endcase
end
OpenRISC_Interface OR_Interface0(
.SDK_CLK(SDK_CLK), //This clk must be the same with core0's clk. (48MHz)
.SDK_RSTN(SDK_RSTN),
//UART data signals
.core0_tf_push_i(core0_tf_push_o),
.core0_print_data_i(core0_print_data_o),
//SMIMS SDK signals
.SDK_FIFO_RD(SDK_FIFO_RD),
.SDK_FIFO_DI(SDK_FIFO_DI),
.SDK_FIFO_Empty(SDK_FIFO_Empty),
.SDK_FIFO_WR(SDK_FIFO_WR),
.SDK_FIFO_DO(SDK_FIFO_DO),
.SDK_FIFO_Full(SDK_FIFO_Full),
.SDK_Interrupt(SDK_Interrupt),
//openRISC signals
.openRISC_RSTN(openRISC_RSTN),
.openRISC_STALL(openRISC_STALL),
.openRISC_ram_we(openRISC_ram_we),
.openRISC_ram_addr(openRISC_ram_addr),
.openRISC_data_o(openRISC_data_o),
.openRISC_data_i(openRISC_data_i),
.core_id(core_id),
//each core's pc
.openRISC_pc_0(openRISC_pc_0),
.openRISC_pc_1(openRISC_pc_1),
.openRISC_pc_2(openRISC_pc_2),
.openRISC_pc_3(openRISC_pc_3),
.openRISC_pc_4(openRISC_pc_4),
.openRISC_pc_5(openRISC_pc_5),
.openRISC_pc_6(openRISC_pc_6),
.openRISC_pc_7(openRISC_pc_7),
//For DEBUG
.state_o(state)
);
/** core 0 **/
or1200_sopc or1200_sopc_inst_0
(
.CLOCK_48(SDK_CLK),
.rst_n(openRISC_RSTN[0]),
.openRISC_STALL(openRISC_STALL[0]),
.openRISC_pc(openRISC_pc_0),
//For ram top module
.RAM_WE(openRISC_ram_we[0]),
.RAM_ADDR(openRISC_ram_addr),
.RAM_DATA_I(openRISC_data_o),
.RAM_DATA_O(openRISC_RAM_DATA_O_0),
.UART_TXD(core0_UART_TXD),
.UART_RXD(core0_UART_RXD),
//UART data signals
.print_data_o(core0_print_data_o),
.tf_push_o(core0_tf_push_o),
//GPIO
.GPIO_o(GPIO_o),
.GPIO_i(GPIO_i)
);
//The following is for multi-core version.
//But haven't implemented.
/** core 1 **/
// or1200_sopc or1200_sopc_inst_1
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[1]),
//
//
// .openRISC_STALL(openRISC_STALL[1]),
// .openRISC_pc(openRISC_pc_1),
// //For ram top module
// .RAM_WE(openRISC_ram_we[1]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_1)
// );
//
/** core 2 **/
//
// or1200_sopc or1200_sopc_inst_2
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[2]),
//
// .openRISC_STALL(openRISC_STALL[2]),
// .openRISC_pc(openRISC_pc_2),
// //For ram top module
// .RAM_WE(openRISC_ram_we[2]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_2)
// );
/** core 3 **/
// or1200_sopc or1200_sopc_inst_3
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[3]),
//
// .openRISC_STALL(openRISC_STALL[3]),
// .openRISC_pc(openRISC_pc_3),
// //For ram top module
// .RAM_WE(openRISC_ram_we[3]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_3)
// );
//
///** core 4 **/
// or1200_sopc or1200_sopc_inst_4
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[4]),
//
// .openRISC_STALL(openRISC_STALL[4]),
// .openRISC_pc(openRISC_pc_4),
// //For ram top module
// .RAM_WE(openRISC_ram_we[4]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_4)
// );
//
///** core 5 **/
// or1200_sopc or1200_sopc_inst_5
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[5]),
//
// .openRISC_STALL(openRISC_STALL[5]),
// .openRISC_pc(openRISC_pc_5),
// //For ram top module
// .RAM_WE(openRISC_ram_we[5]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_5)
// );
//
///** core 6 **/
// or1200_sopc or1200_sopc_inst_6
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[6]),
//
// .openRISC_STALL(openRISC_STALL[6]),
// .openRISC_pc(openRISC_pc_6),
// //For ram top module
// .RAM_WE(openRISC_ram_we[6]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_6)
// );
//
// /** core 7 **/
// or1200_sopc or1200_sopc_inst_7
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[7]),
//
// .openRISC_STALL(openRISC_STALL[7]),
// .openRISC_pc(openRISC_pc_7),
// //For ram top module
// .RAM_WE(openRISC_ram_we[7]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_7)
// );
endmodule
|
// megafunction wizard: %LPM_DIVIDE%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: divider.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module divider (
clock,
denom,
numer,
quotient,
remain);
input clock;
input [4:0] denom;
input [10:0] numer;
output [10:0] quotient;
output [4:0] remain;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "FALSE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "5"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "11"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 5 0 INPUT NODEFVAL "denom[4..0]"
// Retrieval info: USED_PORT: numer 0 0 11 0 INPUT NODEFVAL "numer[10..0]"
// Retrieval info: USED_PORT: quotient 0 0 11 0 OUTPUT NODEFVAL "quotient[10..0]"
// Retrieval info: USED_PORT: remain 0 0 5 0 OUTPUT NODEFVAL "remain[4..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 5 0 denom 0 0 5 0
// Retrieval info: CONNECT: @numer 0 0 11 0 numer 0 0 11 0
// Retrieval info: CONNECT: quotient 0 0 11 0 @quotient 0 0 11 0
// Retrieval info: CONNECT: remain 0 0 5 0 @remain 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL divider.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL divider.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL divider.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL divider.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL divider_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL divider_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_TB_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_TB_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlygate4sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__dlygate4sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_V |
module spi_engine_interconnect (
input clk,
input resetn,
output m_cmd_valid,
input m_cmd_ready,
output [15:0] m_cmd_data,
output m_sdo_valid,
input m_sdo_ready,
output [7:0] m_sdo_data,
input m_sdi_valid,
output m_sdi_ready,
input [7:0] m_sdi_data,
input m_sync_valid,
output m_sync_ready,
input [7:0] m_sync,
input s0_cmd_valid,
output s0_cmd_ready,
input [15:0] s0_cmd_data,
input s0_sdo_valid,
output s0_sdo_ready,
input [7:0] s0_sdo_data,
output s0_sdi_valid,
input s0_sdi_ready,
output [7:0] s0_sdi_data,
output s0_sync_valid,
input s0_sync_ready,
output [7:0] s0_sync,
input s1_cmd_valid,
output s1_cmd_ready,
input [15:0] s1_cmd_data,
input s1_sdo_valid,
output s1_sdo_ready,
input [7:0] s1_sdo_data,
output s1_sdi_valid,
input s1_sdi_ready,
output [7:0] s1_sdi_data,
output s1_sync_valid,
input s1_sync_ready,
output [7:0] s1_sync
);
reg s_active = 1'b0;
reg idle = 1'b1;
`define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
assign m_cmd_data = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
assign m_cmd_valid = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
assign m_sdo_data = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
assign m_sdo_valid = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
assign s0_sdi_data = m_sdi_data;
assign s1_sdi_data = m_sdi_data;
assign m_sdi_ready = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
assign s0_sync = m_sync;
assign s1_sync = m_sync;
assign m_sync_ready = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
always @(posedge clk) begin
if (idle == 1'b1) begin
if (s0_cmd_valid)
s_active <= 1'b0;
else if (s1_cmd_valid)
s_active <= 1'b1;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
idle = 1'b1;
end else begin
if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
idle <= 1'b1;
end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
idle <= 1'b0;
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Memory controller interface
// File : de3d_tc_mc_sigs.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Because other resources in the drawing engine (Texel Cache) can be
// interleaving requests with mine, I must make sure that I know which
// signals are mine
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
// U_HBI hbi_top Host interface (PCI)
// U_VGA vga_top IBM(TM) Compatible VGA core
// U_DE de_top Drawing engine
// U_DLP dlp_top Display List Processor
// U_DDR3 DDR3 DDR3 Memory interface
// u_crt crt_top Display interface
// u_ramdac ramdac Digital DAC
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
/************************************************************************/
/************************************************************************/
module de3d_tc_mc_sigs
(
input de_clk, // Drawing engine clock
input de_rstn, // Drawing engine reset
input ld_push_count, // Load push count from tc_sm.
input [3:0] push_count, // push count from tc_sm.
input mclock, // Memory controller clock
input tex_push_en, // push signal to load data to TC
input [3:0] tc_op_store, // Current tc op.
input [8:0] ul_store_x, // Upper left texel address
input [8:0] ul_store_y, // Upper left texel address
input [8:0] ll_store_x, // Lower left texel address
input [8:0] ll_store_y, // Lower left texel address
input [8:0] ur_store_x, // Upper right texel address
input [8:0] ur_store_y, // Upper right texel address
input [8:0] lr_store_x, // Lower right texel address
input [8:0] lr_store_y, // Lower right texel address
input [2:0] bpt, // bpt
input [3:0] set_read, // LRU
output reg done, // Done sent back to tc_sm.
output reg ram_sel, // RAM select for first read.
output reg [7:0] ram_addr // Address for loading TC RAM.
);
wire ul_lru_read = set_read[3];
wire ll_lru_read = set_read[2];
wire ur_lru_read = set_read[1];
wire lr_lru_read = set_read[0];
reg ld_push_count_t;
reg ld_push_count_d;
reg ld_push_count_mc;
reg mc_ld_push_count;
reg [3:0] de_push_count;
reg [3:0] mc_push_count;
reg done_un;
reg done_de;
reg [1:0] mc_current;
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn) de_push_count <= 4'b0000;
else if(ld_push_count) de_push_count <= push_count;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)ld_push_count_t <= 0;
else if(ld_push_count) ld_push_count_t <= ~ld_push_count_t;
end
/*********************************************************/
/* Syncronize the load push counter to the memory clock. */
always @(posedge mclock) ld_push_count_d <= ld_push_count_t;
always @(posedge mclock) ld_push_count_mc <= ld_push_count_d;
always @* mc_ld_push_count = ld_push_count_mc ^ ld_push_count_d;
/****************************************************/
/* Syncronize the done to the drawing engine clock. */
always @(posedge de_clk) done_un <= mc_push_count[3];
always @(posedge de_clk) done_de <= done_un;
always @* done = ~done_de & done_un;
always @(posedge mclock or negedge de_rstn)
begin
if(!de_rstn)mc_push_count <= 4'b0000;
else if(mc_ld_push_count)mc_push_count <= de_push_count;
else if(tex_push_en)mc_push_count <= mc_push_count + 4'b0001;
end
always @* begin
casex({tc_op_store, mc_push_count[2:1]}) /* synopsys parallel_case */
// Missed one of four texels, load one cache line.
6'b1000_xx: mc_current = 2'b00; // UL.
6'b0100_xx: mc_current = 2'b01; // LL.
6'b0010_xx: mc_current = 2'b10; // UR.
6'b0001_xx: mc_current = 2'b11; // LR.
// Missed two of four texels, load two cache lines.
6'b0011_10: mc_current = 2'b10; // UR.
6'b0011_11: mc_current = 2'b11; // LR.
6'b0101_10: mc_current = 2'b01; // LL.
6'b0101_11: mc_current = 2'b11; // LR.
6'b0110_10: mc_current = 2'b01; // LL.
6'b0110_11: mc_current = 2'b10; // UR.
6'b1001_10: mc_current = 2'b00; // UL.
6'b1001_11: mc_current = 2'b11; // LR.
6'b1010_10: mc_current = 2'b00; // UL.
6'b1010_11: mc_current = 2'b10; // UR.
6'b1100_10: mc_current = 2'b00; // UL.
6'b1100_11: mc_current = 2'b01; // LL.
// Missed three of four texels, load three cache lines.
6'b0111_01: mc_current = 2'b01; // LL.
6'b0111_10: mc_current = 2'b10; // UR.
6'b0111_11: mc_current = 2'b11; // LR.
6'b1011_01: mc_current = 2'b00; // UL.
6'b1011_10: mc_current = 2'b10; // UR.
6'b1011_11: mc_current = 2'b11; // LR.
6'b1101_01: mc_current = 2'b00; // UL.
6'b1101_10: mc_current = 2'b01; // LL.
6'b1101_11: mc_current = 2'b11; // LR.
6'b1110_01: mc_current = 2'b00; // UL.
6'b1110_10: mc_current = 2'b01; // LL.
6'b1110_11: mc_current = 2'b10; // UR.
// Missed four of four texels, load four cache lines.
6'b1111_00: mc_current = 2'b00; // UL.
6'b1111_01: mc_current = 2'b01; // LL.
6'b1111_10: mc_current = 2'b10; // UR.
6'b1111_11: mc_current = 2'b11; // LR.
default: mc_current = 2'b00; // UL.
endcase
end
always @* begin
case (mc_current) /* synopsys full_case parallel_case */
2'b00: // Upper left.
begin
ram_sel = ul_store_y[0];
case (bpt) /* synopsys parallel_case */
3: begin // 8 bpt.
ram_addr = {ul_lru_read,ul_store_y[5:0],ul_store_x[5]};
// ram_sel = (ul_store_x[4] ^ ul_store_y[0]);
end
5: begin // 32 bpt.
ram_addr = {ul_lru_read,ul_store_y[3:0],ul_store_x[5:3]};
// ram_sel = (ul_store_x[2] ^ ul_store_y[0]);
end
default: begin// 16 bpt.
ram_addr = {ul_lru_read,ul_store_y[4:0],ul_store_x[5:4]};
// ram_sel = (ul_store_x[3] ^ ul_store_y[0]);
end
endcase
end
2'b01: // Lower left.
begin
ram_sel = ll_store_y[0];
case (bpt) /* synopsys parallel_case */
3: begin // 8 bpt.
ram_addr = {ll_lru_read,ll_store_y[5:0],ll_store_x[5]};
// ram_sel = (ll_store_x[4] ^ ll_store_y[0]);
end
5: begin // 32 bpt.
ram_addr = {ll_lru_read,ll_store_y[3:0],ul_store_x[5:3]};
// ram_sel = (ll_store_x[2] ^ ll_store_y[0]);
end
default: begin // 16 bpt.
ram_addr = {ll_lru_read,ll_store_y[4:0],ll_store_x[5:4]};
// ram_sel = (ll_store_x[3] ^ ll_store_y[0]);
end
endcase
end
2'b10: // Upper right.
begin
ram_sel = ur_store_y[0];
case (bpt) /* synopsys parallel_case */
3: begin // 8 bpt.
ram_addr = {ur_lru_read,ur_store_y[5:0],ur_store_x[5]};
// ram_sel = (ur_store_x[4] ^ ur_store_y[0]);
end
5: begin // 32 bpt.
ram_addr = {ur_lru_read,ur_store_y[3:0],ur_store_x[5:3]};
// ram_sel = (ur_store_x[2] ^ ur_store_y[0]);
end
default: begin // 16 bpt.
ram_addr = {ur_lru_read,ur_store_y[4:0],ur_store_x[5:4]};
// ram_sel = (ur_store_x[3] ^ ur_store_y[0]);
end
endcase
end
2'b11: // Lower right.
begin
ram_sel = lr_store_y[0];
case (bpt) /* synopsys parallel_case */
3: begin // 8 bpt.
ram_addr = {lr_lru_read,lr_store_y[5:0],lr_store_x[5]};
// ram_sel = (lr_store_x[4] ^ lr_store_y[0]);
end
5: begin // 32 bpt.
ram_addr = {lr_lru_read,lr_store_y[3:0],lr_store_x[5:3]};
// ram_sel = (lr_store_x[2] ^ lr_store_y[0]);
end
default: begin // 16 bpt.
ram_addr = {lr_lru_read,lr_store_y[4:0],lr_store_x[5:4]};
// ram_sel = (lr_store_x[3] ^ lr_store_y[0]);
end
endcase
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A222O_PP_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_PP_SYMBOL_V
|
(*|
.. raw:: html
<link rel="stylesheet" href="tutorial.css" type="text/css" />
.. coq:: none
|*)
(****************************************************************************)
(* Copyright 2020 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
(*|
========
Tutorial
========
Welcome! This is a quick primer for designing circuits with the Cava DSL. This
tutorial will not explain Coq syntax in depth, but will use the same few
patterns throughout; you shouldn't need to be a Coq expert to follow
along. We'll walk through a few small examples end-to-end, showing you how to
define, simulate, and generate netlists for circuits in Cava.
This page (thanks to the Alectryon_ system) allows you to see the Coq output for
each line that has output. Try hovering over the following line (if on mobile,
tap the line):
|*)
Compute (1 + 2).
(*|
See the banner at the top of the page for instructions on how to navigate the proofs.
.. contents:: Table of Contents
:depth: 2
Setup
=====
If you are viewing this tutorial on the web and just trying to get a general
idea of how Cava works, skip to the next section. If you are trying to write
your own circuits or step through this tutorial locally, here are the
quick-start instructions for installing Cava::
$ git clone https://github.com/project-oak/silveroak.git
$ cd silveroak
$ make update-third_party
$ make -j4 cava-coq
You can now make the Cava libraries visible to your project by adding the
following lines to your project's ``_CoqProject`` file::
-R path/to/silveroak/cava/Cava Cava
-R path/to/silveroak/third_party/coq-ext-lib/theories ExtLib
-R path/to/silveroak/third_party/bedrock2/deps/coqutil/src/coqutil coqutil
If you don't have an existing project, you can set up a minimal one as follows:
1. Create a new directory
2. Create a file called ``_CoqProject`` in the new directory containing the
three lines above, with ``path/to/silveroak`` replaced with the path to
your clone of ``silveroak``
3. Create a new file with a ``.v`` extension and open it with your favorite
Coq IDE option (``coqide``, Emacs's Proof General, Vim's ``coqtail``, or VS
Code, among others). The ``_CoqProject`` file should be detected
automatically; try writing the imports below into the ``.v`` file, and step
through them to check that everything's working.
The following lines import everything you need to *define* and *simulate* circuits,
as well as some convenience notations:
|*)
Require Import Cava.Cava.
Import Circuit.Notations.
(*|
If you also want to do *proofs* about circuits, you'll need this import also:
|*)
Require Import Cava.CavaProperties.
(*|
Example 1 : Inverter
====================
To start, let's define a 1-bit inverter.
|*)
Definition inverter
{signal : SignalType -> Type}
{semantics : Cava signal}
: Circuit (signal Bit) (signal Bit) :=
Comb inv.
(*|
A few things to notice here:
* ``SignalType`` is Cava's type system. The inverter is parameterized over
``signal``, which converts ``SignalType``\ s to Coq types. ``Bit`` is one
example of a ``SignalType``; we'll see more examples later on.
* ``Comb`` is short for "combinational"; our inverter has no loops, registers,
or timing requirements, so it is a purely combinational circuit.
* The inverter is also paramterized over ``semantics``, an instance of the
typeclass ``Cava``. This instance provides implementations of circuit
primitives, such as 1-bit logic gates. One primitive gate is a 1-bit inverter
``inv``, so our inverter is just a simple invocation of the primitive.
Normally, we'd write circuit definitions a little more concisely by writing them
inside a ``Section`` that contains ``signal`` and ``semantics`` as context
variables, like this:
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
Definition inverter_concise : Circuit (signal Bit) (signal Bit)
:= Comb inv.
(*|
For the rest of the circuit definitions in this tutorial, you can assume that
we're inside the section and that every definition is parameterized over the
``signal`` and ``semantics`` context variables.
Back to our inverter. Let's take a closer look at the ``inv`` primitive.
|*)
Check inv.
(*|
You can see in the type signature ``signal Bit -> cava (signal Bit)`` that
``inv`` is defined as a pure Coq function in terms of a monad called
``cava``. The ``cava`` monad, like ``inv``, is provided by ``semantics``. The
monad is used to capture sharing; it's semantically different in Cava to write::
x <- inv zero ;;
y <- inv zero ;;
xor2 x y
than it is to write::
x <- inv zero ;;
xor2 x x
Both expressions have the same meaning, and if we were using Gallina ``let``
binders there would be no difference. But the generated circuit can use two
wires for the first definition, and fork the same wire in the second. As circuit
diagrams, this is the difference between::
+-----+ +-----+
0 -----| inv |------| |
+-----+ | xor |----- out
+-----+ | |
0 -----| inv |------| |
+-----+ +-----+
and::
+-----+
+---| |
| | xor |---- out
+-----+ | | |
0 -----| inv |----+---| |
+-----+ +-----+
This difference isn't significant in determining what the value of ``out`` will
be, but it can be very useful when trying to exercise fine-grained control over
circuit layout and area! At a first approximation, you can think of a monadic
bind (``_ <- _ ;; ...``) as *naming a wire* in the circuit graph.
If the monad notations are unfamiliar, the reference_ has more information on
those.
We could have represented sharing by describing circuit graphs with a list of
nodes and edges. However, this is essentially the "machine code" of structural
hardware descriptions, and is far too tedious a representation for humans to
work with. The monadic-function abstraction allows human engineers to think
about the functional behavior and composition of circuits at a more intuitive
level.
Parameterizing over the ``cava`` monad and primitive implementations allows us
to use different instances of ``Cava`` to interpret the same circuit definition
in different ways. One ``Cava`` instance generates netlists by adding and
connecting wires in the background using a state monad. For circuit simulations
and proofs of functional correctness, on the other hand, we don't care about
sharing at all; these use no-op identity monad that acts the same as a ``let``
binder.
Let's use our ``inverter`` definition to see these two interpretations in
action.
.. coq:: none
|*)
End WithCava. (* end the section so we can plug in signal and semantics *)
(*|
First, let's generate a netlist. We need to define an interface that describes
the circuit's input and output ports and behavior relative to the (global) clock
and reset signals. Then we can compute a netlist (type ``CavaState``), which
describes the full layout of the circuit in a way that can be easily translated
to SystemVerilog (we do this using an unverified but small Haskell program).
|*)
(* netlist-generating semantics *)
Existing Instance CavaCombinationalNet.
Definition inverter_interface
:= sequentialInterface "inverter_interface"
"clk" PositiveEdge "rst" PositiveEdge
[mkPort "i" Bit]
[mkPort "o" Bit].
Compute makeCircuitNetlist inverter_interface inverter.
(* A closer look at the circuit body *)
Compute (makeCircuitNetlist inverter_interface inverter).(module).
(*|
You may notice that we're using something called ``sequentialInterface`` here,
and referring to clock and reset signals, even though our inverter is a purely
combinational circuit. We introduce timing in the netlist interface here in
order to drive the circuit with multiple inputs over time, and to plug it in as
a subcomponent of circuits that are not combinational.
Now, let's simulate the circuit, which can be useful for testing and proving
functional correctness. Here, we use the identity-monad interpretation. The
``signal`` for this ``Cava`` instance is ``combType``, which interprets a
``Bit`` simply as a Coq ``bool``. If we provide the three inputs
``[true; false; true]`` to the circuit simulation function ``simulate``, we'll
get ``[false; true; false]``:
|*)
(* identity-monad semantics *)
Existing Instance CombinationalSemantics.
Compute simulate inverter [true; false; true].
Compute simulate inverter [true; false; true; true; true; false].
(*|
In a later example_, we will demonstrate how to additionally validate the
SystemVerilog output by creating a test and checking that a Verilog simulation
or even a running FPGA implementation of the circuit agrees with the Coq
simulation above.
We can use the simulation to write proofs about the circuit. For instance, we
can prove that ``inverter`` obeys a natural Coq specification:
|*)
Lemma inverter_correct (input : list bool) :
simulate inverter input = map negb input.
Proof.
(* inline the circuit definition *)
cbv [inverter].
(* simplify simulate to create an expression in terms of Coq lists *)
autorewrite with push_simulate.
(* assert that the two List.map functions are equivalent *)
apply map_ext. intros.
(* inline the inv primitive (fun x => ret (negb x)) *)
cbn [inv CombinationalSemantics].
(* simplify the identity monad expressions *)
simpl_ident.
reflexivity.
Qed.
(*|
We can even prove that composing two inverters is the same as doing
nothing. Here, ``>==>`` is circuit composition (a Kleisli arrow). The proof
structure is pretty similar.
|*)
Lemma inverter_idempotent (input : list bool) :
simulate (inverter >==> inverter) input = input.
Proof.
cbv [inverter].
autorewrite with push_simulate.
rewrite map_map.
apply List.map_id_ext. intros.
cbn [inv CombinationalSemantics].
simpl_ident.
apply Bool.negb_involutive.
Qed.
(*|
A note about reading Coq proofs: in general, it's more important to understand
the lemma statement (the part before ``Proof``) than it is to understand the
proof body. The lemma statement shows what is being proven, and the proof body
contains an "argument" to Coq that the statement is true.
To summarize, there are three things you can do with Cava circuits:
1. Define them (parameterized over an abstract ``Cava`` instance)
2. Generate netlists for them using the ``CavaCombinationalNet`` instance and
the ``makeCircuitNetlist`` function. These netlists can then be translated into
SystemVerilog.
3. Simulate them using ``simulate``, and prove things about the simulations, by
plugging in the ``CombinationalSemantics`` instance.
In the following examples, we'll use this exact same three-part pattern to
explore more complex circuits.
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
Example 2 : Byte xor
====================
Our next example is a circuit that xors two bytes:
|*)
Definition xor_byte :
Circuit (signal (Vec Bit 8) * signal (Vec Bit 8))
(signal (Vec Bit 8)) :=
Comb (Vec.map2 xor2).
(*|
This circuit maps a 1-bit xor (``xor2``) over the two input vectors. ``xor2`` is
one of the primitives provided by the ``Cava`` instance, like ``inv``. Once
again, this is a combinational circuit, so we define it by wrapping a monadic
function with ``Comb``.
The ``Vec`` here is another ``SignalType``, with a slightly more complicated
construction than ``Bit``. A ``Vec Bit 8`` is a vector of 8 bits: a
byte. Vectors can be formed from any other ``SignalType``, including other
vectors; ``Vec (Vec (Vec Bit 8) 4) 2)`` is a valid construction representing a
two-dimensional array of bytes (equivalently, a three-dimensional array of
bits).
The ``Vec.map2`` definition is from Cava's vector library. It's important not to
confuse ``Vec``, the ``SignalType`` in Cava's type system, with ``Vector.t``,
Coq's standard library vector type. In simulation, ``Vec`` is translated into
``Vector.t``, so you may see both in the codebase. You can also convert back and
forth between ``Vec`` and ``Vector.t`` using the Cava primitives ``packV`` and
``unpackV``. However, Cava's vector library mirrors most of the definitions
available for Coq standard library vectors, so it's usually best to use those
definitions instead: use ``Vec.map2`` instead of ``unpackV``, ``Vector.map2``,
and ``packV``.
To see more definitions from Cava's core library, try taking a look at the Cava
reference_, which documents its contents.
.. coq:: none
|*)
End WithCava.
Local Open Scope vector_scope.
(*|
To generate a netlist for this circuit, we use mostly the same procedure as for
the inverter, except that we change the input and output port types to match the
circuit's type signature.
|*)
Definition xor_byte_interface
:= sequentialInterface "xor_byte_interface"
"clk" PositiveEdge "rst" PositiveEdge
[mkPort "v1" (Vec Bit 8); mkPort "v2" (Vec Bit 8)]
[mkPort "o" (Vec Bit 8)].
Compute (makeCircuitNetlist xor_byte_interface xor_byte).(module).
(*|
Tuples in the input or output types become lists of ports for the netlist
interface, so ``signal (Vec Bit 8) * signal (Vec Bit 8)`` becomes ``[mkPort "v1"
(Vec Bit 8); mkPort "v2" (Vec Bit 8)]``. The names of the ports ("v1", "v2", and
"o") are just for readability and potentially for reference by other netlists;
they can be named however you prefer.
We can also, as before, simulate the circuit.
|*)
Compute
simulate xor_byte
[([true; true; true; false; false; false; false; false],
[false; true; false; true; false; false; false; false])].
(*|
Literal bit vectors are not especially readable, though; it's not immediately
clear that this simulation is 7 xor 10 = 13. For simulations with bitvectors,
it's often clearer to use natural-number-to-bitvector conversions from the Coq
standard library :
|*)
Compute map Bv2N
(simulate xor_byte [(N2Bv_sized 8 7, N2Bv_sized 8 10)]).
(*|
Finally, we can prove that the circuit is correct. In this case, we prove that
the circuit's behavior matches the ``BVxor`` definition from the standard
library, specialized to bit-vectors of length 8.
|*)
Lemma xor_byte_correct (i : list (Vector.t bool 8 * Vector.t bool 8)) :
simulate xor_byte i = map (fun '(v1,v2) => BVxor 8 v1 v2) i.
Proof.
cbv [xor_byte]. autorewrite with push_simulate.
apply map_ext; intros. destruct_pair_let.
cbv [BVxor]. simpl_ident.
apply Vector.map2_ext. reflexivity.
Qed.
(*|
Again, no need to focus too much on the body of the proof here; understanding
the lemma statement is the most important part. However, one interesting thing
to note is that the proof is not computational; we don't analyze the 2^16
possible inputs separately. In fact, we never destruct the vectors or refer to
the length at all, which leads us to our next example.
Example 3: Bit-vector xor
=========================
As it turns out, we can define ``xor_byte`` over *arbitrary-length* bitvectors
with very little modification. The circuit is virtually identical, except that
it takes a length argument ``n`` and all the ``8``\ s are replaced with ``n``:
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*||*)
Definition xor_bitvec (n : nat) :
Circuit (signal (Vec Bit n) * signal (Vec Bit n))
(signal (Vec Bit n)) :=
Comb (Vec.map2 xor2).
(*|
.. coq:: none
|*)
End WithCava.
(*|
We can define an interface for this circuit that also takes ``n`` as an
argument, and then compute a netlist for any number of bits we want.
|*)
Definition xor_bitvec_interface {n : nat}
:= sequentialInterface "xor_bitvec_interface"
"clk" PositiveEdge "rst" PositiveEdge
[mkPort "v1" (Vec Bit n); mkPort "v2" (Vec Bit n)]
[mkPort "o" (Vec Bit n)].
(* Netlist for a 2-bit xor *)
Compute
(makeCircuitNetlist xor_bitvec_interface (xor_bitvec 2)).(module).
(* Netlist for a 100-bit xor! *)
Compute
(makeCircuitNetlist xor_bitvec_interface (xor_bitvec 100)).(module).
(*|
Simulations are the same; just plug in any size.
|*)
(* 7 xor 10 = 13 (n=8) (same as xor_byte) *)
Compute map Bv2N
(simulate (xor_bitvec 8) [(N2Bv_sized 8 7, N2Bv_sized 8 10)]).
(* 1 xor 3 = 2 (n=2) *)
Compute map Bv2N
(simulate (xor_bitvec 2) [(N2Bv_sized 2 1, N2Bv_sized 2 3)]).
(* 1000 xor 3 = 1003 (n=10) *)
Compute map Bv2N
(simulate (xor_bitvec 10)
[(N2Bv_sized 10 1000, N2Bv_sized 10 3)]).
(*|
The correctness proof has is exactly the same as the ``xor_byte`` proof, except
with ``n`` instead of ``8``; the proof body is completely unchanged.
|*)
Lemma xor_bitvec_correct
n (i : list (Vector.t bool n * Vector.t bool n)) :
simulate (xor_bitvec n) i = map (fun '(v1,v2) => BVxor n v1 v2) i.
Proof.
cbv [xor_bitvec]. autorewrite with push_simulate.
apply map_ext; intros. destruct_pair_let.
cbv [BVxor]. simpl_ident.
apply Vector.map2_ext. reflexivity.
Qed.
(*|
We can also easily prove that, for 8-bit vectors, ``xor_bitvec`` is equivalent
to ``xor_byte``:
|*)
Lemma xor_bitvec_xor_byte_equiv
(i : list (Vector.t bool 8 * Vector.t bool 8)) :
simulate (xor_bitvec 8) i = simulate xor_byte i.
Proof. reflexivity. Qed.
(*|
This example demonstrates the advantage of using a proof assistant instead of a
more computational method. The ``xor_bitvec_correct`` proof checks essentially
instantly and holds for *all* values of ``n``. With one circuit definition, and
one proof, you have defined every single length of bit-vector xor you'll ever
need. The same principle can apply to more complicated structures as well.
Example 4: Tree of xors
=======================
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
To take the last circuit a step further, let's consider xoring not just two
``n``-length vectors, but an arbitrary number ``m`` of ``n``-length vectors!
We could write a definition that chains the xors together one by one::
xor (xor (xor (xor (xor a b) c) d) e f)
However, since there are no data dependencies, the circuit will have better
timing properties for possibly large ``m`` if it is a tree, e.g.::
xor (xor (xor a b) c) (xor (xor d e) f)
Luckily, Cava's standard library contains a ``tree`` combinator for exactly this
kind of situation.
|*)
Definition xor_tree {n m : nat} :
Circuit (signal (Vec (Vec Bit n) m))
(signal (Vec Bit n)) :=
Comb (tree (Vec.map2 xor2)).
(*|
.. coq:: none
|*)
End WithCava.
(*|
Now, we can just plug in any sequence of same-size vectors and compute the
results!
One note for those less familiar with Coq: the curly braces ``{}`` around the
``n`` and ``m`` arguments are standard Coq syntax for "implicit" arguments; Coq
will try to guess their values rather than requiring them to be passed
explicitly. So we can actually write ``xor_tree vec`` instead of e.g. ``xor_tree
2 3 vec``, and Coq will try to infer ``n`` and ``m`` from the type of
``vec``. If Coq struggles to infer them, we can also plug in these arguments
manually by referencing their names, e.g. ``xor_tree (m:=3) vec``.
|*)
(* 7 xor 10 = 13 (n=8, m=2)*)
Compute map Bv2N
(simulate xor_tree
[[N2Bv_sized 8 7; N2Bv_sized 8 10]]).
(* 1000 xor 3 = 1003 (n=10, m=2) *)
Compute map Bv2N
(simulate xor_tree
[[N2Bv_sized 10 1000; N2Bv_sized 10 3]]).
(* 1 xor 2 xor 4 xor 8 xor 16 xor 32 xor 64 xor 128 = 255 (n=8, m=8) *)
Compute map Bv2N
(simulate xor_tree
[[ N2Bv_sized 8 1
; N2Bv_sized 8 2
; N2Bv_sized 8 4
; N2Bv_sized 8 8
; N2Bv_sized 8 16
; N2Bv_sized 8 32
; N2Bv_sized 8 64
; N2Bv_sized 8 128
]]).
(*|
To prove the xor tree circuit correct, we prove that it's equivalent to a
``fold_left``, which is a native Coq loop. Essentially, this proof says that the
circuit, even with the tree structure, is equivalent to just chaining ``BVxor``
over the input in order (starting with 0, which is the identity for xor).
.. coq:: none
|*)
Hint Rewrite Nxor_BVxor using solve [eauto] : push_Bv2N.
(*||*)
Lemma xor_tree_correct n m (i : list (Vector.t (Vector.t bool n) m)) :
m <> 0 -> (* rule out size-0 tree *)
simulate xor_tree i = map (fun vs =>
Vector.fold_left
(BVxor n) (N2Bv_sized n 0) vs) i.
Proof.
cbv [xor_tree]. intros.
autorewrite with push_simulate.
apply map_ext; intros.
(* this rewrite produces side conditions; we'll handle them later *)
rewrite @tree_equiv with (t:=Vec Bit n) (id:=N2Bv_sized n 0);
intros; auto; simpl_ident.
{ (* xor circuit is equivalent to BVxor *)
cbv [BVxor].
apply Vector.fold_left_ext; intros; simpl_ident.
apply Vector.map2_ext. reflexivity. }
(* now, solve the tree_equiv side conditions *)
{ (* 0 is a left identity *)
apply Bv2N_inj. autorewrite with push_Bv2N.
apply N.lxor_0_l. }
{ (* 0 is a right identity *)
apply Bv2N_inj. autorewrite with push_Bv2N.
apply N.lxor_0_r. }
{ (* xor is associative *)
apply Bv2N_inj. autorewrite with push_Bv2N.
symmetry. cbn. apply N.lxor_assoc. }
Qed.
(*|
It's worth taking a moment here again to point out just how broad the proof of
correctness is. This proof applies to a circuit that xors two bits, and also
applies to a circuit that xors 1000 1000-bit bitvectors.
As a final touch, we can also prove that, when applied to just two bitvectors
(``m = 2``), ``xor_tree`` is equivalent to ``xor_bitvec``:
|*)
Lemma xor_bitvec_xor_tree_equiv
n (i : list (Vector.t bool n * Vector.t bool n)) :
simulate (xor_bitvec n) i =
simulate xor_tree (map (fun '(v1,v2) => [v1;v2]) i).
Proof.
cbv [xor_bitvec xor_tree]; autorewrite with push_simulate.
rewrite map_map.
apply map_ext; intros. destruct_pair_let.
(* The tree lemma produces the same side conditions as before, but
we solve them here in a more concise way *)
rewrite @tree_equiv with
(t:=Vec Bit n) (id:=N2Bv_sized n 0)
by (intros; auto; simpl_ident; apply Bv2N_inj;
autorewrite with push_Bv2N;
auto using N.lxor_0_r, N.lxor_0_l, N.lxor_assoc).
autorewrite with push_vector_fold vsimpl. simpl_ident.
apply Bv2N_inj. autorewrite with push_Bv2N.
rewrite N.lxor_0_l. reflexivity.
Qed.
(*|
At this point, we've covered pretty much everything you need to start building
*combinational* circuits in Cava -- circuits that don't have any
timing-dependent elements like loops or registers. In the next example, we'll
show how to build *sequential* circuits.
Example 5 : Delay for Three Timesteps
=====================================
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
The simplest sequential element is a unit delay (register). The delay takes in a
value at the end of the clock cycle, and then outputs the same value at the
start of the next clock cycle. So if we want to write a circuit that delays the
input stream by three timesteps, we can write three delays in a row:
|*)
Definition three_delays {t : SignalType}
: Circuit (signal t) (signal t) :=
Delay >==> Delay >==> Delay.
(*|
Note that this circuit definition will delay a signal *of any type*. The ``t``
argument can be anything, although to generate a concrete netlist or simulation
it will need to be plugged in. We'll do simulations and netlist generations with
a few different types.
The ``>==>`` notation means "compose these circuits", i.e connect the output
ports of the left-hand circuit to the input ports of the second. It's short for
``Compose``, which can also be used directly.
|*)
Locate ">==>". (* print the definition of the notation *)
(* Exactly the same thing as three_delays, just without notation *)
Definition three_delays_verbose {t : SignalType}
: Circuit (signal t) (signal t) :=
Compose (Compose Delay Delay) Delay.
(*|
.. coq:: none
|*)
End WithCava.
Local Open Scope list_scope.
(*|
``Compose`` and ``Delay`` are like ``Comb``; they are definitions that create
``Circuit``\ s. You can find a full list of ``Circuit`` constructors in the
reference_.
Here's the netlist for ``three_delays``, generated for two different signal
types:
|*)
Definition three_delays_interface {t : SignalType}
:= sequentialInterface "three_delays_interface"
"clk" PositiveEdge "rst" PositiveEdge
[mkPort "i" t]
[mkPort "o" t].
(* delay a stream of bits *)
Compute
(makeCircuitNetlist three_delays_interface
(three_delays (t:=Bit))).(module).
(* delay a stream of bytes *)
Compute
(makeCircuitNetlist three_delays_interface
(three_delays (t:=Vec Bit 8))).(module).
(*|
Let's simulate the circuit, first using a sequence of 1s:
|*)
Compute simulate (three_delays (t:=Bit)) (repeat true 10).
(*|
You can see that we get three ``false`` outputs before getting the stream of
``true`` values. The initial state of ``Delay`` is always "zeroed out"; for a
custom initial state, you can use the alternative constructor ``DelayInit``,
which takes an initial value.
We can also simulate the circuit with bytes. To make the simulations a little
more interesting, we'll use a small convenience definition that creates a
list of bytes counting up in sequence.
|*)
(* convenience definition for a sequence of numbers as bytes *)
Definition byte_seq start len : list (combType (Vec Bit 8)) :=
map (nat_to_bitvec_sized 8) (seq start len).
Compute map Bv2N (byte_seq 1 10). (* bytes from 1..10 *)
(*|
Now, when we run the simulations, it's easier to follow the timesteps:
|*)
Compute map Bv2N
(simulate three_delays (byte_seq 1 10)).
(*|
We can also compose ``three_delays`` with itself to get six delays:
|*)
Compute map Bv2N
(simulate (three_delays >==> three_delays) (byte_seq 1 10)).
(*|
Finally, the correctness proof for ``three_delays`` says that it prepends three
``defaultSignal`` values (the generic name for "a zeroed-out value of the
correct signal type") to the input, then truncates the new list to the length of
the original input.
|*)
Lemma three_delays_correct t (input : list (combType t)) :
simulate three_delays input
= firstn (length input)
(defaultSignal :: defaultSignal :: defaultSignal :: input).
Proof.
cbv [three_delays]; autorewrite with push_simulate.
push_length; natsimpl.
rewrite <-!firstn_cons. rewrite !firstn_firstn.
natsimpl. reflexivity.
Qed.
(*|
Example 6 : Sum the Input Stream
================================
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
This example will introduce ``Loop``, a circuit constructor that connects the
output port of a circuit to its own input port with a delay in the middle. This
creates *internal state* values, which can be referenced from inside the loop
but are not visible outside it. Visually, a loop looks like this:
.. image:: loop.png
:width: 70%
:alt: Circuit diagram showing a loop.
The following circuit gets a stream of bit-vectors as input, and uses ``Loop``
to provides the rolling sum as output:
|*)
Definition sum {n : nat}
: Circuit (signal (Vec Bit n)) (signal (Vec Bit n)) :=
Loop
(* The combinational circuit that makes up the loop body *)
(Comb
(fun '(input, state) =>
sum <- addN (input, state) ;;
(* return output and new state (the same in our case) *)
ret (sum, sum))).
(*|
The body of this loop is a combinational circuit whose input is the loop input
signal and the internal state, and whose output is the loop output signal and
the new state.
As discussed in the very first example, the ``_ <- _ ;; _`` notation is a
monadic bind; it's like a ``let`` binder or variable assignment, except that it
helps Cava track resource sharing. ``ret`` means "return". You can read in much
more detail about monad notations in the reference_.
For the purposes of the tutorial, we'll introduce just one more monad notation:
monad composition, represented by ``>=>``. Assuming ``f`` and ``g`` are monadic
functions, writing ``f >=> g`` is the same as writing ``fun x => y <- f x ;; g
y``. This is very similar to the notation for ``Compose`` (``>==>``) shown
earlier, except that it works for the bodies of combinational circuits rather
than for sequential circuits.
Using ``>=>``, we can rewrite ``sum`` as:
|*)
(* Means exactly the same thing as sum *)
Definition sum_concise {n : nat}
: Circuit (signal (Vec Bit n)) (signal (Vec Bit n)) :=
Loop (Comb (addN >=> fork2)).
(*|
The ``fork2`` combinator simply duplicates its input (like a fork in a wire).
As written, the ``sum`` and ``sum_concise`` circuits will start with an initial
state of zero (or ``defaultSignal``). If we want to pull in a specific initial
value, we can use ``LoopInit`` instead and plug in a compile-time constant:
|*)
Definition sum_init {n : nat} (init : combType (Vec Bit n)) :=
LoopInit init (Comb (addN >=> fork2)).
(*|
.. coq:: none
|*)
Definition double_sum {n : nat}
: Circuit (signal (Vec Bit n)) (signal (Vec Bit n)) :=
sum >==> sum.
Definition double_sum_mealy {n : nat}
: Circuit (signal (Vec Bit n)) (signal (Vec Bit n)) :=
Loop
(Loop
(Comb (fun '(v, ctr1, ctr2) =>
(* ctr1 += v *)
ctr1' <- addN (ctr1, v) ;;
(* ctr2 += ctr1 *)
ctr2' <- addN (ctr2, ctr1') ;;
(* output = ctr2 (also return new states of sums) *)
ret (ctr2', ctr1', ctr2')
))).
Definition double_sum_mealy_chaining {n : nat}
: Circuit (signal (Vec Bit n)) (signal (Vec Bit n)) :=
Loop
(Loop
(Comb
( (* start: (v, ctr1), ctr2 *)
first addN >=> (* ctr1', ctr2 *)
first fork2 >=> (* (ctr1', ctr1'), ctr2 *)
pair_right >=> (* ctr1', (ctr1', ctr2) *)
second addN >=> (* ctr1', ctr2' *)
swap >=> (* ctr2', ctr1' *)
first fork2 >=> (* (ctr2', ctr2'), ctr1' *)
pair_right >=> (* ctr2', (ctr2', ctr1') *)
swap (* (ctr2', ctr1'), ctr2' *)
))).
(*|
.. coq:: none
|*)
End WithCava.
(* same as sum of 1..10 *)
Compute map Bv2N
(simulate double_sum (repeat (N2Bv_sized 8 1) 10)).
(*|
Here's the netlist for ``sum``. You can see that no "loop" appears in the final
version, just a delay connecting the loop's output to its own input.
|*)
Definition sum_interface {n : nat}
:= sequentialInterface "sum8"
"clk" PositiveEdge "rst" PositiveEdge
[mkPort "i" (Vec Bit n)]
[mkPort "o" (Vec Bit n)].
Compute
(makeCircuitNetlist sum_interface (sum (n:=8))).(module).
(*|
Since this circuit has more complex timing behavior than previous examples, it's
a good model for introducing a new technique: validating the SystemVerilog
output by creating test cases based on the Coq semantics. This serves as an
extra layer of assurance that nothing went wrong in the unverified translation
from our netlist layer to SystemVerilog, and that our semantics are correct.
.. coq:: none
|*)
Local Open Scope N_scope.
(*|
First, we create a definition for the netlist, as well as the inputs and
expected outputs for our test. We generate the expected outputs using
``simulate``, to see what the Coq semantics expect the output to be. Then we can
use ``testBench`` to automatically create an extractable test.
|*)
Definition sum8Netlist := makeCircuitNetlist (sum_interface (n:=8)) sum.
Definition sum8_tb_inputs := map (N2Bv_sized 8) [3; 5; 7; 2; 4; 6].
Definition sum8_tb_expected_outputs := simulate sum sum8_tb_inputs.
(* print out the expected outputs according to the Coq semantics *)
Compute map Bv2N (sum8_tb_expected_outputs).
Definition sum8_tb :=
testBench "sum8_tb" (sum_interface (n := 8)) sum8_tb_inputs
sum8_tb_expected_outputs.
(*|
The circuit netlist and testbench can then be converted in SystemVerilog and
simulated using a SystemVerilog simulator like Verilator::
clang++ -L/usr/local/opt/sqlite/lib sum8_tb.o verilated.o verilated_vcd_c.o Vsum8_tb__ALL.a -o Vsum8_tb -lm -lstdc++ obj_dir/Vsum8_tb
10: tick = 0, i = 3, o = 3
20: tick = 1, i = 5, o = 8
30: tick = 2, i = 7, o = 15
40: tick = 3, i = 2, o = 17
50: tick = 4, i = 4, o = 21
60: tick = 5, i = 6, o = 27
which produces the expected results that were predicted by the model in Coq.
The testbench generates a VCD waveform that we can use to observe graphically
using a VCD waveform viewer like gtkwave:
.. image:: sum8_sim.png
:width: 70%
:alt: Simulation waveform for the sum8 circuit.
We can also synthesize a version of this testbench and the sum8 circuit
into gates using the Xilinx Vivado FPGA tools to produce a bitstream
that can be usd to program an FPGA chip. We can hook up this circuit
with another circuit that acts as a logic analyzer (ILA) then then
run and observe this actually running on an FPGA and capture its output:
.. image:: sum8_ila.png
:width: 70%
:alt: Logic analyzer trace capture for the sum8 circuit.
Reassuringly, the actual circuit behaves as predicted by the Cava model
in Coq and the SystemVerilog simulation.
.. coq:: none
|*)
Local Close Scope N_scope.
(*|
The netlist for ``sum_init`` can use the same interface as ``sum``, but needs an
extra argument for the initial value:
|*)
Compute
(makeCircuitNetlist sum_interface
(sum_init (N2Bv_sized 8 10))).(module).
(*|
Let's run a few simulations to see the circuit in action:
|*)
(* sum of 10 1s = 1,2,3,...10 *)
Compute map Bv2N
(simulate sum (repeat (N2Bv_sized 8 1) 10)).
(* sum of 1..10 = 1, 3, 6, 10, 15, 21, 28, 36, 45, 55 *)
Compute map Bv2N
(simulate sum (byte_seq 1 10)).
(* sum of 10 1s starting at 10 = 11,12,13,...20 *)
Compute map Bv2N
(simulate (sum_init (N2Bv_sized 8 10))
(repeat (N2Bv_sized 8 1) 10)).
(*|
To write a correctness proof for ``sum``, we first need to describe its
behavior. There are many ways to do this, but one way is shown below.
|*)
(* computes the sum of a list of numbers (as a single number, not the
rolling sum) *)
Definition sum_list_N (input : list N) : N :=
fold_left N.add input 0%N.
(* computes the *rolling* sum; the nth element of the output represents
the sum of the input up to index n *)
Definition rolling_sum (input : list N) : list N :=
map (fun i => sum_list_N (firstn (S i) input)) (seq 0 (length input)).
(* example to show the behavior of rolling_sum *)
Compute rolling_sum [5;6;7]%N.
(* specification for the sum circuit : convert to N, get rolling_sum,
convert back to bit-vectors *)
Definition spec_of_sum {n} (input : list (combType (Vec Bit n)))
: list (combType (Vec Bit n))
:= map (N2Bv_sized n) (rolling_sum (map Bv2N input)).
(*|
To reason about loops, it's often helpful to use loop invariants. The invariant
of a circuit loop takes three arguments: the timestep (a ``nat``), the current
circuit state (any state information needed for the loop body, plus the value
held by the delay at this timestep), and the output accumulator (a list of the
outputs generated so far). Because the ``sum`` circuit has a purely
combinational body, it has no internal state, so the body state in our case is
just Coq's ``unit`` type. Here's the invariant statement:
|*)
Definition sum_invariant {n} (input : list (combType (Vec Bit n)))
(t : nat)
(loop_state : unit * combType (Vec Bit n))
(output_accumulator : list (combType (Vec Bit n))) : Prop :=
(* at timestep t... *)
(* ...the loop state holds the sum of the inputs so far (that is,
the first t inputs) *)
loop_state = (tt, N2Bv_sized n (sum_list_N (map Bv2N (firstn t input))))
(* ... and the output accumulator matches the rolling-sum spec
applied to the inputs so far *)
/\ output_accumulator = spec_of_sum (firstn t input).
(*|
Now, we can use the invariant to prove a correctness lemma. This proof could
certainly be a little more elegant and automated, but the steps are left
explicit here for those who are curious to follow the reasoning in detail.
|*)
(* This lemma is helpful for sum_correct *)
Lemma sum_list_N_snoc_bitvec n l (v : Vector.t bool n) :
N2Bv_sized n (sum_list_N (l ++ [Bv2N v]))
= N2Bv_sized n (Bv2N v + Bv2N (N2Bv_sized n (sum_list_N l)))%N.
Proof.
cbv [sum_list_N]. autorewrite with pull_snoc.
(* use Bv2N to bring the goal into the N realm, where it's
easier to solve using modular arithmetic rules *)
bitvec_to_N.
rewrite N.add_mod_idemp_r by (apply N.pow_nonzero; lia).
rewrite N.add_comm.
reflexivity.
Qed.
(* Correctness lemma for sum *)
Lemma sum_correct n (input : list (combType (Vec Bit n))):
simulate sum input = spec_of_sum input.
Proof.
cbv [sum]. autorewrite with push_simulate. simpl_ident.
(* apply loop invariant lemma using sum_invariant; generates three
side conditions *)
eapply fold_left_accumulate_invariant_seq
with (I:=sum_invariant input).
{ (* prove that invariant holds at the start of the loop *)
cbv [sum_invariant]. cbn.
split; reflexivity. }
{ (* prove that, if the invariant holds at the beginning of the loop
body for timestep t, it holds at the end of the loop body for
timestep t + 1 *)
cbv [sum_invariant step]. intros. simpl_ident.
logical_simplify; subst.
split. (* separate the two invariant clauses *)
{ (* prove loop_state has the correct value *)
rewrite firstn_succ_snoc with (d0:=d) by lia.
autorewrite with pull_snoc. simpl_ident.
rewrite sum_list_N_snoc_bitvec.
reflexivity. }
{ (* prove the output accumulator has the correct value *)
cbv [spec_of_sum rolling_sum]. simpl_ident.
(* simplify expression using list lemmas *)
rewrite !map_map. push_length; natsimpl.
rewrite firstn_succ_snoc with (d0:=d) by lia.
pull_snoc; natsimpl.
apply f_equal2. (* split front of lists from last elements *)
{ apply map_ext_in; intro.
rewrite in_seq; intros.
(* list simplifications *)
push_firstn; listsimpl.
reflexivity. }
{ push_firstn. natsimpl.
rewrite sum_list_N_snoc_bitvec. reflexivity. } } }
{ (* prove that the invariant implies the postcondition *)
cbv [sum_invariant]; intros.
logical_simplify; subst.
push_firstn. reflexivity. }
Qed.
(*|
To wrap up our ``sum`` proofs, here's a quick demonstration that ``sum_concise``
is equivalent to ``sum``:
|*)
Lemma sum_concise_correct n (input : list (combType (Vec Bit n))):
simulate sum_concise input = simulate sum input.
Proof. reflexivity. Qed.
(*|
Example 7 : Fibonacci Sequence
==============================
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
In this example, we'll write a circuit that computes the Fibonacci
sequence. Here's the circuit diagram:
.. image:: fibonacci.png
:width: 70%
:alt: Circuit diagram for the fibonacci circuit
In the diagram, ``r1`` and ``r2`` are registers. Because of the delay a register
introduces, the ``addN`` in the middle of the circuit will, at timestep ``t``,
add together the output from timestep ``t-1`` and the output from timestep
``t-2``. In Cava, the circuit description looks like:
|*)
Definition fibonacci {sz}
: Circuit (signal Void) (signal (Vec Bit sz)) :=
(* initial state of r1 = 1 *)
let r1_init : combType (Vec Bit sz) := N2Bv_sized sz 1 in
(* initial state of r2 = 2^sz-1 *)
let r2_init : combType (Vec Bit sz) :=
N2Bv_sized sz (2^N.of_nat sz - 1) in
LoopInit r1_init
( (* start: (in, r1) *)
Comb (dropl >=> fork2) >==> (* r1, r1 *)
Second (DelayInit r2_init) >==> (* r1, r2 *)
Comb (addN >=> fork2) (* r1 + r2, r1 + r2 *)).
(*|
Note the initial values. In order to get the correct output for the first two
timesteps (0 and 1), we set ``r1 = 1`` and ``r2 = 2^sz-1``, where ``sz`` is the
size of the bit vector. Since ``addN`` performs truncating bit-vector addition,
the two initial values will sum to zero.
The circuit input is a ``Void`` signal, another ``SignalType``. It's an empty
type that's interpreted as a ``unit`` in Coq, and only serves to tell the
circuit how many timesteps it should run for.
It's also possible to write the ``fibonacci`` circuit as two nested loops with a
combinational body (essentially a mealy_ machine).
|*)
Definition fibonacci_mealy {sz}
: Circuit (signal Void) (signal (Vec Bit sz)) :=
let v1 : combType (Vec Bit sz) := N2Bv_sized sz 1 in
let v_negative1 : combType (Vec Bit sz) := Vector.const one sz in
LoopInit v1
(LoopInit v_negative1
(Comb
(fun '(_,r1,r2) =>
sum <- addN (r1, r2) ;;
ret (sum, sum, r1)))).
(*|
.. coq:: none
|*)
End WithCava.
(*|
As always, we can generate a netlist:
|*)
Definition fibonacci_interface {n : nat}
:= sequentialInterface "sum_interface"
"clk" PositiveEdge "rst" PositiveEdge
[mkPort "i" Void]
[mkPort "o" (Vec Bit n)].
Compute
(makeCircuitNetlist fibonacci_interface
(fibonacci (sz:=4))).(module).
Compute
(makeCircuitNetlist fibonacci_interface
(fibonacci_mealy (sz:=4))).(module).
(*|
We can run some simulations to make sure the circuit produces the expected
outputs:
|*)
Compute map Bv2N
(simulate (fibonacci (sz:=8)) (repeat tt 10)).
Compute map Bv2N
(simulate (fibonacci_mealy (sz:=8)) (repeat tt 10)).
(*|
Let's now try to prove that the circuit is correct. As with ``sum``, we first
need to first describe the behavior we expect. Here's a natural-number function
that computes the nth element of the Fibonacci sequence:
|*)
Fixpoint fibonacci_nat (n : nat) :=
match n with
| 0 => 0
| S m =>
let f_m := fibonacci_nat m in
match m with
| 0 => 1
| S p => fibonacci_nat p + f_m
end
end.
(*|
So, the specification of our ``fibonacci`` circuit is that, given ``n`` of its
empty inputs, the circuit produces (the bit-vector versions of) the first ``n``
elements of the Fibonacci sequence:
|*)
Definition spec_of_fibonacci {sz} (input : list unit)
: list (combType (Vec Bit sz))
:= map (fun n => N2Bv_sized sz (N.of_nat (fibonacci_nat n)))
(seq 0 (length input)).
(*|
We'll need a loop invariant, which just says that the output accumulator matches
the spec and that the values in ``r1`` and ``r2`` are the right numbers from the
Fibonacci sequence.
|*)
Definition fibonacci_invariant {sz}
(t : nat)
(loop_state :
unit * (unit * combType (Vec Bit sz)) * unit
* combType (Vec Bit sz))
(output_accumulator : list (combType (Vec Bit sz))) : Prop :=
let r1 := snd loop_state in
let r2 := snd (snd (fst (fst loop_state))) in
(* at timestep t... *)
(* ...r1 holds fibonacci_nat (t-1), or 1 if t=0 *)
r1 = match t with
| 0 => N2Bv_sized sz 1
| S t_minus1 => N2Bv_sized sz (N.of_nat (fibonacci_nat t_minus1))
end
(* ... and r2 holds fibonacci_nat (t-2), or 1 if t=1, 2^sz-1 if t=0 *)
/\ r2 = match t with
| 0 => N2Bv_sized sz (2^N.of_nat sz - 1)
| 1 => N2Bv_sized sz 1
| S (S t_minus2) =>
N2Bv_sized sz (N.of_nat (fibonacci_nat t_minus2))
end
(* ... and the output accumulator matches the circuit spec for the
inputs so far *)
/\ output_accumulator = spec_of_fibonacci (repeat tt t).
(*|
Note that, unlike for ``sum``, there's actually a bit-vector
in the loop body state from the ``DelayInit`` element.
The extra ``unit`` types are an unfortunate feature of the current setup and
we're working on removing them. For now, just know that you can figure out what
the loop body's type should be by computing its ``circuit_state``, like this:
|*)
Compute (circuit_state
(* body of fibonacci loop: *)
(Comb (dropl >=> fork2) >==>
Second (DelayInit _) >==>
Comb (addN >=> fork2))).
(*|
Here's the proof of correctness, with the help of a couple of small
helper lemmas:
|*)
(* Helper lemma for fibonacci_correct *)
Lemma bitvec_negative_one_plus_one sz :
N2Bv_sized sz (1 + (2^N.of_nat sz - 1)) = N2Bv_sized sz 0.
Proof.
bitvec_to_N.
assert (2^N.of_nat sz <> 0)%N by (apply N.pow_nonzero; lia).
transitivity ((2^N.of_nat sz) mod (2 ^ N.of_nat sz))%N;
[ f_equal; lia | ].
rewrite N.mod_same, N.mod_0_l by lia.
reflexivity.
Qed.
(* Helper lemma for fibonacci_correct *)
Lemma fibonacci_nat_step n :
fibonacci_nat (S (S n)) = fibonacci_nat (S n) + fibonacci_nat n.
Proof. cbn [fibonacci_nat]. lia. Qed.
(* the nth element of the simulation output is the bit-vector version of
(fibonacci_spec n) *)
Lemma fibonacci_correct sz (input : list unit) :
simulate (fibonacci (sz:=sz)) input = spec_of_fibonacci input.
Proof.
cbv [fibonacci]. autorewrite with push_simulate.
simpl_ident. cbn [circuit_state DelayInit].
eapply fold_left_accumulate_invariant_seq
with (I:=fibonacci_invariant).
{ (* prove loop invariant holds at start *)
cbv [fibonacci_invariant]. cbn.
ssplit; reflexivity. }
{ (* prove that, if the invariant holds at the beginning of the loop
body for timestep t, it holds at the end of the loop body for
timestep t + 1 *)
cbv [fibonacci_invariant DelayInit mcompose].
cbn [circuit_state step]. intros; simpl_ident.
destruct_products. cbn [fst snd] in *.
logical_simplify; subst. simpl_ident.
cbv [spec_of_fibonacci].
autorewrite with push_length.
destruct t; [ | destruct t ].
{ (* t = 0 case *)
cbn [seq map fibonacci_nat].
autorewrite with pull_N2Bv_sized.
rewrite bitvec_negative_one_plus_one.
ssplit; reflexivity. }
{ (* t = 1 case *)
cbn [seq map fibonacci_nat].
autorewrite with pull_N2Bv_sized.
ssplit; reflexivity. }
{ (* t >= 2 *)
autorewrite with pull_snoc natsimpl pull_N2Bv_sized.
rewrite fibonacci_nat_step.
ssplit; repeat (f_equal; try lia). } }
{ (* prove that the invariant implies the postcondition *)
cbv [fibonacci_invariant]; intros.
logical_simplify; subst. cbn [combType].
rewrite <-(list_unit_equiv input).
reflexivity. }
Qed.
(*|
That concludes our tutorial! If you want to explore further, take a look at the
``examples`` directory in our GitHub repo_, or check out our advanced-fetures
demo_. You can also view the full source_ for this page if you want to
experiment with these examples yourself.
.. _Alectryon: https://github.com/cpitclaudel/alectryon
.. _demo: expbysquaring
.. _example: #example-6-sum-the-input-stream
.. _reference: ../reference
.. _mealy: https://en.wikipedia.org/wiki/Mealy_machine
.. _repo: https://github.com/project-oak/silveroak
.. _source: https://github.com/project-oak/silveroak/blob/main/demos/tutorial.v
|*)
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO register
*/
module axis_srl_register #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [DATA_WIDTH+2-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_reg[ptr_reg];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = valid_reg[ptr_reg];
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~output_axis_tready & output_axis_tvalid;
// transfer in if not full
if (input_axis_tready) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};
valid_reg[0] <= input_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (output_axis_tready) begin
ptr_reg <= 0;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output mcu_rrq,
output mcu_write,
output mcu_wrq,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output dac_play_out,
output dac_reset_out,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// feature enable
output reg [7:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// debug
output DBG_mcu_nextaddr
);
initial begin
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg DAC_VOL_LATCH_BUF;
reg DAC_PLAY_OUT_BUF;
reg DAC_RESET_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
DAC_PLAY_OUT_BUF <= 1'b0;
8'he2: // resume DAC
DAC_PLAY_OUT_BUF <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
DAC_RESET_OUT_BUF <= 1'b1;
32'h3:
DAC_RESET_OUT_BUF <= 1'b0;
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
32'h4:
MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'hec: // set DAC properties
begin
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
parameter ST_RQ = 2'b01;
parameter ST_IDLE = 2'b10;
reg [1:0] rrq_state;
initial rrq_state = ST_IDLE;
reg mcu_rrq_r;
reg [1:0] wrq_state;
initial wrq_state = ST_IDLE;
reg mcu_wrq_r;
always @(posedge clk) begin
case(rrq_state)
ST_IDLE: begin
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq_r <= 1'b1;
rrq_state <= ST_RQ;
end else
rrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_rrq_r <= 1'b0;
rrq_state <= ST_IDLE;
end
endcase
end
always @(posedge clk) begin
case(wrq_state)
ST_IDLE: begin
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq_r <= 1'b1;
wrq_state <= ST_RQ;
end else
wrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_wrq_r <= 1'b0;
wrq_state <= ST_IDLE;
end
endcase
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_rrq = mcu_rrq_r;
assign mcu_wrq = mcu_wrq_r;
assign mcu_write = SD_DMA_STATUS
? (SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign dac_play_out = DAC_PLAY_OUT_BUF;
assign dac_reset_out = DAC_RESET_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_2_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_2_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog wrapper for muxb16to1 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb16to1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb16to1_2 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input [15:0] D ;
input [15:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb16to1_2 (
Z,
D,
S
);
output Z;
input [15:0] D;
input [15:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_2_V
|
// bsg_rp_clk_gen_coarse_delay_element
//
// o contains controllably delayed signal
//
// module bsg_clk_gen_coarse_delay_element #(parameter `BSG_INV_PARAM(start_tap_p))
//
module bsg_rp_clk_gen_atomic_delay_tuner
(input i
, input sel_i
, input we_async_i
, input we_inited_i // basically says we_async_i should have successfully passed through
// the generated clock's synchronizers; i.e. the generated clock is
// running and the bsg_tag_slave and client have been initialized
, input async_reset_neg_i
, output we_o
, output o
);
wire [1:0] sel_r;
wire [8:0] signal;
wire we_o_pre_buf;
assign signal[0] = i;
// synopsys rp_group (bsg_clk_gen_adt)
// synopsys rp_fill (13 2 LX)
CKND2BWP I1 (.I(signal[0]), .ZN(signal[1]) );
CKND2BWP I2 (.I(signal[1]), .ZN(signal[2]) );
CKND4BWP I2a (.I(signal[1]), .ZN() );
CKND2BWP I3 (.I(signal[2]), .ZN(signal[3]) );
CKND2BWP I4 (.I(signal[3]), .ZN(signal[4]) );
CKND4BWP I4a (.I(signal[3]), .ZN() );
CKND2BWP I4b (.I(signal[3]), .ZN() ); // this is an extra gate because
// we are not attaching to the mux
// cap tries to match that of mux input
CKND2BWP I5 (.I(signal[4]), .ZN(signal[5]) );
CKND2BWP I6 (.I(signal[5]), .ZN(signal[6]) );
CKND4BWP I6a (.I(signal[5]), .ZN() );
CKND2BWP I7 (.I(signal[6]), .ZN(signal[7]) );
CKND2BWP I8 (.I(signal[7]), .ZN(signal[8]) );
CKND4BWP I8a (.I(signal[7]), .ZN() );
CKND3BWP I8b (.I(signal[7]), .ZN() ); // fudge factor capacitance
// synopsys rp_fill (0 1 RX)
wire zero_bit;
MUX4ND4BWP M1 ( .I0(signal[8])
,.I1(signal[6])
,.I2(zero_bit)
,.I3(signal[0])
,.S0(sel_r[0])
,.S1(sel_r[1])
,.ZN(o )
);
wire [1:0] mux_lo;
wire we_i_sync, we_i_sync_sync, we_i_sync_sync_nand;
// synopsys rp_fill (0 0 RX)
// this gate picks input 01 when async reset is low, initializing the oscillator
IND2D2BWP NB (.A1(sel_r[0]), .B1(async_reset_neg_i), .ZN(sel_r[1]));
TIELBWP ZB (.ZN(zero_bit));
DFCND4BWP sel_r_reg_0 (.D(mux_lo[0]), .CP(o) ,.CDN(async_reset_neg_i), .Q(sel_r[0]), .QN());
//LHCND4BWP sel_r_latch_0 (.D(mux_lo[0]), .E(o) ,.CDN(async_reset_neg_i), .Q(sel_r[0]), .QN());
// 40nm: non-inverting mux 32.5ps + load S->Z
// 40nm: inverting mux 43ps + load S->ZN
// inputs are reversed because select is inverted
// we_i&we_inited_i=1 -> new value (I0)
// we_i&we_inited-i=0 -> use value in register (I1)
MUX2D1BWP MX1 ( .I0(sel_i), .I1(sel_r[0]), .S(we_i_sync_sync_nand), .Z(mux_lo[0]));
// nand 10ps versus 22ps
ND2D1BWP bsg_we_nand (.A1(we_i_sync_sync), .A2(we_inited_i), .ZN(we_i_sync_sync_nand));
// synchronizer flops; negative edge triggered
//DFND1BWP bsg_SYNC_2_r (.D(we_i_sync), .CPN(o), .Q(we_i_sync_sync), .QN());
//DFND1BWP bsg_SYNC_1_r (.D(we_async_i), .CPN(o), .Q(we_i_sync), .QN());
DFNCND1BWP bsg_SYNC_2_r (.D(we_i_sync), .CPN(o), .CDN(async_reset_neg_i), .Q(we_i_sync_sync), .QN());
DFNCND1BWP bsg_SYNC_1_r (.D(we_async_i), .CPN(o), .CDN(async_reset_neg_i), .Q(we_i_sync), .QN());
// drive we signal to next CDT; minimize capacitive load on critical we_i path
INVD0BWP we_o_pre (.I(we_i_sync_sync_nand), .ZN(we_o_pre_buf));
BUFFD4BWP we_o_buf (.I(we_o_pre_buf),. Z(we_o));
// synopsys rp_endgroup (bsg_clk_gen_adt)
endmodule
`BSG_ABSTRACT_MODULE(bsg_rp_clk_gen_atomic_delay_tuner)
|
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
module LenCtr_Lookup(input [4:0] X, output [7:0] Yout);
reg [6:0] Y;
always @*
begin
case(X)
0: Y = 7'h05;
1: Y = 7'h7F;
2: Y = 7'h0A;
3: Y = 7'h01;
4: Y = 7'h14;
5: Y = 7'h02;
6: Y = 7'h28;
7: Y = 7'h03;
8: Y = 7'h50;
9: Y = 7'h04;
10: Y = 7'h1E;
11: Y = 7'h05;
12: Y = 7'h07;
13: Y = 7'h06;
14: Y = 7'h0D;
15: Y = 7'h07;
16: Y = 7'h06;
17: Y = 7'h08;
18: Y = 7'h0C;
19: Y = 7'h09;
20: Y = 7'h18;
21: Y = 7'h0A;
22: Y = 7'h30;
23: Y = 7'h0B;
24: Y = 7'h60;
25: Y = 7'h0C;
26: Y = 7'h24;
27: Y = 7'h0D;
28: Y = 7'h08;
29: Y = 7'h0E;
30: Y = 7'h10;
31: Y = 7'h0F;
endcase
end
assign Yout = {Y, 1'b0};
endmodule
module SquareChan(input clk, input ce, input reset, input sq2,
input [1:0] Addr,
input [7:0] DIN,
input MW,
input LenCtr_Clock,
input Env_Clock,
input Enabled,
input [7:0] LenCtr_In,
output reg [3:0] Sample,
output IsNonZero);
reg [7:0] LenCtr;
// Register 1
reg [1:0] Duty;
reg EnvLoop, EnvDisable, EnvDoReset;
reg [3:0] Volume, Envelope, EnvDivider;
wire LenCtrHalt = EnvLoop; // Aliased bit
assign IsNonZero = (LenCtr != 0);
// Register 2
reg SweepEnable, SweepNegate, SweepReset;
reg [2:0] SweepPeriod, SweepDivider, SweepShift;
reg [10:0] Period;
reg [11:0] TimerCtr;
reg [2:0] SeqPos;
wire [10:0] ShiftedPeriod = (Period >> SweepShift);
wire [10:0] PeriodRhs = (SweepNegate ? (~ShiftedPeriod + {10'b0, sq2}) : ShiftedPeriod);
wire [11:0] NewSweepPeriod = Period + PeriodRhs;
wire ValidFreq = Period[10:3] >= 8 && (SweepNegate || !NewSweepPeriod[11]);
always @(posedge clk) if (reset) begin
LenCtr <= 0;
Duty <= 0;
EnvDoReset <= 0;
EnvLoop <= 0;
EnvDisable <= 0;
Volume <= 0;
Envelope <= 0;
EnvDivider <= 0;
SweepEnable <= 0;
SweepNegate <= 0;
SweepReset <= 0;
SweepPeriod <= 0;
SweepDivider <= 0;
SweepShift <= 0;
Period <= 0;
TimerCtr <= 0;
SeqPos <= 0;
end else if (ce) begin
// Check if writing to the regs of this channel
// NOTE: This needs to be done before the clocking below.
if (MW) begin
case(Addr)
0: begin
// if (sq2) $write("SQ0: Duty=%d, EnvLoop=%d, EnvDisable=%d, Volume=%d\n", DIN[7:6], DIN[5], DIN[4], DIN[3:0]);
Duty <= DIN[7:6];
EnvLoop <= DIN[5];
EnvDisable <= DIN[4];
Volume <= DIN[3:0];
end
1: begin
// if (sq2) $write("SQ1: SweepEnable=%d, SweepPeriod=%d, SweepNegate=%d, SweepShift=%d, DIN=%X\n", DIN[7], DIN[6:4], DIN[3], DIN[2:0], DIN);
SweepEnable <= DIN[7];
SweepPeriod <= DIN[6:4];
SweepNegate <= DIN[3];
SweepShift <= DIN[2:0];
SweepReset <= 1;
end
2: begin
// if (sq2) $write("SQ2: Period=%d. DIN=%X\n", DIN, DIN);
Period[7:0] <= DIN;
end
3: begin
// Upper bits of the period
// if (sq2) $write("SQ3: PeriodUpper=%d LenCtr=%x DIN=%X\n", DIN[2:0], LenCtr_In, DIN);
Period[10:8] <= DIN[2:0];
LenCtr <= LenCtr_In;
EnvDoReset <= 1;
SeqPos <= 0;
end
endcase
end
// Count down the square timer...
if (TimerCtr == 0) begin
// Timer was clocked
TimerCtr <= {Period, 1'b0};
SeqPos <= SeqPos - 1;
end else begin
TimerCtr <= TimerCtr - 1;
end
// Clock the length counter?
if (LenCtr_Clock && LenCtr != 0 && !LenCtrHalt) begin
LenCtr <= LenCtr - 1;
end
// Clock the sweep unit?
if (LenCtr_Clock) begin
if (SweepDivider == 0) begin
SweepDivider <= SweepPeriod;
if (SweepEnable && SweepShift != 0 && ValidFreq)
Period <= NewSweepPeriod[10:0];
end else begin
SweepDivider <= SweepDivider - 1;
end
if (SweepReset)
SweepDivider <= SweepPeriod;
SweepReset <= 0;
end
// Clock the envelope generator?
if (Env_Clock) begin
if (EnvDoReset) begin
EnvDivider <= Volume;
Envelope <= 15;
EnvDoReset <= 0;
end else if (EnvDivider == 0) begin
EnvDivider <= Volume;
if (Envelope != 0 || EnvLoop)
Envelope <= Envelope - 1;
end else begin
EnvDivider <= EnvDivider - 1;
end
end
// Length counter forced to zero if disabled.
if (!Enabled)
LenCtr <= 0;
end
reg DutyEnabled;
always @* begin
// Determine if the duty is enabled or not
case (Duty)
0: DutyEnabled = (SeqPos == 7);
1: DutyEnabled = (SeqPos >= 6);
2: DutyEnabled = (SeqPos >= 4);
3: DutyEnabled = (SeqPos < 6);
endcase
// Compute the output
if (LenCtr == 0 || !ValidFreq || !DutyEnabled)
Sample = 0;
else
Sample = EnvDisable ? Volume : Envelope;
end
endmodule
module TriangleChan(input clk, input ce, input reset,
input [1:0] Addr,
input [7:0] DIN,
input MW,
input LenCtr_Clock,
input LinCtr_Clock,
input Enabled,
input [7:0] LenCtr_In,
output [3:0] Sample,
output IsNonZero);
//
reg [10:0] Period, TimerCtr;
reg [4:0] SeqPos;
//
// Linear counter state
reg [6:0] LinCtrPeriod, LinCtr;
reg LinCtrl, LinHalt;
wire LinCtrZero = (LinCtr == 0);
//
// Length counter state
reg [7:0] LenCtr;
wire LenCtrHalt = LinCtrl; // Aliased bit
wire LenCtrZero = (LenCtr == 0);
assign IsNonZero = !LenCtrZero;
//
always @(posedge clk) if (reset) begin
Period <= 0;
TimerCtr <= 0;
SeqPos <= 0;
LinCtrPeriod <= 0;
LinCtr <= 0;
LinCtrl <= 0;
LinHalt <= 0;
LenCtr <= 0;
end else if (ce) begin
// Check if writing to the regs of this channel
if (MW) begin
case (Addr)
0: begin
LinCtrl <= DIN[7];
LinCtrPeriod <= DIN[6:0];
end
2: begin
Period[7:0] <= DIN;
end
3: begin
Period[10:8] <= DIN[2:0];
LenCtr <= LenCtr_In;
LinHalt <= 1;
end
endcase
end
// Count down the period timer...
if (TimerCtr == 0) begin
TimerCtr <= Period;
end else begin
TimerCtr <= TimerCtr - 1;
end
//
// Clock the length counter?
if (LenCtr_Clock && !LenCtrZero && !LenCtrHalt) begin
LenCtr <= LenCtr - 1;
end
//
// Clock the linear counter?
if (LinCtr_Clock) begin
if (LinHalt)
LinCtr <= LinCtrPeriod;
else if (!LinCtrZero)
LinCtr <= LinCtr - 1;
if (!LinCtrl)
LinHalt <= 0;
end
//
// Length counter forced to zero if disabled.
if (!Enabled)
LenCtr <= 0;
//
// Clock the sequencer position
if (TimerCtr == 0 && !LenCtrZero && !LinCtrZero)
SeqPos <= SeqPos + 1;
end
// Generate the output
assign Sample = SeqPos[3:0] ^ {4{~SeqPos[4]}};
//
endmodule
module NoiseChan(input clk, input ce, input reset,
input [1:0] Addr,
input [7:0] DIN,
input MW,
input LenCtr_Clock,
input Env_Clock,
input Enabled,
input [7:0] LenCtr_In,
output [3:0] Sample,
output IsNonZero);
//
// Envelope volume
reg EnvLoop, EnvDisable, EnvDoReset;
reg [3:0] Volume, Envelope, EnvDivider;
// Length counter
wire LenCtrHalt = EnvLoop; // Aliased bit
reg [7:0] LenCtr;
//
reg ShortMode;
reg [14:0] Shift = 1;
assign IsNonZero = (LenCtr != 0);
//
// Period stuff
reg [3:0] Period;
reg [11:0] NoisePeriod, TimerCtr;
always @* begin
case (Period)
0: NoisePeriod = 12'h004;
1: NoisePeriod = 12'h008;
2: NoisePeriod = 12'h010;
3: NoisePeriod = 12'h020;
4: NoisePeriod = 12'h040;
5: NoisePeriod = 12'h060;
6: NoisePeriod = 12'h080;
7: NoisePeriod = 12'h0A0;
8: NoisePeriod = 12'h0CA;
9: NoisePeriod = 12'h0FE;
10: NoisePeriod = 12'h17C;
11: NoisePeriod = 12'h1FC;
12: NoisePeriod = 12'h2FA;
13: NoisePeriod = 12'h3F8;
14: NoisePeriod = 12'h7F2;
15: NoisePeriod = 12'hFE4;
endcase
end
//
always @(posedge clk) if (reset) begin
EnvLoop <= 0;
EnvDisable <= 0;
EnvDoReset <= 0;
Volume <= 0;
Envelope <= 0;
EnvDivider <= 0;
LenCtr <= 0;
ShortMode <= 0;
Shift <= 1;
Period <= 0;
TimerCtr <= 0;
end else if (ce) begin
// Check if writing to the regs of this channel
if (MW) begin
case (Addr)
0: begin
EnvLoop <= DIN[5];
EnvDisable <= DIN[4];
Volume <= DIN[3:0];
end
2: begin
ShortMode <= DIN[7];
Period <= DIN[3:0];
end
3: begin
LenCtr <= LenCtr_In;
EnvDoReset <= 1;
end
endcase
end
// Count down the period timer...
if (TimerCtr == 0) begin
TimerCtr <= NoisePeriod;
// Clock the shift register. Use either
// bit 1 or 6 as the tap.
Shift <= {
Shift[0] ^ (ShortMode ? Shift[6] : Shift[1]),
Shift[14:1]};
end else begin
TimerCtr <= TimerCtr - 1;
end
// Clock the length counter?
if (LenCtr_Clock && LenCtr != 0 && !LenCtrHalt) begin
LenCtr <= LenCtr - 1;
end
// Clock the envelope generator?
if (Env_Clock) begin
if (EnvDoReset) begin
EnvDivider <= Volume;
Envelope <= 15;
EnvDoReset <= 0;
end else if (EnvDivider == 0) begin
EnvDivider <= Volume;
if (Envelope != 0)
Envelope <= Envelope - 1;
else if (EnvLoop)
Envelope <= 15;
end else
EnvDivider <= EnvDivider - 1;
end
if (!Enabled)
LenCtr <= 0;
end
// Produce the output signal
assign Sample =
(LenCtr == 0 || Shift[0]) ?
0 :
(EnvDisable ? Volume : Envelope);
endmodule
module DmcChan(input clk, input ce, input reset,
input odd_or_even,
input [2:0] Addr,
input [7:0] DIN,
input MW,
output [6:0] Sample,
output DmaReq, // 1 when DMC wants DMA
input DmaAck, // 1 when DMC byte is on DmcData. DmcDmaRequested should go low.
output [15:0] DmaAddr, // Address DMC wants to read
input [7:0] DmaData, // Input data to DMC from memory.
output Irq,
output IsDmcActive);
reg IrqEnable;
reg IrqActive;
reg Loop; // Looping enabled
reg [3:0] Freq; // Current value of frequency register
reg [6:0] Dac = 0; // Current value of DAC
reg [7:0] SampleAddress; // Base address of sample
reg [7:0] SampleLen; // Length of sample
reg [7:0] ShiftReg; // Shift register
reg [8:0] Cycles; // Down counter, is the period
reg [14:0] Address; // 15 bits current address, 0x8000-0xffff
reg [11:0] BytesLeft; // 12 bits bytes left counter 0 - 4081.
reg [2:0] BitsUsed; // Number of bits left in the SampleBuffer.
reg [7:0] SampleBuffer; // Next value to be loaded into shift reg
reg HasSampleBuffer; // Sample buffer is nonempty
reg HasShiftReg; // Shift reg is non empty
reg [8:0] NewPeriod[0:15];
reg DmcEnabled;
reg [1:0] ActivationDelay;
assign DmaAddr = {1'b1, Address};
assign Sample = Dac;
assign Irq = IrqActive;
assign IsDmcActive = DmcEnabled;
assign DmaReq = !HasSampleBuffer && DmcEnabled && !ActivationDelay[0];
initial begin
NewPeriod[0] = 428;
NewPeriod[1] = 380;
NewPeriod[2] = 340;
NewPeriod[3] = 320;
NewPeriod[4] = 286;
NewPeriod[5] = 254;
NewPeriod[6] = 226;
NewPeriod[7] = 214;
NewPeriod[8] = 190;
NewPeriod[9] = 160;
NewPeriod[10] = 142;
NewPeriod[11] = 128;
NewPeriod[12] = 106;
NewPeriod[13] = 84;
NewPeriod[14] = 72;
NewPeriod[15] = 54;
end
// Shift register initially loaded with 07
always @(posedge clk) begin
if (reset) begin
IrqEnable <= 0;
IrqActive <= 0;
Loop <= 0;
Freq <= 0;
Dac <= 0;
SampleAddress <= 0;
SampleLen <= 0;
ShiftReg <= 8'hff;
Cycles <= 439;
Address <= 0;
BytesLeft <= 0;
BitsUsed <= 0;
SampleBuffer <= 0;
HasSampleBuffer <= 0;
HasShiftReg <= 0;
DmcEnabled <= 0;
ActivationDelay <= 0;
end else if (ce) begin
if (ActivationDelay == 3 && !odd_or_even) ActivationDelay <= 1;
if (ActivationDelay == 1) ActivationDelay <= 0;
if (MW) begin
case (Addr)
0: begin // $4010 il-- ffff IRQ enable, loop, frequency index
IrqEnable <= DIN[7];
Loop <= DIN[6];
Freq <= DIN[3:0];
if (!DIN[7]) IrqActive <= 0;
end
1: begin // $4011 -ddd dddd DAC
// This will get missed if the Dac <= far below runs, that is by design.
Dac <= DIN[6:0];
end
2: begin // $4012 aaaa aaaa sample address
SampleAddress <= DIN[7:0];
end
3: begin // $4013 llll llll sample length
SampleLen <= DIN[7:0];
end
5: begin // $4015 write ---D NT21 Enable DMC (D)
IrqActive <= 0;
DmcEnabled <= DIN[4];
// If the DMC bit is set, the DMC sample will be restarted only if not already active.
if (DIN[4] && !DmcEnabled) begin
Address <= {1'b1, SampleAddress, 6'b000000};
BytesLeft <= {SampleLen, 4'b0000};
ActivationDelay <= 3;
end
end
endcase
end
Cycles <= Cycles - 1;
if (Cycles == 1) begin
Cycles <= NewPeriod[Freq];
if (HasShiftReg) begin
if (ShiftReg[0]) begin
Dac[6:1] <= (Dac[6:1] != 6'b111111) ? Dac[6:1] + 6'b000001 : Dac[6:1];
end else begin
Dac[6:1] <= (Dac[6:1] != 6'b000000) ? Dac[6:1] + 6'b111111 : Dac[6:1];
end
end
ShiftReg <= {1'b0, ShiftReg[7:1]};
BitsUsed <= BitsUsed + 1;
if (BitsUsed == 7) begin
HasShiftReg <= HasSampleBuffer;
ShiftReg <= SampleBuffer;
HasSampleBuffer <= 0;
end
end
// Acknowledge DMA?
if (DmaAck) begin
Address <= Address + 1;
BytesLeft <= BytesLeft - 1;
HasSampleBuffer <= 1;
SampleBuffer <= DmaData;
if (BytesLeft == 0) begin
Address <= {1'b1, SampleAddress, 6'b000000};
BytesLeft <= {SampleLen, 4'b0000};
DmcEnabled <= Loop;
if (!Loop && IrqEnable)
IrqActive <= 1;
end
end
end
end
endmodule
module ApuLookupTable(input clk, input [7:0] in_a, input [7:0] in_b, output [15:0] out);
reg [15:0] lookup[0:511];
reg [15:0] tmp_a, tmp_b;
initial begin
lookup[ 0] = 0; lookup[ 1] = 760; lookup[ 2] = 1503; lookup[ 3] = 2228;
lookup[ 4] = 2936; lookup[ 5] = 3627; lookup[ 6] = 4303; lookup[ 7] = 4963;
lookup[ 8] = 5609; lookup[ 9] = 6240; lookup[ 10] = 6858; lookup[ 11] = 7462;
lookup[ 12] = 8053; lookup[ 13] = 8631; lookup[ 14] = 9198; lookup[ 15] = 9752;
lookup[ 16] = 10296; lookup[ 17] = 10828; lookup[ 18] = 11349; lookup[ 19] = 11860;
lookup[ 20] = 12361; lookup[ 21] = 12852; lookup[ 22] = 13334; lookup[ 23] = 13807;
lookup[ 24] = 14270; lookup[ 25] = 14725; lookup[ 26] = 15171; lookup[ 27] = 15609;
lookup[ 28] = 16039; lookup[ 29] = 16461; lookup[ 30] = 16876; lookup[256] = 0;
lookup[257] = 439; lookup[258] = 874; lookup[259] = 1306; lookup[260] = 1735;
lookup[261] = 2160; lookup[262] = 2581; lookup[263] = 2999; lookup[264] = 3414;
lookup[265] = 3826; lookup[266] = 4234; lookup[267] = 4639; lookup[268] = 5041;
lookup[269] = 5440; lookup[270] = 5836; lookup[271] = 6229; lookup[272] = 6618;
lookup[273] = 7005; lookup[274] = 7389; lookup[275] = 7769; lookup[276] = 8147;
lookup[277] = 8522; lookup[278] = 8895; lookup[279] = 9264; lookup[280] = 9631;
lookup[281] = 9995; lookup[282] = 10356; lookup[283] = 10714; lookup[284] = 11070;
lookup[285] = 11423; lookup[286] = 11774; lookup[287] = 12122; lookup[288] = 12468;
lookup[289] = 12811; lookup[290] = 13152; lookup[291] = 13490; lookup[292] = 13825;
lookup[293] = 14159; lookup[294] = 14490; lookup[295] = 14818; lookup[296] = 15145;
lookup[297] = 15469; lookup[298] = 15791; lookup[299] = 16110; lookup[300] = 16427;
lookup[301] = 16742; lookup[302] = 17055; lookup[303] = 17366; lookup[304] = 17675;
lookup[305] = 17981; lookup[306] = 18286; lookup[307] = 18588; lookup[308] = 18888;
lookup[309] = 19187; lookup[310] = 19483; lookup[311] = 19777; lookup[312] = 20069;
lookup[313] = 20360; lookup[314] = 20648; lookup[315] = 20935; lookup[316] = 21219;
lookup[317] = 21502; lookup[318] = 21783; lookup[319] = 22062; lookup[320] = 22339;
lookup[321] = 22615; lookup[322] = 22889; lookup[323] = 23160; lookup[324] = 23431;
lookup[325] = 23699; lookup[326] = 23966; lookup[327] = 24231; lookup[328] = 24494;
lookup[329] = 24756; lookup[330] = 25016; lookup[331] = 25274; lookup[332] = 25531;
lookup[333] = 25786; lookup[334] = 26040; lookup[335] = 26292; lookup[336] = 26542;
lookup[337] = 26791; lookup[338] = 27039; lookup[339] = 27284; lookup[340] = 27529;
lookup[341] = 27772; lookup[342] = 28013; lookup[343] = 28253; lookup[344] = 28492;
lookup[345] = 28729; lookup[346] = 28964; lookup[347] = 29198; lookup[348] = 29431;
lookup[349] = 29663; lookup[350] = 29893; lookup[351] = 30121; lookup[352] = 30349;
lookup[353] = 30575; lookup[354] = 30800; lookup[355] = 31023; lookup[356] = 31245;
lookup[357] = 31466; lookup[358] = 31685; lookup[359] = 31904; lookup[360] = 32121;
lookup[361] = 32336; lookup[362] = 32551; lookup[363] = 32764; lookup[364] = 32976;
lookup[365] = 33187; lookup[366] = 33397; lookup[367] = 33605; lookup[368] = 33813;
lookup[369] = 34019; lookup[370] = 34224; lookup[371] = 34428; lookup[372] = 34630;
lookup[373] = 34832; lookup[374] = 35032; lookup[375] = 35232; lookup[376] = 35430;
lookup[377] = 35627; lookup[378] = 35823; lookup[379] = 36018; lookup[380] = 36212;
lookup[381] = 36405; lookup[382] = 36597; lookup[383] = 36788; lookup[384] = 36978;
lookup[385] = 37166; lookup[386] = 37354; lookup[387] = 37541; lookup[388] = 37727;
lookup[389] = 37912; lookup[390] = 38095; lookup[391] = 38278; lookup[392] = 38460;
lookup[393] = 38641; lookup[394] = 38821; lookup[395] = 39000; lookup[396] = 39178;
lookup[397] = 39355; lookup[398] = 39532; lookup[399] = 39707; lookup[400] = 39881;
lookup[401] = 40055; lookup[402] = 40228; lookup[403] = 40399; lookup[404] = 40570;
lookup[405] = 40740; lookup[406] = 40909; lookup[407] = 41078; lookup[408] = 41245;
lookup[409] = 41412; lookup[410] = 41577; lookup[411] = 41742; lookup[412] = 41906;
lookup[413] = 42070; lookup[414] = 42232; lookup[415] = 42394; lookup[416] = 42555;
lookup[417] = 42715; lookup[418] = 42874; lookup[419] = 43032; lookup[420] = 43190;
lookup[421] = 43347; lookup[422] = 43503; lookup[423] = 43659; lookup[424] = 43813;
lookup[425] = 43967; lookup[426] = 44120; lookup[427] = 44273; lookup[428] = 44424;
lookup[429] = 44575; lookup[430] = 44726; lookup[431] = 44875; lookup[432] = 45024;
lookup[433] = 45172; lookup[434] = 45319; lookup[435] = 45466; lookup[436] = 45612;
lookup[437] = 45757; lookup[438] = 45902; lookup[439] = 46046; lookup[440] = 46189;
lookup[441] = 46332; lookup[442] = 46474; lookup[443] = 46615; lookup[444] = 46756;
lookup[445] = 46895; lookup[446] = 47035; lookup[447] = 47173; lookup[448] = 47312;
lookup[449] = 47449; lookup[450] = 47586; lookup[451] = 47722; lookup[452] = 47857;
lookup[453] = 47992; lookup[454] = 48127; lookup[455] = 48260; lookup[456] = 48393;
lookup[457] = 48526; lookup[458] = 48658;
end
always @(posedge clk) begin
tmp_a <= lookup[{1'b0, in_a}];
tmp_b <= lookup[{1'b1, in_b}];
end
assign out = tmp_a + tmp_b;
endmodule
module APU(input clk, input ce, input reset,
input [4:0] ADDR, // APU Address Line
input [7:0] DIN, // Data to APU
output [7:0] DOUT, // Data from APU
input MW, // Writes to APU
input MR, // Reads from APU
input [4:0] audio_channels, // Enabled audio channels
output [15:0] Sample,
output DmaReq, // 1 when DMC wants DMA
input DmaAck, // 1 when DMC byte is on DmcData. DmcDmaRequested should go low.
output [15:0] DmaAddr, // Address DMC wants to read
input [7:0] DmaData, // Input data to DMC from memory.
output odd_or_even,
output IRQ); // IRQ asserted
// Which channels are enabled?
reg [3:0] Enabled;
// Output samples from the 4 channels
wire [3:0] Sq1Sample,Sq2Sample,TriSample,NoiSample;
// Output samples from the DMC channel
wire [6:0] DmcSample;
wire DmcIrq;
wire IsDmcActive;
// Generate internal memory write signals
wire ApuMW0 = MW && ADDR[4:2]==0; // SQ1
wire ApuMW1 = MW && ADDR[4:2]==1; // SQ2
wire ApuMW2 = MW && ADDR[4:2]==2; // TRI
wire ApuMW3 = MW && ADDR[4:2]==3; // NOI
wire ApuMW4 = MW && ADDR[4:2]>=4; // DMC
wire ApuMW5 = MW && ADDR[4:2]==5; // Control registers
wire Sq1NonZero, Sq2NonZero, TriNonZero, NoiNonZero;
// Common input to all channels
wire [7:0] LenCtr_In;
LenCtr_Lookup len(DIN[7:3], LenCtr_In);
// Frame sequencer registers
reg FrameSeqMode;
reg [15:0] Cycles;
reg ClkE, ClkL;
reg Wrote4017;
reg [1:0] IrqCtr;
reg InternalClock; // APU Differentiates between Even or Odd clocks
assign odd_or_even = InternalClock;
// Generate each channel
SquareChan Sq1(clk, ce, reset, 0, ADDR[1:0], DIN, ApuMW0, ClkL, ClkE, Enabled[0], LenCtr_In, Sq1Sample, Sq1NonZero);
SquareChan Sq2(clk, ce, reset, 1, ADDR[1:0], DIN, ApuMW1, ClkL, ClkE, Enabled[1], LenCtr_In, Sq2Sample, Sq2NonZero);
TriangleChan Tri(clk, ce, reset, ADDR[1:0], DIN, ApuMW2, ClkL, ClkE, Enabled[2], LenCtr_In, TriSample, TriNonZero);
NoiseChan Noi(clk, ce, reset, ADDR[1:0], DIN, ApuMW3, ClkL, ClkE, Enabled[3], LenCtr_In, NoiSample, NoiNonZero);
DmcChan Dmc(clk, ce, reset, odd_or_even, ADDR[2:0], DIN, ApuMW4, DmcSample, DmaReq, DmaAck, DmaAddr, DmaData, DmcIrq, IsDmcActive);
// Reading this register clears the frame interrupt flag (but not the DMC interrupt flag).
// If an interrupt flag was set at the same moment of the read, it will read back as 1 but it will not be cleared.
reg FrameInterrupt, DisableFrameInterrupt;
//mode 0: 4-step effective rate (approx)
//---------------------------------------
// - - - f 60 Hz
// - l - l 120 Hz
// e e e e 240 Hz
//mode 1: 5-step effective rate (approx)
//---------------------------------------
// - - - - - (interrupt flag never set)
// l - l - - 96 Hz
// e e e e - 192 Hz
always @(posedge clk) if (reset) begin
FrameSeqMode <= 0;
DisableFrameInterrupt <= 0;
FrameInterrupt <= 0;
Enabled <= 0;
InternalClock <= 0;
Wrote4017 <= 0;
ClkE <= 0;
ClkL <= 0;
Cycles <= 4; // This needs to be 5 for proper power up behavior
IrqCtr <= 0;
end else if (ce) begin
FrameInterrupt <= IrqCtr[1] ? 1 : (ADDR == 5'h15 && MR || ApuMW5 && ADDR[1:0] == 3 && DIN[6]) ? 0 : FrameInterrupt;
InternalClock <= !InternalClock;
IrqCtr <= {IrqCtr[0], 1'b0};
Cycles <= Cycles + 1;
ClkE <= 0;
ClkL <= 0;
if (Cycles == 7457) begin
ClkE <= 1;
end else if (Cycles == 14913) begin
ClkE <= 1;
ClkL <= 1;
ClkE <= 1;
ClkL <= 1;
end else if (Cycles == 22371) begin
ClkE <= 1;
end else if (Cycles == 29829) begin
if (!FrameSeqMode) begin
ClkE <= 1;
ClkL <= 1;
Cycles <= 0;
IrqCtr <= 3;
FrameInterrupt <= 1;
end
end else if (Cycles == 37281) begin
ClkE <= 1;
ClkL <= 1;
Cycles <= 0;
end
// Handle one cycle delayed write to 4017.
Wrote4017 <= 0;
if (Wrote4017) begin
if (FrameSeqMode) begin
ClkE <= 1;
ClkL <= 1;
end
Cycles <= 0;
end
// if (ClkE||ClkL) $write("%d: Clocking %s%s\n", Cycles, ClkE?"E":" ", ClkL?"L":" ");
// Handle writes to control registers
if (ApuMW5) begin
case (ADDR[1:0])
1: begin // Register $4015
Enabled <= DIN[3:0];
// $write("$4015 = %X\n", DIN);
end
3: begin // Register $4017
FrameSeqMode <= DIN[7]; // 1 = 5 frames cycle, 0 = 4 frames cycle
DisableFrameInterrupt <= DIN[6];
// If the internal clock is even, things happen
// right away.
if (!InternalClock) begin
if (DIN[7]) begin
ClkE <= 1;
ClkL <= 1;
end
Cycles <= 0;
end
// Otherwise they get delayed one clock
Wrote4017 <= InternalClock;
end
endcase
end
end
ApuLookupTable lookup(clk,
(audio_channels[0] ? {4'b0, Sq1Sample} : 8'b0) +
(audio_channels[1] ? {4'b0, Sq2Sample} : 8'b0),
(audio_channels[2] ? {4'b0, TriSample} + {3'b0, TriSample, 1'b0} : 8'b0) +
(audio_channels[3] ? {3'b0, NoiSample, 1'b0} : 8'b0) +
(audio_channels[4] ? {1'b0, DmcSample} : 8'b0),
Sample);
wire frame_irq = FrameInterrupt && !DisableFrameInterrupt;
// Generate bus output
assign DOUT = {DmcIrq, frame_irq, 1'b0,
IsDmcActive,
NoiNonZero,
TriNonZero,
Sq2NonZero,
Sq1NonZero};
assign IRQ = frame_irq || DmcIrq;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_BEHAVIORAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "Interface_Master_BD_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "Interface_Master_BD_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module Interface_Master_BD_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// File : ../RTL/serialInterfaceEngine/processTxByte.v
// Generated : 11/10/06 05:37:23
// From : ../RTL/serialInterfaceEngine/processTxByte.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// processTxByte
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
input [1:0] JBit;
input [1:0] KBit;
input [7:0] TxByteCtrlIn;
input TxByteFullSpeedRateIn;
input [7:0] TxByteIn;
input USBWireGnt;
input USBWireRdy;
input clk;
input processTxByteWEn;
input rst;
output USBWireCtrl;
output [1:0] USBWireData;
output USBWireFullSpeedRate;
output USBWireReq;
output USBWireWEn;
output processTxByteRdy;
wire [1:0] JBit;
wire [1:0] KBit;
wire [7:0] TxByteCtrlIn;
wire TxByteFullSpeedRateIn;
wire [7:0] TxByteIn;
reg USBWireCtrl, next_USBWireCtrl;
reg [1:0] USBWireData, next_USBWireData;
reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire USBWireGnt;
wire USBWireRdy;
reg USBWireReq, next_USBWireReq;
reg USBWireWEn, next_USBWireWEn;
wire clk;
reg processTxByteRdy, next_processTxByteRdy;
wire processTxByteWEn;
wire rst;
// diagram signals declarations
reg [1:0]TXLineState, next_TXLineState;
reg [3:0]TXOneCount, next_TXOneCount;
reg [7:0]TxByteCtrl, next_TxByteCtrl;
reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
reg [7:0]TxByte, next_TxByte;
reg [3:0]i, next_i;
// BINARY ENCODED state machine: prcTxB
// State codes definitions:
`define START_PTBY 5'b00000
`define PTBY_WAIT_EN 5'b00001
`define SEND_BYTE_UPDATE_BYTE 5'b00010
`define SEND_BYTE_WAIT_RDY 5'b00011
`define SEND_BYTE_CHK 5'b00100
`define SEND_BYTE_BIT_STUFF 5'b00101
`define SEND_BYTE_WAIT_RDY2 5'b00110
`define SEND_BYTE_CHK_FIN 5'b00111
`define PTBY_WAIT_GNT 5'b01000
`define STOP_SND_SE0_2 5'b01001
`define STOP_SND_SE0_1 5'b01010
`define STOP_CHK 5'b01011
`define STOP_SND_J 5'b01100
`define STOP_SND_IDLE 5'b01101
`define STOP_FIN 5'b01110
`define WAIT_RDY_WIRE 5'b01111
`define WAIT_RDY_PKT 5'b10000
`define LS_START_SND_IDLE3 5'b10001
`define LS_START_SND_J1 5'b10010
`define LS_START_SND_IDLE1 5'b10011
`define LS_START_SND_IDLE2 5'b10100
`define LS_START_FIN 5'b10101
`define LS_START_W_RDY1 5'b10110
`define LS_START_W_RDY2 5'b10111
`define LS_START_W_RDY3 5'b11000
`define STOP_W_RDY1 5'b11001
`define STOP_W_RDY2 5'b11010
`define STOP_W_RDY3 5'b11011
`define STOP_W_RDY4 5'b11100
reg [4:0] CurrState_prcTxB;
reg [4:0] NextState_prcTxB;
//--------------------------------------------------------------------
// Machine: prcTxB
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)
begin : prcTxB_NextState
NextState_prcTxB <= CurrState_prcTxB;
// Set default values for outputs and signals
next_processTxByteRdy <= processTxByteRdy;
next_USBWireData <= USBWireData;
next_USBWireCtrl <= USBWireCtrl;
next_USBWireReq <= USBWireReq;
next_USBWireWEn <= USBWireWEn;
next_i <= i;
next_TxByte <= TxByte;
next_TxByteCtrl <= TxByteCtrl;
next_TXLineState <= TXLineState;
next_TXOneCount <= TXOneCount;
next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
case (CurrState_prcTxB)
`START_PTBY:
begin
next_processTxByteRdy <= 1'b0;
next_USBWireData <= 2'b00;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireReq <= 1'b0;
next_USBWireWEn <= 1'b0;
next_i <= 4'h0;
next_TxByte <= 8'h00;
next_TxByteCtrl <= 8'h00;
next_TXLineState <= 2'b0;
next_TXOneCount <= 4'h0;
next_USBWireFullSpeedRate <= 1'b0;
next_TxByteFullSpeedRate <= 1'b0;
NextState_prcTxB <= `PTBY_WAIT_EN;
end
`PTBY_WAIT_EN:
begin
next_processTxByteRdy <= 1'b1;
if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
begin
NextState_prcTxB <= `PTBY_WAIT_GNT;
next_processTxByteRdy <= 1'b0;
next_TxByte <= TxByteIn;
next_TxByteCtrl <= TxByteCtrlIn;
next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
next_TXOneCount <= 4'h0;
next_TXLineState <= JBit;
next_USBWireReq <= 1'b1;
end
else if (processTxByteWEn == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_processTxByteRdy <= 1'b0;
next_TxByte <= TxByteIn;
next_TxByteCtrl <= TxByteCtrlIn;
next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
next_i <= 4'h0;
end
end
`PTBY_WAIT_GNT:
if (USBWireGnt == 1'b1)
NextState_prcTxB <= `WAIT_RDY_WIRE;
`WAIT_RDY_WIRE:
if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
NextState_prcTxB <= `LS_START_SND_IDLE1;
else if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `WAIT_RDY_PKT;
//actively drive the first J bit
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`WAIT_RDY_PKT:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_i <= 4'h0;
end
`SEND_BYTE_UPDATE_BYTE:
begin
next_i <= i + 1'b1;
next_TxByte <= {1'b0, TxByte[7:1] };
if (TxByte[0] == 1'b1) //If this bit is 1, then
next_TXOneCount <= TXOneCount + 1'b1;
//increment 'TXOneCount'
else //else this is a zero bit
begin
next_TXOneCount <= 4'h0;
//reset 'TXOneCount'
if (TXLineState == JBit)
next_TXLineState <= KBit;
//toggle the line state
else
next_TXLineState <= JBit;
end
NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
end
`SEND_BYTE_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_CHK;
next_USBWireWEn <= 1'b1;
next_USBWireData <= TXLineState;
next_USBWireCtrl <= `DRIVE;
end
`SEND_BYTE_CHK:
begin
next_USBWireWEn <= 1'b0;
if (TXOneCount == `MAX_CONSEC_SAME_BITS)
NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
else if (i != 4'h8)
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
else
NextState_prcTxB <= `STOP_CHK;
end
`SEND_BYTE_BIT_STUFF:
begin
next_TXOneCount <= 4'h0;
//reset 'TXOneCount'
if (TXLineState == JBit)
next_TXLineState <= KBit;
//toggle the line state
else
next_TXLineState <= JBit;
NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
end
`SEND_BYTE_WAIT_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
next_USBWireWEn <= 1'b1;
next_USBWireData <= TXLineState;
next_USBWireCtrl <= `DRIVE;
end
`SEND_BYTE_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
if (i == 4'h8)
NextState_prcTxB <= `STOP_CHK;
else
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
end
`STOP_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY2;
end
`STOP_SND_SE0_1:
NextState_prcTxB <= `STOP_W_RDY1;
`STOP_CHK:
if (TxByteCtrl == `DATA_STOP)
NextState_prcTxB <= `STOP_SND_SE0_1;
else if (TxByteCtrl == `DATA_STOP_PRE)
NextState_prcTxB <= `STOP_SND_J;
else
NextState_prcTxB <= `PTBY_WAIT_EN;
`STOP_SND_J:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY3;
end
`STOP_SND_IDLE:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY4;
end
`STOP_FIN:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
//release the wire
NextState_prcTxB <= `PTBY_WAIT_EN;
end
`STOP_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_SE0_2;
next_USBWireWEn <= 1'b1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_J;
next_USBWireWEn <= 1'b1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_IDLE;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY4:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_FIN;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_SND_IDLE3:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY2;
end
`LS_START_SND_J1:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY3;
end
`LS_START_SND_IDLE1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_IDLE2;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_SND_IDLE2:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY1;
end
`LS_START_FIN:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_i <= 4'h0;
end
`LS_START_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_IDLE3;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_J1;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_FIN;
//Drive the first JBit
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prcTxB_CurrentState
if (rst)
CurrState_prcTxB <= `START_PTBY;
else
CurrState_prcTxB <= NextState_prcTxB;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prcTxB_RegOutput
if (rst)
begin
i <= 4'h0;
TxByte <= 8'h00;
TxByteCtrl <= 8'h00;
TXLineState <= 2'b0;
TXOneCount <= 4'h0;
TxByteFullSpeedRate <= 1'b0;
processTxByteRdy <= 1'b0;
USBWireData <= 2'b00;
USBWireCtrl <= `TRI_STATE;
USBWireReq <= 1'b0;
USBWireWEn <= 1'b0;
USBWireFullSpeedRate <= 1'b0;
end
else
begin
i <= next_i;
TxByte <= next_TxByte;
TxByteCtrl <= next_TxByteCtrl;
TXLineState <= next_TXLineState;
TXOneCount <= next_TXOneCount;
TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
processTxByteRdy <= next_processTxByteRdy;
USBWireData <= next_USBWireData;
USBWireCtrl <= next_USBWireCtrl;
USBWireReq <= next_USBWireReq;
USBWireWEn <= next_USBWireWEn;
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
end
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lcd (
// inputs:
address,
begintransfer,
clk,
read,
reset_n,
write,
writedata,
// outputs:
LCD_E,
LCD_RS,
LCD_RW,
LCD_data,
readdata
)
;
output LCD_E;
output LCD_RS;
output LCD_RW;
inout [ 7: 0] LCD_data;
output [ 7: 0] readdata;
input [ 1: 0] address;
input begintransfer;
input clk;
input read;
input reset_n;
input write;
input [ 7: 0] writedata;
wire LCD_E;
wire LCD_RS;
wire LCD_RW;
wire [ 7: 0] LCD_data;
wire [ 7: 0] readdata;
assign LCD_RW = address[0];
assign LCD_RS = address[1];
assign LCD_E = read | write;
assign LCD_data = (address[0]) ? 8'bz : writedata;
assign readdata = LCD_data;
//control_slave, which is an e_avalon_slave
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler, Nick Desaulniers
//
// Create Date: 11:20:40 04/07/2011
// Design Name: control_unit
// Module Name: control_unit
// Project Name: omicron
// Target Devices: Xilinx Spartan-3E
// Tool versions:
// Description: The control unit of the cpu pipeline
//
// Revision:
// Revision 0.01 - File Created
// Revision 1.00 - Added cu_branch (CRC)
// Revision 2.00 - Stubbed out control_unit, needs substance (CRC)
// Revision 3.00 - Extended Branch bits (01 branch, 10 jump, 00 no branch, 11 should not occur)
// - Fixed id_opcode switch
// - Modified cu_alu_opcode length
// - Filled in output signals
// - Added SUB alu opcode for branch instructions
// Revision 4.00 - Removed cu_reg_dest (CRC)
// Revision 5.00 - Changed LD and STR instructions to use the CPY opcode (CRC)
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module control_unit(
input clk,
input rst_n,
input [3:0] id_opcode,
output reg cu_reg_load, // RegLd
output reg cu_alu_sel_b, // AluSelB
output reg [10:0] cu_alu_opcode, // AluCtrl
output reg cu_dm_wea, // MemWr
output reg cu_reg_data_loc, // AluOrMem
output reg [1:0] cu_branch // Branch
);
// Instruction opcodes
parameter NOOP_i = 4'b0000;
parameter CPY_i = 4'b0001;
parameter ADD_i = 4'b0010;
parameter SUB_i = 4'b0011;
parameter MUL_i = 4'b0100;
parameter AND_i = 4'b0101;
parameter OR_i = 4'b0110;
parameter NOT_i = 4'b0111;
parameter XOR_i = 4'b1000;
parameter LS_i = 4'b1001;
parameter RS_i = 4'b1010;
parameter BEQ_i = 4'b1011;
parameter BNE_i = 4'b1100;
parameter LD_i = 4'b1101;
parameter STR_i = 4'b1110;
parameter JMP_i = 4'b1111;
// ALU opcodes
parameter NOOP = 11'b00000000001;
parameter CPY = 11'b00000000010;
parameter ADD = 11'b00000000100;
parameter SUB = 11'b00000001000;
parameter MUL = 11'b00000010000;
parameter AND = 11'b00000100000;
parameter OR = 11'b00001000000;
parameter NOT = 11'b00010000000;
parameter XOR = 11'b00100000000;
parameter LS = 11'b01000000000;
parameter RS = 11'b10000000000;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cu_alu_opcode <= NOOP;
cu_reg_load <= 1'b0;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end else begin
case(id_opcode)
NOOP_i: begin
cu_alu_opcode <= NOOP;
cu_reg_load <= 1'b0;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
CPY_i: begin
cu_alu_opcode <= CPY;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
ADD_i: begin
cu_alu_opcode <= ADD;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
SUB_i: begin
cu_alu_opcode <= SUB;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
MUL_i: begin
cu_alu_opcode <= MUL;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
AND_i: begin
cu_alu_opcode <= AND;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
OR_i: begin
cu_alu_opcode <= OR;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
NOT_i: begin
cu_alu_opcode <= NOT;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
XOR_i: begin
cu_alu_opcode <= XOR;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
LS_i: begin
cu_alu_opcode <= LS;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
RS_i: begin
cu_alu_opcode <= RS;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
BEQ_i: begin
cu_alu_opcode <= SUB;
cu_reg_load <= 1'b0;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b01;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
BNE_i: begin
cu_alu_opcode <= SUB;
cu_reg_load <= 1'b0;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b10;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
LD_i: begin
cu_alu_opcode <= CPY;
cu_reg_load <= 1'b1;
cu_reg_data_loc <= 1'b1;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b1;
end
STR_i: begin
cu_alu_opcode <= CPY;
cu_reg_load <= 1'b0;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b00;
cu_dm_wea <= 1'b1;
cu_alu_sel_b <= 1'b1;
end
JMP_i: begin
cu_alu_opcode <= NOOP;
cu_reg_load <= 1'b0;
cu_reg_data_loc <= 1'b0;
cu_branch <= 2'b11;
cu_dm_wea <= 1'b0;
cu_alu_sel_b <= 1'b0;
end
endcase
end
end
endmodule
|
/*
* Testbench for Zet processor
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module test_zet;
// Net declarations
wire [15:0] dat_o;
wire [15:0] mem_dat_i, io_dat_i, dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack, mem_ack, io_ack;
wire inta;
wire [19:0] pc;
reg clk;
reg rst;
reg [15:0] io_reg;
reg intr;
// Wishbone master interface - fetch
wire [15:0] wbf_dat_i;
wire [19:1] wbf_adr_o;
wire [ 1:0] wbf_sel_o;
wire wbf_cyc_o;
wire wbf_stb_o;
wire wbf_ack_i;
// Module instantiations
memory2prt mem0 (
.wb1_clk_i (clk),
.wb1_dat_o(wbf_dat_i),
.wb1_adr_i(wbf_adr_o),
.wb1_sel_i(wbf_sel_o),
.wb1_cyc_i(wbf_cyc_o),
.wb1_stb_i(wbf_stb_o),
.wb1_ack_o(wbf_ack_i),
.wb2_clk_i (clk),
.wb2_rst_i (rst),
.wb2_dat_i (dat_o),
.wb2_dat_o (mem_dat_i),
.wb2_adr_i (adr),
.wb2_we_i (we),
.wb2_sel_i (sel),
.wb2_stb_i (stb & !tga),
.wb2_cyc_i (cyc & !tga),
.wb2_ack_o (mem_ack)
);
zet zet (
.clk_i (clk),
.rst_i (rst),
// Wishbone master interface - fetch
.wbf_dat_i(wbf_dat_i),
.wbf_adr_o(wbf_adr_o),
.wbf_sel_o(wbf_sel_o),
.wbf_cyc_o(wbf_cyc_o),
.wbf_stb_o(wbf_stb_o),
.wbf_ack_i(wbf_ack_i),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.intr (1'b0),
.inta (inta),
.iid (4'h0),
.pc (pc)
);
// Assignments
assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }
: ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);
assign dat_i = inta ? 16'd3 : (tga ? io_dat_i : mem_dat_i);
assign ack = tga ? io_ack : mem_ack;
assign io_ack = stb;
// Behaviour
// IO Stub
always @(posedge clk)
if (adr[15:1]==15'h5b && sel[1] && cyc && stb)
io_reg[7:0] <= dat_o[15:8];
else if (adr[15:1]==15'h5c & sel[0] && cyc && stb)
io_reg[15:8] <= dat_o[7:0];
always #1.5 clk = ~clk;
initial
begin
intr <= 1'b0;
clk <= 1'b1;
rst <= 1'b0;
#5 rst <= 1'b1;
#2 rst <= 1'b0;
#1000 intr <= 1'b1;
//@(posedge inta)
@(posedge clk) intr <= 1'b0;
end
initial
begin
$readmemh("data.rtlrom", mem0.ram1, 19'h78000);
$readmemh("data.rtlrom", mem0.ram2, 19'h78000);
// $readmemb("../rtl/micro_rom.dat",
// zet.core.micro_data.micro_rom.rom);
end
endmodule
|
// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is Agnus
// The copper, blitter and sprite dma have a reqdma output and an ackdma input
// if they are ready for dma they do a dma request by asserting reqdma
// the dma priority logic circuit then checks which module is granted access by
// looking at their priorities and asserting the ackdma signal of the module that
// has the highest priority
//
// Other dma channels (bitplane, audio and disk) only have an enable input (bitplane)
// or only a dma request input from Paula (dmal input, disk and audio)
// and an dma output to indicate that they are using their slot.
// this is because they have the highest priority in the system and cannot be hold up
//
// The bus clock runs at 7.09MHz which is twice as fast as in the original amiga and
// the same as the pixel clock / horizontal beam counter.
//
// general cycle allocation is as follows:
// (lowest 2 bits of horizontal beam counter)
//
// slot 0: 68000 (priority in that order, extra slots because of higher bus speed)
// slot 1: disk, bitplanes, copper, blitter and 68000 (priority in that order)
// slot 2: blitter and 68000 (priority in that order, extra slots because of higher bus speed)
// slot 3: disk, bitplanes, sprites, audio and 68000 (priority in that order)
//
// because only the odd slots are used by the chipset, the chipset runs at the same
// virtual speed as the original. The cpu gets the extra even slots allowing for
// faster cpu's without the need for an extra fastram controller
// Blitter timing is not completely accurate, it uses slot 1 and 2 instead of 1 and 3, this is to let
// the blitter not slow down too much dma contention. (most compatible solution for now)
// Blitter nasty mode activates the buspri signal to indicate to gary to stop access to the chipram/chipregisters.
// Blitter nasty mode is only activated if blitter activates bltpri cause it depends on blitter settings if blitter
// will really block the cpu.
//
module agnus
(
input clk, // clock
input clk7_en, // 28MHz clock
input cck, // colour clock enable, active whenever hpos[0] is high (odd dma slots used by chipset)
input reset, // reset
input aen, // bus adress enable (register bank)
input rd, // bus read
input hwr, // bus high write
input lwr, // bus low write
input [15:0] data_in, // data bus in
output [15:0] data_out, // data bus out
input [8:1] address_in, // 256 words (512 bytes) adress input,
output reg [20:1] address_out, // chip address output,
output [8:1] reg_address_out, // 256 words (512 bytes) register address out,
output reg cpu_custom, // CPU has access to custom chipset (registers and chipRAM / slowRAM)
output reg dbr, // agnus requests data bus
output reg dbwe, // agnus does a memory write cycle (only disk and blitter dma channels may do this)
output _hsync, // horizontal sync
output _vsync, // vertical sync
output _csync, // composite sync
output blank, // video blanking
output sol, // start of video line (active during last pixel of previous line)
output sof, // start of video frame (active during last pixel of previous frame)
output vbl_int, // vertical blanking interrupt request for Paula
output strhor_denise, // horizontal strobe for Denise (due to not cycle exact implementation of Denise it must be delayed by one CCK)
output strhor_paula, // horizontal strobe for Paula
output [8:0] htotal, // video line length
output harddis,
output varbeamen,
output int3, // blitter finished interrupt (to Paula)
input [3:0] audio_dmal, // audio dma data transfer request (from Paula)
input [3:0] audio_dmas, // audio dma location pointer restart (from Paula)
input disk_dmal, // disk dma data transfer request (from Paula)
input disk_dmas, // disk dma special request (from Paula)
input bls, // blitter slowdown
input ntsc, // chip is NTSC
input a1k, // enable A1000 OCS features
input ecs, // enable ECS features
input aga, // enables AGA features
input floppy_speed, // allocates refresh slots for disk DMA
input turbo // alows blitter to take extra DMA slots
);
//register names and adresses
localparam DMACON = 9'h096;
localparam DMACONR = 9'h002;
localparam DIWSTRT = 9'h08e;
localparam DIWSTOP = 9'h090;
localparam DIWHIGH = 9'h1E4;
//local signals
reg [15:0] dmaconr; //dma control read register
wire [8:0] hpos; //alternative horizontal beam counter
wire [10:0] vpos; //vertical beam counter
wire vbl; ///JB: vertical blanking
wire vblend; ///JB: last line of vertical blanking
wire blit_busy; //blitter busy status
wire blit_zero; //blitter zero status
wire bltpri; //blitter nasty
wire bplen; //bitplane dma enable
wire copen; //copper dma enable
wire blten; //blitter dma enable
wire spren; //sprite dma enable
wire dma_ref; //refresh dma slots
wire dma_dsk; //disk dma uses its slot
wire dma_aud; //audio dma uses its slot
wire req_spr; //sprite dma request
reg ack_spr; //sprite dma acknowledge
wire dma_spr; //sprite dma is using its slot
wire dma_bpl; //bitplane dma engine uses it's slot
wire ena_cop; //enables copper (no higher priority dma requests)
wire req_cop; //copper dma request
reg ack_cop; //copper dma acknowledge
wire dma_cop; //copper dma is using its slot
wire ena_blt; //enables blitter (no higher priority dma requests)
wire req_blt; //blitter dma request
reg ack_blt; //blitter dma acknowledge
wire dma_blt; //blitter dma is using its slot
wire [15:0] data_bmc; //beam counter data out
wire [20:1] address_dsk; //disk dma engine chip address out
wire [8:1] reg_address_dsk; //disk dma engine register address out
wire wr_dsk; //disk dma engine write enable out
wire [20:1] address_aud; //audio dma engine chip address out
wire [8:1] reg_address_aud; //audio dma engine register address out
wire [20:1] address_bpl; //bitplane dma engine chip address out
wire [8:1] reg_address_bpl; //bitplane dma engine register address out
wire [20:1] address_spr; //sprite dma engine chip address out
wire [8:1] reg_address_spr; //sprite dma engine register address out
wire [20:1] address_cop; //copper dma engine chip address out
wire [8:1] reg_address_cop; //copper dma engine register address out
wire [20:1] address_blt; //blitter dma engine chip address out
wire [8:1] reg_address_blt; //blitter dma engine register address out
wire [15:0] data_blt; //blitter dma engine data out
wire we_blt; //blitter dma engine write enable out
wire [8:1] reg_address_cpu; //cpu register address
reg [8:1] reg_address; //local register address bus
reg [1:0] bls_cnt; //blitter slowdown counter, counts memory cycles when the CPU misses the bus
parameter BLS_CNT_MAX = 3; //when CPU misses the bus for 3 consecutive memory cycles the blitter is blocked until CPU accesses the bus
//--------------------------------------------------------------------------------------
//register address bus output
assign reg_address_out = reg_address;
//data out multiplexer
assign data_out = data_bmc | dmaconr | data_blt;
//cpu address decoder
assign reg_address_cpu = (aen&(rd|hwr|lwr)) ? address_in : 8'hFF;
//--------------------------------------------------------------------------------------
assign dma_spr = req_spr & spren;
assign dma_cop = req_cop & copen;
assign dma_blt = req_blt & blten;
//chip address, register address and control signal multiplexer
//AND dma priority handler
//first item in this if else if list has highest priority
always @(*)
begin
if (dma_dsk) begin
// bus allocated to disk dma engine
cpu_custom = 0;
dbr = 1;
ack_cop = 0;
ack_blt = 0;
ack_spr = 0;
address_out = address_dsk;
reg_address = reg_address_dsk;
dbwe = wr_dsk;
end else if (dma_ref) begin
// bus allocated to refresh dma engine
cpu_custom = 0;
dbr = 1;
ack_cop = 0;
ack_blt = 0;
ack_spr = 0;
address_out = 0;
reg_address = 8'hFF;
dbwe = 0;
end else if (dma_aud) begin
// bus allocated to audio dma engine
cpu_custom = 0;
dbr = 1;
ack_cop = 0;
ack_blt = 0;
ack_spr = 0;
address_out = address_aud;
reg_address = reg_address_aud;
dbwe = 0;
end else if (dma_bpl) begin
// bus allocated to bitplane dma engine
cpu_custom = 0;
dbr = 1;
ack_cop = 0;
ack_blt = 0;
ack_spr = 0;
address_out = address_bpl;
reg_address = reg_address_bpl;
dbwe = 0;
end else if (dma_spr) begin
// bus allocated to sprite dma engine
cpu_custom = 0;
dbr = 1;
ack_cop = 0;
ack_blt = 0;
ack_spr = 1;
address_out = address_spr;
reg_address = reg_address_spr;
dbwe = 0;
end else if (dma_cop) begin
// bus allocated to copper
cpu_custom = 0;
dbr = 1;
ack_cop = 1;
ack_blt = 0;
ack_spr = 0;
address_out = address_cop;
reg_address = reg_address_cop;
dbwe = 0;
end else if (dma_blt && bls_cnt!=BLS_CNT_MAX) begin
// bus allocated to blitter
cpu_custom = 0;
dbr = 1;
ack_cop = 0;
ack_blt = 1;
ack_spr = 0;
address_out = address_blt;
reg_address = reg_address_blt;
dbwe = we_blt;
end else begin
// bus not allocated by agnus
cpu_custom = 1;
dbr = 0;
ack_cop = 0;
ack_blt = 0;
ack_spr = 0;
address_out = 0;
reg_address = reg_address_cpu; // pass register addresses from cpu address bus
dbwe = 0;
end
end
//--------------------------------------------------------------------------------------
reg [12:0] dmacon;
//dma control register read
always @(*)
if (reg_address[8:1]==DMACONR[8:1])
dmaconr[15:0] <= {1'b0, blit_busy, blit_zero, dmacon[12:0]};
else
dmaconr <= 0;
//dma control register write
always @(posedge clk)
if (clk7_en) begin
if (reset)
dmacon <= 0;
else if (reg_address[8:1]==DMACON[8:1])
begin
if (data_in[15])
dmacon[12:0] <= dmacon[12:0] | data_in[12:0];
else
dmacon[12:0] <= dmacon[12:0] & ~data_in[12:0];
end
end
//assign dma enable bits
assign bltpri = dmacon[10];
assign bplen = dmacon[8] & dmacon[9];
assign copen = dmacon[7] & dmacon[9];
assign blten = dmacon[6] & dmacon[9];
assign spren = dmacon[5] & dmacon[9];
//copper dma is enabled only when any higher priority dma channel is inactive
//copper uses dma slots which can be optionally assigned only to bitplane dma (also to blitter but it has lower priority than copper)
//it is ok to generate this signal form bitplane dma signal only
assign ena_cop = ~dma_bpl;
//dma enable for blitter tells the blitter that no higher priority dma channel is using the bus
//since blitter has the lowest priority and can use any dma slot (even and odd) all other dma channels block blitter activity
assign ena_blt = ~(dma_ref | dma_dsk | dma_aud | dma_spr | dma_bpl | dma_cop) && bls_cnt!=BLS_CNT_MAX ? 1'b1 : 1'b0;
//--------------------------------------------------------------------------------------
agnus_refresh ref1
(
.hpos(hpos),
.dma(dma_ref)
);
//instantiate disk dma engine
agnus_diskdma dsk1
(
.clk(clk),
.clk7_en(clk7_en),
.dma(dma_dsk),
.dmal(disk_dmal),
.dmas(disk_dmas),
.speed(floppy_speed),
.turbo(turbo),
.hpos(hpos),
.wr(wr_dsk),
.reg_address_in(reg_address),
.reg_address_out(reg_address_dsk),
.data_in(data_in),
.address_out(address_dsk)
);
//--------------------------------------------------------------------------------------
//instantiate audio dma engine
agnus_audiodma aud1
(
.clk(clk),
.clk7_en(clk7_en),
.dma(dma_aud),
.audio_dmal(audio_dmal),
.audio_dmas(audio_dmas),
.hpos(hpos),
.reg_address_in(reg_address),
.reg_address_out(reg_address_aud),
.data_in(data_in),
.address_out(address_aud)
);
//--------------------------------------------------------------------------------------
//instantiate bitplane dma
agnus_bitplanedma bpd1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(reset),
.harddis(harddis),
.aga(aga),
.ecs(ecs),
.a1k(a1k),
.sof(sof),
.dmaena(bplen),
.vpos(vpos),
.hpos(hpos),
.dma(dma_bpl),
.reg_address_in(reg_address),
.reg_address_out(reg_address_bpl),
.data_in(data_in),
.address_out(address_bpl)
);
//--------------------------------------------------------------------------------------
//instantiate sprite dma engine
agnus_spritedma spr1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(reset),
.aga(aga),
.ecs(ecs),
.reqdma(req_spr),
.ackdma(ack_spr),
.hpos(hpos),
.vpos(vpos),
.vbl(vbl),
.vblend(vblend),
.reg_address_in(reg_address),
.reg_address_out(reg_address_spr),
.data_in(data_in),
.address_out(address_spr)
);
//--------------------------------------------------------------------------------------
//instantiate copper
agnus_copper cp1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(reset),
.ecs(ecs),
.reqdma(req_cop),
.ackdma(ack_cop),
.enadma(ena_cop),
.sof(sof),
.blit_busy(blit_busy),
.vpos(vpos[7:0]),
.hpos(hpos),
.data_in(data_in),
.reg_address_in(reg_address),
.reg_address_out(reg_address_cop),
.address_out(address_cop)
);
//--------------------------------------------------------------------------------------
always @(posedge clk)
if (clk7_en) begin
if (!cck || turbo)
if (!bls || bltpri)
bls_cnt <= 2'b00;
else if (bls_cnt[1:0] != BLS_CNT_MAX)
bls_cnt <= bls_cnt + 2'b01;
end
//instantiate blitter
agnus_blitter bl1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(reset),
.ecs(ecs),
.clkena(cck | turbo),
.enadma(blten & ena_blt),
.reqdma(req_blt),
.ackdma(ack_blt),
.we(we_blt),
.zero(blit_zero),
.busy(blit_busy),
.int3(int3),
.data_in(data_in),
.data_out(data_blt),
.reg_address_in(reg_address),
.address_out(address_blt),
.reg_address_out(reg_address_blt)
);
//--------------------------------------------------------------------------------------
//instantiate beam counters
agnus_beamcounter bc1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(reset),
.cck(cck),
.ntsc(ntsc),
.aga(aga),
.ecs(ecs),
.a1k(a1k),
.reg_address_in(reg_address),
.data_in(data_in),
.data_out(data_bmc),
.hpos(hpos),
.vpos(vpos),
._hsync(_hsync),
._vsync(_vsync),
._csync(_csync),
.blank(blank),
.vbl(vbl),
.vblend(vblend),
.eol(sol),
.eof(sof),
.vbl_int(vbl_int),
.htotal_out(htotal),
.harddis_out(harddis),
.varbeamen_out(varbeamen)
);
//horizontal strobe for Denise
//in real Amiga Denise's hpos counter seems to be advanced by 4 CCKs in regards to Agnus' one
//Minimig isn't cycle exact and compensation for different data delay in implemented Denise's video pipeline is required
assign strhor_denise = hpos==(6*2-1) && (vpos > 8 || ecs) ? 1'b1 : 1'b0;
assign strhor_paula = hpos==(6*2+1) ? 1'b1 : 1'b0; //hack
//--------------------------------------------------------------------------------------
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_top.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core top level. ////
//// ////
//// Known problems (limits): ////
//// Note that transmitter and receiver instances are inside ////
//// the uart_regs.v file. ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.17 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.16 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.15 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.14 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/08/25 15:46:19 gorban
// Modified port names again
//
// Revision 1.11 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.10 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_top (
print_data_o, //data signal
tf_push_o, //control sinnal
/////////////////////////////////////////////////
wb_clk_i,
// Wishbone signals
wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
int_o, // interrupt request
// UART signals
// serial input/output
stx_pad_o, srx_pad_i,
// modem signals
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
parameter uart_data_width = `UART_DATA_WIDTH;
parameter uart_addr_width = `UART_ADDR_WIDTH;
output [7:0] print_data_o;
assign print_data_o = wb_dat8_i;
output tf_push_o;
input wb_clk_i;
// WISHBONE interface
input wb_rst_i;
input [uart_addr_width-1:0] wb_adr_i;
input [uart_data_width-1:0] wb_dat_i;
output [uart_data_width-1:0] wb_dat_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output wb_ack_o;
output int_o;
// UART signals
input srx_pad_i;
output stx_pad_o;
output rts_pad_o;
input cts_pad_i;
output dtr_pad_o;
input dsr_pad_i;
input ri_pad_i;
input dcd_pad_i;
// optional baudrate output
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
wire stx_pad_o;
wire rts_pad_o;
wire dtr_pad_o;
wire [uart_addr_width-1:0] wb_adr_i;
wire [uart_data_width-1:0] wb_dat_i;
wire [uart_data_width-1:0] wb_dat_o;
wire [7:0] wb_dat8_i; // 8-bit internal data input
wire [7:0] wb_dat8_o; // 8-bit internal data output
wire [31:0] wb_dat32_o; // debug interface 32-bit output
wire [3:0] wb_sel_i; // WISHBONE select signal
wire [uart_addr_width-1:0] wb_adr_int;
wire we_o; // Write enable for registers
wire re_o; // Read enable for registers
//
// MODULE INSTANCES
//
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface wires
wire [3:0] ier;
wire [3:0] iir;
wire [1:0] fcr;
wire [4:0] mcr;
wire [7:0] lcr;
wire [7:0] msr;
wire [7:0] lsr;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
`endif
`ifdef DATA_BUS_WIDTH_8
//// WISHBONE interface module
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_dat32_o(32'b0),
.wb_sel_i(4'b0),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
`else
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_sel_i(wb_sel_i),
.wb_dat32_o(wb_dat32_o),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
`endif
// Registers
uart_regs regs(
.tf_push_o(tf_push_o),
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_addr_i( wb_adr_int ),
.wb_dat_i( wb_dat8_i ),
.wb_dat_o( wb_dat8_o ),
.wb_we_i( we_o ),
.wb_re_i(re_o),
.modem_inputs( {cts_pad_i, dsr_pad_i,
ri_pad_i, dcd_pad_i} ),
.stx_pad_o( stx_pad_o ),
.srx_pad_i( srx_pad_i ),
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals enabled
.ier(ier),
.iir(iir),
.fcr(fcr),
.mcr(mcr),
.lcr(lcr),
.msr(msr),
.lsr(lsr),
.rf_count(rf_count),
.tf_count(tf_count),
.tstate(tstate),
.rstate(rstate),
`endif
.rts_pad_o( rts_pad_o ),
.dtr_pad_o( dtr_pad_o ),
.int_o( int_o )
`ifdef UART_HAS_BAUDRATE_OUTPUT
, .baud_o(baud_o)
`endif
);
`ifdef DATA_BUS_WIDTH_8
`else
uart_debug_if dbg(/*AUTOINST*/
// Outputs
.wb_dat32_o (wb_dat32_o[31:0]),
// Inputs
.wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
.ier (ier[3:0]),
.iir (iir[3:0]),
.fcr (fcr[1:0]),
.mcr (mcr[4:0]),
.lcr (lcr[7:0]),
.msr (msr[7:0]),
.lsr (lsr[7:0]),
.rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]),
.tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]),
.tstate (tstate[2:0]),
.rstate (rstate[3:0]));
`endif
initial
begin
`ifdef DATA_BUS_WIDTH_8
$display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");
`else
$display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n");
`endif
`ifdef UART_HAS_BAUDRATE_OUTPUT
$display("(%m) UART INFO: Has baudrate output\n");
`else
$display("(%m) UART INFO: Doesn't have baudrate output\n");
`endif
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_PP_V |
module system (
clk_50_clk,
kernel_clk_clk,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
peripheral_hps_io_emac1_inst_TX_CLK,
peripheral_hps_io_emac1_inst_TXD0,
peripheral_hps_io_emac1_inst_TXD1,
peripheral_hps_io_emac1_inst_TXD2,
peripheral_hps_io_emac1_inst_TXD3,
peripheral_hps_io_emac1_inst_RXD0,
peripheral_hps_io_emac1_inst_MDIO,
peripheral_hps_io_emac1_inst_MDC,
peripheral_hps_io_emac1_inst_RX_CTL,
peripheral_hps_io_emac1_inst_TX_CTL,
peripheral_hps_io_emac1_inst_RX_CLK,
peripheral_hps_io_emac1_inst_RXD1,
peripheral_hps_io_emac1_inst_RXD2,
peripheral_hps_io_emac1_inst_RXD3,
peripheral_hps_io_sdio_inst_CMD,
peripheral_hps_io_sdio_inst_D0,
peripheral_hps_io_sdio_inst_D1,
peripheral_hps_io_sdio_inst_CLK,
peripheral_hps_io_sdio_inst_D2,
peripheral_hps_io_sdio_inst_D3,
peripheral_hps_io_usb1_inst_D0,
peripheral_hps_io_usb1_inst_D1,
peripheral_hps_io_usb1_inst_D2,
peripheral_hps_io_usb1_inst_D3,
peripheral_hps_io_usb1_inst_D4,
peripheral_hps_io_usb1_inst_D5,
peripheral_hps_io_usb1_inst_D6,
peripheral_hps_io_usb1_inst_D7,
peripheral_hps_io_usb1_inst_CLK,
peripheral_hps_io_usb1_inst_STP,
peripheral_hps_io_usb1_inst_DIR,
peripheral_hps_io_usb1_inst_NXT,
peripheral_hps_io_uart0_inst_RX,
peripheral_hps_io_uart0_inst_TX,
peripheral_hps_io_i2c1_inst_SDA,
peripheral_hps_io_i2c1_inst_SCL,
peripheral_hps_io_gpio_inst_GPIO53,
reset_50_reset_n,
acl_iface_alt_vip_itc_0_clocked_video_vid_clk,
acl_iface_alt_vip_itc_0_clocked_video_vid_data,
acl_iface_alt_vip_itc_0_clocked_video_underflow,
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid,
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync,
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync,
acl_iface_alt_vip_itc_0_clocked_video_vid_f,
acl_iface_alt_vip_itc_0_clocked_video_vid_h,
acl_iface_alt_vip_itc_0_clocked_video_vid_v,
acl_iface_clock_130_clk);
input clk_50_clk;
output kernel_clk_clk;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
output peripheral_hps_io_emac1_inst_TX_CLK;
output peripheral_hps_io_emac1_inst_TXD0;
output peripheral_hps_io_emac1_inst_TXD1;
output peripheral_hps_io_emac1_inst_TXD2;
output peripheral_hps_io_emac1_inst_TXD3;
input peripheral_hps_io_emac1_inst_RXD0;
inout peripheral_hps_io_emac1_inst_MDIO;
output peripheral_hps_io_emac1_inst_MDC;
input peripheral_hps_io_emac1_inst_RX_CTL;
output peripheral_hps_io_emac1_inst_TX_CTL;
input peripheral_hps_io_emac1_inst_RX_CLK;
input peripheral_hps_io_emac1_inst_RXD1;
input peripheral_hps_io_emac1_inst_RXD2;
input peripheral_hps_io_emac1_inst_RXD3;
inout peripheral_hps_io_sdio_inst_CMD;
inout peripheral_hps_io_sdio_inst_D0;
inout peripheral_hps_io_sdio_inst_D1;
output peripheral_hps_io_sdio_inst_CLK;
inout peripheral_hps_io_sdio_inst_D2;
inout peripheral_hps_io_sdio_inst_D3;
inout peripheral_hps_io_usb1_inst_D0;
inout peripheral_hps_io_usb1_inst_D1;
inout peripheral_hps_io_usb1_inst_D2;
inout peripheral_hps_io_usb1_inst_D3;
inout peripheral_hps_io_usb1_inst_D4;
inout peripheral_hps_io_usb1_inst_D5;
inout peripheral_hps_io_usb1_inst_D6;
inout peripheral_hps_io_usb1_inst_D7;
input peripheral_hps_io_usb1_inst_CLK;
output peripheral_hps_io_usb1_inst_STP;
input peripheral_hps_io_usb1_inst_DIR;
input peripheral_hps_io_usb1_inst_NXT;
input peripheral_hps_io_uart0_inst_RX;
output peripheral_hps_io_uart0_inst_TX;
inout peripheral_hps_io_i2c1_inst_SDA;
inout peripheral_hps_io_i2c1_inst_SCL;
inout peripheral_hps_io_gpio_inst_GPIO53;
input reset_50_reset_n;
input acl_iface_alt_vip_itc_0_clocked_video_vid_clk;
output [31:0] acl_iface_alt_vip_itc_0_clocked_video_vid_data;
output acl_iface_alt_vip_itc_0_clocked_video_underflow;
output acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid;
output acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync;
output acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync;
output acl_iface_alt_vip_itc_0_clocked_video_vid_f;
output acl_iface_alt_vip_itc_0_clocked_video_vid_h;
output acl_iface_alt_vip_itc_0_clocked_video_vid_v;
input acl_iface_clock_130_clk;
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Tue Apr 25 09:03:37 2017
//Host : WK115 running 64-bit major release (build 9200)
//Command : generate_target PmodAMP2.bd
//Design : PmodAMP2
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "PmodAMP2,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=PmodAMP2,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=6,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,synth_mode=Global}" *) (* HW_HANDOFF = "PmodAMP2.hwdef" *)
module PmodAMP2
(AXI_LITE_GPIO_araddr,
AXI_LITE_GPIO_arready,
AXI_LITE_GPIO_arvalid,
AXI_LITE_GPIO_awaddr,
AXI_LITE_GPIO_awready,
AXI_LITE_GPIO_awvalid,
AXI_LITE_GPIO_bready,
AXI_LITE_GPIO_bresp,
AXI_LITE_GPIO_bvalid,
AXI_LITE_GPIO_rdata,
AXI_LITE_GPIO_rready,
AXI_LITE_GPIO_rresp,
AXI_LITE_GPIO_rvalid,
AXI_LITE_GPIO_wdata,
AXI_LITE_GPIO_wready,
AXI_LITE_GPIO_wstrb,
AXI_LITE_GPIO_wvalid,
AXI_LITE_PWM_araddr,
AXI_LITE_PWM_arprot,
AXI_LITE_PWM_arready,
AXI_LITE_PWM_arvalid,
AXI_LITE_PWM_awaddr,
AXI_LITE_PWM_awprot,
AXI_LITE_PWM_awready,
AXI_LITE_PWM_awvalid,
AXI_LITE_PWM_bready,
AXI_LITE_PWM_bresp,
AXI_LITE_PWM_bvalid,
AXI_LITE_PWM_rdata,
AXI_LITE_PWM_rready,
AXI_LITE_PWM_rresp,
AXI_LITE_PWM_rvalid,
AXI_LITE_PWM_wdata,
AXI_LITE_PWM_wready,
AXI_LITE_PWM_wstrb,
AXI_LITE_PWM_wvalid,
AXI_LITE_TIMER_araddr,
AXI_LITE_TIMER_arready,
AXI_LITE_TIMER_arvalid,
AXI_LITE_TIMER_awaddr,
AXI_LITE_TIMER_awready,
AXI_LITE_TIMER_awvalid,
AXI_LITE_TIMER_bready,
AXI_LITE_TIMER_bresp,
AXI_LITE_TIMER_bvalid,
AXI_LITE_TIMER_rdata,
AXI_LITE_TIMER_rready,
AXI_LITE_TIMER_rresp,
AXI_LITE_TIMER_rvalid,
AXI_LITE_TIMER_wdata,
AXI_LITE_TIMER_wready,
AXI_LITE_TIMER_wstrb,
AXI_LITE_TIMER_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
s_axi_aclk,
s_axi_aresetn,
timer_interrupt);
input [8:0]AXI_LITE_GPIO_araddr;
output AXI_LITE_GPIO_arready;
input AXI_LITE_GPIO_arvalid;
input [8:0]AXI_LITE_GPIO_awaddr;
output AXI_LITE_GPIO_awready;
input AXI_LITE_GPIO_awvalid;
input AXI_LITE_GPIO_bready;
output [1:0]AXI_LITE_GPIO_bresp;
output AXI_LITE_GPIO_bvalid;
output [31:0]AXI_LITE_GPIO_rdata;
input AXI_LITE_GPIO_rready;
output [1:0]AXI_LITE_GPIO_rresp;
output AXI_LITE_GPIO_rvalid;
input [31:0]AXI_LITE_GPIO_wdata;
output AXI_LITE_GPIO_wready;
input [3:0]AXI_LITE_GPIO_wstrb;
input AXI_LITE_GPIO_wvalid;
input [6:0]AXI_LITE_PWM_araddr;
input [2:0]AXI_LITE_PWM_arprot;
output AXI_LITE_PWM_arready;
input AXI_LITE_PWM_arvalid;
input [6:0]AXI_LITE_PWM_awaddr;
input [2:0]AXI_LITE_PWM_awprot;
output AXI_LITE_PWM_awready;
input AXI_LITE_PWM_awvalid;
input AXI_LITE_PWM_bready;
output [1:0]AXI_LITE_PWM_bresp;
output AXI_LITE_PWM_bvalid;
output [31:0]AXI_LITE_PWM_rdata;
input AXI_LITE_PWM_rready;
output [1:0]AXI_LITE_PWM_rresp;
output AXI_LITE_PWM_rvalid;
input [31:0]AXI_LITE_PWM_wdata;
output AXI_LITE_PWM_wready;
input [3:0]AXI_LITE_PWM_wstrb;
input AXI_LITE_PWM_wvalid;
input [4:0]AXI_LITE_TIMER_araddr;
output AXI_LITE_TIMER_arready;
input AXI_LITE_TIMER_arvalid;
input [4:0]AXI_LITE_TIMER_awaddr;
output AXI_LITE_TIMER_awready;
input AXI_LITE_TIMER_awvalid;
input AXI_LITE_TIMER_bready;
output [1:0]AXI_LITE_TIMER_bresp;
output AXI_LITE_TIMER_bvalid;
output [31:0]AXI_LITE_TIMER_rdata;
input AXI_LITE_TIMER_rready;
output [1:0]AXI_LITE_TIMER_rresp;
output AXI_LITE_TIMER_rvalid;
input [31:0]AXI_LITE_TIMER_wdata;
output AXI_LITE_TIMER_wready;
input [3:0]AXI_LITE_TIMER_wstrb;
input AXI_LITE_TIMER_wvalid;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
input s_axi_aclk;
input s_axi_aresetn;
output timer_interrupt;
wire [0:0]PWM_0_pwm;
wire [6:0]PWM_AXI_1_ARADDR;
wire [2:0]PWM_AXI_1_ARPROT;
wire PWM_AXI_1_ARREADY;
wire PWM_AXI_1_ARVALID;
wire [6:0]PWM_AXI_1_AWADDR;
wire [2:0]PWM_AXI_1_AWPROT;
wire PWM_AXI_1_AWREADY;
wire PWM_AXI_1_AWVALID;
wire PWM_AXI_1_BREADY;
wire [1:0]PWM_AXI_1_BRESP;
wire PWM_AXI_1_BVALID;
wire [31:0]PWM_AXI_1_RDATA;
wire PWM_AXI_1_RREADY;
wire [1:0]PWM_AXI_1_RRESP;
wire PWM_AXI_1_RVALID;
wire [31:0]PWM_AXI_1_WDATA;
wire PWM_AXI_1_WREADY;
wire [3:0]PWM_AXI_1_WSTRB;
wire PWM_AXI_1_WVALID;
wire [8:0]S_AXI_1_ARADDR;
wire S_AXI_1_ARREADY;
wire S_AXI_1_ARVALID;
wire [8:0]S_AXI_1_AWADDR;
wire S_AXI_1_AWREADY;
wire S_AXI_1_AWVALID;
wire S_AXI_1_BREADY;
wire [1:0]S_AXI_1_BRESP;
wire S_AXI_1_BVALID;
wire [31:0]S_AXI_1_RDATA;
wire S_AXI_1_RREADY;
wire [1:0]S_AXI_1_RRESP;
wire S_AXI_1_RVALID;
wire [31:0]S_AXI_1_WDATA;
wire S_AXI_1_WREADY;
wire [3:0]S_AXI_1_WSTRB;
wire S_AXI_1_WVALID;
wire [4:0]S_AXI_2_ARADDR;
wire S_AXI_2_ARREADY;
wire S_AXI_2_ARVALID;
wire [4:0]S_AXI_2_AWADDR;
wire S_AXI_2_AWREADY;
wire S_AXI_2_AWVALID;
wire S_AXI_2_BREADY;
wire [1:0]S_AXI_2_BRESP;
wire S_AXI_2_BVALID;
wire [31:0]S_AXI_2_RDATA;
wire S_AXI_2_RREADY;
wire [1:0]S_AXI_2_RRESP;
wire S_AXI_2_RVALID;
wire [31:0]S_AXI_2_WDATA;
wire S_AXI_2_WREADY;
wire [3:0]S_AXI_2_WSTRB;
wire S_AXI_2_WVALID;
wire [2:0]axi_gpio_0_gpio_io_o;
wire axi_timer_0_interrupt;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
wire [3:0]xlconcat_0_dout;
wire [3:0]xlconstant_0_dout;
assign AXI_LITE_GPIO_arready = S_AXI_1_ARREADY;
assign AXI_LITE_GPIO_awready = S_AXI_1_AWREADY;
assign AXI_LITE_GPIO_bresp[1:0] = S_AXI_1_BRESP;
assign AXI_LITE_GPIO_bvalid = S_AXI_1_BVALID;
assign AXI_LITE_GPIO_rdata[31:0] = S_AXI_1_RDATA;
assign AXI_LITE_GPIO_rresp[1:0] = S_AXI_1_RRESP;
assign AXI_LITE_GPIO_rvalid = S_AXI_1_RVALID;
assign AXI_LITE_GPIO_wready = S_AXI_1_WREADY;
assign AXI_LITE_PWM_arready = PWM_AXI_1_ARREADY;
assign AXI_LITE_PWM_awready = PWM_AXI_1_AWREADY;
assign AXI_LITE_PWM_bresp[1:0] = PWM_AXI_1_BRESP;
assign AXI_LITE_PWM_bvalid = PWM_AXI_1_BVALID;
assign AXI_LITE_PWM_rdata[31:0] = PWM_AXI_1_RDATA;
assign AXI_LITE_PWM_rresp[1:0] = PWM_AXI_1_RRESP;
assign AXI_LITE_PWM_rvalid = PWM_AXI_1_RVALID;
assign AXI_LITE_PWM_wready = PWM_AXI_1_WREADY;
assign AXI_LITE_TIMER_arready = S_AXI_2_ARREADY;
assign AXI_LITE_TIMER_awready = S_AXI_2_AWREADY;
assign AXI_LITE_TIMER_bresp[1:0] = S_AXI_2_BRESP;
assign AXI_LITE_TIMER_bvalid = S_AXI_2_BVALID;
assign AXI_LITE_TIMER_rdata[31:0] = S_AXI_2_RDATA;
assign AXI_LITE_TIMER_rresp[1:0] = S_AXI_2_RRESP;
assign AXI_LITE_TIMER_rvalid = S_AXI_2_RVALID;
assign AXI_LITE_TIMER_wready = S_AXI_2_WREADY;
assign PWM_AXI_1_ARADDR = AXI_LITE_PWM_araddr[6:0];
assign PWM_AXI_1_ARPROT = AXI_LITE_PWM_arprot[2:0];
assign PWM_AXI_1_ARVALID = AXI_LITE_PWM_arvalid;
assign PWM_AXI_1_AWADDR = AXI_LITE_PWM_awaddr[6:0];
assign PWM_AXI_1_AWPROT = AXI_LITE_PWM_awprot[2:0];
assign PWM_AXI_1_AWVALID = AXI_LITE_PWM_awvalid;
assign PWM_AXI_1_BREADY = AXI_LITE_PWM_bready;
assign PWM_AXI_1_RREADY = AXI_LITE_PWM_rready;
assign PWM_AXI_1_WDATA = AXI_LITE_PWM_wdata[31:0];
assign PWM_AXI_1_WSTRB = AXI_LITE_PWM_wstrb[3:0];
assign PWM_AXI_1_WVALID = AXI_LITE_PWM_wvalid;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_1_ARADDR = AXI_LITE_GPIO_araddr[8:0];
assign S_AXI_1_ARVALID = AXI_LITE_GPIO_arvalid;
assign S_AXI_1_AWADDR = AXI_LITE_GPIO_awaddr[8:0];
assign S_AXI_1_AWVALID = AXI_LITE_GPIO_awvalid;
assign S_AXI_1_BREADY = AXI_LITE_GPIO_bready;
assign S_AXI_1_RREADY = AXI_LITE_GPIO_rready;
assign S_AXI_1_WDATA = AXI_LITE_GPIO_wdata[31:0];
assign S_AXI_1_WSTRB = AXI_LITE_GPIO_wstrb[3:0];
assign S_AXI_1_WVALID = AXI_LITE_GPIO_wvalid;
assign S_AXI_2_ARADDR = AXI_LITE_TIMER_araddr[4:0];
assign S_AXI_2_ARVALID = AXI_LITE_TIMER_arvalid;
assign S_AXI_2_AWADDR = AXI_LITE_TIMER_awaddr[4:0];
assign S_AXI_2_AWVALID = AXI_LITE_TIMER_awvalid;
assign S_AXI_2_BREADY = AXI_LITE_TIMER_bready;
assign S_AXI_2_RREADY = AXI_LITE_TIMER_rready;
assign S_AXI_2_WDATA = AXI_LITE_TIMER_wdata[31:0];
assign S_AXI_2_WSTRB = AXI_LITE_TIMER_wstrb[3:0];
assign S_AXI_2_WVALID = AXI_LITE_TIMER_wvalid;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
assign timer_interrupt = axi_timer_0_interrupt;
PmodAMP2_PWM_0_0 PWM_0
(.pwm(PWM_0_pwm),
.pwm_axi_aclk(s_axi_aclk_1),
.pwm_axi_araddr(PWM_AXI_1_ARADDR),
.pwm_axi_aresetn(s_axi_aresetn_1),
.pwm_axi_arprot(PWM_AXI_1_ARPROT),
.pwm_axi_arready(PWM_AXI_1_ARREADY),
.pwm_axi_arvalid(PWM_AXI_1_ARVALID),
.pwm_axi_awaddr(PWM_AXI_1_AWADDR),
.pwm_axi_awprot(PWM_AXI_1_AWPROT),
.pwm_axi_awready(PWM_AXI_1_AWREADY),
.pwm_axi_awvalid(PWM_AXI_1_AWVALID),
.pwm_axi_bready(PWM_AXI_1_BREADY),
.pwm_axi_bresp(PWM_AXI_1_BRESP),
.pwm_axi_bvalid(PWM_AXI_1_BVALID),
.pwm_axi_rdata(PWM_AXI_1_RDATA),
.pwm_axi_rready(PWM_AXI_1_RREADY),
.pwm_axi_rresp(PWM_AXI_1_RRESP),
.pwm_axi_rvalid(PWM_AXI_1_RVALID),
.pwm_axi_wdata(PWM_AXI_1_WDATA),
.pwm_axi_wready(PWM_AXI_1_WREADY),
.pwm_axi_wstrb(PWM_AXI_1_WSTRB),
.pwm_axi_wvalid(PWM_AXI_1_WVALID));
PmodAMP2_axi_gpio_0_0 axi_gpio_0
(.gpio_io_o(axi_gpio_0_gpio_io_o),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_ARREADY),
.s_axi_arvalid(S_AXI_1_ARVALID),
.s_axi_awaddr(S_AXI_1_AWADDR),
.s_axi_awready(S_AXI_1_AWREADY),
.s_axi_awvalid(S_AXI_1_AWVALID),
.s_axi_bready(S_AXI_1_BREADY),
.s_axi_bresp(S_AXI_1_BRESP),
.s_axi_bvalid(S_AXI_1_BVALID),
.s_axi_rdata(S_AXI_1_RDATA),
.s_axi_rready(S_AXI_1_RREADY),
.s_axi_rresp(S_AXI_1_RRESP),
.s_axi_rvalid(S_AXI_1_RVALID),
.s_axi_wdata(S_AXI_1_WDATA),
.s_axi_wready(S_AXI_1_WREADY),
.s_axi_wstrb(S_AXI_1_WSTRB),
.s_axi_wvalid(S_AXI_1_WVALID));
PmodAMP2_axi_timer_0_0 axi_timer_0
(.capturetrig0(1'b0),
.capturetrig1(1'b0),
.freeze(1'b0),
.interrupt(axi_timer_0_interrupt),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_2_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_2_ARREADY),
.s_axi_arvalid(S_AXI_2_ARVALID),
.s_axi_awaddr(S_AXI_2_AWADDR),
.s_axi_awready(S_AXI_2_AWREADY),
.s_axi_awvalid(S_AXI_2_AWVALID),
.s_axi_bready(S_AXI_2_BREADY),
.s_axi_bresp(S_AXI_2_BRESP),
.s_axi_bvalid(S_AXI_2_BVALID),
.s_axi_rdata(S_AXI_2_RDATA),
.s_axi_rready(S_AXI_2_RREADY),
.s_axi_rresp(S_AXI_2_RRESP),
.s_axi_rvalid(S_AXI_2_RVALID),
.s_axi_wdata(S_AXI_2_WDATA),
.s_axi_wready(S_AXI_2_WREADY),
.s_axi_wstrb(S_AXI_2_WSTRB),
.s_axi_wvalid(S_AXI_2_WVALID));
PmodAMP2_pmod_bridge_0_0 pmod_bridge_0
(.in_top_bus_O(xlconcat_0_dout),
.in_top_bus_T(xlconstant_0_dout),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
PmodAMP2_xlconcat_0_0 xlconcat_0
(.In0(PWM_0_pwm),
.In1(axi_gpio_0_gpio_io_o),
.dout(xlconcat_0_dout));
PmodAMP2_xlconstant_0_0 xlconstant_0
(.dout(xlconstant_0_dout));
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpll1.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module altpll1 (
areset,
clkswitch,
inclk0,
inclk1,
activeclock,
c0,
c1,
c2,
c3,
locked);
input areset;
input clkswitch;
input inclk0;
input inclk1;
output activeclock;
output c0;
output c1;
output c2;
output c3;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 clkswitch;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "400.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "400.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "400.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "40.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "40.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "10"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "10"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "10"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "400.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "400.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "400.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "400.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "12.50000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "45.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "135.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "12500"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "313"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "625"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "938"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "25000"
// Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "25000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: activeclock 0 0 0 0 OUTPUT GND "activeclock"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
// Retrieval info: CONNECT: activeclock 0 0 0 0 @activeclock 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:33:20 06/19/2016
// Design Name:
// Module Name: sqrt
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sqrt(e , f);
// input from logarithmic block
input [30:0] e;
//output f
output reg signed [16:0] f;
reg [4:0] exp_f;
//output from leading zero detector
wire [4:0] lzd;
wire valid;
//instantiation of leading zero detector
LZD_32bit l(.in({1'b0,e}),.out(lzd),.valid(valid));
// declaration of all registers
reg [4:0] exp_f1;
reg [30:0] x_f1,x_f;
reg [30:0] y_f;
reg [5:0] address;
reg [63:0] temp1;
// memory allocation
reg [31:0] c0[63:0];
reg [31:0] c1[63:0];
reg [31:0] c2[63:0];
reg [31:0] c3[63:0];
initial
begin
//memory allocation and loading of square root coefficients
$readmemh("c0_sqrt.txt",c0);
$readmemh("c1_sqrt.txt", c1);
$readmemh("c2_sqrt.txt", c2);
$readmemh("c3_sqrt.txt", c3);
//set initial values to zero
exp_f=0;
x_f1=0;
x_f=0;
y_f=0;
exp_f1=0;
end
// e and lzd are in sensitive list for this always block
always @(e,lzd)
begin
// range reduction
exp_f= 5- lzd;
x_f1= e>>exp_f;
//coefficient address is obtained from 6 bits from MSB side of input e
address=e[30:25];
// if exp_f[0]= 1 then coefficients are taken accordingly and y_f is calculated
//when exp_f[0]=1 then coefficients from c0 and c1 are used
//when exp_f[0]=0 then coefficients from c2 and c3 are used
// approximation
if (exp_f[0])
begin
x_f= x_f1>>1;
temp1= c1[address]*x_f1;
y_f =temp1+ c0[address];
end
else
begin
x_f=x_f1;
temp1= c3[address]*x_f1;
y_f =temp1+ c2[address];
end
// range reconstruction
if (exp_f[0])
begin
exp_f1= (exp_f+1)>>1;
end
else
begin
exp_f1= (exp_f)>>1;
end
// output f
f= y_f<<exp_f1;
end
endmodule |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_138x16_shift.v
// /___/ /\ Timestamp: Thu Nov 8 18:35:16 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_138x16_shift.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_138x16_shift.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_138x16_shift.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_138x16_shift.v
// # of Modules : 1
// Design Name : fifo_138x16_shift
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_138x16_shift (
clk, rd_en, empty, wr_en, full, srst, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
output empty;
input wr_en;
output full;
input srst;
output [137 : 0] dout;
input [137 : 0] din;
// synthesis translate_off
wire N0;
wire N13;
wire N15;
wire N16;
wire N4;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>2 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>3 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>2 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>3 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>2 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>3 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>2 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>3 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_i_32 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i_33 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_34 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[0].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[1].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[2].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[3].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[4].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[5].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[6].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[7].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[8].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[9].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[10].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[11].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[12].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[13].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[14].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[15].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[16].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[17].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[18].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[19].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[20].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[21].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[22].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[23].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[24].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[25].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[26].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[27].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[28].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[29].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[30].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[31].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[32].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[33].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[34].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[35].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[36].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[37].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[38].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[39].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[40].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[41].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[42].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[43].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[44].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[45].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[46].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[47].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[48].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[49].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[50].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[51].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[52].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[53].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[54].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[55].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[56].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[57].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[58].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[59].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[60].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[61].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[62].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[63].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[64].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[65].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[66].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[67].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[68].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[69].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[70].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[71].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[72].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[73].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[74].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[75].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[76].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[77].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[78].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[79].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[80].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[81].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[82].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[83].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[84].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[85].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[86].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[87].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[88].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[89].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[90].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[91].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[92].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[93].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[94].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[95].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[96].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[97].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[98].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[99].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[100].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[101].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[102].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[103].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[104].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[105].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[106].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[107].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[108].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[109].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[110].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[111].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[112].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[113].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[114].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[115].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[116].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[117].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[118].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[119].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[120].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[121].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[122].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[123].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[124].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[125].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[126].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[127].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[128].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[129].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[130].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[131].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[132].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[133].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[134].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[135].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[136].gv5.srl32_Q31_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[137].gv5.srl32_Q31_UNCONNECTED ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count ;
wire [137 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i ;
wire [137 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem ;
assign
empty = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_i_32 ,
full = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_34 ,
dout[137] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [137],
dout[136] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [136],
dout[135] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [135],
dout[134] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [134],
dout[133] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [133],
dout[132] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [132],
dout[131] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [131],
dout[130] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [130],
dout[129] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [129],
dout[128] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [128],
dout[127] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [127],
dout[126] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [126],
dout[125] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [125],
dout[124] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [124],
dout[123] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [123],
dout[122] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [122],
dout[121] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [121],
dout[120] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [120],
dout[119] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [119],
dout[118] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [118],
dout[117] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [117],
dout[116] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [116],
dout[115] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [115],
dout[114] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [114],
dout[113] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [113],
dout[112] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [112],
dout[111] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [111],
dout[110] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [110],
dout[109] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [109],
dout[108] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [108],
dout[107] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [107],
dout[106] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [106],
dout[105] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [105],
dout[104] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [104],
dout[103] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [103],
dout[102] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [102],
dout[101] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [101],
dout[100] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [100],
dout[99] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [99],
dout[98] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [98],
dout[97] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [97],
dout[96] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [96],
dout[95] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [95],
dout[94] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [94],
dout[93] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [93],
dout[92] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [92],
dout[91] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [91],
dout[90] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [90],
dout[89] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [89],
dout[88] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [88],
dout[87] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [87],
dout[86] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [86],
dout[85] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [85],
dout[84] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [84],
dout[83] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [83],
dout[82] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [82],
dout[81] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [81],
dout[80] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [80],
dout[79] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [79],
dout[78] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [78],
dout[77] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [77],
dout[76] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [76],
dout[75] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [75],
dout[74] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [74],
dout[73] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [73],
dout[72] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [72],
dout[71] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [71],
dout[70] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [70],
dout[69] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [69],
dout[68] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [68],
dout[67] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [67],
dout[66] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [66],
dout[65] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [65],
dout[64] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [64],
dout[63] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [63],
dout[62] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [62],
dout[61] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [61],
dout[60] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [60],
dout[59] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [59],
dout[58] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [58],
dout[57] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [57],
dout[56] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [56],
dout[55] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [55],
dout[54] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [54],
dout[53] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [53],
dout[52] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [52],
dout[51] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [51],
dout[50] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [50],
dout[49] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [49],
dout[48] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [48],
dout[47] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [47],
dout[46] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [46],
dout[45] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [45],
dout[44] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [44],
dout[43] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [43],
dout[42] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [42],
dout[41] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [41],
dout[40] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [40],
dout[39] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [39],
dout[38] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [38],
dout[37] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [37],
dout[36] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [36],
dout[35] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [35],
dout[34] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [34],
dout[33] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [33],
dout[32] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [32],
dout[31] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [31],
dout[30] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [30],
dout[29] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [29],
dout[28] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [28],
dout[27] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [27],
dout[26] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [26],
dout[25] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [25],
dout[24] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [24],
dout[23] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [23],
dout[22] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [22],
dout[21] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [21],
dout[20] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [20],
dout[19] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [19],
dout[18] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [18],
dout[17] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [17],
dout[16] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [16],
dout[15] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [15],
dout[14] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [14],
dout[13] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [13],
dout[12] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [12],
dout[11] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [11],
dout[10] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [10],
dout[9] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [9],
dout[8] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [8],
dout[7] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [7],
dout[6] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [6],
dout[5] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [5],
dout[4] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [4],
dout[3] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [3],
dout[2] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [2],
dout[1] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [1],
dout[0] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [0];
GND XST_GND (
.G(N0)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[0].gv5.srl32 (
.CLK(clk),
.D(din[0]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [0]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[0].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[1].gv5.srl32 (
.CLK(clk),
.D(din[1]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [1]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[1].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[2].gv5.srl32 (
.CLK(clk),
.D(din[2]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [2]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[2].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[3].gv5.srl32 (
.CLK(clk),
.D(din[3]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [3]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[3].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[4].gv5.srl32 (
.CLK(clk),
.D(din[4]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [4]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[4].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[5].gv5.srl32 (
.CLK(clk),
.D(din[5]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [5]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[5].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[6].gv5.srl32 (
.CLK(clk),
.D(din[6]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [6]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[6].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[7].gv5.srl32 (
.CLK(clk),
.D(din[7]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [7]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[7].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[8].gv5.srl32 (
.CLK(clk),
.D(din[8]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [8]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[8].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[9].gv5.srl32 (
.CLK(clk),
.D(din[9]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [9]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[9].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[10].gv5.srl32 (
.CLK(clk),
.D(din[10]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [10]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[10].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[11].gv5.srl32 (
.CLK(clk),
.D(din[11]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [11]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[11].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[12].gv5.srl32 (
.CLK(clk),
.D(din[12]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [12]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[12].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[13].gv5.srl32 (
.CLK(clk),
.D(din[13]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [13]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[13].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[14].gv5.srl32 (
.CLK(clk),
.D(din[14]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [14]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[14].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[15].gv5.srl32 (
.CLK(clk),
.D(din[15]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [15]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[15].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[16].gv5.srl32 (
.CLK(clk),
.D(din[16]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [16]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[16].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[17].gv5.srl32 (
.CLK(clk),
.D(din[17]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [17]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[17].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[18].gv5.srl32 (
.CLK(clk),
.D(din[18]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [18]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[18].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[19].gv5.srl32 (
.CLK(clk),
.D(din[19]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [19]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[19].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[20].gv5.srl32 (
.CLK(clk),
.D(din[20]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [20]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[20].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[21].gv5.srl32 (
.CLK(clk),
.D(din[21]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [21]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[21].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[22].gv5.srl32 (
.CLK(clk),
.D(din[22]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [22]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[22].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[23].gv5.srl32 (
.CLK(clk),
.D(din[23]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [23]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[23].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[24].gv5.srl32 (
.CLK(clk),
.D(din[24]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [24]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[24].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[25].gv5.srl32 (
.CLK(clk),
.D(din[25]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [25]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[25].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[26].gv5.srl32 (
.CLK(clk),
.D(din[26]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [26]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[26].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[27].gv5.srl32 (
.CLK(clk),
.D(din[27]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [27]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[27].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[28].gv5.srl32 (
.CLK(clk),
.D(din[28]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [28]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[28].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[29].gv5.srl32 (
.CLK(clk),
.D(din[29]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [29]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[29].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[30].gv5.srl32 (
.CLK(clk),
.D(din[30]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [30]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[30].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[31].gv5.srl32 (
.CLK(clk),
.D(din[31]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [31]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[31].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[32].gv5.srl32 (
.CLK(clk),
.D(din[32]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [32]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[32].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[33].gv5.srl32 (
.CLK(clk),
.D(din[33]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [33]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[33].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[34].gv5.srl32 (
.CLK(clk),
.D(din[34]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [34]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[34].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[35].gv5.srl32 (
.CLK(clk),
.D(din[35]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [35]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[35].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[36].gv5.srl32 (
.CLK(clk),
.D(din[36]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [36]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[36].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[37].gv5.srl32 (
.CLK(clk),
.D(din[37]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [37]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[37].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[38].gv5.srl32 (
.CLK(clk),
.D(din[38]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [38]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[38].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[39].gv5.srl32 (
.CLK(clk),
.D(din[39]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [39]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[39].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[40].gv5.srl32 (
.CLK(clk),
.D(din[40]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [40]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[40].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[41].gv5.srl32 (
.CLK(clk),
.D(din[41]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [41]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[41].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[42].gv5.srl32 (
.CLK(clk),
.D(din[42]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [42]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[42].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[43].gv5.srl32 (
.CLK(clk),
.D(din[43]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [43]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[43].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[44].gv5.srl32 (
.CLK(clk),
.D(din[44]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [44]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[44].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[45].gv5.srl32 (
.CLK(clk),
.D(din[45]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [45]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[45].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[46].gv5.srl32 (
.CLK(clk),
.D(din[46]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [46]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[46].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[47].gv5.srl32 (
.CLK(clk),
.D(din[47]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [47]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[47].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[48].gv5.srl32 (
.CLK(clk),
.D(din[48]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [48]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[48].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[49].gv5.srl32 (
.CLK(clk),
.D(din[49]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [49]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[49].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[50].gv5.srl32 (
.CLK(clk),
.D(din[50]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [50]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[50].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[51].gv5.srl32 (
.CLK(clk),
.D(din[51]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [51]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[51].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[52].gv5.srl32 (
.CLK(clk),
.D(din[52]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [52]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[52].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[53].gv5.srl32 (
.CLK(clk),
.D(din[53]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [53]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[53].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[54].gv5.srl32 (
.CLK(clk),
.D(din[54]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [54]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[54].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[55].gv5.srl32 (
.CLK(clk),
.D(din[55]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [55]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[55].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[56].gv5.srl32 (
.CLK(clk),
.D(din[56]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [56]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[56].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[57].gv5.srl32 (
.CLK(clk),
.D(din[57]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [57]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[57].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[58].gv5.srl32 (
.CLK(clk),
.D(din[58]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [58]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[58].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[59].gv5.srl32 (
.CLK(clk),
.D(din[59]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [59]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[59].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[60].gv5.srl32 (
.CLK(clk),
.D(din[60]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [60]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[60].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[61].gv5.srl32 (
.CLK(clk),
.D(din[61]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [61]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[61].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[62].gv5.srl32 (
.CLK(clk),
.D(din[62]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [62]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[62].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[63].gv5.srl32 (
.CLK(clk),
.D(din[63]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [63]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[63].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[64].gv5.srl32 (
.CLK(clk),
.D(din[64]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [64]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[64].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[65].gv5.srl32 (
.CLK(clk),
.D(din[65]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [65]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[65].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[66].gv5.srl32 (
.CLK(clk),
.D(din[66]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [66]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[66].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[67].gv5.srl32 (
.CLK(clk),
.D(din[67]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [67]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[67].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[68].gv5.srl32 (
.CLK(clk),
.D(din[68]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [68]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[68].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[69].gv5.srl32 (
.CLK(clk),
.D(din[69]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [69]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[69].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[70].gv5.srl32 (
.CLK(clk),
.D(din[70]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [70]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[70].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[71].gv5.srl32 (
.CLK(clk),
.D(din[71]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [71]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[71].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[72].gv5.srl32 (
.CLK(clk),
.D(din[72]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [72]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[72].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[73].gv5.srl32 (
.CLK(clk),
.D(din[73]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [73]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[73].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[74].gv5.srl32 (
.CLK(clk),
.D(din[74]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [74]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[74].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[75].gv5.srl32 (
.CLK(clk),
.D(din[75]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [75]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[75].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[76].gv5.srl32 (
.CLK(clk),
.D(din[76]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [76]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[76].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[77].gv5.srl32 (
.CLK(clk),
.D(din[77]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [77]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[77].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[78].gv5.srl32 (
.CLK(clk),
.D(din[78]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [78]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[78].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[79].gv5.srl32 (
.CLK(clk),
.D(din[79]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [79]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[79].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[80].gv5.srl32 (
.CLK(clk),
.D(din[80]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [80]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[80].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[81].gv5.srl32 (
.CLK(clk),
.D(din[81]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [81]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[81].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[82].gv5.srl32 (
.CLK(clk),
.D(din[82]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [82]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[82].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[83].gv5.srl32 (
.CLK(clk),
.D(din[83]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [83]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[83].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[84].gv5.srl32 (
.CLK(clk),
.D(din[84]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [84]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[84].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[85].gv5.srl32 (
.CLK(clk),
.D(din[85]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [85]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[85].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[86].gv5.srl32 (
.CLK(clk),
.D(din[86]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [86]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[86].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[87].gv5.srl32 (
.CLK(clk),
.D(din[87]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [87]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[87].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[88].gv5.srl32 (
.CLK(clk),
.D(din[88]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [88]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[88].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[89].gv5.srl32 (
.CLK(clk),
.D(din[89]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [89]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[89].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[90].gv5.srl32 (
.CLK(clk),
.D(din[90]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [90]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[90].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[91].gv5.srl32 (
.CLK(clk),
.D(din[91]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [91]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[91].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[92].gv5.srl32 (
.CLK(clk),
.D(din[92]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [92]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[92].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[93].gv5.srl32 (
.CLK(clk),
.D(din[93]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [93]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[93].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[94].gv5.srl32 (
.CLK(clk),
.D(din[94]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [94]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[94].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[95].gv5.srl32 (
.CLK(clk),
.D(din[95]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [95]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[95].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[96].gv5.srl32 (
.CLK(clk),
.D(din[96]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [96]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[96].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[97].gv5.srl32 (
.CLK(clk),
.D(din[97]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [97]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[97].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[98].gv5.srl32 (
.CLK(clk),
.D(din[98]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [98]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[98].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[99].gv5.srl32 (
.CLK(clk),
.D(din[99]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [99]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[99].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[100].gv5.srl32 (
.CLK(clk),
.D(din[100]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [100]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[100].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[101].gv5.srl32 (
.CLK(clk),
.D(din[101]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [101]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[101].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[102].gv5.srl32 (
.CLK(clk),
.D(din[102]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [102]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[102].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[103].gv5.srl32 (
.CLK(clk),
.D(din[103]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [103]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[103].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[104].gv5.srl32 (
.CLK(clk),
.D(din[104]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [104]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[104].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[105].gv5.srl32 (
.CLK(clk),
.D(din[105]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [105]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[105].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[106].gv5.srl32 (
.CLK(clk),
.D(din[106]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [106]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[106].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[107].gv5.srl32 (
.CLK(clk),
.D(din[107]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [107]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[107].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[108].gv5.srl32 (
.CLK(clk),
.D(din[108]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [108]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[108].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[109].gv5.srl32 (
.CLK(clk),
.D(din[109]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [109]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[109].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[110].gv5.srl32 (
.CLK(clk),
.D(din[110]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [110]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[110].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[111].gv5.srl32 (
.CLK(clk),
.D(din[111]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [111]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[111].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[112].gv5.srl32 (
.CLK(clk),
.D(din[112]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [112]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[112].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[113].gv5.srl32 (
.CLK(clk),
.D(din[113]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [113]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[113].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[114].gv5.srl32 (
.CLK(clk),
.D(din[114]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [114]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[114].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[115].gv5.srl32 (
.CLK(clk),
.D(din[115]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [115]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[115].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[116].gv5.srl32 (
.CLK(clk),
.D(din[116]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [116]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[116].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[117].gv5.srl32 (
.CLK(clk),
.D(din[117]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [117]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[117].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[118].gv5.srl32 (
.CLK(clk),
.D(din[118]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [118]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[118].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[119].gv5.srl32 (
.CLK(clk),
.D(din[119]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [119]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[119].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[120].gv5.srl32 (
.CLK(clk),
.D(din[120]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [120]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[120].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[121].gv5.srl32 (
.CLK(clk),
.D(din[121]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [121]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[121].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[122].gv5.srl32 (
.CLK(clk),
.D(din[122]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [122]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[122].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[123].gv5.srl32 (
.CLK(clk),
.D(din[123]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [123]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[123].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[124].gv5.srl32 (
.CLK(clk),
.D(din[124]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [124]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[124].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[125].gv5.srl32 (
.CLK(clk),
.D(din[125]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [125]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[125].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[126].gv5.srl32 (
.CLK(clk),
.D(din[126]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [126]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[126].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[127].gv5.srl32 (
.CLK(clk),
.D(din[127]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [127]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[127].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[128].gv5.srl32 (
.CLK(clk),
.D(din[128]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [128]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[128].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[129].gv5.srl32 (
.CLK(clk),
.D(din[129]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [129]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[129].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[130].gv5.srl32 (
.CLK(clk),
.D(din[130]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [130]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[130].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[131].gv5.srl32 (
.CLK(clk),
.D(din[131]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [131]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[131].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[132].gv5.srl32 (
.CLK(clk),
.D(din[132]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [132]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[132].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[133].gv5.srl32 (
.CLK(clk),
.D(din[133]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [133]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[133].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[134].gv5.srl32 (
.CLK(clk),
.D(din[134]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [134]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[134].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[135].gv5.srl32 (
.CLK(clk),
.D(din[135]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [135]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[135].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[136].gv5.srl32 (
.CLK(clk),
.D(din[136]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [136]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[136].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[137].gv5.srl32 (
.CLK(clk),
.D(din[137]),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [137]),
.Q31(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[137].gv5.srl32_Q31_UNCONNECTED ),
.A({N0, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]})
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_137 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [137]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [137])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_136 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [136]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [136])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_135 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [135]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [135])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_134 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [134]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [134])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_133 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [133]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [133])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_132 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [132]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [132])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_131 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [131]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [131])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_130 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [130]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [130])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_129 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [129]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [129])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_128 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [128]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [128])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_127 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [127]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [127])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_126 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [126]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [126])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_125 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [125]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [125])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_124 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [124]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [124])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_123 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [123]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [123])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_122 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [122]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [122])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_121 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [121]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [121])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_120 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [120]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [120])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_119 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [119]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [119])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_118 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [118]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [118])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_117 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [117]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [117])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_116 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [116]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [116])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_115 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [115]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [115])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_114 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [114]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [114])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_113 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [113]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [113])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_112 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [112]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [112])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_111 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [111]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [111])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_110 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [110]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [110])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_109 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [109]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [109])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_108 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [108]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [108])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_107 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [107]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [107])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_106 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [106]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [106])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_105 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [105]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [105])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_104 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [104]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [104])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_103 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [103]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [103])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_102 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [102]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [102])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_101 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [101]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [101])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_100 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [100]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [100])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_99 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [99]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [99])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_98 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [98]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [98])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_97 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [97]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [97])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_96 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [96]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [96])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_95 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [95]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [95])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_94 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [94]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [94])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_93 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [93]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [93])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_92 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [92]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [92])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_91 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [91]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [91])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_90 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [90]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [90])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_89 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [89]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [89])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_88 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [88]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [88])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_87 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [87]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [87])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_86 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [86]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [86])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_85 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [85]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [85])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_84 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [84]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [84])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_83 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [83]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [83])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_82 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [82]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [82])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_81 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [81]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [81])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_80 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [80]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [80])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_79 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [79]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [79])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_78 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [78]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [78])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_77 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [77]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [77])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_76 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [76]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [76])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_75 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [75]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [75])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_74 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [74]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [74])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_73 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [73]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [73])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_72 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [72]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [72])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_71 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [71]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [71])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_70 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [70]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [70])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_69 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [69]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [69])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_68 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [68]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [68])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_67 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [67]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [67])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_66 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [66]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [66])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_65 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [65]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [65])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_64 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [64]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [64])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_63 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [63]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [63])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_62 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [62]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [62])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_61 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [61]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [61])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_60 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [60]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [60])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_59 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [59]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [59])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_58 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [58]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [58])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_57 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [57]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [57])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_56 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [56]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [56])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_55 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [55]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [55])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_54 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [54]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [54])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_53 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [53]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [53])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_52 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [52]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [52])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_51 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [51]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [51])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_50 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [50]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [50])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_49 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [49]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [49])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_48 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [48]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [48])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_47 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [47]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [47])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_46 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [46]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [46])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_45 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [45]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [45])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_44 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [44]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [44])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_43 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [43]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [43])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_42 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [42]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [42])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_41 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [41]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [41])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_40 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [40]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [40])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_39 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [39]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [39])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_38 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [38]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [38])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_37 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [37]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [37])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_36 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [36]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [36])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_35 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [35]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [35])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_34 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [34]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [34])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_33 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [33]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [33])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_32 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [32]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [32])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_31 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [31]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [31])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_30 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [30]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [30])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_29 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [29]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [29])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_28 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [28]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [28])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_27 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [27]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [27])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_26 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [26]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [26])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_25 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [25]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [25])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_24 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [24]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [24])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_23 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [23]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [23])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_22 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [22]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [22])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_21 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [21]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [21])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_20 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [20]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [20])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_19 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [19]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [19])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_18 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [18]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [18])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_17 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [17]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [17])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_16 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [16]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [16])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_15 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [15]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [15])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_14 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [14]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [14])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_13 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [13]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [13])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_12 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [12]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [12])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_11 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [11]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [11])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_10 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [10]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [10])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_9 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [9]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [9])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_mem [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i [0])
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_i_32 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_34 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i_33 )
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>3 ),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>2 ),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>2 ),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>2 ),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>2 ),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>3 ),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>3 ),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [1])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>3 ),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [0])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result [3]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result [2]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result [1]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0])
);
LUT4 #(
.INIT ( 16'h693C ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>31 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [0]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [1]),
.I3(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>3 )
);
LUT4 #(
.INIT ( 16'h693C ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>21 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [0]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [1]),
.I3(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>2 )
);
LUT4 #(
.INIT ( 16'h693C ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<1>1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1]),
.I3(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result [1])
);
LUT5 #(
.INIT ( 32'h7E813FC0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>31 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [0]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [1]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [2]),
.I4(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>3 )
);
LUT5 #(
.INIT ( 32'h7E813FC0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>211 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [0]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [1]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [2]),
.I4(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>2 )
);
LUT5 #(
.INIT ( 32'h7E813FC0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<2>1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2]),
.I4(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result [2])
);
LUT6 #(
.INIT ( 64'h3CCCCCCC9CCCCCC6 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>311 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [1]),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [0]),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>3 )
);
LUT6 #(
.INIT ( 64'h3CCCCCCC9CCCCCC6 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>211 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [1]),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [0]),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>2 )
);
LUT6 #(
.INIT ( 64'h2DF0F0F0F0F0F0D2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<3>1 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [3]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [2]),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [1]),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result [3])
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/ram_rd_en_i11 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i )
);
LUT4 #(
.INIT ( 16'h0CA6 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en1 (
.I0(rd_en),
.I1(wr_en),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i_33 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/cntr_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/ram_wr_en_i11 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
LUT4 #(
.INIT ( 16'hFFFE ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_mux00001_SW0 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [2]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [1]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [0]),
.O(N4)
);
LUT5 #(
.INIT ( 32'hFFFFFFFD ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_mux00001_SW1 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [1]),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [0]),
.O(N13)
);
LUT6 #(
.INIT ( 64'h3030301033313311 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_mux00001 (
.I0(rd_en),
.I1(srst),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i_33 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I4(N4),
.I5(N13),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_i_mux0000 )
);
LUT5 #(
.INIT ( 32'h00C40000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_mux00001_SW3 (
.I0(wr_en),
.I1(rd_en),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i_33 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [1]),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [0]),
.O(N15)
);
LUT4 #(
.INIT ( 16'hFFFD ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_mux00001_SW4 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i_33 ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [1]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [0]),
.O(N16)
);
LUT6 #(
.INIT ( 64'hFFABFEABFFAAFEAA ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_mux00001 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_30 ),
.I4(N16),
.I5(N15),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i_mux0000 )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>31_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>3 )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>21_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>2 )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result<0>1_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/Result [0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
module RAM_TEST #(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 1,
parameter IS_DUAL_PORT = 1,
parameter RANDOM_ITERATION_PER_LOOP = 10,
parameter LFSR_WIDTH = 16,
parameter LFSR_POLY = 16'hD008,
// How much to increment the address to move 1 full data width.
parameter ADDRESS_STEP = 1,
// Max address for this memory
parameter MAX_ADDRESS = 63
) (
input rst,
input clk,
// Memory connection
input [DATA_WIDTH-1:0] read_data,
output reg [DATA_WIDTH-1:0] write_data,
output reg write_enable,
output reg [ADDR_WIDTH-1:0] read_address,
output reg [ADDR_WIDTH-1:0] write_address,
// INIT ROM
// When the memory is first initialized, it is expected to match the ROM
// port.
input [DATA_WIDTH-1:0] rom_read_data,
output reg [ADDR_WIDTH-1:0] rom_read_address,
// When an iteration is complete, success will be 1 for 1 cycle
output reg loop_complete,
// If an error occurs during a test, error will be 1 for each cycle
// with an error.
output reg error,
// error_state will contain the state of test FSM when the error occured.
output reg [7:0] error_state,
// error_address will be the read address where the error occurred.
output reg [ADDR_WIDTH-1:0] error_address,
// expected_data will be the read value expected.
output reg [DATA_WIDTH-1:0] expected_data,
// actual_data will be the read value read.
output reg [DATA_WIDTH-1:0] actual_data
);
reg [7:0] state;
reg [DATA_WIDTH-1:0] test_value;
reg [$clog2(RANDOM_ITERATION_PER_LOOP)-1:0] rand_count;
localparam START = 8'd1,
VERIFY_INIT = 8'd2,
WRITE_ZEROS = 8'd3,
VERIFY_ZEROS = 8'd4,
WRITE_ONES = 8'd5,
VERIFY_ONES = 8'd6,
WRITE_10 = 8'd7,
VERIFY_10 = 8'd8,
WRITE_01 = 8'd9,
VERIFY_01 = 8'd10,
WRITE_RANDOM = 8'd11,
VERIFY_RANDOM = 8'd12,
RESTART_LOOP = 8'd13;
reg pause;
reg lfsr_reset;
reg wait_for_lfsr_reset;
reg [LFSR_WIDTH-1:0] lfsr_seed;
reg [LFSR_WIDTH-1:0] start_lfsr_seed;
wire [LFSR_WIDTH-1:0] rand_data;
LFSR #(
.WIDTH(LFSR_WIDTH),
.POLY(LFSR_POLY)
) lfsr (
.rst(lfsr_reset),
.clk(clk),
.seed(lfsr_seed),
.r(rand_data)
);
always @(posedge clk) begin
if(rst) begin
state <= START;
error <= 0;
write_enable <= 0;
lfsr_reset <= 1;
lfsr_seed <= 1;
end else begin
case(state)
START: begin
lfsr_reset <= 0;
state <= VERIFY_INIT;
read_address <= 0;
rom_read_address <= 0;
write_enable <= 0;
error <= 0;
end
VERIFY_INIT: begin
if(rom_read_data != read_data) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rom_read_data;
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
rom_read_address <= rom_read_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b0}};
state <= WRITE_ZEROS;
end
end
WRITE_ZEROS: begin
loop_complete <= 0;
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
write_address <= write_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
pause <= 1;
state <= VERIFY_ZEROS;
end
end
VERIFY_ZEROS: begin
if(pause) begin
pause <= 0;
end else begin
if(read_data != {DATA_WIDTH{1'b0}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b0}};
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b1}};
state <= WRITE_ONES;
end
end
end
WRITE_ONES: begin
// If dual port, data should still be zero.
if(IS_DUAL_PORT) begin
if(read_data != {DATA_WIDTH{1'b0}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b0}};
actual_data <= read_data;
end else begin
error <= 0;
end
end else begin
if(read_data != {DATA_WIDTH{1'b1}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b1}};
actual_data <= read_data;
end else begin
error <= 0;
end
end
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
write_address <= write_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
state <= VERIFY_ONES;
pause <= 1;
end
end
VERIFY_ONES: begin
if(pause) begin
pause <= 0;
end else begin
if(read_data != {DATA_WIDTH{1'b1}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b1}};
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
state <= WRITE_RANDOM;
write_enable <= 1;
write_address <= 0;
lfsr_seed <= rand_data;
write_data <= rand_data[DATA_WIDTH-1:0];
read_address <= 0;
end
end
end
WRITE_RANDOM: begin
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
write_address <= write_address + ADDRESS_STEP;
write_data <= rand_data[DATA_WIDTH-1:0];
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
state <= VERIFY_RANDOM;
// Return LFSR to state at beginning of WRITE_RANDOM.
lfsr_reset <= 1;
wait_for_lfsr_reset <= 1;
end
end
VERIFY_RANDOM: begin
if(wait_for_lfsr_reset) begin
wait_for_lfsr_reset <= 0;
lfsr_reset <= 1;
end else begin
lfsr_reset <= 0;
if(read_data != rand_data[DATA_WIDTH-1:0]) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rand_data[DATA_WIDTH-1:0];
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
state <= RESTART_LOOP;
end
end
end
RESTART_LOOP: begin
loop_complete <= 1;
error <= 0;
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b0}};
state <= WRITE_ZEROS;
end
default: begin
state <= START;
error <= 0;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLRBP_PP_SYMBOL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_PP_SYMBOL_V
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts video streams between RGB color formats. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_rgb_resampler_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 23;
parameter ODW = 7;
parameter IEW = 1;
parameter OEW = 0;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [11: 0] average_color;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[23:16], stream_in_data[23:22]};
assign g = {stream_in_data[15: 8], stream_in_data[15:14]};
assign b = {stream_in_data[ 7: 0], stream_in_data[ 7: 6]};
assign a = ALPHA;
assign average_color = {2'h0, r} + {1'b0, g, 1'b0} + {2'h0, b};
assign converted_data[ 7: 0] = average_color[11:4];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_TB_V
`define SKY130_FD_SC_LS__EINVN_TB_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__OR4_BEHAVIORAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_BEHAVIORAL_V |
`default_nettype none
//Parallel Adder - non pipeline
module mul4(
input [3 : 0] iSOURCE0,
input [3 : 0] iSOURCE1,
output [7 : 0] oOUTPUT);
assign oOUTPUT = ((iSOURCE0[0])? iSOURCE1 : 7'h00) + ((iSOURCE0[1])? iSOURCE1 << 1 : 7'h00) + ((iSOURCE0[2])? iSOURCE1 << 2 : 7'h00) + ((iSOURCE0[3])? iSOURCE1 << 3 : 7'h00);
endmodule
//Parallel Adder - non pipeline
module mul32(
input [31 : 0] iSOURCE0,
input [31 : 0] iSOURCE1,
output [63 : 0] oDATA,
output oHSF,
output oHOF,
output oHCF,
output oHPF,
output oHZF,
output oLSF,
output oLOF,
output oLCF,
output oLPF,
output oLZF);
wire [63:0] w_tmp_out;
assign w_tmp_out = ((iSOURCE0[0])? iSOURCE1 : 64'h00) + ((iSOURCE0[1])? iSOURCE1 << 1 : 64'h00) + ((iSOURCE0[2])? iSOURCE1 << 2 : 64'h00) + ((iSOURCE0[3])? iSOURCE1 << 3 : 64'h00)
+((iSOURCE0[4])? iSOURCE1 << 4 : 64'h00) + ((iSOURCE0[5])? iSOURCE1 << 5 : 64'h00) + ((iSOURCE0[6])? iSOURCE1 << 6 : 64'h00) + ((iSOURCE0[7])? iSOURCE1 << 7 : 64'h00)
+((iSOURCE0[8])? iSOURCE1 << 8 : 64'h00) + ((iSOURCE0[9])? iSOURCE1 << 9 : 64'h00) + ((iSOURCE0[10])? iSOURCE1 << 10 : 64'h00) + ((iSOURCE0[11])? iSOURCE1 << 11 : 64'h00)
+((iSOURCE0[12])? iSOURCE1 << 12 : 64'h00) + ((iSOURCE0[13])? iSOURCE1 << 13 : 64'h00) + ((iSOURCE0[14])? iSOURCE1 << 14 : 64'h00) + ((iSOURCE0[15])? iSOURCE1 << 15 : 64'h00)
+((iSOURCE0[16])? iSOURCE1 << 16 : 64'h00) + ((iSOURCE0[17])? iSOURCE1 << 17 : 64'h00) + ((iSOURCE0[18])? iSOURCE1 << 18 : 64'h00) + ((iSOURCE0[19])? iSOURCE1 << 19 : 64'h00)
+((iSOURCE0[20])? iSOURCE1 << 20 : 64'h00) + ((iSOURCE0[21])? iSOURCE1 << 21 : 64'h00) + ((iSOURCE0[22])? iSOURCE1 << 22 : 64'h00) + ((iSOURCE0[23])? iSOURCE1 << 23 : 64'h00)
+((iSOURCE0[24])? iSOURCE1 << 24 : 64'h00) + ((iSOURCE0[25])? iSOURCE1 << 25 : 64'h00) + ((iSOURCE0[26])? iSOURCE1 << 26 : 64'h00) + ((iSOURCE0[27])? iSOURCE1 << 27 : 64'h00)
+((iSOURCE0[28])? iSOURCE1 << 28 : 64'h00) + ((iSOURCE0[29])? iSOURCE1 << 29 : 64'h00) + ((iSOURCE0[30])? iSOURCE1 << 30 : 64'h00) + ((iSOURCE0[31])? iSOURCE1 << 31 : 64'h00);
/****************************************
Assign
****************************************/
assign oDATA = w_tmp_out;
assign oHSF = w_tmp_out[31];
assign oHOF = w_tmp_out[32] ^ w_tmp_out[31];
assign oHCF = w_tmp_out[32];
assign oHPF = w_tmp_out[0];
assign oHZF = (w_tmp_out[32:0] == {33{1'b0}})? 1'b1 : 1'b0;
assign oLSF = w_tmp_out[32];
assign oLOF = w_tmp_out[63];
assign oLCF = 1'b0;
assign oLPF = w_tmp_out[32];
assign oLZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_hd__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK,
D ,
DE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V |
`timescale 1ns / 1ps
/*
-- Module Name: Input Queue
-- Description: Estructura FIFO. El modulo permite el intercambio de
medio de almacenamiento. Por ejemplo, el uso del diseño
registerFile_distRAM.v implementa un banco de registros
que utiliza de manera exclusiva bloques de memoria
distribuida en FPGAs de Xilinx.
Las banderas de full/empty estan deshabilitadas ya que
la informacion almacenada es auto regulada por el
mecanismo de creditos.
-- Dependencies: -- system.vh
-- fifo_control.v
-- registerFile_distRAM.v (** intercambiable)
-- Parameters: -- CHANNEL_WIDTH: Ancho de palabra de los canales
de comunicacion entre routers.
-- BUFFER_DEPTH: Numero de direcciones en la
estructura de memoria.
-- ADDR_WIDTH: Numero de bits requerido para
representar el espacio de
direcciones del elemento de
memoria del FIFO.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 07 de Junio 2015
*/
`include "system.vh"
module fifo
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire write_strobe_din,
input wire read_strobe_din,
input wire [`CHANNEL_WIDTH-1:0] write_data_din,
// -- outputs ------------------------------------------------ >>>>>
output wire full_dout,
output wire empty_dout,
output wire [`CHANNEL_WIDTH-1:0] read_data_dout
);
// --- Definiciones Locales -------------------------------------- >>>>>
localparam ADDR_WIDTH = clog2(`BUFFER_DEPTH);
/*
-- Instancia :: Unidad de Control de FIFO
-- Descripcion: Implementacion de estructura de control para FIFO.
Incluye punteros para el camculo de la direccion a
escribir y a leer.
*/
// -- Unidad de Control -------------------------------------- >>>>>
wire [ADDR_WIDTH-1:0] write_addr;
wire [ADDR_WIDTH-1:0] read_addr;
wire write_enable;
fifo_control_unit fifo_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs ----------------------------------------- >>>>>
.write_strobe_din (write_strobe_din),
.read_strobe_din (read_strobe_din),
// -- outputs ---------------------------------------- >>>>>
.full_dout (full_dout),
.empty_dout (empty_dout),
.write_addr_dout (write_addr),
.read_addr_dout (read_addr)
);
assign write_enable = write_strobe_din & ~full_dout;
/*
-- Instancia :: Banco de registros
-- Descripcion: Elemento de almacenamiento del FIFO. Puede intercambiar
la implementacion del banco de memoria (Memoria
Distribuida / Bloque de Memoria).
*/
// -- Banco de Registros ------------------------------------- >>>>>
register_file register_file
(
.clk(clk),
// -- inputs ------------------------------------- >>>>>
.write_strobe_din (write_enable),
.write_address_din (write_addr),
.write_data_din (write_data_din),
.read_address_din (read_addr),
// -- outputs ------------------------------------ >>>>>
.read_data_dout (read_data_dout)
);
// -- Codigo no sintetizable ------------------------------------ >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
wire [`CHANNEL_WIDTH-1:0] read_data;
wire full;
wire empty;
fifo buffer_de_paquetes
(
.clk (clk),
.reset (reset),
// -- inputs --------------------------------------------- >>>>>
.write_strobe_din (write_strobe),
.read_strobe_din (read_strobe),
.write_data_din (write_data),
// -- outputs -------------------------------------------- >>>>>
.full_dout (full),
.empty_dout (empty),
.read_data_dout (read_data)
);
*/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_s_no_pg/sky130_fd_sc_hs__u_df_p_s_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dfstp (
CLK ,
D ,
Q ,
SET_B,
VPWR ,
VGND
);
// Module ports
input CLK ;
input D ;
output Q ;
input SET_B;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_BEHAVIORAL_V |
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/**
* Testbench for rcswitch_reveive.
*
* I use this with iverilog and gtkwave:
*
* iverilog -o rcswitch.vvp clockdiv.v rcswitch.v rcswitch_receive_tb.v
* ./rcswitch_receive.vvp
* gtkwace rcswitch_receive.vcd
*/
module rcswitch_test;
reg in;
initial begin
#0 in = 1;
// Garbage
#30 in = 1; // 1000 - 1
#10 in = 0;
#22 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 2
#10 in = 0;
#30 in = 1; // 1000
#11 in = 0;
// Sync 10000000_00000000_00000000_00000000
#30 in = 1; // 1000 - 1
#10 in = 0;
#30 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 2
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 3
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 4
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
// Address 10001000_10001000_10001000_10001000_10001000
#10 in = 1; // 1000 - 1
#18 in = 0;
#30 in = 1; // 1000
#08 in = 0;
#30 in = 1; // 1000 - 2
#10 in = 0;
#25 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 3
#10 in = 0;
#22 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 4
#10 in = 0;
#30 in = 1; // 1000
#11 in = 0;
#30 in = 1; // 1000 - 5
#10 in = 0;
#30 in = 1; // 1000
#10 in = 0;
// Channel 10001000_10001110_10001110_10001110_10001110
#30 in = 1; // 1000 - 1
#17 in = 0;
#30 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 2
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
#10 in = 1; // 1000 - 3
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
#10 in = 1; // 1000 - 4
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
#10 in = 1; // 1000 - 5
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
// Stat 10001110_10001000
#10 in = 1; // 1000 - 1
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
#10 in = 1; // 1000 - 2
#10 in = 0;
#30 in = 1; // 1000
#10 in = 0;
// Sync 10000000_00000000_00000000_00000000
#30 in = 1; // 1000 - 1
#10 in = 0;
#30 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 2
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 3
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 4
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#100 $finish;
end
// clock
reg clk = 0;
always #1 clk = !clk;
wire [31:0] count_h;
wire [31:0] count_l;
wire detected;
tri_state_detect tsd_inst (
.clk(clk),
.rst(1'b0),
.in(in),
.count_h(count_h),
.count_l(count_l),
.detected(detected)
);
initial
begin
$dumpfile("rcswitch_pt.vcd");
$dumpvars(0, tsd_inst);
end
always @(posedge detected) begin
$display("Pulse with H=%d, L=%d detected.", count_h, count_l);
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_AsyncResetRegVec_36(
input clock,
input reset,
input [2:0] io_d,
output [2:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire T_8;
wire T_9;
wire T_10;
wire [1:0] T_11;
wire [2:0] T_12;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
assign io_q = T_12;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = {reg_2_q,reg_1_q};
assign T_12 = {T_11,reg_0_q};
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_add.list"
`include "top.v"
module top_test_add;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH : 0] expected_output = 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Add test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Add test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
expected_output <= expected_output + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O221AI_PP_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_PP_SYMBOL_V
|
module DCM_BUFG (input I, input RST_N, output O);
wire CLKFB_IN;
wire GND_BIT;
wire [6:0] GND_BUS_7;
wire [15:0] GND_BUS_16;
wire RST_P;
assign GND_BIT = 0;
assign GND_BUS_7 = 7'b0000000;
assign GND_BUS_16 = 16'b0000000000000000;
assign RST_P = !RST_N;
assign O = CLKFB_IN;
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_ADV DCM_ADV_INST (.CLKFB(CLKFB_IN),
.CLKIN(I),
.DADDR(GND_BUS_7[6:0]),
.DCLK(GND_BIT),
.DEN(GND_BIT),
.DI(GND_BUS_16[15:0]),
.DWE(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_P),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.DO(),
.DRDY(),
.LOCKED(LOCKED_OUT),
.PSDONE());
defparam DCM_ADV_INST.CLK_FEEDBACK = "1X";
defparam DCM_ADV_INST.CLKDV_DIVIDE = 2.0;
defparam DCM_ADV_INST.CLKFX_DIVIDE = 1;
defparam DCM_ADV_INST.CLKFX_MULTIPLY = 4;
defparam DCM_ADV_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_ADV_INST.CLKIN_PERIOD = 8.000;
defparam DCM_ADV_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_ADV_INST.DCM_AUTOCALIBRATION = "TRUE";
defparam DCM_ADV_INST.DCM_PERFORMANCE_MODE = "MAX_SPEED";
defparam DCM_ADV_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_ADV_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_ADV_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_ADV_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_ADV_INST.FACTORY_JF = 16'hF0F0;
defparam DCM_ADV_INST.PHASE_SHIFT = 0;
defparam DCM_ADV_INST.STARTUP_WAIT = "FALSE";
defparam DCM_ADV_INST.SIM_DEVICE = "VIRTEX5";
endmodule
|
module commutation(
clk,
enable_i,
reset_i,
advance_i,
direction_i,
break_i,
align_i,
state_o
);
input wire clk, enable_i, reset_i, advance_i, direction_i, break_i, align_i;
reg[2:0] state_number;
output wire[3:0] state_o;
reg[3:0] state_table[7:0];
always @(posedge clk) begin
if (reset_i) begin
state_number <= 0;
state_table[0] <= 4'b0110;
state_table[1] <= 4'b0100;
state_table[2] <= 4'b1100;
state_table[3] <= 4'b1000;
state_table[4] <= 4'b1010;
state_table[5] <= 4'b0010;
state_table[6] <= 4'b0000;
state_table[7] <= 4'b1110;
end else if(enable_i) begin
if(advance_i && direction_i) begin
if(state_number == 5) begin
state_number <= 0;
end else begin
state_number <= state_number + 1;
end
end else if (advance_i && !direction_i) begin
if(state_number == 0) begin
state_number <= 5;
end else begin
state_number <= state_number - 1;
end
end else begin
state_number <= state_number;
end
if(break_i) begin
state_number <= 6;
end
if(align_i) begin
state_number <= 7;
end
end
end
assign state_o = state_table[state_number];
endmodule
|
/*
* Titor - Barrel Processor - Binary to unary decoder
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Decoder
`else
`define INC_Decoder
`timescale 1 ns / 100 ps
// Combinational Module
module Decoder (
address,
bitline,
enable,
);
parameter LOG_SIZE=0;
`include "definition/Definition.v"
input [LOG_SIZE-1:0] address;
output reg [(1<<LOG_SIZE)-1:0] bitline;
input enable;
always @(*) begin
if(!enable) begin bitline <= 0;
end else begin bitline <= (1<<address);
end
end
endmodule
`endif
|
module ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output reg[3:0] CU, input MFC, Reset,Clk, input [31:0] IR,input [3:0] SR);
reg [4:0] State, NextState;
task registerTask;
input [17:0] signals;
//6 7 8 12 14 16
fork
//#2 set the alu signals
#2 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = {signals[17],1'b0,signals[15],1'b0,signals[13],1'b0,signals[11:9],1'b0,1'b0,1'b0,signals[5:0]};
//#4 set the register signals
#4 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
//#6 let data be saved
#6 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
join
endtask
always @ (negedge Clk, posedge Reset)
if (Reset) begin
State <= 5'b00001;ALUSTORE = 0 ; IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;CU=0; opcode=5'b10010;end
else
State <= NextState;
/*
STATUS REGISTER FLAGS
WE FETCH INSTRUCTIONS 8BITS AT A TIME 8BIT DATAPATH
31. Negative, N = (ADD)&&(A[31]==B[31])&&(A[31]!=OUT[31]) || (SUB)
30. Zero, Z = OUT == 0
29. Carry, C = CARRY
28. Overflow, V = OVERFLOW
END
*/
always @ (State, MFC)
case (State)
5'b00000 : NextState = 5'b00000;
5'b00001 : if(MFC) NextState = 5'b10001 ; else NextState = 5'b00010;
5'b00010 : NextState = 5'b00011; // goto stall cycle if not ready
5'b00011 : if(MFC)NextState = 5'b00100; else NextState = 5'b00011;
5'b00100 : NextState = 5'b00101;
5'b00101 : case(IR[31:28])//Decode Begin
4'b0000: if(SR[2]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0001: if(SR[2]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0010: if(SR[1]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0011: if(SR[1]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0100: if(SR[3]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0101: if(SR[3]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0110: if(SR[0]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0111: if(SR[0]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b1000: if(SR[1]==1&SR[2]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b1001: if(SR[1]==0|SR[2]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b1010: if(SR[3]==SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1011: if(SR[3]!=SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1100: if(SR[2]==0&SR[3]==SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1101: if(SR[2]==1|SR[3]!=SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1110: NextState = 5'b00110;
endcase
5'b00110 : case(IR[27:25])
3'b000,3'b001:NextState = 5'b00111;
3'b010,3'b011:NextState = 5'b01000;//Load/Store operation 1
3'b101:NextState = 5'b0001;//branch operation 1
default:NextState = 5'b0001;
endcase
5'b00111 : NextState = 5'b00001; // Data operation 1
5'b01000 : NextState = 5'b00001; //Load/Store operation 1
5'b01001 : NextState = 5'b01010;
5'b01010 : NextState = 5'b01011;
5'b01011 : NextState = 5'b01100;
5'b01100 : NextState = 5'b01101;
5'b01101 : NextState = 5'b01110;
5'b01110 : NextState = 5'b01111;
5'b01111 : NextState = 5'b10000;
5'b10000 : NextState = 5'b10001;
5'b10001 : if(MFC) NextState = 5'b10001 ; else NextState = 5'b00010; // Stall State MFC Already Up
endcase
always @ (State, MFC)
case (State)
5'b00000 : begin end
5'b00001 : begin ALUSTORE = 1 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 1 ; CU=4'hf;opcode=5'b10010;end // send pc to mar: ircu = 1 cu = 1111,MARLOAD = 1
5'b00010 : begin ALUSTORE = 1 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 1 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 1 ; WORD_BYTE= 1 ;READ_WRITE= 1 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10001;end // increment pc : loadpc = 1 ircu = 1 cu = 1111 op = 17
5'b00011 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 1 ; WORD_BYTE= 1 ;READ_WRITE= 1 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10010;end // wait for MFC: MFA = 1 LOADIR = 1 read_write = 1 word_byte = 1
5'b00100 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 1 ;MBRLOAD= 0 ;MBRSTORE= 1 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10010;end // transfer data to IR
5'b00101 : begin ALUSTORE = 1 ;IR_CU=1 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'h0;end // Check status codes
5'b00110 : begin ALUSTORE = 0 ;IR_CU= 1 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;end // Decode instruction type and set out signals
5'b00111 : begin ALUSTORE = 1 ;IR_CU= 1 ; RFLOAD= 1 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;opcode = {1'b0,IR[24:21]};end //Data Operation 1
5'b01000 : begin end //Load/Store operation 1
5'b01001 : begin end
5'b01010 : begin end
5'b01011 : begin end
5'b01100 : begin end
5'b01101 : begin end
5'b01110 : begin end
5'b01111 : begin end
5'b10000 : begin end
5'b10001 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10001;end // Stall State Purpusely Left Empty MFC Already Up
/*branch and load_store instruction*/
default : begin end
endcase
endmodule |
module OT11_27(
clk,
rst_n,
in,
bomb,
in_valid1,
hit,
in_valid2,
out_valid,
out
);
// in,out put
input clk;
input rst_n;
input [7:0] in;
input [7:0] bomb;
input in_valid1;
input [5:0] hit;
input in_valid2;
output reg out_valid;
output reg [6:0] out;
// parameter
parameter IDLE=0, INPUT=1, OPER=2, OUTPUT=3;
// wire, reg
reg [1:0] cState, nState;
reg [5:0] h [9:0];
reg [7:0] b [7:0];
reg [7:0] r [7:0];
wire [7:0] blockNum;
reg [7:0] initBlockNum;
reg [3:0] cnt;
reg [3:0] i;
// conbinational circlk
assign blockNum = b[0][0]+b[0][1]+b[0][2]+b[0][3]+b[0][4]+b[0][5]+b[0][6]+b[0][7]+
b[1][0]+b[1][1]+b[1][2]+b[1][3]+b[1][4]+b[1][5]+b[1][6]+b[1][7]+
b[2][0]+b[2][1]+b[2][2]+b[2][3]+b[2][4]+b[2][5]+b[2][6]+b[2][7]+
b[3][0]+b[3][1]+b[3][2]+b[3][3]+b[3][4]+b[3][5]+b[3][6]+b[3][7]+
b[4][0]+b[4][1]+b[4][2]+b[4][3]+b[4][4]+b[4][5]+b[4][6]+b[4][7]+
b[5][0]+b[5][1]+b[5][2]+b[5][3]+b[5][4]+b[5][5]+b[5][6]+b[5][7]+
b[6][0]+b[6][1]+b[6][2]+b[6][3]+b[6][4]+b[6][5]+b[6][6]+b[6][7]+
b[7][0]+b[7][1]+b[7][2]+b[7][3]+b[7][4]+b[7][5]+b[7][6]+b[7][7];
// finite state machine
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) cState <= IDLE;
else cState <= nState;
end
always@(*)
begin
case(cState)
IDLE: begin
if(in_valid1) nState = INPUT;
else nState = IDLE;
end
INPUT: begin
if(!in_valid2) nState = OPER;
else nState = INPUT;
end
OPER: begin
if(cnt == 9) nState = OUTPUT;
else nState = OPER;
end
OUTPUT: nState = IDLE;
default: nState = IDLE;
endcase
end
// sequencial circket
// cnt
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) cnt <= 0;
else begin
case(cState)
IDLE: begin
if(nState == INPUT && in_valid1) cnt <= 1;
else cnt <= 0;
end
INPUT: begin
if(in_valid2) cnt <= cnt+1;
else cnt <= 0;
end
OPER: cnt <= cnt+1;
OUTPUT: cnt <= cnt;
default: cnt <= cnt;
endcase
end
end
// initBlockNum
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) initBlockNum <= 0;
else begin
case(cState)
IDLE: initBlockNum <= 0;
INPUT: initBlockNum <= initBlockNum;
OPER: begin
if(!cnt) initBlockNum <= blockNum;
else initBlockNum <= initBlockNum;
end
OUTPUT: initBlockNum <= initBlockNum;
default: initBlockNum <= initBlockNum;
endcase
end
end
// h
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) for(i=0;i<10;i=i+1) h[i] <= 0;
else begin
case(cState)
IDLE: begin
for(i=1;i<10;i=i+1) h[i] <= 0;
if(nState == INPUT && in_valid2) h[0] <= hit;
else h[0] <= 0;
end
INPUT: h[cnt] <= hit;
OPER: for(i=0;i<10;i=i+1) h[i] <= h[i];
OUTPUT: for(i=0;i<10;i=i+1) h[i] <= h[i];
default: for(i=0;i<10;i=i+1) h[i] <= h[i];
endcase
end
end
// b
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) for(i=0;i<8;i=i+1) b[i] <= 0;
else begin
case(cState)
IDLE: begin
for(i=1;i<8;i=i+1) b[i] <= 0;
if(nState == INPUT && in_valid1) b[0] <= in;
else b[0] <= 0;
end
INPUT: begin
if(in_valid1) b[cnt] <= in;
else for(i=0;i<8;i=i+1) b[i] <= b[i];
end
OPER: begin
b[h[cnt]/8][h[cnt]%8] <= 0;
if(r[h[cnt]/8][h[cnt]%8]) begin
if(h[cnt]/8+1 < 8 && h[cnt]/8+1 >= 0 && h[cnt]%8 < 8 && h[cnt]%8 >= 0) b[h[cnt]/8+1][h[cnt]%8] <= 0; else b[h[cnt]/8+1][h[cnt]%8] <= b[h[cnt]/8+1][h[cnt]%8];
if(h[cnt]/8-1 < 8 && h[cnt]/8-1 >= 0 && h[cnt]%8 < 8 && h[cnt]%8 >= 0) b[h[cnt]/8-1][h[cnt]%8] <= 0; else b[h[cnt]/8-1][h[cnt]%8] <= b[h[cnt]/8-1][h[cnt]%8];
if(h[cnt]/8 < 8 && h[cnt]/8 >= 0 && h[cnt]%8+1 < 8 && h[cnt]%8+1 >= 0) b[h[cnt]/8][h[cnt]%8+1] <= 0; else b[h[cnt]/8][h[cnt]%8+1] <= b[h[cnt]/8][h[cnt]%8+1];
if(h[cnt]/8 < 8 && h[cnt]/8 >= 0 && h[cnt]%8-1 < 8 && h[cnt]%8-1 >= 0) b[h[cnt]/8][h[cnt]%8-1] <= 0; else b[h[cnt]/8][h[cnt]%8-1] <= b[h[cnt]/8][h[cnt]%8-1];
if(h[cnt]/8+1 < 8 && h[cnt]/8+1 >= 0 && h[cnt]%8-1 < 8 && h[cnt]%8-1 >= 0) b[h[cnt]/8+1][h[cnt]%8-1] <= 0; else b[h[cnt]/8+1][h[cnt]%8-1] <= b[h[cnt]/8+1][h[cnt]%8-1];
if(h[cnt]/8-1 < 8 && h[cnt]/8-1 >= 0 && h[cnt]%8-1 < 8 && h[cnt]%8-1 >= 0) b[h[cnt]/8-1][h[cnt]%8-1] <= 0; else b[h[cnt]/8-1][h[cnt]%8-1] <= b[h[cnt]/8-1][h[cnt]%8-1];
if(h[cnt]/8+1 < 8 && h[cnt]/8+1 >= 0 && h[cnt]%8+1 < 8 && h[cnt]%8+1 >= 0) b[h[cnt]/8+1][h[cnt]%8+1] <= 0; else b[h[cnt]/8+1][h[cnt]%8+1] <= b[h[cnt]/8+1][h[cnt]%8+1];
if(h[cnt]/8-1 < 8 && h[cnt]/8-1 >= 0 && h[cnt]%8+1 < 8 && h[cnt]%8+1 >= 0) b[h[cnt]/8-1][h[cnt]%8+1] <= 0; else b[h[cnt]/8-1][h[cnt]%8+1] <= b[h[cnt]/8-1][h[cnt]%8+1];
end
end
OUTPUT: for(i=0;i<8;i=i+1) b[i] <= b[i];
default: for(i=0;i<8;i=i+1) b[i] <= b[i];
endcase
end
end
// r
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) for(i=0;i<8;i=i+1) r[i] <= 0;
else begin
case(cState)
IDLE: begin
for(i=1;i<8;i=i+1) r[i] <= 0;
if(nState == INPUT && in_valid1) r[0] <= bomb;
else r[0] <= 0;
end
INPUT: begin
if(in_valid1) r[cnt] <= bomb;
else for(i=0;i<8;i=i+1) r[i] <= r[i];
end
OPER: begin
r[h[cnt]/8][h[cnt]%8] <= 0;
if(r[h[cnt]/8][h[cnt]%8]) begin
if(h[cnt]/8+1 < 8 && h[cnt]/8+1 >= 0 && h[cnt]%8 < 8 && h[cnt]%8 >= 0) r[h[cnt]/8+1][h[cnt]%8] <= 0; else r[h[cnt]/8+1][h[cnt]%8] <= r[h[cnt]/8+1][h[cnt]%8];
if(h[cnt]/8-1 < 8 && h[cnt]/8-1 >= 0 && h[cnt]%8 < 8 && h[cnt]%8 >= 0) r[h[cnt]/8-1][h[cnt]%8] <= 0; else r[h[cnt]/8-1][h[cnt]%8] <= r[h[cnt]/8-1][h[cnt]%8];
if(h[cnt]/8 < 8 && h[cnt]/8 >= 0 && h[cnt]%8+1 < 8 && h[cnt]%8+1 >= 0) r[h[cnt]/8][h[cnt]%8+1] <= 0; else r[h[cnt]/8][h[cnt]%8+1] <= r[h[cnt]/8][h[cnt]%8+1];
if(h[cnt]/8 < 8 && h[cnt]/8 >= 0 && h[cnt]%8-1 < 8 && h[cnt]%8-1 >= 0) r[h[cnt]/8][h[cnt]%8-1] <= 0; else r[h[cnt]/8][h[cnt]%8-1] <= r[h[cnt]/8][h[cnt]%8-1];
if(h[cnt]/8+1 < 8 && h[cnt]/8+1 >= 0 && h[cnt]%8-1 < 8 && h[cnt]%8-1 >= 0) r[h[cnt]/8+1][h[cnt]%8-1] <= 0; else r[h[cnt]/8+1][h[cnt]%8-1] <= r[h[cnt]/8+1][h[cnt]%8-1];
if(h[cnt]/8-1 < 8 && h[cnt]/8-1 >= 0 && h[cnt]%8-1 < 8 && h[cnt]%8-1 >= 0) r[h[cnt]/8-1][h[cnt]%8-1] <= 0; else r[h[cnt]/8-1][h[cnt]%8-1] <= r[h[cnt]/8-1][h[cnt]%8-1];
if(h[cnt]/8+1 < 8 && h[cnt]/8+1 >= 0 && h[cnt]%8+1 < 8 && h[cnt]%8+1 >= 0) r[h[cnt]/8+1][h[cnt]%8+1] <= 0; else r[h[cnt]/8+1][h[cnt]%8+1] <= r[h[cnt]/8+1][h[cnt]%8+1];
if(h[cnt]/8-1 < 8 && h[cnt]/8-1 >= 0 && h[cnt]%8+1 < 8 && h[cnt]%8+1 >= 0) r[h[cnt]/8-1][h[cnt]%8+1] <= 0; else r[h[cnt]/8-1][h[cnt]%8+1] <= r[h[cnt]/8-1][h[cnt]%8+1];
end
end
OUTPUT: for(i=0;i<8;i=i+1) r[i] <= r[i];
default: for(i=0;i<8;i=i+1) r[i] <= r[i];
endcase
end
end
// out_valid
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) out_valid <= 0;
else begin
case(cState)
IDLE: out_valid <= 0;
INPUT: out_valid <= 0;
OPER: out_valid <= 0;
OUTPUT: out_valid <= 1;
default: out_valid <= out_valid;
endcase
end
end
// out
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) out <= 0;
else begin
case(cState)
IDLE: out <= 0;
INPUT: out <= out;
OPER: out <= out;
OUTPUT: out <= initBlockNum-blockNum;
default: out <= out;
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/07/04 14:03:17
// Design Name:
// Module Name: clock_50Hz
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_50Hz(clk,rst_n,out_50Hz,out_50Hz_pulse);
input clk,rst_n;
output reg out_50Hz,out_50Hz_pulse;
reg [31:0] counter;
always @ (posedge clk or negedge rst_n)
if (!rst_n) begin
out_50Hz_pulse <= 0;
out_50Hz <= 0;
counter <= 0;
end
else begin //clk=100MHz
if (counter >= 32'd1_999_999) begin
counter <= 0;
out_50Hz_pulse <= 1;
out_50Hz <= 1;
end
else begin
if (counter < 32'd1_000_000) out_50Hz <= 1;
else if (counter < 32'd2_000_000) out_50Hz <= 0;
counter <= counter + 1;
out_50Hz_pulse <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog wrapper for lpflow_inputisolatch with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_inputisolatch.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_inputisolatch_1 (
Q ,
D ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_inputisolatch base (
.Q(Q),
.D(D),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_inputisolatch_1 (
Q ,
D ,
SLEEP_B
);
output Q ;
input D ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_inputisolatch base (
.Q(Q),
.D(D),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_4_V
`define SKY130_FD_SC_HS__NOR3_4_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3_4 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_4_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_64x14.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x14(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 14;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [1:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [1:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x14_bist artisan_ssp(
`else
art_hssp_64x14 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x14 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x14_bist vs_ssp(
`else
vs_hdsp_64x14 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({2'b00, di[13:0]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[13:0]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
RAMB16_S18 ramb16_s18(
.CLK(clk),
.SSR(rst),
.ADDR({4'b0000, addr}),
.DI({2'b00, di[13:0]}),
.DIP(2'b00),
.EN(ce),
.WE(we),
.DO({unconnected, doq[13:0]}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_2_V
`define SKY130_FD_SC_MS__A21OI_2_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21oi_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_2_V
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 15
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 15;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 15;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 200;
parameter gMEM_IF_TRCD_NS = 15.0;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 160.0;
parameter gMEM_IF_TRP_NS = 15.0;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NOR2_PP_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_PP_SYMBOL_V
|
//
// Generated by Bluespec Compiler, version 2014.02.beta1 (build 33429, 2014-02-14)
//
// On Tue May 6 09:19:25 EDT 2014
//
//
// Ports:
// Name I/O size props
// s_axi_AWREADY O 1 reg
// s_axi_WREADY O 1 reg
// s_axi_BVALID O 1
// s_axi_BRESP O 2 reg
// s_axi_ARREADY O 1 reg
// s_axi_RVALID O 1
// s_axi_RDATA O 32 reg
// s_axi_RRESP O 2 reg
// upads_rts O 1 const
// upads_tx O 1 reg
// s_axi_aclk I 1 clock
// s_axi_aresetn I 1 reset
// s_axi_AWADDR I 32 reg
// s_axi_AWPROT I 3 reg
// s_axi_WDATA I 32 reg
// s_axi_WSTRB I 4 reg
// s_axi_ARADDR I 32 reg
// s_axi_ARPROT I 3 reg
// upads_cts_arg I 1 reg
// upads_rx_arg I 1 reg
// s_axi_AWVALID I 1
// s_axi_WVALID I 1
// s_axi_BREADY I 1
// s_axi_ARVALID I 1
// s_axi_RREADY I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkAXBLUART(s_axi_aclk,
s_axi_aresetn,
s_axi_AWVALID,
s_axi_AWREADY,
s_axi_AWADDR,
s_axi_AWPROT,
s_axi_WVALID,
s_axi_WREADY,
s_axi_WDATA,
s_axi_WSTRB,
s_axi_BVALID,
s_axi_BREADY,
s_axi_BRESP,
s_axi_ARVALID,
s_axi_ARREADY,
s_axi_ARADDR,
s_axi_ARPROT,
s_axi_RVALID,
s_axi_RREADY,
s_axi_RDATA,
s_axi_RRESP,
upads_rts,
upads_tx,
upads_cts_arg,
upads_rx_arg);
input s_axi_aclk;
input s_axi_aresetn;
// action method s_axi_mAWVALID
input s_axi_AWVALID;
// value method s_axi_sAWREADY
output s_axi_AWREADY;
// action method s_axi_mAWADDR
input [31 : 0] s_axi_AWADDR;
// action method s_axi_mAWPROT
input [2 : 0] s_axi_AWPROT;
// action method s_axi_mWVALID
input s_axi_WVALID;
// value method s_axi_sWREADY
output s_axi_WREADY;
// action method s_axi_mWDATA
input [31 : 0] s_axi_WDATA;
// action method s_axi_mWSTRB
input [3 : 0] s_axi_WSTRB;
// value method s_axi_sBVALID
output s_axi_BVALID;
// action method s_axi_mBREADY
input s_axi_BREADY;
// value method s_axi_sBRESP
output [1 : 0] s_axi_BRESP;
// action method s_axi_mARVALID
input s_axi_ARVALID;
// value method s_axi_sARREADY
output s_axi_ARREADY;
// action method s_axi_mARADDR
input [31 : 0] s_axi_ARADDR;
// action method s_axi_mARPROT
input [2 : 0] s_axi_ARPROT;
// value method s_axi_sRVALID
output s_axi_RVALID;
// action method s_axi_mRREADY
input s_axi_RREADY;
// value method s_axi_sRDATA
output [31 : 0] s_axi_RDATA;
// value method s_axi_sRRESP
output [1 : 0] s_axi_RRESP;
// value method upads_rts
output upads_rts;
// value method upads_tx
output upads_tx;
// action method upads_cts
input upads_cts_arg;
// action method upads_rx
input upads_rx_arg;
// signals for module outputs
wire [31 : 0] s_axi_RDATA;
wire [1 : 0] s_axi_BRESP, s_axi_RRESP;
wire s_axi_ARREADY,
s_axi_AWREADY,
s_axi_BVALID,
s_axi_RVALID,
s_axi_WREADY,
upads_rts,
upads_tx;
// inlined wires
wire [35 : 0] a4l_a4wrData_data_wire_wget;
wire [34 : 0] a4l_a4rdAddr_data_wire_wget, a4l_a4wrAddr_data_wire_wget;
wire [33 : 0] a4l_a4rdResp_fifof_x_wire_wget;
wire [31 : 0] a4ls_rdAddr_w_wget, a4ls_wrAddr_w_wget, a4ls_wrData_w_wget;
wire [3 : 0] a4ls_wrStrb_w_wget;
wire [2 : 0] a4ls_rdProt_w_wget, a4ls_wrProt_w_wget;
wire [1 : 0] a4l_a4wrResp_fifof_x_wire_wget;
wire a4l_a4rdAddr_enq_enq_whas,
a4l_a4rdAddr_enq_valid_whas,
a4l_a4rdResp_deq_deq_whas,
a4l_a4rdResp_deq_ready_whas,
a4l_a4rdResp_fifof_dequeueing_whas,
a4l_a4rdResp_fifof_enqueueing_whas,
a4l_a4rdResp_fifof_x_wire_whas,
a4l_a4wrAddr_enq_enq_whas,
a4l_a4wrAddr_enq_valid_whas,
a4l_a4wrData_enq_enq_whas,
a4l_a4wrData_enq_valid_whas,
a4l_a4wrResp_deq_deq_whas,
a4l_a4wrResp_deq_ready_whas,
a4l_a4wrResp_fifof_dequeueing_whas,
a4l_a4wrResp_fifof_enqueueing_whas,
a4l_a4wrResp_fifof_x_wire_whas,
a4ls_rdAddrVal_w_wget,
a4ls_rdAddrVal_w_whas,
a4ls_rdAddr_w_whas,
a4ls_rdProt_w_whas,
a4ls_rdRespRdy_w_wget,
a4ls_rdRespRdy_w_whas,
a4ls_wrAddrVal_w_wget,
a4ls_wrAddrVal_w_whas,
a4ls_wrAddr_w_whas,
a4ls_wrDataVal_w_wget,
a4ls_wrDataVal_w_whas,
a4ls_wrData_w_whas,
a4ls_wrProt_w_whas,
a4ls_wrRespRdy_w_wget,
a4ls_wrRespRdy_w_whas,
a4ls_wrStrb_w_whas;
// register a4l_a4rdResp_fifof_cntr_r
reg [1 : 0] a4l_a4rdResp_fifof_cntr_r;
wire [1 : 0] a4l_a4rdResp_fifof_cntr_r_D_IN;
wire a4l_a4rdResp_fifof_cntr_r_EN;
// register a4l_a4rdResp_fifof_q_0
reg [33 : 0] a4l_a4rdResp_fifof_q_0;
reg [33 : 0] a4l_a4rdResp_fifof_q_0_D_IN;
wire a4l_a4rdResp_fifof_q_0_EN;
// register a4l_a4rdResp_fifof_q_1
reg [33 : 0] a4l_a4rdResp_fifof_q_1;
reg [33 : 0] a4l_a4rdResp_fifof_q_1_D_IN;
wire a4l_a4rdResp_fifof_q_1_EN;
// register a4l_a4wrResp_fifof_cntr_r
reg [1 : 0] a4l_a4wrResp_fifof_cntr_r;
wire [1 : 0] a4l_a4wrResp_fifof_cntr_r_D_IN;
wire a4l_a4wrResp_fifof_cntr_r_EN;
// register a4l_a4wrResp_fifof_q_0
reg [1 : 0] a4l_a4wrResp_fifof_q_0;
reg [1 : 0] a4l_a4wrResp_fifof_q_0_D_IN;
wire a4l_a4wrResp_fifof_q_0_EN;
// register a4l_a4wrResp_fifof_q_1
reg [1 : 0] a4l_a4wrResp_fifof_q_1;
wire [1 : 0] a4l_a4wrResp_fifof_q_1_D_IN;
wire a4l_a4wrResp_fifof_q_1_EN;
// register r0
reg [31 : 0] r0;
wire [31 : 0] r0_D_IN;
wire r0_EN;
// register r4
reg [31 : 0] r4;
wire [31 : 0] r4_D_IN;
wire r4_EN;
// register r8
reg [31 : 0] r8;
wire [31 : 0] r8_D_IN;
wire r8_EN;
// register rC
reg [31 : 0] rC;
wire [31 : 0] rC_D_IN;
wire rC_EN;
// register uartInited
reg uartInited;
wire uartInited_D_IN, uartInited_EN;
// register uartTxtP
reg [5 : 0] uartTxtP;
wire [5 : 0] uartTxtP_D_IN;
wire uartTxtP_EN;
// ports of submodule a4l_a4rdAddr_fifof
wire [34 : 0] a4l_a4rdAddr_fifof_D_IN, a4l_a4rdAddr_fifof_D_OUT;
wire a4l_a4rdAddr_fifof_CLR,
a4l_a4rdAddr_fifof_DEQ,
a4l_a4rdAddr_fifof_EMPTY_N,
a4l_a4rdAddr_fifof_ENQ,
a4l_a4rdAddr_fifof_FULL_N;
// ports of submodule a4l_a4wrAddr_fifof
wire [34 : 0] a4l_a4wrAddr_fifof_D_IN, a4l_a4wrAddr_fifof_D_OUT;
wire a4l_a4wrAddr_fifof_CLR,
a4l_a4wrAddr_fifof_DEQ,
a4l_a4wrAddr_fifof_EMPTY_N,
a4l_a4wrAddr_fifof_ENQ,
a4l_a4wrAddr_fifof_FULL_N;
// ports of submodule a4l_a4wrData_fifof
wire [35 : 0] a4l_a4wrData_fifof_D_IN, a4l_a4wrData_fifof_D_OUT;
wire a4l_a4wrData_fifof_CLR,
a4l_a4wrData_fifof_DEQ,
a4l_a4wrData_fifof_EMPTY_N,
a4l_a4wrData_fifof_ENQ,
a4l_a4wrData_fifof_FULL_N;
// ports of submodule bluart
wire [15 : 0] bluart_setClkDiv_put;
wire [7 : 0] bluart_rxChar_get,
bluart_rxLevel,
bluart_txChar_put,
bluart_txLevel;
wire bluart_EN_rxChar_get,
bluart_EN_setClkDiv_put,
bluart_EN_txChar_put,
bluart_RDY_rxChar_get,
bluart_RDY_txChar_put,
bluart_pads_cts_arg,
bluart_pads_rts,
bluart_pads_rx_arg,
bluart_pads_tx;
// rule scheduling signals
wire CAN_FIRE_RL_a4l_cfwr,
WILL_FIRE_RL_a4l_a4rdResp_fifof_both,
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr,
WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr,
WILL_FIRE_RL_a4l_a4wrResp_fifof_both,
WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr,
WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr,
WILL_FIRE_RL_a4l_cfrd,
WILL_FIRE_RL_a4l_cfwr,
WILL_FIRE_RL_init_uart_text;
// inputs to muxes for submodule ports
reg [7 : 0] MUX_bluart_txChar_put_1__VAL_2;
wire [33 : 0] MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1,
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_2,
MUX_a4l_a4rdResp_fifof_q_1_write_1__VAL_2;
wire [1 : 0] MUX_a4l_a4rdResp_fifof_cntr_r_write_1__VAL_2,
MUX_a4l_a4wrResp_fifof_cntr_r_write_1__VAL_2,
MUX_a4l_a4wrResp_fifof_q_0_write_1__VAL_2;
wire MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_1,
MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_2,
MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_1,
MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_2,
MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_1,
MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_2,
MUX_bluart_txChar_put_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h6172, v__h6591, v__h6623;
reg [31 : 0] v__h6246;
reg [7 : 0] put__h3600;
wire [31 : 0] rdat__h6330, rdat__h6336, v__h6367, v__h6388;
wire [5 : 0] x__h3644;
wire [1 : 0] a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60,
a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27;
wire _dfoo1, _dfoo3, _dfoo5, _dfoo7;
// value method s_axi_sAWREADY
assign s_axi_AWREADY = a4l_a4wrAddr_fifof_FULL_N ;
// value method s_axi_sWREADY
assign s_axi_WREADY = a4l_a4wrData_fifof_FULL_N ;
// value method s_axi_sBVALID
assign s_axi_BVALID = a4l_a4wrResp_fifof_cntr_r != 2'd0 ;
// value method s_axi_sBRESP
assign s_axi_BRESP = a4l_a4wrResp_fifof_q_0 ;
// value method s_axi_sARREADY
assign s_axi_ARREADY = a4l_a4rdAddr_fifof_FULL_N ;
// value method s_axi_sRVALID
assign s_axi_RVALID = a4l_a4rdResp_fifof_cntr_r != 2'd0 ;
// value method s_axi_sRDATA
assign s_axi_RDATA = a4l_a4rdResp_fifof_q_0[31:0] ;
// value method s_axi_sRRESP
assign s_axi_RRESP = a4l_a4rdResp_fifof_q_0[33:32] ;
// value method upads_rts
assign upads_rts = bluart_pads_rts ;
// value method upads_tx
assign upads_tx = bluart_pads_tx ;
// submodule a4l_a4rdAddr_fifof
FIFO2 #(.width(32'd35),
.guarded(32'd1)) a4l_a4rdAddr_fifof(.RST(s_axi_aresetn),
.CLK(s_axi_aclk),
.D_IN(a4l_a4rdAddr_fifof_D_IN),
.ENQ(a4l_a4rdAddr_fifof_ENQ),
.DEQ(a4l_a4rdAddr_fifof_DEQ),
.CLR(a4l_a4rdAddr_fifof_CLR),
.D_OUT(a4l_a4rdAddr_fifof_D_OUT),
.FULL_N(a4l_a4rdAddr_fifof_FULL_N),
.EMPTY_N(a4l_a4rdAddr_fifof_EMPTY_N));
// submodule a4l_a4wrAddr_fifof
FIFO2 #(.width(32'd35),
.guarded(32'd1)) a4l_a4wrAddr_fifof(.RST(s_axi_aresetn),
.CLK(s_axi_aclk),
.D_IN(a4l_a4wrAddr_fifof_D_IN),
.ENQ(a4l_a4wrAddr_fifof_ENQ),
.DEQ(a4l_a4wrAddr_fifof_DEQ),
.CLR(a4l_a4wrAddr_fifof_CLR),
.D_OUT(a4l_a4wrAddr_fifof_D_OUT),
.FULL_N(a4l_a4wrAddr_fifof_FULL_N),
.EMPTY_N(a4l_a4wrAddr_fifof_EMPTY_N));
// submodule a4l_a4wrData_fifof
FIFO2 #(.width(32'd36),
.guarded(32'd1)) a4l_a4wrData_fifof(.RST(s_axi_aresetn),
.CLK(s_axi_aclk),
.D_IN(a4l_a4wrData_fifof_D_IN),
.ENQ(a4l_a4wrData_fifof_ENQ),
.DEQ(a4l_a4wrData_fifof_DEQ),
.CLR(a4l_a4wrData_fifof_CLR),
.D_OUT(a4l_a4wrData_fifof_D_OUT),
.FULL_N(a4l_a4wrData_fifof_FULL_N),
.EMPTY_N(a4l_a4wrData_fifof_EMPTY_N));
// submodule bluart
mkBLUART bluart(.CLK(s_axi_aclk),
.RST_N(s_axi_aresetn),
.pads_cts_arg(bluart_pads_cts_arg),
.pads_rx_arg(bluart_pads_rx_arg),
.setClkDiv_put(bluart_setClkDiv_put),
.txChar_put(bluart_txChar_put),
.EN_setClkDiv_put(bluart_EN_setClkDiv_put),
.EN_txChar_put(bluart_EN_txChar_put),
.EN_rxChar_get(bluart_EN_rxChar_get),
.RDY_setClkDiv_put(),
.txLevel(bluart_txLevel),
.RDY_txLevel(),
.rxLevel(bluart_rxLevel),
.RDY_rxLevel(),
.RDY_txChar_put(bluart_RDY_txChar_put),
.rxChar_get(bluart_rxChar_get),
.RDY_rxChar_get(bluart_RDY_rxChar_get),
.pads_rts(bluart_pads_rts),
.pads_tx(bluart_pads_tx));
// rule RL_a4l_cfrd
assign WILL_FIRE_RL_a4l_cfrd =
a4l_a4rdResp_fifof_cntr_r != 2'd2 &&
a4l_a4rdAddr_fifof_EMPTY_N &&
(a4l_a4rdAddr_fifof_D_OUT[7:0] != 8'h30 ||
bluart_rxLevel == 8'd0 ||
bluart_RDY_rxChar_get) ;
// rule RL_init_uart_text
assign WILL_FIRE_RL_init_uart_text = bluart_RDY_txChar_put && !uartInited ;
// rule RL_a4l_cfwr
assign CAN_FIRE_RL_a4l_cfwr =
a4l_a4wrResp_fifof_cntr_r != 2'd2 &&
a4l_a4wrAddr_fifof_EMPTY_N &&
a4l_a4wrData_fifof_EMPTY_N &&
(a4l_a4wrAddr_fifof_D_OUT[7:0] != 8'h2C ||
bluart_RDY_txChar_put) ;
assign WILL_FIRE_RL_a4l_cfwr =
CAN_FIRE_RL_a4l_cfwr && !WILL_FIRE_RL_init_uart_text ;
// rule RL_a4l_a4wrResp_fifof_incCtr
assign WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr =
WILL_FIRE_RL_a4l_cfwr && WILL_FIRE_RL_a4l_cfwr &&
!a4l_a4wrResp_fifof_dequeueing_whas ;
// rule RL_a4l_a4wrResp_fifof_decCtr
assign WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr =
a4l_a4wrResp_fifof_dequeueing_whas && !WILL_FIRE_RL_a4l_cfwr ;
// rule RL_a4l_a4wrResp_fifof_both
assign WILL_FIRE_RL_a4l_a4wrResp_fifof_both =
WILL_FIRE_RL_a4l_cfwr && a4l_a4wrResp_fifof_dequeueing_whas &&
WILL_FIRE_RL_a4l_cfwr ;
// rule RL_a4l_a4rdResp_fifof_incCtr
assign WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr =
WILL_FIRE_RL_a4l_cfrd && WILL_FIRE_RL_a4l_cfrd &&
!a4l_a4rdResp_fifof_dequeueing_whas ;
// rule RL_a4l_a4rdResp_fifof_decCtr
assign WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr =
a4l_a4rdResp_fifof_dequeueing_whas && !WILL_FIRE_RL_a4l_cfrd ;
// rule RL_a4l_a4rdResp_fifof_both
assign WILL_FIRE_RL_a4l_a4rdResp_fifof_both =
WILL_FIRE_RL_a4l_cfrd && a4l_a4rdResp_fifof_dequeueing_whas &&
WILL_FIRE_RL_a4l_cfrd ;
// inputs to muxes for submodule ports
assign MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_1 =
WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr &&
a4l_a4rdResp_fifof_cntr_r == 2'd0 ;
assign MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_2 =
WILL_FIRE_RL_a4l_a4rdResp_fifof_both && _dfoo7 ;
assign MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_1 =
WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr &&
a4l_a4rdResp_fifof_cntr_r == 2'd1 ;
assign MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_2 =
WILL_FIRE_RL_a4l_a4rdResp_fifof_both && _dfoo5 ;
assign MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_1 =
WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr &&
a4l_a4wrResp_fifof_cntr_r == 2'd0 ;
assign MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_2 =
WILL_FIRE_RL_a4l_a4wrResp_fifof_both && _dfoo3 ;
assign MUX_bluart_txChar_put_1__SEL_1 =
WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h2C ;
assign MUX_a4l_a4rdResp_fifof_cntr_r_write_1__VAL_2 =
a4l_a4rdResp_fifof_cntr_r + 2'd1 ;
assign MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 = { 2'd0, v__h6246 } ;
assign MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_2 =
(a4l_a4rdResp_fifof_cntr_r == 2'd1) ?
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 :
a4l_a4rdResp_fifof_q_1 ;
assign MUX_a4l_a4rdResp_fifof_q_1_write_1__VAL_2 =
(a4l_a4rdResp_fifof_cntr_r == 2'd2) ?
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 :
34'd0 ;
assign MUX_a4l_a4wrResp_fifof_cntr_r_write_1__VAL_2 =
a4l_a4wrResp_fifof_cntr_r + 2'd1 ;
assign MUX_a4l_a4wrResp_fifof_q_0_write_1__VAL_2 =
(a4l_a4wrResp_fifof_cntr_r == 2'd1) ?
2'd0 :
a4l_a4wrResp_fifof_q_1 ;
always@(uartTxtP or put__h3600)
begin
case (uartTxtP)
6'd0, 6'd42: MUX_bluart_txChar_put_1__VAL_2 = 8'h0D;
6'd1, 6'd43: MUX_bluart_txChar_put_1__VAL_2 = 8'h0A;
default: MUX_bluart_txChar_put_1__VAL_2 = put__h3600;
endcase
end
// inlined wires
assign a4l_a4wrResp_fifof_x_wire_wget = 2'd0 ;
assign a4l_a4wrResp_fifof_x_wire_whas = WILL_FIRE_RL_a4l_cfwr ;
assign a4l_a4rdResp_fifof_x_wire_wget =
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 ;
assign a4l_a4rdResp_fifof_x_wire_whas = WILL_FIRE_RL_a4l_cfrd ;
assign a4ls_wrAddrVal_w_wget = 1'd1 ;
assign a4ls_wrAddrVal_w_whas = s_axi_AWVALID ;
assign a4ls_wrDataVal_w_wget = 1'd1 ;
assign a4ls_wrDataVal_w_whas = s_axi_WVALID ;
assign a4ls_wrRespRdy_w_wget = 1'd1 ;
assign a4ls_wrRespRdy_w_whas = s_axi_BREADY ;
assign a4ls_rdAddrVal_w_wget = 1'd1 ;
assign a4ls_rdAddrVal_w_whas = s_axi_ARVALID ;
assign a4ls_rdRespRdy_w_wget = 1'd1 ;
assign a4ls_rdRespRdy_w_whas = s_axi_RREADY ;
assign a4ls_wrAddr_w_wget = s_axi_AWADDR ;
assign a4ls_wrAddr_w_whas = 1'd1 ;
assign a4ls_wrProt_w_wget = s_axi_AWPROT ;
assign a4ls_wrProt_w_whas = 1'd1 ;
assign a4ls_wrData_w_wget = s_axi_WDATA ;
assign a4ls_wrData_w_whas = 1'd1 ;
assign a4ls_wrStrb_w_wget = s_axi_WSTRB ;
assign a4ls_wrStrb_w_whas = 1'd1 ;
assign a4ls_rdAddr_w_wget = s_axi_ARADDR ;
assign a4ls_rdAddr_w_whas = 1'd1 ;
assign a4ls_rdProt_w_wget = s_axi_ARPROT ;
assign a4ls_rdProt_w_whas = 1'd1 ;
assign a4l_a4wrAddr_enq_valid_whas = s_axi_AWVALID ;
assign a4l_a4wrAddr_enq_enq_whas = 1'b0 ;
assign a4l_a4wrData_enq_valid_whas = s_axi_WVALID ;
assign a4l_a4wrData_enq_enq_whas = 1'b0 ;
assign a4l_a4wrResp_fifof_enqueueing_whas = WILL_FIRE_RL_a4l_cfwr ;
assign a4l_a4wrResp_fifof_dequeueing_whas =
a4l_a4wrResp_fifof_cntr_r != 2'd0 && s_axi_BREADY ;
assign a4l_a4wrResp_deq_ready_whas = s_axi_BREADY ;
assign a4l_a4wrResp_deq_deq_whas = 1'b0 ;
assign a4l_a4rdAddr_enq_valid_whas = s_axi_ARVALID ;
assign a4l_a4rdAddr_enq_enq_whas = 1'b0 ;
assign a4l_a4rdResp_fifof_enqueueing_whas = WILL_FIRE_RL_a4l_cfrd ;
assign a4l_a4rdResp_fifof_dequeueing_whas =
a4l_a4rdResp_fifof_cntr_r != 2'd0 && s_axi_RREADY ;
assign a4l_a4rdResp_deq_ready_whas = s_axi_RREADY ;
assign a4l_a4rdResp_deq_deq_whas = 1'b0 ;
assign a4l_a4wrAddr_data_wire_wget = { s_axi_AWPROT, s_axi_AWADDR } ;
assign a4l_a4wrData_data_wire_wget = { s_axi_WSTRB, s_axi_WDATA } ;
assign a4l_a4rdAddr_data_wire_wget = { s_axi_ARPROT, s_axi_ARADDR } ;
// register a4l_a4rdResp_fifof_cntr_r
assign a4l_a4rdResp_fifof_cntr_r_D_IN =
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr ?
a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60 :
MUX_a4l_a4rdResp_fifof_cntr_r_write_1__VAL_2 ;
assign a4l_a4rdResp_fifof_cntr_r_EN =
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr ||
WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr ;
// register a4l_a4rdResp_fifof_q_0
always@(MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_1 or
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 or
MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_2 or
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_2 or
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr or a4l_a4rdResp_fifof_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_1:
a4l_a4rdResp_fifof_q_0_D_IN =
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1;
MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_2:
a4l_a4rdResp_fifof_q_0_D_IN =
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_2;
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr:
a4l_a4rdResp_fifof_q_0_D_IN = a4l_a4rdResp_fifof_q_1;
default: a4l_a4rdResp_fifof_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign a4l_a4rdResp_fifof_q_0_EN =
WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr &&
a4l_a4rdResp_fifof_cntr_r == 2'd0 ||
WILL_FIRE_RL_a4l_a4rdResp_fifof_both && _dfoo7 ||
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr ;
// register a4l_a4rdResp_fifof_q_1
always@(MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_1 or
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 or
MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_2 or
MUX_a4l_a4rdResp_fifof_q_1_write_1__VAL_2 or
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_1:
a4l_a4rdResp_fifof_q_1_D_IN =
MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1;
MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_2:
a4l_a4rdResp_fifof_q_1_D_IN =
MUX_a4l_a4rdResp_fifof_q_1_write_1__VAL_2;
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr:
a4l_a4rdResp_fifof_q_1_D_IN = 34'd0;
default: a4l_a4rdResp_fifof_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign a4l_a4rdResp_fifof_q_1_EN =
WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr &&
a4l_a4rdResp_fifof_cntr_r == 2'd1 ||
WILL_FIRE_RL_a4l_a4rdResp_fifof_both && _dfoo5 ||
WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr ;
// register a4l_a4wrResp_fifof_cntr_r
assign a4l_a4wrResp_fifof_cntr_r_D_IN =
WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr ?
a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27 :
MUX_a4l_a4wrResp_fifof_cntr_r_write_1__VAL_2 ;
assign a4l_a4wrResp_fifof_cntr_r_EN =
WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr ||
WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr ;
// register a4l_a4wrResp_fifof_q_0
always@(MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_1 or
MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_2 or
MUX_a4l_a4wrResp_fifof_q_0_write_1__VAL_2 or
WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr or a4l_a4wrResp_fifof_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_1:
a4l_a4wrResp_fifof_q_0_D_IN = 2'd0;
MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_2:
a4l_a4wrResp_fifof_q_0_D_IN =
MUX_a4l_a4wrResp_fifof_q_0_write_1__VAL_2;
WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr:
a4l_a4wrResp_fifof_q_0_D_IN = a4l_a4wrResp_fifof_q_1;
default: a4l_a4wrResp_fifof_q_0_D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign a4l_a4wrResp_fifof_q_0_EN =
WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr &&
a4l_a4wrResp_fifof_cntr_r == 2'd0 ||
WILL_FIRE_RL_a4l_a4wrResp_fifof_both && _dfoo3 ||
WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr ;
// register a4l_a4wrResp_fifof_q_1
assign a4l_a4wrResp_fifof_q_1_D_IN = 2'd0 ;
assign a4l_a4wrResp_fifof_q_1_EN =
WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr &&
a4l_a4wrResp_fifof_cntr_r == 2'd1 ||
WILL_FIRE_RL_a4l_a4wrResp_fifof_both && _dfoo1 ||
WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr ;
// register r0
assign r0_D_IN = a4l_a4wrData_fifof_D_OUT[31:0] ;
assign r0_EN =
WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h0 ;
// register r4
assign r4_D_IN = a4l_a4wrData_fifof_D_OUT[31:0] ;
assign r4_EN =
WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h04 ;
// register r8
assign r8_D_IN = a4l_a4wrData_fifof_D_OUT[31:0] ;
assign r8_EN =
WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h08 ;
// register rC
assign rC_D_IN = a4l_a4wrData_fifof_D_OUT[31:0] ;
assign rC_EN =
WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h0C ;
// register uartInited
assign uartInited_D_IN = 1'd1 ;
assign uartInited_EN = WILL_FIRE_RL_init_uart_text && uartTxtP == 6'd43 ;
// register uartTxtP
assign uartTxtP_D_IN = uartTxtP + 6'd1 ;
assign uartTxtP_EN = WILL_FIRE_RL_init_uart_text ;
// submodule a4l_a4rdAddr_fifof
assign a4l_a4rdAddr_fifof_D_IN = a4l_a4rdAddr_data_wire_wget ;
assign a4l_a4rdAddr_fifof_ENQ = a4l_a4rdAddr_fifof_FULL_N && s_axi_ARVALID ;
assign a4l_a4rdAddr_fifof_DEQ = WILL_FIRE_RL_a4l_cfrd ;
assign a4l_a4rdAddr_fifof_CLR = 1'b0 ;
// submodule a4l_a4wrAddr_fifof
assign a4l_a4wrAddr_fifof_D_IN = a4l_a4wrAddr_data_wire_wget ;
assign a4l_a4wrAddr_fifof_ENQ = a4l_a4wrAddr_fifof_FULL_N && s_axi_AWVALID ;
assign a4l_a4wrAddr_fifof_DEQ = WILL_FIRE_RL_a4l_cfwr ;
assign a4l_a4wrAddr_fifof_CLR = 1'b0 ;
// submodule a4l_a4wrData_fifof
assign a4l_a4wrData_fifof_D_IN = a4l_a4wrData_data_wire_wget ;
assign a4l_a4wrData_fifof_ENQ = a4l_a4wrData_fifof_FULL_N && s_axi_WVALID ;
assign a4l_a4wrData_fifof_DEQ = WILL_FIRE_RL_a4l_cfwr ;
assign a4l_a4wrData_fifof_CLR = 1'b0 ;
// submodule bluart
assign bluart_pads_cts_arg = upads_cts_arg ;
assign bluart_pads_rx_arg = upads_rx_arg ;
assign bluart_setClkDiv_put = a4l_a4wrData_fifof_D_OUT[15:0] ;
assign bluart_txChar_put =
MUX_bluart_txChar_put_1__SEL_1 ?
a4l_a4wrData_fifof_D_OUT[7:0] :
MUX_bluart_txChar_put_1__VAL_2 ;
assign bluart_EN_setClkDiv_put =
WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h20 ;
assign bluart_EN_txChar_put =
WILL_FIRE_RL_a4l_cfwr &&
a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h2C ||
WILL_FIRE_RL_init_uart_text ;
assign bluart_EN_rxChar_get =
WILL_FIRE_RL_a4l_cfrd &&
a4l_a4rdAddr_fifof_D_OUT[7:0] == 8'h30 &&
bluart_rxLevel != 8'd0 ;
// remaining internal signals
assign _dfoo1 =
a4l_a4wrResp_fifof_cntr_r != 2'd2 ||
a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
a4l_a4wrResp_fifof_cntr_r != 2'd1 ||
a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27 == 2'd0 ;
assign _dfoo5 =
a4l_a4rdResp_fifof_cntr_r != 2'd2 ||
a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60 == 2'd1 ;
assign _dfoo7 =
a4l_a4rdResp_fifof_cntr_r != 2'd1 ||
a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60 == 2'd0 ;
assign a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60 =
a4l_a4rdResp_fifof_cntr_r - 2'd1 ;
assign a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27 =
a4l_a4wrResp_fifof_cntr_r - 2'd1 ;
assign rdat__h6330 = { 24'd0, bluart_txLevel } ;
assign rdat__h6336 = { 24'd0, bluart_rxLevel } ;
assign v__h6367 = (bluart_rxLevel == 8'd0) ? 32'd0 : v__h6388 ;
assign v__h6388 = { 24'd0, bluart_rxChar_get } ;
assign x__h3644 = uartTxtP - 6'd2 ;
always@(a4l_a4rdAddr_fifof_D_OUT or
v__h6367 or r0 or r4 or r8 or rC or rdat__h6330 or rdat__h6336)
begin
case (a4l_a4rdAddr_fifof_D_OUT[7:0])
8'h0: v__h6246 = r0;
8'h04: v__h6246 = r4;
8'h08: v__h6246 = r8;
8'h0C: v__h6246 = rC;
8'h10: v__h6246 = 32'hDEADBEEF;
8'h14: v__h6246 = 32'hBABECAFE;
8'h18: v__h6246 = 32'hF00DFACE;
8'h1C: v__h6246 = 32'hFEEDC0DE;
8'h24: v__h6246 = rdat__h6330;
8'h28: v__h6246 = rdat__h6336;
default: v__h6246 = v__h6367;
endcase
end
always@(x__h3644)
begin
case (x__h3644)
6'd0, 6'd5, 6'd15: put__h3600 = 8'd65;
6'd1: put__h3600 = 8'd88;
6'd2: put__h3600 = 8'd66;
6'd3, 6'd28, 6'd29: put__h3600 = 8'd76;
6'd4: put__h3600 = 8'd85;
6'd6, 6'd22: put__h3600 = 8'd82;
6'd7: put__h3600 = 8'd84;
6'd8: put__h3600 = 8'd46;
6'd9: put__h3600 = 8'd98;
6'd10, 6'd26: put__h3600 = 8'd115;
6'd11: put__h3600 = 8'd118;
6'd12, 6'd14, 6'd21, 6'd27, 6'd31, 6'd35: put__h3600 = 8'd32;
6'd13: put__h3600 = 8'd45;
6'd16: put__h3600 = 8'd116;
6'd17: put__h3600 = 8'd111;
6'd18: put__h3600 = 8'd109;
6'd19: put__h3600 = 8'd105;
6'd20, 6'd33: put__h3600 = 8'd99;
6'd23: put__h3600 = 8'd117;
6'd24: put__h3600 = 8'd108;
6'd25: put__h3600 = 8'd101;
6'd30: put__h3600 = 8'd67;
6'd32: put__h3600 = 8'd40;
6'd34: put__h3600 = 8'd41;
6'd36: put__h3600 = 8'd50;
6'd37: put__h3600 = 8'd48;
6'd38: put__h3600 = 8'd49;
6'd39: put__h3600 = 8'd52;
default: put__h3600 = 8'b10101010 /* unspecified value */ ;
endcase
end
// handling of inlined registers
always@(posedge s_axi_aclk)
begin
if (s_axi_aresetn == `BSV_RESET_VALUE)
begin
a4l_a4rdResp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
a4l_a4rdResp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0;
a4l_a4rdResp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0;
a4l_a4wrResp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
a4l_a4wrResp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 2'd0;
a4l_a4wrResp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
r0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
r4 <= `BSV_ASSIGNMENT_DELAY 32'd0;
r8 <= `BSV_ASSIGNMENT_DELAY 32'd0;
rC <= `BSV_ASSIGNMENT_DELAY 32'd0;
uartInited <= `BSV_ASSIGNMENT_DELAY 1'd0;
uartTxtP <= `BSV_ASSIGNMENT_DELAY 6'd0;
end
else
begin
if (a4l_a4rdResp_fifof_cntr_r_EN)
a4l_a4rdResp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY
a4l_a4rdResp_fifof_cntr_r_D_IN;
if (a4l_a4rdResp_fifof_q_0_EN)
a4l_a4rdResp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY
a4l_a4rdResp_fifof_q_0_D_IN;
if (a4l_a4rdResp_fifof_q_1_EN)
a4l_a4rdResp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY
a4l_a4rdResp_fifof_q_1_D_IN;
if (a4l_a4wrResp_fifof_cntr_r_EN)
a4l_a4wrResp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY
a4l_a4wrResp_fifof_cntr_r_D_IN;
if (a4l_a4wrResp_fifof_q_0_EN)
a4l_a4wrResp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY
a4l_a4wrResp_fifof_q_0_D_IN;
if (a4l_a4wrResp_fifof_q_1_EN)
a4l_a4wrResp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY
a4l_a4wrResp_fifof_q_1_D_IN;
if (r0_EN) r0 <= `BSV_ASSIGNMENT_DELAY r0_D_IN;
if (r4_EN) r4 <= `BSV_ASSIGNMENT_DELAY r4_D_IN;
if (r8_EN) r8 <= `BSV_ASSIGNMENT_DELAY r8_D_IN;
if (rC_EN) rC <= `BSV_ASSIGNMENT_DELAY rC_D_IN;
if (uartInited_EN)
uartInited <= `BSV_ASSIGNMENT_DELAY uartInited_D_IN;
if (uartTxtP_EN) uartTxtP <= `BSV_ASSIGNMENT_DELAY uartTxtP_D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
a4l_a4rdResp_fifof_cntr_r = 2'h2;
a4l_a4rdResp_fifof_q_0 = 34'h2AAAAAAAA;
a4l_a4rdResp_fifof_q_1 = 34'h2AAAAAAAA;
a4l_a4wrResp_fifof_cntr_r = 2'h2;
a4l_a4wrResp_fifof_q_0 = 2'h2;
a4l_a4wrResp_fifof_q_1 = 2'h2;
r0 = 32'hAAAAAAAA;
r4 = 32'hAAAAAAAA;
r8 = 32'hAAAAAAAA;
rC = 32'hAAAAAAAA;
uartInited = 1'h0;
uartTxtP = 6'h2A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge s_axi_aclk)
begin
#0;
if (s_axi_aresetn != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_a4l_cfrd)
begin
v__h6591 = $time;
#0;
end
if (s_axi_aresetn != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_a4l_cfrd)
$display("[%0d]: %m: AXI4-LITE CONFIG READ Addr:%0x",
v__h6591,
a4l_a4rdAddr_fifof_D_OUT[31:0]);
if (s_axi_aresetn != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_a4l_cfrd)
begin
v__h6623 = $time;
#0;
end
if (s_axi_aresetn != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_a4l_cfrd)
$display("[%0d]: %m: AXI4-LITE CONFIG READ RESPOSNE Data:%0x",
v__h6623,
v__h6246);
if (s_axi_aresetn != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_a4l_cfwr)
begin
v__h6172 = $time;
#0;
end
if (s_axi_aresetn != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_a4l_cfwr)
$display("[%0d]: %m: AXI4-LITE CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h6172,
a4l_a4wrAddr_fifof_D_OUT[31:0],
a4l_a4wrData_fifof_D_OUT[35:32],
a4l_a4wrData_fifof_D_OUT[31:0]);
end
// synopsys translate_on
endmodule // mkAXBLUART
|
module wb_upsizer_tb
(input wb_clk_i,
input wb_rst_i,
output done);
localparam aw = 32;
localparam MEMORY_SIZE_WORDS = 2**10;
localparam DW_IN = 32;
localparam SCALE = 2;
localparam DW_OUT = DW_IN * SCALE;
wire [aw-1:0] wbm_m2s_adr;
wire [DW_IN-1:0] wbm_m2s_dat;
wire [DW_IN/8-1:0] wbm_m2s_sel;
wire wbm_m2s_we ;
wire wbm_m2s_cyc;
wire wbm_m2s_stb;
wire [2:0] wbm_m2s_cti;
wire [1:0] wbm_m2s_bte;
wire [DW_IN-1:0] wbm_s2m_dat;
wire wbm_s2m_ack;
wire wbm_s2m_err;
wire wbm_s2m_rty;
wire [aw-1:0] wbs_m2s_adr;
wire [DW_OUT-1:0] wbs_m2s_dat;
wire [DW_OUT/8-1:0] wbs_m2s_sel;
wire wbs_m2s_we ;
wire wbs_m2s_cyc;
wire wbs_m2s_stb;
wire [2:0] wbs_m2s_cti;
wire [1:0] wbs_m2s_bte;
wire [DW_OUT-1:0] wbs_s2m_dat;
wire wbs_s2m_ack;
wire wbs_s2m_err;
wire wbs_s2m_rty;
wire [31:0] slave_writes;
wire [31:0] slave_reads;
wb_bfm_transactor
#(.MEM_HIGH(MEMORY_SIZE_WORDS-1),
.MEM_LOW (0),
.VERBOSE (0))
wb_bfm_transactor0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wbm_m2s_adr),
.wb_dat_o (wbm_m2s_dat),
.wb_sel_o (wbm_m2s_sel),
.wb_we_o (wbm_m2s_we ),
.wb_cyc_o (wbm_m2s_cyc),
.wb_stb_o (wbm_m2s_stb),
.wb_cti_o (wbm_m2s_cti),
.wb_bte_o (wbm_m2s_bte),
.wb_dat_i (wbm_s2m_dat),
.wb_ack_i (wbm_s2m_ack),
.wb_err_i (wbm_s2m_err),
.wb_rty_i (wbm_s2m_rty),
//Test Control
.done(done));
integer idx;
always @(done) begin
if(done === 1) begin
$display("Average wait times");
$display("Master : %f", ack_delay/num_transactions);
$display("%0d : All tests passed!", $time);
end
end
wb_upsizer
#(.DW_IN (DW_IN),
.SCALE (SCALE))
dut
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
// Master Interface
.wbs_adr_i (wbm_m2s_adr),
.wbs_dat_i (wbm_m2s_dat),
.wbs_sel_i (wbm_m2s_sel),
.wbs_we_i (wbm_m2s_we ),
.wbs_cyc_i (wbm_m2s_cyc),
.wbs_stb_i (wbm_m2s_stb),
.wbs_cti_i (wbm_m2s_cti),
.wbs_bte_i (wbm_m2s_bte),
.wbs_dat_o (wbm_s2m_dat),
.wbs_ack_o (wbm_s2m_ack),
.wbs_err_o (wbm_s2m_err),
.wbs_rty_o (wbm_s2m_rty),
// Wishbone Slave interface
.wbm_adr_o (wbs_m2s_adr),
.wbm_dat_o (wbs_m2s_dat),
.wbm_sel_o (wbs_m2s_sel),
.wbm_we_o (wbs_m2s_we),
.wbm_cyc_o (wbs_m2s_cyc),
.wbm_stb_o (wbs_m2s_stb),
.wbm_cti_o (wbs_m2s_cti),
.wbm_bte_o (wbs_m2s_bte),
.wbm_dat_i (wbs_s2m_dat),
.wbm_ack_i (wbs_s2m_ack),
.wbm_err_i (wbs_s2m_err),
.wbm_rty_i (wbs_s2m_rty));
assign slave_writes = mem.writes;
assign slave_reads = mem.reads;
time start_time;
time ack_delay;
integer num_transactions;
initial begin
ack_delay = 0;
num_transactions = 0;
while(1) begin
@(posedge wbm_m2s_cyc);
start_time = $time;
@(posedge wbm_s2m_ack);
ack_delay = ack_delay + $time-start_time;
num_transactions = num_transactions+1;
end
end
wb_bfm_memory #(.DEBUG (0),
.dw (DW_OUT),
.mem_size_bytes(MEMORY_SIZE_WORDS*(DW_IN/8)))
mem
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (wbs_m2s_cti),
.wb_bte_i (wbs_m2s_bte),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (wbs_s2m_err),
.wb_rty_o (wbs_s2m_rty));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O21BAI_BEHAVIORAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_BEHAVIORAL_V |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module eth_parser
#(parameter DATA_WIDTH = 64,
parameter NUM_QUEUES = 8,
parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES)
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
// --- Interface to process block
output is_arp_pkt,
output is_ip_pkt,
output is_for_us,
output is_broadcast,
output [NUM_QUEUES_WIDTH-1:0] mac_dst_port_num,
input eth_parser_rd_info,
output eth_parser_info_vld,
// --- Interface to preprocess block
input word_MAC_DA_HI,
input word_MAC_DASA,
input word_ETH_IP_VER,
// --- Interface to registers
input [47:0] mac_0, // address of rx queue 0
input [47:0] mac_1, // address of rx queue 1
input [47:0] mac_2, // address of rx queue 2
input [47:0] mac_3, // address of rx queue 3
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------------ Internal Parameter ---------------------------
parameter ETH_ARP = 16'h0806;
parameter ETH_IP = 16'h0800;
parameter IDLE = 0;
parameter DO_SEARCH = 1;
//---------------------- Wires/Regs -------------------------------
reg [47:0] dst_MAC;
reg [47:0] mac_sel;
reg [15:0] ethertype;
reg search_req;
reg state, state_next;
reg [log2(NUM_QUEUES/2):0] mac_count, mac_count_next;
reg wr_en;
reg port_found;
wire broadcast_bit;
//----------------------- Modules ---------------------------------
fallthrough_small_fifo #(.WIDTH(4+NUM_QUEUES_WIDTH), .MAX_DEPTH_BITS(2))
eth_fifo
(.din ({port_found, // is for us
(ethertype==ETH_ARP), // is ARP
(ethertype==ETH_IP), // is IP
(broadcast_bit), // is broadcast
{mac_count[log2(NUM_QUEUES/2)-1:0], 1'b0}}), // dst port num
.wr_en (wr_en), // Write enable
.rd_en (eth_parser_rd_info), // Read the next word
.dout ({is_for_us, is_arp_pkt, is_ip_pkt, is_broadcast, mac_dst_port_num}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------ Logic ----------------------------------
assign eth_parser_info_vld = !empty;
assign broadcast_bit = dst_MAC[40];
always @(*) begin
mac_sel = mac_0;
case(mac_count)
0: mac_sel = 48'h004E46324300; //mac_0; //Deepak hardcoding
1: mac_sel = 48'h004E46324301; //mac_1;
2: mac_sel = 48'h004E46324302; //mac_2;
3: mac_sel = 48'h004E46324303; //mac_3;
4: mac_sel = ~48'h0;
endcase // case(mac_count)
end // always @ (*)
/******************************************************************
* Get the destination, source and ethertype of the pkt
*****************************************************************/
always @(posedge clk) begin
if(reset) begin
dst_MAC <= 0;
ethertype <= 0;
search_req <= 0;
end
else begin
if(word_MAC_DA_HI) begin
dst_MAC[47:16] <= in_data[DATA_WIDTH-1:DATA_WIDTH-32];
end
if(word_MAC_DASA) begin
dst_MAC[15:0] <= in_data[31:16];
end
if(word_ETH_IP_VER) begin
ethertype <= in_data[31:16];
search_req <= 1;
end
else begin
search_req <= 0;
end
end // else: !if(reset)
end // always @ (posedge clk)
/*************************************************************
* check to see if the destination port matches any of our port
* MAC addresses. We need to make sure that this search is
* completed before the end of the packet.
*************************************************************/
always @(*) begin
state_next = state;
mac_count_next = mac_count;
wr_en = 0;
port_found = 0;
case(state)
IDLE: begin
if(search_req) begin
state_next = DO_SEARCH;
mac_count_next = NUM_QUEUES/2;
end
end
DO_SEARCH: begin
mac_count_next = mac_count-1;
//if(mac_sel==dst_MAC || broadcast_bit) begin //deepak -Disable broadcast traffic
if(mac_sel==dst_MAC) begin
wr_en = 1;
state_next = IDLE;
port_found = 1;
end
else if(mac_count == 0) begin
state_next = IDLE;
wr_en = 1;
end
end
endcase // case(state)
end // always @(*)
always @(posedge clk) begin
if(reset) begin
state <= IDLE;
mac_count <= 0;
end
else begin
state <= state_next;
mac_count <= mac_count_next;
end
end
// synthesis translate_off
always @(posedge clk) begin
if(state==DO_SEARCH && word_MAC_DA_HI) begin
$display("%t %m ERROR: Latched new address before the last search was done!", $time);
$stop;
end
end
// synthesis translate_on
endmodule // eth_parser
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