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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// Modifications Copryright (c) 2017 Simon Southwell. All rights reserved.
module SEG7_LUT_4 (oSEG0, oSEG1, oSEG2, oSEG3, iDIG);
input [31:0] iDIG;
output [6:0] oSEG0, oSEG1, oSEG2, oSEG3;
SEG7_LUT u0 (oSEG0, {iDIG[16], iDIG[3:0]} );
SEG7_LUT u1 (oSEG1, {iDIG[17], iDIG[7:4]} );
SEG7_LUT u2 (oSEG2, {iDIG[18], iDIG[11:8]} );
SEG7_LUT u3 (oSEG3, {iDIG[19], iDIG[15:12]});
endmodule
|
// File expr.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module expr(
reset,
sysclk,
ival
);
input reset, sysclk, ival;
wire reset;
wire sysclk;
wire ival;
reg [13:0] foo;
wire [2:0] baz;
reg [22:0] bam;
wire [5:3] out_i;
wire [8:0] input_status;
wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
// drive input status
assign input_status = {foo[9:4],((baz[3:0] & foo[3:0] | (( ~baz[3:0] & bam[3:0]))))};
// drive based on foo
assign out_i = ((enable & ((aux ^ outy)))) | ((debug & dv & ~enable)) | (( ~debug & ~enable & value));
// not drive
always @(negedge reset or negedge sysclk) begin
if((reset != 1'b 0)) begin
foo <= {14{1'b0}};
end else begin
foo[3 * ((2 - 1))] <= (4 * ((1 + 2)));
bam[13:0] <= foo;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_4_V
`define SKY130_FD_SC_LP__ISOBUFSRC_4_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for isobufsrc with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__isobufsrc_4 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__isobufsrc_4 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_4_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module spi #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 2
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire SPI_CLK,
output wire SCLK,
input wire SDO,
output wire SDI,
input wire EXT_START,
output wire SEN,
output wire SLD
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
spi_core #(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES)
) i_spi_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SPI_CLK(SPI_CLK),
.SCLK(SCLK),
.SDO(SDO),
.SDI(SDI),
.EXT_START(EXT_START),
.SEN(SEN),
.SLD(SLD)
);
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-channel allocation arbiter
*
* This VC arbiter simply consists of one arbiter per output-port.
* Each arbiter has np*nv inputs.
*
*/
module NW_vc_arbiter (request,
req_priority,
grant,
vc_allocated,
// vcreq_foroutput,
clk, rst_n);
parameter np=5;
parameter nv=4;
parameter multistage=2;
parameter dynamic_priority_vc_alloc=0;
//parameter type flit_priority_t = flit_pri_t;
input [np-1:0][nv-1:0][np-1:0] request;
input flit_priority_t req_priority [np-1:0][nv-1:0];
output [np-1:0][nv-1:0][np-1:0] grant;
// was VC allocated? previous grant was successful! use new arb. state (make sure things are fair)
input [np-1:0] vc_allocated;
input clk, rst_n;
// inputs and outputs to matrix arbiters
wire [np*nv-1:0] output_req [np-1:0];
wire [np*nv-1:0] output_grant [np-1:0];
genvar ip, vc, op;
generate
for (ip=0; ip<np; ip=ip+1) begin:i
for (vc=0; vc<nv; vc=vc+1) begin:v
for (op=0; op<np; op=op+1) begin:o
// generate inputs to arbiters
assign output_req[op][ip*nv+vc] = (NW_route_valid_turn(ip, op)) ? request[ip][vc][op] : 1'b0;
// put output signals in correct order
assign grant[ip][vc][op]=output_grant[op][ip*nv+vc];
end
end
end
//
// np x np*nv-input matrix arbiters
//
for (op=0; op<np; op=op+1) begin:o2
NW_tree_arbiter #(.multistage(multistage),
.size(np*nv),
.groupsize(nv),
.priority_support(dynamic_priority_vc_alloc)
//,
//.priority_type(flit_priority_t)
) vcarb
(.request(output_req[op]),
.req_priority(req_priority),
.grant(output_grant[op]),
.success(vc_allocated[op]),// be careful
.clk, .rst_n);
// assign vcreq_foroutput[op]=|output_req[op];
end
endgenerate
endmodule // precomp_vc_alloc
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Oct 31 15:07:48 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0],probe27[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [8:0]probe19;
input [7:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [7:0]probe25;
input [3:0]probe26;
input [0:0]probe27;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_LP_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DLATCH_LP_SYMBOL_V
/**
* udp_dlatch$lP: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$lP (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_LP_SYMBOL_V
|
`include "constants.vh"
`default_nettype none
module tag_decoder
(
input wire [`SPECTAG_LEN-1:0] in,
output reg [2:0] out
);
always @ (*) begin
out = 0;
case (in)
5'b00001: out = 0;
5'b00010: out = 1;
5'b00100: out = 2;
5'b01000: out = 3;
5'b10000: out = 4;
default: out = 0;
endcase // case (in)
end
endmodule // tag_decoder
module miss_prediction_fix_table
(
input wire clk,
input wire reset,
output reg [`SPECTAG_LEN-1:0] mpft_valid,
input wire [`SPECTAG_LEN-1:0] value_addr,
output wire [`SPECTAG_LEN-1:0] mpft_value,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prsuccess_tag,
input wire [`SPECTAG_LEN-1:0] setspec1_tag, //inst1_spectag
input wire setspec1_en, //inst1_isbranch & ~inst1_inv
input wire [`SPECTAG_LEN-1:0] setspec2_tag,
input wire setspec2_en
);
reg [`SPECTAG_LEN-1:0] value0;
reg [`SPECTAG_LEN-1:0] value1;
reg [`SPECTAG_LEN-1:0] value2;
reg [`SPECTAG_LEN-1:0] value3;
reg [`SPECTAG_LEN-1:0] value4;
wire [2:0] val_idx;
tag_decoder td(
.in(value_addr),
.out(val_idx)
);
assign mpft_value = {
value4[val_idx],
value3[val_idx],
value2[val_idx],
value1[val_idx],
value0[val_idx]
};
/*
wire [`SPECTAG_LEN-1:0] value0_wdec =
(~setspec1_tag[0] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b00001) ? mpft_valid : 5'b0))) |
(~setspec2_tag[0] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b00001) ? mpft_valid : 5'b0)));
*/
wire [`SPECTAG_LEN-1:0] wdecdata = mpft_valid | (setspec1_en ? setspec1_tag : 0);
wire [`SPECTAG_LEN-1:0] value0_wdec =
(~setspec1_tag[0] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b00001) ? mpft_valid : 5'b0))) |
(~setspec2_tag[0] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b00001) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value1_wdec =
(~setspec1_tag[1] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b00010) ? mpft_valid : 5'b0))) |
(~setspec2_tag[1] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b00010) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value2_wdec =
(~setspec1_tag[2] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b00100) ? mpft_valid : 5'b0))) |
(~setspec2_tag[2] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b00100) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value3_wdec =
(~setspec1_tag[3] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b01000) ? mpft_valid : 5'b0))) |
(~setspec2_tag[3] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b01000) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value4_wdec =
(~setspec1_tag[4] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b10000) ? mpft_valid : 5'b0))) |
(~setspec2_tag[4] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b10000) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value0_wprs =
(prsuccess_tag[0] ? 5'b0 : ~prsuccess_tag);
wire [`SPECTAG_LEN-1:0] value1_wprs =
(prsuccess_tag[1] ? 5'b0 : ~prsuccess_tag);
wire [`SPECTAG_LEN-1:0] value2_wprs =
(prsuccess_tag[2] ? 5'b0 : ~prsuccess_tag);
wire [`SPECTAG_LEN-1:0] value3_wprs =
(prsuccess_tag[3] ? 5'b0 : ~prsuccess_tag);
wire [`SPECTAG_LEN-1:0] value4_wprs =
(prsuccess_tag[4] ? 5'b0 : ~prsuccess_tag);
always @ (posedge clk) begin
if (reset | prmiss) begin
mpft_valid <= 0;
end else if (prsuccess) begin
mpft_valid <= mpft_valid & ~prsuccess_tag;
end else begin
mpft_valid <= mpft_valid |
(setspec1_en ? setspec1_tag : 0) |
(setspec2_en ? setspec2_tag : 0);
end
end
always @ (posedge clk) begin
if (reset | prmiss) begin
value0 <= 0;
value1 <= 0;
value2 <= 0;
value3 <= 0;
value4 <= 0;
end else begin
value0 <= prsuccess ? (value0 & value0_wprs) : (value0 | value0_wdec);
value1 <= prsuccess ? (value1 & value1_wprs) : (value1 | value1_wdec);
value2 <= prsuccess ? (value2 & value2_wprs) : (value2 | value2_wdec);
value3 <= prsuccess ? (value3 & value3_wprs) : (value3 | value3_wdec);
value4 <= prsuccess ? (value4 & value4_wprs) : (value4 | value4_wdec);
end
end
endmodule // miss_prediction_fix_table
`default_nettype wire
|
// file: bd_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_ref_i___200.000______0.000______50.0______114.829_____98.575
// ____aclk____50.000______0.000______50.0______151.636_____98.575
// sys_clk_i___100.000______0.000______50.0______130.958_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module bd_clk_wiz_0_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_ref_i,
output aclk,
output sys_clk_i,
// Status and control signals
input resetn,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_bd_clk_wiz_0_0;
wire clk_in2_bd_clk_wiz_0_0;
IBUF clkin1_ibufg
(.O (clk_in1_bd_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_ref_i_bd_clk_wiz_0_0;
wire aclk_bd_clk_wiz_0_0;
wire sys_clk_i_bd_clk_wiz_0_0;
wire clk_out4_bd_clk_wiz_0_0;
wire clk_out5_bd_clk_wiz_0_0;
wire clk_out6_bd_clk_wiz_0_0;
wire clk_out7_bd_clk_wiz_0_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_bd_clk_wiz_0_0;
wire clkfbout_buf_bd_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (5.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (20),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (10),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_bd_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_ref_i_bd_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (aclk_bd_clk_wiz_0_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (sys_clk_i_bd_clk_wiz_0_0),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_bd_clk_wiz_0_0),
.CLKIN1 (clk_in1_bd_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_bd_clk_wiz_0_0),
.I (clkfbout_bd_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_ref_i),
.I (clk_ref_i_bd_clk_wiz_0_0));
BUFG clkout2_buf
(.O (aclk),
.I (aclk_bd_clk_wiz_0_0));
BUFG clkout3_buf
(.O (sys_clk_i),
.I (sys_clk_i_bd_clk_wiz_0_0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_SYMBOL_V
`define SKY130_FD_SC_LS__O32AI_SYMBOL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o32ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_SYMBOL_V
`define SKY130_FD_SC_HDLL__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_SYMBOL_V
|
`timescale 1ns / 1ps
module SeparadorNumeros
#(parameter stateA = 'b0001, //idle
parameter stateB = 'b0010, //convert
parameter stateC = 'b0100 //send
)
(input [31:0] alu_in,
input start_conversion,
input tx_done,
input clk,
output reg [7:0] value_to_send = 0,
output reg tx_start = 0
);
reg [3:0] diez;
reg [3:0] nueve;
reg [3:0] ocho;
reg [3:0] siete;
reg [3:0] seis;
reg [3:0] cinco;
reg [3:0] cuatro;
reg [3:0] tres;
reg [3:0] dos;
reg [3:0] uno;
reg done_convert = 0;
reg done_send = 0;
reg [3:0] state = stateA;
reg [3:0] next_state = stateA;
integer enviando_valor = 10;
always@(posedge clk)
begin
state = next_state;
end
always@(posedge clk)
begin
case(state)
stateA:
begin
if(!start_conversion) next_state = stateA;
else next_state = stateB;
end
stateB:
begin
if(!done_convert) next_state = stateB;
else next_state = stateC;
end
stateC:
begin
if(!done_send)next_state = stateC;
else next_state = stateA;
end
endcase
end
integer i;
integer retardo = 0;
always@(posedge clk)
begin
if(state == stateA)
begin
done_send = 0;
done_convert = 0;
tx_start = 0;
enviando_valor = 10;
end
if(state == stateB)
begin
diez = 4'd0;
nueve = 4'd0;
ocho = 4'd0;
siete = 4'd0;
seis = 4'd0;
cinco = 4'd0;
cuatro = 4'd0;
tres = 4'd0;
dos = 4'd0;
uno = 4'd0;
for(i=31;i>=0; i=i-1)
begin
if(diez >= 5)
diez = diez + 3;
if(nueve >= 5)
nueve = nueve + 3;
if(ocho >= 5)
ocho = ocho + 3;
if(siete >= 5)
siete = siete + 3;
if(seis >= 5)
seis = seis + 3;
if(cinco >= 5)
cinco = cinco + 3;
if(cuatro >= 5)
cuatro = cuatro + 3;
if(tres >= 5)
tres = tres + 3;
if(dos >= 5)
dos = dos + 3;
if(uno >= 5)
uno = uno + 3;
diez = diez << 1;
diez[0] = nueve[3];
nueve = nueve << 1;
nueve[0] = ocho[3];
ocho = ocho << 1;
ocho[0] = siete[3];
siete = siete << 1;
siete[0] = seis[3];
seis = seis << 1;
seis[0] = cinco[3];
cinco = cinco << 1;
cinco[0] = cuatro[3];
cuatro = cuatro << 1;
cuatro[0] = tres[3];
tres = tres << 1;
tres[0] = dos[3];
dos = dos << 1;
dos[0] = uno[3];
uno = uno << 1;
uno[0] = alu_in[i];
end
done_convert = 1;
end
if(state == stateC)
begin
if(tx_done)
begin
case(enviando_valor)
10:
begin
if(retardo == 0)
begin
value_to_send <= diez + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo - 1;
end
9:
begin
if(retardo == 0)
begin
value_to_send <= nueve + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
8:
begin
if(retardo == 0)
begin
value_to_send <= ocho + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
7:
begin
if(retardo == 0)
begin
value_to_send <= siete + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
6:
begin
if(retardo == 0)
begin
value_to_send <= seis + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
5:
begin
if(retardo == 0)
begin
value_to_send <= cinco + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
4:
begin
if(retardo == 0)
begin
value_to_send <= cuatro + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
3:
begin
if(retardo == 0)
begin
value_to_send <= tres + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
2:
begin
if(retardo == 0)
begin
value_to_send <= dos + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
1:
begin
if(retardo == 0)
begin
value_to_send <= uno + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
default:
begin
tx_start = 0;
enviando_valor = 10;
done_send = 1;
end
endcase
end
else tx_start = 0;
end
end
endmodule
|
`default_nettype wire
module cache_ram_16entry_512bit(
input clock,
input [63:0] byteena_a,
//Write
input wren,
input [3:0] wraddress,
input [511:0] data,
//Read
input [3:0] rdaddress,
output [511:0] q
);
reg [511:0] b_mem[0:15];
always@(posedge clock)begin
if(wren)begin
b_mem[wraddress] <= func_byteena_o(byteena_a, b_mem[wraddress], data);
end
end
function [511:0] func_byteena_o;
input [63:0] func_byteena;
input [511:0] func_current_data;
input [511:0] func_new_data;
reg [511:0] func_local_data;
begin
func_local_data[7:0] = (func_byteena[0])? func_new_data[7:0] : func_current_data[7:0];
func_local_data[15:8] = (func_byteena[1])? func_new_data[15:8] : func_current_data[15:8];
func_local_data[23:16] = (func_byteena[2])? func_new_data[23:16] : func_current_data[23:16];
func_local_data[31:24] = (func_byteena[3])? func_new_data[31:24] : func_current_data[31:24];
func_local_data[39:32] = (func_byteena[4])? func_new_data[39:32] : func_current_data[39:32];
func_local_data[47:40] = (func_byteena[5])? func_new_data[47:40] : func_current_data[47:40];
func_local_data[55:48] = (func_byteena[6])? func_new_data[55:48] : func_current_data[55:48];
func_local_data[63:56] = (func_byteena[7])? func_new_data[63:56] : func_current_data[63:56];
func_local_data[71:64] = (func_byteena[8])? func_new_data[71:64] : func_current_data[71:64];
func_local_data[79:72] = (func_byteena[9])? func_new_data[79:72] : func_current_data[79:72];
func_local_data[87:80] = (func_byteena[10])? func_new_data[87:80] : func_current_data[87:80];
func_local_data[95:88] = (func_byteena[11])? func_new_data[95:88] : func_current_data[95:88];
func_local_data[103:96] = (func_byteena[12])? func_new_data[103:96] : func_current_data[103:96];
func_local_data[111:104] = (func_byteena[13])? func_new_data[111:104] : func_current_data[111:104];
func_local_data[119:112] = (func_byteena[14])? func_new_data[119:112] : func_current_data[119:112];
func_local_data[127:120] = (func_byteena[15])? func_new_data[127:120] : func_current_data[127:120];
func_local_data[135:128] = (func_byteena[16])? func_new_data[135:128] : func_current_data[135:128];
func_local_data[143:136] = (func_byteena[17])? func_new_data[143:136] : func_current_data[143:136];
func_local_data[151:144] = (func_byteena[18])? func_new_data[151:144] : func_current_data[151:144];
func_local_data[159:152] = (func_byteena[19])? func_new_data[159:152] : func_current_data[159:152];
func_local_data[167:160] = (func_byteena[20])? func_new_data[167:160] : func_current_data[167:160];
func_local_data[175:168] = (func_byteena[21])? func_new_data[175:168] : func_current_data[175:168];
func_local_data[183:176] = (func_byteena[22])? func_new_data[183:176] : func_current_data[183:176];
func_local_data[191:184] = (func_byteena[23])? func_new_data[191:184] : func_current_data[191:184];
func_local_data[199:192] = (func_byteena[24])? func_new_data[199:192] : func_current_data[199:192];
func_local_data[207:200] = (func_byteena[25])? func_new_data[207:200] : func_current_data[207:200];
func_local_data[215:208] = (func_byteena[26])? func_new_data[215:208] : func_current_data[215:208];
func_local_data[223:216] = (func_byteena[27])? func_new_data[223:216] : func_current_data[223:216];
func_local_data[231:224] = (func_byteena[28])? func_new_data[231:224] : func_current_data[231:224];
func_local_data[239:232] = (func_byteena[29])? func_new_data[239:232] : func_current_data[239:232];
func_local_data[247:240] = (func_byteena[30])? func_new_data[247:240] : func_current_data[247:240];
func_local_data[255:248] = (func_byteena[31])? func_new_data[255:248] : func_current_data[255:248];
func_local_data[263:256] = (func_byteena[32])? func_new_data[263:256] : func_current_data[263:256];
func_local_data[271:264] = (func_byteena[33])? func_new_data[271:264] : func_current_data[271:264];
func_local_data[279:272] = (func_byteena[34])? func_new_data[279:272] : func_current_data[279:272];
func_local_data[287:280] = (func_byteena[35])? func_new_data[287:280] : func_current_data[287:280];
func_local_data[295:288] = (func_byteena[36])? func_new_data[295:288] : func_current_data[295:288];
func_local_data[303:296] = (func_byteena[37])? func_new_data[303:296] : func_current_data[303:296];
func_local_data[311:304] = (func_byteena[38])? func_new_data[311:304] : func_current_data[311:304];
func_local_data[319:312] = (func_byteena[39])? func_new_data[319:312] : func_current_data[319:312];
func_local_data[327:320] = (func_byteena[40])? func_new_data[327:320] : func_current_data[327:320];
func_local_data[335:328] = (func_byteena[41])? func_new_data[335:328] : func_current_data[335:328];
func_local_data[343:336] = (func_byteena[42])? func_new_data[343:336] : func_current_data[343:336];
func_local_data[351:344] = (func_byteena[43])? func_new_data[351:344] : func_current_data[351:344];
func_local_data[359:352] = (func_byteena[44])? func_new_data[359:352] : func_current_data[359:352];
func_local_data[367:360] = (func_byteena[45])? func_new_data[367:360] : func_current_data[367:360];
func_local_data[375:368] = (func_byteena[46])? func_new_data[375:368] : func_current_data[375:368];
func_local_data[383:376] = (func_byteena[47])? func_new_data[383:376] : func_current_data[383:376];
func_local_data[391:384] = (func_byteena[48])? func_new_data[391:384] : func_current_data[391:384];
func_local_data[399:392] = (func_byteena[49])? func_new_data[399:392] : func_current_data[399:392];
func_local_data[407:400] = (func_byteena[50])? func_new_data[407:400] : func_current_data[407:400];
func_local_data[415:408] = (func_byteena[51])? func_new_data[415:408] : func_current_data[415:408];
func_local_data[423:416] = (func_byteena[52])? func_new_data[423:416] : func_current_data[423:416];
func_local_data[431:424] = (func_byteena[53])? func_new_data[431:424] : func_current_data[431:424];
func_local_data[439:432] = (func_byteena[54])? func_new_data[439:432] : func_current_data[439:432];
func_local_data[447:440] = (func_byteena[55])? func_new_data[447:440] : func_current_data[447:440];
func_local_data[455:448] = (func_byteena[56])? func_new_data[455:448] : func_current_data[455:448];
func_local_data[463:456] = (func_byteena[57])? func_new_data[463:456] : func_current_data[463:456];
func_local_data[471:464] = (func_byteena[58])? func_new_data[471:464] : func_current_data[471:464];
func_local_data[479:472] = (func_byteena[59])? func_new_data[479:472] : func_current_data[479:472];
func_local_data[487:480] = (func_byteena[60])? func_new_data[487:480] : func_current_data[487:480];
func_local_data[495:488] = (func_byteena[61])? func_new_data[495:488] : func_current_data[495:488];
func_local_data[503:496] = (func_byteena[62])? func_new_data[503:496] : func_current_data[503:496];
func_local_data[511:504] = (func_byteena[63])? func_new_data[511:504] : func_current_data[511:504];
func_byteena_o = func_local_data;
end
endfunction
reg [511:0] b_data_buff;
always@(posedge clock)begin
b_data_buff <= b_mem[rdaddress];
end
assign q = b_data_buff;//b_mem[rdaddress];
endmodule
`default_nettype none
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Wed Oct 18 15:15:21 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_stub.v
// Design : ip_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
module ip_design_processing_system7_0_0(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I,
I2C0_SCL_O, I2C0_SCL_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID,
M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID,
M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_CLK1, FCLK_RESET0_N, MIO,
DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB,
DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK,
PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_clk (
clk_in_p,
clk_in_n,
clk);
parameter DEVICE_TYPE = 0;
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
input clk_in_p;
input clk_in_n;
output clk;
// wires
wire clk_ibuf_s;
// instantiations
IBUFGDS i_rx_clk_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_ibuf_s));
generate
if (DEVICE_TYPE == VIRTEX6) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_ibuf_s),
.O (clk));
end else begin
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
module ALU(
output reg [31:0] alu_out,
output flag_z, flag_v, flag_n,
input [31:0] in0, in1, //in0 is rs, in1 can be rt or sign/unsign-extended immediate value
input [4:0] shamt,
input [15:0] perf_cnt, //input from performance counter
input alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3
);
localparam ADD = 4'h0, SUB = 4'h1, LUI = 4'h2, MOV = 4'h3;
localparam AND = 4'h4, SLL = 4'h5, SRA = 4'h6, SRL = 4'h7;
localparam NOT = 4'h8, OR = 4'h9, XOR = 4'ha, ADDB = 4'hb;
localparam ADDBI = 4'hc, SUBB = 4'hd, SUBBI = 4'he, LLDC = 4'hf; //LDC stands for load counters
wire [3:0] alu_ctrl = {alu_ctrl3, alu_ctrl2, alu_ctrl1, alu_ctrl0};
//////wires for shift
wire [31:0] dsll0, dsll1, dsll2, dsll3, dsll4;
wire [31:0] dsrl0, dsrl1, dsrl2, dsrl3, dsrl4;
wire [31:0] dsra0, dsra1, dsra2, dsra3, dsra4;
//////wires for byte-wise arithmetic
wire [8:0] addb0_int, addb1_int, addb2_int, addb3_int;
wire [7:0] addb0, addb1, addb2, addb3;
wire [7:0] subb0, subb1, subb2, subb3;
//////ALU result
always @(alu_ctrl or in0 or in1) begin
case (alu_ctrl)
ADD: alu_out = in0 + in1;
SUB: alu_out = in0 - in1;
LUI: alu_out = {in1[15:0], 16'h0000}; //the concatenation is done before going into ALU
MOV: alu_out = in0;
AND: alu_out = in0 & in1;
SLL: alu_out = dsll4;
SRA: alu_out = dsra4;
SRL: alu_out = dsrl4;
NOT: alu_out = ~in0;
OR: alu_out = in0 | in1;
XOR: alu_out = in0 ^ in1;
ADDB: alu_out = {addb3, addb2, addb1, addb0}; //currently don't care about the correctness of these byte-wise ops
ADDBI: alu_out = {addb3, addb2, addb1, addb0};
SUBB: alu_out = {subb3, subb2, subb1, subb0};
SUBBI: alu_out = {subb3, subb2, subb1, subb0};
LLDC: alu_out = {16'h0000, perf_cnt};
endcase
end
//////flags //////our flag only used in branch instruction, we don't have overflow exception
assign flag_z = ~(|alu_out);
assign flag_n = alu_out[31];
assign flag_v = (in0[31] & in1[31] & ~alu_out[31]) || (~in0[31] & ~in1[31] & alu_out[31]);
///////////////////////////////////////////////////////////////////////////////////////////////
//////////////////log shifter//////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////
//shifter left logically (SLL) block
assign dsll0 = shamt[0] ? {in0[30:0], 1'b0} : in0; //shift left logic/arithmetic
assign dsll1 = shamt[1] ? {dsll0[29:0], 2'b00} : dsll0;
assign dsll2 = shamt[2] ? {dsll1[27:0], 4'h0} : dsll1;
assign dsll3 = shamt[3] ? {dsll2[23:0], 8'h00} : dsll2;
assign dsll4 = shamt[4] ? {dsll3[15:0], 16'h0000} : dsll3;
//SRL block
assign dsrl0 = shamt[0] ? {1'b0, in0[31:1]} : in0; //shift right logically
assign dsrl1 = shamt[1] ? {2'b00, dsrl0[31:2]} : dsrl0;
assign dsrl2 = shamt[2] ? {4'h0, dsrl1[31:4]} : dsrl1;
assign dsrl3 = shamt[3] ? {8'h00, dsrl2[31:8]} : dsrl2;
assign dsrl4 = shamt[4] ? {16'h0000, dsrl3[31:16]} : dsrl3;
//SRA block
assign dsra0 = shamt[0] ? { in0[31], in0[31:1]} : in0;
assign dsra1 = shamt[1] ? { {2{dsra0[31]}} , dsra0[31:2]} : dsra0; //shift right arithmetically
assign dsra2 = shamt[2] ? { {4{dsra1[31]}} , dsra1[31:4]} : dsra1;
assign dsra3 = shamt[3] ? { {8{dsra2[31]}} , dsra2[31:8]} : dsra2;
assign dsra4 = shamt[4] ? { {16{dsra3[31]}} , dsra3[31:16]} : dsra3;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////saturating unsigned arithmetic for byte-wise operation//////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
assign addb0_int = in0[7:0] + in1[7:0];
assign addb1_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[15:8] + in1[15:8];
assign addb2_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[23:16] + in1[23:16];
assign addb3_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[31:24] + in1[31:24];
assign addb0 = addb0_int[8] ? 8'hFF : addb0_int[7:0];
assign addb1 = addb1_int[8] ? 8'hFF : addb1_int[7:0];
assign addb2 = addb2_int[8] ? 8'hFF : addb2_int[7:0];
assign addb3 = addb3_int[8] ? 8'hFF : addb3_int[7:0];
assign subb0 = in0[7:0] - in1[7:0];
assign subb1 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[15:8] - in1[15:8];
assign subb2 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[23:16] - in1[23:16];
assign subb3 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[31:24] - in1[31:24];
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@brief Reports a fixed 32-bit identifier in the USER1 register.
We could use USERCODE for this, but that would prevent it from being used by an end-user design.
*/
module JtagUserIdentifier #(
parameter IDCODE_VID = 24'h000000,
parameter IDCODE_PID = 8'h00
)();
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The TAP interface for discovery (DEBUG_IDCODE register)
reg[31:0] tap_shreg = 0;
wire tap_active;
wire tap_shift;
wire tap_clear;
wire tap_tck_raw;
wire tap_tck_bufh;
//The TAP itself
JtagTAP #(
.USER_INSTRUCTION(1)
) tap_tap (
.instruction_active(tap_active),
.state_capture_dr(tap_clear),
.state_reset(),
.state_runtest(),
.state_shift_dr(tap_shift),
.state_update_dr(),
.tck(tap_tck_raw),
.tck_gated(),
.tms(),
.tdi(),
.tdo(tap_shreg[0])
);
//Buffer the clock b/c ISE is derpy and often won't instantiate a buffer (woo skew!)
//TODO: according to comments in older code BUFHs here sometimes won't work in spartan6?
ClockBuffer #(
.TYPE("LOCAL"),
.CE("NO")
) tap_tck_clkbuf (
.clkin(tap_tck_raw),
.clkout(tap_tck_bufh),
.ce(1'b1)
);
//The actual shift register
always @(posedge tap_tck_bufh) begin
if(!tap_active) begin
end
else if(tap_clear)
tap_shreg <= {IDCODE_VID, IDCODE_PID};
else if(tap_shift)
tap_shreg <= {1'b1, tap_shreg[31:1]};
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module sends and receives data from the audio's and TV in's *
* control registers for the chips on Altera's DE1 board. Plus, it can *
* send and receive data from the TRDB_DC2 and TRDB_LCM add-on modules. *
* *
******************************************************************************/
module audio_and_video_config (
// Inputs
clk,
reset,
// Bidirectionals
I2C_SDAT,
I2C_SCLK
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter I2C_BUS_MODE = 1'b0;
parameter CFG_TYPE = 8'h01;
parameter MIN_ROM_ADDRESS = 6'h00;
parameter MAX_ROM_ADDRESS = 6'h32;
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'd149;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'd73;
parameter AUD_SAMPLE_CTRL = 9'd0;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
// Bidirectionals
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire clk_400KHz;
wire start_and_stop_en;
wire change_output_bit_en;
wire enable_clk;
wire send_start_bit;
wire send_stop_bit;
wire [7:0] auto_init_data;
wire auto_init_transfer_data;
wire auto_init_start_bit;
wire auto_init_stop_bit;
wire auto_init_complete;
wire auto_init_error;
wire transfer_data;
wire transfer_complete;
wire i2c_ack;
wire [7:0] i2c_received_data;
// Internal Registers
reg [7:0] data_to_transfer;
reg [2:0] num_bits_to_transfer;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
begin
data_to_transfer <= 8'h00;
num_bits_to_transfer <= 3'h0;
end
else
if (auto_init_complete == 1'b0)
begin
data_to_transfer <= auto_init_data;
num_bits_to_transfer <= 3'h7;
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign transfer_data = auto_init_transfer_data;
assign send_start_bit = auto_init_start_bit;
assign send_stop_bit = auto_init_stop_bit;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_Slow_Clock_Generator Clock_Generator_400KHz (
// Inputs
.clk (clk),
.reset (reset),
.enable_clk (enable_clk),
// Bidirectionals
// Outputs
.new_clk (clk_400KHz),
.rising_edge (),
.falling_edge (),
.middle_of_high_level (start_and_stop_en),
.middle_of_low_level (change_output_bit_en)
);
defparam
Clock_Generator_400KHz.COUNTER_BITS = 10, // 4, //
Clock_Generator_400KHz.COUNTER_INC = 10'h001; // 4'h1; //
Altera_UP_I2C_AV_Auto_Initialize Auto_Initialize (
// Inputs
.clk (clk),
.reset (reset),
.clear_error (1'b1),
.ack (i2c_ack),
.transfer_complete (transfer_complete),
// Bidirectionals
// Outputs
.data_out (auto_init_data),
.transfer_data (auto_init_transfer_data),
.send_start_bit (auto_init_start_bit),
.send_stop_bit (auto_init_stop_bit),
.auto_init_complete (auto_init_complete),
.auto_init_error (auto_init_error)
);
defparam
Auto_Initialize.MIN_ROM_ADDRESS = MIN_ROM_ADDRESS,
Auto_Initialize.MAX_ROM_ADDRESS = MAX_ROM_ADDRESS,
Auto_Initialize.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Initialize.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Initialize.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Initialize.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Initialize.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Initialize.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Initialize.AUD_POWER = AUD_POWER,
Auto_Initialize.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Initialize.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Initialize.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
Altera_UP_I2C I2C_Controller (
// Inputs
.clk (clk),
.reset (reset),
.clear_ack (1'b1),
.clk_400KHz (clk_400KHz),
.start_and_stop_en (start_and_stop_en),
.change_output_bit_en (change_output_bit_en),
.send_start_bit (send_start_bit),
.send_stop_bit (send_stop_bit),
.data_in (data_to_transfer),
.transfer_data (transfer_data),
.read_byte (1'b0),
.num_bits_to_transfer (num_bits_to_transfer),
// Bidirectionals
.i2c_sdata (I2C_SDAT),
// Outputs
.i2c_sclk (I2C_SCLK),
.i2c_scen (),
.enable_clk (enable_clk),
.ack (i2c_ack),
.data_from_i2c (i2c_received_data),
.transfer_complete (transfer_complete)
);
defparam
I2C_Controller.I2C_BUS_MODE = I2C_BUS_MODE;
endmodule
|
/*
Microcode Execute
Microcode Op
31:24, Opcode
23, Last Uop (Reset to Start)
*/
`include "ArithAlu.v"
`include "MemAlu.v"
`include "GpReg.v"
`include "MemTile.v"
`include "DecOp.v"
/*
module ExUop(
clk,
istrWord,
uopWord,
uopCmd,
idRegD,
idRegS,
idRegT,
idImm
);
*/
module ExUop(clk);
input clk; //clock
/*
input[31:0] istrWord; //source instruction word
input[31:0] uopWord; //uop word
input[7:0] uopCmd;
input[6:0] idRegD; //Source Opcode D (or N)
input[6:0] idRegS; //Source Opcode S (or M)
input[6:0] idRegT; //Source Opcode T
input[31:0] idImm; //Source Immediate
*/
reg[31:0] istrWord; //source instruction word
reg[31:0] uopWord; //uop word
reg[7:0] uopCmd;
reg[6:0] idRegD; //Source Opcode D (or N)
reg[6:0] idRegS; //Source Opcode S (or M)
reg[6:0] idRegT; //Source Opcode T
reg[31:0] idImm; //Source Immediate
reg[11:0] idUopPc; //Instruction Uop PC
parameter[7:0] UOP_BRINST = 8'h00; //Branch Decoded Instruction
parameter[7:0] UOP_ADDI = 8'h01;
parameter[7:0] UOP_SUBI = 8'h02;
parameter[7:0] UOP_MULI = 8'h03;
parameter[7:0] UOP_ANDI = 8'h04;
parameter[7:0] UOP_ORI = 8'h05;
parameter[7:0] UOP_XORI = 8'h06;
parameter[7:0] UOP_SHLI = 8'h07;
parameter[7:0] UOP_SHRI = 8'h08;
parameter[7:0] UOP_SARI = 8'h09;
parameter[7:0] UOP_ADDCI = 8'h0A;
parameter[7:0] UOP_CMPEQI = 8'h0B;
parameter[7:0] UOP_CMPGTI = 8'h0C;
parameter[7:0] UOP_CMPGEI = 8'h0D;
parameter[7:0] UOP_CMPHSI = 8'h0E;
parameter[7:0] UOP_CMPHII = 8'h0F;
parameter[7:0] UOP_GETINST = 8'h10; //Fetch Instruction
parameter[7:0] UOP_ADDQ = 8'h11;
parameter[7:0] UOP_SUBQ = 8'h12;
parameter[7:0] UOP_MULQ = 8'h13;
parameter[7:0] UOP_ANDQ = 8'h14;
parameter[7:0] UOP_ORQ = 8'h15;
parameter[7:0] UOP_XORQ = 8'h16;
parameter[7:0] UOP_SHLQ = 8'h17;
parameter[7:0] UOP_SHRQ = 8'h18;
parameter[7:0] UOP_SARQ = 8'h19;
parameter[7:0] UOP_ADDCQ = 8'h1A;
parameter[7:0] UOP_CMPEQQ = 8'h1B;
parameter[7:0] UOP_CMPGTQ = 8'h1C;
parameter[7:0] UOP_CMPGEQ = 8'h1D;
parameter[7:0] UOP_CMPHSQ = 8'h1E;
parameter[7:0] UOP_CMPHIQ = 8'h1F;
parameter[7:0] UOP_LEAB = 8'h21;
parameter[7:0] UOP_LEAW = 8'h22;
parameter[7:0] UOP_LEAI = 8'h23;
parameter[7:0] UOP_LEAQ = 8'h24;
parameter[7:0] UOP_LEAV = 8'h25;
parameter[7:0] UOP_MOVLDB = 8'h31;
parameter[7:0] UOP_MOVLDW = 8'h32;
parameter[7:0] UOP_MOVLDI = 8'h33;
parameter[7:0] UOP_MOVLDQ = 8'h34;
parameter[7:0] UOP_MOVLDUB = 8'h36;
parameter[7:0] UOP_MOVLDUW = 8'h37;
parameter[7:0] UOP_MOVSTB = 8'h39;
parameter[7:0] UOP_MOVSTW = 8'h3A;
parameter[7:0] UOP_MOVSTI = 8'h3B;
parameter[7:0] UOP_MOVSTQ = 8'h3C;
reg[63:0] iDataD;
reg[63:0] iDataS;
reg[63:0] iDataT;
reg[63:0] tData2D;
reg[6:0] tIdReg2D;
reg tIsWr2D;
reg tIsQw2D;
reg[63:0] oData2D;
reg[6:0] oIdReg2D;
reg oIsWr2D;
reg oIsQw2D;
// ArithAlu alu1;
// MemAlu agu1;
GpReg regs(clk,
oIsWr2D, oIsWr2D, oIdReg2D, oData2D,
idRegD, iDataD, idRegS, iDataS, idRegT, iDataT);
reg[63:0] tDataAluD;
reg[31:0] regSr;
reg[31:0] tRegSr;
reg[63:0] regPc;
reg[63:0] regNextPc;
reg[3:0] aluCmd;
reg[3:0] tAluSr;
ArithAlu alu1(clk, aluCmd,
iDataS, iDataT, tDataAluD, regSr[3:0], tAluSr);
reg[63:0] tDataAguD;
reg[2:0] aguCmd;
MemAlu agu1(clk, aguCmd,
iDataS, iDataT[31:0], idImm, tDataAguD);
reg memRd;
reg memWr;
reg[2:0] memCmd;
reg[47:0] memAddr;
reg[63:0] memRdValue;
reg[63:0] memWrValue;
MemTile mem1(clk, memRd, memWr, memCmd,
memAddr, memRdValue, memWrValue);
reg[1:0] idStepPc;
DecOp dec1(clk, istrWord,
idRegD, idRegS, idRegT, idImm, idUopPc, idStepPc);
reg[63:0] tRegStepPc;
reg[11:0] uopPc;
reg[11:0] uopNextPc;
reg[31:0] uopPgm[4096];
always @ (clk)
begin
uopWord=uopPgm[uopPc];
if(uopWord[23])
uopNextPc=12'h000;
else
uopNextPc=uopPc+1;
uopCmd=uopWord[31:24];
regPc[31: 0]=regs.regs[regs.REG_PC_LO];
regPc[63:32]=regs.regs[regs.REG_PC_HI];
regNextPc=regPc;
regSr=regs.regs[regs.REG_SR];
case(uopCmd[7:4])
4'h0:
begin
if(uopCmd[3:0]==4'h0)
begin
uopNextPc=idUopPc;
tRegStepPc[63:3]=61'h0;
tRegStepPc[2:1]=idStepPc[1:0];
tRegStepPc[0]=1'b0;
regNextPc=regPc+tRegStepPc;
end
else
begin
aluCmd=uopCmd[3:0];
tData2D=tDataAluD;
tIsWr2D=aluCmd<alu1.UOP_CMPEQ;
tIsQw2D=1'b0;
if(aluCmd<alu1.UOP_ADDC)
tRegSr=regSr;
else
begin
tRegSr[31:1]=regSr[31:1];
tRegSr[0]=tAluSr[0];
end
end
end
4'h1:
begin
if(uopCmd[3:0]==4'h0)
begin
memAddr[47:0]=regPc[47:0];
memCmd=mem1.MD_DWORD;
memRd=1'b1;
memWr=1'b0;
istrWord=memRdValue[31:0];
tData2D=tDataAguD;
tIsWr2D=1'b0;
tIsQw2D=1'b0;
tRegSr=regSr;
end
else
begin
aluCmd=uopCmd[3:0];
tData2D=tDataAluD;
tIsWr2D=aluCmd<alu1.UOP_CMPEQ;
tIsQw2D=1'b1;
if(aluCmd<alu1.UOP_ADDC)
tRegSr=regSr;
else
begin
tRegSr[31:1]=regSr[31:1];
tRegSr[0]=tAluSr[1];
end
end
end
4'h2:
begin
aguCmd=uopCmd[2:0];
tData2D=tDataAguD;
tIsWr2D=1'b1;
tIsQw2D=1'b1;
tRegSr=regSr;
end
4'h3:
begin
aguCmd=uopCmd[2:0];
memCmd=uopCmd[2:0];
memAddr=tDataAguD[47:0];
tIsWr2D=uopCmd[3];
tIsQw2D=uopCmd[2];
tRegSr=regSr;
memWrValue=iDataD;
tData2D=memRdValue;
if(uopCmd[3])
begin
memRd=1'b0;
memWr=1'b1;
end
else
begin
memRd=1'b1;
memWr=1'b0;
end
end
default: begin
tData2D=iDataD;
tIsWr2D=1'b0;
tIsQw2D=1'b0;
tRegSr=regSr;
end
endcase
end
always @ (posedge clk) begin
oData2D <= tData2D;
oIsWr2D <= tIsWr2D;
oIsQw2D <= tIsQw2D;
// regSr <= tRegSr;
regs.regs[regs.REG_SR] <= tRegSr;
uopPc <= uopNextPc;
regs.regs[regs.REG_PC_LO] <= regNextPc[31: 0];
regs.regs[regs.REG_PC_HI] <= regNextPc[63:32];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_PP_SYMBOL_V
`define SKY130_FD_SC_LS__MUX2I_PP_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2i (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output Y ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module PM_ctl # (
parameter integer C_IMG_WW = 12,
parameter integer C_IMG_HW = 12,
parameter integer C_FRMN_WIDTH = 2,
parameter integer C_STEP_NUMBER_WIDTH = 32,
parameter integer C_SPEED_DATA_WIDTH = 32,
parameter integer C_L2R = 1
) (
input wire clk,
input wire resetn,
output reg exe_done,
input wire [31:0] img_delay_cnt,
input wire [C_FRMN_WIDTH-1:0] img_delay_frm,
input wire req_single_dir,
input wire req_abs,
input wire req_dep_img,
input wire [C_IMG_WW-1:0] req_img_dst,
input wire [C_IMG_WW-1:0] req_img_tol,
input wire [C_SPEED_DATA_WIDTH-1:0] req_speed,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] req_step,
input wire img_pulse,
input wire img_valid, /// image position valid
input wire [C_IMG_WW-1:0] img_pos, /// sync as pen[0]
output wire m_sel ,
input wire m_ntsign ,
input wire m_zpsign ,
input wire m_ptsign ,
input wire m_state ,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] m_position,
output reg m_start ,
output reg m_stop ,
output reg [C_SPEED_DATA_WIDTH-1:0] m_speed ,
output reg signed [C_STEP_NUMBER_WIDTH-1:0] m_step ,
output reg m_abs ,
output reg m_mod_remain,
output reg signed [C_STEP_NUMBER_WIDTH-1:0] m_new_remain,
//output reg rd_en,
output reg [C_IMG_WW-1:0] rd_addr,
input wire [C_STEP_NUMBER_WIDTH-1:0] rd_data,
output wire [31:0] test1,
output wire [31:0] test2,
output wire [31:0] test3,
output wire [31:0] test4
);
wire req_dir_back;
assign req_dir_back = req_step[C_STEP_NUMBER_WIDTH-1];
/////////////////// motor_pos ///////////////////////////////////////////
wire signed [C_STEP_NUMBER_WIDTH-1:0] movie_pos;
img_delay_ctl # (
.C_STEP_NUMBER_WIDTH(C_STEP_NUMBER_WIDTH),
.C_FRMN_WIDTH(C_FRMN_WIDTH),
.C_TEST(0)
) delay_ctl_inst (
.clk(clk),
.eof(img_pulse),
.delay0_cnt (img_delay_cnt),
.delay0_frm (img_delay_frm),
.delay0_pulse(),
.cur_pos(m_position),
.movie_pos(movie_pos)
);
//////////////////////////////// delay1 ////////////////////////////////////////
reg [C_IMG_WW-1:0] pos_l; /// left
reg [C_IMG_WW-1:0] pos_d; /// dst
reg [C_IMG_WW-1:0] pos_r; /// right
reg [C_IMG_WW-1:0] pos_c; /// cur
always @ (posedge clk) begin
if (img_pulse) begin
pos_l <= req_img_dst - req_img_tol;
pos_d <= req_img_dst;
pos_r <= req_img_dst + req_img_tol;
pos_c <= img_pos;
end
end
reg pen_d1;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d1 <= 0;
else
pen_d1 <= (img_pulse && req_dep_img);
end
//////////////////////////////// delay2 ////////////////////////////////////////
reg pos_lofl;
reg pos_rofr;
reg pos_lofd;
reg[C_IMG_WW-1:0] pos_dmc;
reg[C_IMG_WW-1:0] pos_cmd;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
pos_lofl <= 0;
pos_rofr <= 0;
pos_dmc <= 0;
pos_cmd <= 0;
end
else if (pen_d1) begin
if (pos_c < pos_l)
pos_lofl <= 1;
else
pos_lofl <= 0;
if (pos_c > pos_r)
pos_rofr <= 1;
else
pos_rofr <= 0;
if (pos_c < pos_d)
pos_lofd <= 1;
else
pos_lofd <= 0;
pos_dmc <= (pos_d - pos_c);
pos_cmd <= (pos_c - pos_d);
end
end
reg pen_d2;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d2 <= 0;
else
pen_d2 <= pen_d1;
end
//////////////////////////////// delay3 ////////////////////////////////////////
reg pos_needback;
reg pos_ok;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
//rd_en <= 1'b0;
pos_ok <= 0;
pos_needback <= 0;
rd_addr <= 0;
end
else if (pen_d2) begin
if (pos_rofr == 1'b0 && pos_lofl == 1'b0)
pos_ok <= 1'b1;
pos_needback <= (pos_lofd != C_L2R);
//rd_en <= 1'b1;
if (pos_rofr)
rd_addr <= pos_cmd;
else if (pos_lofl)
rd_addr <= pos_dmc;
else
rd_addr <= 0;
end
else begin
//rd_en <= 1'b0;
end
end
reg pen_d3;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d3 <= 0;
else
pen_d3 <= pen_d2;
end
//////////////////////////////// delay4 ////////////////////////////////////////
//reg pos_needback_d4;
reg pos_ok_d4;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
pos_ok_d4 <= 0;
//pos_needback_d4 <= 0;
end
else if (pen_d3) begin
pos_ok_d4 <= pos_ok;
//pos_needback_d4 <= pos_needback;
end
end
reg pen_d4;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d4 <= 0;
else
pen_d4 <= pen_d3;
end
//////////////////////////////// delay5 ////////////////////////////////////////
reg signed [C_STEP_NUMBER_WIDTH-1:0] dst_pos;
reg pos_over;
reg pos_ok_d5;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
dst_pos <= 0;
pos_over <= 0;
pos_ok_d5 <= 0;
end
else if (pen_d4) begin
pos_ok_d5 <= pos_ok_d4;
if (pos_ok_d4)
pos_over <= 0;
else
pos_over <= (pos_needback != req_dir_back);
if (pos_needback)
dst_pos <= movie_pos - rd_data;
else
dst_pos <= movie_pos + rd_data;
end
end
reg pen_d5;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d5 <= 0;
else
pen_d5 <= pen_d4;
end
//////////////////////////////// delay6 ////////////////////////////////////////
reg m_started;
wire m_running;
assign m_running = m_state;
always @ (posedge clk) begin
if (resetn == 1'b0)
m_started <= 1'b0;
else if (m_start)
m_started <= 1'b1;
end
reg m_run_over;
always @ (posedge clk) begin
if (resetn == 1'b0)
m_run_over <= 1'b0;
else if (m_running)
m_run_over <= 1'b1;
end
wire m_stopped;
assign m_stopped = (m_run_over && ~m_running);
/// stop
always @ (posedge clk) begin
if (resetn == 1'b0)
m_stop <= 1'b0;
else if (m_stop == 1'b1)
m_stop <= 1'b0;
else if (pen_d5) begin
if (req_single_dir) begin
/*
if (m_running) begin
if (req_dir_back) begin
if (m_position <= dst_pos)
m_stop <= 1'b1;
end
else begin
if (m_position >= dst_pos)
m_stop <= 1'b1;
end
end
*/
end
end
end
/// start
reg need_dyn_adjust;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_start <= 1'b0;
m_abs <= 1'b0;
need_dyn_adjust <= 1'b0;
end
else if (m_start == 1'b1) begin
m_start <= 1'b0;
end
else if (req_dep_img) begin
if (pen_d5) begin
if (req_single_dir) begin
if (pos_ok_d5 == 1'b0 && pos_over == 1'b0 && m_started == 1'b0) begin
m_start <= 1'b1;
m_speed <= req_speed;
if (img_valid)
m_step <= rd_data;
else begin
m_step <= 0;
end
m_abs <= 1'b0;
end
need_dyn_adjust <= ~img_valid;
end
end
end
else begin
if (m_started == 1'b0) begin
m_start <= 1'b1;
m_speed <= req_speed;
m_step <= req_step;
m_abs <= req_abs;
end
end
end
/// change remain step
reg [31:0] r_test1; assign test1 = r_test1;
reg [31:0] r_test2; assign test2 = r_test2;
reg [31:0] r_test3; assign test3 = r_test3;
reg [31:0] r_test4; assign test4 = r_test4;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_mod_remain <= 1'b0;
end
else if (m_mod_remain == 1'b1) begin
m_mod_remain <= 1'b0;
end
else if (pen_d5) begin
if (req_single_dir) begin
if (m_running && need_dyn_adjust && img_valid) begin
r_test1 <= dst_pos;
r_test2 <= m_position;
r_test3 <= movie_pos;
r_test4 <= rd_data;
if (req_dir_back) begin
if (m_position > dst_pos) begin
m_mod_remain <= 1'b1;
m_new_remain <= m_position - dst_pos;
end
end
else begin
if (m_position < dst_pos) begin
m_mod_remain <= 1'b1;
m_new_remain <= dst_pos - m_position;
end
end
end
end
end
end
//////////////// exe_done
always @ (posedge clk) begin
if (resetn == 1'b0)
exe_done <= 1'b0;
else if (req_single_dir) begin
if (m_stopped || pos_over)
exe_done <= 1'b1;
end
end
assign m_sel = resetn;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 18.02.2016 11:42:49
// Design Name:
// Module Name: red_pitaya_lpf_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_lpf_block
#(
parameter SHIFTBITS = 4,//shift can be from 0 to 15 bits
parameter SIGNALBITS = 14, //bitwidth of signals
parameter MINBW = 10 //minimum allowed filter bandwidth
)
(
input clk_i,
input rstn_i ,
input [SHIFTBITS:0] shift,
input filter_on,
input highpass,
input signed [SIGNALBITS-1:0] signal_i,
output signed [SIGNALBITS-1:0] signal_o
);
`define CLOG2(x) \
(x < 2) ? 1 : \
(x < 4) ? 2 : \
(x < 8) ? 3 : \
(x < 16) ? 4 : \
(x < 32) ? 5 : \
(x < 64) ? 6 : \
(x < 128) ? 7 : \
(x < 256) ? 8 : \
(x < 512) ? 9 : \
(x < 1024) ? 10 : \
(x < 2048) ? 11 : \
(x < 2**12) ? 12 : \
(x < 2**13) ? 13 : \
(x < 2**14) ? 14 : \
(x < 2**15) ? 15 : \
(x < 2**16) ? 16 : \
(x < 2**17) ? 17 : \
(x < 2**18) ? 18 : \
(x < 2**19) ? 19 : \
(x < 2**20) ? 20 : \
(x < 2**21) ? 21 : \
(x < 2**22) ? 22 : \
(x < 2**23) ? 23 : \
(x < 2**24) ? 24 : \
(x < 2**25) ? 25 : \
(x < 2**26) ? 26 : \
(x < 2**27) ? 27 : \
(x < 2**28) ? 28 : \
(x < 2**29) ? 29 : \
(x < 2**30) ? 30 : \
(x < 2**31) ? 31 : \
(x <= 2**32) ? 32 : \
-1
localparam MAXSHIFT = `CLOG2(125000000/MINBW); // gives an effective limit of 10 MHz (divided by 4 pi)
reg signed [SIGNALBITS+MAXSHIFT-1:0] y;
reg signed [SIGNALBITS+MAXSHIFT-1:0] delta; //we need this cumbersome imperfect implementation with a delta buffer to introduce some delay so the code works at 125 MHZ
wire signed [SIGNALBITS+MAXSHIFT-1:0] shifted_delta;
wire signed [SIGNALBITS-1:0] y_out;
wire filter_off;
assign y_out = y[MAXSHIFT+SIGNALBITS-1:MAXSHIFT];
assign shifted_delta = delta<<((shift<MAXSHIFT) ? shift : MAXSHIFT);
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
y <= {MAXSHIFT+SIGNALBITS{1'b0}};
delta <= {MAXSHIFT+SIGNALBITS{1'b0}};
end
else begin
delta <= signal_i - y_out;
y <= y + shifted_delta;
end
end
assign signal_o = (filter_on == 1'b0) ? signal_i : ( (highpass==1'b0) ? y_out : delta);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111A_2_V
`define SKY130_FD_SC_HS__O2111A_2_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111a_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111A_2_V
|
/*
* Copyright 2013-2021 Robert Newgard
*
* This file is part of fcs.
*
* fcs is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fcs is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with fcs. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "fcs32_8.v"
`include "fcs32_brev.v"
module uut_8_top
(
output wire [31:0] res_o,
output wire [31:0] exp_o,
output wire [31:0] obs_o,
output wire val_o,
input wire [7:0] data_i,
input wire sof_i,
input wire eof_i,
input wire pclk_i
);
/* -----------------------------------------------------------
parameters
------------------------------------------------------------*/
localparam LO = 1'b0;
localparam HI = 1'b1;
localparam [31:0] ZEROS = {32{LO}};
localparam [31:0] ONES = {32{HI}};
localparam FIRST = 7;
localparam LAST = 9;
/* -----------------------------------------------------------
net declarations
------------------------------------------------------------*/
reg [7:0] data_z1;
reg sof_z1;
reg [7:0] data_z2;
reg sof_z2;
reg [7:0] data_z3;
reg sof_z3;
reg [7:0] data_z4;
reg sof_z4;
reg val_z5;
reg [31:0] exp_z5;
reg [31:0] fcs_z5;
reg val_z6;
reg [31:0] exp_z6;
reg [31:0] fcs_z6;
reg [31:0] exp[FIRST:LAST];
reg [31:0] crc[FIRST:LAST];
reg val[FIRST:LAST];
/* -----------------------------------------------------------
input assignments
------------------------------------------------------------*/
/* -----------------------------------------------------------
Pipeline
------------------------------------------------------------*/
always @ (posedge pclk_i) begin
data_z1[7:0] <= data_i[7:0];
sof_z1 <= sof_i;
data_z2[7:0] <= data_z1[7:0];
sof_z2 <= sof_z1;
data_z3[7:0] <= data_z2[7:0];
sof_z3 <= sof_z2;
data_z4[7:0] <= data_z3[7:0];
sof_z4 <= sof_z3;
val_z5 <= eof_i;
if (eof_i == HI) begin
exp_z5[31:0] <= {data_z3[7:0], data_z2[7:0], data_z1[7:0], data_i[7:0]};
end
if (sof_z4 == HI) begin
fcs_z5[31:0] <= fcs32_8(data_z4[7:0], ONES[31:0]);
end else begin
fcs_z5[31:0] <= fcs32_8(data_z4[7:0], fcs_z5[31:0]);
end
val_z6 <= val_z5;
exp_z6[31:0] <= exp_z5[31:0];
fcs_z6[31:0] <= fcs32_brev(fcs_z5[31:0]);
end
generate
genvar i;
for (i = FIRST ; i <= LAST ; i = i + 1) begin : ppln_delay
always @ (posedge pclk_i) begin
if (i == FIRST) begin
exp[i][31:0] <= exp_z6[31:0];
crc[i][31:0] <= fcs_z6[31:0];
val[i] <= val_z6;
end else begin
exp[i][31:0] <= exp[i - 1][31:0];
crc[i][31:0] <= crc[i - 1][31:0];
val[i] <= val[i - 1];
end
end
end
endgenerate
/* -----------------------------------------------------------
output assignments
------------------------------------------------------------*/
always @ (*) begin
res_o[31:0] = fcs_z5[31:0];
exp_o[31:0] = exp[LAST][31:0];
obs_o[31:0] = crc[LAST][31:0];
val_o = val[LAST];
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:14 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_xbar_0_stub.v
// Design : zynq_design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[23:0],m_axi_awaddr[63:0],m_axi_awlen[15:0],m_axi_awsize[5:0],m_axi_awburst[3:0],m_axi_awlock[1:0],m_axi_awcache[7:0],m_axi_awprot[5:0],m_axi_awregion[7:0],m_axi_awqos[7:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[1:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bid[23:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_arid[23:0],m_axi_araddr[63:0],m_axi_arlen[15:0],m_axi_arsize[5:0],m_axi_arburst[3:0],m_axi_arlock[1:0],m_axi_arcache[7:0],m_axi_arprot[5:0],m_axi_arregion[7:0],m_axi_arqos[7:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rid[23:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rlast[1:0],m_axi_rvalid[1:0],m_axi_rready[1:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [23:0]m_axi_awid;
output [63:0]m_axi_awaddr;
output [15:0]m_axi_awlen;
output [5:0]m_axi_awsize;
output [3:0]m_axi_awburst;
output [1:0]m_axi_awlock;
output [7:0]m_axi_awcache;
output [5:0]m_axi_awprot;
output [7:0]m_axi_awregion;
output [7:0]m_axi_awqos;
output [1:0]m_axi_awvalid;
input [1:0]m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [1:0]m_axi_wlast;
output [1:0]m_axi_wvalid;
input [1:0]m_axi_wready;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [1:0]m_axi_bvalid;
output [1:0]m_axi_bready;
output [23:0]m_axi_arid;
output [63:0]m_axi_araddr;
output [15:0]m_axi_arlen;
output [5:0]m_axi_arsize;
output [3:0]m_axi_arburst;
output [1:0]m_axi_arlock;
output [7:0]m_axi_arcache;
output [5:0]m_axi_arprot;
output [7:0]m_axi_arregion;
output [7:0]m_axi_arqos;
output [1:0]m_axi_arvalid;
input [1:0]m_axi_arready;
input [23:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [3:0]m_axi_rresp;
input [1:0]m_axi_rlast;
input [1:0]m_axi_rvalid;
output [1:0]m_axi_rready;
endmodule
|
//==================================================================================================
// Filename : musb_branch_unit.v
// Created On : 2014-09-27 20:14:58
// Last Modified : 2015-05-24 21:00:28
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Branch detection.
//==================================================================================================
`include "musb_defines.v"
module musb_branch_unit(
input [5:0] opcode, // Instruction opcode
input [31:0] id_pc_add4, // Instruction address + 4
input [31:0] id_data_rs, // Data from R0
input [31:0] id_data_rt, // Data from R1
input [25:0] op_imm26, // imm21/Imm16
output reg [31:0] pc_branch_address, // Destination address
output reg take_branch // Valid branch
);
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire beq;
wire bne;
wire bgez;
wire bgtz;
wire blez;
wire bltz;
wire [31:0] long_jump;
wire [31:0] short_jump;
wire [5:0] inst_function;
wire [4:0] op_rt;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign beq = id_data_rs == id_data_rt;
assign bne = ~beq;
assign bgez = ~id_data_rs[31];
assign bgtz = id_data_rs > 32'b0;
assign blez = ~bgtz;
assign bltz = id_data_rs[31];
assign long_jump = {id_pc_add4[31:28], op_imm26, 2'b00 };
assign short_jump = $signed(id_pc_add4) + $signed( { op_imm26[`MUSB_INSTR_IMM16], 2'b00 } );
assign inst_function = op_imm26[`MUSB_INSTR_FUNCT];
assign op_rt = op_imm26[`MUSB_INSTR_RT];
//--------------------------------------------------------------------------
// Get branch address
//--------------------------------------------------------------------------
always @(*) begin
case (opcode)
`OP_BEQ : begin pc_branch_address <= short_jump; take_branch <= beq; end
`OP_BGTZ : begin pc_branch_address <= short_jump; take_branch <= bgtz; end
`OP_BLEZ : begin pc_branch_address <= short_jump; take_branch <= blez; end
`OP_BNE : begin pc_branch_address <= short_jump; take_branch <= bne; end
`OP_J : begin pc_branch_address <= long_jump; take_branch <= 1'b1; end
`OP_JAL : begin pc_branch_address <= long_jump; take_branch <= 1'b1; end
`OP_TYPE_REGIMM : begin
case (op_rt)
`RT_OP_BGEZ : begin pc_branch_address <= short_jump; take_branch <= bgez; end
`RT_OP_BGEZAL : begin pc_branch_address <= short_jump; take_branch <= bgez; end
`RT_OP_BLTZ : begin pc_branch_address <= short_jump; take_branch <= bltz; end
`RT_OP_BLTZAL : begin pc_branch_address <= short_jump; take_branch <= bltz; end
default : begin pc_branch_address <= 32'bx00; take_branch <= 1'b0; end
endcase
end
`OP_TYPE_R : begin
case(inst_function)
`FUNCTION_OP_JALR : begin pc_branch_address <= id_data_rs; take_branch <= 1'b1; end
`FUNCTION_OP_JR : begin pc_branch_address <= id_data_rs; take_branch <= 1'b1; end
default : begin pc_branch_address <= 32'bx00; take_branch <= 1'b0; end
endcase
end
default : begin pc_branch_address <= 32'bx00; take_branch <= 1'b0; end
endcase
end
endmodule
|
module stateEncoder(clk, state, enable, out);
/*
This module reads the state vector. When it perceives a rising edge in the enable bit,
it is trigerred to encode the state information into a serial output sequence. This is
done via the following protocol :
(header signal) (space) (first state bit) (space) (second state bit) (space) ... (last state bit) (space) (closer signal)
1. The header signal is a high state in the output for three consecutive clock cycles followed by a low state for one clock cycle
2. The spacer is two clock cycles in the low position.
3. the states are conveyed bit-by-bit in sequence from highest (most-significant) bit to lowest (least-significant) bit. Three clock cycles are used. The output is held high or low for one clock cycle according to whether the state bit is high or low.
4. the closer signal puts the output high for two clock cycles, then low.
The whole sequence takes 4 clock cycles for the header, #state bits+(#state bit+1)*2=23 for the state information, and 2 clock cycles for the closer. In total, 29 clock cycles are used.
While a signal is being output during these 29 cycles, the enable bit is ignored.
Ted Golfinopoulos, 13 Jan 2012
*/
//`define STATE_LENGTH 4'b0111 //=7 -> Define a macro containing the number of bits in the state vector
//`define HEADER_LENGTH 3'b110 //Number of clock cycles in header sequence (6).
parameter STATE_LENGTH=4'b0111; //=7 -> Define a macro containing the number of bits in the state vector
parameter HEADER_LENGTH=3'b110; //Number of clock cycles in header sequence (6).
parameter HEADER_ON_COUNTS=2'b11; //Header should be on for this number of counts.
parameter CLOSER_ON_COUNTS=2'b10; //Closer should be on for this number of counts.
input clk; //Clock signal
//input [`STATE_LENGTH-1:0] state; //State vector to encode on serial output line.
//reg [`STATE_LENGTH-1:0] storedState; //Store state vector on an enable trigger for stability.
input [STATE_LENGTH-1:0] state; //State vector to encode on serial output line.
reg [STATE_LENGTH-1:0] storedState; //Store state vector on an enable trigger for stability.
input enable; //Trigger for encode action.
output out; //Serial output into which state vector is encoded.
reg outReg;
reg [4:0] cntr; //Five-bit counter, reused and reset in each output sequence block.
reg encodingInProgress, playState, playCloser, finished; //Flags determining which state of output sequence we are in.
reg [3:0] stateIndex; //Make one bit larger than needed as of 13 Jan 2012.
initial begin
outReg=1'b0; //Initialize output storage register.
//Set sequence flags low - wait for enable edge to output a state sequence.
encodingInProgress=1'b0;
playState=1'b0;
playCloser=1'b0;
finished=1'b0;
//stateIndex=`STATE_LENGTH-1'b1;
stateIndex=STATE_LENGTH-1'b1;
storedState=1'b0; //Initialize stored state.
end
assign out=outReg; //Tie output to outReg.
//Output state sequence with a header and closer on an enable edge.
always @(posedge enable or posedge finished) begin
//If another encoding job is not already in progress, initiate a new one.
//Otherwise, don't change the current output message.
if(enable) begin
if( !encodingInProgress && !playState && !playCloser) begin
storedState=state; //Store current state in a register.
encodingInProgress=1'b1; //Set encodingInProgress flag high and begin encoding an output message.
end
end else if(finished) begin
encodingInProgress=1'b0; //Set encodingInProgress flag low.
end
end
//This always block is responsible for outputting the header signal
always @(posedge clk) begin
if( !encodingInProgress ) begin
outReg=1'b0; //Make sure output is low if a sequence is not being encoded.
//Keep playState and playCloser flags off if not encoding.
playState=1'b0;
playCloser=1'b0;
cntr=1'b0; //Keep counter at zero if encoding is not in progress.
finished = 1'b0; //Turn off finished - it is only the positive edge of this flag that is used.
//stateIndex=`STATE_LENGTH-1'b1; //Reset state index counter.
stateIndex=STATE_LENGTH-1'b1; //Reset state index counter.
end
//If flag to play header is on, output header sequence until it is complete.
//Then, free output control and intitiate signal sequence.
//Note: encodingInProgress is clocked by enable and finished, and so we can't turn it off in this block.
//Header output is terminated by inititiation of next stage in sequence, playState.
if(encodingInProgress && !playState && !playCloser) begin
cntr=cntr+1'b1; //Increment counter.
if(cntr<=HEADER_ON_COUNTS) begin
outReg=1'b1; //Assert output for header on period
$display("HEADER ON");
end else if(cntr<=HEADER_LENGTH) begin
outReg=1'b0; //Pull output low during off period of header.
$display("HEADER OFF");
end else begin
playState=1'b1; //Assert playState flag and initiate playState sequence.
cntr=1'b0; //Reset counter.
$display("HEADER DONE.");
end
end else if(!encodingInProgress) cntr=1'b0; //Continuously reset counter if not being used.
//end
//This always block is responsible for outputting the encoded state signal
//always @(posedge clk) begin
//If flag to play state is on, output signal sequence until it is complete.
//Then, free output control and initiate closer sequence.
if(playState && !playCloser) begin
$display("Displaying state bit %d", stateIndex);
cntr=cntr+1'b1; //Increment counter.
if(cntr==2'b10) begin
outReg=storedState[stateIndex]; //Set output to
end else begin
outReg=1'b0; //Pull output low (spacing between on periods during state sequence).
end
if(cntr==2'b11) begin
cntr=1'b0; //Reset triplet counter
//Decrement state index (note that we output starting
//with most significant bit and go down to least significant bit).
if(stateIndex>1'b0) begin
stateIndex=stateIndex-1'b1;
end else if(stateIndex==1'b0) begin //If the stateIndex is zero, the state encoding is done.
playState=1'b0; //Reset signal output flag.
playCloser=1'b1; //Advance to the playCloser stage of the encoded sequence.
cntr=1'b0; //Reset triplet counter.
//stateIndex=`STATE_LENGTH-1'b1; //Reset state index counter.
stateIndex=STATE_LENGTH-1'b1; //Reset state index counter.
end
end
end
//end
//This always block is responsible for outputting the closer signal.
//always @(posedge clk) begin
//If the flag for plaging the closer is high, play the closer sequence until complete.
//There should be to LOW clock cycles between the last state bit and the next potentially
//high bit according to the documentation. One low clock cycle is created in the playState
//sequence. The other one is created here.
if(playCloser && !playState) begin
cntr=cntr+1'b1; //Increment counter.
if(cntr>2'b10 && cntr<=2'b10+CLOSER_ON_COUNTS) begin //The output is on when this condition is true.
outReg=1'b1; //Assert output high for two clock cycles per closer protocol.
$display("CLOSER ON.");
end else if(cntr>=3'b100) begin
outReg=1'b0; //Pull output low. Encoded sequence is done.
playCloser=1'b0; //Reset playCloser flag.
finished=1'b1; //Reset finished bit flag, since encoding is done.
cntr=1'b0; //Reset counter.
$display("CLOSER OFF");
$display("FINISHED");
end else begin //The output is off when this condition is true (i.e. other conditions are false).
outReg=1'b0;
$display("CLOSER OFF");
end
end
end
endmodule
/*
`define CLOSER 4'b0110
`define SPACER 2'b10
reg [5:0] outputIndex;
*/
/*
//Create output message.
outputMessage={`HEADER, state, `CLOSER}; //Encode and cache output message.
*/
/*
outputMessage={`HEADER, `SPACER,
state[6], `SPACER,
state[5], `SPACER,
state[4], `SPACER,
state[3], `SPACER,
state[2], `SPACER,
state[1], `SPACER,
state[0], `SPACER,
`CLOSER};
*/
/*
if(encodingInProgress) begin
if(headerIndex<HEADER_LENGTH+1'b1) begin
headerIndex=headerIndex+1'b1; //Increment header index
assign out=header[headerIndex-1]; //Make a continuous assignment
end else //Turn control over to signal player
encodingInProgress=1'b0; //Turn off play header flag.
playState=1'b1; //Initiate signal segment of message.
deassign out;
end
end else begin
headerIndex=1'b0; //Reset header index counter.
encodingInProgress=1'b0; //Reset encodingInProgress flag.
end
*/
/*
//Insert first spacer.
if(!firstSpacerFinished) begin
if(cntr<`SPACER) begin
assign out=1'b0;
cntr=cntr+1'b1; //Increment counter
end else begin
cntr=0'b0; //Reset counter
firstSpacerFinished=1'b1; //Assert that first spacer has been output.
end
stateIndex=1'b0; //Reset state index.
end else begin
if(stateIndex<`STATE_LENGTH) begin
if(cntr==1'b0) begin
assign out=
else if(cntr <= `SPACER) begin
end else begin cntr=1'b0; //Reset counter.
end
end
//Play signals followed by spacers
*/
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 23:15:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: Switch_Synchronizer_Bank
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Switch Synchronizer Bank
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Switch_Synchronizer_Bank
#(
parameter SWITCH_SYNC_CHANNELS = 1,
parameter CLK_RATE_HZ = 50000000, // Hz
parameter DEBOUNCE_TIME = 10000, // ns
parameter SIG_OUT_INIT = 1'b0
)
(
// Input Signals (asynchronous)
input [SWITCH_SYNC_CHANNELS-1:0] SIG_IN,
// Output Signals (synchronized to CLK domain)
output [SWITCH_SYNC_CHANNELS-1:0] SIG_OUT,
// System Signals
input CLK
);
//
// Switch Input Debounce Synchronizers
//
genvar i;
generate
begin
for (i = 0; i < SWITCH_SYNC_CHANNELS; i=i+1)
begin : sw_sync_gen
Switch_Debounce_Synchronizer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ),
.DEBOUNCE_TIME( DEBOUNCE_TIME ),
.SIG_OUT_INIT( SIG_OUT_INIT )
)
sw_synchronizer
(
// Input Signals (asynchronous)
.SIG_IN( SIG_IN[i] ),
// Output Signals (synchronized to CLK domain)
.SIG_OUT( SIG_OUT[i] ),
// System Signals
.CLK( CLK )
);
end
end
endgenerate
endmodule
|
// file automatically generated by top_generator script
// this is a memory hierarchy done as a class project for CMPE220 at UCSC
// this specific file was generated for:
// 2 core(s),
// 4 data cache slice(s) per core, and
// 2 directory(ies)
`include "scmem.vh"
module top_2core2dr(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input clk
,input reset
//******************************************
//* CORE 0 *
//******************************************//
// icache core 0
,input core0_coretoic_pc_valid
,output core0_coretoic_pc_retry
,input I_coretoic_pc_type core0_coretoic_pc
,output core0_ictocore_valid
,input core0_ictocore_retry
,output I_ictocore_type core0_ictocore
// dcache core 0, slice 0
,input core0_slice0_coretodc_ld_valid
,output core0_slice0_coretodc_ld_retry
,input I_coretodc_ld_type core0_slice0_coretodc_ld
,output core0_slice0_dctocore_ld_valid
,input core0_slice0_dctocore_ld_retry
,output I_dctocore_ld_type core0_slice0_dctocore_ld
,input core0_slice0_coretodc_std_valid
,output core0_slice0_coretodc_std_retry
,input I_coretodc_std_type core0_slice0_coretodc_std
,output core0_slice0_dctocore_std_ack_valid
,input core0_slice0_dctocore_std_ack_retry
,output I_dctocore_std_ack_type core0_slice0_dctocore_std_ack
,input c0_s0_coretodctlb_ld_valid
,output c0_s0_coretodctlb_ld_retry
,input I_coretodctlb_ld_type c0_s0_coretodctlb_ld
,input c0_s0_coretodctlb_st_valid
,output c0_s0_coretodctlb_st_retry
,input I_coretodctlb_st_type c0_s0_coretodctlb_st
// dcache core 0, slice 1
,input core0_slice1_coretodc_ld_valid
,output core0_slice1_coretodc_ld_retry
,input I_coretodc_ld_type core0_slice1_coretodc_ld
,output core0_slice1_dctocore_ld_valid
,input core0_slice1_dctocore_ld_retry
,output I_dctocore_ld_type core0_slice1_dctocore_ld
,input core0_slice1_coretodc_std_valid
,output core0_slice1_coretodc_std_retry
,input I_coretodc_std_type core0_slice1_coretodc_std
,output core0_slice1_dctocore_std_ack_valid
,input core0_slice1_dctocore_std_ack_retry
,output I_dctocore_std_ack_type core0_slice1_dctocore_std_ack
,input c0_s1_coretodctlb_ld_valid
,output c0_s1_coretodctlb_ld_retry
,input I_coretodctlb_ld_type c0_s1_coretodctlb_ld
,input c0_s1_coretodctlb_st_valid
,output c0_s1_coretodctlb_st_retry
,input I_coretodctlb_st_type c0_s1_coretodctlb_st
`ifdef SC_4PIPE
// dcache core 0, slice 2
,input core0_slice2_coretodc_ld_valid
,output core0_slice2_coretodc_ld_retry
,input I_coretodc_ld_type core0_slice2_coretodc_ld
,output core0_slice2_dctocore_ld_valid
,input core0_slice2_dctocore_ld_retry
,output I_dctocore_ld_type core0_slice2_dctocore_ld
,input core0_slice2_coretodc_std_valid
,output core0_slice2_coretodc_std_retry
,input I_coretodc_std_type core0_slice2_coretodc_std
,output core0_slice2_dctocore_std_ack_valid
,input core0_slice2_dctocore_std_ack_retry
,output I_dctocore_std_ack_type core0_slice2_dctocore_std_ack
,input c0_s2_coretodctlb_ld_valid
,output c0_s2_coretodctlb_ld_retry
,input I_coretodctlb_ld_type c0_s2_coretodctlb_ld
,input c0_s2_coretodctlb_st_valid
,output c0_s2_coretodctlb_st_retry
,input I_coretodctlb_st_type c0_s2_coretodctlb_st
// dcache core 0, slice 3
,input core0_slice3_coretodc_ld_valid
,output core0_slice3_coretodc_ld_retry
,input I_coretodc_ld_type core0_slice3_coretodc_ld
,output core0_slice3_dctocore_ld_valid
,input core0_slice3_dctocore_ld_retry
,output I_dctocore_ld_type core0_slice3_dctocore_ld
,input core0_slice3_coretodc_std_valid
,output core0_slice3_coretodc_std_retry
,input I_coretodc_std_type core0_slice3_coretodc_std
,output core0_slice3_dctocore_std_ack_valid
,input core0_slice3_dctocore_std_ack_retry
,output I_dctocore_std_ack_type core0_slice3_dctocore_std_ack
,input c0_s3_coretodctlb_ld_valid
,output c0_s3_coretodctlb_ld_retry
,input I_coretodctlb_ld_type c0_s3_coretodctlb_ld
,input c0_s3_coretodctlb_st_valid
,output c0_s3_coretodctlb_st_retry
,input I_coretodctlb_st_type c0_s3_coretodctlb_st
`endif
// core 0 prefetch
,input logic core0_pfgtopfe_op_valid
,output logic core0_pfgtopfe_op_retry
,input I_pfgtopfe_op_type core0_pfgtopfe_op
//******************************************
//* CORE 1 *
//******************************************//
// icache core 1
,input core1_coretoic_pc_valid
,output core1_coretoic_pc_retry
,input I_coretoic_pc_type core1_coretoic_pc
,output core1_ictocore_valid
,input core1_ictocore_retry
,output I_ictocore_type core1_ictocore
// dcache core 1, slice 0
,input core1_slice0_coretodc_ld_valid
,output core1_slice0_coretodc_ld_retry
,input I_coretodc_ld_type core1_slice0_coretodc_ld
,output core1_slice0_dctocore_ld_valid
,input core1_slice0_dctocore_ld_retry
,output I_dctocore_ld_type core1_slice0_dctocore_ld
,input core1_slice0_coretodc_std_valid
,output core1_slice0_coretodc_std_retry
,input I_coretodc_std_type core1_slice0_coretodc_std
,output core1_slice0_dctocore_std_ack_valid
,input core1_slice0_dctocore_std_ack_retry
,output I_dctocore_std_ack_type core1_slice0_dctocore_std_ack
,input c1_s0_coretodctlb_ld_valid
,output c1_s0_coretodctlb_ld_retry
,input I_coretodctlb_ld_type c1_s0_coretodctlb_ld
,input c1_s0_coretodctlb_st_valid
,output c1_s0_coretodctlb_st_retry
,input I_coretodctlb_st_type c1_s0_coretodctlb_st
// dcache core 1, slice 1
,input core1_slice1_coretodc_ld_valid
,output core1_slice1_coretodc_ld_retry
,input I_coretodc_ld_type core1_slice1_coretodc_ld
,output core1_slice1_dctocore_ld_valid
,input core1_slice1_dctocore_ld_retry
,output I_dctocore_ld_type core1_slice1_dctocore_ld
,input core1_slice1_coretodc_std_valid
,output core1_slice1_coretodc_std_retry
,input I_coretodc_std_type core1_slice1_coretodc_std
,output core1_slice1_dctocore_std_ack_valid
,input core1_slice1_dctocore_std_ack_retry
,output I_dctocore_std_ack_type core1_slice1_dctocore_std_ack
,input c1_s1_coretodctlb_ld_valid
,output c1_s1_coretodctlb_ld_retry
,input I_coretodctlb_ld_type c1_s1_coretodctlb_ld
,input c1_s1_coretodctlb_st_valid
,output c1_s1_coretodctlb_st_retry
,input I_coretodctlb_st_type c1_s1_coretodctlb_st
`ifdef SC_4PIPE
// dcache core 1, slice 2
,input core1_slice2_coretodc_ld_valid
,output core1_slice2_coretodc_ld_retry
,input I_coretodc_ld_type core1_slice2_coretodc_ld
,output core1_slice2_dctocore_ld_valid
,input core1_slice2_dctocore_ld_retry
,output I_dctocore_ld_type core1_slice2_dctocore_ld
,input core1_slice2_coretodc_std_valid
,output core1_slice2_coretodc_std_retry
,input I_coretodc_std_type core1_slice2_coretodc_std
,output core1_slice2_dctocore_std_ack_valid
,input core1_slice2_dctocore_std_ack_retry
,output I_dctocore_std_ack_type core1_slice2_dctocore_std_ack
,input c1_s2_coretodctlb_ld_valid
,output c1_s2_coretodctlb_ld_retry
,input I_coretodctlb_ld_type c1_s2_coretodctlb_ld
,input c1_s2_coretodctlb_st_valid
,output c1_s2_coretodctlb_st_retry
,input I_coretodctlb_st_type c1_s2_coretodctlb_st
// dcache core 1, slice 3
,input core1_slice3_coretodc_ld_valid
,output core1_slice3_coretodc_ld_retry
,input I_coretodc_ld_type core1_slice3_coretodc_ld
,output core1_slice3_dctocore_ld_valid
,input core1_slice3_dctocore_ld_retry
,output I_dctocore_ld_type core1_slice3_dctocore_ld
,input core1_slice3_coretodc_std_valid
,output core1_slice3_coretodc_std_retry
,input I_coretodc_std_type core1_slice3_coretodc_std
,output core1_slice3_dctocore_std_ack_valid
,input core1_slice3_dctocore_std_ack_retry
,output I_dctocore_std_ack_type core1_slice3_dctocore_std_ack
,input c1_s3_coretodctlb_ld_valid
,output c1_s3_coretodctlb_ld_retry
,input I_coretodctlb_ld_type c1_s3_coretodctlb_ld
,input c1_s3_coretodctlb_st_valid
,output c1_s3_coretodctlb_st_retry
,input I_coretodctlb_st_type c1_s3_coretodctlb_st
`endif
// core 1 prefetch
,input logic core1_pfgtopfe_op_valid
,output logic core1_pfgtopfe_op_retry
,input I_pfgtopfe_op_type core1_pfgtopfe_op
//******************************************
//* Directory 0 *
//******************************************//
,output dr0_drtomem_req_valid
,input dr0_drtomem_req_retry
,output I_drtomem_req_type dr0_drtomem_req
,input dr0_memtodr_ack_valid
,output dr0_memtodr_ack_retry
,input I_memtodr_ack_type dr0_memtodr_ack
,output dr0_drtomem_wb_valid
,input dr0_drtomem_wb_retry
,output I_drtomem_wb_type dr0_drtomem_wb
,output logic dr0_drtomem_pfreq_valid
,input logic dr0_drtomem_pfreq_retry
,output I_drtomem_pfreq_type dr0_drtomem_pfreq
//******************************************
//* Directory 1 *
//******************************************//
,output dr1_drtomem_req_valid
,input dr1_drtomem_req_retry
,output I_drtomem_req_type dr1_drtomem_req
,input dr1_memtodr_ack_valid
,output dr1_memtodr_ack_retry
,input I_memtodr_ack_type dr1_memtodr_ack
,output dr1_drtomem_wb_valid
,input dr1_drtomem_wb_retry
,output I_drtomem_wb_type dr1_drtomem_wb
,output logic dr1_drtomem_pfreq_valid
,input logic dr1_drtomem_pfreq_retry
,output I_drtomem_pfreq_type dr1_drtomem_pfreq
);
wire core0_slice0_l1tol2_req_valid ;
wire core0_slice0_l1tol2_req_retry ;
I_l1tol2_req_type core0_slice0_l1tol2_req ;
wire core0_slice0_l2tol1_snack_valid ;
wire core0_slice0_l2tol1_snack_retry ;
I_l2tol1_snack_type core0_slice0_l2tol1_snack ;
wire core0_slice0_l1tol2_snoop_ack_valid;
wire core0_slice0_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core0_slice0_l1tol2_snoop_ack ;
wire core0_slice0_l1tol2_disp_valid ;
wire core0_slice0_l1tol2_disp_retry ;
I_l1tol2_disp_type core0_slice0_l1tol2_disp ;
wire core0_slice0_l2tol1_dack_valid ;
wire core0_slice0_l2tol1_dack_retry ;
I_l2tol1_dack_type core0_slice0_l2tol1_dack ;
PF_cache_stats_type core0_slice0_pf0_dcstats ;
wire core0_slice0_l1tol2tlb_req_valid;
wire core0_slice0_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core0_slice0_l1tol2tlb_req ;
dcache_pipe core0_slice0_dcache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_slice0_l1tol2_req_valid )
,.l1tol2_req_retry (core0_slice0_l1tol2_req_retry )
,.l1tol2_req (core0_slice0_l1tol2_req )
,.l2tol1_snack_valid (core0_slice0_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_slice0_l2tol1_snack_retry )
,.l2tol1_snack (core0_slice0_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_slice0_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_slice0_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_slice0_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core0_slice0_l1tol2_disp_valid )
,.l1tol2_disp_retry (core0_slice0_l1tol2_disp_retry )
,.l1tol2_disp (core0_slice0_l1tol2_disp )
,.l2tol1_dack_valid (core0_slice0_l2tol1_dack_valid )
,.l2tol1_dack_retry (core0_slice0_l2tol1_dack_retry )
,.l2tol1_dack (core0_slice0_l2tol1_dack )
,.l1tol2tlb_req_valid(core0_slice0_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_slice0_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_slice0_l1tol2tlb_req )
,.coretodc_ld_valid (core0_slice0_coretodc_ld_valid )
,.coretodc_ld_retry (core0_slice0_coretodc_ld_retry )
,.coretodc_ld (core0_slice0_coretodc_ld )
,.dctocore_ld_valid (core0_slice0_dctocore_ld_valid )
,.dctocore_ld_retry (core0_slice0_dctocore_ld_retry )
,.dctocore_ld (core0_slice0_dctocore_ld )
,.coretodc_std_valid (core0_slice0_coretodc_std_valid )
,.coretodc_std_retry (core0_slice0_coretodc_std_retry )
,.coretodc_std (core0_slice0_coretodc_std )
,.dctocore_std_ack_valid(core0_slice0_dctocore_std_ack_valid)
,.dctocore_std_ack_retry(core0_slice0_dctocore_std_ack_retry)
,.dctocore_std_ack (core0_slice0_dctocore_std_ack )
,.cachetopf_stats (core0_slice0_pf0_dcstats )
,.l1tlbtol1_fwd0_valid(core0_slice0_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core0_slice0_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core0_slice0_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core0_slice0_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core0_slice0_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core0_slice0_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core0_slice0_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core0_slice0_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core0_slice0_l1tlbtol1_cmd )
);
wire core0_slice0_l1tlbtol1_fwd0_valid;
wire core0_slice0_l1tlbtol1_fwd0_retry;
I_l1tlbtol1_fwd_type core0_slice0_l1tlbtol1_fwd0 ;
wire core0_slice0_l1tlbtol1_fwd1_valid;
wire core0_slice0_l1tlbtol1_fwd1_retry;
I_l1tlbtol1_fwd_type core0_slice0_l1tlbtol1_fwd1 ;
wire core0_slice0_l1tlbtol1_cmd_valid ;
wire core0_slice0_l1tlbtol1_cmd_retry ;
I_l1tlbtol1_cmd_type core0_slice0_l1tlbtol1_cmd ;
wire core0_slice0_l2tlbtol1tlb_snoop_valid;
wire core0_slice0_l2tlbtol1tlb_snoop_retry;
I_l2tlbtol1tlb_snoop_type core0_slice0_l2tlbtol1tlb_snoop ;
wire core0_slice0_l2tlbtol1tlb_ack_valid ;
wire core0_slice0_l2tlbtol1tlb_ack_retry ;
I_l2tlbtol1tlb_ack_type core0_slice0_l2tlbtol1tlb_ack ;
wire core0_slice0_l1tlbtol2tlb_req_valid ;
wire core0_slice0_l1tlbtol2tlb_req_retry ;
I_l1tlbtol2tlb_req_type core0_slice0_l1tlbtol2tlb_req ;
wire core0_slice0_l1tlbtol2tlb_sack_valid ;
wire core0_slice0_l1tlbtol2tlb_sack_retry ;
I_l1tlbtol2tlb_sack_type core0_slice0_l1tlbtol2tlb_sack ;
wire core0_slice0_pftodc_req0_valid;
wire core0_slice0_pftodc_req0_retry;
I_pfetol1tlb_req_type core0_slice0_pftodc_req0 ;
dctlb dcltb_c0s0(
.clk(clk)
,.reset(reset)
,.coretodctlb_ld_valid(c0_s0_coretodctlb_ld_valid)
,.coretodctlb_ld_retry(c0_s0_coretodctlb_ld_retry)
,.coretodctlb_ld (c0_s0_coretodctlb_ld )
,.coretodctlb_st_valid(c0_s0_coretodctlb_st_valid)
,.coretodctlb_st_retry(c0_s0_coretodctlb_st_retry)
,.coretodctlb_st (c0_s0_coretodctlb_st )
,.pfetol1tlb_req_valid (core0_slice0_pftodc_req0_valid)
,.pfetol1tlb_req_retry (core0_slice0_pftodc_req0_retry)
,.pfetol1tlb_req (core0_slice0_pftodc_req0 )
,.l1tlbtol1_fwd0_valid(core0_slice0_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core0_slice0_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core0_slice0_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core0_slice0_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core0_slice0_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core0_slice0_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core0_slice0_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core0_slice0_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core0_slice0_l1tlbtol1_cmd )
,.l2tlbtol1tlb_snoop_valid(core0_slice0_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core0_slice0_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core0_slice0_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core0_slice0_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core0_slice0_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core0_slice0_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core0_slice0_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core0_slice0_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core0_slice0_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core0_slice0_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core0_slice0_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core0_slice0_l1tlbtol2tlb_sack )
);
wire core0_slice1_l1tol2_req_valid ;
wire core0_slice1_l1tol2_req_retry ;
I_l1tol2_req_type core0_slice1_l1tol2_req ;
wire core0_slice1_l2tol1_snack_valid ;
wire core0_slice1_l2tol1_snack_retry ;
I_l2tol1_snack_type core0_slice1_l2tol1_snack ;
wire core0_slice1_l1tol2_snoop_ack_valid;
wire core0_slice1_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core0_slice1_l1tol2_snoop_ack ;
wire core0_slice1_l1tol2_disp_valid ;
wire core0_slice1_l1tol2_disp_retry ;
I_l1tol2_disp_type core0_slice1_l1tol2_disp ;
wire core0_slice1_l2tol1_dack_valid ;
wire core0_slice1_l2tol1_dack_retry ;
I_l2tol1_dack_type core0_slice1_l2tol1_dack ;
PF_cache_stats_type core0_slice1_pf1_dcstats ;
wire core0_slice1_l1tol2tlb_req_valid;
wire core0_slice1_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core0_slice1_l1tol2tlb_req ;
dcache_pipe core0_slice1_dcache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_slice1_l1tol2_req_valid )
,.l1tol2_req_retry (core0_slice1_l1tol2_req_retry )
,.l1tol2_req (core0_slice1_l1tol2_req )
,.l2tol1_snack_valid (core0_slice1_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_slice1_l2tol1_snack_retry )
,.l2tol1_snack (core0_slice1_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_slice1_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_slice1_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_slice1_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core0_slice1_l1tol2_disp_valid )
,.l1tol2_disp_retry (core0_slice1_l1tol2_disp_retry )
,.l1tol2_disp (core0_slice1_l1tol2_disp )
,.l2tol1_dack_valid (core0_slice1_l2tol1_dack_valid )
,.l2tol1_dack_retry (core0_slice1_l2tol1_dack_retry )
,.l2tol1_dack (core0_slice1_l2tol1_dack )
,.l1tol2tlb_req_valid(core0_slice1_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_slice1_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_slice1_l1tol2tlb_req )
,.coretodc_ld_valid (core0_slice1_coretodc_ld_valid )
,.coretodc_ld_retry (core0_slice1_coretodc_ld_retry )
,.coretodc_ld (core0_slice1_coretodc_ld )
,.dctocore_ld_valid (core0_slice1_dctocore_ld_valid )
,.dctocore_ld_retry (core0_slice1_dctocore_ld_retry )
,.dctocore_ld (core0_slice1_dctocore_ld )
,.coretodc_std_valid (core0_slice1_coretodc_std_valid )
,.coretodc_std_retry (core0_slice1_coretodc_std_retry )
,.coretodc_std (core0_slice1_coretodc_std )
,.dctocore_std_ack_valid(core0_slice1_dctocore_std_ack_valid)
,.dctocore_std_ack_retry(core0_slice1_dctocore_std_ack_retry)
,.dctocore_std_ack (core0_slice1_dctocore_std_ack )
,.cachetopf_stats (core0_slice1_pf1_dcstats )
,.l1tlbtol1_fwd0_valid(core0_slice1_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core0_slice1_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core0_slice1_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core0_slice1_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core0_slice1_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core0_slice1_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core0_slice1_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core0_slice1_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core0_slice1_l1tlbtol1_cmd )
);
wire core0_slice1_l1tlbtol1_fwd0_valid;
wire core0_slice1_l1tlbtol1_fwd0_retry;
I_l1tlbtol1_fwd_type core0_slice1_l1tlbtol1_fwd0 ;
wire core0_slice1_l1tlbtol1_fwd1_valid;
wire core0_slice1_l1tlbtol1_fwd1_retry;
I_l1tlbtol1_fwd_type core0_slice1_l1tlbtol1_fwd1 ;
wire core0_slice1_l1tlbtol1_cmd_valid ;
wire core0_slice1_l1tlbtol1_cmd_retry ;
I_l1tlbtol1_cmd_type core0_slice1_l1tlbtol1_cmd ;
wire core0_slice1_l2tlbtol1tlb_snoop_valid;
wire core0_slice1_l2tlbtol1tlb_snoop_retry;
I_l2tlbtol1tlb_snoop_type core0_slice1_l2tlbtol1tlb_snoop ;
wire core0_slice1_l2tlbtol1tlb_ack_valid ;
wire core0_slice1_l2tlbtol1tlb_ack_retry ;
I_l2tlbtol1tlb_ack_type core0_slice1_l2tlbtol1tlb_ack ;
wire core0_slice1_l1tlbtol2tlb_req_valid ;
wire core0_slice1_l1tlbtol2tlb_req_retry ;
I_l1tlbtol2tlb_req_type core0_slice1_l1tlbtol2tlb_req ;
wire core0_slice1_l1tlbtol2tlb_sack_valid ;
wire core0_slice1_l1tlbtol2tlb_sack_retry ;
I_l1tlbtol2tlb_sack_type core0_slice1_l1tlbtol2tlb_sack ;
wire core0_slice1_pftodc_req1_valid;
wire core0_slice1_pftodc_req1_retry;
I_pfetol1tlb_req_type core0_slice1_pftodc_req1 ;
dctlb dcltb_c0s1(
.clk(clk)
,.reset(reset)
,.coretodctlb_ld_valid(c0_s1_coretodctlb_ld_valid)
,.coretodctlb_ld_retry(c0_s1_coretodctlb_ld_retry)
,.coretodctlb_ld (c0_s1_coretodctlb_ld )
,.coretodctlb_st_valid(c0_s1_coretodctlb_st_valid)
,.coretodctlb_st_retry(c0_s1_coretodctlb_st_retry)
,.coretodctlb_st (c0_s1_coretodctlb_st )
,.pfetol1tlb_req_valid (core0_slice1_pftodc_req1_valid)
,.pfetol1tlb_req_retry (core0_slice1_pftodc_req1_retry)
,.pfetol1tlb_req (core0_slice1_pftodc_req1 )
,.l1tlbtol1_fwd0_valid(core0_slice1_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core0_slice1_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core0_slice1_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core0_slice1_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core0_slice1_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core0_slice1_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core0_slice1_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core0_slice1_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core0_slice1_l1tlbtol1_cmd )
,.l2tlbtol1tlb_snoop_valid(core0_slice1_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core0_slice1_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core0_slice1_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core0_slice1_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core0_slice1_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core0_slice1_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core0_slice1_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core0_slice1_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core0_slice1_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core0_slice1_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core0_slice1_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core0_slice1_l1tlbtol2tlb_sack )
);
`ifdef SC_4PIPE
wire core0_slice2_l1tol2_req_valid ;
wire core0_slice2_l1tol2_req_retry ;
I_l1tol2_req_type core0_slice2_l1tol2_req ;
wire core0_slice2_l2tol1_snack_valid ;
wire core0_slice2_l2tol1_snack_retry ;
I_l2tol1_snack_type core0_slice2_l2tol1_snack ;
wire core0_slice2_l1tol2_snoop_ack_valid;
wire core0_slice2_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core0_slice2_l1tol2_snoop_ack ;
wire core0_slice2_l1tol2_disp_valid ;
wire core0_slice2_l1tol2_disp_retry ;
I_l1tol2_disp_type core0_slice2_l1tol2_disp ;
wire core0_slice2_l2tol1_dack_valid ;
wire core0_slice2_l2tol1_dack_retry ;
I_l2tol1_dack_type core0_slice2_l2tol1_dack ;
PF_cache_stats_type core0_slice2_pf2_dcstats ;
wire core0_slice2_l1tol2tlb_req_valid;
wire core0_slice2_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core0_slice2_l1tol2tlb_req ;
dcache_pipe core0_slice2_dcache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_slice2_l1tol2_req_valid )
,.l1tol2_req_retry (core0_slice2_l1tol2_req_retry )
,.l1tol2_req (core0_slice2_l1tol2_req )
,.l2tol1_snack_valid (core0_slice2_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_slice2_l2tol1_snack_retry )
,.l2tol1_snack (core0_slice2_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_slice2_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_slice2_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_slice2_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core0_slice2_l1tol2_disp_valid )
,.l1tol2_disp_retry (core0_slice2_l1tol2_disp_retry )
,.l1tol2_disp (core0_slice2_l1tol2_disp )
,.l2tol1_dack_valid (core0_slice2_l2tol1_dack_valid )
,.l2tol1_dack_retry (core0_slice2_l2tol1_dack_retry )
,.l2tol1_dack (core0_slice2_l2tol1_dack )
,.l1tol2tlb_req_valid(core0_slice2_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_slice2_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_slice2_l1tol2tlb_req )
,.coretodc_ld_valid (core0_slice2_coretodc_ld_valid )
,.coretodc_ld_retry (core0_slice2_coretodc_ld_retry )
,.coretodc_ld (core0_slice2_coretodc_ld )
,.dctocore_ld_valid (core0_slice2_dctocore_ld_valid )
,.dctocore_ld_retry (core0_slice2_dctocore_ld_retry )
,.dctocore_ld (core0_slice2_dctocore_ld )
,.coretodc_std_valid (core0_slice2_coretodc_std_valid )
,.coretodc_std_retry (core0_slice2_coretodc_std_retry )
,.coretodc_std (core0_slice2_coretodc_std )
,.dctocore_std_ack_valid(core0_slice2_dctocore_std_ack_valid)
,.dctocore_std_ack_retry(core0_slice2_dctocore_std_ack_retry)
,.dctocore_std_ack (core0_slice2_dctocore_std_ack )
,.cachetopf_stats (core0_slice2_pf2_dcstats )
,.l1tlbtol1_fwd0_valid(core0_slice2_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core0_slice2_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core0_slice2_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core0_slice2_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core0_slice2_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core0_slice2_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core0_slice2_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core0_slice2_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core0_slice2_l1tlbtol1_cmd )
);
wire core0_slice2_l1tlbtol1_fwd0_valid;
wire core0_slice2_l1tlbtol1_fwd0_retry;
I_l1tlbtol1_fwd_type core0_slice2_l1tlbtol1_fwd0 ;
wire core0_slice2_l1tlbtol1_fwd1_valid;
wire core0_slice2_l1tlbtol1_fwd1_retry;
I_l1tlbtol1_fwd_type core0_slice2_l1tlbtol1_fwd1 ;
wire core0_slice2_l1tlbtol1_cmd_valid ;
wire core0_slice2_l1tlbtol1_cmd_retry ;
I_l1tlbtol1_cmd_type core0_slice2_l1tlbtol1_cmd ;
wire core0_slice2_l2tlbtol1tlb_snoop_valid;
wire core0_slice2_l2tlbtol1tlb_snoop_retry;
I_l2tlbtol1tlb_snoop_type core0_slice2_l2tlbtol1tlb_snoop ;
wire core0_slice2_l2tlbtol1tlb_ack_valid ;
wire core0_slice2_l2tlbtol1tlb_ack_retry ;
I_l2tlbtol1tlb_ack_type core0_slice2_l2tlbtol1tlb_ack ;
wire core0_slice2_l1tlbtol2tlb_req_valid ;
wire core0_slice2_l1tlbtol2tlb_req_retry ;
I_l1tlbtol2tlb_req_type core0_slice2_l1tlbtol2tlb_req ;
wire core0_slice2_l1tlbtol2tlb_sack_valid ;
wire core0_slice2_l1tlbtol2tlb_sack_retry ;
I_l1tlbtol2tlb_sack_type core0_slice2_l1tlbtol2tlb_sack ;
wire core0_slice2_pftodc_req2_valid;
wire core0_slice2_pftodc_req2_retry;
I_pfetol1tlb_req_type core0_slice2_pftodc_req2 ;
dctlb dcltb_c0s2(
.clk(clk)
,.reset(reset)
,.coretodctlb_ld_valid(c0_s2_coretodctlb_ld_valid)
,.coretodctlb_ld_retry(c0_s2_coretodctlb_ld_retry)
,.coretodctlb_ld (c0_s2_coretodctlb_ld )
,.coretodctlb_st_valid(c0_s2_coretodctlb_st_valid)
,.coretodctlb_st_retry(c0_s2_coretodctlb_st_retry)
,.coretodctlb_st (c0_s2_coretodctlb_st )
,.pfetol1tlb_req_valid (core0_slice2_pftodc_req2_valid)
,.pfetol1tlb_req_retry (core0_slice2_pftodc_req2_retry)
,.pfetol1tlb_req (core0_slice2_pftodc_req2 )
,.l1tlbtol1_fwd0_valid(core0_slice2_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core0_slice2_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core0_slice2_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core0_slice2_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core0_slice2_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core0_slice2_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core0_slice2_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core0_slice2_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core0_slice2_l1tlbtol1_cmd )
,.l2tlbtol1tlb_snoop_valid(core0_slice2_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core0_slice2_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core0_slice2_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core0_slice2_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core0_slice2_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core0_slice2_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core0_slice2_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core0_slice2_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core0_slice2_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core0_slice2_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core0_slice2_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core0_slice2_l1tlbtol2tlb_sack )
);
wire core0_slice3_l1tol2_req_valid ;
wire core0_slice3_l1tol2_req_retry ;
I_l1tol2_req_type core0_slice3_l1tol2_req ;
wire core0_slice3_l2tol1_snack_valid ;
wire core0_slice3_l2tol1_snack_retry ;
I_l2tol1_snack_type core0_slice3_l2tol1_snack ;
wire core0_slice3_l1tol2_snoop_ack_valid;
wire core0_slice3_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core0_slice3_l1tol2_snoop_ack ;
wire core0_slice3_l1tol2_disp_valid ;
wire core0_slice3_l1tol2_disp_retry ;
I_l1tol2_disp_type core0_slice3_l1tol2_disp ;
wire core0_slice3_l2tol1_dack_valid ;
wire core0_slice3_l2tol1_dack_retry ;
I_l2tol1_dack_type core0_slice3_l2tol1_dack ;
PF_cache_stats_type core0_slice3_pf3_dcstats ;
wire core0_slice3_l1tol2tlb_req_valid;
wire core0_slice3_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core0_slice3_l1tol2tlb_req ;
dcache_pipe core0_slice3_dcache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_slice3_l1tol2_req_valid )
,.l1tol2_req_retry (core0_slice3_l1tol2_req_retry )
,.l1tol2_req (core0_slice3_l1tol2_req )
,.l2tol1_snack_valid (core0_slice3_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_slice3_l2tol1_snack_retry )
,.l2tol1_snack (core0_slice3_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_slice3_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_slice3_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_slice3_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core0_slice3_l1tol2_disp_valid )
,.l1tol2_disp_retry (core0_slice3_l1tol2_disp_retry )
,.l1tol2_disp (core0_slice3_l1tol2_disp )
,.l2tol1_dack_valid (core0_slice3_l2tol1_dack_valid )
,.l2tol1_dack_retry (core0_slice3_l2tol1_dack_retry )
,.l2tol1_dack (core0_slice3_l2tol1_dack )
,.l1tol2tlb_req_valid(core0_slice3_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_slice3_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_slice3_l1tol2tlb_req )
,.coretodc_ld_valid (core0_slice3_coretodc_ld_valid )
,.coretodc_ld_retry (core0_slice3_coretodc_ld_retry )
,.coretodc_ld (core0_slice3_coretodc_ld )
,.dctocore_ld_valid (core0_slice3_dctocore_ld_valid )
,.dctocore_ld_retry (core0_slice3_dctocore_ld_retry )
,.dctocore_ld (core0_slice3_dctocore_ld )
,.coretodc_std_valid (core0_slice3_coretodc_std_valid )
,.coretodc_std_retry (core0_slice3_coretodc_std_retry )
,.coretodc_std (core0_slice3_coretodc_std )
,.dctocore_std_ack_valid(core0_slice3_dctocore_std_ack_valid)
,.dctocore_std_ack_retry(core0_slice3_dctocore_std_ack_retry)
,.dctocore_std_ack (core0_slice3_dctocore_std_ack )
,.cachetopf_stats (core0_slice3_pf3_dcstats )
,.l1tlbtol1_fwd0_valid(core0_slice3_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core0_slice3_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core0_slice3_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core0_slice3_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core0_slice3_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core0_slice3_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core0_slice3_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core0_slice3_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core0_slice3_l1tlbtol1_cmd )
);
wire core0_slice3_l1tlbtol1_fwd0_valid;
wire core0_slice3_l1tlbtol1_fwd0_retry;
I_l1tlbtol1_fwd_type core0_slice3_l1tlbtol1_fwd0 ;
wire core0_slice3_l1tlbtol1_fwd1_valid;
wire core0_slice3_l1tlbtol1_fwd1_retry;
I_l1tlbtol1_fwd_type core0_slice3_l1tlbtol1_fwd1 ;
wire core0_slice3_l1tlbtol1_cmd_valid ;
wire core0_slice3_l1tlbtol1_cmd_retry ;
I_l1tlbtol1_cmd_type core0_slice3_l1tlbtol1_cmd ;
wire core0_slice3_l2tlbtol1tlb_snoop_valid;
wire core0_slice3_l2tlbtol1tlb_snoop_retry;
I_l2tlbtol1tlb_snoop_type core0_slice3_l2tlbtol1tlb_snoop ;
wire core0_slice3_l2tlbtol1tlb_ack_valid ;
wire core0_slice3_l2tlbtol1tlb_ack_retry ;
I_l2tlbtol1tlb_ack_type core0_slice3_l2tlbtol1tlb_ack ;
wire core0_slice3_l1tlbtol2tlb_req_valid ;
wire core0_slice3_l1tlbtol2tlb_req_retry ;
I_l1tlbtol2tlb_req_type core0_slice3_l1tlbtol2tlb_req ;
wire core0_slice3_l1tlbtol2tlb_sack_valid ;
wire core0_slice3_l1tlbtol2tlb_sack_retry ;
I_l1tlbtol2tlb_sack_type core0_slice3_l1tlbtol2tlb_sack ;
wire core0_slice3_pftodc_req3_valid;
wire core0_slice3_pftodc_req3_retry;
I_pfetol1tlb_req_type core0_slice3_pftodc_req3 ;
dctlb dcltb_c0s3(
.clk(clk)
,.reset(reset)
,.coretodctlb_ld_valid(c0_s3_coretodctlb_ld_valid)
,.coretodctlb_ld_retry(c0_s3_coretodctlb_ld_retry)
,.coretodctlb_ld (c0_s3_coretodctlb_ld )
,.coretodctlb_st_valid(c0_s3_coretodctlb_st_valid)
,.coretodctlb_st_retry(c0_s3_coretodctlb_st_retry)
,.coretodctlb_st (c0_s3_coretodctlb_st )
,.pfetol1tlb_req_valid (core0_slice3_pftodc_req3_valid)
,.pfetol1tlb_req_retry (core0_slice3_pftodc_req3_retry)
,.pfetol1tlb_req (core0_slice3_pftodc_req3 )
,.l1tlbtol1_fwd0_valid(core0_slice3_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core0_slice3_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core0_slice3_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core0_slice3_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core0_slice3_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core0_slice3_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core0_slice3_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core0_slice3_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core0_slice3_l1tlbtol1_cmd )
,.l2tlbtol1tlb_snoop_valid(core0_slice3_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core0_slice3_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core0_slice3_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core0_slice3_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core0_slice3_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core0_slice3_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core0_slice3_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core0_slice3_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core0_slice3_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core0_slice3_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core0_slice3_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core0_slice3_l1tlbtol2tlb_sack )
);
`endif
wire core0_l1tol2_req_valid ;
wire core0_l1tol2_req_retry ;
I_l1tol2_req_type core0_l1tol2_req ;
wire core0_l2tol1_snack_valid ;
wire core0_l2tol1_snack_retry ;
I_l2tol1_snack_type core0_l2tol1_snack ;
wire core0_l1tol2_snoop_ack_valid;
wire core0_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core0_l1tol2_snoop_ack ;
wire core0_l1tlbtol1_fwd_valid;
wire core0_l1tlbtol1_fwd_retry;
I_l1tlbtol1_fwd_type core0_l1tlbtol1_fwd ;
wire core0_l1tlbtol1_cmd_valid;
wire core0_l1tlbtol1_cmd_retry;
I_l1tlbtol1_cmd_type core0_l1tlbtol1_cmd ;
wire core0_l1tol2tlb_req_valid;
wire core0_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core0_l1tol2tlb_req ;
PF_cache_stats_type core0_cachetopf_stats;
icache core0_icache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_l1tol2_req_valid )
,.l1tol2_req_retry (core0_l1tol2_req_retry )
,.l1tol2_req (core0_l1tol2_req )
,.l2tol1_snack_valid (core0_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_l2tol1_snack_retry )
,.l2tol1_snack (core0_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_l1tol2_snoop_ack )
,.l1tlbtol1_fwd_valid(core0_l1tlbtol1_fwd_valid)
,.l1tlbtol1_fwd_retry(core0_l1tlbtol1_fwd_retry)
,.l1tlbtol1_fwd (core0_l1tlbtol1_fwd )
,.l1tlbtol1_cmd_valid(core0_l1tlbtol1_cmd_valid)
,.l1tlbtol1_cmd_retry(core0_l1tlbtol1_cmd_retry)
,.l1tlbtol1_cmd (core0_l1tlbtol1_cmd )
,.l1tol2tlb_req_valid(core0_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_l1tol2tlb_req )
,.cachetopf_stats(core0_cachetopf_stats)
,.coretoic_pc_valid (core0_coretoic_pc_valid )
,.coretoic_pc_retry (core0_coretoic_pc_retry )
,.coretoic_pc (core0_coretoic_pc )
,.ictocore_valid (core0_ictocore_valid )
,.ictocore_retry (core0_ictocore_retry )
,.ictocore (core0_ictocore )
);
PF_cache_stats_type core0_slice0_pf0_l2stats ;
wire core0_slice0_l2todr_req_valid ;
wire core0_slice0_l2todr_req_retry ;
I_l2todr_req_type core0_slice0_l2todr_req ;
wire core0_slice0_drtol2_snack_valid ;
wire core0_slice0_drtol2_snack_retry ;
I_drtol2_snack_type core0_slice0_drtol2_snack ;
wire core0_slice0_l2todr_disp_valid ;
wire core0_slice0_l2todr_disp_retry ;
I_l2todr_disp_type core0_slice0_l2todr_disp ;
wire core0_slice0_drtol2_dack_valid ;
wire core0_slice0_drtol2_dack_retry ;
I_drtol2_dack_type core0_slice0_drtol2_dack ;
wire core0_slice0_l2todr_snoop_ack_valid;
wire core0_slice0_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_slice0_l2todr_snoop_ack ;
PF_cache_stats_type core0_l2d_slice0_pf0_dcstats ;
wire core0_slice0_l2todr_pfreq_valid ;
wire core0_slice0_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core0_slice0_l2todr_pfreq ;
wire core0_slice0_l2tlbtol2_fwd_valid;
wire core0_slice0_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core0_slice0_l2tlbtol2_fwd ;
l2cache_pipe core0_l2d_slice0(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_slice0_l1tol2_req_valid )
,.l1tol2_req_retry (core0_slice0_l1tol2_req_retry )
,.l1tol2_req (core0_slice0_l1tol2_req )
,.l2tol1_snack_valid (core0_slice0_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_slice0_l2tol1_snack_retry )
,.l2tol1_snack (core0_slice0_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_slice0_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_slice0_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_slice0_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core0_slice0_l1tol2_disp_valid )
,.l1tol2_disp_retry (core0_slice0_l1tol2_disp_retry )
,.l1tol2_disp (core0_slice0_l1tol2_disp )
,.l2tol1_dack_valid (core0_slice0_l2tol1_dack_valid )
,.l2tol1_dack_retry (core0_slice0_l2tol1_dack_retry )
,.l2tol1_dack (core0_slice0_l2tol1_dack )
,.l2todr_pfreq_valid (core0_slice0_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core0_slice0_l2todr_pfreq_retry )
,.l2todr_pfreq (core0_slice0_l2todr_pfreq )
,.l2tlbtol2_fwd_valid(core0_slice0_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_slice0_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_slice0_l2tlbtol2_fwd )
,.l2todr_req_valid (core0_slice0_l2todr_req_valid )
,.l2todr_req_retry (core0_slice0_l2todr_req_retry )
,.l2todr_req (core0_slice0_l2todr_req )
,.drtol2_snack_valid (core0_slice0_drtol2_snack_valid )
,.drtol2_snack_retry (core0_slice0_drtol2_snack_retry )
,.drtol2_snack (core0_slice0_drtol2_snack )
,.l2todr_disp_valid (core0_slice0_l2todr_disp_valid )
,.l2todr_disp_retry (core0_slice0_l2todr_disp_retry )
,.l2todr_disp (core0_slice0_l2todr_disp )
,.drtol2_dack_valid (core0_slice0_drtol2_dack_valid )
,.drtol2_dack_retry (core0_slice0_drtol2_dack_retry )
,.drtol2_dack (core0_slice0_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_slice0_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_slice0_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_slice0_l2todr_snoop_ack )
,.cachetopf_stats (core0_slice0_pf0_l2stats )
);
wire core0_slice0_l2tlb_l2todr_req_valid ;
wire core0_slice0_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core0_slice0_l2tlb_l2todr_req ;
wire core0_slice0_l2tlb_drtol2_snack_valid ;
wire core0_slice0_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core0_slice0_l2tlb_drtol2_snack ;
wire core0_slice0_l2tlb_l2todr_disp_valid ;
wire core0_slice0_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core0_slice0_l2tlb_l2todr_disp ;
wire core0_slice0_l2tlb_drtol2_dack_valid ;
wire core0_slice0_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core0_slice0_l2tlb_drtol2_dack ;
wire core0_slice0_l2tlb_l2todr_snoop_ack_valid;
wire core0_slice0_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_slice0_l2tlb_l2todr_snoop_ack ;
l2tlb l2tlb_core0_slice0(
.clk(clk)
,.reset(reset)
,.l2tlbtol1tlb_snoop_valid(core0_slice0_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core0_slice0_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core0_slice0_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core0_slice0_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core0_slice0_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core0_slice0_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core0_slice0_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core0_slice0_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core0_slice0_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core0_slice0_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core0_slice0_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core0_slice0_l1tlbtol2tlb_sack )
,.l1tol2tlb_req_valid(core0_slice0_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_slice0_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_slice0_l1tol2tlb_req )
,.l2tlbtol2_fwd_valid(core0_slice0_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_slice0_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_slice0_l2tlbtol2_fwd )
,.l2todr_req_valid (core0_slice0_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core0_slice0_l2tlb_l2todr_req_retry )
,.l2todr_req (core0_slice0_l2tlb_l2todr_req )
,.drtol2_snack_valid (core0_slice0_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core0_slice0_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core0_slice0_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core0_slice0_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core0_slice0_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core0_slice0_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core0_slice0_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core0_slice0_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core0_slice0_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_slice0_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_slice0_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_slice0_l2tlb_l2todr_snoop_ack )
);
PF_cache_stats_type core0_slice1_pf1_l2stats ;
wire core0_slice1_l2todr_req_valid ;
wire core0_slice1_l2todr_req_retry ;
I_l2todr_req_type core0_slice1_l2todr_req ;
wire core0_slice1_drtol2_snack_valid ;
wire core0_slice1_drtol2_snack_retry ;
I_drtol2_snack_type core0_slice1_drtol2_snack ;
wire core0_slice1_l2todr_disp_valid ;
wire core0_slice1_l2todr_disp_retry ;
I_l2todr_disp_type core0_slice1_l2todr_disp ;
wire core0_slice1_drtol2_dack_valid ;
wire core0_slice1_drtol2_dack_retry ;
I_drtol2_dack_type core0_slice1_drtol2_dack ;
wire core0_slice1_l2todr_snoop_ack_valid;
wire core0_slice1_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_slice1_l2todr_snoop_ack ;
PF_cache_stats_type core0_l2d_slice1_pf1_dcstats ;
wire core0_slice1_l2todr_pfreq_valid ;
wire core0_slice1_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core0_slice1_l2todr_pfreq ;
wire core0_slice1_l2tlbtol2_fwd_valid;
wire core0_slice1_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core0_slice1_l2tlbtol2_fwd ;
l2cache_pipe core0_l2d_slice1(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_slice1_l1tol2_req_valid )
,.l1tol2_req_retry (core0_slice1_l1tol2_req_retry )
,.l1tol2_req (core0_slice1_l1tol2_req )
,.l2tol1_snack_valid (core0_slice1_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_slice1_l2tol1_snack_retry )
,.l2tol1_snack (core0_slice1_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_slice1_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_slice1_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_slice1_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core0_slice1_l1tol2_disp_valid )
,.l1tol2_disp_retry (core0_slice1_l1tol2_disp_retry )
,.l1tol2_disp (core0_slice1_l1tol2_disp )
,.l2tol1_dack_valid (core0_slice1_l2tol1_dack_valid )
,.l2tol1_dack_retry (core0_slice1_l2tol1_dack_retry )
,.l2tol1_dack (core0_slice1_l2tol1_dack )
,.l2todr_pfreq_valid (core0_slice1_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core0_slice1_l2todr_pfreq_retry )
,.l2todr_pfreq (core0_slice1_l2todr_pfreq )
,.l2tlbtol2_fwd_valid(core0_slice1_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_slice1_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_slice1_l2tlbtol2_fwd )
,.l2todr_req_valid (core0_slice1_l2todr_req_valid )
,.l2todr_req_retry (core0_slice1_l2todr_req_retry )
,.l2todr_req (core0_slice1_l2todr_req )
,.drtol2_snack_valid (core0_slice1_drtol2_snack_valid )
,.drtol2_snack_retry (core0_slice1_drtol2_snack_retry )
,.drtol2_snack (core0_slice1_drtol2_snack )
,.l2todr_disp_valid (core0_slice1_l2todr_disp_valid )
,.l2todr_disp_retry (core0_slice1_l2todr_disp_retry )
,.l2todr_disp (core0_slice1_l2todr_disp )
,.drtol2_dack_valid (core0_slice1_drtol2_dack_valid )
,.drtol2_dack_retry (core0_slice1_drtol2_dack_retry )
,.drtol2_dack (core0_slice1_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_slice1_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_slice1_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_slice1_l2todr_snoop_ack )
,.cachetopf_stats (core0_slice1_pf1_l2stats )
);
wire core0_slice1_l2tlb_l2todr_req_valid ;
wire core0_slice1_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core0_slice1_l2tlb_l2todr_req ;
wire core0_slice1_l2tlb_drtol2_snack_valid ;
wire core0_slice1_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core0_slice1_l2tlb_drtol2_snack ;
wire core0_slice1_l2tlb_l2todr_disp_valid ;
wire core0_slice1_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core0_slice1_l2tlb_l2todr_disp ;
wire core0_slice1_l2tlb_drtol2_dack_valid ;
wire core0_slice1_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core0_slice1_l2tlb_drtol2_dack ;
wire core0_slice1_l2tlb_l2todr_snoop_ack_valid;
wire core0_slice1_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_slice1_l2tlb_l2todr_snoop_ack ;
l2tlb l2tlb_core0_slice1(
.clk(clk)
,.reset(reset)
,.l2tlbtol1tlb_snoop_valid(core0_slice1_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core0_slice1_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core0_slice1_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core0_slice1_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core0_slice1_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core0_slice1_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core0_slice1_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core0_slice1_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core0_slice1_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core0_slice1_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core0_slice1_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core0_slice1_l1tlbtol2tlb_sack )
,.l1tol2tlb_req_valid(core0_slice1_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_slice1_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_slice1_l1tol2tlb_req )
,.l2tlbtol2_fwd_valid(core0_slice1_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_slice1_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_slice1_l2tlbtol2_fwd )
,.l2todr_req_valid (core0_slice1_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core0_slice1_l2tlb_l2todr_req_retry )
,.l2todr_req (core0_slice1_l2tlb_l2todr_req )
,.drtol2_snack_valid (core0_slice1_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core0_slice1_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core0_slice1_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core0_slice1_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core0_slice1_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core0_slice1_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core0_slice1_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core0_slice1_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core0_slice1_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_slice1_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_slice1_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_slice1_l2tlb_l2todr_snoop_ack )
);
`ifdef SC_4PIPE
PF_cache_stats_type core0_slice2_pf2_l2stats ;
wire core0_slice2_l2todr_req_valid ;
wire core0_slice2_l2todr_req_retry ;
I_l2todr_req_type core0_slice2_l2todr_req ;
wire core0_slice2_drtol2_snack_valid ;
wire core0_slice2_drtol2_snack_retry ;
I_drtol2_snack_type core0_slice2_drtol2_snack ;
wire core0_slice2_l2todr_disp_valid ;
wire core0_slice2_l2todr_disp_retry ;
I_l2todr_disp_type core0_slice2_l2todr_disp ;
wire core0_slice2_drtol2_dack_valid ;
wire core0_slice2_drtol2_dack_retry ;
I_drtol2_dack_type core0_slice2_drtol2_dack ;
wire core0_slice2_l2todr_snoop_ack_valid;
wire core0_slice2_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_slice2_l2todr_snoop_ack ;
PF_cache_stats_type core0_l2d_slice2_pf2_dcstats ;
wire core0_slice2_l2todr_pfreq_valid ;
wire core0_slice2_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core0_slice2_l2todr_pfreq ;
wire core0_slice2_l2tlbtol2_fwd_valid;
wire core0_slice2_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core0_slice2_l2tlbtol2_fwd ;
l2cache_pipe core0_l2d_slice2(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_slice2_l1tol2_req_valid )
,.l1tol2_req_retry (core0_slice2_l1tol2_req_retry )
,.l1tol2_req (core0_slice2_l1tol2_req )
,.l2tol1_snack_valid (core0_slice2_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_slice2_l2tol1_snack_retry )
,.l2tol1_snack (core0_slice2_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_slice2_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_slice2_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_slice2_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core0_slice2_l1tol2_disp_valid )
,.l1tol2_disp_retry (core0_slice2_l1tol2_disp_retry )
,.l1tol2_disp (core0_slice2_l1tol2_disp )
,.l2tol1_dack_valid (core0_slice2_l2tol1_dack_valid )
,.l2tol1_dack_retry (core0_slice2_l2tol1_dack_retry )
,.l2tol1_dack (core0_slice2_l2tol1_dack )
,.l2todr_pfreq_valid (core0_slice2_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core0_slice2_l2todr_pfreq_retry )
,.l2todr_pfreq (core0_slice2_l2todr_pfreq )
,.l2tlbtol2_fwd_valid(core0_slice2_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_slice2_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_slice2_l2tlbtol2_fwd )
,.l2todr_req_valid (core0_slice2_l2todr_req_valid )
,.l2todr_req_retry (core0_slice2_l2todr_req_retry )
,.l2todr_req (core0_slice2_l2todr_req )
,.drtol2_snack_valid (core0_slice2_drtol2_snack_valid )
,.drtol2_snack_retry (core0_slice2_drtol2_snack_retry )
,.drtol2_snack (core0_slice2_drtol2_snack )
,.l2todr_disp_valid (core0_slice2_l2todr_disp_valid )
,.l2todr_disp_retry (core0_slice2_l2todr_disp_retry )
,.l2todr_disp (core0_slice2_l2todr_disp )
,.drtol2_dack_valid (core0_slice2_drtol2_dack_valid )
,.drtol2_dack_retry (core0_slice2_drtol2_dack_retry )
,.drtol2_dack (core0_slice2_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_slice2_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_slice2_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_slice2_l2todr_snoop_ack )
,.cachetopf_stats (core0_slice2_pf2_l2stats )
);
wire core0_slice2_l2tlb_l2todr_req_valid ;
wire core0_slice2_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core0_slice2_l2tlb_l2todr_req ;
wire core0_slice2_l2tlb_drtol2_snack_valid ;
wire core0_slice2_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core0_slice2_l2tlb_drtol2_snack ;
wire core0_slice2_l2tlb_l2todr_disp_valid ;
wire core0_slice2_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core0_slice2_l2tlb_l2todr_disp ;
wire core0_slice2_l2tlb_drtol2_dack_valid ;
wire core0_slice2_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core0_slice2_l2tlb_drtol2_dack ;
wire core0_slice2_l2tlb_l2todr_snoop_ack_valid;
wire core0_slice2_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_slice2_l2tlb_l2todr_snoop_ack ;
l2tlb l2tlb_core0_slice2(
.clk(clk)
,.reset(reset)
,.l2tlbtol1tlb_snoop_valid(core0_slice2_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core0_slice2_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core0_slice2_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core0_slice2_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core0_slice2_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core0_slice2_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core0_slice2_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core0_slice2_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core0_slice2_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core0_slice2_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core0_slice2_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core0_slice2_l1tlbtol2tlb_sack )
,.l1tol2tlb_req_valid(core0_slice2_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_slice2_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_slice2_l1tol2tlb_req )
,.l2tlbtol2_fwd_valid(core0_slice2_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_slice2_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_slice2_l2tlbtol2_fwd )
,.l2todr_req_valid (core0_slice2_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core0_slice2_l2tlb_l2todr_req_retry )
,.l2todr_req (core0_slice2_l2tlb_l2todr_req )
,.drtol2_snack_valid (core0_slice2_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core0_slice2_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core0_slice2_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core0_slice2_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core0_slice2_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core0_slice2_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core0_slice2_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core0_slice2_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core0_slice2_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_slice2_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_slice2_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_slice2_l2tlb_l2todr_snoop_ack )
);
PF_cache_stats_type core0_slice3_pf3_l2stats ;
wire core0_slice3_l2todr_req_valid ;
wire core0_slice3_l2todr_req_retry ;
I_l2todr_req_type core0_slice3_l2todr_req ;
wire core0_slice3_drtol2_snack_valid ;
wire core0_slice3_drtol2_snack_retry ;
I_drtol2_snack_type core0_slice3_drtol2_snack ;
wire core0_slice3_l2todr_disp_valid ;
wire core0_slice3_l2todr_disp_retry ;
I_l2todr_disp_type core0_slice3_l2todr_disp ;
wire core0_slice3_drtol2_dack_valid ;
wire core0_slice3_drtol2_dack_retry ;
I_drtol2_dack_type core0_slice3_drtol2_dack ;
wire core0_slice3_l2todr_snoop_ack_valid;
wire core0_slice3_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_slice3_l2todr_snoop_ack ;
PF_cache_stats_type core0_l2d_slice3_pf3_dcstats ;
wire core0_slice3_l2todr_pfreq_valid ;
wire core0_slice3_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core0_slice3_l2todr_pfreq ;
wire core0_slice3_l2tlbtol2_fwd_valid;
wire core0_slice3_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core0_slice3_l2tlbtol2_fwd ;
l2cache_pipe core0_l2d_slice3(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_slice3_l1tol2_req_valid )
,.l1tol2_req_retry (core0_slice3_l1tol2_req_retry )
,.l1tol2_req (core0_slice3_l1tol2_req )
,.l2tol1_snack_valid (core0_slice3_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_slice3_l2tol1_snack_retry )
,.l2tol1_snack (core0_slice3_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_slice3_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_slice3_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_slice3_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core0_slice3_l1tol2_disp_valid )
,.l1tol2_disp_retry (core0_slice3_l1tol2_disp_retry )
,.l1tol2_disp (core0_slice3_l1tol2_disp )
,.l2tol1_dack_valid (core0_slice3_l2tol1_dack_valid )
,.l2tol1_dack_retry (core0_slice3_l2tol1_dack_retry )
,.l2tol1_dack (core0_slice3_l2tol1_dack )
,.l2todr_pfreq_valid (core0_slice3_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core0_slice3_l2todr_pfreq_retry )
,.l2todr_pfreq (core0_slice3_l2todr_pfreq )
,.l2tlbtol2_fwd_valid(core0_slice3_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_slice3_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_slice3_l2tlbtol2_fwd )
,.l2todr_req_valid (core0_slice3_l2todr_req_valid )
,.l2todr_req_retry (core0_slice3_l2todr_req_retry )
,.l2todr_req (core0_slice3_l2todr_req )
,.drtol2_snack_valid (core0_slice3_drtol2_snack_valid )
,.drtol2_snack_retry (core0_slice3_drtol2_snack_retry )
,.drtol2_snack (core0_slice3_drtol2_snack )
,.l2todr_disp_valid (core0_slice3_l2todr_disp_valid )
,.l2todr_disp_retry (core0_slice3_l2todr_disp_retry )
,.l2todr_disp (core0_slice3_l2todr_disp )
,.drtol2_dack_valid (core0_slice3_drtol2_dack_valid )
,.drtol2_dack_retry (core0_slice3_drtol2_dack_retry )
,.drtol2_dack (core0_slice3_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_slice3_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_slice3_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_slice3_l2todr_snoop_ack )
,.cachetopf_stats (core0_slice3_pf3_l2stats )
);
wire core0_slice3_l2tlb_l2todr_req_valid ;
wire core0_slice3_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core0_slice3_l2tlb_l2todr_req ;
wire core0_slice3_l2tlb_drtol2_snack_valid ;
wire core0_slice3_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core0_slice3_l2tlb_drtol2_snack ;
wire core0_slice3_l2tlb_l2todr_disp_valid ;
wire core0_slice3_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core0_slice3_l2tlb_l2todr_disp ;
wire core0_slice3_l2tlb_drtol2_dack_valid ;
wire core0_slice3_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core0_slice3_l2tlb_drtol2_dack ;
wire core0_slice3_l2tlb_l2todr_snoop_ack_valid;
wire core0_slice3_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_slice3_l2tlb_l2todr_snoop_ack ;
l2tlb l2tlb_core0_slice3(
.clk(clk)
,.reset(reset)
,.l2tlbtol1tlb_snoop_valid(core0_slice3_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core0_slice3_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core0_slice3_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core0_slice3_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core0_slice3_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core0_slice3_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core0_slice3_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core0_slice3_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core0_slice3_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core0_slice3_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core0_slice3_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core0_slice3_l1tlbtol2tlb_sack )
,.l1tol2tlb_req_valid(core0_slice3_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core0_slice3_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core0_slice3_l1tol2tlb_req )
,.l2tlbtol2_fwd_valid(core0_slice3_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_slice3_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_slice3_l2tlbtol2_fwd )
,.l2todr_req_valid (core0_slice3_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core0_slice3_l2tlb_l2todr_req_retry )
,.l2todr_req (core0_slice3_l2tlb_l2todr_req )
,.drtol2_snack_valid (core0_slice3_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core0_slice3_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core0_slice3_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core0_slice3_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core0_slice3_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core0_slice3_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core0_slice3_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core0_slice3_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core0_slice3_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_slice3_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_slice3_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_slice3_l2tlb_l2todr_snoop_ack )
);
`endif
PF_cache_stats_type core0_icache_pficache_l2stats ;
wire core0_icache_l2tlbtol2_fwd_valid;
wire core0_icache_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core0_icache_l2tlbtol2_fwd ;
wire core0_icache_l2todr_pfreq_valid ;
wire core0_icache_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core0_icache_l2todr_pfreq ;
wire unconnected_0_icache_l1tol2_disp_retry ;
wire unconnected_0_icache_l2tol1_dack_valid ;
I_l2tol1_dack_type unconnected_0_icache_l2tol1_dack ;
wire core0_icache_l2todr_req_valid ;
wire core0_icache_l2todr_req_retry ;
I_l2todr_req_type core0_icache_l2todr_req ;
wire core0_icache_drtol2_snack_valid ;
wire core0_icache_drtol2_snack_retry ;
I_drtol2_snack_type core0_icache_drtol2_snack ;
wire core0_icache_l2todr_disp_valid ;
wire core0_icache_l2todr_disp_retry ;
I_l2todr_disp_type core0_icache_l2todr_disp ;
wire core0_icache_drtol2_dack_valid ;
wire core0_icache_drtol2_dack_retry ;
I_drtol2_dack_type core0_icache_drtol2_dack ;
wire core0_icache_l2todr_snoop_ack_valid;
wire core0_icache_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_icache_l2todr_snoop_ack ;
l2cache_pipe core0_l2icache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core0_l1tol2_req_valid )
,.l1tol2_req_retry (core0_l1tol2_req_retry )
,.l1tol2_req (core0_l1tol2_req )
,.l2tol1_snack_valid (core0_l2tol1_snack_valid )
,.l2tol1_snack_retry (core0_l2tol1_snack_retry )
,.l2tol1_snack (core0_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core0_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core0_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core0_l1tol2_snoop_ack )
,.l1tol2_disp_valid(1'b0)
,.l1tol2_disp ({$bits(I_l1tol2_disp_type) {1'b0}})
,.l2tol1_dack_retry(1'b0)
,.l2todr_req_valid (core0_icache_l2todr_req_valid )
,.l2todr_req_retry (core0_icache_l2todr_req_retry )
,.l2todr_req (core0_icache_l2todr_req )
,.drtol2_snack_valid (core0_icache_drtol2_snack_valid )
,.drtol2_snack_retry (core0_icache_drtol2_snack_retry )
,.drtol2_snack (core0_icache_drtol2_snack )
,.l2todr_disp_valid (core0_icache_l2todr_disp_valid )
,.l2todr_disp_retry (core0_icache_l2todr_disp_retry )
,.l2todr_disp (core0_icache_l2todr_disp )
,.drtol2_dack_valid (core0_icache_drtol2_dack_valid )
,.drtol2_dack_retry (core0_icache_drtol2_dack_retry )
,.drtol2_dack (core0_icache_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_icache_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_icache_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_icache_l2todr_snoop_ack )
,.l2tlbtol2_fwd_valid(core0_icache_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core0_icache_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core0_icache_l2tlbtol2_fwd )
,.l2todr_pfreq_valid (core0_icache_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core0_icache_l2todr_pfreq_retry )
,.l2todr_pfreq (core0_icache_l2todr_pfreq )
,.cachetopf_stats (core0_icache_pficache_l2stats )
,.l1tol2_disp_retry (unconnected_0_icache_l1tol2_disp_retry )
,.l2tol1_dack_valid (unconnected_0_icache_l2tol1_dack_valid )
,.l2tol1_dack (unconnected_0_icache_l2tol1_dack )
);
wire core0_l2todr_req_valid ;
wire core0_l2todr_req_retry ;
I_l2todr_req_type core0_l2todr_req ;
wire core0_drtol2_snack_valid ;
wire core0_drtol2_snack_retry ;
I_drtol2_snack_type core0_drtol2_snack ;
wire core0_l2todr_disp_valid ;
wire core0_l2todr_disp_retry ;
I_l2todr_disp_type core0_l2todr_disp ;
wire core0_drtol2_dack_valid ;
wire core0_drtol2_dack_retry ;
I_drtol2_dack_type core0_drtol2_dack ;
wire core0_l2todr_snoop_ack_valid;
wire core0_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_l2todr_snoop_ack ;
wire core0_l2todr_pfreq_valid ;
wire core0_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core0_l2todr_pfreq ;
arbl2 l2arbiter_core0(
.clk(clk)
,.reset(reset)
,.l2d_0todr_req_valid (core0_slice0_l2todr_req_valid )
,.l2d_0todr_req_retry (core0_slice0_l2todr_req_retry )
,.l2d_0todr_req (core0_slice0_l2todr_req )
,.drtol2d_0_snack_valid (core0_slice0_drtol2_snack_valid )
,.drtol2d_0_snack_retry (core0_slice0_drtol2_snack_retry )
,.drtol2d_0_snack (core0_slice0_drtol2_snack )
,.l2d_0todr_disp_valid (core0_slice0_l2todr_disp_valid )
,.l2d_0todr_disp_retry (core0_slice0_l2todr_disp_retry )
,.l2d_0todr_disp (core0_slice0_l2todr_disp )
,.drtol2d_0_dack_valid (core0_slice0_drtol2_dack_valid )
,.drtol2d_0_dack_retry (core0_slice0_drtol2_dack_retry )
,.drtol2d_0_dack (core0_slice0_drtol2_dack )
,.l2d_0todr_snoop_ack_valid(core0_slice0_l2todr_snoop_ack_valid)
,.l2d_0todr_snoop_ack_retry(core0_slice0_l2todr_snoop_ack_retry)
,.l2d_0todr_snoop_ack (core0_slice0_l2todr_snoop_ack )
,.l2d_0todr_pfreq_valid (core0_slice0_l2todr_pfreq_valid )
,.l2d_0todr_pfreq_retry (core0_slice0_l2todr_pfreq_retry )
,.l2d_0todr_pfreq (core0_slice0_l2todr_pfreq )
,.l2d_1todr_req_valid (core0_slice1_l2todr_req_valid )
,.l2d_1todr_req_retry (core0_slice1_l2todr_req_retry )
,.l2d_1todr_req (core0_slice1_l2todr_req )
,.drtol2d_1_snack_valid (core0_slice1_drtol2_snack_valid )
,.drtol2d_1_snack_retry (core0_slice1_drtol2_snack_retry )
,.drtol2d_1_snack (core0_slice1_drtol2_snack )
,.l2d_1todr_disp_valid (core0_slice1_l2todr_disp_valid )
,.l2d_1todr_disp_retry (core0_slice1_l2todr_disp_retry )
,.l2d_1todr_disp (core0_slice1_l2todr_disp )
,.drtol2d_1_dack_valid (core0_slice1_drtol2_dack_valid )
,.drtol2d_1_dack_retry (core0_slice1_drtol2_dack_retry )
,.drtol2d_1_dack (core0_slice1_drtol2_dack )
,.l2d_1todr_snoop_ack_valid(core0_slice1_l2todr_snoop_ack_valid)
,.l2d_1todr_snoop_ack_retry(core0_slice1_l2todr_snoop_ack_retry)
,.l2d_1todr_snoop_ack (core0_slice1_l2todr_snoop_ack )
,.l2d_1todr_pfreq_valid (core0_slice1_l2todr_pfreq_valid )
,.l2d_1todr_pfreq_retry (core0_slice1_l2todr_pfreq_retry )
,.l2d_1todr_pfreq (core0_slice1_l2todr_pfreq )
`ifdef SC_4PIPE
,.l2d_2todr_req_valid (core0_slice2_l2todr_req_valid )
,.l2d_2todr_req_retry (core0_slice2_l2todr_req_retry )
,.l2d_2todr_req (core0_slice2_l2todr_req )
,.drtol2d_2_snack_valid (core0_slice2_drtol2_snack_valid )
,.drtol2d_2_snack_retry (core0_slice2_drtol2_snack_retry )
,.drtol2d_2_snack (core0_slice2_drtol2_snack )
,.l2d_2todr_disp_valid (core0_slice2_l2todr_disp_valid )
,.l2d_2todr_disp_retry (core0_slice2_l2todr_disp_retry )
,.l2d_2todr_disp (core0_slice2_l2todr_disp )
,.drtol2d_2_dack_valid (core0_slice2_drtol2_dack_valid )
,.drtol2d_2_dack_retry (core0_slice2_drtol2_dack_retry )
,.drtol2d_2_dack (core0_slice2_drtol2_dack )
,.l2d_2todr_snoop_ack_valid(core0_slice2_l2todr_snoop_ack_valid)
,.l2d_2todr_snoop_ack_retry(core0_slice2_l2todr_snoop_ack_retry)
,.l2d_2todr_snoop_ack (core0_slice2_l2todr_snoop_ack )
,.l2d_2todr_pfreq_valid (core0_slice2_l2todr_pfreq_valid )
,.l2d_2todr_pfreq_retry (core0_slice2_l2todr_pfreq_retry )
,.l2d_2todr_pfreq (core0_slice2_l2todr_pfreq )
,.l2d_3todr_req_valid (core0_slice3_l2todr_req_valid )
,.l2d_3todr_req_retry (core0_slice3_l2todr_req_retry )
,.l2d_3todr_req (core0_slice3_l2todr_req )
,.drtol2d_3_snack_valid (core0_slice3_drtol2_snack_valid )
,.drtol2d_3_snack_retry (core0_slice3_drtol2_snack_retry )
,.drtol2d_3_snack (core0_slice3_drtol2_snack )
,.l2d_3todr_disp_valid (core0_slice3_l2todr_disp_valid )
,.l2d_3todr_disp_retry (core0_slice3_l2todr_disp_retry )
,.l2d_3todr_disp (core0_slice3_l2todr_disp )
,.drtol2d_3_dack_valid (core0_slice3_drtol2_dack_valid )
,.drtol2d_3_dack_retry (core0_slice3_drtol2_dack_retry )
,.drtol2d_3_dack (core0_slice3_drtol2_dack )
,.l2d_3todr_snoop_ack_valid(core0_slice3_l2todr_snoop_ack_valid)
,.l2d_3todr_snoop_ack_retry(core0_slice3_l2todr_snoop_ack_retry)
,.l2d_3todr_snoop_ack (core0_slice3_l2todr_snoop_ack )
,.l2d_3todr_pfreq_valid (core0_slice3_l2todr_pfreq_valid )
,.l2d_3todr_pfreq_retry (core0_slice3_l2todr_pfreq_retry )
,.l2d_3todr_pfreq (core0_slice3_l2todr_pfreq )
`endif
,.l2todr_req_valid (core0_l2todr_req_valid )
,.l2todr_req_retry (core0_l2todr_req_retry )
,.l2todr_req (core0_l2todr_req )
,.drtol2_snack_valid (core0_drtol2_snack_valid )
,.drtol2_snack_retry (core0_drtol2_snack_retry )
,.drtol2_snack (core0_drtol2_snack )
,.l2todr_disp_valid (core0_l2todr_disp_valid )
,.l2todr_disp_retry (core0_l2todr_disp_retry )
,.l2todr_disp (core0_l2todr_disp )
,.drtol2_dack_valid (core0_drtol2_dack_valid )
,.drtol2_dack_retry (core0_drtol2_dack_retry )
,.drtol2_dack (core0_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_l2todr_snoop_ack )
,.l2todr_pfreq_valid (core0_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core0_l2todr_pfreq_retry )
,.l2todr_pfreq (core0_l2todr_pfreq )
);
wire core0_l2tlb_l2todr_req_valid ;
wire core0_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core0_l2tlb_l2todr_req ;
wire core0_l2tlb_drtol2_snack_valid ;
wire core0_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core0_l2tlb_drtol2_snack ;
wire core0_l2tlb_l2todr_disp_valid ;
wire core0_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core0_l2tlb_l2todr_disp ;
wire core0_l2tlb_drtol2_dack_valid ;
wire core0_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core0_l2tlb_drtol2_dack ;
wire core0_l2tlb_l2todr_snoop_ack_valid;
wire core0_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core0_l2tlb_l2todr_snoop_ack ;
arbl2tlb l2tlbarbiter_core0(
.clk(clk)
,.reset(reset)
,.l2d_0todr_req_valid (core0_slice0_l2tlb_l2todr_req_valid )
,.l2d_0todr_req_retry (core0_slice0_l2tlb_l2todr_req_retry )
,.l2d_0todr_req (core0_slice0_l2tlb_l2todr_req )
,.drtol2d_0_snack_valid (core0_slice0_l2tlb_drtol2_snack_valid )
,.drtol2d_0_snack_retry (core0_slice0_l2tlb_drtol2_snack_retry )
,.drtol2d_0_snack (core0_slice0_l2tlb_drtol2_snack )
,.l2d_0todr_disp_valid (core0_slice0_l2tlb_l2todr_disp_valid )
,.l2d_0todr_disp_retry (core0_slice0_l2tlb_l2todr_disp_retry )
,.l2d_0todr_disp (core0_slice0_l2tlb_l2todr_disp )
,.drtol2d_0_dack_valid (core0_slice0_l2tlb_drtol2_dack_valid )
,.drtol2d_0_dack_retry (core0_slice0_l2tlb_drtol2_dack_retry )
,.drtol2d_0_dack (core0_slice0_l2tlb_drtol2_dack )
,.l2d_0todr_snoop_ack_valid(core0_slice0_l2tlb_l2todr_snoop_ack_valid)
,.l2d_0todr_snoop_ack_retry(core0_slice0_l2tlb_l2todr_snoop_ack_retry)
,.l2d_0todr_snoop_ack (core0_slice0_l2tlb_l2todr_snoop_ack )
,.l2d_1todr_req_valid (core0_slice1_l2tlb_l2todr_req_valid )
,.l2d_1todr_req_retry (core0_slice1_l2tlb_l2todr_req_retry )
,.l2d_1todr_req (core0_slice1_l2tlb_l2todr_req )
,.drtol2d_1_snack_valid (core0_slice1_l2tlb_drtol2_snack_valid )
,.drtol2d_1_snack_retry (core0_slice1_l2tlb_drtol2_snack_retry )
,.drtol2d_1_snack (core0_slice1_l2tlb_drtol2_snack )
,.l2d_1todr_disp_valid (core0_slice1_l2tlb_l2todr_disp_valid )
,.l2d_1todr_disp_retry (core0_slice1_l2tlb_l2todr_disp_retry )
,.l2d_1todr_disp (core0_slice1_l2tlb_l2todr_disp )
,.drtol2d_1_dack_valid (core0_slice1_l2tlb_drtol2_dack_valid )
,.drtol2d_1_dack_retry (core0_slice1_l2tlb_drtol2_dack_retry )
,.drtol2d_1_dack (core0_slice1_l2tlb_drtol2_dack )
,.l2d_1todr_snoop_ack_valid(core0_slice1_l2tlb_l2todr_snoop_ack_valid)
,.l2d_1todr_snoop_ack_retry(core0_slice1_l2tlb_l2todr_snoop_ack_retry)
,.l2d_1todr_snoop_ack (core0_slice1_l2tlb_l2todr_snoop_ack )
`ifdef SC_4PIPE
,.l2d_2todr_req_valid (core0_slice2_l2tlb_l2todr_req_valid )
,.l2d_2todr_req_retry (core0_slice2_l2tlb_l2todr_req_retry )
,.l2d_2todr_req (core0_slice2_l2tlb_l2todr_req )
,.drtol2d_2_snack_valid (core0_slice2_l2tlb_drtol2_snack_valid )
,.drtol2d_2_snack_retry (core0_slice2_l2tlb_drtol2_snack_retry )
,.drtol2d_2_snack (core0_slice2_l2tlb_drtol2_snack )
,.l2d_2todr_disp_valid (core0_slice2_l2tlb_l2todr_disp_valid )
,.l2d_2todr_disp_retry (core0_slice2_l2tlb_l2todr_disp_retry )
,.l2d_2todr_disp (core0_slice2_l2tlb_l2todr_disp )
,.drtol2d_2_dack_valid (core0_slice2_l2tlb_drtol2_dack_valid )
,.drtol2d_2_dack_retry (core0_slice2_l2tlb_drtol2_dack_retry )
,.drtol2d_2_dack (core0_slice2_l2tlb_drtol2_dack )
,.l2d_2todr_snoop_ack_valid(core0_slice2_l2tlb_l2todr_snoop_ack_valid)
,.l2d_2todr_snoop_ack_retry(core0_slice2_l2tlb_l2todr_snoop_ack_retry)
,.l2d_2todr_snoop_ack (core0_slice2_l2tlb_l2todr_snoop_ack )
,.l2d_3todr_req_valid (core0_slice3_l2tlb_l2todr_req_valid )
,.l2d_3todr_req_retry (core0_slice3_l2tlb_l2todr_req_retry )
,.l2d_3todr_req (core0_slice3_l2tlb_l2todr_req )
,.drtol2d_3_snack_valid (core0_slice3_l2tlb_drtol2_snack_valid )
,.drtol2d_3_snack_retry (core0_slice3_l2tlb_drtol2_snack_retry )
,.drtol2d_3_snack (core0_slice3_l2tlb_drtol2_snack )
,.l2d_3todr_disp_valid (core0_slice3_l2tlb_l2todr_disp_valid )
,.l2d_3todr_disp_retry (core0_slice3_l2tlb_l2todr_disp_retry )
,.l2d_3todr_disp (core0_slice3_l2tlb_l2todr_disp )
,.drtol2d_3_dack_valid (core0_slice3_l2tlb_drtol2_dack_valid )
,.drtol2d_3_dack_retry (core0_slice3_l2tlb_drtol2_dack_retry )
,.drtol2d_3_dack (core0_slice3_l2tlb_drtol2_dack )
,.l2d_3todr_snoop_ack_valid(core0_slice3_l2tlb_l2todr_snoop_ack_valid)
,.l2d_3todr_snoop_ack_retry(core0_slice3_l2tlb_l2todr_snoop_ack_retry)
,.l2d_3todr_snoop_ack (core0_slice3_l2tlb_l2todr_snoop_ack )
`endif
,.l2todr_req_valid (core0_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core0_l2tlb_l2todr_req_retry )
,.l2todr_req (core0_l2tlb_l2todr_req )
,.drtol2_snack_valid (core0_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core0_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core0_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core0_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core0_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core0_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core0_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core0_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core0_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core0_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core0_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core0_l2tlb_l2todr_snoop_ack )
);
PF_cache_stats_type unconnected_pfe0_pf_dcstats ;
PF_cache_stats_type unconnected_pfe0_pf_l2stats ;
pfengine core0_pfe(
.clk(clk)
,.reset(reset)
,.pfgtopfe_op_valid(core0_pfgtopfe_op_valid)
,.pfgtopfe_op_retry(core0_pfgtopfe_op_retry)
,.pfgtopfe_op (core0_pfgtopfe_op )
,.pf0_l2stats (core0_slice0_pf0_l2stats )
,.pftodc_req0_valid(core0_slice0_pftodc_req0_valid)
,.pftodc_req0_retry(core0_slice0_pftodc_req0_retry)
,.pftodc_req0 (core0_slice0_pftodc_req0 )
,.pf0_dcstats (core0_slice0_pf0_dcstats )
,.pf1_l2stats (core0_slice1_pf1_l2stats )
,.pftodc_req1_valid(core0_slice1_pftodc_req1_valid)
,.pftodc_req1_retry(core0_slice1_pftodc_req1_retry)
,.pftodc_req1 (core0_slice1_pftodc_req1 )
,.pf1_dcstats (core0_slice1_pf1_dcstats )
`ifdef SC_4PIPE
,.pf2_l2stats (core0_slice2_pf2_l2stats )
,.pftodc_req2_valid(core0_slice2_pftodc_req2_valid)
,.pftodc_req2_retry(core0_slice2_pftodc_req2_retry)
,.pftodc_req2 (core0_slice2_pftodc_req2 )
,.pf2_dcstats (core0_slice2_pf2_dcstats )
,.pf3_l2stats (core0_slice3_pf3_l2stats )
,.pftodc_req3_valid(core0_slice3_pftodc_req3_valid)
,.pftodc_req3_retry(core0_slice3_pftodc_req3_retry)
,.pftodc_req3 (core0_slice3_pftodc_req3 )
,.pf3_dcstats (core0_slice3_pf3_dcstats )
`endif
,.pf_dcstats (unconnected_pfe0_pf_dcstats )
,.pf_l2stats (unconnected_pfe0_pf_l2stats )
);
wire core1_slice0_l1tol2_req_valid ;
wire core1_slice0_l1tol2_req_retry ;
I_l1tol2_req_type core1_slice0_l1tol2_req ;
wire core1_slice0_l2tol1_snack_valid ;
wire core1_slice0_l2tol1_snack_retry ;
I_l2tol1_snack_type core1_slice0_l2tol1_snack ;
wire core1_slice0_l1tol2_snoop_ack_valid;
wire core1_slice0_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core1_slice0_l1tol2_snoop_ack ;
wire core1_slice0_l1tol2_disp_valid ;
wire core1_slice0_l1tol2_disp_retry ;
I_l1tol2_disp_type core1_slice0_l1tol2_disp ;
wire core1_slice0_l2tol1_dack_valid ;
wire core1_slice0_l2tol1_dack_retry ;
I_l2tol1_dack_type core1_slice0_l2tol1_dack ;
PF_cache_stats_type core1_slice0_pf0_dcstats ;
wire core1_slice0_l1tol2tlb_req_valid;
wire core1_slice0_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core1_slice0_l1tol2tlb_req ;
dcache_pipe core1_slice0_dcache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_slice0_l1tol2_req_valid )
,.l1tol2_req_retry (core1_slice0_l1tol2_req_retry )
,.l1tol2_req (core1_slice0_l1tol2_req )
,.l2tol1_snack_valid (core1_slice0_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_slice0_l2tol1_snack_retry )
,.l2tol1_snack (core1_slice0_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_slice0_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_slice0_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_slice0_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core1_slice0_l1tol2_disp_valid )
,.l1tol2_disp_retry (core1_slice0_l1tol2_disp_retry )
,.l1tol2_disp (core1_slice0_l1tol2_disp )
,.l2tol1_dack_valid (core1_slice0_l2tol1_dack_valid )
,.l2tol1_dack_retry (core1_slice0_l2tol1_dack_retry )
,.l2tol1_dack (core1_slice0_l2tol1_dack )
,.l1tol2tlb_req_valid(core1_slice0_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_slice0_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_slice0_l1tol2tlb_req )
,.coretodc_ld_valid (core1_slice0_coretodc_ld_valid )
,.coretodc_ld_retry (core1_slice0_coretodc_ld_retry )
,.coretodc_ld (core1_slice0_coretodc_ld )
,.dctocore_ld_valid (core1_slice0_dctocore_ld_valid )
,.dctocore_ld_retry (core1_slice0_dctocore_ld_retry )
,.dctocore_ld (core1_slice0_dctocore_ld )
,.coretodc_std_valid (core1_slice0_coretodc_std_valid )
,.coretodc_std_retry (core1_slice0_coretodc_std_retry )
,.coretodc_std (core1_slice0_coretodc_std )
,.dctocore_std_ack_valid(core1_slice0_dctocore_std_ack_valid)
,.dctocore_std_ack_retry(core1_slice0_dctocore_std_ack_retry)
,.dctocore_std_ack (core1_slice0_dctocore_std_ack )
,.cachetopf_stats (core1_slice0_pf0_dcstats )
,.l1tlbtol1_fwd0_valid(core1_slice0_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core1_slice0_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core1_slice0_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core1_slice0_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core1_slice0_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core1_slice0_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core1_slice0_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core1_slice0_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core1_slice0_l1tlbtol1_cmd )
);
wire core1_slice0_l1tlbtol1_fwd0_valid;
wire core1_slice0_l1tlbtol1_fwd0_retry;
I_l1tlbtol1_fwd_type core1_slice0_l1tlbtol1_fwd0 ;
wire core1_slice0_l1tlbtol1_fwd1_valid;
wire core1_slice0_l1tlbtol1_fwd1_retry;
I_l1tlbtol1_fwd_type core1_slice0_l1tlbtol1_fwd1 ;
wire core1_slice0_l1tlbtol1_cmd_valid ;
wire core1_slice0_l1tlbtol1_cmd_retry ;
I_l1tlbtol1_cmd_type core1_slice0_l1tlbtol1_cmd ;
wire core1_slice0_l2tlbtol1tlb_snoop_valid;
wire core1_slice0_l2tlbtol1tlb_snoop_retry;
I_l2tlbtol1tlb_snoop_type core1_slice0_l2tlbtol1tlb_snoop ;
wire core1_slice0_l2tlbtol1tlb_ack_valid ;
wire core1_slice0_l2tlbtol1tlb_ack_retry ;
I_l2tlbtol1tlb_ack_type core1_slice0_l2tlbtol1tlb_ack ;
wire core1_slice0_l1tlbtol2tlb_req_valid ;
wire core1_slice0_l1tlbtol2tlb_req_retry ;
I_l1tlbtol2tlb_req_type core1_slice0_l1tlbtol2tlb_req ;
wire core1_slice0_l1tlbtol2tlb_sack_valid ;
wire core1_slice0_l1tlbtol2tlb_sack_retry ;
I_l1tlbtol2tlb_sack_type core1_slice0_l1tlbtol2tlb_sack ;
wire core1_slice0_pftodc_req0_valid;
wire core1_slice0_pftodc_req0_retry;
I_pfetol1tlb_req_type core1_slice0_pftodc_req0 ;
dctlb dcltb_c1s0(
.clk(clk)
,.reset(reset)
,.coretodctlb_ld_valid(c1_s0_coretodctlb_ld_valid)
,.coretodctlb_ld_retry(c1_s0_coretodctlb_ld_retry)
,.coretodctlb_ld (c1_s0_coretodctlb_ld )
,.coretodctlb_st_valid(c1_s0_coretodctlb_st_valid)
,.coretodctlb_st_retry(c1_s0_coretodctlb_st_retry)
,.coretodctlb_st (c1_s0_coretodctlb_st )
,.pfetol1tlb_req_valid (core1_slice0_pftodc_req0_valid)
,.pfetol1tlb_req_retry (core1_slice0_pftodc_req0_retry)
,.pfetol1tlb_req (core1_slice0_pftodc_req0 )
,.l1tlbtol1_fwd0_valid(core1_slice0_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core1_slice0_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core1_slice0_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core1_slice0_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core1_slice0_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core1_slice0_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core1_slice0_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core1_slice0_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core1_slice0_l1tlbtol1_cmd )
,.l2tlbtol1tlb_snoop_valid(core1_slice0_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core1_slice0_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core1_slice0_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core1_slice0_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core1_slice0_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core1_slice0_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core1_slice0_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core1_slice0_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core1_slice0_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core1_slice0_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core1_slice0_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core1_slice0_l1tlbtol2tlb_sack )
);
wire core1_slice1_l1tol2_req_valid ;
wire core1_slice1_l1tol2_req_retry ;
I_l1tol2_req_type core1_slice1_l1tol2_req ;
wire core1_slice1_l2tol1_snack_valid ;
wire core1_slice1_l2tol1_snack_retry ;
I_l2tol1_snack_type core1_slice1_l2tol1_snack ;
wire core1_slice1_l1tol2_snoop_ack_valid;
wire core1_slice1_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core1_slice1_l1tol2_snoop_ack ;
wire core1_slice1_l1tol2_disp_valid ;
wire core1_slice1_l1tol2_disp_retry ;
I_l1tol2_disp_type core1_slice1_l1tol2_disp ;
wire core1_slice1_l2tol1_dack_valid ;
wire core1_slice1_l2tol1_dack_retry ;
I_l2tol1_dack_type core1_slice1_l2tol1_dack ;
PF_cache_stats_type core1_slice1_pf1_dcstats ;
wire core1_slice1_l1tol2tlb_req_valid;
wire core1_slice1_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core1_slice1_l1tol2tlb_req ;
dcache_pipe core1_slice1_dcache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_slice1_l1tol2_req_valid )
,.l1tol2_req_retry (core1_slice1_l1tol2_req_retry )
,.l1tol2_req (core1_slice1_l1tol2_req )
,.l2tol1_snack_valid (core1_slice1_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_slice1_l2tol1_snack_retry )
,.l2tol1_snack (core1_slice1_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_slice1_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_slice1_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_slice1_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core1_slice1_l1tol2_disp_valid )
,.l1tol2_disp_retry (core1_slice1_l1tol2_disp_retry )
,.l1tol2_disp (core1_slice1_l1tol2_disp )
,.l2tol1_dack_valid (core1_slice1_l2tol1_dack_valid )
,.l2tol1_dack_retry (core1_slice1_l2tol1_dack_retry )
,.l2tol1_dack (core1_slice1_l2tol1_dack )
,.l1tol2tlb_req_valid(core1_slice1_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_slice1_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_slice1_l1tol2tlb_req )
,.coretodc_ld_valid (core1_slice1_coretodc_ld_valid )
,.coretodc_ld_retry (core1_slice1_coretodc_ld_retry )
,.coretodc_ld (core1_slice1_coretodc_ld )
,.dctocore_ld_valid (core1_slice1_dctocore_ld_valid )
,.dctocore_ld_retry (core1_slice1_dctocore_ld_retry )
,.dctocore_ld (core1_slice1_dctocore_ld )
,.coretodc_std_valid (core1_slice1_coretodc_std_valid )
,.coretodc_std_retry (core1_slice1_coretodc_std_retry )
,.coretodc_std (core1_slice1_coretodc_std )
,.dctocore_std_ack_valid(core1_slice1_dctocore_std_ack_valid)
,.dctocore_std_ack_retry(core1_slice1_dctocore_std_ack_retry)
,.dctocore_std_ack (core1_slice1_dctocore_std_ack )
,.cachetopf_stats (core1_slice1_pf1_dcstats )
,.l1tlbtol1_fwd0_valid(core1_slice1_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core1_slice1_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core1_slice1_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core1_slice1_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core1_slice1_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core1_slice1_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core1_slice1_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core1_slice1_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core1_slice1_l1tlbtol1_cmd )
);
wire core1_slice1_l1tlbtol1_fwd0_valid;
wire core1_slice1_l1tlbtol1_fwd0_retry;
I_l1tlbtol1_fwd_type core1_slice1_l1tlbtol1_fwd0 ;
wire core1_slice1_l1tlbtol1_fwd1_valid;
wire core1_slice1_l1tlbtol1_fwd1_retry;
I_l1tlbtol1_fwd_type core1_slice1_l1tlbtol1_fwd1 ;
wire core1_slice1_l1tlbtol1_cmd_valid ;
wire core1_slice1_l1tlbtol1_cmd_retry ;
I_l1tlbtol1_cmd_type core1_slice1_l1tlbtol1_cmd ;
wire core1_slice1_l2tlbtol1tlb_snoop_valid;
wire core1_slice1_l2tlbtol1tlb_snoop_retry;
I_l2tlbtol1tlb_snoop_type core1_slice1_l2tlbtol1tlb_snoop ;
wire core1_slice1_l2tlbtol1tlb_ack_valid ;
wire core1_slice1_l2tlbtol1tlb_ack_retry ;
I_l2tlbtol1tlb_ack_type core1_slice1_l2tlbtol1tlb_ack ;
wire core1_slice1_l1tlbtol2tlb_req_valid ;
wire core1_slice1_l1tlbtol2tlb_req_retry ;
I_l1tlbtol2tlb_req_type core1_slice1_l1tlbtol2tlb_req ;
wire core1_slice1_l1tlbtol2tlb_sack_valid ;
wire core1_slice1_l1tlbtol2tlb_sack_retry ;
I_l1tlbtol2tlb_sack_type core1_slice1_l1tlbtol2tlb_sack ;
wire core1_slice1_pftodc_req1_valid;
wire core1_slice1_pftodc_req1_retry;
I_pfetol1tlb_req_type core1_slice1_pftodc_req1 ;
dctlb dcltb_c1s1(
.clk(clk)
,.reset(reset)
,.coretodctlb_ld_valid(c1_s1_coretodctlb_ld_valid)
,.coretodctlb_ld_retry(c1_s1_coretodctlb_ld_retry)
,.coretodctlb_ld (c1_s1_coretodctlb_ld )
,.coretodctlb_st_valid(c1_s1_coretodctlb_st_valid)
,.coretodctlb_st_retry(c1_s1_coretodctlb_st_retry)
,.coretodctlb_st (c1_s1_coretodctlb_st )
,.pfetol1tlb_req_valid (core1_slice1_pftodc_req1_valid)
,.pfetol1tlb_req_retry (core1_slice1_pftodc_req1_retry)
,.pfetol1tlb_req (core1_slice1_pftodc_req1 )
,.l1tlbtol1_fwd0_valid(core1_slice1_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core1_slice1_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core1_slice1_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core1_slice1_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core1_slice1_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core1_slice1_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core1_slice1_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core1_slice1_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core1_slice1_l1tlbtol1_cmd )
,.l2tlbtol1tlb_snoop_valid(core1_slice1_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core1_slice1_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core1_slice1_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core1_slice1_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core1_slice1_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core1_slice1_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core1_slice1_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core1_slice1_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core1_slice1_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core1_slice1_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core1_slice1_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core1_slice1_l1tlbtol2tlb_sack )
);
`ifdef SC_4PIPE
wire core1_slice2_l1tol2_req_valid ;
wire core1_slice2_l1tol2_req_retry ;
I_l1tol2_req_type core1_slice2_l1tol2_req ;
wire core1_slice2_l2tol1_snack_valid ;
wire core1_slice2_l2tol1_snack_retry ;
I_l2tol1_snack_type core1_slice2_l2tol1_snack ;
wire core1_slice2_l1tol2_snoop_ack_valid;
wire core1_slice2_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core1_slice2_l1tol2_snoop_ack ;
wire core1_slice2_l1tol2_disp_valid ;
wire core1_slice2_l1tol2_disp_retry ;
I_l1tol2_disp_type core1_slice2_l1tol2_disp ;
wire core1_slice2_l2tol1_dack_valid ;
wire core1_slice2_l2tol1_dack_retry ;
I_l2tol1_dack_type core1_slice2_l2tol1_dack ;
PF_cache_stats_type core1_slice2_pf2_dcstats ;
wire core1_slice2_l1tol2tlb_req_valid;
wire core1_slice2_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core1_slice2_l1tol2tlb_req ;
dcache_pipe core1_slice2_dcache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_slice2_l1tol2_req_valid )
,.l1tol2_req_retry (core1_slice2_l1tol2_req_retry )
,.l1tol2_req (core1_slice2_l1tol2_req )
,.l2tol1_snack_valid (core1_slice2_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_slice2_l2tol1_snack_retry )
,.l2tol1_snack (core1_slice2_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_slice2_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_slice2_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_slice2_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core1_slice2_l1tol2_disp_valid )
,.l1tol2_disp_retry (core1_slice2_l1tol2_disp_retry )
,.l1tol2_disp (core1_slice2_l1tol2_disp )
,.l2tol1_dack_valid (core1_slice2_l2tol1_dack_valid )
,.l2tol1_dack_retry (core1_slice2_l2tol1_dack_retry )
,.l2tol1_dack (core1_slice2_l2tol1_dack )
,.l1tol2tlb_req_valid(core1_slice2_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_slice2_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_slice2_l1tol2tlb_req )
,.coretodc_ld_valid (core1_slice2_coretodc_ld_valid )
,.coretodc_ld_retry (core1_slice2_coretodc_ld_retry )
,.coretodc_ld (core1_slice2_coretodc_ld )
,.dctocore_ld_valid (core1_slice2_dctocore_ld_valid )
,.dctocore_ld_retry (core1_slice2_dctocore_ld_retry )
,.dctocore_ld (core1_slice2_dctocore_ld )
,.coretodc_std_valid (core1_slice2_coretodc_std_valid )
,.coretodc_std_retry (core1_slice2_coretodc_std_retry )
,.coretodc_std (core1_slice2_coretodc_std )
,.dctocore_std_ack_valid(core1_slice2_dctocore_std_ack_valid)
,.dctocore_std_ack_retry(core1_slice2_dctocore_std_ack_retry)
,.dctocore_std_ack (core1_slice2_dctocore_std_ack )
,.cachetopf_stats (core1_slice2_pf2_dcstats )
,.l1tlbtol1_fwd0_valid(core1_slice2_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core1_slice2_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core1_slice2_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core1_slice2_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core1_slice2_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core1_slice2_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core1_slice2_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core1_slice2_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core1_slice2_l1tlbtol1_cmd )
);
wire core1_slice2_l1tlbtol1_fwd0_valid;
wire core1_slice2_l1tlbtol1_fwd0_retry;
I_l1tlbtol1_fwd_type core1_slice2_l1tlbtol1_fwd0 ;
wire core1_slice2_l1tlbtol1_fwd1_valid;
wire core1_slice2_l1tlbtol1_fwd1_retry;
I_l1tlbtol1_fwd_type core1_slice2_l1tlbtol1_fwd1 ;
wire core1_slice2_l1tlbtol1_cmd_valid ;
wire core1_slice2_l1tlbtol1_cmd_retry ;
I_l1tlbtol1_cmd_type core1_slice2_l1tlbtol1_cmd ;
wire core1_slice2_l2tlbtol1tlb_snoop_valid;
wire core1_slice2_l2tlbtol1tlb_snoop_retry;
I_l2tlbtol1tlb_snoop_type core1_slice2_l2tlbtol1tlb_snoop ;
wire core1_slice2_l2tlbtol1tlb_ack_valid ;
wire core1_slice2_l2tlbtol1tlb_ack_retry ;
I_l2tlbtol1tlb_ack_type core1_slice2_l2tlbtol1tlb_ack ;
wire core1_slice2_l1tlbtol2tlb_req_valid ;
wire core1_slice2_l1tlbtol2tlb_req_retry ;
I_l1tlbtol2tlb_req_type core1_slice2_l1tlbtol2tlb_req ;
wire core1_slice2_l1tlbtol2tlb_sack_valid ;
wire core1_slice2_l1tlbtol2tlb_sack_retry ;
I_l1tlbtol2tlb_sack_type core1_slice2_l1tlbtol2tlb_sack ;
wire core1_slice2_pftodc_req2_valid;
wire core1_slice2_pftodc_req2_retry;
I_pfetol1tlb_req_type core1_slice2_pftodc_req2 ;
dctlb dcltb_c1s2(
.clk(clk)
,.reset(reset)
,.coretodctlb_ld_valid(c1_s2_coretodctlb_ld_valid)
,.coretodctlb_ld_retry(c1_s2_coretodctlb_ld_retry)
,.coretodctlb_ld (c1_s2_coretodctlb_ld )
,.coretodctlb_st_valid(c1_s2_coretodctlb_st_valid)
,.coretodctlb_st_retry(c1_s2_coretodctlb_st_retry)
,.coretodctlb_st (c1_s2_coretodctlb_st )
,.pfetol1tlb_req_valid (core1_slice2_pftodc_req2_valid)
,.pfetol1tlb_req_retry (core1_slice2_pftodc_req2_retry)
,.pfetol1tlb_req (core1_slice2_pftodc_req2 )
,.l1tlbtol1_fwd0_valid(core1_slice2_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core1_slice2_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core1_slice2_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core1_slice2_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core1_slice2_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core1_slice2_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core1_slice2_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core1_slice2_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core1_slice2_l1tlbtol1_cmd )
,.l2tlbtol1tlb_snoop_valid(core1_slice2_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core1_slice2_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core1_slice2_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core1_slice2_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core1_slice2_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core1_slice2_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core1_slice2_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core1_slice2_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core1_slice2_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core1_slice2_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core1_slice2_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core1_slice2_l1tlbtol2tlb_sack )
);
wire core1_slice3_l1tol2_req_valid ;
wire core1_slice3_l1tol2_req_retry ;
I_l1tol2_req_type core1_slice3_l1tol2_req ;
wire core1_slice3_l2tol1_snack_valid ;
wire core1_slice3_l2tol1_snack_retry ;
I_l2tol1_snack_type core1_slice3_l2tol1_snack ;
wire core1_slice3_l1tol2_snoop_ack_valid;
wire core1_slice3_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core1_slice3_l1tol2_snoop_ack ;
wire core1_slice3_l1tol2_disp_valid ;
wire core1_slice3_l1tol2_disp_retry ;
I_l1tol2_disp_type core1_slice3_l1tol2_disp ;
wire core1_slice3_l2tol1_dack_valid ;
wire core1_slice3_l2tol1_dack_retry ;
I_l2tol1_dack_type core1_slice3_l2tol1_dack ;
PF_cache_stats_type core1_slice3_pf3_dcstats ;
wire core1_slice3_l1tol2tlb_req_valid;
wire core1_slice3_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core1_slice3_l1tol2tlb_req ;
dcache_pipe core1_slice3_dcache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_slice3_l1tol2_req_valid )
,.l1tol2_req_retry (core1_slice3_l1tol2_req_retry )
,.l1tol2_req (core1_slice3_l1tol2_req )
,.l2tol1_snack_valid (core1_slice3_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_slice3_l2tol1_snack_retry )
,.l2tol1_snack (core1_slice3_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_slice3_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_slice3_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_slice3_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core1_slice3_l1tol2_disp_valid )
,.l1tol2_disp_retry (core1_slice3_l1tol2_disp_retry )
,.l1tol2_disp (core1_slice3_l1tol2_disp )
,.l2tol1_dack_valid (core1_slice3_l2tol1_dack_valid )
,.l2tol1_dack_retry (core1_slice3_l2tol1_dack_retry )
,.l2tol1_dack (core1_slice3_l2tol1_dack )
,.l1tol2tlb_req_valid(core1_slice3_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_slice3_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_slice3_l1tol2tlb_req )
,.coretodc_ld_valid (core1_slice3_coretodc_ld_valid )
,.coretodc_ld_retry (core1_slice3_coretodc_ld_retry )
,.coretodc_ld (core1_slice3_coretodc_ld )
,.dctocore_ld_valid (core1_slice3_dctocore_ld_valid )
,.dctocore_ld_retry (core1_slice3_dctocore_ld_retry )
,.dctocore_ld (core1_slice3_dctocore_ld )
,.coretodc_std_valid (core1_slice3_coretodc_std_valid )
,.coretodc_std_retry (core1_slice3_coretodc_std_retry )
,.coretodc_std (core1_slice3_coretodc_std )
,.dctocore_std_ack_valid(core1_slice3_dctocore_std_ack_valid)
,.dctocore_std_ack_retry(core1_slice3_dctocore_std_ack_retry)
,.dctocore_std_ack (core1_slice3_dctocore_std_ack )
,.cachetopf_stats (core1_slice3_pf3_dcstats )
,.l1tlbtol1_fwd0_valid(core1_slice3_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core1_slice3_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core1_slice3_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core1_slice3_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core1_slice3_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core1_slice3_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core1_slice3_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core1_slice3_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core1_slice3_l1tlbtol1_cmd )
);
wire core1_slice3_l1tlbtol1_fwd0_valid;
wire core1_slice3_l1tlbtol1_fwd0_retry;
I_l1tlbtol1_fwd_type core1_slice3_l1tlbtol1_fwd0 ;
wire core1_slice3_l1tlbtol1_fwd1_valid;
wire core1_slice3_l1tlbtol1_fwd1_retry;
I_l1tlbtol1_fwd_type core1_slice3_l1tlbtol1_fwd1 ;
wire core1_slice3_l1tlbtol1_cmd_valid ;
wire core1_slice3_l1tlbtol1_cmd_retry ;
I_l1tlbtol1_cmd_type core1_slice3_l1tlbtol1_cmd ;
wire core1_slice3_l2tlbtol1tlb_snoop_valid;
wire core1_slice3_l2tlbtol1tlb_snoop_retry;
I_l2tlbtol1tlb_snoop_type core1_slice3_l2tlbtol1tlb_snoop ;
wire core1_slice3_l2tlbtol1tlb_ack_valid ;
wire core1_slice3_l2tlbtol1tlb_ack_retry ;
I_l2tlbtol1tlb_ack_type core1_slice3_l2tlbtol1tlb_ack ;
wire core1_slice3_l1tlbtol2tlb_req_valid ;
wire core1_slice3_l1tlbtol2tlb_req_retry ;
I_l1tlbtol2tlb_req_type core1_slice3_l1tlbtol2tlb_req ;
wire core1_slice3_l1tlbtol2tlb_sack_valid ;
wire core1_slice3_l1tlbtol2tlb_sack_retry ;
I_l1tlbtol2tlb_sack_type core1_slice3_l1tlbtol2tlb_sack ;
wire core1_slice3_pftodc_req3_valid;
wire core1_slice3_pftodc_req3_retry;
I_pfetol1tlb_req_type core1_slice3_pftodc_req3 ;
dctlb dcltb_c1s3(
.clk(clk)
,.reset(reset)
,.coretodctlb_ld_valid(c1_s3_coretodctlb_ld_valid)
,.coretodctlb_ld_retry(c1_s3_coretodctlb_ld_retry)
,.coretodctlb_ld (c1_s3_coretodctlb_ld )
,.coretodctlb_st_valid(c1_s3_coretodctlb_st_valid)
,.coretodctlb_st_retry(c1_s3_coretodctlb_st_retry)
,.coretodctlb_st (c1_s3_coretodctlb_st )
,.pfetol1tlb_req_valid (core1_slice3_pftodc_req3_valid)
,.pfetol1tlb_req_retry (core1_slice3_pftodc_req3_retry)
,.pfetol1tlb_req (core1_slice3_pftodc_req3 )
,.l1tlbtol1_fwd0_valid(core1_slice3_l1tlbtol1_fwd0_valid)
,.l1tlbtol1_fwd0_retry(core1_slice3_l1tlbtol1_fwd0_retry)
,.l1tlbtol1_fwd0 (core1_slice3_l1tlbtol1_fwd0 )
,.l1tlbtol1_fwd1_valid(core1_slice3_l1tlbtol1_fwd1_valid)
,.l1tlbtol1_fwd1_retry(core1_slice3_l1tlbtol1_fwd1_retry)
,.l1tlbtol1_fwd1 (core1_slice3_l1tlbtol1_fwd1 )
,.l1tlbtol1_cmd_valid (core1_slice3_l1tlbtol1_cmd_valid )
,.l1tlbtol1_cmd_retry (core1_slice3_l1tlbtol1_cmd_retry )
,.l1tlbtol1_cmd (core1_slice3_l1tlbtol1_cmd )
,.l2tlbtol1tlb_snoop_valid(core1_slice3_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core1_slice3_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core1_slice3_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core1_slice3_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core1_slice3_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core1_slice3_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core1_slice3_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core1_slice3_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core1_slice3_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core1_slice3_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core1_slice3_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core1_slice3_l1tlbtol2tlb_sack )
);
`endif
wire core1_l1tol2_req_valid ;
wire core1_l1tol2_req_retry ;
I_l1tol2_req_type core1_l1tol2_req ;
wire core1_l2tol1_snack_valid ;
wire core1_l2tol1_snack_retry ;
I_l2tol1_snack_type core1_l2tol1_snack ;
wire core1_l1tol2_snoop_ack_valid;
wire core1_l1tol2_snoop_ack_retry;
I_l2snoop_ack_type core1_l1tol2_snoop_ack ;
wire core1_l1tlbtol1_fwd_valid;
wire core1_l1tlbtol1_fwd_retry;
I_l1tlbtol1_fwd_type core1_l1tlbtol1_fwd ;
wire core1_l1tlbtol1_cmd_valid;
wire core1_l1tlbtol1_cmd_retry;
I_l1tlbtol1_cmd_type core1_l1tlbtol1_cmd ;
wire core1_l1tol2tlb_req_valid;
wire core1_l1tol2tlb_req_retry;
I_l1tol2tlb_req_type core1_l1tol2tlb_req ;
PF_cache_stats_type core1_cachetopf_stats;
icache core1_icache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_l1tol2_req_valid )
,.l1tol2_req_retry (core1_l1tol2_req_retry )
,.l1tol2_req (core1_l1tol2_req )
,.l2tol1_snack_valid (core1_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_l2tol1_snack_retry )
,.l2tol1_snack (core1_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_l1tol2_snoop_ack )
,.l1tlbtol1_fwd_valid(core1_l1tlbtol1_fwd_valid)
,.l1tlbtol1_fwd_retry(core1_l1tlbtol1_fwd_retry)
,.l1tlbtol1_fwd (core1_l1tlbtol1_fwd )
,.l1tlbtol1_cmd_valid(core1_l1tlbtol1_cmd_valid)
,.l1tlbtol1_cmd_retry(core1_l1tlbtol1_cmd_retry)
,.l1tlbtol1_cmd (core1_l1tlbtol1_cmd )
,.l1tol2tlb_req_valid(core1_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_l1tol2tlb_req )
,.cachetopf_stats(core1_cachetopf_stats)
,.coretoic_pc_valid (core1_coretoic_pc_valid )
,.coretoic_pc_retry (core1_coretoic_pc_retry )
,.coretoic_pc (core1_coretoic_pc )
,.ictocore_valid (core1_ictocore_valid )
,.ictocore_retry (core1_ictocore_retry )
,.ictocore (core1_ictocore )
);
PF_cache_stats_type core1_slice0_pf0_l2stats ;
wire core1_slice0_l2todr_req_valid ;
wire core1_slice0_l2todr_req_retry ;
I_l2todr_req_type core1_slice0_l2todr_req ;
wire core1_slice0_drtol2_snack_valid ;
wire core1_slice0_drtol2_snack_retry ;
I_drtol2_snack_type core1_slice0_drtol2_snack ;
wire core1_slice0_l2todr_disp_valid ;
wire core1_slice0_l2todr_disp_retry ;
I_l2todr_disp_type core1_slice0_l2todr_disp ;
wire core1_slice0_drtol2_dack_valid ;
wire core1_slice0_drtol2_dack_retry ;
I_drtol2_dack_type core1_slice0_drtol2_dack ;
wire core1_slice0_l2todr_snoop_ack_valid;
wire core1_slice0_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_slice0_l2todr_snoop_ack ;
PF_cache_stats_type core1_l2d_slice0_pf0_dcstats ;
wire core1_slice0_l2todr_pfreq_valid ;
wire core1_slice0_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core1_slice0_l2todr_pfreq ;
wire core1_slice0_l2tlbtol2_fwd_valid;
wire core1_slice0_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core1_slice0_l2tlbtol2_fwd ;
l2cache_pipe core1_l2d_slice0(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_slice0_l1tol2_req_valid )
,.l1tol2_req_retry (core1_slice0_l1tol2_req_retry )
,.l1tol2_req (core1_slice0_l1tol2_req )
,.l2tol1_snack_valid (core1_slice0_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_slice0_l2tol1_snack_retry )
,.l2tol1_snack (core1_slice0_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_slice0_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_slice0_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_slice0_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core1_slice0_l1tol2_disp_valid )
,.l1tol2_disp_retry (core1_slice0_l1tol2_disp_retry )
,.l1tol2_disp (core1_slice0_l1tol2_disp )
,.l2tol1_dack_valid (core1_slice0_l2tol1_dack_valid )
,.l2tol1_dack_retry (core1_slice0_l2tol1_dack_retry )
,.l2tol1_dack (core1_slice0_l2tol1_dack )
,.l2todr_pfreq_valid (core1_slice0_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core1_slice0_l2todr_pfreq_retry )
,.l2todr_pfreq (core1_slice0_l2todr_pfreq )
,.l2tlbtol2_fwd_valid(core1_slice0_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_slice0_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_slice0_l2tlbtol2_fwd )
,.l2todr_req_valid (core1_slice0_l2todr_req_valid )
,.l2todr_req_retry (core1_slice0_l2todr_req_retry )
,.l2todr_req (core1_slice0_l2todr_req )
,.drtol2_snack_valid (core1_slice0_drtol2_snack_valid )
,.drtol2_snack_retry (core1_slice0_drtol2_snack_retry )
,.drtol2_snack (core1_slice0_drtol2_snack )
,.l2todr_disp_valid (core1_slice0_l2todr_disp_valid )
,.l2todr_disp_retry (core1_slice0_l2todr_disp_retry )
,.l2todr_disp (core1_slice0_l2todr_disp )
,.drtol2_dack_valid (core1_slice0_drtol2_dack_valid )
,.drtol2_dack_retry (core1_slice0_drtol2_dack_retry )
,.drtol2_dack (core1_slice0_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_slice0_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_slice0_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_slice0_l2todr_snoop_ack )
,.cachetopf_stats (core1_slice0_pf0_l2stats )
);
wire core1_slice0_l2tlb_l2todr_req_valid ;
wire core1_slice0_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core1_slice0_l2tlb_l2todr_req ;
wire core1_slice0_l2tlb_drtol2_snack_valid ;
wire core1_slice0_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core1_slice0_l2tlb_drtol2_snack ;
wire core1_slice0_l2tlb_l2todr_disp_valid ;
wire core1_slice0_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core1_slice0_l2tlb_l2todr_disp ;
wire core1_slice0_l2tlb_drtol2_dack_valid ;
wire core1_slice0_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core1_slice0_l2tlb_drtol2_dack ;
wire core1_slice0_l2tlb_l2todr_snoop_ack_valid;
wire core1_slice0_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_slice0_l2tlb_l2todr_snoop_ack ;
l2tlb l2tlb_core1_slice0(
.clk(clk)
,.reset(reset)
,.l2tlbtol1tlb_snoop_valid(core1_slice0_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core1_slice0_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core1_slice0_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core1_slice0_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core1_slice0_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core1_slice0_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core1_slice0_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core1_slice0_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core1_slice0_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core1_slice0_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core1_slice0_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core1_slice0_l1tlbtol2tlb_sack )
,.l1tol2tlb_req_valid(core1_slice0_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_slice0_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_slice0_l1tol2tlb_req )
,.l2tlbtol2_fwd_valid(core1_slice0_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_slice0_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_slice0_l2tlbtol2_fwd )
,.l2todr_req_valid (core1_slice0_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core1_slice0_l2tlb_l2todr_req_retry )
,.l2todr_req (core1_slice0_l2tlb_l2todr_req )
,.drtol2_snack_valid (core1_slice0_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core1_slice0_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core1_slice0_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core1_slice0_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core1_slice0_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core1_slice0_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core1_slice0_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core1_slice0_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core1_slice0_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_slice0_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_slice0_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_slice0_l2tlb_l2todr_snoop_ack )
);
PF_cache_stats_type core1_slice1_pf1_l2stats ;
wire core1_slice1_l2todr_req_valid ;
wire core1_slice1_l2todr_req_retry ;
I_l2todr_req_type core1_slice1_l2todr_req ;
wire core1_slice1_drtol2_snack_valid ;
wire core1_slice1_drtol2_snack_retry ;
I_drtol2_snack_type core1_slice1_drtol2_snack ;
wire core1_slice1_l2todr_disp_valid ;
wire core1_slice1_l2todr_disp_retry ;
I_l2todr_disp_type core1_slice1_l2todr_disp ;
wire core1_slice1_drtol2_dack_valid ;
wire core1_slice1_drtol2_dack_retry ;
I_drtol2_dack_type core1_slice1_drtol2_dack ;
wire core1_slice1_l2todr_snoop_ack_valid;
wire core1_slice1_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_slice1_l2todr_snoop_ack ;
PF_cache_stats_type core1_l2d_slice1_pf1_dcstats ;
wire core1_slice1_l2todr_pfreq_valid ;
wire core1_slice1_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core1_slice1_l2todr_pfreq ;
wire core1_slice1_l2tlbtol2_fwd_valid;
wire core1_slice1_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core1_slice1_l2tlbtol2_fwd ;
l2cache_pipe core1_l2d_slice1(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_slice1_l1tol2_req_valid )
,.l1tol2_req_retry (core1_slice1_l1tol2_req_retry )
,.l1tol2_req (core1_slice1_l1tol2_req )
,.l2tol1_snack_valid (core1_slice1_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_slice1_l2tol1_snack_retry )
,.l2tol1_snack (core1_slice1_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_slice1_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_slice1_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_slice1_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core1_slice1_l1tol2_disp_valid )
,.l1tol2_disp_retry (core1_slice1_l1tol2_disp_retry )
,.l1tol2_disp (core1_slice1_l1tol2_disp )
,.l2tol1_dack_valid (core1_slice1_l2tol1_dack_valid )
,.l2tol1_dack_retry (core1_slice1_l2tol1_dack_retry )
,.l2tol1_dack (core1_slice1_l2tol1_dack )
,.l2todr_pfreq_valid (core1_slice1_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core1_slice1_l2todr_pfreq_retry )
,.l2todr_pfreq (core1_slice1_l2todr_pfreq )
,.l2tlbtol2_fwd_valid(core1_slice1_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_slice1_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_slice1_l2tlbtol2_fwd )
,.l2todr_req_valid (core1_slice1_l2todr_req_valid )
,.l2todr_req_retry (core1_slice1_l2todr_req_retry )
,.l2todr_req (core1_slice1_l2todr_req )
,.drtol2_snack_valid (core1_slice1_drtol2_snack_valid )
,.drtol2_snack_retry (core1_slice1_drtol2_snack_retry )
,.drtol2_snack (core1_slice1_drtol2_snack )
,.l2todr_disp_valid (core1_slice1_l2todr_disp_valid )
,.l2todr_disp_retry (core1_slice1_l2todr_disp_retry )
,.l2todr_disp (core1_slice1_l2todr_disp )
,.drtol2_dack_valid (core1_slice1_drtol2_dack_valid )
,.drtol2_dack_retry (core1_slice1_drtol2_dack_retry )
,.drtol2_dack (core1_slice1_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_slice1_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_slice1_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_slice1_l2todr_snoop_ack )
,.cachetopf_stats (core1_slice1_pf1_l2stats )
);
wire core1_slice1_l2tlb_l2todr_req_valid ;
wire core1_slice1_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core1_slice1_l2tlb_l2todr_req ;
wire core1_slice1_l2tlb_drtol2_snack_valid ;
wire core1_slice1_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core1_slice1_l2tlb_drtol2_snack ;
wire core1_slice1_l2tlb_l2todr_disp_valid ;
wire core1_slice1_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core1_slice1_l2tlb_l2todr_disp ;
wire core1_slice1_l2tlb_drtol2_dack_valid ;
wire core1_slice1_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core1_slice1_l2tlb_drtol2_dack ;
wire core1_slice1_l2tlb_l2todr_snoop_ack_valid;
wire core1_slice1_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_slice1_l2tlb_l2todr_snoop_ack ;
l2tlb l2tlb_core1_slice1(
.clk(clk)
,.reset(reset)
,.l2tlbtol1tlb_snoop_valid(core1_slice1_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core1_slice1_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core1_slice1_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core1_slice1_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core1_slice1_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core1_slice1_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core1_slice1_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core1_slice1_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core1_slice1_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core1_slice1_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core1_slice1_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core1_slice1_l1tlbtol2tlb_sack )
,.l1tol2tlb_req_valid(core1_slice1_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_slice1_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_slice1_l1tol2tlb_req )
,.l2tlbtol2_fwd_valid(core1_slice1_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_slice1_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_slice1_l2tlbtol2_fwd )
,.l2todr_req_valid (core1_slice1_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core1_slice1_l2tlb_l2todr_req_retry )
,.l2todr_req (core1_slice1_l2tlb_l2todr_req )
,.drtol2_snack_valid (core1_slice1_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core1_slice1_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core1_slice1_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core1_slice1_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core1_slice1_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core1_slice1_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core1_slice1_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core1_slice1_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core1_slice1_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_slice1_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_slice1_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_slice1_l2tlb_l2todr_snoop_ack )
);
`ifdef SC_4PIPE
PF_cache_stats_type core1_slice2_pf2_l2stats ;
wire core1_slice2_l2todr_req_valid ;
wire core1_slice2_l2todr_req_retry ;
I_l2todr_req_type core1_slice2_l2todr_req ;
wire core1_slice2_drtol2_snack_valid ;
wire core1_slice2_drtol2_snack_retry ;
I_drtol2_snack_type core1_slice2_drtol2_snack ;
wire core1_slice2_l2todr_disp_valid ;
wire core1_slice2_l2todr_disp_retry ;
I_l2todr_disp_type core1_slice2_l2todr_disp ;
wire core1_slice2_drtol2_dack_valid ;
wire core1_slice2_drtol2_dack_retry ;
I_drtol2_dack_type core1_slice2_drtol2_dack ;
wire core1_slice2_l2todr_snoop_ack_valid;
wire core1_slice2_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_slice2_l2todr_snoop_ack ;
PF_cache_stats_type core1_l2d_slice2_pf2_dcstats ;
wire core1_slice2_l2todr_pfreq_valid ;
wire core1_slice2_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core1_slice2_l2todr_pfreq ;
wire core1_slice2_l2tlbtol2_fwd_valid;
wire core1_slice2_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core1_slice2_l2tlbtol2_fwd ;
l2cache_pipe core1_l2d_slice2(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_slice2_l1tol2_req_valid )
,.l1tol2_req_retry (core1_slice2_l1tol2_req_retry )
,.l1tol2_req (core1_slice2_l1tol2_req )
,.l2tol1_snack_valid (core1_slice2_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_slice2_l2tol1_snack_retry )
,.l2tol1_snack (core1_slice2_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_slice2_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_slice2_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_slice2_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core1_slice2_l1tol2_disp_valid )
,.l1tol2_disp_retry (core1_slice2_l1tol2_disp_retry )
,.l1tol2_disp (core1_slice2_l1tol2_disp )
,.l2tol1_dack_valid (core1_slice2_l2tol1_dack_valid )
,.l2tol1_dack_retry (core1_slice2_l2tol1_dack_retry )
,.l2tol1_dack (core1_slice2_l2tol1_dack )
,.l2todr_pfreq_valid (core1_slice2_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core1_slice2_l2todr_pfreq_retry )
,.l2todr_pfreq (core1_slice2_l2todr_pfreq )
,.l2tlbtol2_fwd_valid(core1_slice2_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_slice2_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_slice2_l2tlbtol2_fwd )
,.l2todr_req_valid (core1_slice2_l2todr_req_valid )
,.l2todr_req_retry (core1_slice2_l2todr_req_retry )
,.l2todr_req (core1_slice2_l2todr_req )
,.drtol2_snack_valid (core1_slice2_drtol2_snack_valid )
,.drtol2_snack_retry (core1_slice2_drtol2_snack_retry )
,.drtol2_snack (core1_slice2_drtol2_snack )
,.l2todr_disp_valid (core1_slice2_l2todr_disp_valid )
,.l2todr_disp_retry (core1_slice2_l2todr_disp_retry )
,.l2todr_disp (core1_slice2_l2todr_disp )
,.drtol2_dack_valid (core1_slice2_drtol2_dack_valid )
,.drtol2_dack_retry (core1_slice2_drtol2_dack_retry )
,.drtol2_dack (core1_slice2_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_slice2_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_slice2_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_slice2_l2todr_snoop_ack )
,.cachetopf_stats (core1_slice2_pf2_l2stats )
);
wire core1_slice2_l2tlb_l2todr_req_valid ;
wire core1_slice2_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core1_slice2_l2tlb_l2todr_req ;
wire core1_slice2_l2tlb_drtol2_snack_valid ;
wire core1_slice2_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core1_slice2_l2tlb_drtol2_snack ;
wire core1_slice2_l2tlb_l2todr_disp_valid ;
wire core1_slice2_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core1_slice2_l2tlb_l2todr_disp ;
wire core1_slice2_l2tlb_drtol2_dack_valid ;
wire core1_slice2_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core1_slice2_l2tlb_drtol2_dack ;
wire core1_slice2_l2tlb_l2todr_snoop_ack_valid;
wire core1_slice2_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_slice2_l2tlb_l2todr_snoop_ack ;
l2tlb l2tlb_core1_slice2(
.clk(clk)
,.reset(reset)
,.l2tlbtol1tlb_snoop_valid(core1_slice2_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core1_slice2_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core1_slice2_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core1_slice2_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core1_slice2_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core1_slice2_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core1_slice2_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core1_slice2_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core1_slice2_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core1_slice2_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core1_slice2_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core1_slice2_l1tlbtol2tlb_sack )
,.l1tol2tlb_req_valid(core1_slice2_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_slice2_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_slice2_l1tol2tlb_req )
,.l2tlbtol2_fwd_valid(core1_slice2_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_slice2_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_slice2_l2tlbtol2_fwd )
,.l2todr_req_valid (core1_slice2_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core1_slice2_l2tlb_l2todr_req_retry )
,.l2todr_req (core1_slice2_l2tlb_l2todr_req )
,.drtol2_snack_valid (core1_slice2_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core1_slice2_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core1_slice2_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core1_slice2_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core1_slice2_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core1_slice2_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core1_slice2_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core1_slice2_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core1_slice2_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_slice2_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_slice2_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_slice2_l2tlb_l2todr_snoop_ack )
);
PF_cache_stats_type core1_slice3_pf3_l2stats ;
wire core1_slice3_l2todr_req_valid ;
wire core1_slice3_l2todr_req_retry ;
I_l2todr_req_type core1_slice3_l2todr_req ;
wire core1_slice3_drtol2_snack_valid ;
wire core1_slice3_drtol2_snack_retry ;
I_drtol2_snack_type core1_slice3_drtol2_snack ;
wire core1_slice3_l2todr_disp_valid ;
wire core1_slice3_l2todr_disp_retry ;
I_l2todr_disp_type core1_slice3_l2todr_disp ;
wire core1_slice3_drtol2_dack_valid ;
wire core1_slice3_drtol2_dack_retry ;
I_drtol2_dack_type core1_slice3_drtol2_dack ;
wire core1_slice3_l2todr_snoop_ack_valid;
wire core1_slice3_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_slice3_l2todr_snoop_ack ;
PF_cache_stats_type core1_l2d_slice3_pf3_dcstats ;
wire core1_slice3_l2todr_pfreq_valid ;
wire core1_slice3_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core1_slice3_l2todr_pfreq ;
wire core1_slice3_l2tlbtol2_fwd_valid;
wire core1_slice3_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core1_slice3_l2tlbtol2_fwd ;
l2cache_pipe core1_l2d_slice3(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_slice3_l1tol2_req_valid )
,.l1tol2_req_retry (core1_slice3_l1tol2_req_retry )
,.l1tol2_req (core1_slice3_l1tol2_req )
,.l2tol1_snack_valid (core1_slice3_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_slice3_l2tol1_snack_retry )
,.l2tol1_snack (core1_slice3_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_slice3_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_slice3_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_slice3_l1tol2_snoop_ack )
,.l1tol2_disp_valid (core1_slice3_l1tol2_disp_valid )
,.l1tol2_disp_retry (core1_slice3_l1tol2_disp_retry )
,.l1tol2_disp (core1_slice3_l1tol2_disp )
,.l2tol1_dack_valid (core1_slice3_l2tol1_dack_valid )
,.l2tol1_dack_retry (core1_slice3_l2tol1_dack_retry )
,.l2tol1_dack (core1_slice3_l2tol1_dack )
,.l2todr_pfreq_valid (core1_slice3_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core1_slice3_l2todr_pfreq_retry )
,.l2todr_pfreq (core1_slice3_l2todr_pfreq )
,.l2tlbtol2_fwd_valid(core1_slice3_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_slice3_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_slice3_l2tlbtol2_fwd )
,.l2todr_req_valid (core1_slice3_l2todr_req_valid )
,.l2todr_req_retry (core1_slice3_l2todr_req_retry )
,.l2todr_req (core1_slice3_l2todr_req )
,.drtol2_snack_valid (core1_slice3_drtol2_snack_valid )
,.drtol2_snack_retry (core1_slice3_drtol2_snack_retry )
,.drtol2_snack (core1_slice3_drtol2_snack )
,.l2todr_disp_valid (core1_slice3_l2todr_disp_valid )
,.l2todr_disp_retry (core1_slice3_l2todr_disp_retry )
,.l2todr_disp (core1_slice3_l2todr_disp )
,.drtol2_dack_valid (core1_slice3_drtol2_dack_valid )
,.drtol2_dack_retry (core1_slice3_drtol2_dack_retry )
,.drtol2_dack (core1_slice3_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_slice3_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_slice3_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_slice3_l2todr_snoop_ack )
,.cachetopf_stats (core1_slice3_pf3_l2stats )
);
wire core1_slice3_l2tlb_l2todr_req_valid ;
wire core1_slice3_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core1_slice3_l2tlb_l2todr_req ;
wire core1_slice3_l2tlb_drtol2_snack_valid ;
wire core1_slice3_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core1_slice3_l2tlb_drtol2_snack ;
wire core1_slice3_l2tlb_l2todr_disp_valid ;
wire core1_slice3_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core1_slice3_l2tlb_l2todr_disp ;
wire core1_slice3_l2tlb_drtol2_dack_valid ;
wire core1_slice3_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core1_slice3_l2tlb_drtol2_dack ;
wire core1_slice3_l2tlb_l2todr_snoop_ack_valid;
wire core1_slice3_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_slice3_l2tlb_l2todr_snoop_ack ;
l2tlb l2tlb_core1_slice3(
.clk(clk)
,.reset(reset)
,.l2tlbtol1tlb_snoop_valid(core1_slice3_l2tlbtol1tlb_snoop_valid)
,.l2tlbtol1tlb_snoop_retry(core1_slice3_l2tlbtol1tlb_snoop_retry)
,.l2tlbtol1tlb_snoop (core1_slice3_l2tlbtol1tlb_snoop )
,.l2tlbtol1tlb_ack_valid (core1_slice3_l2tlbtol1tlb_ack_valid )
,.l2tlbtol1tlb_ack_retry (core1_slice3_l2tlbtol1tlb_ack_retry )
,.l2tlbtol1tlb_ack (core1_slice3_l2tlbtol1tlb_ack )
,.l1tlbtol2tlb_req_valid (core1_slice3_l1tlbtol2tlb_req_valid )
,.l1tlbtol2tlb_req_retry (core1_slice3_l1tlbtol2tlb_req_retry )
,.l1tlbtol2tlb_req (core1_slice3_l1tlbtol2tlb_req )
,.l1tlbtol2tlb_sack_valid (core1_slice3_l1tlbtol2tlb_sack_valid )
,.l1tlbtol2tlb_sack_retry (core1_slice3_l1tlbtol2tlb_sack_retry )
,.l1tlbtol2tlb_sack (core1_slice3_l1tlbtol2tlb_sack )
,.l1tol2tlb_req_valid(core1_slice3_l1tol2tlb_req_valid)
,.l1tol2tlb_req_retry(core1_slice3_l1tol2tlb_req_retry)
,.l1tol2tlb_req (core1_slice3_l1tol2tlb_req )
,.l2tlbtol2_fwd_valid(core1_slice3_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_slice3_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_slice3_l2tlbtol2_fwd )
,.l2todr_req_valid (core1_slice3_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core1_slice3_l2tlb_l2todr_req_retry )
,.l2todr_req (core1_slice3_l2tlb_l2todr_req )
,.drtol2_snack_valid (core1_slice3_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core1_slice3_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core1_slice3_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core1_slice3_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core1_slice3_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core1_slice3_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core1_slice3_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core1_slice3_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core1_slice3_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_slice3_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_slice3_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_slice3_l2tlb_l2todr_snoop_ack )
);
`endif
PF_cache_stats_type core1_icache_pficache_l2stats ;
wire core1_icache_l2tlbtol2_fwd_valid;
wire core1_icache_l2tlbtol2_fwd_retry;
I_l2tlbtol2_fwd_type core1_icache_l2tlbtol2_fwd ;
wire core1_icache_l2todr_pfreq_valid ;
wire core1_icache_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core1_icache_l2todr_pfreq ;
wire unconnected_1_icache_l1tol2_disp_retry ;
wire unconnected_1_icache_l2tol1_dack_valid ;
I_l2tol1_dack_type unconnected_1_icache_l2tol1_dack ;
wire core1_icache_l2todr_req_valid ;
wire core1_icache_l2todr_req_retry ;
I_l2todr_req_type core1_icache_l2todr_req ;
wire core1_icache_drtol2_snack_valid ;
wire core1_icache_drtol2_snack_retry ;
I_drtol2_snack_type core1_icache_drtol2_snack ;
wire core1_icache_l2todr_disp_valid ;
wire core1_icache_l2todr_disp_retry ;
I_l2todr_disp_type core1_icache_l2todr_disp ;
wire core1_icache_drtol2_dack_valid ;
wire core1_icache_drtol2_dack_retry ;
I_drtol2_dack_type core1_icache_drtol2_dack ;
wire core1_icache_l2todr_snoop_ack_valid;
wire core1_icache_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_icache_l2todr_snoop_ack ;
l2cache_pipe core1_l2icache(
.clk(clk)
,.reset(reset)
,.l1tol2_req_valid (core1_l1tol2_req_valid )
,.l1tol2_req_retry (core1_l1tol2_req_retry )
,.l1tol2_req (core1_l1tol2_req )
,.l2tol1_snack_valid (core1_l2tol1_snack_valid )
,.l2tol1_snack_retry (core1_l2tol1_snack_retry )
,.l2tol1_snack (core1_l2tol1_snack )
,.l1tol2_snoop_ack_valid(core1_l1tol2_snoop_ack_valid)
,.l1tol2_snoop_ack_retry(core1_l1tol2_snoop_ack_retry)
,.l1tol2_snoop_ack (core1_l1tol2_snoop_ack )
,.l1tol2_disp_valid(1'b0)
,.l1tol2_disp ({$bits(I_l1tol2_disp_type) {1'b0}})
,.l2tol1_dack_retry(1'b0)
,.l2todr_req_valid (core1_icache_l2todr_req_valid )
,.l2todr_req_retry (core1_icache_l2todr_req_retry )
,.l2todr_req (core1_icache_l2todr_req )
,.drtol2_snack_valid (core1_icache_drtol2_snack_valid )
,.drtol2_snack_retry (core1_icache_drtol2_snack_retry )
,.drtol2_snack (core1_icache_drtol2_snack )
,.l2todr_disp_valid (core1_icache_l2todr_disp_valid )
,.l2todr_disp_retry (core1_icache_l2todr_disp_retry )
,.l2todr_disp (core1_icache_l2todr_disp )
,.drtol2_dack_valid (core1_icache_drtol2_dack_valid )
,.drtol2_dack_retry (core1_icache_drtol2_dack_retry )
,.drtol2_dack (core1_icache_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_icache_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_icache_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_icache_l2todr_snoop_ack )
,.l2tlbtol2_fwd_valid(core1_icache_l2tlbtol2_fwd_valid)
,.l2tlbtol2_fwd_retry(core1_icache_l2tlbtol2_fwd_retry)
,.l2tlbtol2_fwd (core1_icache_l2tlbtol2_fwd )
,.l2todr_pfreq_valid (core1_icache_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core1_icache_l2todr_pfreq_retry )
,.l2todr_pfreq (core1_icache_l2todr_pfreq )
,.cachetopf_stats (core1_icache_pficache_l2stats )
,.l1tol2_disp_retry (unconnected_1_icache_l1tol2_disp_retry )
,.l2tol1_dack_valid (unconnected_1_icache_l2tol1_dack_valid )
,.l2tol1_dack (unconnected_1_icache_l2tol1_dack )
);
wire core1_l2todr_req_valid ;
wire core1_l2todr_req_retry ;
I_l2todr_req_type core1_l2todr_req ;
wire core1_drtol2_snack_valid ;
wire core1_drtol2_snack_retry ;
I_drtol2_snack_type core1_drtol2_snack ;
wire core1_l2todr_disp_valid ;
wire core1_l2todr_disp_retry ;
I_l2todr_disp_type core1_l2todr_disp ;
wire core1_drtol2_dack_valid ;
wire core1_drtol2_dack_retry ;
I_drtol2_dack_type core1_drtol2_dack ;
wire core1_l2todr_snoop_ack_valid;
wire core1_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_l2todr_snoop_ack ;
wire core1_l2todr_pfreq_valid ;
wire core1_l2todr_pfreq_retry ;
I_l2todr_pfreq_type core1_l2todr_pfreq ;
arbl2 l2arbiter_core1(
.clk(clk)
,.reset(reset)
,.l2d_0todr_req_valid (core1_slice0_l2todr_req_valid )
,.l2d_0todr_req_retry (core1_slice0_l2todr_req_retry )
,.l2d_0todr_req (core1_slice0_l2todr_req )
,.drtol2d_0_snack_valid (core1_slice0_drtol2_snack_valid )
,.drtol2d_0_snack_retry (core1_slice0_drtol2_snack_retry )
,.drtol2d_0_snack (core1_slice0_drtol2_snack )
,.l2d_0todr_disp_valid (core1_slice0_l2todr_disp_valid )
,.l2d_0todr_disp_retry (core1_slice0_l2todr_disp_retry )
,.l2d_0todr_disp (core1_slice0_l2todr_disp )
,.drtol2d_0_dack_valid (core1_slice0_drtol2_dack_valid )
,.drtol2d_0_dack_retry (core1_slice0_drtol2_dack_retry )
,.drtol2d_0_dack (core1_slice0_drtol2_dack )
,.l2d_0todr_snoop_ack_valid(core1_slice0_l2todr_snoop_ack_valid)
,.l2d_0todr_snoop_ack_retry(core1_slice0_l2todr_snoop_ack_retry)
,.l2d_0todr_snoop_ack (core1_slice0_l2todr_snoop_ack )
,.l2d_0todr_pfreq_valid (core1_slice0_l2todr_pfreq_valid )
,.l2d_0todr_pfreq_retry (core1_slice0_l2todr_pfreq_retry )
,.l2d_0todr_pfreq (core1_slice0_l2todr_pfreq )
,.l2d_1todr_req_valid (core1_slice1_l2todr_req_valid )
,.l2d_1todr_req_retry (core1_slice1_l2todr_req_retry )
,.l2d_1todr_req (core1_slice1_l2todr_req )
,.drtol2d_1_snack_valid (core1_slice1_drtol2_snack_valid )
,.drtol2d_1_snack_retry (core1_slice1_drtol2_snack_retry )
,.drtol2d_1_snack (core1_slice1_drtol2_snack )
,.l2d_1todr_disp_valid (core1_slice1_l2todr_disp_valid )
,.l2d_1todr_disp_retry (core1_slice1_l2todr_disp_retry )
,.l2d_1todr_disp (core1_slice1_l2todr_disp )
,.drtol2d_1_dack_valid (core1_slice1_drtol2_dack_valid )
,.drtol2d_1_dack_retry (core1_slice1_drtol2_dack_retry )
,.drtol2d_1_dack (core1_slice1_drtol2_dack )
,.l2d_1todr_snoop_ack_valid(core1_slice1_l2todr_snoop_ack_valid)
,.l2d_1todr_snoop_ack_retry(core1_slice1_l2todr_snoop_ack_retry)
,.l2d_1todr_snoop_ack (core1_slice1_l2todr_snoop_ack )
,.l2d_1todr_pfreq_valid (core1_slice1_l2todr_pfreq_valid )
,.l2d_1todr_pfreq_retry (core1_slice1_l2todr_pfreq_retry )
,.l2d_1todr_pfreq (core1_slice1_l2todr_pfreq )
`ifdef SC_4PIPE
,.l2d_2todr_req_valid (core1_slice2_l2todr_req_valid )
,.l2d_2todr_req_retry (core1_slice2_l2todr_req_retry )
,.l2d_2todr_req (core1_slice2_l2todr_req )
,.drtol2d_2_snack_valid (core1_slice2_drtol2_snack_valid )
,.drtol2d_2_snack_retry (core1_slice2_drtol2_snack_retry )
,.drtol2d_2_snack (core1_slice2_drtol2_snack )
,.l2d_2todr_disp_valid (core1_slice2_l2todr_disp_valid )
,.l2d_2todr_disp_retry (core1_slice2_l2todr_disp_retry )
,.l2d_2todr_disp (core1_slice2_l2todr_disp )
,.drtol2d_2_dack_valid (core1_slice2_drtol2_dack_valid )
,.drtol2d_2_dack_retry (core1_slice2_drtol2_dack_retry )
,.drtol2d_2_dack (core1_slice2_drtol2_dack )
,.l2d_2todr_snoop_ack_valid(core1_slice2_l2todr_snoop_ack_valid)
,.l2d_2todr_snoop_ack_retry(core1_slice2_l2todr_snoop_ack_retry)
,.l2d_2todr_snoop_ack (core1_slice2_l2todr_snoop_ack )
,.l2d_2todr_pfreq_valid (core1_slice2_l2todr_pfreq_valid )
,.l2d_2todr_pfreq_retry (core1_slice2_l2todr_pfreq_retry )
,.l2d_2todr_pfreq (core1_slice2_l2todr_pfreq )
,.l2d_3todr_req_valid (core1_slice3_l2todr_req_valid )
,.l2d_3todr_req_retry (core1_slice3_l2todr_req_retry )
,.l2d_3todr_req (core1_slice3_l2todr_req )
,.drtol2d_3_snack_valid (core1_slice3_drtol2_snack_valid )
,.drtol2d_3_snack_retry (core1_slice3_drtol2_snack_retry )
,.drtol2d_3_snack (core1_slice3_drtol2_snack )
,.l2d_3todr_disp_valid (core1_slice3_l2todr_disp_valid )
,.l2d_3todr_disp_retry (core1_slice3_l2todr_disp_retry )
,.l2d_3todr_disp (core1_slice3_l2todr_disp )
,.drtol2d_3_dack_valid (core1_slice3_drtol2_dack_valid )
,.drtol2d_3_dack_retry (core1_slice3_drtol2_dack_retry )
,.drtol2d_3_dack (core1_slice3_drtol2_dack )
,.l2d_3todr_snoop_ack_valid(core1_slice3_l2todr_snoop_ack_valid)
,.l2d_3todr_snoop_ack_retry(core1_slice3_l2todr_snoop_ack_retry)
,.l2d_3todr_snoop_ack (core1_slice3_l2todr_snoop_ack )
,.l2d_3todr_pfreq_valid (core1_slice3_l2todr_pfreq_valid )
,.l2d_3todr_pfreq_retry (core1_slice3_l2todr_pfreq_retry )
,.l2d_3todr_pfreq (core1_slice3_l2todr_pfreq )
`endif
,.l2todr_req_valid (core1_l2todr_req_valid )
,.l2todr_req_retry (core1_l2todr_req_retry )
,.l2todr_req (core1_l2todr_req )
,.drtol2_snack_valid (core1_drtol2_snack_valid )
,.drtol2_snack_retry (core1_drtol2_snack_retry )
,.drtol2_snack (core1_drtol2_snack )
,.l2todr_disp_valid (core1_l2todr_disp_valid )
,.l2todr_disp_retry (core1_l2todr_disp_retry )
,.l2todr_disp (core1_l2todr_disp )
,.drtol2_dack_valid (core1_drtol2_dack_valid )
,.drtol2_dack_retry (core1_drtol2_dack_retry )
,.drtol2_dack (core1_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_l2todr_snoop_ack )
,.l2todr_pfreq_valid (core1_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (core1_l2todr_pfreq_retry )
,.l2todr_pfreq (core1_l2todr_pfreq )
);
wire core1_l2tlb_l2todr_req_valid ;
wire core1_l2tlb_l2todr_req_retry ;
I_l2todr_req_type core1_l2tlb_l2todr_req ;
wire core1_l2tlb_drtol2_snack_valid ;
wire core1_l2tlb_drtol2_snack_retry ;
I_drtol2_snack_type core1_l2tlb_drtol2_snack ;
wire core1_l2tlb_l2todr_disp_valid ;
wire core1_l2tlb_l2todr_disp_retry ;
I_l2todr_disp_type core1_l2tlb_l2todr_disp ;
wire core1_l2tlb_drtol2_dack_valid ;
wire core1_l2tlb_drtol2_dack_retry ;
I_drtol2_dack_type core1_l2tlb_drtol2_dack ;
wire core1_l2tlb_l2todr_snoop_ack_valid;
wire core1_l2tlb_l2todr_snoop_ack_retry;
I_drsnoop_ack_type core1_l2tlb_l2todr_snoop_ack ;
arbl2tlb l2tlbarbiter_core1(
.clk(clk)
,.reset(reset)
,.l2d_0todr_req_valid (core1_slice0_l2tlb_l2todr_req_valid )
,.l2d_0todr_req_retry (core1_slice0_l2tlb_l2todr_req_retry )
,.l2d_0todr_req (core1_slice0_l2tlb_l2todr_req )
,.drtol2d_0_snack_valid (core1_slice0_l2tlb_drtol2_snack_valid )
,.drtol2d_0_snack_retry (core1_slice0_l2tlb_drtol2_snack_retry )
,.drtol2d_0_snack (core1_slice0_l2tlb_drtol2_snack )
,.l2d_0todr_disp_valid (core1_slice0_l2tlb_l2todr_disp_valid )
,.l2d_0todr_disp_retry (core1_slice0_l2tlb_l2todr_disp_retry )
,.l2d_0todr_disp (core1_slice0_l2tlb_l2todr_disp )
,.drtol2d_0_dack_valid (core1_slice0_l2tlb_drtol2_dack_valid )
,.drtol2d_0_dack_retry (core1_slice0_l2tlb_drtol2_dack_retry )
,.drtol2d_0_dack (core1_slice0_l2tlb_drtol2_dack )
,.l2d_0todr_snoop_ack_valid(core1_slice0_l2tlb_l2todr_snoop_ack_valid)
,.l2d_0todr_snoop_ack_retry(core1_slice0_l2tlb_l2todr_snoop_ack_retry)
,.l2d_0todr_snoop_ack (core1_slice0_l2tlb_l2todr_snoop_ack )
,.l2d_1todr_req_valid (core1_slice1_l2tlb_l2todr_req_valid )
,.l2d_1todr_req_retry (core1_slice1_l2tlb_l2todr_req_retry )
,.l2d_1todr_req (core1_slice1_l2tlb_l2todr_req )
,.drtol2d_1_snack_valid (core1_slice1_l2tlb_drtol2_snack_valid )
,.drtol2d_1_snack_retry (core1_slice1_l2tlb_drtol2_snack_retry )
,.drtol2d_1_snack (core1_slice1_l2tlb_drtol2_snack )
,.l2d_1todr_disp_valid (core1_slice1_l2tlb_l2todr_disp_valid )
,.l2d_1todr_disp_retry (core1_slice1_l2tlb_l2todr_disp_retry )
,.l2d_1todr_disp (core1_slice1_l2tlb_l2todr_disp )
,.drtol2d_1_dack_valid (core1_slice1_l2tlb_drtol2_dack_valid )
,.drtol2d_1_dack_retry (core1_slice1_l2tlb_drtol2_dack_retry )
,.drtol2d_1_dack (core1_slice1_l2tlb_drtol2_dack )
,.l2d_1todr_snoop_ack_valid(core1_slice1_l2tlb_l2todr_snoop_ack_valid)
,.l2d_1todr_snoop_ack_retry(core1_slice1_l2tlb_l2todr_snoop_ack_retry)
,.l2d_1todr_snoop_ack (core1_slice1_l2tlb_l2todr_snoop_ack )
`ifdef SC_4PIPE
,.l2d_2todr_req_valid (core1_slice2_l2tlb_l2todr_req_valid )
,.l2d_2todr_req_retry (core1_slice2_l2tlb_l2todr_req_retry )
,.l2d_2todr_req (core1_slice2_l2tlb_l2todr_req )
,.drtol2d_2_snack_valid (core1_slice2_l2tlb_drtol2_snack_valid )
,.drtol2d_2_snack_retry (core1_slice2_l2tlb_drtol2_snack_retry )
,.drtol2d_2_snack (core1_slice2_l2tlb_drtol2_snack )
,.l2d_2todr_disp_valid (core1_slice2_l2tlb_l2todr_disp_valid )
,.l2d_2todr_disp_retry (core1_slice2_l2tlb_l2todr_disp_retry )
,.l2d_2todr_disp (core1_slice2_l2tlb_l2todr_disp )
,.drtol2d_2_dack_valid (core1_slice2_l2tlb_drtol2_dack_valid )
,.drtol2d_2_dack_retry (core1_slice2_l2tlb_drtol2_dack_retry )
,.drtol2d_2_dack (core1_slice2_l2tlb_drtol2_dack )
,.l2d_2todr_snoop_ack_valid(core1_slice2_l2tlb_l2todr_snoop_ack_valid)
,.l2d_2todr_snoop_ack_retry(core1_slice2_l2tlb_l2todr_snoop_ack_retry)
,.l2d_2todr_snoop_ack (core1_slice2_l2tlb_l2todr_snoop_ack )
,.l2d_3todr_req_valid (core1_slice3_l2tlb_l2todr_req_valid )
,.l2d_3todr_req_retry (core1_slice3_l2tlb_l2todr_req_retry )
,.l2d_3todr_req (core1_slice3_l2tlb_l2todr_req )
,.drtol2d_3_snack_valid (core1_slice3_l2tlb_drtol2_snack_valid )
,.drtol2d_3_snack_retry (core1_slice3_l2tlb_drtol2_snack_retry )
,.drtol2d_3_snack (core1_slice3_l2tlb_drtol2_snack )
,.l2d_3todr_disp_valid (core1_slice3_l2tlb_l2todr_disp_valid )
,.l2d_3todr_disp_retry (core1_slice3_l2tlb_l2todr_disp_retry )
,.l2d_3todr_disp (core1_slice3_l2tlb_l2todr_disp )
,.drtol2d_3_dack_valid (core1_slice3_l2tlb_drtol2_dack_valid )
,.drtol2d_3_dack_retry (core1_slice3_l2tlb_drtol2_dack_retry )
,.drtol2d_3_dack (core1_slice3_l2tlb_drtol2_dack )
,.l2d_3todr_snoop_ack_valid(core1_slice3_l2tlb_l2todr_snoop_ack_valid)
,.l2d_3todr_snoop_ack_retry(core1_slice3_l2tlb_l2todr_snoop_ack_retry)
,.l2d_3todr_snoop_ack (core1_slice3_l2tlb_l2todr_snoop_ack )
`endif
,.l2todr_req_valid (core1_l2tlb_l2todr_req_valid )
,.l2todr_req_retry (core1_l2tlb_l2todr_req_retry )
,.l2todr_req (core1_l2tlb_l2todr_req )
,.drtol2_snack_valid (core1_l2tlb_drtol2_snack_valid )
,.drtol2_snack_retry (core1_l2tlb_drtol2_snack_retry )
,.drtol2_snack (core1_l2tlb_drtol2_snack )
,.l2todr_disp_valid (core1_l2tlb_l2todr_disp_valid )
,.l2todr_disp_retry (core1_l2tlb_l2todr_disp_retry )
,.l2todr_disp (core1_l2tlb_l2todr_disp )
,.drtol2_dack_valid (core1_l2tlb_drtol2_dack_valid )
,.drtol2_dack_retry (core1_l2tlb_drtol2_dack_retry )
,.drtol2_dack (core1_l2tlb_drtol2_dack )
,.l2todr_snoop_ack_valid(core1_l2tlb_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(core1_l2tlb_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (core1_l2tlb_l2todr_snoop_ack )
);
PF_cache_stats_type unconnected_pfe1_pf_dcstats ;
PF_cache_stats_type unconnected_pfe1_pf_l2stats ;
pfengine core1_pfe(
.clk(clk)
,.reset(reset)
,.pfgtopfe_op_valid(core1_pfgtopfe_op_valid)
,.pfgtopfe_op_retry(core1_pfgtopfe_op_retry)
,.pfgtopfe_op (core1_pfgtopfe_op )
,.pf0_l2stats (core1_slice0_pf0_l2stats )
,.pftodc_req0_valid(core1_slice0_pftodc_req0_valid)
,.pftodc_req0_retry(core1_slice0_pftodc_req0_retry)
,.pftodc_req0 (core1_slice0_pftodc_req0 )
,.pf0_dcstats (core1_slice0_pf0_dcstats )
,.pf1_l2stats (core1_slice1_pf1_l2stats )
,.pftodc_req1_valid(core1_slice1_pftodc_req1_valid)
,.pftodc_req1_retry(core1_slice1_pftodc_req1_retry)
,.pftodc_req1 (core1_slice1_pftodc_req1 )
,.pf1_dcstats (core1_slice1_pf1_dcstats )
`ifdef SC_4PIPE
,.pf2_l2stats (core1_slice2_pf2_l2stats )
,.pftodc_req2_valid(core1_slice2_pftodc_req2_valid)
,.pftodc_req2_retry(core1_slice2_pftodc_req2_retry)
,.pftodc_req2 (core1_slice2_pftodc_req2 )
,.pf2_dcstats (core1_slice2_pf2_dcstats )
,.pf3_l2stats (core1_slice3_pf3_l2stats )
,.pftodc_req3_valid(core1_slice3_pftodc_req3_valid)
,.pftodc_req3_retry(core1_slice3_pftodc_req3_retry)
,.pftodc_req3 (core1_slice3_pftodc_req3 )
,.pf3_dcstats (core1_slice3_pf3_dcstats )
`endif
,.pf_dcstats (unconnected_pfe1_pf_dcstats )
,.pf_l2stats (unconnected_pfe1_pf_l2stats )
);
directory_bank dr_0(
.clk(clk)
,.reset(reset)
,.l2todr_req_valid (dr0_l2todr_req_valid )
,.l2todr_req_retry (dr0_l2todr_req_retry )
,.l2todr_req (dr0_l2todr_req )
,.drtol2_snack_valid (dr0_drtol2_snack_valid )
,.drtol2_snack_retry (dr0_drtol2_snack_retry )
,.drtol2_snack (dr0_drtol2_snack )
,.l2todr_disp_valid (dr0_l2todr_disp_valid )
,.l2todr_disp_retry (dr0_l2todr_disp_retry )
,.l2todr_disp (dr0_l2todr_disp )
,.drtol2_dack_valid (dr0_drtol2_dack_valid )
,.drtol2_dack_retry (dr0_drtol2_dack_retry )
,.drtol2_dack (dr0_drtol2_dack )
,.l2todr_snoop_ack_valid(dr0_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(dr0_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (dr0_l2todr_snoop_ack )
,.l2todr_pfreq_valid (dr0_tlb_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (dr0_tlb_l2todr_pfreq_retry )
,.l2todr_pfreq (dr0_tlb_l2todr_pfreq )
,.drtomem_req_valid (dr0_drtomem_req_valid )
,.drtomem_req_retry (dr0_drtomem_req_retry )
,.drtomem_req (dr0_drtomem_req )
,.memtodr_ack_valid (dr0_memtodr_ack_valid )
,.memtodr_ack_retry (dr0_memtodr_ack_retry )
,.memtodr_ack (dr0_memtodr_ack )
,.drtomem_wb_valid (dr0_drtomem_wb_valid )
,.drtomem_wb_retry (dr0_drtomem_wb_retry )
,.drtomem_wb (dr0_drtomem_wb )
,.drtomem_pfreq_valid (dr0_drtomem_pfreq_valid )
,.drtomem_pfreq_retry (dr0_drtomem_pfreq_retry )
,.drtomem_pfreq (dr0_drtomem_pfreq )
);
directory_bank dr_1(
.clk(clk)
,.reset(reset)
,.l2todr_req_valid (dr1_l2todr_req_valid )
,.l2todr_req_retry (dr1_l2todr_req_retry )
,.l2todr_req (dr1_l2todr_req )
,.drtol2_snack_valid (dr1_drtol2_snack_valid )
,.drtol2_snack_retry (dr1_drtol2_snack_retry )
,.drtol2_snack (dr1_drtol2_snack )
,.l2todr_disp_valid (dr1_l2todr_disp_valid )
,.l2todr_disp_retry (dr1_l2todr_disp_retry )
,.l2todr_disp (dr1_l2todr_disp )
,.drtol2_dack_valid (dr1_drtol2_dack_valid )
,.drtol2_dack_retry (dr1_drtol2_dack_retry )
,.drtol2_dack (dr1_drtol2_dack )
,.l2todr_snoop_ack_valid(dr1_l2todr_snoop_ack_valid)
,.l2todr_snoop_ack_retry(dr1_l2todr_snoop_ack_retry)
,.l2todr_snoop_ack (dr1_l2todr_snoop_ack )
,.l2todr_pfreq_valid (dr1_tlb_l2todr_pfreq_valid )
,.l2todr_pfreq_retry (dr1_tlb_l2todr_pfreq_retry )
,.l2todr_pfreq (dr1_tlb_l2todr_pfreq )
,.drtomem_req_valid (dr1_drtomem_req_valid )
,.drtomem_req_retry (dr1_drtomem_req_retry )
,.drtomem_req (dr1_drtomem_req )
,.memtodr_ack_valid (dr1_memtodr_ack_valid )
,.memtodr_ack_retry (dr1_memtodr_ack_retry )
,.memtodr_ack (dr1_memtodr_ack )
,.drtomem_wb_valid (dr1_drtomem_wb_valid )
,.drtomem_wb_retry (dr1_drtomem_wb_retry )
,.drtomem_wb (dr1_drtomem_wb )
,.drtomem_pfreq_valid (dr1_drtomem_pfreq_valid )
,.drtomem_pfreq_retry (dr1_drtomem_pfreq_retry )
,.drtomem_pfreq (dr1_drtomem_pfreq )
);
wire dr0_l2todr_req_valid ;
wire dr0_l2todr_req_retry ;
I_l2todr_req_type dr0_l2todr_req ;
wire dr0_drtol2_snack_valid ;
wire dr0_drtol2_snack_retry ;
I_drtol2_snack_type dr0_drtol2_snack ;
wire dr0_l2todr_disp_valid ;
wire dr0_l2todr_disp_retry ;
I_l2todr_disp_type dr0_l2todr_disp ;
wire dr0_drtol2_dack_valid ;
wire dr0_drtol2_dack_retry ;
I_drtol2_dack_type dr0_drtol2_dack ;
wire dr0_l2todr_snoop_ack_valid;
wire dr0_l2todr_snoop_ack_retry;
I_drsnoop_ack_type dr0_l2todr_snoop_ack ;
wire dr0_tlb_l2todr_pfreq_valid ;
wire dr0_tlb_l2todr_pfreq_retry ;
I_l2todr_pfreq_type dr0_tlb_l2todr_pfreq ;
wire dr1_l2todr_req_valid ;
wire dr1_l2todr_req_retry ;
I_l2todr_req_type dr1_l2todr_req ;
wire dr1_drtol2_snack_valid ;
wire dr1_drtol2_snack_retry ;
I_drtol2_snack_type dr1_drtol2_snack ;
wire dr1_l2todr_disp_valid ;
wire dr1_l2todr_disp_retry ;
I_l2todr_disp_type dr1_l2todr_disp ;
wire dr1_drtol2_dack_valid ;
wire dr1_drtol2_dack_retry ;
I_drtol2_dack_type dr1_drtol2_dack ;
wire dr1_l2todr_snoop_ack_valid;
wire dr1_l2todr_snoop_ack_retry;
I_drsnoop_ack_type dr1_l2todr_snoop_ack ;
wire dr1_tlb_l2todr_pfreq_valid ;
wire dr1_tlb_l2todr_pfreq_retry ;
I_l2todr_pfreq_type dr1_tlb_l2todr_pfreq ;
net_2core2dr network(
.clk(clk)
,.reset(reset)
// core 0 l2i and l2d
,.c0_l2itodr_req_valid (core0_icache_l2todr_req_valid )
,.c0_l2itodr_req_retry (core0_icache_l2todr_req_retry )
,.c0_l2itodr_req (core0_icache_l2todr_req )
,.c0_drtol2i_snack_valid (core0_icache_drtol2_snack_valid )
,.c0_drtol2i_snack_retry (core0_icache_drtol2_snack_retry )
,.c0_drtol2i_snack (core0_icache_drtol2_snack )
,.c0_l2itodr_disp_valid (core0_icache_l2todr_disp_valid )
,.c0_l2itodr_disp_retry (core0_icache_l2todr_disp_retry )
,.c0_l2itodr_disp (core0_icache_l2todr_disp )
,.c0_drtol2i_dack_valid (core0_icache_drtol2_dack_valid )
,.c0_drtol2i_dack_retry (core0_icache_drtol2_dack_retry )
,.c0_drtol2i_dack (core0_icache_drtol2_dack )
,.c0_l2itodr_snoop_ack_valid(core0_icache_l2todr_snoop_ack_valid)
,.c0_l2itodr_snoop_ack_retry(core0_icache_l2todr_snoop_ack_retry)
,.c0_l2itodr_snoop_ack (core0_icache_l2todr_snoop_ack )
,.c0_l2ittodr_req_valid (core0_icache_l2todr_req_valid )
,.c0_l2ittodr_req_retry (core0_icache_l2todr_req_retry )
,.c0_l2ittodr_req (core0_icache_l2todr_req )
,.c0_drtol2it_snack_valid (core0_icache_drtol2_snack_valid )
,.c0_drtol2it_snack_retry (core0_icache_drtol2_snack_retry )
,.c0_drtol2it_snack (core0_icache_drtol2_snack )
,.c0_l2ittodr_disp_valid (core0_icache_l2todr_disp_valid )
,.c0_l2ittodr_disp_retry (core0_icache_l2todr_disp_retry )
,.c0_l2ittodr_disp (core0_icache_l2todr_disp )
,.c0_drtol2it_dack_valid (core0_icache_drtol2_dack_valid )
,.c0_drtol2it_dack_retry (core0_icache_drtol2_dack_retry )
,.c0_drtol2it_dack (core0_icache_drtol2_dack )
,.c0_l2ittodr_snoop_ack_valid(core0_icache_l2todr_snoop_ack_valid)
,.c0_l2ittodr_snoop_ack_retry(core0_icache_l2todr_snoop_ack_retry)
,.c0_l2ittodr_snoop_ack (core0_icache_l2todr_snoop_ack )
,.c0_l2itodr_pfreq_valid (core0_icache_l2todr_pfreq_valid )
,.c0_l2itodr_pfreq_retry (core0_icache_l2todr_pfreq_retry )
,.c0_l2itodr_pfreq (core0_icache_l2todr_pfreq )
,.c0_l2d_0todr_req_valid (core0_l2todr_req_valid )
,.c0_l2d_0todr_req_retry (core0_l2todr_req_retry )
,.c0_l2d_0todr_req (core0_l2todr_req )
,.c0_drtol2d_0_snack_valid (core0_drtol2_snack_valid )
,.c0_drtol2d_0_snack_retry (core0_drtol2_snack_retry )
,.c0_drtol2d_0_snack (core0_drtol2_snack )
,.c0_l2d_0todr_disp_valid (core0_l2todr_disp_valid )
,.c0_l2d_0todr_disp_retry (core0_l2todr_disp_retry )
,.c0_l2d_0todr_disp (core0_l2todr_disp )
,.c0_drtol2d_0_dack_valid (core0_drtol2_dack_valid )
,.c0_drtol2d_0_dack_retry (core0_drtol2_dack_retry )
,.c0_drtol2d_0_dack (core0_drtol2_dack )
,.c0_l2d_0todr_snoop_ack_valid(core0_l2todr_snoop_ack_valid)
,.c0_l2d_0todr_snoop_ack_retry(core0_l2todr_snoop_ack_retry)
,.c0_l2d_0todr_snoop_ack (core0_l2todr_snoop_ack )
,.c0_l2d_0todr_pfreq_valid (core0_l2todr_pfreq_valid )
,.c0_l2d_0todr_pfreq_retry (core0_l2todr_pfreq_retry )
,.c0_l2d_0todr_pfreq (core0_l2todr_pfreq )
,.c0_l2dt_0todr_req_valid (core0_l2tlb_l2todr_req_valid )
,.c0_l2dt_0todr_req_retry (core0_l2tlb_l2todr_req_retry )
,.c0_l2dt_0todr_req (core0_l2tlb_l2todr_req )
,.c0_drtol2dt_0_snack_valid (core0_l2tlb_drtol2_snack_valid )
,.c0_drtol2dt_0_snack_retry (core0_l2tlb_drtol2_snack_retry )
,.c0_drtol2dt_0_snack (core0_l2tlb_drtol2_snack )
,.c0_l2dt_0todr_disp_valid (core0_l2tlb_l2todr_disp_valid )
,.c0_l2dt_0todr_disp_retry (core0_l2tlb_l2todr_disp_retry )
,.c0_l2dt_0todr_disp (core0_l2tlb_l2todr_disp )
,.c0_drtol2dt_0_dack_valid (core0_l2tlb_drtol2_dack_valid )
,.c0_drtol2dt_0_dack_retry (core0_l2tlb_drtol2_dack_retry )
,.c0_drtol2dt_0_dack (core0_l2tlb_drtol2_dack )
,.c0_l2dt_0todr_snoop_ack_valid(core0_l2tlb_l2todr_snoop_ack_valid)
,.c0_l2dt_0todr_snoop_ack_retry(core0_l2tlb_l2todr_snoop_ack_retry)
,.c0_l2dt_0todr_snoop_ack (core0_l2tlb_l2todr_snoop_ack )
// core 1 l2i and l2d
,.c1_l2itodr_req_valid (core1_icache_l2todr_req_valid )
,.c1_l2itodr_req_retry (core1_icache_l2todr_req_retry )
,.c1_l2itodr_req (core1_icache_l2todr_req )
,.c1_drtol2i_snack_valid (core1_icache_drtol2_snack_valid )
,.c1_drtol2i_snack_retry (core1_icache_drtol2_snack_retry )
,.c1_drtol2i_snack (core1_icache_drtol2_snack )
,.c1_l2itodr_disp_valid (core1_icache_l2todr_disp_valid )
,.c1_l2itodr_disp_retry (core1_icache_l2todr_disp_retry )
,.c1_l2itodr_disp (core1_icache_l2todr_disp )
,.c1_drtol2i_dack_valid (core1_icache_drtol2_dack_valid )
,.c1_drtol2i_dack_retry (core1_icache_drtol2_dack_retry )
,.c1_drtol2i_dack (core1_icache_drtol2_dack )
,.c1_l2itodr_snoop_ack_valid(core1_icache_l2todr_snoop_ack_valid)
,.c1_l2itodr_snoop_ack_retry(core1_icache_l2todr_snoop_ack_retry)
,.c1_l2itodr_snoop_ack (core1_icache_l2todr_snoop_ack )
,.c1_l2ittodr_req_valid (core1_icache_l2todr_req_valid )
,.c1_l2ittodr_req_retry (core1_icache_l2todr_req_retry )
,.c1_l2ittodr_req (core1_icache_l2todr_req )
,.c1_drtol2it_snack_valid (core1_icache_drtol2_snack_valid )
,.c1_drtol2it_snack_retry (core1_icache_drtol2_snack_retry )
,.c1_drtol2it_snack (core1_icache_drtol2_snack )
,.c1_l2ittodr_disp_valid (core1_icache_l2todr_disp_valid )
,.c1_l2ittodr_disp_retry (core1_icache_l2todr_disp_retry )
,.c1_l2ittodr_disp (core1_icache_l2todr_disp )
,.c1_drtol2it_dack_valid (core1_icache_drtol2_dack_valid )
,.c1_drtol2it_dack_retry (core1_icache_drtol2_dack_retry )
,.c1_drtol2it_dack (core1_icache_drtol2_dack )
,.c1_l2ittodr_snoop_ack_valid(core1_icache_l2todr_snoop_ack_valid)
,.c1_l2ittodr_snoop_ack_retry(core1_icache_l2todr_snoop_ack_retry)
,.c1_l2ittodr_snoop_ack (core1_icache_l2todr_snoop_ack )
,.c1_l2itodr_pfreq_valid (core1_icache_l2todr_pfreq_valid )
,.c1_l2itodr_pfreq_retry (core1_icache_l2todr_pfreq_retry )
,.c1_l2itodr_pfreq (core1_icache_l2todr_pfreq )
,.c1_l2d_0todr_req_valid (core1_l2todr_req_valid )
,.c1_l2d_0todr_req_retry (core1_l2todr_req_retry )
,.c1_l2d_0todr_req (core1_l2todr_req )
,.c1_drtol2d_0_snack_valid (core1_drtol2_snack_valid )
,.c1_drtol2d_0_snack_retry (core1_drtol2_snack_retry )
,.c1_drtol2d_0_snack (core1_drtol2_snack )
,.c1_l2d_0todr_disp_valid (core1_l2todr_disp_valid )
,.c1_l2d_0todr_disp_retry (core1_l2todr_disp_retry )
,.c1_l2d_0todr_disp (core1_l2todr_disp )
,.c1_drtol2d_0_dack_valid (core1_drtol2_dack_valid )
,.c1_drtol2d_0_dack_retry (core1_drtol2_dack_retry )
,.c1_drtol2d_0_dack (core1_drtol2_dack )
,.c1_l2d_0todr_snoop_ack_valid(core1_l2todr_snoop_ack_valid)
,.c1_l2d_0todr_snoop_ack_retry(core1_l2todr_snoop_ack_retry)
,.c1_l2d_0todr_snoop_ack (core1_l2todr_snoop_ack )
,.c1_l2d_0todr_pfreq_valid (core1_l2todr_pfreq_valid )
,.c1_l2d_0todr_pfreq_retry (core1_l2todr_pfreq_retry )
,.c1_l2d_0todr_pfreq (core1_l2todr_pfreq )
,.c1_l2dt_0todr_req_valid (core1_l2tlb_l2todr_req_valid )
,.c1_l2dt_0todr_req_retry (core1_l2tlb_l2todr_req_retry )
,.c1_l2dt_0todr_req (core1_l2tlb_l2todr_req )
,.c1_drtol2dt_0_snack_valid (core1_l2tlb_drtol2_snack_valid )
,.c1_drtol2dt_0_snack_retry (core1_l2tlb_drtol2_snack_retry )
,.c1_drtol2dt_0_snack (core1_l2tlb_drtol2_snack )
,.c1_l2dt_0todr_disp_valid (core1_l2tlb_l2todr_disp_valid )
,.c1_l2dt_0todr_disp_retry (core1_l2tlb_l2todr_disp_retry )
,.c1_l2dt_0todr_disp (core1_l2tlb_l2todr_disp )
,.c1_drtol2dt_0_dack_valid (core1_l2tlb_drtol2_dack_valid )
,.c1_drtol2dt_0_dack_retry (core1_l2tlb_drtol2_dack_retry )
,.c1_drtol2dt_0_dack (core1_l2tlb_drtol2_dack )
,.c1_l2dt_0todr_snoop_ack_valid(core1_l2tlb_l2todr_snoop_ack_valid)
,.c1_l2dt_0todr_snoop_ack_retry(core1_l2tlb_l2todr_snoop_ack_retry)
,.c1_l2dt_0todr_snoop_ack (core1_l2tlb_l2todr_snoop_ack )
// Directory 0 interface
,.l2todr0_req_valid (dr0_l2todr_req_valid )
,.l2todr0_req_retry (dr0_l2todr_req_retry )
,.l2todr0_req (dr0_l2todr_req )
,.dr0tol2_snack_valid (dr0_drtol2_snack_valid )
,.dr0tol2_snack_retry (dr0_drtol2_snack_retry )
,.dr0tol2_snack (dr0_drtol2_snack )
,.l2todr0_disp_valid (dr0_l2todr_disp_valid )
,.l2todr0_disp_retry (dr0_l2todr_disp_retry )
,.l2todr0_disp (dr0_l2todr_disp )
,.dr0tol2_dack_valid (dr0_drtol2_dack_valid )
,.dr0tol2_dack_retry (dr0_drtol2_dack_retry )
,.dr0tol2_dack (dr0_drtol2_dack )
,.l2todr0_snoop_ack_valid(dr0_l2todr_snoop_ack_valid)
,.l2todr0_snoop_ack_retry(dr0_l2todr_snoop_ack_retry)
,.l2todr0_snoop_ack (dr0_l2todr_snoop_ack )
,.l2todr0_pfreq_valid (dr0_tlb_l2todr_pfreq_valid )
,.l2todr0_pfreq_retry (dr0_tlb_l2todr_pfreq_retry )
,.l2todr0_pfreq (dr0_tlb_l2todr_pfreq )
// Directory 1 interface
,.l2todr1_req_valid (dr1_l2todr_req_valid )
,.l2todr1_req_retry (dr1_l2todr_req_retry )
,.l2todr1_req (dr1_l2todr_req )
,.dr1tol2_snack_valid (dr1_drtol2_snack_valid )
,.dr1tol2_snack_retry (dr1_drtol2_snack_retry )
,.dr1tol2_snack (dr1_drtol2_snack )
,.l2todr1_disp_valid (dr1_l2todr_disp_valid )
,.l2todr1_disp_retry (dr1_l2todr_disp_retry )
,.l2todr1_disp (dr1_l2todr_disp )
,.dr1tol2_dack_valid (dr1_drtol2_dack_valid )
,.dr1tol2_dack_retry (dr1_drtol2_dack_retry )
,.dr1tol2_dack (dr1_drtol2_dack )
,.l2todr1_snoop_ack_valid(dr1_l2todr_snoop_ack_valid)
,.l2todr1_snoop_ack_retry(dr1_l2todr_snoop_ack_retry)
,.l2todr1_snoop_ack (dr1_l2todr_snoop_ack )
,.l2todr1_pfreq_valid (dr1_tlb_l2todr_pfreq_valid )
,.l2todr1_pfreq_retry (dr1_tlb_l2todr_pfreq_retry )
,.l2todr1_pfreq (dr1_tlb_l2todr_pfreq )
);
/* verilator lint_on UNUSED */
/* verilator lint_on UNDRIVEN */
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DIODE_BEHAVIORAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_M_V
`define SKY130_FD_SC_LP__O21AI_M_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_m (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_m (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_M_V
|
// 4 3 2 1 0
// L W S E N
// sram: x: 00 y: 10
// scheduler: x: 00 y: 01
module mapreduce(clk, rst, scheduler_wen);
parameter WIDTH=36;
parameter DEPTH=8;
parameter ADDR=4;
parameter lhsCount=5;
parameter rhsCount=5;
input clk;
input rst;
// Start the scheduler from the outside.
// Since the scheduler is the trigger of the whole system, thus start the whole system.
input scheduler_wen;
// For version 0.0, the communication is only:
// from scheduler to sram
// from sram to scheduler
// from scheduler to mapper
// from mapper to reducer
wire [WIDTH-1:0] link_sramtoscheduler;
wire [WIDTH-1:0] link_schedulertosram;
wire [WIDTH-1:0] link_schedulertonode;
wire [WIDTH-1:0] link_nodetoreducer;
// Define the locations of each submodule
reg [1:0] sram_locationx;
reg [1:0] sram_locationy;
reg [1:0] scheduler_locationx;
reg [1:0] scheduler_locationy;
reg [1:0] node_locationx;
reg [1:0] node_locationy;
reg [1:0] reducer_locationx;
reg [1:0] reducer_locationy;
wire [4:0] scheduler_valid_in_0;
reg [4:0] scheduler_valid_in_1;
reg [4:0] scheduler_valid_in_2;
// Modulate the timing
// Delay the input to scheduler_valide_in_L.
assign scheduler_valid_in_0[4] = scheduler_router0.sch0.enableout;
always@(posedge clk or negedge rst)
if(!rst)
scheduler_valid_in_1 <= 5'd0;
else
scheduler_valid_in_1 <= scheduler_valid_in_0;
always@(posedge clk or negedge rst)
if(!rst)
scheduler_valid_in_2 <= 5'd0;
else
scheduler_valid_in_2 <= scheduler_valid_in_1;
wire scheduler_valid_in_N;
wire scheduler_valid_in_S;
wire scheduler_valid_in_W;
wire scheduler_valid_in_E;
assign scheduler_router0.Data_in_valid[4] = scheduler_valid_in_1[4];
// Valid_in Definitions
wire sram_valid_in_N;
wire sram_valid_in_S;
wire sram_valid_in_W;
wire sram_valid_in_E;
wire node_valid_in_N;
wire node_valid_in_S;
wire node_valid_in_W;
wire node_valid_in_E;
// Valid_out Definitions
wire scheduler_valid_out_N;
wire scheduler_valid_out_S;
wire scheduler_valid_out_W;
wire scheduler_valid_out_E;
wire sram_valid_out_N;
wire sram_valid_out_S;
wire sram_valid_out_W;
wire sram_valid_out_E;
wire node_valid_out_N;
wire node_valid_out_S;
wire node_valid_out_W;
wire node_valid_out_E;
// Cross-router valid signal connection.
assign scheduler_valid_in_W = sram_valid_out_E;
assign scheduler_valid_in_S = 0;
assign scheduler_valid_in_E = 0;
assign scheduler_valid_in_N = 0;
assign sram_valid_in_W = 0;
assign sram_valid_in_S = 0;
assign sram_valid_in_E = scheduler_valid_out_W;
assign sram_valid_in_N = 0;
assign node_valid_in_W = scheduler_valid_out_E;
assign node_valid_in_S = 0;
assign node_valid_in_E = 0;
assign node_valid_in_N = 0;
// PE locations.
always@*
if(!rst) begin
sram_locationx = 2'b00;
sram_locationy = 2'b01;
scheduler_locationx = 2'b01;
scheduler_locationy = 2'b01;
node_locationx = 2'b10;
node_locationy = 2'b01;
end
else begin
sram_locationx = 2'b00;
sram_locationy = 2'b01;
scheduler_locationx = 2'b01;
scheduler_locationy = 2'b01;
node_locationx = 2'b10;
node_locationy = 2'b01;
end
// Instantiations
sram_router sram_router0(
.clk(clk),
.rst(rst),
.Data_in_N(),
.Data_in_S(),
.Data_in_W(),
.Data_in_E(link_schedulertosram),
.Data_in_ready_N(),
.Data_in_ready_S(),
.Data_in_ready_W(),
.Data_in_ready_E(),
.Data_out_N(),
.Data_out_S(),
.Data_out_W(),
.Data_out_E(link_sramtoscheduler),
.Data_out_ready_N(),
.Data_out_ready_S(),
.Data_out_ready_W(),
.Data_out_ready_E(),
.Data_in_valid_N(sram_valid_in_N),
.Data_in_valid_S(sram_valid_in_S),
.Data_in_valid_W(sram_valid_in_W),
.Data_in_valid_E(sram_valid_in_E),
.Data_out_valid_N(sram_valid_out_N),
.Data_out_valid_S(sram_valid_out_S),
.Data_out_valid_W(sram_valid_out_W),
.Data_out_valid_E(sram_valid_out_E),
.noc_locationx(sram_locationx),
.noc_locationy(sram_locationy)
);
scheduler_router scheduler_router0(
.clk(clk),
.rst(rst),
.wen(scheduler_wen),
.Data_in_N(),
.Data_in_S(),
.Data_in_W(link_sramtoscheduler),
.Data_in_E(),
.Data_in_ready_N(),
.Data_in_ready_S(),
.Data_in_ready_W(),
.Data_in_ready_E(),
.Data_out_N(),
.Data_out_S(),
.Data_out_W(link_schedulertosram),
.Data_out_E(link_schedulertonode),
.Data_out_ready_N(),
.Data_out_ready_S(),
.Data_out_ready_W(),
.Data_out_ready_E(),
.Data_out_valid_N(scheduler_valid_out_N),
.Data_out_valid_S(scheduler_valid_out_S),
.Data_out_valid_W(scheduler_valid_out_W),
.Data_out_valid_E(scheduler_valid_out_E),
//.bustorouter_valid(scheduler_valid_in),
.Data_in_valid_N(scheduler_valid_in_N),
.Data_in_valid_E(scheduler_valid_in_E),
.Data_in_valid_S(scheduler_valid_in_S),
.Data_in_valid_W(scheduler_valid_in_W),
.noc_locationx(scheduler_locationx),
.noc_locationy(scheduler_locationy)
);
node_router node_router0(
.clk(clk),
.rst(rst),
.Data_in_N(),
.Data_in_S(),
.Data_in_W(link_schedulertonode),
.Data_in_E(),
.Data_in_ready_N(),
.Data_in_ready_S(),
.Data_in_ready_W(),
.Data_in_ready_E(),
.Data_out_N(),
.Data_out_S(),
.Data_out_W(),
.Data_out_E(),
.Data_out_ready_N(),
.Data_out_ready_S(),
.Data_out_ready_W(),
.Data_out_ready_E(),
.Data_out_valid_N(node_valid_out_N),
.Data_out_valid_S(node_valid_out_S),
.Data_out_valid_W(node_valid_out_W),
.Data_out_valid_E(node_valid_out_E),
.Data_in_valid_N(node_valid_in_N),
.Data_in_valid_E(node_valid_in_E),
.Data_in_valid_S(node_valid_in_S),
.Data_in_valid_W(node_valid_in_W),
.noc_locationx(node_locationx),
.noc_locationy(node_locationy)
);
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description:
* Tranlates data from a Ping Pong FIFO to an AXI Stream
*
* Changes: Who? What?
* 04/06/2017: DFM Initial check in.
* 04/06/2017: DFM Added count so that the 'last' will not be strobed until
* all is sent.
*/
`timescale 1ps / 1ps
module adapter_ppfifo_2_axi_stream #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
)(
input rst,
//Ping Poing FIFO Read Interface
input i_ppfifo_rdy,
output reg o_ppfifo_act,
input [23:0] i_ppfifo_size,
input [(DATA_WIDTH + 1) - 1:0] i_ppfifo_data,
output o_ppfifo_stb,
//AXI Stream Output
input i_axi_clk,
output [3:0] o_axi_user,
input i_axi_ready,
output [DATA_WIDTH - 1:0] o_axi_data,
output o_axi_last,
output reg o_axi_valid,
output [31:0] o_debug
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
reg [3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
assign o_axi_data = i_ppfifo_data[DATA_WIDTH - 1: 0];
assign o_ppfifo_stb = (i_axi_ready & o_axi_valid);
assign o_axi_user[0] = (r_count < i_ppfifo_size) ? i_ppfifo_data[DATA_WIDTH] : 1'b0;
assign o_axi_user[3:1] = 3'h0;
assign o_axi_last = ((r_count + 1) >= i_ppfifo_size) & o_ppfifo_act & o_axi_valid;
//synchronous logic
assign o_debug[3:0] = state;
assign o_debug[4] = (r_count < i_ppfifo_size) ? i_ppfifo_data[DATA_WIDTH]: 1'b0;
assign o_debug[5] = o_ppfifo_act;
assign o_debug[6] = i_ppfifo_rdy;
assign o_debug[7] = (r_count > 0);
assign o_debug[8] = (i_ppfifo_size > 0);
assign o_debug[9] = (r_count == i_ppfifo_size);
assign o_debug[15:10] = 0;
assign o_debug[23:16] = r_count[7:0];
assign o_debug[31:24] = 0;
always @ (posedge i_axi_clk) begin
o_axi_valid <= 0;
if (rst) begin
state <= IDLE;
o_ppfifo_act <= 0;
r_count <= 0;
end
else begin
case (state)
IDLE: begin
o_ppfifo_act <= 0;
if (i_ppfifo_rdy && !o_ppfifo_act) begin
r_count <= 0;
o_ppfifo_act <= 1;
state <= READY;
end
end
READY: begin
if (r_count < i_ppfifo_size) begin
o_axi_valid <= 1;
if (i_axi_ready && o_axi_valid) begin
r_count <= r_count + 1;
if ((r_count + 1) >= i_ppfifo_size) begin
o_axi_valid <= 0;
end
end
end
else begin
o_ppfifo_act <= 0;
state <= RELEASE;
end
end
RELEASE: begin
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLXBP_FUNCTIONAL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_FUNCTIONAL_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: small_fifo_test.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module small_fifo_test (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [71:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [71:0] q;
output [2:0] usedw;
wire [2:0] sub_wire0;
wire sub_wire1;
wire [71:0] sub_wire2;
wire sub_wire3;
wire [2:0] usedw = sub_wire0[2:0];
wire empty = sub_wire1;
wire [71:0] q = sub_wire2[71:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.sclr (sclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix II",
scfifo_component.lpm_numwords = 8,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 72,
scfifo_component.lpm_widthu = 3,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "8"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "72"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL data[71..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL q[71..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
// Retrieval info: USED_PORT: usedw 0 0 3 0 OUTPUT NODEFVAL usedw[2..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 3 0 @usedw 0 0 3 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Wed May 03 18:20:15 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/andrewandre/Documents/GitHub/kernel-on-chip/hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_sim_netlist.v
// Design : bd_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module bd_clk_wiz_0_0
(clk_ref_i,
aclk,
sys_clk_i,
resetn,
clk_in1);
output clk_ref_i;
output aclk;
output sys_clk_i;
input resetn;
input clk_in1;
wire aclk;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_ref_i;
wire resetn;
wire sys_clk_i;
bd_clk_wiz_0_0_bd_clk_wiz_0_0_clk_wiz inst
(.aclk(aclk),
.clk_in1(clk_in1),
.clk_ref_i(clk_ref_i),
.resetn(resetn),
.sys_clk_i(sys_clk_i));
endmodule
(* ORIG_REF_NAME = "bd_clk_wiz_0_0_clk_wiz" *)
module bd_clk_wiz_0_0_bd_clk_wiz_0_0_clk_wiz
(clk_ref_i,
aclk,
sys_clk_i,
resetn,
clk_in1);
output clk_ref_i;
output aclk;
output sys_clk_i;
input resetn;
input clk_in1;
wire aclk;
wire aclk_bd_clk_wiz_0_0;
wire clk_in1;
wire clk_in1_bd_clk_wiz_0_0;
wire clk_ref_i;
wire clk_ref_i_bd_clk_wiz_0_0;
wire clkfbout_bd_clk_wiz_0_0;
wire clkfbout_buf_bd_clk_wiz_0_0;
wire reset_high;
wire resetn;
wire sys_clk_i;
wire sys_clk_i_bd_clk_wiz_0_0;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_bd_clk_wiz_0_0),
.O(clkfbout_buf_bd_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_bd_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_ref_i_bd_clk_wiz_0_0),
.O(clk_ref_i));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(aclk_bd_clk_wiz_0_0),
.O(aclk));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(sys_clk_i_bd_clk_wiz_0_0),
.O(sys_clk_i));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(5.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(20),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(10),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_bd_clk_wiz_0_0),
.CLKFBOUT(clkfbout_bd_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_bd_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_ref_i_bd_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(aclk_bd_clk_wiz_0_0),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(sys_clk_i_bd_clk_wiz_0_0),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
mmcm_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog wrapper for lpflow_clkinvkapwr with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkinvkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.49d
// \ \ Application: netgen
// / / Filename: floating_point_v5_0.v
// /___/ /\ Timestamp: Wed Mar 26 14:09:06 2014
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ecelrc/students/smirkhani/maysam/adder/tmp/_cg/floating_point_v5_0.ngc /home/ecelrc/students/smirkhani/maysam/adder/tmp/_cg/floating_point_v5_0.v
// Device : 7vx330tffg1157-2
// Input file : /home/ecelrc/students/smirkhani/maysam/adder/tmp/_cg/floating_point_v5_0.ngc
// Output file : /home/ecelrc/students/smirkhani/maysam/adder/tmp/_cg/floating_point_v5_0.v
// # of Modules : 1
// Design Name : floating_point_v5_0
// Xilinx : /misc/linuxws/packages/Xilinx/14.4/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module floating_point_v5_0 (
clk, a, b, operation, result
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input [63 : 0] a;
input [63 : 0] b;
input [5 : 0] operation;
output [63 : 0] result;
// synthesis translate_off
wire \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire sig00000149;
wire sig0000014a;
wire sig0000014b;
wire sig0000014c;
wire sig0000014d;
wire sig0000014e;
wire sig0000014f;
wire sig00000150;
wire sig00000151;
wire sig00000152;
wire sig00000153;
wire sig00000154;
wire sig00000155;
wire sig00000156;
wire sig00000157;
wire sig00000158;
wire sig00000159;
wire sig0000015a;
wire sig0000015b;
wire sig0000015c;
wire sig0000015d;
wire sig0000015e;
wire sig0000015f;
wire sig00000160;
wire sig00000161;
wire sig00000162;
wire sig00000163;
wire sig00000164;
wire sig00000165;
wire sig00000166;
wire sig00000167;
wire sig00000168;
wire sig00000169;
wire sig0000016a;
wire sig0000016b;
wire sig0000016c;
wire sig0000016d;
wire sig0000016e;
wire sig0000016f;
wire sig00000170;
wire sig00000171;
wire sig00000172;
wire sig00000173;
wire sig00000174;
wire sig00000175;
wire sig00000176;
wire sig00000177;
wire sig00000178;
wire sig00000179;
wire sig0000017a;
wire sig0000017b;
wire sig0000017c;
wire sig0000017d;
wire sig0000017e;
wire sig0000017f;
wire sig00000180;
wire sig00000181;
wire sig00000182;
wire sig00000183;
wire sig00000184;
wire sig00000185;
wire sig00000186;
wire sig00000187;
wire sig00000188;
wire sig00000189;
wire sig0000018a;
wire sig0000018b;
wire sig0000018c;
wire sig0000018d;
wire sig0000018e;
wire sig0000018f;
wire sig00000190;
wire sig00000191;
wire sig00000192;
wire sig00000193;
wire sig00000194;
wire sig00000195;
wire sig00000196;
wire sig00000197;
wire sig00000198;
wire sig00000199;
wire sig0000019a;
wire sig0000019b;
wire sig0000019c;
wire sig0000019d;
wire sig0000019e;
wire sig0000019f;
wire sig000001a0;
wire sig000001a1;
wire sig000001a2;
wire sig000001a3;
wire sig000001a4;
wire sig000001a5;
wire sig000001a6;
wire sig000001a7;
wire sig000001a8;
wire sig000001a9;
wire sig000001aa;
wire sig000001ab;
wire sig000001ac;
wire sig000001ad;
wire sig000001ae;
wire sig000001af;
wire sig000001b0;
wire sig000001b1;
wire sig000001b2;
wire sig000001b3;
wire sig000001b4;
wire sig000001b5;
wire sig000001b6;
wire sig000001b7;
wire sig000001b8;
wire sig000001b9;
wire sig000001ba;
wire sig000001bb;
wire sig000001bc;
wire sig000001bd;
wire sig000001be;
wire sig000001bf;
wire sig000001c0;
wire sig000001c1;
wire sig000001c2;
wire sig000001c3;
wire sig000001c4;
wire sig000001c5;
wire sig000001c6;
wire sig000001c7;
wire sig000001c8;
wire sig000001c9;
wire sig000001ca;
wire sig000001cb;
wire sig000001cc;
wire sig000001cd;
wire sig000001ce;
wire sig000001cf;
wire sig000001d0;
wire sig000001d1;
wire sig000001d2;
wire sig000001d3;
wire sig000001d4;
wire sig000001d5;
wire sig000001d6;
wire sig000001d7;
wire sig000001d8;
wire sig000001d9;
wire sig000001da;
wire sig000001db;
wire sig000001dc;
wire sig000001dd;
wire sig000001de;
wire sig000001df;
wire sig000001e0;
wire sig000001e1;
wire sig000001e2;
wire sig000001e3;
wire sig000001e4;
wire sig000001e5;
wire sig000001e6;
wire sig000001e7;
wire sig000001e8;
wire sig000001e9;
wire sig000001ea;
wire sig000001eb;
wire sig000001ec;
wire sig000001ed;
wire sig000001ee;
wire sig000001ef;
wire sig000001f0;
wire sig000001f1;
wire sig000001f2;
wire sig000001f3;
wire sig000001f4;
wire sig000001f5;
wire sig000001f6;
wire sig000001f7;
wire sig000001f8;
wire sig000001f9;
wire sig000001fa;
wire sig000001fb;
wire sig000001fc;
wire sig000001fd;
wire sig000001fe;
wire sig000001ff;
wire sig00000200;
wire sig00000201;
wire sig00000202;
wire sig00000203;
wire sig00000204;
wire sig00000205;
wire sig00000206;
wire sig00000207;
wire sig00000208;
wire sig00000209;
wire sig0000020a;
wire sig0000020b;
wire sig0000020c;
wire sig0000020d;
wire sig0000020e;
wire sig0000020f;
wire sig00000210;
wire sig00000211;
wire sig00000212;
wire sig00000213;
wire sig00000214;
wire sig00000215;
wire sig00000216;
wire sig00000217;
wire sig00000218;
wire sig00000219;
wire sig0000021a;
wire sig0000021b;
wire sig0000021c;
wire sig0000021d;
wire sig0000021e;
wire sig0000021f;
wire sig00000220;
wire sig00000221;
wire sig00000222;
wire sig00000223;
wire sig00000224;
wire sig00000225;
wire sig00000226;
wire sig00000227;
wire sig00000228;
wire sig00000229;
wire sig0000022a;
wire sig0000022b;
wire sig0000022c;
wire sig0000022d;
wire sig0000022e;
wire sig0000022f;
wire sig00000230;
wire sig00000231;
wire sig00000232;
wire sig00000233;
wire sig00000234;
wire sig00000235;
wire sig00000236;
wire sig00000237;
wire sig00000238;
wire sig00000239;
wire sig0000023a;
wire sig0000023b;
wire sig0000023c;
wire sig0000023d;
wire sig0000023e;
wire sig0000023f;
wire sig00000240;
wire sig00000241;
wire sig00000242;
wire sig00000243;
wire sig00000244;
wire sig00000245;
wire sig00000246;
wire sig00000247;
wire sig00000248;
wire sig00000249;
wire sig0000024a;
wire sig0000024b;
wire sig0000024c;
wire sig0000024d;
wire sig0000024e;
wire sig0000024f;
wire sig00000250;
wire sig00000251;
wire sig00000252;
wire sig00000253;
wire sig00000254;
wire sig00000255;
wire sig00000256;
wire sig00000257;
wire sig00000258;
wire sig00000259;
wire sig0000025a;
wire sig0000025b;
wire sig0000025c;
wire sig0000025d;
wire sig0000025e;
wire sig0000025f;
wire sig00000260;
wire sig00000261;
wire sig00000262;
wire sig00000263;
wire sig00000264;
wire sig00000265;
wire sig00000266;
wire sig00000267;
wire sig00000268;
wire sig00000269;
wire sig0000026a;
wire sig0000026b;
wire sig0000026c;
wire sig0000026d;
wire sig0000026e;
wire sig0000026f;
wire sig00000270;
wire sig00000271;
wire sig00000272;
wire sig00000273;
wire sig00000274;
wire sig00000275;
wire sig00000276;
wire sig00000277;
wire sig00000278;
wire sig00000279;
wire sig0000027a;
wire sig0000027b;
wire sig0000027c;
wire sig0000027d;
wire sig0000027e;
wire sig0000027f;
wire sig00000280;
wire sig00000281;
wire sig00000282;
wire sig00000283;
wire sig00000284;
wire sig00000285;
wire sig00000286;
wire sig00000287;
wire sig00000288;
wire sig00000289;
wire sig0000028a;
wire sig0000028b;
wire sig0000028c;
wire sig0000028d;
wire sig0000028e;
wire sig0000028f;
wire sig00000290;
wire sig00000291;
wire sig00000292;
wire sig00000293;
wire sig00000294;
wire sig00000295;
wire sig00000296;
wire sig00000297;
wire sig00000298;
wire sig00000299;
wire sig0000029a;
wire sig0000029b;
wire sig0000029c;
wire sig0000029d;
wire sig0000029e;
wire sig0000029f;
wire sig000002a0;
wire sig000002a1;
wire sig000002a2;
wire sig000002a3;
wire sig000002a4;
wire sig000002a5;
wire sig000002a6;
wire sig000002a7;
wire sig000002a8;
wire sig000002a9;
wire sig000002aa;
wire sig000002ab;
wire sig000002ac;
wire sig000002ad;
wire sig000002ae;
wire sig000002af;
wire sig000002b0;
wire sig000002b1;
wire sig000002b2;
wire sig000002b3;
wire sig000002b4;
wire sig000002b5;
wire sig000002b6;
wire sig000002b7;
wire sig000002b8;
wire sig000002b9;
wire sig000002ba;
wire sig000002bb;
wire sig000002bc;
wire sig000002bd;
wire sig000002be;
wire sig000002bf;
wire sig000002c0;
wire sig000002c1;
wire sig000002c2;
wire sig000002c3;
wire sig000002c4;
wire sig000002c5;
wire sig000002c6;
wire sig000002c7;
wire sig000002c8;
wire sig000002c9;
wire sig000002ca;
wire sig000002cb;
wire sig000002cc;
wire sig000002cd;
wire sig000002ce;
wire sig000002cf;
wire sig000002d0;
wire sig000002d1;
wire sig000002d2;
wire sig000002d3;
wire sig000002d4;
wire sig000002d5;
wire sig000002d6;
wire sig000002d7;
wire sig000002d8;
wire sig000002d9;
wire sig000002da;
wire sig000002db;
wire sig000002dc;
wire sig000002dd;
wire sig000002de;
wire sig000002df;
wire sig000002e0;
wire sig000002e1;
wire sig000002e2;
wire sig000002e3;
wire sig000002e4;
wire sig000002e5;
wire sig000002e6;
wire sig000002e7;
wire sig000002e8;
wire sig000002e9;
wire sig000002ea;
wire sig000002eb;
wire sig000002ec;
wire sig000002ed;
wire sig000002ee;
wire sig000002ef;
wire sig000002f0;
wire sig000002f1;
wire sig000002f2;
wire sig000002f3;
wire sig000002f4;
wire sig000002f5;
wire sig000002f6;
wire sig000002f7;
wire sig000002f8;
wire sig000002f9;
wire sig000002fa;
wire sig000002fb;
wire sig000002fc;
wire sig000002fd;
wire sig000002fe;
wire sig000002ff;
wire sig00000300;
wire sig00000301;
wire sig00000302;
wire sig00000303;
wire sig00000304;
wire sig00000305;
wire sig00000306;
wire sig00000307;
wire sig00000308;
wire sig00000309;
wire sig0000030a;
wire sig0000030b;
wire sig0000030c;
wire sig0000030d;
wire sig0000030e;
wire sig0000030f;
wire sig00000310;
wire sig00000311;
wire sig00000312;
wire sig00000313;
wire sig00000314;
wire sig00000315;
wire sig00000316;
wire sig00000317;
wire sig00000318;
wire sig00000319;
wire sig0000031a;
wire sig0000031b;
wire sig0000031c;
wire sig0000031d;
wire sig0000031e;
wire sig0000031f;
wire sig00000320;
wire sig00000321;
wire sig00000322;
wire sig00000323;
wire sig00000324;
wire sig00000325;
wire sig00000326;
wire sig00000327;
wire sig00000328;
wire sig00000329;
wire sig0000032a;
wire sig0000032b;
wire sig0000032c;
wire sig0000032d;
wire sig0000032e;
wire sig0000032f;
wire sig00000330;
wire sig00000331;
wire sig00000332;
wire sig00000333;
wire sig00000334;
wire sig00000335;
wire sig00000336;
wire sig00000337;
wire sig00000338;
wire sig00000339;
wire sig0000033a;
wire sig0000033b;
wire sig0000033c;
wire sig0000033d;
wire sig0000033e;
wire sig0000033f;
wire sig00000340;
wire sig00000341;
wire sig00000342;
wire sig00000343;
wire sig00000344;
wire sig00000345;
wire sig00000346;
wire sig00000347;
wire sig00000348;
wire sig00000349;
wire sig0000034a;
wire sig0000034b;
wire sig0000034c;
wire sig0000034d;
wire sig0000034e;
wire sig0000034f;
wire sig00000350;
wire sig00000351;
wire sig00000352;
wire sig00000353;
wire sig00000354;
wire sig00000355;
wire sig00000356;
wire sig00000357;
wire sig00000358;
wire sig00000359;
wire sig0000035a;
wire sig0000035b;
wire sig0000035c;
wire sig0000035d;
wire sig0000035e;
wire sig0000035f;
wire sig00000360;
wire sig00000361;
wire sig00000362;
wire sig00000363;
wire sig00000364;
wire sig00000365;
wire sig00000366;
wire sig00000367;
wire sig00000368;
wire sig00000369;
wire sig0000036a;
wire sig0000036b;
wire sig0000036c;
wire sig0000036d;
wire sig0000036e;
wire sig0000036f;
wire sig00000370;
wire sig00000371;
wire sig00000372;
wire sig00000373;
wire sig00000374;
wire sig00000375;
wire sig00000376;
wire sig00000377;
wire sig00000378;
wire sig00000379;
wire sig0000037a;
wire sig0000037b;
wire sig0000037c;
wire sig0000037d;
wire sig0000037e;
wire sig0000037f;
wire sig00000380;
wire sig00000381;
wire sig00000382;
wire sig00000383;
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wire sig00000793;
wire sig00000794;
wire sig00000795;
wire sig00000796;
wire sig00000797;
wire sig00000798;
wire sig00000799;
wire sig0000079a;
wire sig0000079b;
wire sig0000079c;
wire sig0000079d;
wire sig0000079e;
wire sig0000079f;
wire sig000007a0;
wire sig000007a1;
wire sig000007a2;
wire sig000007a3;
wire sig000007a4;
wire sig000007a5;
wire sig000007a6;
wire sig000007a7;
wire sig000007a8;
wire sig000007a9;
wire sig000007aa;
wire sig000007ab;
wire sig000007ac;
wire sig000007ad;
wire sig000007ae;
wire sig000007af;
wire sig000007b0;
wire sig000007b1;
wire sig000007b2;
wire sig000007b3;
wire sig000007b4;
wire sig000007b5;
wire sig000007b6;
wire sig000007b7;
wire sig000007b8;
wire sig000007b9;
wire sig000007ba;
wire sig000007bb;
wire sig000007bc;
wire sig000007bd;
wire sig000007be;
wire sig000007bf;
wire sig000007c0;
wire sig000007c1;
wire sig000007c2;
wire sig000007c3;
wire sig000007c4;
wire sig000007c5;
wire sig000007c6;
wire sig000007c7;
wire sig000007c8;
wire sig000007c9;
wire sig000007ca;
wire sig000007cb;
wire sig000007cc;
wire sig000007cd;
wire sig000007ce;
wire sig000007cf;
wire sig000007d0;
wire sig000007d1;
wire sig000007d2;
wire sig000007d3;
wire sig000007d4;
wire sig000007d5;
wire sig000007d6;
wire sig000007d7;
wire sig000007d8;
wire sig000007d9;
wire sig000007da;
wire sig000007db;
wire sig000007dc;
wire sig000007dd;
wire sig000007de;
wire sig000007df;
wire sig000007e0;
wire sig000007e1;
wire sig000007e2;
wire sig000007e3;
wire sig000007e4;
wire sig000007e5;
wire sig000007e6;
wire sig000007e7;
wire sig000007e8;
wire sig000007e9;
wire sig000007ea;
wire sig000007eb;
wire sig000007ec;
wire sig000007ed;
wire sig000007ee;
wire sig000007ef;
wire sig000007f0;
wire sig000007f1;
wire sig000007f2;
wire sig000007f3;
wire sig000007f4;
wire sig000007f5;
wire sig000007f6;
wire sig000007f7;
wire sig000007f8;
wire sig000007f9;
wire sig000007fa;
wire sig000007fb;
wire sig000007fc;
wire sig000007fd;
wire sig000007fe;
wire sig000007ff;
wire sig00000800;
wire sig00000801;
wire sig00000802;
wire sig00000803;
wire sig00000804;
wire sig00000805;
wire sig00000806;
wire sig00000807;
wire sig00000808;
wire sig00000809;
wire sig0000080a;
wire sig0000080b;
wire sig0000080c;
wire sig0000080d;
wire sig0000080e;
wire sig0000080f;
wire sig00000810;
wire sig00000811;
wire sig00000812;
wire sig00000813;
wire sig00000814;
wire sig00000815;
wire sig00000816;
wire sig00000817;
wire sig00000818;
wire sig00000819;
wire sig0000081a;
wire sig0000081b;
wire sig0000081c;
wire sig0000081d;
wire sig0000081e;
wire sig0000081f;
wire sig00000820;
wire sig00000821;
wire sig00000822;
wire sig00000823;
wire sig00000824;
wire sig00000825;
wire sig00000826;
wire sig00000827;
wire sig00000828;
wire sig00000829;
wire sig0000082a;
wire sig0000082b;
wire sig0000082c;
wire sig0000082d;
wire sig0000082e;
wire sig0000082f;
wire sig00000830;
wire sig00000831;
wire sig00000832;
wire sig00000833;
wire sig00000834;
wire sig00000835;
wire sig00000836;
wire sig00000837;
wire sig00000838;
wire sig00000839;
wire sig0000083a;
wire sig0000083b;
wire sig0000083c;
wire sig0000083d;
wire sig0000083e;
wire sig0000083f;
wire sig00000840;
wire sig00000841;
wire sig00000842;
wire sig00000843;
wire sig00000844;
wire sig00000845;
wire NLW_blk000003c6_O_UNCONNECTED;
wire NLW_blk000003cc_O_UNCONNECTED;
wire NLW_blk00000416_O_UNCONNECTED;
wire NLW_blk00000418_O_UNCONNECTED;
wire NLW_blk0000041a_O_UNCONNECTED;
wire NLW_blk0000041c_O_UNCONNECTED;
wire NLW_blk0000041e_O_UNCONNECTED;
wire NLW_blk00000420_O_UNCONNECTED;
wire NLW_blk00000422_O_UNCONNECTED;
wire NLW_blk00000424_O_UNCONNECTED;
wire NLW_blk00000426_O_UNCONNECTED;
wire NLW_blk00000428_O_UNCONNECTED;
wire NLW_blk0000042a_O_UNCONNECTED;
wire NLW_blk0000042c_O_UNCONNECTED;
wire NLW_blk0000042d_O_UNCONNECTED;
wire NLW_blk0000043b_O_UNCONNECTED;
wire NLW_blk0000043f_O_UNCONNECTED;
wire NLW_blk00000441_O_UNCONNECTED;
wire NLW_blk00000443_O_UNCONNECTED;
wire NLW_blk00000445_O_UNCONNECTED;
wire NLW_blk00000447_O_UNCONNECTED;
wire NLW_blk00000449_O_UNCONNECTED;
wire NLW_blk0000044b_O_UNCONNECTED;
wire NLW_blk0000044d_O_UNCONNECTED;
wire NLW_blk0000044f_O_UNCONNECTED;
wire NLW_blk00000451_O_UNCONNECTED;
wire NLW_blk00000452_O_UNCONNECTED;
wire NLW_blk000007d8_Q15_UNCONNECTED;
wire NLW_blk000007da_Q15_UNCONNECTED;
wire NLW_blk000007dc_Q15_UNCONNECTED;
wire NLW_blk000007de_Q15_UNCONNECTED;
wire NLW_blk000007e0_Q15_UNCONNECTED;
wire NLW_blk000007e2_Q15_UNCONNECTED;
wire NLW_blk000007e4_Q15_UNCONNECTED;
wire NLW_blk000007e6_Q15_UNCONNECTED;
wire NLW_blk000007e8_Q15_UNCONNECTED;
wire NLW_blk000007ea_Q15_UNCONNECTED;
wire NLW_blk000007ec_Q15_UNCONNECTED;
wire NLW_blk000007ee_Q15_UNCONNECTED;
wire NLW_blk000007f0_Q15_UNCONNECTED;
wire NLW_blk000007f2_Q15_UNCONNECTED;
wire NLW_blk000007f4_Q15_UNCONNECTED;
wire NLW_blk000007f6_Q15_UNCONNECTED;
wire NLW_blk000007f8_Q15_UNCONNECTED;
wire NLW_blk000007fa_Q15_UNCONNECTED;
wire NLW_blk000007fc_Q15_UNCONNECTED;
wire NLW_blk000007fe_Q15_UNCONNECTED;
wire NLW_blk00000800_Q15_UNCONNECTED;
wire NLW_blk00000802_Q15_UNCONNECTED;
wire NLW_blk00000804_Q15_UNCONNECTED;
wire NLW_blk00000806_Q15_UNCONNECTED;
wire NLW_blk00000808_Q15_UNCONNECTED;
wire NLW_blk0000080a_Q15_UNCONNECTED;
wire NLW_blk0000080c_Q15_UNCONNECTED;
wire NLW_blk0000080e_Q15_UNCONNECTED;
wire NLW_blk00000810_Q15_UNCONNECTED;
wire NLW_blk00000812_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000812_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000812_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000812_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000812_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000812_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000812_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000812_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000812_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000812_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000812_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000812_P<47>_UNCONNECTED ;
wire \NLW_blk00000812_P<46>_UNCONNECTED ;
wire \NLW_blk00000812_P<45>_UNCONNECTED ;
wire \NLW_blk00000812_P<44>_UNCONNECTED ;
wire \NLW_blk00000812_P<43>_UNCONNECTED ;
wire \NLW_blk00000812_P<42>_UNCONNECTED ;
wire \NLW_blk00000812_P<41>_UNCONNECTED ;
wire \NLW_blk00000812_P<40>_UNCONNECTED ;
wire \NLW_blk00000812_P<39>_UNCONNECTED ;
wire \NLW_blk00000812_P<38>_UNCONNECTED ;
wire \NLW_blk00000812_P<37>_UNCONNECTED ;
wire \NLW_blk00000812_P<36>_UNCONNECTED ;
wire \NLW_blk00000812_P<35>_UNCONNECTED ;
wire \NLW_blk00000812_P<34>_UNCONNECTED ;
wire \NLW_blk00000812_P<33>_UNCONNECTED ;
wire \NLW_blk00000812_P<32>_UNCONNECTED ;
wire \NLW_blk00000812_P<31>_UNCONNECTED ;
wire \NLW_blk00000812_P<30>_UNCONNECTED ;
wire \NLW_blk00000812_P<29>_UNCONNECTED ;
wire \NLW_blk00000812_P<28>_UNCONNECTED ;
wire \NLW_blk00000812_P<27>_UNCONNECTED ;
wire \NLW_blk00000812_P<26>_UNCONNECTED ;
wire \NLW_blk00000812_P<25>_UNCONNECTED ;
wire \NLW_blk00000812_P<24>_UNCONNECTED ;
wire \NLW_blk00000812_P<23>_UNCONNECTED ;
wire \NLW_blk00000812_P<22>_UNCONNECTED ;
wire \NLW_blk00000812_P<21>_UNCONNECTED ;
wire \NLW_blk00000812_P<20>_UNCONNECTED ;
wire \NLW_blk00000812_P<19>_UNCONNECTED ;
wire \NLW_blk00000812_P<18>_UNCONNECTED ;
wire \NLW_blk00000812_P<17>_UNCONNECTED ;
wire \NLW_blk00000812_P<16>_UNCONNECTED ;
wire \NLW_blk00000812_P<15>_UNCONNECTED ;
wire \NLW_blk00000812_P<14>_UNCONNECTED ;
wire \NLW_blk00000812_P<13>_UNCONNECTED ;
wire \NLW_blk00000812_P<12>_UNCONNECTED ;
wire \NLW_blk00000812_P<11>_UNCONNECTED ;
wire \NLW_blk00000812_P<10>_UNCONNECTED ;
wire \NLW_blk00000812_P<9>_UNCONNECTED ;
wire \NLW_blk00000812_P<8>_UNCONNECTED ;
wire \NLW_blk00000812_P<7>_UNCONNECTED ;
wire \NLW_blk00000812_P<6>_UNCONNECTED ;
wire \NLW_blk00000812_P<5>_UNCONNECTED ;
wire \NLW_blk00000812_P<4>_UNCONNECTED ;
wire \NLW_blk00000812_P<3>_UNCONNECTED ;
wire \NLW_blk00000812_P<2>_UNCONNECTED ;
wire \NLW_blk00000812_P<1>_UNCONNECTED ;
wire \NLW_blk00000812_P<0>_UNCONNECTED ;
wire NLW_blk00000813_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000813_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000813_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000813_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000813_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000813_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000813_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000813_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000813_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000813_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000813_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<0>_UNCONNECTED ;
wire NLW_blk00000814_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000814_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000814_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000814_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000814_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000814_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000814_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000814_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000814_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000814_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000814_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000814_P<0>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<0>_UNCONNECTED ;
wire [10 : 0] \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op ;
wire [51 : 0] \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op ;
assign
result[63] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op ,
result[62] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [10],
result[61] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [9],
result[60] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [8],
result[59] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [7],
result[58] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [6],
result[57] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [5],
result[56] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [4],
result[55] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [3],
result[54] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [2],
result[53] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [1],
result[52] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [0],
result[51] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [51],
result[50] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [50],
result[49] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [49],
result[48] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [48],
result[47] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [47],
result[46] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [46],
result[45] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [45],
result[44] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [44],
result[43] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [43],
result[42] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [42],
result[41] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [41],
result[40] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [40],
result[39] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [39],
result[38] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [38],
result[37] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [37],
result[36] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [36],
result[35] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [35],
result[34] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [34],
result[33] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [33],
result[32] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [32],
result[31] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [31],
result[30] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [30],
result[29] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [29],
result[28] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [28],
result[27] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [27],
result[26] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [26],
result[25] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [25],
result[24] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [24],
result[23] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [23],
result[22] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [22],
result[21] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [21],
result[20] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [20],
result[19] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [19],
result[18] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [18],
result[17] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [17],
result[16] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [16],
result[15] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [15],
result[14] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [14],
result[13] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [13],
result[12] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [12],
result[11] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [11],
result[10] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [10],
result[9] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [9],
result[8] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [8],
result[7] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [7],
result[6] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [6],
result[5] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [5],
result[4] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [4],
result[3] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [3],
result[2] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [2],
result[1] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [1],
result[0] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [0];
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig000006c3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(sig00000001),
.D(sig00000156),
.Q(sig0000023f)
);
FD #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.D(sig00000279),
.Q(sig0000023b)
);
FD #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.D(sig00000278),
.Q(sig0000023c)
);
FD #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.D(sig00000277),
.Q(sig0000023e)
);
FD #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.D(sig000002b6),
.Q(sig0000023a)
);
FD #(
.INIT ( 1'b0 ))
blk00000008 (
.C(clk),
.D(sig000002b7),
.Q(sig0000023d)
);
XORCY blk00000009 (
.CI(sig0000024b),
.LI(sig00000001),
.O(sig000002aa)
);
XORCY blk0000000a (
.CI(sig0000024d),
.LI(sig0000024c),
.O(sig000002b5)
);
MUXCY blk0000000b (
.CI(sig0000024d),
.DI(sig000002d1),
.S(sig0000024c),
.O(sig0000024b)
);
XORCY blk0000000c (
.CI(sig0000024f),
.LI(sig0000024e),
.O(sig000002b4)
);
MUXCY blk0000000d (
.CI(sig0000024f),
.DI(sig000002d0),
.S(sig0000024e),
.O(sig0000024d)
);
XORCY blk0000000e (
.CI(sig00000251),
.LI(sig00000250),
.O(sig000002b3)
);
MUXCY blk0000000f (
.CI(sig00000251),
.DI(sig000002cf),
.S(sig00000250),
.O(sig0000024f)
);
XORCY blk00000010 (
.CI(sig00000253),
.LI(sig00000252),
.O(sig000002b2)
);
MUXCY blk00000011 (
.CI(sig00000253),
.DI(sig000002ce),
.S(sig00000252),
.O(sig00000251)
);
XORCY blk00000012 (
.CI(sig00000255),
.LI(sig00000254),
.O(sig000002b1)
);
MUXCY blk00000013 (
.CI(sig00000255),
.DI(sig000002cd),
.S(sig00000254),
.O(sig00000253)
);
XORCY blk00000014 (
.CI(sig00000257),
.LI(sig00000256),
.O(sig000002b0)
);
MUXCY blk00000015 (
.CI(sig00000257),
.DI(sig000002cc),
.S(sig00000256),
.O(sig00000255)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000016 (
.I0(sig000002cc),
.I1(sig00000189),
.O(sig00000256)
);
XORCY blk00000017 (
.CI(sig00000259),
.LI(sig00000258),
.O(sig000002af)
);
MUXCY blk00000018 (
.CI(sig00000259),
.DI(sig000002cb),
.S(sig00000258),
.O(sig00000257)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000019 (
.I0(sig000002cb),
.I1(sig00000188),
.O(sig00000258)
);
XORCY blk0000001a (
.CI(sig0000025b),
.LI(sig0000025a),
.O(sig000002ae)
);
MUXCY blk0000001b (
.CI(sig0000025b),
.DI(sig000002ca),
.S(sig0000025a),
.O(sig00000259)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000001c (
.I0(sig000002ca),
.I1(sig00000187),
.O(sig0000025a)
);
XORCY blk0000001d (
.CI(sig0000025d),
.LI(sig0000025c),
.O(sig000002ad)
);
MUXCY blk0000001e (
.CI(sig0000025d),
.DI(sig000002c9),
.S(sig0000025c),
.O(sig0000025b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000001f (
.I0(sig000002c9),
.I1(sig00000186),
.O(sig0000025c)
);
XORCY blk00000020 (
.CI(sig0000025f),
.LI(sig0000025e),
.O(sig000002ac)
);
MUXCY blk00000021 (
.CI(sig0000025f),
.DI(sig000002c8),
.S(sig0000025e),
.O(sig0000025d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000022 (
.I0(sig000002c8),
.I1(sig0000011c),
.O(sig0000025e)
);
XORCY blk00000023 (
.CI(sig00000001),
.LI(sig00000260),
.O(sig000002ab)
);
MUXCY blk00000024 (
.CI(sig00000001),
.DI(sig000002c7),
.S(sig00000260),
.O(sig0000025f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000025 (
.I0(sig000002c7),
.I1(sig0000011d),
.O(sig00000260)
);
XORCY blk00000026 (
.CI(sig00000261),
.LI(sig00000001),
.O(sig0000029e)
);
XORCY blk00000027 (
.CI(sig00000263),
.LI(sig00000262),
.O(sig0000029d)
);
MUXCY blk00000028 (
.CI(sig00000263),
.DI(b[62]),
.S(sig00000262),
.O(sig00000261)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000029 (
.I0(b[62]),
.I1(a[62]),
.O(sig00000262)
);
XORCY blk0000002a (
.CI(sig00000265),
.LI(sig00000264),
.O(sig0000029c)
);
MUXCY blk0000002b (
.CI(sig00000265),
.DI(b[61]),
.S(sig00000264),
.O(sig00000263)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000002c (
.I0(b[61]),
.I1(a[61]),
.O(sig00000264)
);
XORCY blk0000002d (
.CI(sig00000267),
.LI(sig00000266),
.O(sig0000029b)
);
MUXCY blk0000002e (
.CI(sig00000267),
.DI(b[60]),
.S(sig00000266),
.O(sig00000265)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000002f (
.I0(b[60]),
.I1(a[60]),
.O(sig00000266)
);
XORCY blk00000030 (
.CI(sig00000269),
.LI(sig00000268),
.O(sig0000029a)
);
MUXCY blk00000031 (
.CI(sig00000269),
.DI(b[59]),
.S(sig00000268),
.O(sig00000267)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000032 (
.I0(b[59]),
.I1(a[59]),
.O(sig00000268)
);
XORCY blk00000033 (
.CI(sig0000026b),
.LI(sig0000026a),
.O(sig00000299)
);
MUXCY blk00000034 (
.CI(sig0000026b),
.DI(b[58]),
.S(sig0000026a),
.O(sig00000269)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000035 (
.I0(b[58]),
.I1(a[58]),
.O(sig0000026a)
);
XORCY blk00000036 (
.CI(sig0000026d),
.LI(sig0000026c),
.O(sig00000298)
);
MUXCY blk00000037 (
.CI(sig0000026d),
.DI(b[57]),
.S(sig0000026c),
.O(sig0000026b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000038 (
.I0(b[57]),
.I1(a[57]),
.O(sig0000026c)
);
XORCY blk00000039 (
.CI(sig0000026f),
.LI(sig0000026e),
.O(sig00000297)
);
MUXCY blk0000003a (
.CI(sig0000026f),
.DI(b[56]),
.S(sig0000026e),
.O(sig0000026d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000003b (
.I0(b[56]),
.I1(a[56]),
.O(sig0000026e)
);
XORCY blk0000003c (
.CI(sig00000271),
.LI(sig00000270),
.O(sig00000296)
);
MUXCY blk0000003d (
.CI(sig00000271),
.DI(b[55]),
.S(sig00000270),
.O(sig0000026f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000003e (
.I0(b[55]),
.I1(a[55]),
.O(sig00000270)
);
XORCY blk0000003f (
.CI(sig00000273),
.LI(sig00000272),
.O(sig00000295)
);
MUXCY blk00000040 (
.CI(sig00000273),
.DI(b[54]),
.S(sig00000272),
.O(sig00000271)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000041 (
.I0(b[54]),
.I1(a[54]),
.O(sig00000272)
);
XORCY blk00000042 (
.CI(sig00000275),
.LI(sig00000274),
.O(sig00000294)
);
MUXCY blk00000043 (
.CI(sig00000275),
.DI(b[53]),
.S(sig00000274),
.O(sig00000273)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000044 (
.I0(b[53]),
.I1(a[53]),
.O(sig00000274)
);
MUXCY blk00000045 (
.CI(sig00000001),
.DI(b[52]),
.S(sig00000276),
.O(sig00000275)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000046 (
.I0(b[52]),
.I1(a[52]),
.O(sig00000276)
);
FDE #(
.INIT ( 1'b0 ))
blk00000047 (
.C(clk),
.CE(sig00000001),
.D(sig000002a1),
.Q(sig000002b6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000048 (
.C(clk),
.CE(sig00000001),
.D(sig000002a2),
.Q(sig000002b7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000049 (
.C(clk),
.CE(sig00000001),
.D(a[63]),
.Q(sig000002f5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004a (
.C(clk),
.CE(sig00000001),
.D(sig000002a9),
.Q(sig000002f4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004b (
.C(clk),
.CE(sig00000001),
.D(sig000002aa),
.Q(sig000002b8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004c (
.C(clk),
.CE(sig00000001),
.D(sig00000157),
.Q(sig0000027d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004d (
.C(clk),
.CE(sig00000001),
.D(sig0000027d),
.Q(sig0000030c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004e (
.C(clk),
.CE(sig00000001),
.D(sig000002a0),
.Q(sig0000027e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004f (
.C(clk),
.CE(sig00000001),
.D(sig0000027e),
.Q(sig0000022b)
);
FD #(
.INIT ( 1'b0 ))
blk00000050 (
.C(clk),
.D(sig000001c2),
.Q(sig0000027f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000051 (
.C(clk),
.CE(sig00000001),
.D(sig0000022d),
.Q(sig000002f3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000052 (
.C(clk),
.CE(sig00000001),
.D(sig00000291),
.Q(sig000002f2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000053 (
.C(clk),
.CE(sig00000001),
.D(sig00000293),
.Q(sig000002f1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000054 (
.C(clk),
.CE(sig00000001),
.D(sig00000292),
.Q(sig000002ef)
);
FDE #(
.INIT ( 1'b0 ))
blk00000055 (
.C(clk),
.CE(sig00000001),
.D(sig00000290),
.Q(sig000004b6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000056 (
.C(clk),
.CE(sig00000001),
.D(sig000002a6),
.Q(sig000002ee)
);
FDE #(
.INIT ( 1'b0 ))
blk00000057 (
.C(clk),
.CE(sig00000001),
.D(sig000002a7),
.Q(sig000002f0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000058 (
.C(clk),
.CE(sig00000001),
.D(sig000002a8),
.Q(sig000002ed)
);
FDE #(
.INIT ( 1'b0 ))
blk00000059 (
.C(clk),
.CE(sig00000001),
.D(sig0000029f),
.Q(sig000002c5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005a (
.C(clk),
.CE(sig00000001),
.D(sig0000030e),
.Q(sig000002c4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005b (
.C(clk),
.CE(sig00000001),
.D(sig00000283),
.Q(sig0000030f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005c (
.C(clk),
.CE(sig00000001),
.D(sig00000282),
.Q(sig00000310)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005d (
.C(clk),
.CE(sig00000001),
.D(sig00000281),
.Q(sig00000312)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005e (
.C(clk),
.CE(sig00000001),
.D(sig00000280),
.Q(sig00000313)
);
MUXCY blk0000005f (
.CI(sig00000328),
.DI(sig000006c3),
.S(sig00000326),
.O(sig00000327)
);
MUXCY blk00000060 (
.CI(sig00000329),
.DI(sig000006c3),
.S(sig0000031e),
.O(sig00000328)
);
MUXCY blk00000061 (
.CI(sig0000032a),
.DI(sig000006c3),
.S(sig0000031f),
.O(sig00000329)
);
MUXCY blk00000062 (
.CI(sig0000032b),
.DI(sig000006c3),
.S(sig00000320),
.O(sig0000032a)
);
MUXCY blk00000063 (
.CI(sig0000032c),
.DI(sig000006c3),
.S(sig00000321),
.O(sig0000032b)
);
MUXCY blk00000064 (
.CI(sig0000032d),
.DI(sig000006c3),
.S(sig00000322),
.O(sig0000032c)
);
MUXCY blk00000065 (
.CI(sig0000032e),
.DI(sig000006c3),
.S(sig00000323),
.O(sig0000032d)
);
MUXCY blk00000066 (
.CI(sig0000032f),
.DI(sig000006c3),
.S(sig00000324),
.O(sig0000032e)
);
MUXCY blk00000067 (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig00000325),
.O(sig0000032f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000068 (
.C(clk),
.CE(sig00000001),
.D(sig00000327),
.Q(sig00000311)
);
MUXCY blk00000069 (
.CI(sig00000331),
.DI(sig000006c3),
.S(sig0000031d),
.O(sig00000330)
);
MUXCY blk0000006a (
.CI(sig00000332),
.DI(sig000006c3),
.S(sig00000315),
.O(sig00000331)
);
MUXCY blk0000006b (
.CI(sig00000333),
.DI(sig000006c3),
.S(sig00000316),
.O(sig00000332)
);
MUXCY blk0000006c (
.CI(sig00000334),
.DI(sig000006c3),
.S(sig00000317),
.O(sig00000333)
);
MUXCY blk0000006d (
.CI(sig00000335),
.DI(sig000006c3),
.S(sig00000318),
.O(sig00000334)
);
MUXCY blk0000006e (
.CI(sig00000336),
.DI(sig000006c3),
.S(sig00000319),
.O(sig00000335)
);
MUXCY blk0000006f (
.CI(sig00000337),
.DI(sig000006c3),
.S(sig0000031a),
.O(sig00000336)
);
MUXCY blk00000070 (
.CI(sig00000338),
.DI(sig000006c3),
.S(sig0000031b),
.O(sig00000337)
);
MUXCY blk00000071 (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig0000031c),
.O(sig00000338)
);
FDE #(
.INIT ( 1'b0 ))
blk00000072 (
.C(clk),
.CE(sig00000001),
.D(sig00000330),
.Q(sig00000314)
);
MUXCY blk00000073 (
.CI(sig0000037a),
.DI(sig00000359),
.S(sig0000035a),
.O(sig00000379)
);
MUXCY blk00000074 (
.CI(sig0000037b),
.DI(sig0000035b),
.S(sig0000035c),
.O(sig0000037a)
);
MUXCY blk00000075 (
.CI(sig0000037c),
.DI(sig0000035d),
.S(sig0000035e),
.O(sig0000037b)
);
MUXCY blk00000076 (
.CI(sig0000037d),
.DI(sig0000035f),
.S(sig00000360),
.O(sig0000037c)
);
MUXCY blk00000077 (
.CI(sig0000037e),
.DI(sig00000361),
.S(sig00000362),
.O(sig0000037d)
);
MUXCY blk00000078 (
.CI(sig0000037f),
.DI(sig00000363),
.S(sig00000364),
.O(sig0000037e)
);
MUXCY blk00000079 (
.CI(sig00000380),
.DI(sig00000365),
.S(sig00000366),
.O(sig0000037f)
);
MUXCY blk0000007a (
.CI(sig00000381),
.DI(sig00000367),
.S(sig00000368),
.O(sig00000380)
);
MUXCY blk0000007b (
.CI(sig00000382),
.DI(sig00000369),
.S(sig0000036a),
.O(sig00000381)
);
MUXCY blk0000007c (
.CI(sig00000383),
.DI(sig0000036b),
.S(sig0000036c),
.O(sig00000382)
);
MUXCY blk0000007d (
.CI(sig00000384),
.DI(sig0000036d),
.S(sig0000036e),
.O(sig00000383)
);
MUXCY blk0000007e (
.CI(sig00000385),
.DI(sig0000036f),
.S(sig00000370),
.O(sig00000384)
);
MUXCY blk0000007f (
.CI(sig00000386),
.DI(sig00000371),
.S(sig00000372),
.O(sig00000385)
);
MUXCY blk00000080 (
.CI(sig00000387),
.DI(sig00000373),
.S(sig00000374),
.O(sig00000386)
);
MUXCY blk00000081 (
.CI(sig00000388),
.DI(sig00000375),
.S(sig00000376),
.O(sig00000387)
);
MUXCY blk00000082 (
.CI(sig000006c3),
.DI(sig00000377),
.S(sig00000378),
.O(sig00000388)
);
FDE #(
.INIT ( 1'b0 ))
blk00000083 (
.C(clk),
.CE(sig00000001),
.D(sig00000379),
.Q(sig0000027b)
);
MUXCY blk00000084 (
.CI(sig0000038a),
.DI(sig00000339),
.S(sig0000033a),
.O(sig00000389)
);
MUXCY blk00000085 (
.CI(sig0000038b),
.DI(sig0000033b),
.S(sig0000033c),
.O(sig0000038a)
);
MUXCY blk00000086 (
.CI(sig0000038c),
.DI(sig0000033d),
.S(sig0000033e),
.O(sig0000038b)
);
MUXCY blk00000087 (
.CI(sig0000038d),
.DI(sig0000033f),
.S(sig00000340),
.O(sig0000038c)
);
MUXCY blk00000088 (
.CI(sig0000038e),
.DI(sig00000341),
.S(sig00000342),
.O(sig0000038d)
);
MUXCY blk00000089 (
.CI(sig0000038f),
.DI(sig00000343),
.S(sig00000344),
.O(sig0000038e)
);
MUXCY blk0000008a (
.CI(sig00000390),
.DI(sig00000345),
.S(sig00000346),
.O(sig0000038f)
);
MUXCY blk0000008b (
.CI(sig00000391),
.DI(sig00000347),
.S(sig00000348),
.O(sig00000390)
);
MUXCY blk0000008c (
.CI(sig00000392),
.DI(sig00000349),
.S(sig0000034a),
.O(sig00000391)
);
MUXCY blk0000008d (
.CI(sig00000393),
.DI(sig0000034b),
.S(sig0000034c),
.O(sig00000392)
);
MUXCY blk0000008e (
.CI(sig00000394),
.DI(sig0000034d),
.S(sig0000034e),
.O(sig00000393)
);
MUXCY blk0000008f (
.CI(sig00000395),
.DI(sig0000034f),
.S(sig00000350),
.O(sig00000394)
);
MUXCY blk00000090 (
.CI(sig00000396),
.DI(sig00000351),
.S(sig00000352),
.O(sig00000395)
);
MUXCY blk00000091 (
.CI(sig00000397),
.DI(sig00000353),
.S(sig00000354),
.O(sig00000396)
);
MUXCY blk00000092 (
.CI(sig00000398),
.DI(sig00000355),
.S(sig00000356),
.O(sig00000397)
);
MUXCY blk00000093 (
.CI(sig000006c3),
.DI(sig00000357),
.S(sig00000358),
.O(sig00000398)
);
FDE #(
.INIT ( 1'b0 ))
blk00000094 (
.C(clk),
.CE(sig00000001),
.D(sig00000389),
.Q(sig0000027a)
);
MUXCY blk00000095 (
.CI(sig000003a5),
.DI(sig000006c3),
.S(sig00000399),
.O(sig000003a4)
);
MUXCY blk00000096 (
.CI(sig000003a6),
.DI(sig000006c3),
.S(sig0000039a),
.O(sig000003a5)
);
MUXCY blk00000097 (
.CI(sig000003a7),
.DI(sig000006c3),
.S(sig0000039b),
.O(sig000003a6)
);
MUXCY blk00000098 (
.CI(sig000003a8),
.DI(sig000006c3),
.S(sig0000039c),
.O(sig000003a7)
);
MUXCY blk00000099 (
.CI(sig000003a9),
.DI(sig000006c3),
.S(sig0000039d),
.O(sig000003a8)
);
MUXCY blk0000009a (
.CI(sig000003aa),
.DI(sig000006c3),
.S(sig0000039e),
.O(sig000003a9)
);
MUXCY blk0000009b (
.CI(sig000003ab),
.DI(sig000006c3),
.S(sig0000039f),
.O(sig000003aa)
);
MUXCY blk0000009c (
.CI(sig000003ac),
.DI(sig000006c3),
.S(sig000003a0),
.O(sig000003ab)
);
MUXCY blk0000009d (
.CI(sig000003ad),
.DI(sig000006c3),
.S(sig000003a1),
.O(sig000003ac)
);
MUXCY blk0000009e (
.CI(sig000003ae),
.DI(sig000006c3),
.S(sig000003a2),
.O(sig000003ad)
);
MUXCY blk0000009f (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig000003a3),
.O(sig000003ae)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a0 (
.C(clk),
.CE(sig00000001),
.D(sig000003a4),
.Q(sig0000027c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a1 (
.C(clk),
.CE(sig00000001),
.D(sig000002b5),
.Q(sig000002c3)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a2 (
.C(clk),
.CE(sig00000001),
.D(sig000002b4),
.Q(sig000002c2)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a3 (
.C(clk),
.CE(sig00000001),
.D(sig000002b3),
.Q(sig000002c1)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a4 (
.C(clk),
.CE(sig00000001),
.D(sig000002b2),
.Q(sig000002c0)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a5 (
.C(clk),
.CE(sig00000001),
.D(sig000002b1),
.Q(sig000002bf)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a6 (
.C(clk),
.CE(sig00000001),
.D(sig000002b0),
.Q(sig000002be)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a7 (
.C(clk),
.CE(sig00000001),
.D(sig000002af),
.Q(sig000002bd)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a8 (
.C(clk),
.CE(sig00000001),
.D(sig000002ae),
.Q(sig000002bc)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a9 (
.C(clk),
.CE(sig00000001),
.D(sig000002ad),
.Q(sig000002bb)
);
FDE #(
.INIT ( 1'b0 ))
blk000000aa (
.C(clk),
.CE(sig00000001),
.D(sig000002ac),
.Q(sig000002ba)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ab (
.C(clk),
.CE(sig00000001),
.D(sig000002ab),
.Q(sig000002b9)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ac (
.C(clk),
.CE(sig00000001),
.D(b[62]),
.Q(sig00000300)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ad (
.C(clk),
.CE(sig00000001),
.D(b[61]),
.Q(sig000002ff)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ae (
.C(clk),
.CE(sig00000001),
.D(b[60]),
.Q(sig000002fe)
);
FDE #(
.INIT ( 1'b0 ))
blk000000af (
.C(clk),
.CE(sig00000001),
.D(b[59]),
.Q(sig000002fd)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b0 (
.C(clk),
.CE(sig00000001),
.D(b[58]),
.Q(sig000002fc)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b1 (
.C(clk),
.CE(sig00000001),
.D(b[57]),
.Q(sig000002fb)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b2 (
.C(clk),
.CE(sig00000001),
.D(b[56]),
.Q(sig000002fa)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b3 (
.C(clk),
.CE(sig00000001),
.D(b[55]),
.Q(sig000002f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b4 (
.C(clk),
.CE(sig00000001),
.D(b[54]),
.Q(sig000002f8)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b5 (
.C(clk),
.CE(sig00000001),
.D(b[53]),
.Q(sig000002f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b6 (
.C(clk),
.CE(sig00000001),
.D(b[52]),
.Q(sig000002f6)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b7 (
.C(clk),
.CE(sig00000001),
.D(a[62]),
.Q(sig0000030b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b8 (
.C(clk),
.CE(sig00000001),
.D(a[61]),
.Q(sig0000030a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b9 (
.C(clk),
.CE(sig00000001),
.D(a[60]),
.Q(sig00000309)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ba (
.C(clk),
.CE(sig00000001),
.D(a[59]),
.Q(sig00000308)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bb (
.C(clk),
.CE(sig00000001),
.D(a[58]),
.Q(sig00000307)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bc (
.C(clk),
.CE(sig00000001),
.D(a[57]),
.Q(sig00000306)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.CE(sig00000001),
.D(a[56]),
.Q(sig00000305)
);
FDE #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.CE(sig00000001),
.D(a[55]),
.Q(sig00000304)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.CE(sig00000001),
.D(a[54]),
.Q(sig00000303)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.CE(sig00000001),
.D(a[53]),
.Q(sig00000302)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.CE(sig00000001),
.D(a[52]),
.Q(sig00000301)
);
FD #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.D(sig0000029e),
.Q(sig0000024a)
);
FD #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.D(sig0000029d),
.Q(sig00000249)
);
FD #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.D(sig0000029c),
.Q(sig00000248)
);
FD #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.D(sig0000029b),
.Q(sig00000247)
);
FD #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.D(sig0000029a),
.Q(sig00000246)
);
FD #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.D(sig00000299),
.Q(sig00000245)
);
FD #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.D(sig00000298),
.Q(sig00000244)
);
FD #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.D(sig00000297),
.Q(sig00000243)
);
FD #(
.INIT ( 1'b0 ))
blk000000ca (
.C(clk),
.D(sig00000296),
.Q(sig00000242)
);
FD #(
.INIT ( 1'b0 ))
blk000000cb (
.C(clk),
.D(sig00000295),
.Q(sig00000241)
);
FD #(
.INIT ( 1'b0 ))
blk000000cc (
.C(clk),
.D(sig00000294),
.Q(sig00000240)
);
FD #(
.INIT ( 1'b0 ))
blk000000cd (
.C(clk),
.D(sig000002a5),
.Q(sig000003b0)
);
FD #(
.INIT ( 1'b0 ))
blk000000ce (
.C(clk),
.D(sig000002a4),
.Q(sig000003af)
);
FD #(
.INIT ( 1'b0 ))
blk000000cf (
.C(clk),
.D(sig000002a3),
.Q(sig000003b1)
);
XORCY blk000000d0 (
.CI(sig000003b2),
.LI(sig000006c3),
.O(sig000002e9)
);
XORCY blk000000d1 (
.CI(sig000003b3),
.LI(sig0000028e),
.O(sig000002e8)
);
MUXCY blk000000d2 (
.CI(sig000003b3),
.DI(sig000006c3),
.S(sig0000028e),
.O(sig000003b2)
);
XORCY blk000000d3 (
.CI(sig000003b4),
.LI(sig0000028d),
.O(sig000002e7)
);
MUXCY blk000000d4 (
.CI(sig000003b4),
.DI(sig000006c3),
.S(sig0000028d),
.O(sig000003b3)
);
XORCY blk000000d5 (
.CI(sig000003b5),
.LI(sig0000028c),
.O(sig000002e6)
);
MUXCY blk000000d6 (
.CI(sig000003b5),
.DI(sig000006c3),
.S(sig0000028c),
.O(sig000003b4)
);
XORCY blk000000d7 (
.CI(sig000003b6),
.LI(sig0000028b),
.O(sig000002e5)
);
MUXCY blk000000d8 (
.CI(sig000003b6),
.DI(sig000006c3),
.S(sig0000028b),
.O(sig000003b5)
);
XORCY blk000000d9 (
.CI(sig000003b7),
.LI(sig0000028a),
.O(sig000002e4)
);
MUXCY blk000000da (
.CI(sig000003b7),
.DI(sig000006c3),
.S(sig0000028a),
.O(sig000003b6)
);
XORCY blk000000db (
.CI(sig000003b8),
.LI(sig00000289),
.O(sig000002e3)
);
MUXCY blk000000dc (
.CI(sig000003b8),
.DI(sig000006c3),
.S(sig00000289),
.O(sig000003b7)
);
XORCY blk000000dd (
.CI(sig000003b9),
.LI(sig00000288),
.O(sig000002e2)
);
MUXCY blk000000de (
.CI(sig000003b9),
.DI(sig000006c3),
.S(sig00000288),
.O(sig000003b8)
);
XORCY blk000000df (
.CI(sig000003ba),
.LI(sig00000287),
.O(sig000002e1)
);
MUXCY blk000000e0 (
.CI(sig000003ba),
.DI(sig000006c3),
.S(sig00000287),
.O(sig000003b9)
);
XORCY blk000000e1 (
.CI(sig000003bb),
.LI(sig00000286),
.O(sig000002e0)
);
MUXCY blk000000e2 (
.CI(sig000003bb),
.DI(sig000006c3),
.S(sig00000286),
.O(sig000003ba)
);
XORCY blk000000e3 (
.CI(sig000003bc),
.LI(sig00000285),
.O(sig000002df)
);
MUXCY blk000000e4 (
.CI(sig000003bc),
.DI(sig000006c3),
.S(sig00000285),
.O(sig000003bb)
);
XORCY blk000000e5 (
.CI(sig000006c3),
.LI(sig00000284),
.O(sig000002de)
);
MUXCY blk000000e6 (
.CI(sig000006c3),
.DI(sig00000001),
.S(sig00000284),
.O(sig000003bc)
);
FD #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.D(sig000002e9),
.Q(sig000002dd)
);
FD #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.D(sig000002e8),
.Q(sig000002dc)
);
FD #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.D(sig000002e7),
.Q(sig000002db)
);
FD #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.D(sig000002e6),
.Q(sig000002da)
);
FD #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.D(sig000002e5),
.Q(sig000002d9)
);
FD #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.D(sig000002e4),
.Q(sig000002d8)
);
FD #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.D(sig000002e3),
.Q(sig000002d7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.D(sig000002e2),
.Q(sig000002d6)
);
FD #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.D(sig000002e1),
.Q(sig000002d5)
);
FD #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.D(sig000002e0),
.Q(sig000002d4)
);
FD #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.D(sig000002df),
.Q(sig000002d3)
);
FD #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.D(sig000002de),
.Q(sig000002d2)
);
FD #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.D(sig0000028f),
.Q(sig000003bd)
);
FD #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.D(sig000003c8),
.Q(sig00000239)
);
FD #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.D(sig000003c7),
.Q(sig00000238)
);
FD #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.D(sig000003c6),
.Q(sig00000237)
);
FD #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.D(sig000003c5),
.Q(sig00000236)
);
FD #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.D(sig000003c4),
.Q(sig00000235)
);
FD #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.D(sig000003c3),
.Q(sig00000234)
);
FD #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.D(sig000003c2),
.Q(sig00000233)
);
FD #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.D(sig000003c1),
.Q(sig00000232)
);
FD #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.D(sig000003c0),
.Q(sig00000231)
);
FD #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.D(sig000003bf),
.Q(sig00000230)
);
FD #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.D(sig000003be),
.Q(sig0000022f)
);
FD #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.D(sig000002c3),
.Q(sig000003c8)
);
FD #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.D(sig000002c2),
.Q(sig000003c7)
);
FD #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.D(sig000002c1),
.Q(sig000003c6)
);
FD #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.D(sig000002c0),
.Q(sig000003c5)
);
FD #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.D(sig000002bf),
.Q(sig000003c4)
);
FD #(
.INIT ( 1'b0 ))
blk00000104 (
.C(clk),
.D(sig000002be),
.Q(sig000003c3)
);
FD #(
.INIT ( 1'b0 ))
blk00000105 (
.C(clk),
.D(sig000002bd),
.Q(sig000003c2)
);
FD #(
.INIT ( 1'b0 ))
blk00000106 (
.C(clk),
.D(sig000002bc),
.Q(sig000003c1)
);
FD #(
.INIT ( 1'b0 ))
blk00000107 (
.C(clk),
.D(sig000002bb),
.Q(sig000003c0)
);
FD #(
.INIT ( 1'b0 ))
blk00000108 (
.C(clk),
.D(sig000002ba),
.Q(sig000003bf)
);
FD #(
.INIT ( 1'b0 ))
blk00000109 (
.C(clk),
.D(sig000002b9),
.Q(sig000003be)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010a (
.C(clk),
.CE(sig00000001),
.D(b[51]),
.Q(sig000001f6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.CE(sig00000001),
.D(b[50]),
.Q(sig000001f5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.CE(sig00000001),
.D(b[49]),
.Q(sig000001f4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.CE(sig00000001),
.D(b[48]),
.Q(sig000001f3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010e (
.C(clk),
.CE(sig00000001),
.D(b[47]),
.Q(sig000001f2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010f (
.C(clk),
.CE(sig00000001),
.D(b[46]),
.Q(sig000001f1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000110 (
.C(clk),
.CE(sig00000001),
.D(b[45]),
.Q(sig000001f0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000111 (
.C(clk),
.CE(sig00000001),
.D(b[44]),
.Q(sig000001ef)
);
FDE #(
.INIT ( 1'b0 ))
blk00000112 (
.C(clk),
.CE(sig00000001),
.D(b[43]),
.Q(sig000001ee)
);
FDE #(
.INIT ( 1'b0 ))
blk00000113 (
.C(clk),
.CE(sig00000001),
.D(b[42]),
.Q(sig000001ed)
);
FDE #(
.INIT ( 1'b0 ))
blk00000114 (
.C(clk),
.CE(sig00000001),
.D(b[41]),
.Q(sig000001ec)
);
FDE #(
.INIT ( 1'b0 ))
blk00000115 (
.C(clk),
.CE(sig00000001),
.D(b[40]),
.Q(sig000001eb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000116 (
.C(clk),
.CE(sig00000001),
.D(b[39]),
.Q(sig000001ea)
);
FDE #(
.INIT ( 1'b0 ))
blk00000117 (
.C(clk),
.CE(sig00000001),
.D(b[38]),
.Q(sig000001e9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000118 (
.C(clk),
.CE(sig00000001),
.D(b[37]),
.Q(sig000001e8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000119 (
.C(clk),
.CE(sig00000001),
.D(b[36]),
.Q(sig000001e7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011a (
.C(clk),
.CE(sig00000001),
.D(b[35]),
.Q(sig000001e6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011b (
.C(clk),
.CE(sig00000001),
.D(b[34]),
.Q(sig000001e5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011c (
.C(clk),
.CE(sig00000001),
.D(b[33]),
.Q(sig000001e4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011d (
.C(clk),
.CE(sig00000001),
.D(b[32]),
.Q(sig000001e3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011e (
.C(clk),
.CE(sig00000001),
.D(b[31]),
.Q(sig000001e2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011f (
.C(clk),
.CE(sig00000001),
.D(b[30]),
.Q(sig000001e1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000120 (
.C(clk),
.CE(sig00000001),
.D(b[29]),
.Q(sig000001e0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000121 (
.C(clk),
.CE(sig00000001),
.D(b[28]),
.Q(sig000001df)
);
FDE #(
.INIT ( 1'b0 ))
blk00000122 (
.C(clk),
.CE(sig00000001),
.D(b[27]),
.Q(sig000001de)
);
FDE #(
.INIT ( 1'b0 ))
blk00000123 (
.C(clk),
.CE(sig00000001),
.D(b[26]),
.Q(sig000001dd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000124 (
.C(clk),
.CE(sig00000001),
.D(b[25]),
.Q(sig000001dc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000125 (
.C(clk),
.CE(sig00000001),
.D(b[24]),
.Q(sig000001db)
);
FDE #(
.INIT ( 1'b0 ))
blk00000126 (
.C(clk),
.CE(sig00000001),
.D(b[23]),
.Q(sig000001da)
);
FDE #(
.INIT ( 1'b0 ))
blk00000127 (
.C(clk),
.CE(sig00000001),
.D(b[22]),
.Q(sig000001d9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000128 (
.C(clk),
.CE(sig00000001),
.D(b[21]),
.Q(sig000001d8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000129 (
.C(clk),
.CE(sig00000001),
.D(b[20]),
.Q(sig000001d7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012a (
.C(clk),
.CE(sig00000001),
.D(b[19]),
.Q(sig000001d6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012b (
.C(clk),
.CE(sig00000001),
.D(b[18]),
.Q(sig000001d5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012c (
.C(clk),
.CE(sig00000001),
.D(b[17]),
.Q(sig000001d4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012d (
.C(clk),
.CE(sig00000001),
.D(b[16]),
.Q(sig000001d3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012e (
.C(clk),
.CE(sig00000001),
.D(b[15]),
.Q(sig000001d2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012f (
.C(clk),
.CE(sig00000001),
.D(b[14]),
.Q(sig000001d1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000130 (
.C(clk),
.CE(sig00000001),
.D(b[13]),
.Q(sig000001d0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000131 (
.C(clk),
.CE(sig00000001),
.D(b[12]),
.Q(sig000001cf)
);
FDE #(
.INIT ( 1'b0 ))
blk00000132 (
.C(clk),
.CE(sig00000001),
.D(b[11]),
.Q(sig000001ce)
);
FDE #(
.INIT ( 1'b0 ))
blk00000133 (
.C(clk),
.CE(sig00000001),
.D(b[10]),
.Q(sig000001cd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000134 (
.C(clk),
.CE(sig00000001),
.D(b[9]),
.Q(sig000001cc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000135 (
.C(clk),
.CE(sig00000001),
.D(b[8]),
.Q(sig000001cb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000136 (
.C(clk),
.CE(sig00000001),
.D(b[7]),
.Q(sig000001ca)
);
FDE #(
.INIT ( 1'b0 ))
blk00000137 (
.C(clk),
.CE(sig00000001),
.D(b[6]),
.Q(sig000001c9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000138 (
.C(clk),
.CE(sig00000001),
.D(b[5]),
.Q(sig000001c8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000139 (
.C(clk),
.CE(sig00000001),
.D(b[4]),
.Q(sig000001c7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013a (
.C(clk),
.CE(sig00000001),
.D(b[3]),
.Q(sig000001c6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013b (
.C(clk),
.CE(sig00000001),
.D(b[2]),
.Q(sig000001c5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013c (
.C(clk),
.CE(sig00000001),
.D(b[1]),
.Q(sig000001c4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013d (
.C(clk),
.CE(sig00000001),
.D(b[0]),
.Q(sig000001c3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013e (
.C(clk),
.CE(sig00000001),
.D(a[51]),
.Q(sig0000022a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013f (
.C(clk),
.CE(sig00000001),
.D(a[50]),
.Q(sig00000229)
);
FDE #(
.INIT ( 1'b0 ))
blk00000140 (
.C(clk),
.CE(sig00000001),
.D(a[49]),
.Q(sig00000228)
);
FDE #(
.INIT ( 1'b0 ))
blk00000141 (
.C(clk),
.CE(sig00000001),
.D(a[48]),
.Q(sig00000227)
);
FDE #(
.INIT ( 1'b0 ))
blk00000142 (
.C(clk),
.CE(sig00000001),
.D(a[47]),
.Q(sig00000226)
);
FDE #(
.INIT ( 1'b0 ))
blk00000143 (
.C(clk),
.CE(sig00000001),
.D(a[46]),
.Q(sig00000225)
);
FDE #(
.INIT ( 1'b0 ))
blk00000144 (
.C(clk),
.CE(sig00000001),
.D(a[45]),
.Q(sig00000224)
);
FDE #(
.INIT ( 1'b0 ))
blk00000145 (
.C(clk),
.CE(sig00000001),
.D(a[44]),
.Q(sig00000223)
);
FDE #(
.INIT ( 1'b0 ))
blk00000146 (
.C(clk),
.CE(sig00000001),
.D(a[43]),
.Q(sig00000222)
);
FDE #(
.INIT ( 1'b0 ))
blk00000147 (
.C(clk),
.CE(sig00000001),
.D(a[42]),
.Q(sig00000221)
);
FDE #(
.INIT ( 1'b0 ))
blk00000148 (
.C(clk),
.CE(sig00000001),
.D(a[41]),
.Q(sig00000220)
);
FDE #(
.INIT ( 1'b0 ))
blk00000149 (
.C(clk),
.CE(sig00000001),
.D(a[40]),
.Q(sig0000021f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014a (
.C(clk),
.CE(sig00000001),
.D(a[39]),
.Q(sig0000021e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014b (
.C(clk),
.CE(sig00000001),
.D(a[38]),
.Q(sig0000021d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014c (
.C(clk),
.CE(sig00000001),
.D(a[37]),
.Q(sig0000021c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014d (
.C(clk),
.CE(sig00000001),
.D(a[36]),
.Q(sig0000021b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014e (
.C(clk),
.CE(sig00000001),
.D(a[35]),
.Q(sig0000021a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014f (
.C(clk),
.CE(sig00000001),
.D(a[34]),
.Q(sig00000219)
);
FDE #(
.INIT ( 1'b0 ))
blk00000150 (
.C(clk),
.CE(sig00000001),
.D(a[33]),
.Q(sig00000218)
);
FDE #(
.INIT ( 1'b0 ))
blk00000151 (
.C(clk),
.CE(sig00000001),
.D(a[32]),
.Q(sig00000217)
);
FDE #(
.INIT ( 1'b0 ))
blk00000152 (
.C(clk),
.CE(sig00000001),
.D(a[31]),
.Q(sig00000216)
);
FDE #(
.INIT ( 1'b0 ))
blk00000153 (
.C(clk),
.CE(sig00000001),
.D(a[30]),
.Q(sig00000215)
);
FDE #(
.INIT ( 1'b0 ))
blk00000154 (
.C(clk),
.CE(sig00000001),
.D(a[29]),
.Q(sig00000214)
);
FDE #(
.INIT ( 1'b0 ))
blk00000155 (
.C(clk),
.CE(sig00000001),
.D(a[28]),
.Q(sig00000213)
);
FDE #(
.INIT ( 1'b0 ))
blk00000156 (
.C(clk),
.CE(sig00000001),
.D(a[27]),
.Q(sig00000212)
);
FDE #(
.INIT ( 1'b0 ))
blk00000157 (
.C(clk),
.CE(sig00000001),
.D(a[26]),
.Q(sig00000211)
);
FDE #(
.INIT ( 1'b0 ))
blk00000158 (
.C(clk),
.CE(sig00000001),
.D(a[25]),
.Q(sig00000210)
);
FDE #(
.INIT ( 1'b0 ))
blk00000159 (
.C(clk),
.CE(sig00000001),
.D(a[24]),
.Q(sig0000020f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015a (
.C(clk),
.CE(sig00000001),
.D(a[23]),
.Q(sig0000020e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015b (
.C(clk),
.CE(sig00000001),
.D(a[22]),
.Q(sig0000020d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(sig00000001),
.D(a[21]),
.Q(sig0000020c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015d (
.C(clk),
.CE(sig00000001),
.D(a[20]),
.Q(sig0000020b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(sig00000001),
.D(a[19]),
.Q(sig0000020a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015f (
.C(clk),
.CE(sig00000001),
.D(a[18]),
.Q(sig00000209)
);
FDE #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.CE(sig00000001),
.D(a[17]),
.Q(sig00000208)
);
FDE #(
.INIT ( 1'b0 ))
blk00000161 (
.C(clk),
.CE(sig00000001),
.D(a[16]),
.Q(sig00000207)
);
FDE #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.CE(sig00000001),
.D(a[15]),
.Q(sig00000206)
);
FDE #(
.INIT ( 1'b0 ))
blk00000163 (
.C(clk),
.CE(sig00000001),
.D(a[14]),
.Q(sig00000205)
);
FDE #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.CE(sig00000001),
.D(a[13]),
.Q(sig00000204)
);
FDE #(
.INIT ( 1'b0 ))
blk00000165 (
.C(clk),
.CE(sig00000001),
.D(a[12]),
.Q(sig00000203)
);
FDE #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.CE(sig00000001),
.D(a[11]),
.Q(sig00000202)
);
FDE #(
.INIT ( 1'b0 ))
blk00000167 (
.C(clk),
.CE(sig00000001),
.D(a[10]),
.Q(sig00000201)
);
FDE #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.CE(sig00000001),
.D(a[9]),
.Q(sig00000200)
);
FDE #(
.INIT ( 1'b0 ))
blk00000169 (
.C(clk),
.CE(sig00000001),
.D(a[8]),
.Q(sig000001ff)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.CE(sig00000001),
.D(a[7]),
.Q(sig000001fe)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016b (
.C(clk),
.CE(sig00000001),
.D(a[6]),
.Q(sig000001fd)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016c (
.C(clk),
.CE(sig00000001),
.D(a[5]),
.Q(sig000001fc)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016d (
.C(clk),
.CE(sig00000001),
.D(a[4]),
.Q(sig000001fb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016e (
.C(clk),
.CE(sig00000001),
.D(a[3]),
.Q(sig000001fa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016f (
.C(clk),
.CE(sig00000001),
.D(a[2]),
.Q(sig000001f9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000170 (
.C(clk),
.CE(sig00000001),
.D(a[1]),
.Q(sig000001f8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000171 (
.C(clk),
.CE(sig00000001),
.D(a[0]),
.Q(sig000001f7)
);
XORCY blk00000172 (
.CI(sig000003c9),
.LI(sig00000583),
.O(sig000004c6)
);
XORCY blk00000173 (
.CI(sig000003ca),
.LI(sig00000582),
.O(sig000004c5)
);
MUXCY blk00000174 (
.CI(sig000003ca),
.DI(sig000006c3),
.S(sig00000582),
.O(sig000003c9)
);
XORCY blk00000175 (
.CI(sig000003cb),
.LI(sig00000581),
.O(sig000004c4)
);
MUXCY blk00000176 (
.CI(sig000003cb),
.DI(sig000006c3),
.S(sig00000581),
.O(sig000003ca)
);
XORCY blk00000177 (
.CI(sig000003cc),
.LI(sig00000580),
.O(sig000004c3)
);
MUXCY blk00000178 (
.CI(sig000003cc),
.DI(sig000006c3),
.S(sig00000580),
.O(sig000003cb)
);
XORCY blk00000179 (
.CI(sig000003cd),
.LI(sig0000057f),
.O(sig000004c2)
);
MUXCY blk0000017a (
.CI(sig000003cd),
.DI(sig000006c3),
.S(sig0000057f),
.O(sig000003cc)
);
XORCY blk0000017b (
.CI(sig000003ce),
.LI(sig0000057e),
.O(sig000004c1)
);
MUXCY blk0000017c (
.CI(sig000003ce),
.DI(sig000006c3),
.S(sig0000057e),
.O(sig000003cd)
);
XORCY blk0000017d (
.CI(sig000003cf),
.LI(sig0000057d),
.O(sig000004c0)
);
MUXCY blk0000017e (
.CI(sig000003cf),
.DI(sig000006c3),
.S(sig0000057d),
.O(sig000003ce)
);
XORCY blk0000017f (
.CI(sig000003d0),
.LI(sig0000057c),
.O(sig000004bf)
);
MUXCY blk00000180 (
.CI(sig000003d0),
.DI(sig000006c3),
.S(sig0000057c),
.O(sig000003cf)
);
XORCY blk00000181 (
.CI(sig000003d1),
.LI(sig0000057b),
.O(sig000004be)
);
MUXCY blk00000182 (
.CI(sig000003d1),
.DI(sig000006c3),
.S(sig0000057b),
.O(sig000003d0)
);
XORCY blk00000183 (
.CI(sig000003d2),
.LI(sig0000057a),
.O(sig000004bd)
);
MUXCY blk00000184 (
.CI(sig000003d2),
.DI(sig000006c3),
.S(sig0000057a),
.O(sig000003d1)
);
XORCY blk00000185 (
.CI(sig000006c3),
.LI(sig00000828),
.O(sig000004bc)
);
MUXCY blk00000186 (
.CI(sig000006c3),
.DI(sig0000024a),
.S(sig00000828),
.O(sig000003d2)
);
FD #(
.INIT ( 1'b0 ))
blk00000187 (
.C(clk),
.D(sig000004b8),
.Q(sig000004c7)
);
FD #(
.INIT ( 1'b0 ))
blk00000188 (
.C(clk),
.D(sig000004b7),
.Q(sig000004c8)
);
FD #(
.INIT ( 1'b0 ))
blk00000189 (
.C(clk),
.D(sig000004ba),
.Q(sig000004c9)
);
FD #(
.INIT ( 1'b0 ))
blk0000018a (
.C(clk),
.D(sig000004cc),
.Q(sig000003d3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018b (
.C(clk),
.CE(sig00000001),
.D(sig000004d0),
.Q(sig0000040e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018c (
.C(clk),
.CE(sig00000001),
.D(sig000004d1),
.Q(sig0000040d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018d (
.C(clk),
.CE(sig00000001),
.D(sig000004b4),
.Q(sig0000050d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018e (
.C(clk),
.CE(sig00000001),
.D(sig0000022c),
.Q(sig000004b5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018f (
.C(clk),
.CE(sig00000001),
.D(sig000004b5),
.Q(sig00000544)
);
FDE #(
.INIT ( 1'b0 ))
blk00000190 (
.C(clk),
.CE(sig00000001),
.D(sig000004b6),
.Q(sig000004b4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000191 (
.C(clk),
.CE(sig00000001),
.D(sig000004cf),
.Q(sig000004cb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000192 (
.C(clk),
.CE(sig00000001),
.D(sig000004b9),
.Q(sig000004cd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000193 (
.C(clk),
.CE(sig00000001),
.D(sig000004bb),
.Q(sig000004ca)
);
FD #(
.INIT ( 1'b0 ))
blk00000194 (
.C(clk),
.D(sig00000543),
.Q(sig0000050c)
);
FD #(
.INIT ( 1'b0 ))
blk00000195 (
.C(clk),
.D(sig00000542),
.Q(sig0000050b)
);
FD #(
.INIT ( 1'b0 ))
blk00000196 (
.C(clk),
.D(sig00000541),
.Q(sig0000050a)
);
FD #(
.INIT ( 1'b0 ))
blk00000197 (
.C(clk),
.D(sig00000540),
.Q(sig00000509)
);
FD #(
.INIT ( 1'b0 ))
blk00000198 (
.C(clk),
.D(sig0000053f),
.Q(sig00000508)
);
FD #(
.INIT ( 1'b0 ))
blk00000199 (
.C(clk),
.D(sig0000053e),
.Q(sig00000507)
);
FD #(
.INIT ( 1'b0 ))
blk0000019a (
.C(clk),
.D(sig0000053d),
.Q(sig00000506)
);
FD #(
.INIT ( 1'b0 ))
blk0000019b (
.C(clk),
.D(sig0000053c),
.Q(sig00000505)
);
FD #(
.INIT ( 1'b0 ))
blk0000019c (
.C(clk),
.D(sig0000053b),
.Q(sig00000504)
);
FD #(
.INIT ( 1'b0 ))
blk0000019d (
.C(clk),
.D(sig0000053a),
.Q(sig00000503)
);
FD #(
.INIT ( 1'b0 ))
blk0000019e (
.C(clk),
.D(sig00000539),
.Q(sig00000502)
);
FD #(
.INIT ( 1'b0 ))
blk0000019f (
.C(clk),
.D(sig00000538),
.Q(sig00000501)
);
FD #(
.INIT ( 1'b0 ))
blk000001a0 (
.C(clk),
.D(sig00000537),
.Q(sig00000500)
);
FD #(
.INIT ( 1'b0 ))
blk000001a1 (
.C(clk),
.D(sig00000536),
.Q(sig000004ff)
);
FD #(
.INIT ( 1'b0 ))
blk000001a2 (
.C(clk),
.D(sig00000535),
.Q(sig000004fe)
);
FD #(
.INIT ( 1'b0 ))
blk000001a3 (
.C(clk),
.D(sig00000534),
.Q(sig000004fd)
);
FD #(
.INIT ( 1'b0 ))
blk000001a4 (
.C(clk),
.D(sig00000533),
.Q(sig000004fc)
);
FD #(
.INIT ( 1'b0 ))
blk000001a5 (
.C(clk),
.D(sig00000532),
.Q(sig000004fb)
);
FD #(
.INIT ( 1'b0 ))
blk000001a6 (
.C(clk),
.D(sig00000531),
.Q(sig000004fa)
);
FD #(
.INIT ( 1'b0 ))
blk000001a7 (
.C(clk),
.D(sig00000530),
.Q(sig000004f9)
);
FD #(
.INIT ( 1'b0 ))
blk000001a8 (
.C(clk),
.D(sig0000052f),
.Q(sig000004f8)
);
FD #(
.INIT ( 1'b0 ))
blk000001a9 (
.C(clk),
.D(sig0000052e),
.Q(sig000004f7)
);
FD #(
.INIT ( 1'b0 ))
blk000001aa (
.C(clk),
.D(sig0000052d),
.Q(sig000004f6)
);
FD #(
.INIT ( 1'b0 ))
blk000001ab (
.C(clk),
.D(sig0000052c),
.Q(sig000004f5)
);
FD #(
.INIT ( 1'b0 ))
blk000001ac (
.C(clk),
.D(sig0000052b),
.Q(sig000004f4)
);
FD #(
.INIT ( 1'b0 ))
blk000001ad (
.C(clk),
.D(sig0000052a),
.Q(sig000004f3)
);
FD #(
.INIT ( 1'b0 ))
blk000001ae (
.C(clk),
.D(sig00000529),
.Q(sig000004f2)
);
FD #(
.INIT ( 1'b0 ))
blk000001af (
.C(clk),
.D(sig00000528),
.Q(sig000004f1)
);
FD #(
.INIT ( 1'b0 ))
blk000001b0 (
.C(clk),
.D(sig00000527),
.Q(sig000004f0)
);
FD #(
.INIT ( 1'b0 ))
blk000001b1 (
.C(clk),
.D(sig00000526),
.Q(sig000004ef)
);
FD #(
.INIT ( 1'b0 ))
blk000001b2 (
.C(clk),
.D(sig00000525),
.Q(sig000004ee)
);
FD #(
.INIT ( 1'b0 ))
blk000001b3 (
.C(clk),
.D(sig00000524),
.Q(sig000004ed)
);
FD #(
.INIT ( 1'b0 ))
blk000001b4 (
.C(clk),
.D(sig00000523),
.Q(sig000004ec)
);
FD #(
.INIT ( 1'b0 ))
blk000001b5 (
.C(clk),
.D(sig00000522),
.Q(sig000004eb)
);
FD #(
.INIT ( 1'b0 ))
blk000001b6 (
.C(clk),
.D(sig00000521),
.Q(sig000004ea)
);
FD #(
.INIT ( 1'b0 ))
blk000001b7 (
.C(clk),
.D(sig00000520),
.Q(sig000004e9)
);
FD #(
.INIT ( 1'b0 ))
blk000001b8 (
.C(clk),
.D(sig0000051f),
.Q(sig000004e8)
);
FD #(
.INIT ( 1'b0 ))
blk000001b9 (
.C(clk),
.D(sig0000051e),
.Q(sig000004e7)
);
FD #(
.INIT ( 1'b0 ))
blk000001ba (
.C(clk),
.D(sig0000051d),
.Q(sig000004e6)
);
FD #(
.INIT ( 1'b0 ))
blk000001bb (
.C(clk),
.D(sig0000051c),
.Q(sig000004e5)
);
FD #(
.INIT ( 1'b0 ))
blk000001bc (
.C(clk),
.D(sig0000051b),
.Q(sig000004e4)
);
FD #(
.INIT ( 1'b0 ))
blk000001bd (
.C(clk),
.D(sig0000051a),
.Q(sig000004e3)
);
FD #(
.INIT ( 1'b0 ))
blk000001be (
.C(clk),
.D(sig00000519),
.Q(sig000004e2)
);
FD #(
.INIT ( 1'b0 ))
blk000001bf (
.C(clk),
.D(sig00000518),
.Q(sig000004e1)
);
FD #(
.INIT ( 1'b0 ))
blk000001c0 (
.C(clk),
.D(sig00000517),
.Q(sig000004e0)
);
FD #(
.INIT ( 1'b0 ))
blk000001c1 (
.C(clk),
.D(sig00000516),
.Q(sig000004df)
);
FD #(
.INIT ( 1'b0 ))
blk000001c2 (
.C(clk),
.D(sig00000515),
.Q(sig000004de)
);
FD #(
.INIT ( 1'b0 ))
blk000001c3 (
.C(clk),
.D(sig00000514),
.Q(sig000004dd)
);
FD #(
.INIT ( 1'b0 ))
blk000001c4 (
.C(clk),
.D(sig00000513),
.Q(sig000004dc)
);
FD #(
.INIT ( 1'b0 ))
blk000001c5 (
.C(clk),
.D(sig00000512),
.Q(sig000004db)
);
FD #(
.INIT ( 1'b0 ))
blk000001c6 (
.C(clk),
.D(sig00000511),
.Q(sig000004da)
);
FD #(
.INIT ( 1'b0 ))
blk000001c7 (
.C(clk),
.D(sig00000510),
.Q(sig000004d9)
);
FD #(
.INIT ( 1'b0 ))
blk000001c8 (
.C(clk),
.D(sig0000050f),
.Q(sig000004d8)
);
FD #(
.INIT ( 1'b0 ))
blk000001c9 (
.C(clk),
.D(sig0000050e),
.Q(sig000004d7)
);
FD #(
.INIT ( 1'b0 ))
blk000001ca (
.C(clk),
.D(sig000004c6),
.Q(sig000004d6)
);
FD #(
.INIT ( 1'b0 ))
blk000001cb (
.C(clk),
.D(sig000004c5),
.Q(sig000004d5)
);
FD #(
.INIT ( 1'b0 ))
blk000001cc (
.C(clk),
.D(sig000004c4),
.Q(sig000004d4)
);
FD #(
.INIT ( 1'b0 ))
blk000001cd (
.C(clk),
.D(sig000004c3),
.Q(sig000004d3)
);
FD #(
.INIT ( 1'b0 ))
blk000001ce (
.C(clk),
.D(sig000004c2),
.Q(sig000004d2)
);
FD #(
.INIT ( 1'b0 ))
blk000001cf (
.C(clk),
.D(sig000004c1),
.Q(sig000003d4)
);
FD #(
.INIT ( 1'b0 ))
blk000001d0 (
.C(clk),
.D(sig000004c0),
.Q(sig000003d5)
);
FD #(
.INIT ( 1'b0 ))
blk000001d1 (
.C(clk),
.D(sig000004bf),
.Q(sig000004d1)
);
FD #(
.INIT ( 1'b0 ))
blk000001d2 (
.C(clk),
.D(sig000004be),
.Q(sig000004d0)
);
FD #(
.INIT ( 1'b0 ))
blk000001d3 (
.C(clk),
.D(sig000004bd),
.Q(sig000004cf)
);
FD #(
.INIT ( 1'b0 ))
blk000001d4 (
.C(clk),
.D(sig000004bc),
.Q(sig000004ce)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d5 (
.C(clk),
.CE(sig00000001),
.D(sig0000040f),
.Q(sig000003d6)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d6 (
.C(clk),
.CE(sig00000001),
.D(sig00000410),
.Q(sig000003d7)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d7 (
.C(clk),
.CE(sig00000001),
.D(sig00000411),
.Q(sig000003d8)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d8 (
.C(clk),
.CE(sig00000001),
.D(sig00000412),
.Q(sig000003d9)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d9 (
.C(clk),
.CE(sig00000001),
.D(sig00000413),
.Q(sig000003da)
);
FDE #(
.INIT ( 1'b0 ))
blk000001da (
.C(clk),
.CE(sig00000001),
.D(sig00000414),
.Q(sig000003db)
);
FDE #(
.INIT ( 1'b0 ))
blk000001db (
.C(clk),
.CE(sig00000001),
.D(sig00000415),
.Q(sig000003dc)
);
FDE #(
.INIT ( 1'b0 ))
blk000001dc (
.C(clk),
.CE(sig00000001),
.D(sig00000416),
.Q(sig000003dd)
);
FDE #(
.INIT ( 1'b0 ))
blk000001dd (
.C(clk),
.CE(sig00000001),
.D(sig00000417),
.Q(sig000003de)
);
FDE #(
.INIT ( 1'b0 ))
blk000001de (
.C(clk),
.CE(sig00000001),
.D(sig00000418),
.Q(sig000003df)
);
FDE #(
.INIT ( 1'b0 ))
blk000001df (
.C(clk),
.CE(sig00000001),
.D(sig00000419),
.Q(sig000003e0)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e0 (
.C(clk),
.CE(sig00000001),
.D(sig0000041a),
.Q(sig000003e1)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e1 (
.C(clk),
.CE(sig00000001),
.D(sig0000041b),
.Q(sig000003e2)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e2 (
.C(clk),
.CE(sig00000001),
.D(sig0000041c),
.Q(sig000003e3)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e3 (
.C(clk),
.CE(sig00000001),
.D(sig0000041d),
.Q(sig000003e4)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e4 (
.C(clk),
.CE(sig00000001),
.D(sig0000041e),
.Q(sig000003e5)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e5 (
.C(clk),
.CE(sig00000001),
.D(sig0000041f),
.Q(sig000003e6)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e6 (
.C(clk),
.CE(sig00000001),
.D(sig00000420),
.Q(sig000003e7)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e7 (
.C(clk),
.CE(sig00000001),
.D(sig00000421),
.Q(sig000003e8)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e8 (
.C(clk),
.CE(sig00000001),
.D(sig00000422),
.Q(sig000003e9)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e9 (
.C(clk),
.CE(sig00000001),
.D(sig00000423),
.Q(sig000003ea)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ea (
.C(clk),
.CE(sig00000001),
.D(sig00000424),
.Q(sig000003eb)
);
FDE #(
.INIT ( 1'b0 ))
blk000001eb (
.C(clk),
.CE(sig00000001),
.D(sig00000425),
.Q(sig000003ec)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ec (
.C(clk),
.CE(sig00000001),
.D(sig00000426),
.Q(sig000003ed)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ed (
.C(clk),
.CE(sig00000001),
.D(sig00000427),
.Q(sig000003ee)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ee (
.C(clk),
.CE(sig00000001),
.D(sig00000428),
.Q(sig000003ef)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ef (
.C(clk),
.CE(sig00000001),
.D(sig00000429),
.Q(sig000003f0)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f0 (
.C(clk),
.CE(sig00000001),
.D(sig0000042a),
.Q(sig000003f1)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f1 (
.C(clk),
.CE(sig00000001),
.D(sig0000042b),
.Q(sig000003f2)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f2 (
.C(clk),
.CE(sig00000001),
.D(sig0000042c),
.Q(sig000003f3)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f3 (
.C(clk),
.CE(sig00000001),
.D(sig0000042d),
.Q(sig000003f4)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f4 (
.C(clk),
.CE(sig00000001),
.D(sig0000042e),
.Q(sig000003f5)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f5 (
.C(clk),
.CE(sig00000001),
.D(sig0000042f),
.Q(sig000003f6)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f6 (
.C(clk),
.CE(sig00000001),
.D(sig00000430),
.Q(sig000003f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f7 (
.C(clk),
.CE(sig00000001),
.D(sig00000431),
.Q(sig000003f8)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f8 (
.C(clk),
.CE(sig00000001),
.D(sig00000432),
.Q(sig000003f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f9 (
.C(clk),
.CE(sig00000001),
.D(sig00000433),
.Q(sig000003fa)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fa (
.C(clk),
.CE(sig00000001),
.D(sig00000434),
.Q(sig000003fb)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fb (
.C(clk),
.CE(sig00000001),
.D(sig00000435),
.Q(sig000003fc)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fc (
.C(clk),
.CE(sig00000001),
.D(sig00000436),
.Q(sig000003fd)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fd (
.C(clk),
.CE(sig00000001),
.D(sig00000437),
.Q(sig000003fe)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fe (
.C(clk),
.CE(sig00000001),
.D(sig00000438),
.Q(sig000003ff)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ff (
.C(clk),
.CE(sig00000001),
.D(sig00000439),
.Q(sig00000400)
);
FDE #(
.INIT ( 1'b0 ))
blk00000200 (
.C(clk),
.CE(sig00000001),
.D(sig0000043a),
.Q(sig00000401)
);
FDE #(
.INIT ( 1'b0 ))
blk00000201 (
.C(clk),
.CE(sig00000001),
.D(sig0000043b),
.Q(sig00000402)
);
FDE #(
.INIT ( 1'b0 ))
blk00000202 (
.C(clk),
.CE(sig00000001),
.D(sig0000043c),
.Q(sig00000403)
);
FDE #(
.INIT ( 1'b0 ))
blk00000203 (
.C(clk),
.CE(sig00000001),
.D(sig0000043d),
.Q(sig00000404)
);
FDE #(
.INIT ( 1'b0 ))
blk00000204 (
.C(clk),
.CE(sig00000001),
.D(sig0000043e),
.Q(sig00000405)
);
FDE #(
.INIT ( 1'b0 ))
blk00000205 (
.C(clk),
.CE(sig00000001),
.D(sig0000043f),
.Q(sig00000406)
);
FDE #(
.INIT ( 1'b0 ))
blk00000206 (
.C(clk),
.CE(sig00000001),
.D(sig00000440),
.Q(sig00000407)
);
FDE #(
.INIT ( 1'b0 ))
blk00000207 (
.C(clk),
.CE(sig00000001),
.D(sig00000441),
.Q(sig00000408)
);
FDE #(
.INIT ( 1'b0 ))
blk00000208 (
.C(clk),
.CE(sig00000001),
.D(sig00000442),
.Q(sig00000409)
);
FDE #(
.INIT ( 1'b0 ))
blk00000209 (
.C(clk),
.CE(sig00000001),
.D(sig00000443),
.Q(sig0000040a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020a (
.C(clk),
.CE(sig00000001),
.D(sig00000444),
.Q(sig0000040b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020b (
.C(clk),
.CE(sig00000001),
.D(sig00000445),
.Q(sig0000040c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020c (
.C(clk),
.CE(sig00000001),
.D(sig00000446),
.Q(sig0000047d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020d (
.C(clk),
.CE(sig00000001),
.D(sig00000447),
.Q(sig0000047e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020e (
.C(clk),
.CE(sig00000001),
.D(sig00000448),
.Q(sig0000047f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020f (
.C(clk),
.CE(sig00000001),
.D(sig00000449),
.Q(sig00000480)
);
FDE #(
.INIT ( 1'b0 ))
blk00000210 (
.C(clk),
.CE(sig00000001),
.D(sig0000044a),
.Q(sig00000481)
);
FDE #(
.INIT ( 1'b0 ))
blk00000211 (
.C(clk),
.CE(sig00000001),
.D(sig0000044b),
.Q(sig00000482)
);
FDE #(
.INIT ( 1'b0 ))
blk00000212 (
.C(clk),
.CE(sig00000001),
.D(sig0000044c),
.Q(sig00000483)
);
FDE #(
.INIT ( 1'b0 ))
blk00000213 (
.C(clk),
.CE(sig00000001),
.D(sig0000044d),
.Q(sig00000484)
);
FDE #(
.INIT ( 1'b0 ))
blk00000214 (
.C(clk),
.CE(sig00000001),
.D(sig0000044e),
.Q(sig00000485)
);
FDE #(
.INIT ( 1'b0 ))
blk00000215 (
.C(clk),
.CE(sig00000001),
.D(sig0000044f),
.Q(sig00000486)
);
FDE #(
.INIT ( 1'b0 ))
blk00000216 (
.C(clk),
.CE(sig00000001),
.D(sig00000450),
.Q(sig00000487)
);
FDE #(
.INIT ( 1'b0 ))
blk00000217 (
.C(clk),
.CE(sig00000001),
.D(sig00000451),
.Q(sig00000488)
);
FDE #(
.INIT ( 1'b0 ))
blk00000218 (
.C(clk),
.CE(sig00000001),
.D(sig00000452),
.Q(sig00000489)
);
FDE #(
.INIT ( 1'b0 ))
blk00000219 (
.C(clk),
.CE(sig00000001),
.D(sig00000453),
.Q(sig0000048a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021a (
.C(clk),
.CE(sig00000001),
.D(sig00000454),
.Q(sig0000048b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021b (
.C(clk),
.CE(sig00000001),
.D(sig00000455),
.Q(sig0000048c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021c (
.C(clk),
.CE(sig00000001),
.D(sig00000456),
.Q(sig0000048d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021d (
.C(clk),
.CE(sig00000001),
.D(sig00000457),
.Q(sig0000048e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021e (
.C(clk),
.CE(sig00000001),
.D(sig00000458),
.Q(sig0000048f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021f (
.C(clk),
.CE(sig00000001),
.D(sig00000459),
.Q(sig00000490)
);
FDE #(
.INIT ( 1'b0 ))
blk00000220 (
.C(clk),
.CE(sig00000001),
.D(sig0000045a),
.Q(sig00000491)
);
FDE #(
.INIT ( 1'b0 ))
blk00000221 (
.C(clk),
.CE(sig00000001),
.D(sig0000045b),
.Q(sig00000492)
);
FDE #(
.INIT ( 1'b0 ))
blk00000222 (
.C(clk),
.CE(sig00000001),
.D(sig0000045c),
.Q(sig00000493)
);
FDE #(
.INIT ( 1'b0 ))
blk00000223 (
.C(clk),
.CE(sig00000001),
.D(sig0000045d),
.Q(sig00000494)
);
FDE #(
.INIT ( 1'b0 ))
blk00000224 (
.C(clk),
.CE(sig00000001),
.D(sig0000045e),
.Q(sig00000495)
);
FDE #(
.INIT ( 1'b0 ))
blk00000225 (
.C(clk),
.CE(sig00000001),
.D(sig0000045f),
.Q(sig00000496)
);
FDE #(
.INIT ( 1'b0 ))
blk00000226 (
.C(clk),
.CE(sig00000001),
.D(sig00000460),
.Q(sig00000497)
);
FDE #(
.INIT ( 1'b0 ))
blk00000227 (
.C(clk),
.CE(sig00000001),
.D(sig00000461),
.Q(sig00000498)
);
FDE #(
.INIT ( 1'b0 ))
blk00000228 (
.C(clk),
.CE(sig00000001),
.D(sig00000462),
.Q(sig00000499)
);
FDE #(
.INIT ( 1'b0 ))
blk00000229 (
.C(clk),
.CE(sig00000001),
.D(sig00000463),
.Q(sig0000049a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022a (
.C(clk),
.CE(sig00000001),
.D(sig00000464),
.Q(sig0000049b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022b (
.C(clk),
.CE(sig00000001),
.D(sig00000465),
.Q(sig0000049c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022c (
.C(clk),
.CE(sig00000001),
.D(sig00000466),
.Q(sig0000049d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022d (
.C(clk),
.CE(sig00000001),
.D(sig00000467),
.Q(sig0000049e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022e (
.C(clk),
.CE(sig00000001),
.D(sig00000468),
.Q(sig0000049f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022f (
.C(clk),
.CE(sig00000001),
.D(sig00000469),
.Q(sig000004a0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000230 (
.C(clk),
.CE(sig00000001),
.D(sig0000046a),
.Q(sig000004a1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000231 (
.C(clk),
.CE(sig00000001),
.D(sig0000046b),
.Q(sig000004a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000232 (
.C(clk),
.CE(sig00000001),
.D(sig0000046c),
.Q(sig000004a3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000233 (
.C(clk),
.CE(sig00000001),
.D(sig0000046d),
.Q(sig000004a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000234 (
.C(clk),
.CE(sig00000001),
.D(sig0000046e),
.Q(sig000004a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000235 (
.C(clk),
.CE(sig00000001),
.D(sig0000046f),
.Q(sig000004a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000236 (
.C(clk),
.CE(sig00000001),
.D(sig00000470),
.Q(sig000004a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000237 (
.C(clk),
.CE(sig00000001),
.D(sig00000471),
.Q(sig000004a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000238 (
.C(clk),
.CE(sig00000001),
.D(sig00000472),
.Q(sig000004a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000239 (
.C(clk),
.CE(sig00000001),
.D(sig00000473),
.Q(sig000004aa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023a (
.C(clk),
.CE(sig00000001),
.D(sig00000474),
.Q(sig000004ab)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023b (
.C(clk),
.CE(sig00000001),
.D(sig00000475),
.Q(sig000004ac)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023c (
.C(clk),
.CE(sig00000001),
.D(sig00000476),
.Q(sig000004ad)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023d (
.C(clk),
.CE(sig00000001),
.D(sig00000477),
.Q(sig000004ae)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023e (
.C(clk),
.CE(sig00000001),
.D(sig00000478),
.Q(sig000004af)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023f (
.C(clk),
.CE(sig00000001),
.D(sig00000479),
.Q(sig000004b0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000240 (
.C(clk),
.CE(sig00000001),
.D(sig0000047a),
.Q(sig000004b1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000241 (
.C(clk),
.CE(sig00000001),
.D(sig0000047b),
.Q(sig000004b2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000242 (
.C(clk),
.CE(sig00000001),
.D(sig0000047c),
.Q(sig000004b3)
);
MUXF8 blk00000243 (
.I0(sig00000586),
.I1(sig00000585),
.S(sig00000595),
.O(sig00000584)
);
MUXF7 blk00000244 (
.I0(sig00000598),
.I1(sig00000597),
.S(sig00000596),
.O(sig00000585)
);
MUXF7 blk00000245 (
.I0(sig0000059a),
.I1(sig00000599),
.S(sig00000596),
.O(sig00000586)
);
FDE #(
.INIT ( 1'b0 ))
blk00000246 (
.C(clk),
.CE(sig00000001),
.D(sig000003d5),
.Q(sig00000596)
);
FDE #(
.INIT ( 1'b0 ))
blk00000247 (
.C(clk),
.CE(sig00000001),
.D(sig000003d4),
.Q(sig00000595)
);
MUXCY blk00000248 (
.CI(sig000005c7),
.DI(sig000006c3),
.S(sig000005b7),
.O(sig000005c6)
);
MUXCY blk00000249 (
.CI(sig000005c8),
.DI(sig000006c3),
.S(sig000005b8),
.O(sig000005c7)
);
MUXCY blk0000024a (
.CI(sig000005c9),
.DI(sig000006c3),
.S(sig000005b9),
.O(sig000005c8)
);
MUXCY blk0000024b (
.CI(sig000005ca),
.DI(sig000006c3),
.S(sig000005ba),
.O(sig000005c9)
);
MUXCY blk0000024c (
.CI(sig000005cb),
.DI(sig000006c3),
.S(sig000005bb),
.O(sig000005ca)
);
MUXCY blk0000024d (
.CI(sig000005cc),
.DI(sig000006c3),
.S(sig000005bc),
.O(sig000005cb)
);
MUXCY blk0000024e (
.CI(sig000005cd),
.DI(sig000006c3),
.S(sig000005bd),
.O(sig000005cc)
);
MUXCY blk0000024f (
.CI(sig000005ce),
.DI(sig000006c3),
.S(sig000005be),
.O(sig000005cd)
);
MUXCY blk00000250 (
.CI(sig000005cf),
.DI(sig000006c3),
.S(sig000005bf),
.O(sig000005ce)
);
MUXCY blk00000251 (
.CI(sig000005d0),
.DI(sig000006c3),
.S(sig000005c0),
.O(sig000005cf)
);
MUXCY blk00000252 (
.CI(sig000005d1),
.DI(sig000006c3),
.S(sig000005c1),
.O(sig000005d0)
);
MUXCY blk00000253 (
.CI(sig000005d2),
.DI(sig000006c3),
.S(sig000005c2),
.O(sig000005d1)
);
MUXCY blk00000254 (
.CI(sig000005d3),
.DI(sig000006c3),
.S(sig000005c3),
.O(sig000005d2)
);
MUXCY blk00000255 (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig000005c4),
.O(sig000005d3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000256 (
.C(clk),
.CE(sig00000001),
.D(sig000005c6),
.Q(sig000005c5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000257 (
.C(clk),
.CE(sig00000001),
.D(sig000005c7),
.Q(sig000005ab)
);
FDE #(
.INIT ( 1'b0 ))
blk00000258 (
.C(clk),
.CE(sig00000001),
.D(sig000005c8),
.Q(sig000005aa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000259 (
.C(clk),
.CE(sig00000001),
.D(sig000005c9),
.Q(sig000005ad)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025a (
.C(clk),
.CE(sig00000001),
.D(sig000005ca),
.Q(sig000005ae)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025b (
.C(clk),
.CE(sig00000001),
.D(sig000005cb),
.Q(sig000005af)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025c (
.C(clk),
.CE(sig00000001),
.D(sig000005cc),
.Q(sig000005ac)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025d (
.C(clk),
.CE(sig00000001),
.D(sig000005cd),
.Q(sig000005b1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025e (
.C(clk),
.CE(sig00000001),
.D(sig000005ce),
.Q(sig000005b2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025f (
.C(clk),
.CE(sig00000001),
.D(sig000005cf),
.Q(sig000005b3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000260 (
.C(clk),
.CE(sig00000001),
.D(sig000005d0),
.Q(sig000005b0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000261 (
.C(clk),
.CE(sig00000001),
.D(sig000005d1),
.Q(sig000005b4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000262 (
.C(clk),
.CE(sig00000001),
.D(sig000005d2),
.Q(sig000005b5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000263 (
.C(clk),
.CE(sig00000001),
.D(sig000005d3),
.Q(sig000005b6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000264 (
.C(clk),
.CE(sig00000001),
.D(sig00000584),
.Q(sig000004cc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000265 (
.C(clk),
.CE(sig00000001),
.D(sig00000001),
.Q(sig0000059c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000266 (
.C(clk),
.CE(sig00000001),
.D(sig00000587),
.Q(sig0000059d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000267 (
.C(clk),
.CE(sig00000001),
.D(sig00000588),
.Q(sig0000059b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000268 (
.C(clk),
.CE(sig00000001),
.D(sig00000589),
.Q(sig0000059f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000269 (
.C(clk),
.CE(sig00000001),
.D(sig0000058a),
.Q(sig000005a0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026a (
.C(clk),
.CE(sig00000001),
.D(sig0000058b),
.Q(sig000005a1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026b (
.C(clk),
.CE(sig00000001),
.D(sig0000058c),
.Q(sig0000059e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026c (
.C(clk),
.CE(sig00000001),
.D(sig0000058d),
.Q(sig000005a3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026d (
.C(clk),
.CE(sig00000001),
.D(sig0000058e),
.Q(sig000005a4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026e (
.C(clk),
.CE(sig00000001),
.D(sig0000058f),
.Q(sig000005a5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026f (
.C(clk),
.CE(sig00000001),
.D(sig00000590),
.Q(sig000005a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000270 (
.C(clk),
.CE(sig00000001),
.D(sig00000591),
.Q(sig000005a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000271 (
.C(clk),
.CE(sig00000001),
.D(sig00000592),
.Q(sig000005a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000272 (
.C(clk),
.CE(sig00000001),
.D(sig00000593),
.Q(sig000005a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000273 (
.C(clk),
.CE(sig00000001),
.D(sig00000594),
.Q(sig000005a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000274 (
.C(clk),
.CE(sig00000001),
.D(sig000004ca),
.Q(sig00000697)
);
FDE #(
.INIT ( 1'b0 ))
blk00000275 (
.C(clk),
.CE(sig00000001),
.D(sig0000050d),
.Q(sig00000696)
);
FD #(
.INIT ( 1'b0 ))
blk00000276 (
.C(clk),
.D(sig00000571),
.Q(sig00000665)
);
FD #(
.INIT ( 1'b0 ))
blk00000277 (
.C(clk),
.D(sig00000570),
.Q(sig00000664)
);
FD #(
.INIT ( 1'b0 ))
blk00000278 (
.C(clk),
.D(sig0000056f),
.Q(sig00000663)
);
FD #(
.INIT ( 1'b0 ))
blk00000279 (
.C(clk),
.D(sig0000056e),
.Q(sig00000662)
);
FD #(
.INIT ( 1'b0 ))
blk0000027a (
.C(clk),
.D(sig0000056d),
.Q(sig00000661)
);
FD #(
.INIT ( 1'b0 ))
blk0000027b (
.C(clk),
.D(sig0000056c),
.Q(sig00000660)
);
FD #(
.INIT ( 1'b0 ))
blk0000027c (
.C(clk),
.D(sig0000056b),
.Q(sig0000065f)
);
FD #(
.INIT ( 1'b0 ))
blk0000027d (
.C(clk),
.D(sig0000056a),
.Q(sig0000065e)
);
FD #(
.INIT ( 1'b0 ))
blk0000027e (
.C(clk),
.D(sig00000569),
.Q(sig0000065d)
);
FD #(
.INIT ( 1'b0 ))
blk0000027f (
.C(clk),
.D(sig00000568),
.Q(sig0000065c)
);
FD #(
.INIT ( 1'b0 ))
blk00000280 (
.C(clk),
.D(sig00000567),
.Q(sig0000065b)
);
FD #(
.INIT ( 1'b0 ))
blk00000281 (
.C(clk),
.D(sig00000566),
.Q(sig0000065a)
);
FD #(
.INIT ( 1'b0 ))
blk00000282 (
.C(clk),
.D(sig00000565),
.Q(sig00000659)
);
FD #(
.INIT ( 1'b0 ))
blk00000283 (
.C(clk),
.D(sig00000564),
.Q(sig00000658)
);
FD #(
.INIT ( 1'b0 ))
blk00000284 (
.C(clk),
.D(sig00000563),
.Q(sig00000657)
);
FD #(
.INIT ( 1'b0 ))
blk00000285 (
.C(clk),
.D(sig00000562),
.Q(sig00000656)
);
FD #(
.INIT ( 1'b0 ))
blk00000286 (
.C(clk),
.D(sig00000561),
.Q(sig00000655)
);
FD #(
.INIT ( 1'b0 ))
blk00000287 (
.C(clk),
.D(sig00000560),
.Q(sig00000654)
);
FD #(
.INIT ( 1'b0 ))
blk00000288 (
.C(clk),
.D(sig0000055f),
.Q(sig00000653)
);
FD #(
.INIT ( 1'b0 ))
blk00000289 (
.C(clk),
.D(sig0000055e),
.Q(sig00000652)
);
FD #(
.INIT ( 1'b0 ))
blk0000028a (
.C(clk),
.D(sig0000055d),
.Q(sig00000651)
);
FD #(
.INIT ( 1'b0 ))
blk0000028b (
.C(clk),
.D(sig0000055c),
.Q(sig00000650)
);
FD #(
.INIT ( 1'b0 ))
blk0000028c (
.C(clk),
.D(sig0000055b),
.Q(sig0000064f)
);
FD #(
.INIT ( 1'b0 ))
blk0000028d (
.C(clk),
.D(sig0000055a),
.Q(sig0000064e)
);
FD #(
.INIT ( 1'b0 ))
blk0000028e (
.C(clk),
.D(sig00000559),
.Q(sig0000064d)
);
FD #(
.INIT ( 1'b0 ))
blk0000028f (
.C(clk),
.D(sig00000558),
.Q(sig0000064c)
);
FD #(
.INIT ( 1'b0 ))
blk00000290 (
.C(clk),
.D(sig00000557),
.Q(sig0000064b)
);
FD #(
.INIT ( 1'b0 ))
blk00000291 (
.C(clk),
.D(sig00000556),
.Q(sig0000064a)
);
FD #(
.INIT ( 1'b0 ))
blk00000292 (
.C(clk),
.D(sig00000555),
.Q(sig00000649)
);
FD #(
.INIT ( 1'b0 ))
blk00000293 (
.C(clk),
.D(sig00000554),
.Q(sig00000648)
);
FD #(
.INIT ( 1'b0 ))
blk00000294 (
.C(clk),
.D(sig00000553),
.Q(sig00000647)
);
FD #(
.INIT ( 1'b0 ))
blk00000295 (
.C(clk),
.D(sig00000552),
.Q(sig00000646)
);
FD #(
.INIT ( 1'b0 ))
blk00000296 (
.C(clk),
.D(sig00000551),
.Q(sig00000645)
);
FD #(
.INIT ( 1'b0 ))
blk00000297 (
.C(clk),
.D(sig00000550),
.Q(sig00000644)
);
FD #(
.INIT ( 1'b0 ))
blk00000298 (
.C(clk),
.D(sig0000054f),
.Q(sig00000643)
);
FD #(
.INIT ( 1'b0 ))
blk00000299 (
.C(clk),
.D(sig0000054e),
.Q(sig00000642)
);
FD #(
.INIT ( 1'b0 ))
blk0000029a (
.C(clk),
.D(sig0000054d),
.Q(sig00000641)
);
FD #(
.INIT ( 1'b0 ))
blk0000029b (
.C(clk),
.D(sig0000054c),
.Q(sig00000640)
);
FD #(
.INIT ( 1'b0 ))
blk0000029c (
.C(clk),
.D(sig0000054b),
.Q(sig0000063f)
);
FD #(
.INIT ( 1'b0 ))
blk0000029d (
.C(clk),
.D(sig0000054a),
.Q(sig0000063e)
);
FD #(
.INIT ( 1'b0 ))
blk0000029e (
.C(clk),
.D(sig00000549),
.Q(sig0000063d)
);
FD #(
.INIT ( 1'b0 ))
blk0000029f (
.C(clk),
.D(sig00000548),
.Q(sig0000063c)
);
FD #(
.INIT ( 1'b0 ))
blk000002a0 (
.C(clk),
.D(sig00000547),
.Q(sig0000063b)
);
FD #(
.INIT ( 1'b0 ))
blk000002a1 (
.C(clk),
.D(sig00000546),
.Q(sig0000063a)
);
FD #(
.INIT ( 1'b0 ))
blk000002a2 (
.C(clk),
.D(sig00000545),
.Q(sig00000639)
);
FD #(
.INIT ( 1'b0 ))
blk000002a3 (
.C(clk),
.D(sig00000579),
.Q(sig0000069f)
);
FD #(
.INIT ( 1'b0 ))
blk000002a4 (
.C(clk),
.D(sig00000578),
.Q(sig0000069e)
);
FD #(
.INIT ( 1'b0 ))
blk000002a5 (
.C(clk),
.D(sig00000577),
.Q(sig0000069d)
);
FD #(
.INIT ( 1'b0 ))
blk000002a6 (
.C(clk),
.D(sig00000576),
.Q(sig0000069c)
);
FD #(
.INIT ( 1'b0 ))
blk000002a7 (
.C(clk),
.D(sig00000575),
.Q(sig0000069b)
);
FD #(
.INIT ( 1'b0 ))
blk000002a8 (
.C(clk),
.D(sig00000574),
.Q(sig0000069a)
);
FD #(
.INIT ( 1'b0 ))
blk000002a9 (
.C(clk),
.D(sig00000573),
.Q(sig00000699)
);
FD #(
.INIT ( 1'b0 ))
blk000002aa (
.C(clk),
.D(sig00000572),
.Q(sig00000698)
);
FD #(
.INIT ( 1'b0 ))
blk000002ab (
.C(clk),
.D(sig0000047d),
.Q(sig00000600)
);
FD #(
.INIT ( 1'b0 ))
blk000002ac (
.C(clk),
.D(sig0000047e),
.Q(sig000005ff)
);
FD #(
.INIT ( 1'b0 ))
blk000002ad (
.C(clk),
.D(sig0000047f),
.Q(sig000005fe)
);
FD #(
.INIT ( 1'b0 ))
blk000002ae (
.C(clk),
.D(sig00000480),
.Q(sig000005fd)
);
FD #(
.INIT ( 1'b0 ))
blk000002af (
.C(clk),
.D(sig00000481),
.Q(sig000005fc)
);
FD #(
.INIT ( 1'b0 ))
blk000002b0 (
.C(clk),
.D(sig00000482),
.Q(sig000005fb)
);
FD #(
.INIT ( 1'b0 ))
blk000002b1 (
.C(clk),
.D(sig00000483),
.Q(sig000005fa)
);
FD #(
.INIT ( 1'b0 ))
blk000002b2 (
.C(clk),
.D(sig00000484),
.Q(sig000005f9)
);
XORCY blk000002b3 (
.CI(sig000006a2),
.LI(sig00000827),
.O(sig000006a0)
);
XORCY blk000002b4 (
.CI(sig000006a4),
.LI(sig00000811),
.O(sig000006a1)
);
MUXCY blk000002b5 (
.CI(sig000006a4),
.DI(sig00000608),
.S(sig00000811),
.O(sig000006a2)
);
XORCY blk000002b6 (
.CI(sig000006a6),
.LI(sig00000812),
.O(sig000006a3)
);
MUXCY blk000002b7 (
.CI(sig000006a6),
.DI(sig00000607),
.S(sig00000812),
.O(sig000006a4)
);
XORCY blk000002b8 (
.CI(sig000006a8),
.LI(sig00000813),
.O(sig000006a5)
);
MUXCY blk000002b9 (
.CI(sig000006a8),
.DI(sig00000606),
.S(sig00000813),
.O(sig000006a6)
);
XORCY blk000002ba (
.CI(sig000006aa),
.LI(sig00000814),
.O(sig000006a7)
);
MUXCY blk000002bb (
.CI(sig000006aa),
.DI(sig00000605),
.S(sig00000814),
.O(sig000006a8)
);
XORCY blk000002bc (
.CI(sig000006ac),
.LI(sig00000815),
.O(sig000006a9)
);
MUXCY blk000002bd (
.CI(sig000006ac),
.DI(sig00000604),
.S(sig00000815),
.O(sig000006aa)
);
XORCY blk000002be (
.CI(sig000006ae),
.LI(sig00000816),
.O(sig000006ab)
);
MUXCY blk000002bf (
.CI(sig000006ae),
.DI(sig00000603),
.S(sig00000816),
.O(sig000006ac)
);
XORCY blk000002c0 (
.CI(sig000006b0),
.LI(sig00000817),
.O(sig000006ad)
);
MUXCY blk000002c1 (
.CI(sig000006b0),
.DI(sig00000602),
.S(sig00000817),
.O(sig000006ae)
);
XORCY blk000002c2 (
.CI(sig00000001),
.LI(sig00000818),
.O(sig000006af)
);
MUXCY blk000002c3 (
.CI(sig00000001),
.DI(sig00000601),
.S(sig00000818),
.O(sig000006b0)
);
XORCY blk000002c4 (
.CI(sig000006b3),
.LI(sig000005dc),
.O(sig000006b1)
);
XORCY blk000002c5 (
.CI(sig000006b5),
.LI(sig000005db),
.O(sig000006b2)
);
MUXCY blk000002c6 (
.CI(sig000006b5),
.DI(sig00000608),
.S(sig000005db),
.O(sig000006b3)
);
XORCY blk000002c7 (
.CI(sig000006b7),
.LI(sig000005da),
.O(sig000006b4)
);
MUXCY blk000002c8 (
.CI(sig000006b7),
.DI(sig00000607),
.S(sig000005da),
.O(sig000006b5)
);
XORCY blk000002c9 (
.CI(sig000006b9),
.LI(sig000005d9),
.O(sig000006b6)
);
MUXCY blk000002ca (
.CI(sig000006b9),
.DI(sig00000606),
.S(sig000005d9),
.O(sig000006b7)
);
XORCY blk000002cb (
.CI(sig000006bb),
.LI(sig000005d8),
.O(sig000006b8)
);
MUXCY blk000002cc (
.CI(sig000006bb),
.DI(sig00000605),
.S(sig000005d8),
.O(sig000006b9)
);
XORCY blk000002cd (
.CI(sig000006bd),
.LI(sig000005d7),
.O(sig000006ba)
);
MUXCY blk000002ce (
.CI(sig000006bd),
.DI(sig00000604),
.S(sig000005d7),
.O(sig000006bb)
);
XORCY blk000002cf (
.CI(sig000006bf),
.LI(sig000005d6),
.O(sig000006bc)
);
MUXCY blk000002d0 (
.CI(sig000006bf),
.DI(sig00000603),
.S(sig000005d6),
.O(sig000006bd)
);
XORCY blk000002d1 (
.CI(sig000006c1),
.LI(sig000005d5),
.O(sig000006be)
);
MUXCY blk000002d2 (
.CI(sig000006c1),
.DI(sig00000602),
.S(sig000005d5),
.O(sig000006bf)
);
XORCY blk000002d3 (
.CI(sig000006c3),
.LI(sig000005d4),
.O(sig000006c0)
);
MUXCY blk000002d4 (
.CI(sig000006c3),
.DI(sig00000601),
.S(sig000005d4),
.O(sig000006c1)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d5 (
.C(clk),
.CE(sig00000001),
.D(sig000006b1),
.Q(sig000005f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d6 (
.C(clk),
.CE(sig00000001),
.D(sig000006b2),
.Q(sig000005f6)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d7 (
.C(clk),
.CE(sig00000001),
.D(sig000006b4),
.Q(sig000005f5)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d8 (
.C(clk),
.CE(sig00000001),
.D(sig000006b6),
.Q(sig000005f4)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d9 (
.C(clk),
.CE(sig00000001),
.D(sig000006b8),
.Q(sig000005f3)
);
FDE #(
.INIT ( 1'b0 ))
blk000002da (
.C(clk),
.CE(sig00000001),
.D(sig000006ba),
.Q(sig000005f2)
);
FDE #(
.INIT ( 1'b0 ))
blk000002db (
.C(clk),
.CE(sig00000001),
.D(sig000006bc),
.Q(sig000005f1)
);
FDE #(
.INIT ( 1'b0 ))
blk000002dc (
.C(clk),
.CE(sig00000001),
.D(sig000006be),
.Q(sig000005f0)
);
FDE #(
.INIT ( 1'b0 ))
blk000002dd (
.C(clk),
.CE(sig00000001),
.D(sig000006c0),
.Q(sig000005ef)
);
FDE #(
.INIT ( 1'b0 ))
blk000002de (
.C(clk),
.CE(sig00000001),
.D(sig000006a0),
.Q(sig000005ee)
);
FDE #(
.INIT ( 1'b0 ))
blk000002df (
.C(clk),
.CE(sig00000001),
.D(sig000006a1),
.Q(sig000005ed)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e0 (
.C(clk),
.CE(sig00000001),
.D(sig000006a3),
.Q(sig000005ec)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e1 (
.C(clk),
.CE(sig00000001),
.D(sig000006a5),
.Q(sig000005eb)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e2 (
.C(clk),
.CE(sig00000001),
.D(sig000006a7),
.Q(sig000005ea)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e3 (
.C(clk),
.CE(sig00000001),
.D(sig000006a9),
.Q(sig000005e9)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e4 (
.C(clk),
.CE(sig00000001),
.D(sig000006ab),
.Q(sig000005e8)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e5 (
.C(clk),
.CE(sig00000001),
.D(sig000006ad),
.Q(sig000005e7)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e6 (
.C(clk),
.CE(sig00000001),
.D(sig000006af),
.Q(sig000005e6)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e7 (
.C(clk),
.CE(sig00000001),
.D(sig000005e5),
.Q(sig000001c2)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e8 (
.C(clk),
.CE(sig00000001),
.D(sig000005e4),
.Q(sig000001c1)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e9 (
.C(clk),
.CE(sig00000001),
.D(sig000005e3),
.Q(sig000001c0)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ea (
.C(clk),
.CE(sig00000001),
.D(sig000005e2),
.Q(sig000001bf)
);
FDE #(
.INIT ( 1'b0 ))
blk000002eb (
.C(clk),
.CE(sig00000001),
.D(sig000005e1),
.Q(sig000001be)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ec (
.C(clk),
.CE(sig00000001),
.D(sig000005e0),
.Q(sig000001bd)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ed (
.C(clk),
.CE(sig00000001),
.D(sig000005df),
.Q(sig000001bc)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ee (
.C(clk),
.CE(sig00000001),
.D(sig000005de),
.Q(sig000001bb)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ef (
.C(clk),
.CE(sig00000001),
.D(sig000005dd),
.Q(sig000001ba)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f0 (
.C(clk),
.CE(sig00000001),
.D(sig00000695),
.Q(sig000001b9)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f1 (
.C(clk),
.CE(sig00000001),
.D(sig00000694),
.Q(sig000001b8)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f2 (
.C(clk),
.CE(sig00000001),
.D(sig00000693),
.Q(sig000001b7)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f3 (
.C(clk),
.CE(sig00000001),
.D(sig00000692),
.Q(sig000001b6)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f4 (
.C(clk),
.CE(sig00000001),
.D(sig00000691),
.Q(sig000001b5)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f5 (
.C(clk),
.CE(sig00000001),
.D(sig00000690),
.Q(sig000001b4)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f6 (
.C(clk),
.CE(sig00000001),
.D(sig0000068f),
.Q(sig000001b3)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f7 (
.C(clk),
.CE(sig00000001),
.D(sig0000068e),
.Q(sig000001b2)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f8 (
.C(clk),
.CE(sig00000001),
.D(sig0000068d),
.Q(sig000001b1)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f9 (
.C(clk),
.CE(sig00000001),
.D(sig0000068c),
.Q(sig000001b0)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fa (
.C(clk),
.CE(sig00000001),
.D(sig0000068b),
.Q(sig000001af)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fb (
.C(clk),
.CE(sig00000001),
.D(sig0000068a),
.Q(sig000001ae)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fc (
.C(clk),
.CE(sig00000001),
.D(sig00000689),
.Q(sig000001ad)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fd (
.C(clk),
.CE(sig00000001),
.D(sig00000688),
.Q(sig000001ac)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fe (
.C(clk),
.CE(sig00000001),
.D(sig00000687),
.Q(sig000001ab)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ff (
.C(clk),
.CE(sig00000001),
.D(sig00000686),
.Q(sig000001aa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000300 (
.C(clk),
.CE(sig00000001),
.D(sig00000685),
.Q(sig000001a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000301 (
.C(clk),
.CE(sig00000001),
.D(sig00000684),
.Q(sig000001a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000302 (
.C(clk),
.CE(sig00000001),
.D(sig00000683),
.Q(sig000001a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000303 (
.C(clk),
.CE(sig00000001),
.D(sig00000682),
.Q(sig000001a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000304 (
.C(clk),
.CE(sig00000001),
.D(sig00000681),
.Q(sig000001a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000305 (
.C(clk),
.CE(sig00000001),
.D(sig00000680),
.Q(sig000001a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000306 (
.C(clk),
.CE(sig00000001),
.D(sig0000067f),
.Q(sig000001a3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000307 (
.C(clk),
.CE(sig00000001),
.D(sig0000067e),
.Q(sig000001a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000308 (
.C(clk),
.CE(sig00000001),
.D(sig0000067d),
.Q(sig000001a1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000309 (
.C(clk),
.CE(sig00000001),
.D(sig0000067c),
.Q(sig000001a0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030a (
.C(clk),
.CE(sig00000001),
.D(sig0000067b),
.Q(sig0000019f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030b (
.C(clk),
.CE(sig00000001),
.D(sig0000067a),
.Q(sig0000019e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030c (
.C(clk),
.CE(sig00000001),
.D(sig00000679),
.Q(sig0000019d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030d (
.C(clk),
.CE(sig00000001),
.D(sig00000678),
.Q(sig0000019c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030e (
.C(clk),
.CE(sig00000001),
.D(sig00000677),
.Q(sig0000019b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030f (
.C(clk),
.CE(sig00000001),
.D(sig00000676),
.Q(sig0000019a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000310 (
.C(clk),
.CE(sig00000001),
.D(sig00000675),
.Q(sig00000199)
);
FDE #(
.INIT ( 1'b0 ))
blk00000311 (
.C(clk),
.CE(sig00000001),
.D(sig00000674),
.Q(sig00000198)
);
FDE #(
.INIT ( 1'b0 ))
blk00000312 (
.C(clk),
.CE(sig00000001),
.D(sig00000673),
.Q(sig00000197)
);
FDE #(
.INIT ( 1'b0 ))
blk00000313 (
.C(clk),
.CE(sig00000001),
.D(sig00000672),
.Q(sig00000196)
);
FDE #(
.INIT ( 1'b0 ))
blk00000314 (
.C(clk),
.CE(sig00000001),
.D(sig00000671),
.Q(sig00000195)
);
FDE #(
.INIT ( 1'b0 ))
blk00000315 (
.C(clk),
.CE(sig00000001),
.D(sig00000670),
.Q(sig00000194)
);
FDE #(
.INIT ( 1'b0 ))
blk00000316 (
.C(clk),
.CE(sig00000001),
.D(sig0000066f),
.Q(sig00000193)
);
FDE #(
.INIT ( 1'b0 ))
blk00000317 (
.C(clk),
.CE(sig00000001),
.D(sig0000066e),
.Q(sig00000192)
);
FDE #(
.INIT ( 1'b0 ))
blk00000318 (
.C(clk),
.CE(sig00000001),
.D(sig0000066d),
.Q(sig00000191)
);
FDE #(
.INIT ( 1'b0 ))
blk00000319 (
.C(clk),
.CE(sig00000001),
.D(sig0000066c),
.Q(sig00000190)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031a (
.C(clk),
.CE(sig00000001),
.D(sig0000066b),
.Q(sig0000018f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031b (
.C(clk),
.CE(sig00000001),
.D(sig0000066a),
.Q(sig0000018e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031c (
.C(clk),
.CE(sig00000001),
.D(sig00000669),
.Q(sig0000018d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031d (
.C(clk),
.CE(sig00000001),
.D(sig00000668),
.Q(sig0000018c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031e (
.C(clk),
.CE(sig00000001),
.D(sig00000667),
.Q(sig0000018b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031f (
.C(clk),
.CE(sig00000001),
.D(sig00000072),
.Q(sig00000002)
);
FDE #(
.INIT ( 1'b0 ))
blk00000320 (
.C(clk),
.CE(sig00000001),
.D(sig00000073),
.Q(sig00000003)
);
FDE #(
.INIT ( 1'b0 ))
blk00000321 (
.C(clk),
.CE(sig00000001),
.D(sig00000074),
.Q(sig00000004)
);
FDE #(
.INIT ( 1'b0 ))
blk00000322 (
.C(clk),
.CE(sig00000001),
.D(sig00000075),
.Q(sig00000005)
);
FDE #(
.INIT ( 1'b0 ))
blk00000323 (
.C(clk),
.CE(sig00000001),
.D(sig00000076),
.Q(sig00000006)
);
FDE #(
.INIT ( 1'b0 ))
blk00000324 (
.C(clk),
.CE(sig00000001),
.D(sig00000077),
.Q(sig00000007)
);
FDE #(
.INIT ( 1'b0 ))
blk00000325 (
.C(clk),
.CE(sig00000001),
.D(sig00000078),
.Q(sig00000008)
);
FDE #(
.INIT ( 1'b0 ))
blk00000326 (
.C(clk),
.CE(sig00000001),
.D(sig00000079),
.Q(sig00000009)
);
FDE #(
.INIT ( 1'b0 ))
blk00000327 (
.C(clk),
.CE(sig00000001),
.D(sig0000007a),
.Q(sig0000000a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000328 (
.C(clk),
.CE(sig00000001),
.D(sig0000007b),
.Q(sig0000000b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000329 (
.C(clk),
.CE(sig00000001),
.D(sig0000007c),
.Q(sig0000000c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032a (
.C(clk),
.CE(sig00000001),
.D(sig0000007d),
.Q(sig0000000d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032b (
.C(clk),
.CE(sig00000001),
.D(sig0000007e),
.Q(sig0000000e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032c (
.C(clk),
.CE(sig00000001),
.D(sig0000007f),
.Q(sig0000000f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032d (
.C(clk),
.CE(sig00000001),
.D(sig00000080),
.Q(sig00000010)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032e (
.C(clk),
.CE(sig00000001),
.D(sig00000081),
.Q(sig00000011)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032f (
.C(clk),
.CE(sig00000001),
.D(sig00000082),
.Q(sig00000012)
);
FDE #(
.INIT ( 1'b0 ))
blk00000330 (
.C(clk),
.CE(sig00000001),
.D(sig00000083),
.Q(sig00000013)
);
FDE #(
.INIT ( 1'b0 ))
blk00000331 (
.C(clk),
.CE(sig00000001),
.D(sig00000084),
.Q(sig00000014)
);
FDE #(
.INIT ( 1'b0 ))
blk00000332 (
.C(clk),
.CE(sig00000001),
.D(sig00000085),
.Q(sig00000015)
);
FDE #(
.INIT ( 1'b0 ))
blk00000333 (
.C(clk),
.CE(sig00000001),
.D(sig00000086),
.Q(sig00000016)
);
FDE #(
.INIT ( 1'b0 ))
blk00000334 (
.C(clk),
.CE(sig00000001),
.D(sig00000087),
.Q(sig00000017)
);
FDE #(
.INIT ( 1'b0 ))
blk00000335 (
.C(clk),
.CE(sig00000001),
.D(sig00000088),
.Q(sig00000018)
);
FDE #(
.INIT ( 1'b0 ))
blk00000336 (
.C(clk),
.CE(sig00000001),
.D(sig00000089),
.Q(sig00000019)
);
FDE #(
.INIT ( 1'b0 ))
blk00000337 (
.C(clk),
.CE(sig00000001),
.D(sig0000008a),
.Q(sig0000001a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000338 (
.C(clk),
.CE(sig00000001),
.D(sig0000008b),
.Q(sig0000001b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000339 (
.C(clk),
.CE(sig00000001),
.D(sig0000008c),
.Q(sig0000001c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033a (
.C(clk),
.CE(sig00000001),
.D(sig0000008d),
.Q(sig0000001d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033b (
.C(clk),
.CE(sig00000001),
.D(sig0000008e),
.Q(sig0000001e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033c (
.C(clk),
.CE(sig00000001),
.D(sig0000008f),
.Q(sig0000001f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033d (
.C(clk),
.CE(sig00000001),
.D(sig00000090),
.Q(sig00000020)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033e (
.C(clk),
.CE(sig00000001),
.D(sig00000091),
.Q(sig00000021)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033f (
.C(clk),
.CE(sig00000001),
.D(sig00000092),
.Q(sig00000022)
);
FDE #(
.INIT ( 1'b0 ))
blk00000340 (
.C(clk),
.CE(sig00000001),
.D(sig00000093),
.Q(sig00000023)
);
FDE #(
.INIT ( 1'b0 ))
blk00000341 (
.C(clk),
.CE(sig00000001),
.D(sig00000094),
.Q(sig00000024)
);
FDE #(
.INIT ( 1'b0 ))
blk00000342 (
.C(clk),
.CE(sig00000001),
.D(sig00000095),
.Q(sig00000025)
);
FDE #(
.INIT ( 1'b0 ))
blk00000343 (
.C(clk),
.CE(sig00000001),
.D(sig00000096),
.Q(sig00000026)
);
FDE #(
.INIT ( 1'b0 ))
blk00000344 (
.C(clk),
.CE(sig00000001),
.D(sig00000097),
.Q(sig00000027)
);
FDE #(
.INIT ( 1'b0 ))
blk00000345 (
.C(clk),
.CE(sig00000001),
.D(sig00000098),
.Q(sig00000028)
);
FDE #(
.INIT ( 1'b0 ))
blk00000346 (
.C(clk),
.CE(sig00000001),
.D(sig00000099),
.Q(sig00000029)
);
FDE #(
.INIT ( 1'b0 ))
blk00000347 (
.C(clk),
.CE(sig00000001),
.D(sig0000009a),
.Q(sig0000002a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000348 (
.C(clk),
.CE(sig00000001),
.D(sig0000009b),
.Q(sig0000002b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000349 (
.C(clk),
.CE(sig00000001),
.D(sig0000009c),
.Q(sig0000002c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034a (
.C(clk),
.CE(sig00000001),
.D(sig0000009d),
.Q(sig0000002d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034b (
.C(clk),
.CE(sig00000001),
.D(sig0000009e),
.Q(sig0000002e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034c (
.C(clk),
.CE(sig00000001),
.D(sig0000009f),
.Q(sig0000002f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034d (
.C(clk),
.CE(sig00000001),
.D(sig000000a0),
.Q(sig00000030)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034e (
.C(clk),
.CE(sig00000001),
.D(sig000000a1),
.Q(sig00000031)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034f (
.C(clk),
.CE(sig00000001),
.D(sig000000a2),
.Q(sig00000032)
);
FDE #(
.INIT ( 1'b0 ))
blk00000350 (
.C(clk),
.CE(sig00000001),
.D(sig000000a3),
.Q(sig00000033)
);
FDE #(
.INIT ( 1'b0 ))
blk00000351 (
.C(clk),
.CE(sig00000001),
.D(sig000000a4),
.Q(sig00000034)
);
FDE #(
.INIT ( 1'b0 ))
blk00000352 (
.C(clk),
.CE(sig00000001),
.D(sig000000a5),
.Q(sig00000035)
);
FDE #(
.INIT ( 1'b0 ))
blk00000353 (
.C(clk),
.CE(sig00000001),
.D(sig000000a6),
.Q(sig00000036)
);
FDE #(
.INIT ( 1'b0 ))
blk00000354 (
.C(clk),
.CE(sig00000001),
.D(sig000000a7),
.Q(sig00000037)
);
FDE #(
.INIT ( 1'b0 ))
blk00000355 (
.C(clk),
.CE(sig00000001),
.D(sig000000a8),
.Q(sig00000038)
);
FDE #(
.INIT ( 1'b0 ))
blk00000356 (
.C(clk),
.CE(sig00000001),
.D(sig000000a9),
.Q(sig00000039)
);
FDE #(
.INIT ( 1'b0 ))
blk00000357 (
.C(clk),
.CE(sig00000001),
.D(sig000000aa),
.Q(sig0000003a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000358 (
.C(clk),
.CE(sig00000001),
.D(sig000000ab),
.Q(sig0000003b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000359 (
.C(clk),
.CE(sig00000001),
.D(sig000000ac),
.Q(sig0000003c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035a (
.C(clk),
.CE(sig00000001),
.D(sig000000ad),
.Q(sig0000003d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035b (
.C(clk),
.CE(sig00000001),
.D(sig000000ae),
.Q(sig0000003e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035c (
.C(clk),
.CE(sig00000001),
.D(sig000000af),
.Q(sig0000003f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035d (
.C(clk),
.CE(sig00000001),
.D(sig000000b0),
.Q(sig00000040)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035e (
.C(clk),
.CE(sig00000001),
.D(sig000000b1),
.Q(sig00000041)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035f (
.C(clk),
.CE(sig00000001),
.D(sig000000b2),
.Q(sig00000042)
);
FDE #(
.INIT ( 1'b0 ))
blk00000360 (
.C(clk),
.CE(sig00000001),
.D(sig000000b3),
.Q(sig00000043)
);
FDE #(
.INIT ( 1'b0 ))
blk00000361 (
.C(clk),
.CE(sig00000001),
.D(sig000000b4),
.Q(sig00000044)
);
FDE #(
.INIT ( 1'b0 ))
blk00000362 (
.C(clk),
.CE(sig00000001),
.D(sig000000b5),
.Q(sig00000045)
);
FDE #(
.INIT ( 1'b0 ))
blk00000363 (
.C(clk),
.CE(sig00000001),
.D(sig000000b6),
.Q(sig00000046)
);
FDE #(
.INIT ( 1'b0 ))
blk00000364 (
.C(clk),
.CE(sig00000001),
.D(sig000000b7),
.Q(sig00000047)
);
FDE #(
.INIT ( 1'b0 ))
blk00000365 (
.C(clk),
.CE(sig00000001),
.D(sig000000b8),
.Q(sig00000048)
);
FDE #(
.INIT ( 1'b0 ))
blk00000366 (
.C(clk),
.CE(sig00000001),
.D(sig000000b9),
.Q(sig00000049)
);
FDE #(
.INIT ( 1'b0 ))
blk00000367 (
.C(clk),
.CE(sig00000001),
.D(sig000000ba),
.Q(sig0000004a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000368 (
.C(clk),
.CE(sig00000001),
.D(sig000000bb),
.Q(sig0000004b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000369 (
.C(clk),
.CE(sig00000001),
.D(sig000000bc),
.Q(sig0000004c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036a (
.C(clk),
.CE(sig00000001),
.D(sig000000bd),
.Q(sig0000004d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036b (
.C(clk),
.CE(sig00000001),
.D(sig000000be),
.Q(sig0000004e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036c (
.C(clk),
.CE(sig00000001),
.D(sig000000bf),
.Q(sig0000004f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036d (
.C(clk),
.CE(sig00000001),
.D(sig000000c0),
.Q(sig00000050)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036e (
.C(clk),
.CE(sig00000001),
.D(sig000000c1),
.Q(sig00000051)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036f (
.C(clk),
.CE(sig00000001),
.D(sig000000c2),
.Q(sig00000052)
);
FDE #(
.INIT ( 1'b0 ))
blk00000370 (
.C(clk),
.CE(sig00000001),
.D(sig000000c3),
.Q(sig00000053)
);
FDE #(
.INIT ( 1'b0 ))
blk00000371 (
.C(clk),
.CE(sig00000001),
.D(sig000000c4),
.Q(sig00000054)
);
FDE #(
.INIT ( 1'b0 ))
blk00000372 (
.C(clk),
.CE(sig00000001),
.D(sig000000c5),
.Q(sig00000055)
);
FDE #(
.INIT ( 1'b0 ))
blk00000373 (
.C(clk),
.CE(sig00000001),
.D(sig000000c6),
.Q(sig00000056)
);
FDE #(
.INIT ( 1'b0 ))
blk00000374 (
.C(clk),
.CE(sig00000001),
.D(sig000000c7),
.Q(sig00000057)
);
FDE #(
.INIT ( 1'b0 ))
blk00000375 (
.C(clk),
.CE(sig00000001),
.D(sig000000c8),
.Q(sig00000058)
);
FDE #(
.INIT ( 1'b0 ))
blk00000376 (
.C(clk),
.CE(sig00000001),
.D(sig000000c9),
.Q(sig00000059)
);
FDE #(
.INIT ( 1'b0 ))
blk00000377 (
.C(clk),
.CE(sig00000001),
.D(sig000000ca),
.Q(sig0000005a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000378 (
.C(clk),
.CE(sig00000001),
.D(sig000000cb),
.Q(sig0000005b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000379 (
.C(clk),
.CE(sig00000001),
.D(sig000000cc),
.Q(sig0000005c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037a (
.C(clk),
.CE(sig00000001),
.D(sig000000cd),
.Q(sig0000005d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037b (
.C(clk),
.CE(sig00000001),
.D(sig000000ce),
.Q(sig0000005e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037c (
.C(clk),
.CE(sig00000001),
.D(sig000000cf),
.Q(sig0000005f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037d (
.C(clk),
.CE(sig00000001),
.D(sig000000d0),
.Q(sig00000060)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037e (
.C(clk),
.CE(sig00000001),
.D(sig000000d1),
.Q(sig00000061)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037f (
.C(clk),
.CE(sig00000001),
.D(sig000000d2),
.Q(sig00000062)
);
FDE #(
.INIT ( 1'b0 ))
blk00000380 (
.C(clk),
.CE(sig00000001),
.D(sig000000d3),
.Q(sig00000063)
);
FDE #(
.INIT ( 1'b0 ))
blk00000381 (
.C(clk),
.CE(sig00000001),
.D(sig000000d4),
.Q(sig00000064)
);
FDE #(
.INIT ( 1'b0 ))
blk00000382 (
.C(clk),
.CE(sig00000001),
.D(sig000000d5),
.Q(sig00000065)
);
FDE #(
.INIT ( 1'b0 ))
blk00000383 (
.C(clk),
.CE(sig00000001),
.D(sig000000d6),
.Q(sig00000066)
);
FDE #(
.INIT ( 1'b0 ))
blk00000384 (
.C(clk),
.CE(sig00000001),
.D(sig000000d7),
.Q(sig00000067)
);
FDE #(
.INIT ( 1'b0 ))
blk00000385 (
.C(clk),
.CE(sig00000001),
.D(sig000000d8),
.Q(sig00000068)
);
FDE #(
.INIT ( 1'b0 ))
blk00000386 (
.C(clk),
.CE(sig00000001),
.D(sig000000d9),
.Q(sig00000069)
);
FDE #(
.INIT ( 1'b0 ))
blk00000387 (
.C(clk),
.CE(sig00000001),
.D(sig000000da),
.Q(sig0000006a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000388 (
.C(clk),
.CE(sig00000001),
.D(sig000000db),
.Q(sig0000006b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000389 (
.C(clk),
.CE(sig00000001),
.D(sig000000dc),
.Q(sig0000006c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038a (
.C(clk),
.CE(sig00000001),
.D(sig000000dd),
.Q(sig0000006d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038b (
.C(clk),
.CE(sig00000001),
.D(sig000000de),
.Q(sig0000006e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038c (
.C(clk),
.CE(sig00000001),
.D(sig000000df),
.Q(sig0000006f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038d (
.C(clk),
.CE(sig00000001),
.D(sig000000e0),
.Q(sig00000070)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038e (
.C(clk),
.CE(sig00000001),
.D(sig000000e1),
.Q(sig00000071)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038f (
.C(clk),
.CE(sig00000001),
.D(sig000001c1),
.Q(sig0000011e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000390 (
.C(clk),
.CE(sig00000001),
.D(sig000001c0),
.Q(sig0000011f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000391 (
.C(clk),
.CE(sig00000001),
.D(sig000001bf),
.Q(sig00000120)
);
FDE #(
.INIT ( 1'b0 ))
blk00000392 (
.C(clk),
.CE(sig00000001),
.D(sig000001be),
.Q(sig00000121)
);
FDE #(
.INIT ( 1'b0 ))
blk00000393 (
.C(clk),
.CE(sig00000001),
.D(sig000001bd),
.Q(sig00000122)
);
FDE #(
.INIT ( 1'b0 ))
blk00000394 (
.C(clk),
.CE(sig00000001),
.D(sig000001bc),
.Q(sig00000123)
);
FDE #(
.INIT ( 1'b0 ))
blk00000395 (
.C(clk),
.CE(sig00000001),
.D(sig000001bb),
.Q(sig00000124)
);
FDE #(
.INIT ( 1'b0 ))
blk00000396 (
.C(clk),
.CE(sig00000001),
.D(sig000001ba),
.Q(sig00000125)
);
FDE #(
.INIT ( 1'b0 ))
blk00000397 (
.C(clk),
.CE(sig00000001),
.D(sig000001b9),
.Q(sig00000126)
);
FDE #(
.INIT ( 1'b0 ))
blk00000398 (
.C(clk),
.CE(sig00000001),
.D(sig000001b8),
.Q(sig00000127)
);
FDE #(
.INIT ( 1'b0 ))
blk00000399 (
.C(clk),
.CE(sig00000001),
.D(sig000001b7),
.Q(sig00000128)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039a (
.C(clk),
.CE(sig00000001),
.D(sig000001b6),
.Q(sig00000129)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039b (
.C(clk),
.CE(sig00000001),
.D(sig000001b5),
.Q(sig0000012a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039c (
.C(clk),
.CE(sig00000001),
.D(sig000001b4),
.Q(sig0000012b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039d (
.C(clk),
.CE(sig00000001),
.D(sig000001b3),
.Q(sig0000012c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039e (
.C(clk),
.CE(sig00000001),
.D(sig000001b2),
.Q(sig0000012d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039f (
.C(clk),
.CE(sig00000001),
.D(sig000001b1),
.Q(sig0000012e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a0 (
.C(clk),
.CE(sig00000001),
.D(sig000001b0),
.Q(sig0000012f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a1 (
.C(clk),
.CE(sig00000001),
.D(sig000001af),
.Q(sig00000130)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a2 (
.C(clk),
.CE(sig00000001),
.D(sig000001ae),
.Q(sig00000131)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a3 (
.C(clk),
.CE(sig00000001),
.D(sig000001ad),
.Q(sig00000132)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a4 (
.C(clk),
.CE(sig00000001),
.D(sig000001ac),
.Q(sig00000133)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a5 (
.C(clk),
.CE(sig00000001),
.D(sig000001ab),
.Q(sig00000134)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a6 (
.C(clk),
.CE(sig00000001),
.D(sig000001aa),
.Q(sig00000135)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a7 (
.C(clk),
.CE(sig00000001),
.D(sig000001a9),
.Q(sig00000136)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a8 (
.C(clk),
.CE(sig00000001),
.D(sig000001a8),
.Q(sig00000137)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a9 (
.C(clk),
.CE(sig00000001),
.D(sig000001a7),
.Q(sig00000138)
);
FDE #(
.INIT ( 1'b0 ))
blk000003aa (
.C(clk),
.CE(sig00000001),
.D(sig000001a6),
.Q(sig00000139)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ab (
.C(clk),
.CE(sig00000001),
.D(sig000001a5),
.Q(sig0000013a)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ac (
.C(clk),
.CE(sig00000001),
.D(sig000001a4),
.Q(sig0000013b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ad (
.C(clk),
.CE(sig00000001),
.D(sig000001a3),
.Q(sig0000013c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ae (
.C(clk),
.CE(sig00000001),
.D(sig000001a2),
.Q(sig0000013d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003af (
.C(clk),
.CE(sig00000001),
.D(sig000001a1),
.Q(sig0000013e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b0 (
.C(clk),
.CE(sig00000001),
.D(sig000001a0),
.Q(sig0000013f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b1 (
.C(clk),
.CE(sig00000001),
.D(sig0000019f),
.Q(sig00000140)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b2 (
.C(clk),
.CE(sig00000001),
.D(sig0000019e),
.Q(sig00000141)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b3 (
.C(clk),
.CE(sig00000001),
.D(sig0000019d),
.Q(sig00000142)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b4 (
.C(clk),
.CE(sig00000001),
.D(sig0000019c),
.Q(sig00000143)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b5 (
.C(clk),
.CE(sig00000001),
.D(sig0000019b),
.Q(sig00000144)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b6 (
.C(clk),
.CE(sig00000001),
.D(sig0000019a),
.Q(sig00000145)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b7 (
.C(clk),
.CE(sig00000001),
.D(sig00000199),
.Q(sig00000146)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b8 (
.C(clk),
.CE(sig00000001),
.D(sig00000198),
.Q(sig00000147)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b9 (
.C(clk),
.CE(sig00000001),
.D(sig00000197),
.Q(sig00000148)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ba (
.C(clk),
.CE(sig00000001),
.D(sig00000196),
.Q(sig00000149)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bb (
.C(clk),
.CE(sig00000001),
.D(sig00000195),
.Q(sig0000014a)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bc (
.C(clk),
.CE(sig00000001),
.D(sig00000194),
.Q(sig0000014b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bd (
.C(clk),
.CE(sig00000001),
.D(sig00000193),
.Q(sig0000014c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003be (
.C(clk),
.CE(sig00000001),
.D(sig00000192),
.Q(sig0000014d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bf (
.C(clk),
.CE(sig00000001),
.D(sig00000191),
.Q(sig0000014e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c0 (
.C(clk),
.CE(sig00000001),
.D(sig00000190),
.Q(sig0000014f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c1 (
.C(clk),
.CE(sig00000001),
.D(sig0000018f),
.Q(sig00000150)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c2 (
.C(clk),
.CE(sig00000001),
.D(sig0000018e),
.Q(sig00000151)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c3 (
.C(clk),
.CE(sig00000001),
.D(sig0000018d),
.Q(sig00000152)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c4 (
.C(clk),
.CE(sig00000001),
.D(sig0000018c),
.Q(sig00000153)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c5 (
.C(clk),
.CE(sig00000001),
.D(sig0000018b),
.Q(sig00000154)
);
MUXF7 blk000003c6 (
.I0(sig000006c2),
.I1(sig000006c3),
.S(sig0000011a),
.O(NLW_blk000003c6_O_UNCONNECTED)
);
MUXF7 blk000003c7 (
.I0(sig000006c4),
.I1(sig000006c6),
.S(sig0000011a),
.O(sig000006c8)
);
MUXF7 blk000003c8 (
.I0(sig000006c5),
.I1(sig000006c7),
.S(sig0000011a),
.O(sig000006c9)
);
MUXF7 blk000003c9 (
.I0(sig000006ca),
.I1(sig000006ce),
.S(sig00000118),
.O(sig000006d1)
);
MUXF7 blk000003ca (
.I0(sig000006cb),
.I1(sig000006cf),
.S(sig00000118),
.O(sig000006d2)
);
MUXF7 blk000003cb (
.I0(sig000006cc),
.I1(sig000006d0),
.S(sig00000118),
.O(sig000006d3)
);
MUXF7 blk000003cc (
.I0(sig000006cd),
.I1(sig000006c3),
.S(sig00000118),
.O(NLW_blk000003cc_O_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003cd (
.C(clk),
.CE(sig00000001),
.D(sig000006c9),
.Q(sig0000011c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ce (
.C(clk),
.CE(sig00000001),
.D(sig000006c8),
.Q(sig0000011d)
);
FD #(
.INIT ( 1'b0 ))
blk000003cf (
.C(clk),
.D(sig000006d1),
.Q(sig000006e4)
);
FD #(
.INIT ( 1'b0 ))
blk000003d0 (
.C(clk),
.D(sig000006d2),
.Q(sig0000011a)
);
FD #(
.INIT ( 1'b0 ))
blk000003d1 (
.C(clk),
.D(sig000006d3),
.Q(sig000006e3)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d2 (
.C(clk),
.CE(sig00000001),
.D(sig0000011a),
.Q(sig00000187)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d3 (
.C(clk),
.CE(sig00000001),
.D(sig0000011b),
.Q(sig00000186)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d4 (
.C(clk),
.CE(sig00000001),
.D(sig000006d4),
.Q(sig00000157)
);
MUXCY blk000003d5 (
.CI(sig000006fb),
.DI(sig000006c3),
.S(sig000006dc),
.O(sig000006fa)
);
MUXCY blk000003d6 (
.CI(sig000006fc),
.DI(sig000006c3),
.S(sig000006db),
.O(sig000006fb)
);
MUXCY blk000003d7 (
.CI(sig000006fd),
.DI(sig000006c3),
.S(sig000006da),
.O(sig000006fc)
);
MUXCY blk000003d8 (
.CI(sig000006fe),
.DI(sig000006c3),
.S(sig000006d9),
.O(sig000006fd)
);
MUXCY blk000003d9 (
.CI(sig000006ff),
.DI(sig000006c3),
.S(sig000006d8),
.O(sig000006fe)
);
MUXCY blk000003da (
.CI(sig00000700),
.DI(sig000006c3),
.S(sig000006d7),
.O(sig000006ff)
);
MUXCY blk000003db (
.CI(sig00000701),
.DI(sig000006c3),
.S(sig000006d6),
.O(sig00000700)
);
MUXCY blk000003dc (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig000006d5),
.O(sig00000701)
);
FDE #(
.INIT ( 1'b0 ))
blk000003dd (
.C(clk),
.CE(sig00000001),
.D(sig000006fa),
.Q(sig00000118)
);
FDE #(
.INIT ( 1'b0 ))
blk000003de (
.C(clk),
.CE(sig00000001),
.D(sig000006fb),
.Q(sig000006f5)
);
FDE #(
.INIT ( 1'b0 ))
blk000003df (
.C(clk),
.CE(sig00000001),
.D(sig000006fc),
.Q(sig000006f4)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e0 (
.C(clk),
.CE(sig00000001),
.D(sig000006fd),
.Q(sig000006f3)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e1 (
.C(clk),
.CE(sig00000001),
.D(sig000006fe),
.Q(sig000006f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e2 (
.C(clk),
.CE(sig00000001),
.D(sig000006ff),
.Q(sig000006f8)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e3 (
.C(clk),
.CE(sig00000001),
.D(sig00000700),
.Q(sig000006f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e4 (
.C(clk),
.CE(sig00000001),
.D(sig00000701),
.Q(sig000006f6)
);
MUXCY blk000003e5 (
.CI(sig00000703),
.DI(sig000006c3),
.S(sig000006e2),
.O(sig00000702)
);
MUXCY blk000003e6 (
.CI(sig00000704),
.DI(sig000006c3),
.S(sig000006e1),
.O(sig00000703)
);
MUXCY blk000003e7 (
.CI(sig00000705),
.DI(sig000006c3),
.S(sig000006e0),
.O(sig00000704)
);
MUXCY blk000003e8 (
.CI(sig00000706),
.DI(sig000006c3),
.S(sig000006df),
.O(sig00000705)
);
MUXCY blk000003e9 (
.CI(sig00000707),
.DI(sig000006c3),
.S(sig000006de),
.O(sig00000706)
);
MUXCY blk000003ea (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig000006dd),
.O(sig00000707)
);
FDE #(
.INIT ( 1'b0 ))
blk000003eb (
.C(clk),
.CE(sig00000001),
.D(sig00000702),
.Q(sig000006f2)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ec (
.C(clk),
.CE(sig00000001),
.D(sig00000703),
.Q(sig000006ed)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ed (
.C(clk),
.CE(sig00000001),
.D(sig00000704),
.Q(sig000006f1)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ee (
.C(clk),
.CE(sig00000001),
.D(sig00000705),
.Q(sig000006f0)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ef (
.C(clk),
.CE(sig00000001),
.D(sig00000706),
.Q(sig000006ef)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f0 (
.C(clk),
.CE(sig00000001),
.D(sig00000707),
.Q(sig000006ee)
);
MUXF7 blk000003f1 (
.I0(sig00000718),
.I1(sig00000710),
.S(sig00000118),
.O(sig00000708)
);
MUXF7 blk000003f2 (
.I0(sig00000719),
.I1(sig00000711),
.S(sig00000118),
.O(sig00000709)
);
MUXF7 blk000003f3 (
.I0(sig0000071a),
.I1(sig00000712),
.S(sig00000118),
.O(sig0000070a)
);
MUXF7 blk000003f4 (
.I0(sig0000071b),
.I1(sig00000713),
.S(sig00000118),
.O(sig0000070b)
);
MUXF7 blk000003f5 (
.I0(sig0000071c),
.I1(sig00000714),
.S(sig00000118),
.O(sig0000070c)
);
MUXF7 blk000003f6 (
.I0(sig0000071d),
.I1(sig00000715),
.S(sig00000118),
.O(sig0000070d)
);
MUXF7 blk000003f7 (
.I0(sig0000071e),
.I1(sig00000716),
.S(sig00000118),
.O(sig0000070e)
);
MUXF7 blk000003f8 (
.I0(sig0000071f),
.I1(sig00000717),
.S(sig00000118),
.O(sig0000070f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f9 (
.C(clk),
.CE(sig00000001),
.D(sig00000708),
.Q(sig000006e6)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fa (
.C(clk),
.CE(sig00000001),
.D(sig00000709),
.Q(sig000006e5)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fb (
.C(clk),
.CE(sig00000001),
.D(sig0000070a),
.Q(sig000006e8)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fc (
.C(clk),
.CE(sig00000001),
.D(sig0000070b),
.Q(sig000006e7)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fd (
.C(clk),
.CE(sig00000001),
.D(sig0000070c),
.Q(sig000006ea)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fe (
.C(clk),
.CE(sig00000001),
.D(sig0000070d),
.Q(sig000006e9)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ff (
.C(clk),
.CE(sig00000001),
.D(sig0000070e),
.Q(sig000006ec)
);
FDE #(
.INIT ( 1'b0 ))
blk00000400 (
.C(clk),
.CE(sig00000001),
.D(sig0000070f),
.Q(sig000006eb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000401 (
.C(clk),
.CE(sig00000001),
.D(sig00000769),
.Q(sig00000761)
);
FDE #(
.INIT ( 1'b0 ))
blk00000402 (
.C(clk),
.CE(sig00000001),
.D(sig0000076a),
.Q(sig00000762)
);
FDE #(
.INIT ( 1'b0 ))
blk00000403 (
.C(clk),
.CE(sig00000001),
.D(sig0000076b),
.Q(sig00000763)
);
FDE #(
.INIT ( 1'b0 ))
blk00000404 (
.C(clk),
.CE(sig00000001),
.D(sig0000076c),
.Q(sig00000764)
);
FDE #(
.INIT ( 1'b0 ))
blk00000405 (
.C(clk),
.CE(sig00000001),
.D(sig0000076d),
.Q(sig00000765)
);
FDE #(
.INIT ( 1'b0 ))
blk00000406 (
.C(clk),
.CE(sig00000001),
.D(sig0000076e),
.Q(sig00000766)
);
FDE #(
.INIT ( 1'b0 ))
blk00000407 (
.C(clk),
.CE(sig00000001),
.D(sig0000076f),
.Q(sig00000760)
);
FDE #(
.INIT ( 1'b0 ))
blk00000408 (
.C(clk),
.CE(sig00000001),
.D(sig00000720),
.Q(sig00000768)
);
MUXCY blk00000409 (
.CI(sig000006c3),
.DI(sig000006c3),
.S(sig00000819),
.O(sig00000721)
);
XORCY blk0000040a (
.CI(sig000006c3),
.LI(sig00000819),
.O(sig00000722)
);
MUXCY blk0000040b (
.CI(sig00000721),
.DI(sig000006c3),
.S(sig0000081a),
.O(sig00000723)
);
XORCY blk0000040c (
.CI(sig00000721),
.LI(sig0000081a),
.O(sig00000724)
);
MUXCY blk0000040d (
.CI(sig00000723),
.DI(sig000006c3),
.S(sig0000081b),
.O(sig00000725)
);
XORCY blk0000040e (
.CI(sig00000723),
.LI(sig0000081b),
.O(sig00000726)
);
MUXCY blk0000040f (
.CI(sig00000725),
.DI(sig000006c3),
.S(sig0000081c),
.O(sig00000727)
);
XORCY blk00000410 (
.CI(sig00000725),
.LI(sig0000081c),
.O(sig00000728)
);
MUXCY blk00000411 (
.CI(sig00000727),
.DI(sig000006c3),
.S(sig0000081d),
.O(sig00000729)
);
XORCY blk00000412 (
.CI(sig00000727),
.LI(sig0000081d),
.O(sig0000072a)
);
MUXCY blk00000413 (
.CI(sig00000729),
.DI(sig000006c3),
.S(sig0000081e),
.O(sig0000072b)
);
XORCY blk00000414 (
.CI(sig00000729),
.LI(sig0000081e),
.O(sig0000072c)
);
MUXCY blk00000415 (
.CI(sig0000072b),
.DI(sig000006c3),
.S(sig0000081f),
.O(sig0000072d)
);
XORCY blk00000416 (
.CI(sig0000072b),
.LI(sig0000081f),
.O(NLW_blk00000416_O_UNCONNECTED)
);
MUXCY blk00000417 (
.CI(sig0000072d),
.DI(sig00000001),
.S(sig00000001),
.O(sig0000072e)
);
XORCY blk00000418 (
.CI(sig0000072d),
.LI(sig00000001),
.O(NLW_blk00000418_O_UNCONNECTED)
);
MUXCY blk00000419 (
.CI(sig0000072e),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000072f)
);
XORCY blk0000041a (
.CI(sig0000072e),
.LI(sig000006c3),
.O(NLW_blk0000041a_O_UNCONNECTED)
);
MUXCY blk0000041b (
.CI(sig0000072f),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000730)
);
XORCY blk0000041c (
.CI(sig0000072f),
.LI(sig000006c3),
.O(NLW_blk0000041c_O_UNCONNECTED)
);
MUXCY blk0000041d (
.CI(sig00000730),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000731)
);
XORCY blk0000041e (
.CI(sig00000730),
.LI(sig000006c3),
.O(NLW_blk0000041e_O_UNCONNECTED)
);
MUXCY blk0000041f (
.CI(sig00000731),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000732)
);
XORCY blk00000420 (
.CI(sig00000731),
.LI(sig000006c3),
.O(NLW_blk00000420_O_UNCONNECTED)
);
MUXCY blk00000421 (
.CI(sig00000732),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000733)
);
XORCY blk00000422 (
.CI(sig00000732),
.LI(sig000006c3),
.O(NLW_blk00000422_O_UNCONNECTED)
);
MUXCY blk00000423 (
.CI(sig00000733),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000734)
);
XORCY blk00000424 (
.CI(sig00000733),
.LI(sig000006c3),
.O(NLW_blk00000424_O_UNCONNECTED)
);
MUXCY blk00000425 (
.CI(sig00000734),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000735)
);
XORCY blk00000426 (
.CI(sig00000734),
.LI(sig000006c3),
.O(NLW_blk00000426_O_UNCONNECTED)
);
MUXCY blk00000427 (
.CI(sig00000735),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000736)
);
XORCY blk00000428 (
.CI(sig00000735),
.LI(sig000006c3),
.O(NLW_blk00000428_O_UNCONNECTED)
);
MUXCY blk00000429 (
.CI(sig00000736),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000737)
);
XORCY blk0000042a (
.CI(sig00000736),
.LI(sig000006c3),
.O(NLW_blk0000042a_O_UNCONNECTED)
);
MUXCY blk0000042b (
.CI(sig00000737),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000738)
);
XORCY blk0000042c (
.CI(sig00000737),
.LI(sig000006c3),
.O(NLW_blk0000042c_O_UNCONNECTED)
);
XORCY blk0000042d (
.CI(sig00000738),
.LI(sig000006c3),
.O(NLW_blk0000042d_O_UNCONNECTED)
);
MUXCY blk0000042e (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig00000820),
.O(sig00000739)
);
XORCY blk0000042f (
.CI(sig00000001),
.LI(sig00000820),
.O(sig0000073a)
);
MUXCY blk00000430 (
.CI(sig00000739),
.DI(sig000006c3),
.S(sig00000821),
.O(sig0000073b)
);
XORCY blk00000431 (
.CI(sig00000739),
.LI(sig00000821),
.O(sig0000073c)
);
MUXCY blk00000432 (
.CI(sig0000073b),
.DI(sig000006c3),
.S(sig00000822),
.O(sig0000073d)
);
XORCY blk00000433 (
.CI(sig0000073b),
.LI(sig00000822),
.O(sig0000073e)
);
MUXCY blk00000434 (
.CI(sig0000073d),
.DI(sig000006c3),
.S(sig00000823),
.O(sig0000073f)
);
XORCY blk00000435 (
.CI(sig0000073d),
.LI(sig00000823),
.O(sig00000740)
);
MUXCY blk00000436 (
.CI(sig0000073f),
.DI(sig000006c3),
.S(sig00000824),
.O(sig00000741)
);
XORCY blk00000437 (
.CI(sig0000073f),
.LI(sig00000824),
.O(sig00000742)
);
MUXCY blk00000438 (
.CI(sig00000741),
.DI(sig000006c3),
.S(sig00000825),
.O(sig00000743)
);
XORCY blk00000439 (
.CI(sig00000741),
.LI(sig00000825),
.O(sig00000744)
);
MUXCY blk0000043a (
.CI(sig00000743),
.DI(sig000006c3),
.S(sig00000826),
.O(sig00000745)
);
XORCY blk0000043b (
.CI(sig00000743),
.LI(sig00000826),
.O(NLW_blk0000043b_O_UNCONNECTED)
);
MUXCY blk0000043c (
.CI(sig00000745),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000746)
);
XORCY blk0000043d (
.CI(sig00000745),
.LI(sig00000001),
.O(sig00000747)
);
MUXCY blk0000043e (
.CI(sig00000746),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000748)
);
XORCY blk0000043f (
.CI(sig00000746),
.LI(sig000006c3),
.O(NLW_blk0000043f_O_UNCONNECTED)
);
MUXCY blk00000440 (
.CI(sig00000748),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000749)
);
XORCY blk00000441 (
.CI(sig00000748),
.LI(sig000006c3),
.O(NLW_blk00000441_O_UNCONNECTED)
);
MUXCY blk00000442 (
.CI(sig00000749),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074a)
);
XORCY blk00000443 (
.CI(sig00000749),
.LI(sig000006c3),
.O(NLW_blk00000443_O_UNCONNECTED)
);
MUXCY blk00000444 (
.CI(sig0000074a),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074b)
);
XORCY blk00000445 (
.CI(sig0000074a),
.LI(sig000006c3),
.O(NLW_blk00000445_O_UNCONNECTED)
);
MUXCY blk00000446 (
.CI(sig0000074b),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074c)
);
XORCY blk00000447 (
.CI(sig0000074b),
.LI(sig000006c3),
.O(NLW_blk00000447_O_UNCONNECTED)
);
MUXCY blk00000448 (
.CI(sig0000074c),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074d)
);
XORCY blk00000449 (
.CI(sig0000074c),
.LI(sig000006c3),
.O(NLW_blk00000449_O_UNCONNECTED)
);
MUXCY blk0000044a (
.CI(sig0000074d),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074e)
);
XORCY blk0000044b (
.CI(sig0000074d),
.LI(sig000006c3),
.O(NLW_blk0000044b_O_UNCONNECTED)
);
MUXCY blk0000044c (
.CI(sig0000074e),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074f)
);
XORCY blk0000044d (
.CI(sig0000074e),
.LI(sig000006c3),
.O(NLW_blk0000044d_O_UNCONNECTED)
);
MUXCY blk0000044e (
.CI(sig0000074f),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000750)
);
XORCY blk0000044f (
.CI(sig0000074f),
.LI(sig000006c3),
.O(NLW_blk0000044f_O_UNCONNECTED)
);
MUXCY blk00000450 (
.CI(sig00000750),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000751)
);
XORCY blk00000451 (
.CI(sig00000750),
.LI(sig000006c3),
.O(NLW_blk00000451_O_UNCONNECTED)
);
XORCY blk00000452 (
.CI(sig00000751),
.LI(sig000006c3),
.O(NLW_blk00000452_O_UNCONNECTED)
);
FD #(
.INIT ( 1'b0 ))
blk00000453 (
.C(clk),
.D(sig00000117),
.Q(sig0000076f)
);
FD #(
.INIT ( 1'b0 ))
blk00000454 (
.C(clk),
.D(sig00000116),
.Q(sig0000076e)
);
FD #(
.INIT ( 1'b0 ))
blk00000455 (
.C(clk),
.D(sig00000115),
.Q(sig0000076d)
);
FD #(
.INIT ( 1'b0 ))
blk00000456 (
.C(clk),
.D(sig00000114),
.Q(sig0000076c)
);
FD #(
.INIT ( 1'b0 ))
blk00000457 (
.C(clk),
.D(sig00000113),
.Q(sig0000076b)
);
FD #(
.INIT ( 1'b0 ))
blk00000458 (
.C(clk),
.D(sig00000112),
.Q(sig0000076a)
);
FD #(
.INIT ( 1'b0 ))
blk00000459 (
.C(clk),
.D(sig00000111),
.Q(sig00000769)
);
FD #(
.INIT ( 1'b0 ))
blk0000045a (
.C(clk),
.D(sig00000110),
.Q(sig00000752)
);
FD #(
.INIT ( 1'b0 ))
blk0000045b (
.C(clk),
.D(sig0000010f),
.Q(sig0000079d)
);
FD #(
.INIT ( 1'b0 ))
blk0000045c (
.C(clk),
.D(sig0000010e),
.Q(sig0000079c)
);
FD #(
.INIT ( 1'b0 ))
blk0000045d (
.C(clk),
.D(sig0000010d),
.Q(sig0000079b)
);
FD #(
.INIT ( 1'b0 ))
blk0000045e (
.C(clk),
.D(sig0000010c),
.Q(sig0000079a)
);
FD #(
.INIT ( 1'b0 ))
blk0000045f (
.C(clk),
.D(sig0000010b),
.Q(sig00000799)
);
FD #(
.INIT ( 1'b0 ))
blk00000460 (
.C(clk),
.D(sig0000010a),
.Q(sig00000798)
);
FD #(
.INIT ( 1'b0 ))
blk00000461 (
.C(clk),
.D(sig00000109),
.Q(sig00000797)
);
FD #(
.INIT ( 1'b0 ))
blk00000462 (
.C(clk),
.D(sig00000108),
.Q(sig00000796)
);
FD #(
.INIT ( 1'b0 ))
blk00000463 (
.C(clk),
.D(sig00000107),
.Q(sig00000795)
);
FD #(
.INIT ( 1'b0 ))
blk00000464 (
.C(clk),
.D(sig00000106),
.Q(sig00000794)
);
FD #(
.INIT ( 1'b0 ))
blk00000465 (
.C(clk),
.D(sig00000105),
.Q(sig00000793)
);
FD #(
.INIT ( 1'b0 ))
blk00000466 (
.C(clk),
.D(sig00000104),
.Q(sig00000792)
);
FD #(
.INIT ( 1'b0 ))
blk00000467 (
.C(clk),
.D(sig00000103),
.Q(sig00000791)
);
FD #(
.INIT ( 1'b0 ))
blk00000468 (
.C(clk),
.D(sig00000102),
.Q(sig00000790)
);
FD #(
.INIT ( 1'b0 ))
blk00000469 (
.C(clk),
.D(sig00000101),
.Q(sig0000078f)
);
FD #(
.INIT ( 1'b0 ))
blk0000046a (
.C(clk),
.D(sig00000100),
.Q(sig0000078e)
);
FD #(
.INIT ( 1'b0 ))
blk0000046b (
.C(clk),
.D(sig000000ff),
.Q(sig0000078d)
);
FD #(
.INIT ( 1'b0 ))
blk0000046c (
.C(clk),
.D(sig000000fe),
.Q(sig0000078c)
);
FD #(
.INIT ( 1'b0 ))
blk0000046d (
.C(clk),
.D(sig000000fd),
.Q(sig0000078b)
);
FD #(
.INIT ( 1'b0 ))
blk0000046e (
.C(clk),
.D(sig000000fc),
.Q(sig0000078a)
);
FD #(
.INIT ( 1'b0 ))
blk0000046f (
.C(clk),
.D(sig000000fb),
.Q(sig00000789)
);
FD #(
.INIT ( 1'b0 ))
blk00000470 (
.C(clk),
.D(sig000000fa),
.Q(sig00000788)
);
FD #(
.INIT ( 1'b0 ))
blk00000471 (
.C(clk),
.D(sig000000f9),
.Q(sig00000787)
);
FD #(
.INIT ( 1'b0 ))
blk00000472 (
.C(clk),
.D(sig000000f8),
.Q(sig00000786)
);
FD #(
.INIT ( 1'b0 ))
blk00000473 (
.C(clk),
.D(sig000000f7),
.Q(sig00000785)
);
FD #(
.INIT ( 1'b0 ))
blk00000474 (
.C(clk),
.D(sig000000f6),
.Q(sig00000784)
);
FD #(
.INIT ( 1'b0 ))
blk00000475 (
.C(clk),
.D(sig000000f5),
.Q(sig00000783)
);
FD #(
.INIT ( 1'b0 ))
blk00000476 (
.C(clk),
.D(sig000000f4),
.Q(sig00000782)
);
FD #(
.INIT ( 1'b0 ))
blk00000477 (
.C(clk),
.D(sig000000f3),
.Q(sig00000781)
);
FD #(
.INIT ( 1'b0 ))
blk00000478 (
.C(clk),
.D(sig000000f2),
.Q(sig00000780)
);
FD #(
.INIT ( 1'b0 ))
blk00000479 (
.C(clk),
.D(sig000000f1),
.Q(sig0000077f)
);
FD #(
.INIT ( 1'b0 ))
blk0000047a (
.C(clk),
.D(sig000000f0),
.Q(sig0000077e)
);
FD #(
.INIT ( 1'b0 ))
blk0000047b (
.C(clk),
.D(sig000000ef),
.Q(sig0000077d)
);
FD #(
.INIT ( 1'b0 ))
blk0000047c (
.C(clk),
.D(sig000000ee),
.Q(sig0000077c)
);
FD #(
.INIT ( 1'b0 ))
blk0000047d (
.C(clk),
.D(sig000000ed),
.Q(sig0000077b)
);
FD #(
.INIT ( 1'b0 ))
blk0000047e (
.C(clk),
.D(sig000000ec),
.Q(sig0000077a)
);
FD #(
.INIT ( 1'b0 ))
blk0000047f (
.C(clk),
.D(sig000000eb),
.Q(sig00000779)
);
FD #(
.INIT ( 1'b0 ))
blk00000480 (
.C(clk),
.D(sig000000ea),
.Q(sig00000778)
);
FD #(
.INIT ( 1'b0 ))
blk00000481 (
.C(clk),
.D(sig000000e9),
.Q(sig00000777)
);
FD #(
.INIT ( 1'b0 ))
blk00000482 (
.C(clk),
.D(sig000000e8),
.Q(sig00000776)
);
FD #(
.INIT ( 1'b0 ))
blk00000483 (
.C(clk),
.D(sig000000e7),
.Q(sig00000775)
);
FD #(
.INIT ( 1'b0 ))
blk00000484 (
.C(clk),
.D(sig000000e6),
.Q(sig00000774)
);
FD #(
.INIT ( 1'b0 ))
blk00000485 (
.C(clk),
.D(sig000000e5),
.Q(sig00000773)
);
FD #(
.INIT ( 1'b0 ))
blk00000486 (
.C(clk),
.D(sig000000e4),
.Q(sig00000772)
);
FD #(
.INIT ( 1'b0 ))
blk00000487 (
.C(clk),
.D(sig000000e3),
.Q(sig00000771)
);
FD #(
.INIT ( 1'b0 ))
blk00000488 (
.C(clk),
.D(sig000000e2),
.Q(sig00000770)
);
FDE #(
.INIT ( 1'b0 ))
blk00000489 (
.C(clk),
.CE(sig00000001),
.D(sig0000072c),
.Q(sig0000075f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048a (
.C(clk),
.CE(sig00000001),
.D(sig0000072a),
.Q(sig0000075e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048b (
.C(clk),
.CE(sig00000001),
.D(sig00000728),
.Q(sig0000075d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048c (
.C(clk),
.CE(sig00000001),
.D(sig00000726),
.Q(sig0000075c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048d (
.C(clk),
.CE(sig00000001),
.D(sig00000724),
.Q(sig0000075b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048e (
.C(clk),
.CE(sig00000001),
.D(sig00000722),
.Q(sig0000075a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048f (
.C(clk),
.CE(sig00000001),
.D(sig00000747),
.Q(sig00000759)
);
FDE #(
.INIT ( 1'b0 ))
blk00000490 (
.C(clk),
.CE(sig00000001),
.D(sig00000744),
.Q(sig00000758)
);
FDE #(
.INIT ( 1'b0 ))
blk00000491 (
.C(clk),
.CE(sig00000001),
.D(sig00000742),
.Q(sig00000757)
);
FDE #(
.INIT ( 1'b0 ))
blk00000492 (
.C(clk),
.CE(sig00000001),
.D(sig00000740),
.Q(sig00000756)
);
FDE #(
.INIT ( 1'b0 ))
blk00000493 (
.C(clk),
.CE(sig00000001),
.D(sig0000073e),
.Q(sig00000755)
);
FDE #(
.INIT ( 1'b0 ))
blk00000494 (
.C(clk),
.CE(sig00000001),
.D(sig0000073c),
.Q(sig00000754)
);
FDE #(
.INIT ( 1'b0 ))
blk00000495 (
.C(clk),
.CE(sig00000001),
.D(sig0000073a),
.Q(sig00000753)
);
XORCY blk00000496 (
.CI(sig0000079e),
.LI(sig000007f2),
.O(sig000007b3)
);
XORCY blk00000497 (
.CI(sig0000079f),
.LI(sig000007f1),
.O(sig000007b2)
);
MUXCY blk00000498 (
.CI(sig0000079f),
.DI(sig000006c3),
.S(sig000007f1),
.O(sig0000079e)
);
XORCY blk00000499 (
.CI(sig000007a0),
.LI(sig000007f0),
.O(sig000007b1)
);
MUXCY blk0000049a (
.CI(sig000007a0),
.DI(sig000006c3),
.S(sig000007f0),
.O(sig0000079f)
);
XORCY blk0000049b (
.CI(sig000007a1),
.LI(sig000007ef),
.O(sig000007b0)
);
MUXCY blk0000049c (
.CI(sig000007a1),
.DI(sig000006c3),
.S(sig000007ef),
.O(sig000007a0)
);
XORCY blk0000049d (
.CI(sig000007a2),
.LI(sig000007ee),
.O(sig000007af)
);
MUXCY blk0000049e (
.CI(sig000007a2),
.DI(sig000006c3),
.S(sig000007ee),
.O(sig000007a1)
);
XORCY blk0000049f (
.CI(sig000007a3),
.LI(sig000007ed),
.O(sig000007ae)
);
MUXCY blk000004a0 (
.CI(sig000007a3),
.DI(sig000006c3),
.S(sig000007ed),
.O(sig000007a2)
);
XORCY blk000004a1 (
.CI(sig000007a4),
.LI(sig000007ec),
.O(sig000007ad)
);
MUXCY blk000004a2 (
.CI(sig000007a4),
.DI(sig000006c3),
.S(sig000007ec),
.O(sig000007a3)
);
XORCY blk000004a3 (
.CI(sig000007a5),
.LI(sig000007eb),
.O(sig000007ac)
);
MUXCY blk000004a4 (
.CI(sig000007a5),
.DI(sig000006c3),
.S(sig000007eb),
.O(sig000007a4)
);
XORCY blk000004a5 (
.CI(sig000007a6),
.LI(sig000007ea),
.O(sig000007ab)
);
MUXCY blk000004a6 (
.CI(sig000007a6),
.DI(sig000006c3),
.S(sig000007ea),
.O(sig000007a5)
);
XORCY blk000004a7 (
.CI(sig000007a7),
.LI(sig000007e9),
.O(sig000007aa)
);
MUXCY blk000004a8 (
.CI(sig000007a7),
.DI(sig000006c3),
.S(sig000007e9),
.O(sig000007a6)
);
XORCY blk000004a9 (
.CI(sig000006c3),
.LI(sig000007a8),
.O(sig000007a9)
);
MUXCY blk000004aa (
.CI(sig000006c3),
.DI(sig000007e8),
.S(sig000007a8),
.O(sig000007a7)
);
FD blk000004ab (
.C(clk),
.D(sig000007b3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [10])
);
FD blk000004ac (
.C(clk),
.D(sig000007b2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [9])
);
FD blk000004ad (
.C(clk),
.D(sig000007b1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [8])
);
FD blk000004ae (
.C(clk),
.D(sig000007b0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [7])
);
FD blk000004af (
.C(clk),
.D(sig000007af),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [6])
);
FD blk000004b0 (
.C(clk),
.D(sig000007ae),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [5])
);
FD blk000004b1 (
.C(clk),
.D(sig000007ad),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [4])
);
FD blk000004b2 (
.C(clk),
.D(sig000007ac),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [3])
);
FD blk000004b3 (
.C(clk),
.D(sig000007ab),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [2])
);
FD blk000004b4 (
.C(clk),
.D(sig000007aa),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [1])
);
FD blk000004b5 (
.C(clk),
.D(sig000007a9),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [0])
);
FD blk000004b6 (
.C(clk),
.D(sig000007e7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [51])
);
FD blk000004b7 (
.C(clk),
.D(sig000007e6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [50])
);
FD blk000004b8 (
.C(clk),
.D(sig000007e5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [49])
);
FD blk000004b9 (
.C(clk),
.D(sig000007e4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [48])
);
FD blk000004ba (
.C(clk),
.D(sig000007e3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [47])
);
FD blk000004bb (
.C(clk),
.D(sig000007e2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [46])
);
FD blk000004bc (
.C(clk),
.D(sig000007e1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [45])
);
FD blk000004bd (
.C(clk),
.D(sig000007e0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [44])
);
FD blk000004be (
.C(clk),
.D(sig000007df),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [43])
);
FD blk000004bf (
.C(clk),
.D(sig000007de),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [42])
);
FD blk000004c0 (
.C(clk),
.D(sig000007dd),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [41])
);
FD blk000004c1 (
.C(clk),
.D(sig000007dc),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [40])
);
FD blk000004c2 (
.C(clk),
.D(sig000007db),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [39])
);
FD blk000004c3 (
.C(clk),
.D(sig000007da),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [38])
);
FD blk000004c4 (
.C(clk),
.D(sig000007d9),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [37])
);
FD blk000004c5 (
.C(clk),
.D(sig000007d8),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [36])
);
FD blk000004c6 (
.C(clk),
.D(sig000007d7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [35])
);
FD blk000004c7 (
.C(clk),
.D(sig000007d6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [34])
);
FD blk000004c8 (
.C(clk),
.D(sig000007d5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [33])
);
FD blk000004c9 (
.C(clk),
.D(sig000007d4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [32])
);
FD blk000004ca (
.C(clk),
.D(sig000007d3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [31])
);
FD blk000004cb (
.C(clk),
.D(sig000007d2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [30])
);
FD blk000004cc (
.C(clk),
.D(sig000007d1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [29])
);
FD blk000004cd (
.C(clk),
.D(sig000007d0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [28])
);
FD blk000004ce (
.C(clk),
.D(sig000007cf),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [27])
);
FD blk000004cf (
.C(clk),
.D(sig000007ce),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [26])
);
FD blk000004d0 (
.C(clk),
.D(sig000007cd),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [25])
);
FD blk000004d1 (
.C(clk),
.D(sig000007cc),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [24])
);
FD blk000004d2 (
.C(clk),
.D(sig000007cb),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [23])
);
FD blk000004d3 (
.C(clk),
.D(sig000007ca),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [22])
);
FD blk000004d4 (
.C(clk),
.D(sig000007c9),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [21])
);
FD blk000004d5 (
.C(clk),
.D(sig000007c8),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [20])
);
FD blk000004d6 (
.C(clk),
.D(sig000007c7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [19])
);
FD blk000004d7 (
.C(clk),
.D(sig000007c6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [18])
);
FD blk000004d8 (
.C(clk),
.D(sig000007c5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [17])
);
FD blk000004d9 (
.C(clk),
.D(sig000007c4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [16])
);
FD blk000004da (
.C(clk),
.D(sig000007c3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [15])
);
FD blk000004db (
.C(clk),
.D(sig000007c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [14])
);
FD blk000004dc (
.C(clk),
.D(sig000007c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [13])
);
FD blk000004dd (
.C(clk),
.D(sig000007c0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [12])
);
FD blk000004de (
.C(clk),
.D(sig000007bf),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [11])
);
FD blk000004df (
.C(clk),
.D(sig000007be),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [10])
);
FD blk000004e0 (
.C(clk),
.D(sig000007bd),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [9])
);
FD blk000004e1 (
.C(clk),
.D(sig000007bc),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [8])
);
FD blk000004e2 (
.C(clk),
.D(sig000007bb),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [7])
);
FD blk000004e3 (
.C(clk),
.D(sig000007ba),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [6])
);
FD blk000004e4 (
.C(clk),
.D(sig000007b9),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [5])
);
FD blk000004e5 (
.C(clk),
.D(sig000007b8),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [4])
);
FD blk000004e6 (
.C(clk),
.D(sig000007b7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [3])
);
FD blk000004e7 (
.C(clk),
.D(sig000007b6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [2])
);
FD blk000004e8 (
.C(clk),
.D(sig000007b5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [1])
);
FD blk000004e9 (
.C(clk),
.D(sig000007b4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [0])
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ea (
.I0(sig00000124),
.I1(sig00000134),
.I2(sig00000144),
.I3(sig00000154),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a2)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004eb (
.I0(sig00000123),
.I1(sig00000133),
.I2(sig00000143),
.I3(sig00000153),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a3)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ec (
.I0(sig0000027f),
.I1(sig0000012d),
.I2(sig0000013d),
.I3(sig0000014d),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a9)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ed (
.I0(sig00000122),
.I1(sig00000132),
.I2(sig00000142),
.I3(sig00000152),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a4)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ee (
.I0(sig00000121),
.I1(sig00000131),
.I2(sig00000141),
.I3(sig00000151),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a5)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ef (
.I0(sig00000120),
.I1(sig00000130),
.I2(sig00000140),
.I3(sig00000150),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a6)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004f0 (
.I0(sig0000011f),
.I1(sig0000012f),
.I2(sig0000013f),
.I3(sig0000014f),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a7)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004f1 (
.I0(sig0000011e),
.I1(sig0000012e),
.I2(sig0000013e),
.I3(sig0000014e),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a8)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f2 (
.I0(sig0000000e),
.I1(sig00000006),
.I2(sig00000002),
.I3(sig0000000a),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000b6)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f3 (
.I0(sig0000000f),
.I1(sig00000007),
.I2(sig00000003),
.I3(sig0000000b),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000b7)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f4 (
.I0(sig00000010),
.I1(sig00000008),
.I2(sig00000004),
.I3(sig0000000c),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000b8)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f5 (
.I0(sig00000011),
.I1(sig00000009),
.I2(sig00000005),
.I3(sig0000000d),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000b9)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f6 (
.I0(sig00000012),
.I1(sig0000000a),
.I2(sig00000006),
.I3(sig0000000e),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000ba)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f7 (
.I0(sig00000016),
.I1(sig0000000e),
.I2(sig0000000a),
.I3(sig00000012),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000be)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f8 (
.I0(sig00000017),
.I1(sig0000000f),
.I2(sig0000000b),
.I3(sig00000013),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000bf)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f9 (
.I0(sig00000018),
.I1(sig00000010),
.I2(sig0000000c),
.I3(sig00000014),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c0)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fa (
.I0(sig00000019),
.I1(sig00000011),
.I2(sig0000000d),
.I3(sig00000015),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c1)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fb (
.I0(sig0000001a),
.I1(sig00000012),
.I2(sig0000000e),
.I3(sig00000016),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c2)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fc (
.I0(sig0000001f),
.I1(sig00000017),
.I2(sig00000013),
.I3(sig0000001b),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c7)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fd (
.I0(sig00000020),
.I1(sig00000018),
.I2(sig00000014),
.I3(sig0000001c),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c8)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fe (
.I0(sig00000021),
.I1(sig00000019),
.I2(sig00000015),
.I3(sig0000001d),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c9)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004ff (
.I0(sig00000013),
.I1(sig0000000b),
.I2(sig00000007),
.I3(sig0000000f),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000bb)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000500 (
.I0(sig00000022),
.I1(sig0000001a),
.I2(sig00000016),
.I3(sig0000001e),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000ca)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000501 (
.I0(sig0000001b),
.I1(sig00000013),
.I2(sig0000000f),
.I3(sig00000017),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c3)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000502 (
.I0(sig00000023),
.I1(sig0000001b),
.I2(sig00000017),
.I3(sig0000001f),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000cb)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000503 (
.I0(sig00000024),
.I1(sig0000001c),
.I2(sig00000018),
.I3(sig00000020),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000cc)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000504 (
.I0(sig0000001c),
.I1(sig00000014),
.I2(sig00000010),
.I3(sig00000018),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c4)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000505 (
.I0(sig00000025),
.I1(sig0000001d),
.I2(sig00000019),
.I3(sig00000021),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000cd)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000506 (
.I0(sig0000001d),
.I1(sig00000015),
.I2(sig00000011),
.I3(sig00000019),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c5)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000507 (
.I0(sig00000026),
.I1(sig0000001e),
.I2(sig0000001a),
.I3(sig00000022),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000ce)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000508 (
.I0(sig0000001e),
.I1(sig00000016),
.I2(sig00000012),
.I3(sig0000001a),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c6)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000509 (
.I0(sig00000027),
.I1(sig0000001f),
.I2(sig0000001b),
.I3(sig00000023),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000cf)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050a (
.I0(sig00000028),
.I1(sig00000020),
.I2(sig0000001c),
.I3(sig00000024),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d0)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050b (
.I0(sig00000029),
.I1(sig00000021),
.I2(sig0000001d),
.I3(sig00000025),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d1)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050c (
.I0(sig0000002a),
.I1(sig00000022),
.I2(sig0000001e),
.I3(sig00000026),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d2)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050d (
.I0(sig00000014),
.I1(sig0000000c),
.I2(sig00000008),
.I3(sig00000010),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000bc)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050e (
.I0(sig0000002b),
.I1(sig00000023),
.I2(sig0000001f),
.I3(sig00000027),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d3)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050f (
.I0(sig0000002c),
.I1(sig00000024),
.I2(sig00000020),
.I3(sig00000028),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d4)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000510 (
.I0(sig0000002d),
.I1(sig00000025),
.I2(sig00000021),
.I3(sig00000029),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d5)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000511 (
.I0(sig0000002e),
.I1(sig00000026),
.I2(sig00000022),
.I3(sig0000002a),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d6)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000512 (
.I0(sig0000002f),
.I1(sig00000027),
.I2(sig00000023),
.I3(sig0000002b),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d7)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000513 (
.I0(sig00000030),
.I1(sig00000028),
.I2(sig00000024),
.I3(sig0000002c),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d8)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000514 (
.I0(sig00000038),
.I1(sig00000034),
.I2(sig00000030),
.I3(sig0000002c),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000e0)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000515 (
.I0(sig00000031),
.I1(sig00000029),
.I2(sig00000025),
.I3(sig0000002d),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d9)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000516 (
.I0(sig00000032),
.I1(sig0000002e),
.I2(sig0000002a),
.I3(sig00000026),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000da)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000517 (
.I0(sig00000039),
.I1(sig00000035),
.I2(sig00000031),
.I3(sig0000002d),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000e1)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000518 (
.I0(sig00000015),
.I1(sig0000000d),
.I2(sig00000009),
.I3(sig00000011),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000bd)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000519 (
.I0(sig00000033),
.I1(sig0000002f),
.I2(sig0000002b),
.I3(sig00000027),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000db)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000051a (
.I0(sig00000034),
.I1(sig00000030),
.I2(sig0000002c),
.I3(sig00000028),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000dc)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000051b (
.I0(sig00000035),
.I1(sig00000031),
.I2(sig0000002d),
.I3(sig00000029),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000dd)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000051c (
.I0(sig00000036),
.I1(sig00000032),
.I2(sig0000002e),
.I3(sig0000002a),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000de)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000051d (
.I0(sig00000037),
.I1(sig00000033),
.I2(sig0000002f),
.I3(sig0000002b),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000df)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000051e (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006d),
.I3(sig0000006b),
.I4(sig0000006c),
.I5(sig0000006e),
.O(sig00000114)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000051f (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006b),
.I3(sig00000069),
.I4(sig0000006a),
.I5(sig0000006c),
.O(sig00000112)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000520 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000041),
.I3(sig0000003f),
.I4(sig00000040),
.I5(sig00000042),
.O(sig000000e8)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000521 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000003f),
.I3(sig0000003d),
.I4(sig0000003e),
.I5(sig00000040),
.O(sig000000e6)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000522 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000042),
.I3(sig00000040),
.I4(sig00000041),
.I5(sig00000043),
.O(sig000000e9)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000523 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000040),
.I3(sig0000003e),
.I4(sig0000003f),
.I5(sig00000041),
.O(sig000000e7)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000524 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000043),
.I3(sig00000041),
.I4(sig00000042),
.I5(sig00000044),
.O(sig000000ea)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000525 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000048),
.I3(sig00000046),
.I4(sig00000047),
.I5(sig00000049),
.O(sig000000ef)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000526 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000046),
.I3(sig00000044),
.I4(sig00000045),
.I5(sig00000047),
.O(sig000000ed)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000527 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000049),
.I3(sig00000047),
.I4(sig00000048),
.I5(sig0000004a),
.O(sig000000f0)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000528 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000047),
.I3(sig00000045),
.I4(sig00000046),
.I5(sig00000048),
.O(sig000000ee)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000529 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004a),
.I3(sig00000048),
.I4(sig00000049),
.I5(sig0000004b),
.O(sig000000f1)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052a (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006e),
.I3(sig0000006c),
.I4(sig0000006d),
.I5(sig0000006f),
.O(sig00000115)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052b (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006c),
.I3(sig0000006a),
.I4(sig0000006b),
.I5(sig0000006d),
.O(sig00000113)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052c (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000044),
.I3(sig00000042),
.I4(sig00000043),
.I5(sig00000045),
.O(sig000000eb)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052d (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000051),
.I3(sig0000004f),
.I4(sig00000050),
.I5(sig00000052),
.O(sig000000f8)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052e (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004f),
.I3(sig0000004d),
.I4(sig0000004e),
.I5(sig00000050),
.O(sig000000f6)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052f (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000052),
.I3(sig00000050),
.I4(sig00000051),
.I5(sig00000053),
.O(sig000000f9)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000530 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000050),
.I3(sig0000004e),
.I4(sig0000004f),
.I5(sig00000051),
.O(sig000000f7)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000531 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000053),
.I3(sig00000051),
.I4(sig00000052),
.I5(sig00000054),
.O(sig000000fa)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000532 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000054),
.I3(sig00000052),
.I4(sig00000053),
.I5(sig00000055),
.O(sig000000fb)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000533 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004b),
.I3(sig00000049),
.I4(sig0000004a),
.I5(sig0000004c),
.O(sig000000f2)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000534 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006f),
.I3(sig0000006d),
.I4(sig0000006e),
.I5(sig00000070),
.O(sig00000116)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000535 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000055),
.I3(sig00000053),
.I4(sig00000054),
.I5(sig00000056),
.O(sig000000fc)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000536 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000056),
.I3(sig00000054),
.I4(sig00000055),
.I5(sig00000057),
.O(sig000000fd)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000537 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000057),
.I3(sig00000055),
.I4(sig00000056),
.I5(sig00000058),
.O(sig000000fe)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000538 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000058),
.I3(sig00000056),
.I4(sig00000057),
.I5(sig00000059),
.O(sig000000ff)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000539 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000045),
.I3(sig00000043),
.I4(sig00000044),
.I5(sig00000046),
.O(sig000000ec)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053a (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000059),
.I3(sig00000057),
.I4(sig00000058),
.I5(sig0000005a),
.O(sig00000100)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053b (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005a),
.I3(sig00000058),
.I4(sig00000059),
.I5(sig0000005b),
.O(sig00000101)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053c (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005b),
.I3(sig00000059),
.I4(sig0000005a),
.I5(sig0000005c),
.O(sig00000102)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053d (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005c),
.I3(sig0000005a),
.I4(sig0000005b),
.I5(sig0000005d),
.O(sig00000103)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053e (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005d),
.I3(sig0000005b),
.I4(sig0000005c),
.I5(sig0000005e),
.O(sig00000104)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053f (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004c),
.I3(sig0000004a),
.I4(sig0000004b),
.I5(sig0000004d),
.O(sig000000f3)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000540 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005e),
.I3(sig0000005c),
.I4(sig0000005d),
.I5(sig0000005f),
.O(sig00000105)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000541 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005f),
.I3(sig0000005d),
.I4(sig0000005e),
.I5(sig00000060),
.O(sig00000106)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000542 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000060),
.I3(sig0000005e),
.I4(sig0000005f),
.I5(sig00000061),
.O(sig00000107)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000543 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000061),
.I3(sig0000005f),
.I4(sig00000060),
.I5(sig00000062),
.O(sig00000108)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000544 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000062),
.I3(sig00000060),
.I4(sig00000061),
.I5(sig00000063),
.O(sig00000109)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000545 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000063),
.I3(sig00000061),
.I4(sig00000062),
.I5(sig00000064),
.O(sig0000010a)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000546 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000064),
.I3(sig00000062),
.I4(sig00000063),
.I5(sig00000065),
.O(sig0000010b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000547 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000070),
.I3(sig0000006e),
.I4(sig0000006f),
.I5(sig00000071),
.O(sig00000117)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000548 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000065),
.I3(sig00000063),
.I4(sig00000064),
.I5(sig00000066),
.O(sig0000010c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000549 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000066),
.I3(sig00000064),
.I4(sig00000065),
.I5(sig00000067),
.O(sig0000010d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054a (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004d),
.I3(sig0000004b),
.I4(sig0000004c),
.I5(sig0000004e),
.O(sig000000f4)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054b (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000067),
.I3(sig00000065),
.I4(sig00000066),
.I5(sig00000068),
.O(sig0000010e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054c (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000068),
.I3(sig00000066),
.I4(sig00000067),
.I5(sig00000069),
.O(sig0000010f)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054d (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000069),
.I3(sig00000067),
.I4(sig00000068),
.I5(sig0000006a),
.O(sig00000110)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054e (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006a),
.I3(sig00000068),
.I4(sig00000069),
.I5(sig0000006b),
.O(sig00000111)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054f (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000003c),
.I3(sig0000003a),
.I4(sig0000003b),
.I5(sig0000003d),
.O(sig000000e3)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000550 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000003d),
.I3(sig0000003b),
.I4(sig0000003c),
.I5(sig0000003e),
.O(sig000000e4)
);
LUT5 #(
.INIT ( 32'h00AAF0CC ))
blk00000551 (
.I0(sig0000003a),
.I1(sig0000003c),
.I2(sig0000003b),
.I3(sig0000011d),
.I4(sig0000011c),
.O(sig000000e2)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000552 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000003e),
.I3(sig0000003c),
.I4(sig0000003d),
.I5(sig0000003f),
.O(sig000000e5)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000553 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004e),
.I3(sig0000004c),
.I4(sig0000004d),
.I5(sig0000004f),
.O(sig000000f5)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000554 (
.I0(a[52]),
.I1(b[52]),
.O(sig00000156)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000555 (
.I0(b[63]),
.I1(operation[0]),
.O(sig000002a9)
);
LUT3 #(
.INIT ( 8'hF8 ))
blk00000556 (
.I0(sig0000027c),
.I1(sig0000027a),
.I2(sig0000027b),
.O(sig0000022e)
);
LUT5 #(
.INIT ( 32'hFEEE0222 ))
blk00000557 (
.I0(sig000002f5),
.I1(sig0000027b),
.I2(sig0000027c),
.I3(sig0000027a),
.I4(sig000002f4),
.O(sig000002a8)
);
LUT4 #(
.INIT ( 16'hAA8A ))
blk00000558 (
.I0(sig000002ea),
.I1(sig000002eb),
.I2(sig0000030c),
.I3(sig000002ec),
.O(sig000002a0)
);
LUT4 #(
.INIT ( 16'hEA2A ))
blk00000559 (
.I0(sig000002f4),
.I1(sig00000313),
.I2(sig00000314),
.I3(sig000002f5),
.O(sig000002a6)
);
LUT4 #(
.INIT ( 16'h8000 ))
blk0000055a (
.I0(sig00000313),
.I1(sig00000314),
.I2(sig00000310),
.I3(sig00000311),
.O(sig00000293)
);
LUT4 #(
.INIT ( 16'hF888 ))
blk0000055b (
.I0(sig00000313),
.I1(sig00000314),
.I2(sig00000310),
.I3(sig00000311),
.O(sig00000292)
);
LUT5 #(
.INIT ( 32'hFFFF1504 ))
blk0000055c (
.I0(sig000002f2),
.I1(sig000002f1),
.I2(sig000004b6),
.I3(sig000002ef),
.I4(sig000002f3),
.O(sig000002a5)
);
LUT4 #(
.INIT ( 16'h5554 ))
blk0000055d (
.I0(sig000002f3),
.I1(sig000002f1),
.I2(sig000002ef),
.I3(sig000002f2),
.O(sig000002a4)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF55555554 ))
blk0000055e (
.I0(sig000002eb),
.I1(sig0000030c),
.I2(sig000002b8),
.I3(sig000002c5),
.I4(sig000002c4),
.I5(sig000002ec),
.O(sig000002a2)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAABAA ))
blk0000055f (
.I0(sig000002eb),
.I1(sig0000030c),
.I2(sig000002ec),
.I3(sig000002c5),
.I4(sig000002b8),
.I5(sig000002c4),
.O(sig000002a1)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000560 (
.I0(sig0000024a),
.I1(sig0000030b),
.I2(sig00000300),
.O(sig0000028e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000561 (
.I0(sig000002f7),
.I1(sig00000302),
.I2(sig0000024a),
.O(sig00000285)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000562 (
.I0(sig000002f8),
.I1(sig00000303),
.I2(sig0000024a),
.O(sig00000286)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000563 (
.I0(sig000002f9),
.I1(sig00000304),
.I2(sig0000024a),
.O(sig00000287)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000564 (
.I0(sig000002fa),
.I1(sig00000305),
.I2(sig0000024a),
.O(sig00000288)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000565 (
.I0(sig000002fb),
.I1(sig00000306),
.I2(sig0000024a),
.O(sig00000289)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000566 (
.I0(sig000002fc),
.I1(sig00000307),
.I2(sig0000024a),
.O(sig0000028a)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000567 (
.I0(sig0000024a),
.I1(sig00000308),
.I2(sig000002fd),
.O(sig0000028b)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000568 (
.I0(sig0000024a),
.I1(sig00000309),
.I2(sig000002fe),
.O(sig0000028c)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000569 (
.I0(sig0000024a),
.I1(sig0000030a),
.I2(sig000002ff),
.O(sig0000028d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000056a (
.I0(sig000002f5),
.I1(sig000002f4),
.O(sig00000290)
);
LUT3 #(
.INIT ( 8'h53 ))
blk0000056b (
.I0(sig00000301),
.I1(sig000002f6),
.I2(sig0000024a),
.O(sig00000284)
);
LUT2 #(
.INIT ( 4'hE ))
blk0000056c (
.I0(sig000002b7),
.I1(sig000002b6),
.O(sig00000277)
);
LUT2 #(
.INIT ( 4'h2 ))
blk0000056d (
.I0(sig000002b6),
.I1(sig000002b7),
.O(sig00000278)
);
LUT2 #(
.INIT ( 4'h2 ))
blk0000056e (
.I0(sig000002b7),
.I1(sig000002b6),
.O(sig00000279)
);
LUT4 #(
.INIT ( 16'h22F2 ))
blk0000056f (
.I0(sig00000313),
.I1(sig00000314),
.I2(sig00000310),
.I3(sig00000311),
.O(sig00000291)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000570 (
.I0(sig000002c6),
.I1(sig0000030d),
.O(sig0000029f)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000571 (
.I0(sig000002f5),
.I1(sig000002f4),
.O(sig000002a7)
);
LUT2 #(
.INIT ( 4'hE ))
blk00000572 (
.I0(sig0000030f),
.I1(sig00000312),
.O(sig0000022c)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000573 (
.I0(sig0000030f),
.I1(sig00000312),
.O(sig0000022d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000574 (
.I0(a[42]),
.I1(a[43]),
.I2(a[44]),
.I3(a[45]),
.I4(a[46]),
.I5(a[47]),
.O(sig00000315)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000575 (
.I0(a[36]),
.I1(a[37]),
.I2(a[38]),
.I3(a[39]),
.I4(a[40]),
.I5(a[41]),
.O(sig00000316)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000576 (
.I0(a[30]),
.I1(a[31]),
.I2(a[32]),
.I3(a[33]),
.I4(a[34]),
.I5(a[35]),
.O(sig00000317)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000577 (
.I0(a[24]),
.I1(a[25]),
.I2(a[26]),
.I3(a[27]),
.I4(a[28]),
.I5(a[29]),
.O(sig00000318)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000578 (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.I5(a[23]),
.O(sig00000319)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000579 (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig0000031a)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057a (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig0000031b)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057b (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig0000031c)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000057c (
.I0(a[48]),
.I1(a[49]),
.I2(a[50]),
.I3(a[51]),
.O(sig0000031d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057d (
.I0(b[42]),
.I1(b[43]),
.I2(b[44]),
.I3(b[45]),
.I4(b[46]),
.I5(b[47]),
.O(sig0000031e)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057e (
.I0(b[36]),
.I1(b[37]),
.I2(b[38]),
.I3(b[39]),
.I4(b[40]),
.I5(b[41]),
.O(sig0000031f)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057f (
.I0(b[30]),
.I1(b[31]),
.I2(b[32]),
.I3(b[33]),
.I4(b[34]),
.I5(b[35]),
.O(sig00000320)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000580 (
.I0(b[24]),
.I1(b[25]),
.I2(b[26]),
.I3(b[27]),
.I4(b[28]),
.I5(b[29]),
.O(sig00000321)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000581 (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.I5(b[23]),
.O(sig00000322)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000582 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig00000323)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000583 (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig00000324)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000584 (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig00000325)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000585 (
.I0(b[48]),
.I1(b[49]),
.I2(b[50]),
.I3(b[51]),
.O(sig00000326)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000586 (
.I0(b[19]),
.I1(a[19]),
.I2(b[18]),
.I3(a[18]),
.O(sig00000346)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000587 (
.I0(b[17]),
.I1(a[17]),
.I2(b[16]),
.I3(a[16]),
.O(sig00000348)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000588 (
.I0(b[15]),
.I1(a[15]),
.I2(b[14]),
.I3(a[14]),
.O(sig0000034a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000589 (
.I0(b[13]),
.I1(a[13]),
.I2(b[12]),
.I3(a[12]),
.O(sig0000034c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058a (
.I0(b[11]),
.I1(a[11]),
.I2(b[10]),
.I3(a[10]),
.O(sig0000034e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058b (
.I0(b[9]),
.I1(a[9]),
.I2(b[8]),
.I3(a[8]),
.O(sig00000350)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058c (
.I0(b[7]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(sig00000352)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058d (
.I0(b[5]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(sig00000354)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058e (
.I0(b[3]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(sig00000356)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058f (
.I0(b[31]),
.I1(a[31]),
.I2(b[30]),
.I3(a[30]),
.O(sig0000033a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000590 (
.I0(b[29]),
.I1(a[29]),
.I2(b[28]),
.I3(a[28]),
.O(sig0000033c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000591 (
.I0(b[27]),
.I1(a[27]),
.I2(b[26]),
.I3(a[26]),
.O(sig0000033e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000592 (
.I0(b[25]),
.I1(a[25]),
.I2(b[24]),
.I3(a[24]),
.O(sig00000340)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000593 (
.I0(b[23]),
.I1(a[23]),
.I2(b[22]),
.I3(a[22]),
.O(sig00000342)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000594 (
.I0(b[21]),
.I1(a[21]),
.I2(b[20]),
.I3(a[20]),
.O(sig00000344)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000595 (
.I0(b[1]),
.I1(a[1]),
.I2(b[0]),
.I3(a[0]),
.O(sig00000358)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk00000596 (
.I0(b[31]),
.I1(a[31]),
.I2(b[30]),
.I3(a[30]),
.O(sig00000339)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk00000597 (
.I0(b[29]),
.I1(a[29]),
.I2(b[28]),
.I3(a[28]),
.O(sig0000033b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk00000598 (
.I0(b[27]),
.I1(a[27]),
.I2(b[26]),
.I3(a[26]),
.O(sig0000033d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk00000599 (
.I0(b[25]),
.I1(a[25]),
.I2(b[24]),
.I3(a[24]),
.O(sig0000033f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059a (
.I0(b[23]),
.I1(a[23]),
.I2(b[22]),
.I3(a[22]),
.O(sig00000341)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059b (
.I0(b[21]),
.I1(a[21]),
.I2(b[20]),
.I3(a[20]),
.O(sig00000343)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059c (
.I0(b[19]),
.I1(a[19]),
.I2(b[18]),
.I3(a[18]),
.O(sig00000345)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059d (
.I0(b[17]),
.I1(a[17]),
.I2(b[16]),
.I3(a[16]),
.O(sig00000347)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059e (
.I0(b[15]),
.I1(a[15]),
.I2(b[14]),
.I3(a[14]),
.O(sig00000349)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059f (
.I0(b[13]),
.I1(a[13]),
.I2(b[12]),
.I3(a[12]),
.O(sig0000034b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a0 (
.I0(b[11]),
.I1(a[11]),
.I2(b[10]),
.I3(a[10]),
.O(sig0000034d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a1 (
.I0(b[9]),
.I1(a[9]),
.I2(b[8]),
.I3(a[8]),
.O(sig0000034f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a2 (
.I0(b[7]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(sig00000351)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a3 (
.I0(b[5]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(sig00000353)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a4 (
.I0(b[3]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(sig00000355)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a5 (
.I0(b[1]),
.I1(a[1]),
.I2(b[0]),
.I3(a[0]),
.O(sig00000357)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005a6 (
.I0(b[51]),
.I1(a[51]),
.I2(b[50]),
.I3(a[50]),
.O(sig00000366)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005a7 (
.I0(b[49]),
.I1(a[49]),
.I2(b[48]),
.I3(a[48]),
.O(sig00000368)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005a8 (
.I0(b[47]),
.I1(a[47]),
.I2(b[46]),
.I3(a[46]),
.O(sig0000036a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005a9 (
.I0(b[45]),
.I1(a[45]),
.I2(b[44]),
.I3(a[44]),
.O(sig0000036c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005aa (
.I0(b[43]),
.I1(a[43]),
.I2(b[42]),
.I3(a[42]),
.O(sig0000036e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005ab (
.I0(b[41]),
.I1(a[41]),
.I2(b[40]),
.I3(a[40]),
.O(sig00000370)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005ac (
.I0(b[39]),
.I1(a[39]),
.I2(b[38]),
.I3(a[38]),
.O(sig00000372)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005ad (
.I0(b[37]),
.I1(a[37]),
.I2(b[36]),
.I3(a[36]),
.O(sig00000374)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005ae (
.I0(b[35]),
.I1(a[35]),
.I2(b[34]),
.I3(a[34]),
.O(sig00000376)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000005af (
.I0(b[62]),
.I1(a[62]),
.O(sig0000035a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b0 (
.I0(b[61]),
.I1(a[61]),
.I2(b[60]),
.I3(a[60]),
.O(sig0000035c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b1 (
.I0(b[59]),
.I1(a[59]),
.I2(b[58]),
.I3(a[58]),
.O(sig0000035e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b2 (
.I0(b[57]),
.I1(a[57]),
.I2(b[56]),
.I3(a[56]),
.O(sig00000360)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b3 (
.I0(b[55]),
.I1(a[55]),
.I2(b[54]),
.I3(a[54]),
.O(sig00000362)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b4 (
.I0(b[53]),
.I1(a[53]),
.I2(b[52]),
.I3(a[52]),
.O(sig00000364)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b5 (
.I0(b[33]),
.I1(a[33]),
.I2(b[32]),
.I3(a[32]),
.O(sig00000378)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000005b6 (
.I0(b[62]),
.I1(a[62]),
.O(sig00000359)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005b7 (
.I0(b[61]),
.I1(a[61]),
.I2(b[60]),
.I3(a[60]),
.O(sig0000035b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005b8 (
.I0(b[59]),
.I1(a[59]),
.I2(b[58]),
.I3(a[58]),
.O(sig0000035d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005b9 (
.I0(b[57]),
.I1(a[57]),
.I2(b[56]),
.I3(a[56]),
.O(sig0000035f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005ba (
.I0(b[55]),
.I1(a[55]),
.I2(b[54]),
.I3(a[54]),
.O(sig00000361)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005bb (
.I0(b[53]),
.I1(a[53]),
.I2(b[52]),
.I3(a[52]),
.O(sig00000363)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005bc (
.I0(b[51]),
.I1(a[51]),
.I2(b[50]),
.I3(a[50]),
.O(sig00000365)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005bd (
.I0(b[49]),
.I1(a[49]),
.I2(b[48]),
.I3(a[48]),
.O(sig00000367)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005be (
.I0(b[47]),
.I1(a[47]),
.I2(b[46]),
.I3(a[46]),
.O(sig00000369)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005bf (
.I0(b[45]),
.I1(a[45]),
.I2(b[44]),
.I3(a[44]),
.O(sig0000036b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c0 (
.I0(b[43]),
.I1(a[43]),
.I2(b[42]),
.I3(a[42]),
.O(sig0000036d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c1 (
.I0(b[41]),
.I1(a[41]),
.I2(b[40]),
.I3(a[40]),
.O(sig0000036f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c2 (
.I0(b[39]),
.I1(a[39]),
.I2(b[38]),
.I3(a[38]),
.O(sig00000371)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c3 (
.I0(b[37]),
.I1(a[37]),
.I2(b[36]),
.I3(a[36]),
.O(sig00000373)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c4 (
.I0(b[35]),
.I1(a[35]),
.I2(b[34]),
.I3(a[34]),
.O(sig00000375)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c5 (
.I0(b[33]),
.I1(a[33]),
.I2(b[32]),
.I3(a[32]),
.O(sig00000377)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005c6 (
.I0(b[59]),
.I1(a[59]),
.I2(b[61]),
.I3(a[61]),
.I4(b[60]),
.I5(a[60]),
.O(sig0000039a)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005c7 (
.I0(b[56]),
.I1(a[56]),
.I2(b[58]),
.I3(a[58]),
.I4(b[57]),
.I5(a[57]),
.O(sig0000039b)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005c8 (
.I0(b[53]),
.I1(a[53]),
.I2(b[55]),
.I3(a[55]),
.I4(b[54]),
.I5(a[54]),
.O(sig0000039c)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005c9 (
.I0(b[50]),
.I1(a[50]),
.I2(b[52]),
.I3(a[52]),
.I4(b[51]),
.I5(a[51]),
.O(sig0000039d)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005ca (
.I0(b[47]),
.I1(a[47]),
.I2(b[49]),
.I3(a[49]),
.I4(b[48]),
.I5(a[48]),
.O(sig0000039e)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005cb (
.I0(b[44]),
.I1(a[44]),
.I2(b[46]),
.I3(a[46]),
.I4(b[45]),
.I5(a[45]),
.O(sig0000039f)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005cc (
.I0(b[42]),
.I1(a[42]),
.I2(b[41]),
.I3(a[41]),
.I4(b[43]),
.I5(a[43]),
.O(sig000003a0)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005cd (
.I0(b[38]),
.I1(a[38]),
.I2(b[40]),
.I3(a[40]),
.I4(b[39]),
.I5(a[39]),
.O(sig000003a1)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005ce (
.I0(b[35]),
.I1(a[35]),
.I2(b[37]),
.I3(a[37]),
.I4(b[36]),
.I5(a[36]),
.O(sig000003a2)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005cf (
.I0(b[32]),
.I1(a[32]),
.I2(b[34]),
.I3(a[34]),
.I4(b[33]),
.I5(a[33]),
.O(sig000003a3)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000005d0 (
.I0(a[62]),
.I1(b[62]),
.O(sig00000399)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005d1 (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004ec),
.I3(sig0000050c),
.I4(sig000004fc),
.I5(sig000004dc),
.O(sig0000043f)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005d2 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fc),
.I3(sig0000050c),
.O(sig0000041f)
);
LUT5 #(
.INIT ( 32'hE6C4A280 ))
blk000005d3 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000506),
.I3(sig000004f6),
.I4(sig000004e6),
.O(sig00000445)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005d4 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f6),
.I3(sig00000506),
.O(sig00000425)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005d5 (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004eb),
.I3(sig0000050b),
.I4(sig000004fb),
.I5(sig000004db),
.O(sig00000440)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005d6 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fb),
.I3(sig0000050b),
.O(sig00000420)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005d7 (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004ea),
.I3(sig0000050a),
.I4(sig000004fa),
.I5(sig000004da),
.O(sig00000441)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005d8 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fa),
.I3(sig0000050a),
.O(sig00000421)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005d9 (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004e8),
.I3(sig00000508),
.I4(sig000004f8),
.I5(sig000004d8),
.O(sig00000443)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005da (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f8),
.I3(sig00000508),
.O(sig00000423)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005db (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004e9),
.I3(sig00000509),
.I4(sig000004f9),
.I5(sig000004d9),
.O(sig00000442)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005dc (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f9),
.I3(sig00000509),
.O(sig00000422)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005dd (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004e7),
.I3(sig00000507),
.I4(sig000004f7),
.I5(sig000004d7),
.O(sig00000444)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005de (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f7),
.I3(sig00000507),
.O(sig00000424)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005df (
.I0(sig000001ea),
.I1(sig000001eb),
.I2(sig0000021f),
.I3(sig0000021e),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000536)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e0 (
.I0(sig000001eb),
.I1(sig000001ec),
.I2(sig00000220),
.I3(sig0000021f),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000537)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e1 (
.I0(sig000001e9),
.I1(sig000001ea),
.I2(sig0000021e),
.I3(sig0000021d),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000535)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e2 (
.I0(sig000001e8),
.I1(sig000001e9),
.I2(sig0000021d),
.I3(sig0000021c),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000534)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e3 (
.I0(sig000001e7),
.I1(sig000001e8),
.I2(sig0000021c),
.I3(sig0000021b),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000533)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e4 (
.I0(sig000001e3),
.I1(sig000001e4),
.I2(sig00000218),
.I3(sig00000217),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052f)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e5 (
.I0(sig000001e4),
.I1(sig000001e5),
.I2(sig00000219),
.I3(sig00000218),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000530)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e6 (
.I0(sig000001e2),
.I1(sig000001e3),
.I2(sig00000217),
.I3(sig00000216),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052e)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e7 (
.I0(sig000001e6),
.I1(sig000001e7),
.I2(sig0000021b),
.I3(sig0000021a),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000532)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e8 (
.I0(sig000001e1),
.I1(sig000001e2),
.I2(sig00000216),
.I3(sig00000215),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052d)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e9 (
.I0(sig000001e0),
.I1(sig000001e1),
.I2(sig00000215),
.I3(sig00000214),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052c)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ea (
.I0(sig000001da),
.I1(sig000001db),
.I2(sig0000020f),
.I3(sig0000020e),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000526)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005eb (
.I0(sig000001db),
.I1(sig000001dc),
.I2(sig00000210),
.I3(sig0000020f),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000527)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ec (
.I0(sig000001d9),
.I1(sig000001da),
.I2(sig0000020e),
.I3(sig0000020d),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000525)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ed (
.I0(sig000001df),
.I1(sig000001e0),
.I2(sig00000214),
.I3(sig00000213),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052b)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ee (
.I0(sig000001d8),
.I1(sig000001d9),
.I2(sig0000020d),
.I3(sig0000020c),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000524)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ef (
.I0(sig000001d7),
.I1(sig000001d8),
.I2(sig0000020c),
.I3(sig0000020b),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000523)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f0 (
.I0(sig000001d6),
.I1(sig000001d7),
.I2(sig0000020b),
.I3(sig0000020a),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000522)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f1 (
.I0(sig000001d5),
.I1(sig000001d6),
.I2(sig0000020a),
.I3(sig00000209),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000521)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f2 (
.I0(sig000001d4),
.I1(sig000001d5),
.I2(sig00000209),
.I3(sig00000208),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000520)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f3 (
.I0(sig000001e5),
.I1(sig000001e6),
.I2(sig0000021a),
.I3(sig00000219),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000531)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f4 (
.I0(sig000001d3),
.I1(sig000001d4),
.I2(sig00000208),
.I3(sig00000207),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051f)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f5 (
.I0(sig000001d2),
.I1(sig000001d3),
.I2(sig00000207),
.I3(sig00000206),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051e)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f6 (
.I0(sig000001d1),
.I1(sig000001d2),
.I2(sig00000206),
.I3(sig00000205),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051d)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f7 (
.I0(sig000001c3),
.I1(sig000001c4),
.I2(sig000001f8),
.I3(sig000001f7),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000050f)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f8 (
.I0(sig000001c4),
.I1(sig000001c5),
.I2(sig000001f9),
.I3(sig000001f8),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000510)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f9 (
.I0(sig000001d0),
.I1(sig000001d1),
.I2(sig00000205),
.I3(sig00000204),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051c)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fa (
.I0(sig000001de),
.I1(sig000001df),
.I2(sig00000213),
.I3(sig00000212),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052a)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fb (
.I0(sig000001cf),
.I1(sig000001d0),
.I2(sig00000204),
.I3(sig00000203),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051b)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fc (
.I0(sig000001ce),
.I1(sig000001cf),
.I2(sig00000203),
.I3(sig00000202),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051a)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fd (
.I0(sig000001cd),
.I1(sig000001ce),
.I2(sig00000202),
.I3(sig00000201),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000519)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fe (
.I0(sig000001cc),
.I1(sig000001cd),
.I2(sig00000201),
.I3(sig00000200),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000518)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ff (
.I0(sig000001c6),
.I1(sig000001c7),
.I2(sig000001fb),
.I3(sig000001fa),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000512)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000600 (
.I0(sig000001c5),
.I1(sig000001c6),
.I2(sig000001fa),
.I3(sig000001f9),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000511)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000601 (
.I0(sig000001cb),
.I1(sig000001cc),
.I2(sig00000200),
.I3(sig000001ff),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000517)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000602 (
.I0(sig000001ca),
.I1(sig000001cb),
.I2(sig000001ff),
.I3(sig000001fe),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000516)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000603 (
.I0(sig000001c9),
.I1(sig000001ca),
.I2(sig000001fe),
.I3(sig000001fd),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000515)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000604 (
.I0(sig000001c8),
.I1(sig000001c9),
.I2(sig000001fd),
.I3(sig000001fc),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000514)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000605 (
.I0(sig000001c7),
.I1(sig000001c8),
.I2(sig000001fc),
.I3(sig000001fb),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000513)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000606 (
.I0(sig000001f5),
.I1(sig000001f6),
.I2(sig0000022a),
.I3(sig00000229),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000541)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000607 (
.I0(sig000001dd),
.I1(sig000001de),
.I2(sig00000212),
.I3(sig00000211),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000529)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000608 (
.I0(sig000001f4),
.I1(sig000001f5),
.I2(sig00000229),
.I3(sig00000228),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000540)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000609 (
.I0(sig000001f3),
.I1(sig000001f4),
.I2(sig00000228),
.I3(sig00000227),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053f)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060a (
.I0(sig000001f2),
.I1(sig000001f3),
.I2(sig00000227),
.I3(sig00000226),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053e)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060b (
.I0(sig000001f1),
.I1(sig000001f2),
.I2(sig00000226),
.I3(sig00000225),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053d)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060c (
.I0(sig000001f0),
.I1(sig000001f1),
.I2(sig00000225),
.I3(sig00000224),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053c)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060d (
.I0(sig000001ef),
.I1(sig000001f0),
.I2(sig00000224),
.I3(sig00000223),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053b)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060e (
.I0(sig000001ee),
.I1(sig000001ef),
.I2(sig00000223),
.I3(sig00000222),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053a)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060f (
.I0(sig000001ed),
.I1(sig000001ee),
.I2(sig00000222),
.I3(sig00000221),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000539)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000610 (
.I0(sig000001dc),
.I1(sig000001dd),
.I2(sig00000211),
.I3(sig00000210),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000528)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000611 (
.I0(sig000001ec),
.I1(sig000001ed),
.I2(sig00000221),
.I3(sig00000220),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000538)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000612 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003de),
.I3(sig000003d6),
.I4(sig000003da),
.I5(sig000003e2),
.O(sig00000452)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000613 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003da),
.I3(sig000003d6),
.O(sig0000044a)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000614 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003df),
.I3(sig000003d7),
.I4(sig000003db),
.I5(sig000003e3),
.O(sig00000453)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000615 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003db),
.I3(sig000003d7),
.O(sig0000044b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000616 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e0),
.I3(sig000003d8),
.I4(sig000003dc),
.I5(sig000003e4),
.O(sig00000454)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000617 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003dc),
.I3(sig000003d8),
.O(sig0000044c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000618 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e1),
.I3(sig000003d9),
.I4(sig000003dd),
.I5(sig000003e5),
.O(sig00000455)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000619 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003dd),
.I3(sig000003d9),
.O(sig0000044d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061a (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e5),
.I3(sig000003dd),
.I4(sig000003e1),
.I5(sig000003e9),
.O(sig00000459)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000061b (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003dd),
.I3(sig000003e1),
.I4(sig000003d9),
.O(sig00000451)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061c (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e6),
.I3(sig000003de),
.I4(sig000003e2),
.I5(sig000003ea),
.O(sig0000045a)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061d (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e7),
.I3(sig000003df),
.I4(sig000003e3),
.I5(sig000003eb),
.O(sig0000045b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061e (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e8),
.I3(sig000003e0),
.I4(sig000003e4),
.I5(sig000003ec),
.O(sig0000045c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061f (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e9),
.I3(sig000003e1),
.I4(sig000003e5),
.I5(sig000003ed),
.O(sig0000045d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000620 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ee),
.I3(sig000003e6),
.I4(sig000003ea),
.I5(sig000003f2),
.O(sig00000462)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000621 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ef),
.I3(sig000003e7),
.I4(sig000003eb),
.I5(sig000003f3),
.O(sig00000463)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000622 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e2),
.I3(sig000003da),
.I4(sig000003de),
.I5(sig000003e6),
.O(sig00000456)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000623 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003da),
.I3(sig000003de),
.I4(sig000003d6),
.O(sig0000044e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000624 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f0),
.I3(sig000003e8),
.I4(sig000003ec),
.I5(sig000003f4),
.O(sig00000464)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000625 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f1),
.I3(sig000003e9),
.I4(sig000003ed),
.I5(sig000003f5),
.O(sig00000465)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000626 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ea),
.I3(sig000003e2),
.I4(sig000003e6),
.I5(sig000003ee),
.O(sig0000045e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000627 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f2),
.I3(sig000003ea),
.I4(sig000003ee),
.I5(sig000003f6),
.O(sig00000466)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000628 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f3),
.I3(sig000003eb),
.I4(sig000003ef),
.I5(sig000003f7),
.O(sig00000467)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000629 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003eb),
.I3(sig000003e3),
.I4(sig000003e7),
.I5(sig000003ef),
.O(sig0000045f)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062a (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f4),
.I3(sig000003ec),
.I4(sig000003f0),
.I5(sig000003f8),
.O(sig00000468)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062b (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ec),
.I3(sig000003e4),
.I4(sig000003e8),
.I5(sig000003f0),
.O(sig00000460)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062c (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f5),
.I3(sig000003ed),
.I4(sig000003f1),
.I5(sig000003f9),
.O(sig00000469)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062d (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ed),
.I3(sig000003e5),
.I4(sig000003e9),
.I5(sig000003f1),
.O(sig00000461)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062e (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f6),
.I3(sig000003ee),
.I4(sig000003f2),
.I5(sig000003fa),
.O(sig0000046a)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062f (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f7),
.I3(sig000003ef),
.I4(sig000003f3),
.I5(sig000003fb),
.O(sig0000046b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000630 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f8),
.I3(sig000003f0),
.I4(sig000003f4),
.I5(sig000003fc),
.O(sig0000046c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000631 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e3),
.I3(sig000003db),
.I4(sig000003df),
.I5(sig000003e7),
.O(sig00000457)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000632 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003db),
.I3(sig000003df),
.I4(sig000003d7),
.O(sig0000044f)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000633 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f9),
.I3(sig000003f1),
.I4(sig000003f5),
.I5(sig000003fd),
.O(sig0000046d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000634 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fa),
.I3(sig000003f2),
.I4(sig000003f6),
.I5(sig000003fe),
.O(sig0000046e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000635 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fb),
.I3(sig000003f3),
.I4(sig000003f7),
.I5(sig000003ff),
.O(sig0000046f)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000636 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fc),
.I3(sig000003f4),
.I4(sig000003f8),
.I5(sig00000400),
.O(sig00000470)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000637 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fd),
.I3(sig000003f5),
.I4(sig000003f9),
.I5(sig00000401),
.O(sig00000471)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000638 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fe),
.I3(sig000003f6),
.I4(sig000003fa),
.I5(sig00000402),
.O(sig00000472)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000639 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ff),
.I3(sig000003f7),
.I4(sig000003fb),
.I5(sig00000403),
.O(sig00000473)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063a (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000407),
.I3(sig000003ff),
.I4(sig00000403),
.I5(sig0000040b),
.O(sig0000047b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063b (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000400),
.I3(sig000003f8),
.I4(sig000003fc),
.I5(sig00000404),
.O(sig00000474)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063c (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000401),
.I3(sig000003f9),
.I4(sig000003fd),
.I5(sig00000405),
.O(sig00000475)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063d (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e4),
.I3(sig000003dc),
.I4(sig000003e0),
.I5(sig000003e8),
.O(sig00000458)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000063e (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003dc),
.I3(sig000003e0),
.I4(sig000003d8),
.O(sig00000450)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063f (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000408),
.I3(sig00000400),
.I4(sig00000404),
.I5(sig0000040c),
.O(sig0000047c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000640 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000402),
.I3(sig000003fa),
.I4(sig000003fe),
.I5(sig00000406),
.O(sig00000476)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000641 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000403),
.I3(sig000003fb),
.I4(sig000003ff),
.I5(sig00000407),
.O(sig00000477)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000642 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000404),
.I3(sig000003fc),
.I4(sig00000400),
.I5(sig00000408),
.O(sig00000478)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000643 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000405),
.I3(sig000003fd),
.I4(sig00000401),
.I5(sig00000409),
.O(sig00000479)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000644 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000406),
.I3(sig000003fe),
.I4(sig00000402),
.I5(sig0000040a),
.O(sig0000047a)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000645 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f0),
.I3(sig000004e0),
.I4(sig00000500),
.O(sig0000043b)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000646 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f1),
.I3(sig000004e1),
.I4(sig00000501),
.O(sig0000043a)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000647 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f2),
.I3(sig000004e2),
.I4(sig00000502),
.O(sig00000439)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000648 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f3),
.I3(sig000004e3),
.I4(sig00000503),
.O(sig00000438)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000649 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f4),
.I3(sig000004e4),
.I4(sig00000504),
.O(sig00000437)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064a (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f5),
.I3(sig000004e5),
.I4(sig00000505),
.O(sig00000436)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064b (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f6),
.I3(sig000004e6),
.I4(sig00000506),
.O(sig00000435)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064c (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f7),
.I3(sig000004e7),
.I4(sig00000507),
.O(sig00000434)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064d (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f8),
.I3(sig000004e8),
.I4(sig00000508),
.O(sig00000433)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064e (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f9),
.I3(sig000004e9),
.I4(sig00000509),
.O(sig00000432)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064f (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fa),
.I3(sig000004ea),
.I4(sig0000050a),
.O(sig00000431)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000650 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fb),
.I3(sig000004eb),
.I4(sig0000050b),
.O(sig00000430)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000651 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fc),
.I3(sig000004ec),
.I4(sig0000050c),
.O(sig0000042f)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000652 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ed),
.I3(sig000004fd),
.O(sig0000042e)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000653 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ee),
.I3(sig000004fe),
.O(sig0000042d)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000654 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ef),
.I3(sig000004ff),
.O(sig0000042c)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000655 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f0),
.I3(sig00000500),
.O(sig0000042b)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000656 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f1),
.I3(sig00000501),
.O(sig0000042a)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000657 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f2),
.I3(sig00000502),
.O(sig00000429)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000658 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f3),
.I3(sig00000503),
.O(sig00000428)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000659 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f4),
.I3(sig00000504),
.O(sig00000427)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000065a (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f5),
.I3(sig00000505),
.O(sig00000426)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000065b (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ed),
.I3(sig000004dd),
.I4(sig000004fd),
.O(sig0000043e)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000065c (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ee),
.I3(sig000004de),
.I4(sig000004fe),
.O(sig0000043d)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000065d (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ef),
.I3(sig000004df),
.I4(sig000004ff),
.O(sig0000043c)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000065e (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003d9),
.O(sig00000449)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000065f (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003d8),
.O(sig00000448)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000660 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003d7),
.O(sig00000447)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000661 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003d6),
.O(sig00000446)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000662 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fd),
.O(sig0000041e)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000663 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fe),
.O(sig0000041d)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000664 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ff),
.O(sig0000041c)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000665 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000500),
.O(sig0000041b)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000666 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000501),
.O(sig0000041a)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000667 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000502),
.O(sig00000419)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000668 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000503),
.O(sig00000418)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000669 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000504),
.O(sig00000417)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066a (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000505),
.O(sig00000416)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066b (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000506),
.O(sig00000415)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066c (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000507),
.O(sig00000414)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066d (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000508),
.O(sig00000413)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066e (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000509),
.O(sig00000412)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066f (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig0000050a),
.O(sig00000411)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000670 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig0000050b),
.O(sig00000410)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000671 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig0000050c),
.O(sig0000040f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000672 (
.I0(sig00000249),
.I1(sig0000024a),
.O(sig00000583)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000673 (
.I0(sig00000240),
.I1(sig0000024a),
.O(sig0000057a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000674 (
.I0(sig00000241),
.I1(sig0000024a),
.O(sig0000057b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000675 (
.I0(sig00000242),
.I1(sig0000024a),
.O(sig0000057c)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000676 (
.I0(sig00000243),
.I1(sig0000024a),
.O(sig0000057d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000677 (
.I0(sig00000244),
.I1(sig0000024a),
.O(sig0000057e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000678 (
.I0(sig00000245),
.I1(sig0000024a),
.O(sig0000057f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000679 (
.I0(sig00000246),
.I1(sig0000024a),
.O(sig00000580)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000067a (
.I0(sig00000247),
.I1(sig0000024a),
.O(sig00000581)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000067b (
.I0(sig00000248),
.I1(sig0000024a),
.O(sig00000582)
);
LUT2 #(
.INIT ( 4'hE ))
blk0000067c (
.I0(sig000004cd),
.I1(sig00000544),
.O(sig000004bb)
);
LUT3 #(
.INIT ( 8'h1F ))
blk0000067d (
.I0(sig0000050b),
.I1(sig0000050a),
.I2(sig000004cf),
.O(sig00000587)
);
LUT3 #(
.INIT ( 8'h1F ))
blk0000067e (
.I0(sig00000507),
.I1(sig00000506),
.I2(sig000004cf),
.O(sig00000588)
);
LUT3 #(
.INIT ( 8'h1F ))
blk0000067f (
.I0(sig000004ff),
.I1(sig000004fe),
.I2(sig000004cf),
.O(sig0000058a)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000680 (
.I0(sig000004fb),
.I1(sig000004fa),
.I2(sig000004cf),
.O(sig0000058b)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000681 (
.I0(sig00000503),
.I1(sig00000502),
.I2(sig000004cf),
.O(sig00000589)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000682 (
.I0(sig000004f3),
.I1(sig000004f2),
.I2(sig000004cf),
.O(sig0000058d)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000683 (
.I0(sig000004ef),
.I1(sig000004ee),
.I2(sig000004cf),
.O(sig0000058e)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000684 (
.I0(sig000004f7),
.I1(sig000004f6),
.I2(sig000004cf),
.O(sig0000058c)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000685 (
.I0(sig000004e7),
.I1(sig000004e6),
.I2(sig000004cf),
.O(sig00000590)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000686 (
.I0(sig000004e3),
.I1(sig000004e2),
.I2(sig000004cf),
.O(sig00000591)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000687 (
.I0(sig000004eb),
.I1(sig000004ea),
.I2(sig000004cf),
.O(sig0000058f)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000688 (
.I0(sig000004db),
.I1(sig000004da),
.I2(sig000004cf),
.O(sig00000593)
);
LUT2 #(
.INIT ( 4'h7 ))
blk00000689 (
.I0(sig000004cf),
.I1(sig000004d7),
.O(sig00000594)
);
LUT3 #(
.INIT ( 8'h1F ))
blk0000068a (
.I0(sig000004df),
.I1(sig000004de),
.I2(sig000004cf),
.O(sig00000592)
);
LUT3 #(
.INIT ( 8'h01 ))
blk0000068b (
.I0(sig0000050a),
.I1(sig0000050b),
.I2(sig0000050c),
.O(sig000005b7)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000068c (
.I0(sig00000506),
.I1(sig00000507),
.I2(sig00000508),
.I3(sig00000509),
.O(sig000005b8)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000068d (
.I0(sig00000502),
.I1(sig00000503),
.I2(sig00000504),
.I3(sig00000505),
.O(sig000005b9)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000068e (
.I0(sig000004fe),
.I1(sig000004ff),
.I2(sig00000500),
.I3(sig00000501),
.O(sig000005ba)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000068f (
.I0(sig000004fa),
.I1(sig000004fb),
.I2(sig000004fc),
.I3(sig000004fd),
.O(sig000005bb)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000690 (
.I0(sig000004f6),
.I1(sig000004f7),
.I2(sig000004f8),
.I3(sig000004f9),
.O(sig000005bc)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000691 (
.I0(sig000004f2),
.I1(sig000004f3),
.I2(sig000004f4),
.I3(sig000004f5),
.O(sig000005bd)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000692 (
.I0(sig000004ee),
.I1(sig000004ef),
.I2(sig000004f0),
.I3(sig000004f1),
.O(sig000005be)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000693 (
.I0(sig000004ea),
.I1(sig000004eb),
.I2(sig000004ec),
.I3(sig000004ed),
.O(sig000005bf)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000694 (
.I0(sig000004e6),
.I1(sig000004e7),
.I2(sig000004e8),
.I3(sig000004e9),
.O(sig000005c0)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000695 (
.I0(sig000004e2),
.I1(sig000004e3),
.I2(sig000004e4),
.I3(sig000004e5),
.O(sig000005c1)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000696 (
.I0(sig000004de),
.I1(sig000004df),
.I2(sig000004e0),
.I3(sig000004e1),
.O(sig000005c2)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000697 (
.I0(sig000004da),
.I1(sig000004db),
.I2(sig000004dc),
.I3(sig000004dd),
.O(sig000005c3)
);
LUT3 #(
.INIT ( 8'h01 ))
blk00000698 (
.I0(sig000004d7),
.I1(sig000004d8),
.I2(sig000004d9),
.O(sig000005c4)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000699 (
.I0(sig00000696),
.I1(sig00000697),
.O(sig000005dc)
);
LUT6 #(
.INIT ( 64'hCCCCCCCCC3993C66 ))
blk0000069a (
.I0(sig000005f9),
.I1(sig00000601),
.I2(sig000005fb),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d4)
);
LUT6 #(
.INIT ( 64'hCCCCCCCCC3993C66 ))
blk0000069b (
.I0(sig000005fa),
.I1(sig00000602),
.I2(sig000005fc),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d5)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk0000069c (
.I0(sig00000603),
.I1(sig000005fb),
.I2(sig000005fd),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d6)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk0000069d (
.I0(sig00000604),
.I1(sig000005fc),
.I2(sig000005fe),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d7)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk0000069e (
.I0(sig00000605),
.I1(sig000005fd),
.I2(sig000005ff),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d8)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk0000069f (
.I0(sig00000606),
.I1(sig000005fe),
.I2(sig00000600),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d9)
);
LUT5 #(
.INIT ( 32'hAAAA59A6 ))
blk000006a0 (
.I0(sig00000607),
.I1(sig000005ff),
.I2(sig000005f8),
.I3(sig00000696),
.I4(sig00000697),
.O(sig000005da)
);
LUT5 #(
.INIT ( 32'hAAAA59A6 ))
blk000006a1 (
.I0(sig00000608),
.I1(sig00000600),
.I2(sig000005f8),
.I3(sig00000696),
.I4(sig00000697),
.O(sig000005db)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a2 (
.I0(sig00000666),
.I1(sig000005e6),
.I2(sig000005ef),
.O(sig000005dd)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a3 (
.I0(sig00000666),
.I1(sig000005e7),
.I2(sig000005f0),
.O(sig000005de)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a4 (
.I0(sig00000666),
.I1(sig000005e8),
.I2(sig000005f1),
.O(sig000005df)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a5 (
.I0(sig00000666),
.I1(sig000005e9),
.I2(sig000005f2),
.O(sig000005e0)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a6 (
.I0(sig00000666),
.I1(sig000005ea),
.I2(sig000005f3),
.O(sig000005e1)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a7 (
.I0(sig00000666),
.I1(sig000005eb),
.I2(sig000005f4),
.O(sig000005e2)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a8 (
.I0(sig00000666),
.I1(sig000005ec),
.I2(sig000005f5),
.O(sig000005e3)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a9 (
.I0(sig00000666),
.I1(sig000005ed),
.I2(sig000005f6),
.O(sig000005e4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006aa (
.I0(sig00000666),
.I1(sig000005ee),
.I2(sig000005f7),
.O(sig000005e5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006ab (
.I0(sig000006e4),
.I1(sig000006e9),
.I2(sig000006eb),
.O(sig000006c4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006ac (
.I0(sig000006e4),
.I1(sig000006ea),
.I2(sig000006ec),
.O(sig000006c5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006ad (
.I0(sig000006e3),
.I1(sig000006e5),
.I2(sig000006e7),
.O(sig000006c6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006ae (
.I0(sig000006e3),
.I1(sig000006e6),
.I2(sig000006e8),
.O(sig000006c7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006af (
.I0(sig000006f9),
.I1(sig000006f3),
.I2(sig000006f6),
.O(sig000006ca)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b0 (
.I0(sig000006f9),
.I1(sig000006f4),
.I2(sig000006f7),
.O(sig000006cb)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b1 (
.I0(sig000006f9),
.I1(sig000006f5),
.I2(sig000006f8),
.O(sig000006cc)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000006b2 (
.I0(sig000006f9),
.I1(sig00000118),
.O(sig000006cd)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b3 (
.I0(sig000006f1),
.I1(sig000006ed),
.I2(sig000006ee),
.O(sig000006ce)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b4 (
.I0(sig000006f1),
.I1(sig000006f2),
.I2(sig000006ef),
.O(sig000006cf)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006b5 (
.I0(sig000006f0),
.I1(sig000006f1),
.O(sig000006d0)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b6 (
.I0(sig00000118),
.I1(sig000006f1),
.I2(sig000006f9),
.O(sig00000119)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000006b7 (
.I0(sig000006e3),
.I1(sig000006e4),
.I2(sig0000011a),
.O(sig0000011b)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000006b8 (
.I0(sig0000011a),
.I1(sig000006e4),
.O(sig000006c2)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000006b9 (
.I0(sig00000118),
.I1(sig000006f2),
.O(sig000006d4)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006ba (
.I0(sig000001c2),
.I1(sig000001c1),
.I2(sig000001c0),
.I3(sig000001bf),
.O(sig000006d5)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006bb (
.I0(sig000001be),
.I1(sig000001bd),
.I2(sig000001bc),
.I3(sig000001bb),
.O(sig000006d6)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006bc (
.I0(sig000001b8),
.I1(sig000001b7),
.I2(sig000001ba),
.I3(sig000001b9),
.O(sig000006d7)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006bd (
.I0(sig000001b6),
.I1(sig000001b5),
.I2(sig000001b4),
.I3(sig000001b3),
.O(sig000006d8)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006be (
.I0(sig000001b2),
.I1(sig000001b1),
.I2(sig000001b0),
.I3(sig000001af),
.O(sig000006d9)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006bf (
.I0(sig000001ae),
.I1(sig000001ad),
.I2(sig000001ac),
.I3(sig000001ab),
.O(sig000006da)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c0 (
.I0(sig000001aa),
.I1(sig000001a9),
.I2(sig000001a8),
.I3(sig000001a7),
.O(sig000006db)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c1 (
.I0(sig000001a6),
.I1(sig000001a5),
.I2(sig000001a4),
.I3(sig000001a3),
.O(sig000006dc)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c2 (
.I0(sig000001a2),
.I1(sig000001a1),
.I2(sig000001a0),
.I3(sig0000019f),
.O(sig000006dd)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c3 (
.I0(sig0000019e),
.I1(sig0000019d),
.I2(sig0000019c),
.I3(sig0000019b),
.O(sig000006de)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c4 (
.I0(sig0000019a),
.I1(sig00000199),
.I2(sig00000198),
.I3(sig00000197),
.O(sig000006df)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c5 (
.I0(sig00000196),
.I1(sig00000195),
.I2(sig00000194),
.I3(sig00000193),
.O(sig000006e0)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c6 (
.I0(sig00000192),
.I1(sig00000191),
.I2(sig00000190),
.I3(sig0000018f),
.O(sig000006e1)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c7 (
.I0(sig0000018e),
.I1(sig0000018d),
.I2(sig0000018c),
.I3(sig0000018b),
.O(sig000006e2)
);
LUT5 #(
.INIT ( 32'h11110010 ))
blk000006c8 (
.I0(sig000006f1),
.I1(sig00000145),
.I2(sig00000148),
.I3(sig00000147),
.I4(sig00000146),
.O(sig00000713)
);
LUT5 #(
.INIT ( 32'h01010100 ))
blk000006c9 (
.I0(sig000006f1),
.I1(sig00000146),
.I2(sig00000145),
.I3(sig00000148),
.I4(sig00000147),
.O(sig00000712)
);
LUT5 #(
.INIT ( 32'h11110010 ))
blk000006ca (
.I0(sig000006f1),
.I1(sig00000149),
.I2(sig0000014c),
.I3(sig0000014b),
.I4(sig0000014a),
.O(sig00000711)
);
LUT5 #(
.INIT ( 32'h01010100 ))
blk000006cb (
.I0(sig000006f1),
.I1(sig0000014a),
.I2(sig00000149),
.I3(sig0000014c),
.I4(sig0000014b),
.O(sig00000710)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006cc (
.I0(sig00000158),
.I1(sig0000023e),
.O(sig000007b4)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006cd (
.I0(sig00000159),
.I1(sig0000023e),
.O(sig000007b5)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ce (
.I0(sig0000015b),
.I1(sig0000023e),
.O(sig000007b7)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006cf (
.I0(sig0000015c),
.I1(sig0000023e),
.O(sig000007b8)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d0 (
.I0(sig0000015a),
.I1(sig0000023e),
.O(sig000007b6)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d1 (
.I0(sig0000015e),
.I1(sig0000023e),
.O(sig000007ba)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d2 (
.I0(sig0000015f),
.I1(sig0000023e),
.O(sig000007bb)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d3 (
.I0(sig0000015d),
.I1(sig0000023e),
.O(sig000007b9)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d4 (
.I0(sig00000160),
.I1(sig0000023e),
.O(sig000007bc)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d5 (
.I0(sig00000161),
.I1(sig0000023e),
.O(sig000007bd)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d6 (
.I0(sig00000162),
.I1(sig0000023e),
.O(sig000007be)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d7 (
.I0(sig00000163),
.I1(sig0000023e),
.O(sig000007bf)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d8 (
.I0(sig00000165),
.I1(sig0000023e),
.O(sig000007c1)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d9 (
.I0(sig00000166),
.I1(sig0000023e),
.O(sig000007c2)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006da (
.I0(sig00000164),
.I1(sig0000023e),
.O(sig000007c0)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006db (
.I0(sig00000167),
.I1(sig0000023e),
.O(sig000007c3)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006dc (
.I0(sig00000168),
.I1(sig0000023e),
.O(sig000007c4)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006dd (
.I0(sig00000169),
.I1(sig0000023e),
.O(sig000007c5)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006de (
.I0(sig0000016a),
.I1(sig0000023e),
.O(sig000007c6)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006df (
.I0(sig0000016c),
.I1(sig0000023e),
.O(sig000007c8)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e0 (
.I0(sig0000016d),
.I1(sig0000023e),
.O(sig000007c9)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e1 (
.I0(sig0000016b),
.I1(sig0000023e),
.O(sig000007c7)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e2 (
.I0(sig0000016e),
.I1(sig0000023e),
.O(sig000007ca)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e3 (
.I0(sig0000016f),
.I1(sig0000023e),
.O(sig000007cb)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e4 (
.I0(sig00000170),
.I1(sig0000023e),
.O(sig000007cc)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e5 (
.I0(sig00000171),
.I1(sig0000023e),
.O(sig000007cd)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e6 (
.I0(sig00000173),
.I1(sig0000023e),
.O(sig000007cf)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e7 (
.I0(sig00000174),
.I1(sig0000023e),
.O(sig000007d0)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e8 (
.I0(sig00000172),
.I1(sig0000023e),
.O(sig000007ce)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e9 (
.I0(sig00000176),
.I1(sig0000023e),
.O(sig000007d2)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ea (
.I0(sig00000177),
.I1(sig0000023e),
.O(sig000007d3)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006eb (
.I0(sig00000175),
.I1(sig0000023e),
.O(sig000007d1)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ec (
.I0(sig00000179),
.I1(sig0000023e),
.O(sig000007d5)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ed (
.I0(sig0000017a),
.I1(sig0000023e),
.O(sig000007d6)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ee (
.I0(sig00000178),
.I1(sig0000023e),
.O(sig000007d4)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ef (
.I0(sig0000017b),
.I1(sig0000023e),
.O(sig000007d7)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f0 (
.I0(sig0000017c),
.I1(sig0000023e),
.O(sig000007d8)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f1 (
.I0(sig0000017d),
.I1(sig0000023e),
.O(sig000007d9)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f2 (
.I0(sig0000017e),
.I1(sig0000023e),
.O(sig000007da)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f3 (
.I0(sig00000180),
.I1(sig0000023e),
.O(sig000007dc)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f4 (
.I0(sig00000181),
.I1(sig0000023e),
.O(sig000007dd)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f5 (
.I0(sig0000017f),
.I1(sig0000023e),
.O(sig000007db)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f6 (
.I0(sig00000182),
.I1(sig0000023e),
.O(sig000007de)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f7 (
.I0(sig00000183),
.I1(sig0000023e),
.O(sig000007df)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f8 (
.I0(sig00000184),
.I1(sig0000023e),
.O(sig000007e0)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f9 (
.I0(sig00000185),
.I1(sig0000023e),
.O(sig000007e1)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fa (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075b),
.I3(sig00000754),
.O(sig000007e3)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fb (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075c),
.I3(sig00000755),
.O(sig000007e4)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fc (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075a),
.I3(sig00000753),
.O(sig000007e2)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fd (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075d),
.I3(sig00000756),
.O(sig000007e5)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fe (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075e),
.I3(sig00000757),
.O(sig000007e6)
);
LUT5 #(
.INIT ( 32'h55555410 ))
blk000006ff (
.I0(sig0000023d),
.I1(sig00000767),
.I2(sig0000075f),
.I3(sig00000758),
.I4(sig0000023c),
.O(sig000007e7)
);
LUT3 #(
.INIT ( 8'h0E ))
blk00000700 (
.I0(sig0000022f),
.I1(sig0000023a),
.I2(sig0000023b),
.O(sig000007e8)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000701 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000239),
.O(sig000007f2)
);
LUT3 #(
.INIT ( 8'h0E ))
blk00000702 (
.I0(sig00000230),
.I1(sig0000023a),
.I2(sig0000023b),
.O(sig000007e9)
);
LUT3 #(
.INIT ( 8'h0E ))
blk00000703 (
.I0(sig00000231),
.I1(sig0000023a),
.I2(sig0000023b),
.O(sig000007ea)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000704 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000232),
.O(sig000007eb)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000705 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000233),
.O(sig000007ec)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000706 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000234),
.O(sig000007ed)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000707 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000235),
.O(sig000007ee)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000708 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000236),
.O(sig000007ef)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000709 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000237),
.O(sig000007f0)
);
LUT3 #(
.INIT ( 8'h54 ))
blk0000070a (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000238),
.O(sig000007f1)
);
LUT6 #(
.INIT ( 64'h0001000000000001 ))
blk0000070b (
.I0(sig000002d0),
.I1(sig000002cf),
.I2(sig000002ce),
.I3(sig000002d1),
.I4(sig000002cc),
.I5(sig00000189),
.O(sig000007f3)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000070c (
.I0(sig00000188),
.I1(sig000002cb),
.I2(sig000002c7),
.I3(sig0000011d),
.O(sig000007f4)
);
LUT5 #(
.INIT ( 32'h00009009 ))
blk0000070d (
.I0(sig000002c9),
.I1(sig00000186),
.I2(sig000002c8),
.I3(sig0000011c),
.I4(sig000002cd),
.O(sig000007f5)
);
LUT5 #(
.INIT ( 32'h90000000 ))
blk0000070e (
.I0(sig00000187),
.I1(sig000002ca),
.I2(sig000007f5),
.I3(sig000007f3),
.I4(sig000007f4),
.O(sig0000030e)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000070f (
.I0(sig000002ef),
.I1(sig000002ee),
.I2(sig000002ed),
.O(sig000007f6)
);
LUT5 #(
.INIT ( 32'hAA0BAA08 ))
blk00000710 (
.I0(sig000002f0),
.I1(sig000002f1),
.I2(sig000002f2),
.I3(sig000002f3),
.I4(sig000007f6),
.O(sig000002a3)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000711 (
.I0(a[57]),
.I1(a[56]),
.I2(a[55]),
.I3(a[54]),
.I4(a[53]),
.I5(a[52]),
.O(sig000007f7)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000712 (
.I0(a[62]),
.I1(a[61]),
.I2(a[60]),
.I3(a[59]),
.I4(a[58]),
.I5(sig000007f7),
.O(sig00000280)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk00000713 (
.I0(a[57]),
.I1(a[56]),
.I2(a[55]),
.I3(a[54]),
.I4(a[53]),
.I5(a[52]),
.O(sig000007f8)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000714 (
.I0(a[62]),
.I1(a[61]),
.I2(a[60]),
.I3(a[59]),
.I4(a[58]),
.I5(sig000007f8),
.O(sig00000281)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000715 (
.I0(b[57]),
.I1(b[56]),
.I2(b[55]),
.I3(b[54]),
.I4(b[53]),
.I5(b[52]),
.O(sig000007f9)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000716 (
.I0(b[62]),
.I1(b[61]),
.I2(b[60]),
.I3(b[59]),
.I4(b[58]),
.I5(sig000007f9),
.O(sig00000282)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk00000717 (
.I0(b[57]),
.I1(b[56]),
.I2(b[55]),
.I3(b[54]),
.I4(b[53]),
.I5(b[52]),
.O(sig000007fa)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000718 (
.I0(b[62]),
.I1(b[61]),
.I2(b[60]),
.I3(b[59]),
.I4(b[58]),
.I5(sig000007fa),
.O(sig00000283)
);
LUT5 #(
.INIT ( 32'h40000000 ))
blk00000719 (
.I0(sig000002dd),
.I1(sig000002d2),
.I2(sig000002d5),
.I3(sig000002d4),
.I4(sig000002d3),
.O(sig000007fb)
);
LUT5 #(
.INIT ( 32'h80000000 ))
blk0000071a (
.I0(sig000002d9),
.I1(sig000002d8),
.I2(sig000002dc),
.I3(sig000002db),
.I4(sig000002da),
.O(sig000007fc)
);
LUT4 #(
.INIT ( 16'h8000 ))
blk0000071b (
.I0(sig000002d7),
.I1(sig000002d6),
.I2(sig000007fc),
.I3(sig000007fb),
.O(sig0000028f)
);
LUT6 #(
.INIT ( 64'h8888888880000000 ))
blk0000071c (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004ce),
.I3(sig000004cf),
.I4(sig000004d0),
.I5(sig000004d1),
.O(sig000007fd)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk0000071d (
.I0(sig000004d4),
.I1(sig000004d5),
.I2(sig000004d6),
.I3(sig000004d2),
.I4(sig000004d3),
.I5(sig000007fd),
.O(sig000004b9)
);
LUT5 #(
.INIT ( 32'h0FFF7777 ))
blk0000071e (
.I0(sig0000059b),
.I1(sig000005aa),
.I2(sig000005ab),
.I3(sig0000059d),
.I4(sig0000040e),
.O(sig000007fe)
);
LUT5 #(
.INIT ( 32'h8880BBB3 ))
blk0000071f (
.I0(sig0000059c),
.I1(sig0000040d),
.I2(sig0000040e),
.I3(sig000005c5),
.I4(sig000007fe),
.O(sig00000597)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000720 (
.I0(sig000005b4),
.I1(sig000005a7),
.I2(sig000005b6),
.I3(sig000005a9),
.I4(sig0000040d),
.O(sig000007ff)
);
LUT6 #(
.INIT ( 64'hFBBBEAAA51114000 ))
blk00000721 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000005a8),
.I3(sig000005b5),
.I4(sig000005a6),
.I5(sig000007ff),
.O(sig0000059a)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000722 (
.I0(sig000005ad),
.I1(sig0000059f),
.I2(sig000005af),
.I3(sig000005a1),
.I4(sig0000040d),
.O(sig00000800)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000723 (
.I0(sig000005ae),
.I1(sig000005a0),
.I2(sig000005ac),
.I3(sig0000059e),
.I4(sig0000040d),
.O(sig00000801)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000724 (
.I0(sig0000040e),
.I1(sig00000800),
.I2(sig00000801),
.O(sig00000598)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000725 (
.I0(sig000005b1),
.I1(sig000005a3),
.I2(sig000005b3),
.I3(sig000005a5),
.I4(sig0000040d),
.O(sig00000802)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000726 (
.I0(sig000005b2),
.I1(sig000005a4),
.I2(sig000005b0),
.I3(sig000005a2),
.I4(sig0000040d),
.O(sig00000803)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000727 (
.I0(sig0000040e),
.I1(sig00000802),
.I2(sig00000803),
.O(sig00000599)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk00000728 (
.I0(sig0000013e),
.I1(sig0000013f),
.I2(sig00000140),
.I3(sig0000013d),
.O(sig00000804)
);
LUT6 #(
.INIT ( 64'h2222020077775755 ))
blk00000729 (
.I0(sig000006f1),
.I1(sig0000014d),
.I2(sig0000014f),
.I3(sig00000150),
.I4(sig0000014e),
.I5(sig00000804),
.O(sig00000717)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000072a (
.I0(sig0000013e),
.I1(sig0000013f),
.I2(sig00000140),
.I3(sig0000013d),
.O(sig00000805)
);
LUT6 #(
.INIT ( 64'h0404040037373733 ))
blk0000072b (
.I0(sig0000014d),
.I1(sig000006f1),
.I2(sig0000014e),
.I3(sig00000150),
.I4(sig0000014f),
.I5(sig00000805),
.O(sig00000716)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk0000072c (
.I0(sig00000142),
.I1(sig00000143),
.I2(sig00000144),
.I3(sig00000141),
.O(sig00000806)
);
LUT6 #(
.INIT ( 64'h2222020077775755 ))
blk0000072d (
.I0(sig000006f1),
.I1(sig00000151),
.I2(sig00000153),
.I3(sig00000154),
.I4(sig00000152),
.I5(sig00000806),
.O(sig00000715)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000072e (
.I0(sig00000142),
.I1(sig00000143),
.I2(sig00000144),
.I3(sig00000141),
.O(sig00000807)
);
LUT6 #(
.INIT ( 64'h0404040037373733 ))
blk0000072f (
.I0(sig00000151),
.I1(sig000006f1),
.I2(sig00000152),
.I3(sig00000154),
.I4(sig00000153),
.I5(sig00000807),
.O(sig00000714)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk00000730 (
.I0(sig0000012e),
.I1(sig0000012f),
.I2(sig00000130),
.I3(sig0000012d),
.O(sig00000808)
);
LUT6 #(
.INIT ( 64'h10111010BABBBABA ))
blk00000731 (
.I0(sig000006f9),
.I1(sig0000027f),
.I2(sig0000011e),
.I3(sig0000011f),
.I4(sig00000120),
.I5(sig00000808),
.O(sig0000071f)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk00000732 (
.I0(sig0000012d),
.I1(sig0000012f),
.I2(sig00000130),
.I3(sig0000012e),
.O(sig00000809)
);
LUT6 #(
.INIT ( 64'h01010100CDCDCDCC ))
blk00000733 (
.I0(sig0000027f),
.I1(sig000006f9),
.I2(sig0000011e),
.I3(sig00000120),
.I4(sig0000011f),
.I5(sig00000809),
.O(sig0000071e)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk00000734 (
.I0(sig00000132),
.I1(sig00000133),
.I2(sig00000134),
.I3(sig00000131),
.O(sig0000080a)
);
LUT6 #(
.INIT ( 64'h10111010BABBBABA ))
blk00000735 (
.I0(sig000006f9),
.I1(sig00000121),
.I2(sig00000122),
.I3(sig00000123),
.I4(sig00000124),
.I5(sig0000080a),
.O(sig0000071d)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk00000736 (
.I0(sig00000131),
.I1(sig00000133),
.I2(sig00000134),
.I3(sig00000132),
.O(sig0000080b)
);
LUT6 #(
.INIT ( 64'h01010100CDCDCDCC ))
blk00000737 (
.I0(sig00000122),
.I1(sig000006f9),
.I2(sig00000121),
.I3(sig00000124),
.I4(sig00000123),
.I5(sig0000080b),
.O(sig0000071c)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk00000738 (
.I0(sig00000136),
.I1(sig00000137),
.I2(sig00000138),
.I3(sig00000135),
.O(sig0000080c)
);
LUT6 #(
.INIT ( 64'h10111010BABBBABA ))
blk00000739 (
.I0(sig000006f9),
.I1(sig00000125),
.I2(sig00000126),
.I3(sig00000127),
.I4(sig00000128),
.I5(sig0000080c),
.O(sig0000071b)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000073a (
.I0(sig00000135),
.I1(sig00000137),
.I2(sig00000138),
.I3(sig00000136),
.O(sig0000080d)
);
LUT6 #(
.INIT ( 64'h01010100CDCDCDCC ))
blk0000073b (
.I0(sig00000126),
.I1(sig000006f9),
.I2(sig00000125),
.I3(sig00000128),
.I4(sig00000127),
.I5(sig0000080d),
.O(sig0000071a)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk0000073c (
.I0(sig0000013a),
.I1(sig0000013b),
.I2(sig0000013c),
.I3(sig00000139),
.O(sig0000080e)
);
LUT6 #(
.INIT ( 64'h10111010BABBBABA ))
blk0000073d (
.I0(sig000006f9),
.I1(sig00000129),
.I2(sig0000012a),
.I3(sig0000012b),
.I4(sig0000012c),
.I5(sig0000080e),
.O(sig00000719)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000073e (
.I0(sig00000139),
.I1(sig0000013b),
.I2(sig0000013c),
.I3(sig0000013a),
.O(sig0000080f)
);
LUT6 #(
.INIT ( 64'h01010100CDCDCDCC ))
blk0000073f (
.I0(sig0000012a),
.I1(sig000006f9),
.I2(sig00000129),
.I3(sig0000012c),
.I4(sig0000012b),
.I5(sig0000080f),
.O(sig00000718)
);
LUT2 #(
.INIT ( 4'hD ))
blk00000740 (
.I0(sig0000003b),
.I1(sig0000011d),
.O(sig00000810)
);
LUT6 #(
.INIT ( 64'hFFFF00005D5F0000 ))
blk00000741 (
.I0(sig00000155),
.I1(sig0000003a),
.I2(sig0000011c),
.I3(sig00000810),
.I4(sig000000e2),
.I5(sig000000e3),
.O(sig00000720)
);
FD blk00000742 (
.C(clk),
.D(sig0000022b),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op )
);
LUT5 #(
.INIT ( 32'hAAAA59A6 ))
blk00000743 (
.I0(sig00000608),
.I1(sig00000600),
.I2(sig000005f8),
.I3(sig00000696),
.I4(sig00000697),
.O(sig00000811)
);
LUT5 #(
.INIT ( 32'hAAAA59A6 ))
blk00000744 (
.I0(sig00000607),
.I1(sig000005ff),
.I2(sig000005f8),
.I3(sig00000696),
.I4(sig00000697),
.O(sig00000812)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk00000745 (
.I0(sig00000606),
.I1(sig000005fe),
.I2(sig00000600),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000813)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk00000746 (
.I0(sig00000605),
.I1(sig000005fd),
.I2(sig000005ff),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000814)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk00000747 (
.I0(sig00000604),
.I1(sig000005fc),
.I2(sig000005fe),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000815)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk00000748 (
.I0(sig00000603),
.I1(sig000005fb),
.I2(sig000005fd),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000816)
);
LUT6 #(
.INIT ( 64'hCCCCCCCCC3993C66 ))
blk00000749 (
.I0(sig000005fa),
.I1(sig00000602),
.I2(sig000005fc),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000817)
);
LUT6 #(
.INIT ( 64'hCCCCCCCCC3993C66 ))
blk0000074a (
.I0(sig000005f9),
.I1(sig00000601),
.I2(sig000005fb),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000818)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074b (
.I0(sig00000761),
.O(sig00000819)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074c (
.I0(sig00000762),
.O(sig0000081a)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074d (
.I0(sig00000763),
.O(sig0000081b)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074e (
.I0(sig00000764),
.O(sig0000081c)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074f (
.I0(sig00000765),
.O(sig0000081d)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000750 (
.I0(sig00000766),
.O(sig0000081e)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000751 (
.I0(sig00000760),
.O(sig0000081f)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000752 (
.I0(sig00000761),
.O(sig00000820)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000753 (
.I0(sig00000762),
.O(sig00000821)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000754 (
.I0(sig00000763),
.O(sig00000822)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000755 (
.I0(sig00000764),
.O(sig00000823)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000756 (
.I0(sig00000765),
.O(sig00000824)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000757 (
.I0(sig00000766),
.O(sig00000825)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000758 (
.I0(sig00000760),
.O(sig00000826)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000759 (
.I0(sig00000696),
.I1(sig00000697),
.O(sig00000827)
);
LUT6 #(
.INIT ( 64'h0000FFA50000FFC3 ))
blk0000075a (
.I0(sig00000759),
.I1(sig0000059c),
.I2(sig0000022f),
.I3(sig0000023a),
.I4(sig0000023b),
.I5(sig00000767),
.O(sig000007a8)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075b (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000144),
.I3(sig00000154),
.O(sig00000082)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075c (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000143),
.I3(sig00000153),
.O(sig00000083)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075d (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013d),
.I3(sig0000014d),
.O(sig00000089)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075e (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000142),
.I3(sig00000152),
.O(sig00000084)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075f (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000141),
.I3(sig00000151),
.O(sig00000085)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000760 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000140),
.I3(sig00000150),
.O(sig00000086)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000761 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013f),
.I3(sig0000014f),
.O(sig00000087)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000762 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013e),
.I3(sig0000014e),
.O(sig00000088)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000763 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000006),
.I3(sig00000002),
.O(sig000000ae)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000764 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000007),
.I3(sig00000003),
.O(sig000000af)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000765 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000008),
.I3(sig00000004),
.O(sig000000b0)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000766 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000009),
.I3(sig00000005),
.O(sig000000b1)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000767 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000135),
.I3(sig00000145),
.O(sig00000091)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000768 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000136),
.I3(sig00000146),
.O(sig00000090)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000769 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000137),
.I3(sig00000147),
.O(sig0000008f)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076a (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000138),
.I3(sig00000148),
.O(sig0000008e)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076b (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000139),
.I3(sig00000149),
.O(sig0000008d)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076c (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013a),
.I3(sig0000014a),
.O(sig0000008c)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076d (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013b),
.I3(sig0000014b),
.O(sig0000008b)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076e (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013c),
.I3(sig0000014c),
.O(sig0000008a)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000076f (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000005),
.O(sig000000ad)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000770 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000004),
.O(sig000000ac)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000771 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000003),
.O(sig000000ab)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000772 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000002),
.O(sig000000aa)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000773 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000145),
.O(sig00000081)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000774 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000146),
.O(sig00000080)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000775 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000147),
.O(sig0000007f)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000776 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000148),
.O(sig0000007e)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000777 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000149),
.O(sig0000007d)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000778 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014a),
.O(sig0000007c)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000779 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014b),
.O(sig0000007b)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077a (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014c),
.O(sig0000007a)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077b (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014d),
.O(sig00000079)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077c (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014e),
.O(sig00000078)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077d (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014f),
.O(sig00000077)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077e (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000150),
.O(sig00000076)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077f (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000151),
.O(sig00000075)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000780 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000152),
.O(sig00000074)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000781 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000153),
.O(sig00000073)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000782 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000154),
.O(sig00000072)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000783 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig0000000a),
.I3(sig00000006),
.I4(sig000006e3),
.I5(sig00000002),
.O(sig000000b2)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000784 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig0000000b),
.I3(sig00000007),
.I4(sig000006e3),
.I5(sig00000003),
.O(sig000000b3)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000785 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig0000000c),
.I3(sig00000008),
.I4(sig000006e3),
.I5(sig00000004),
.O(sig000000b4)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000786 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig0000000d),
.I3(sig00000009),
.I4(sig000006e3),
.I5(sig00000005),
.O(sig000000b5)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000787 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000127),
.I3(sig00000137),
.I4(sig000006f1),
.I5(sig00000147),
.O(sig0000009f)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000788 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000128),
.I3(sig00000138),
.I4(sig000006f1),
.I5(sig00000148),
.O(sig0000009e)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000789 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000129),
.I3(sig00000139),
.I4(sig000006f1),
.I5(sig00000149),
.O(sig0000009d)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078a (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012a),
.I3(sig0000013a),
.I4(sig000006f1),
.I5(sig0000014a),
.O(sig0000009c)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078b (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012b),
.I3(sig0000013b),
.I4(sig000006f1),
.I5(sig0000014b),
.O(sig0000009b)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078c (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012c),
.I3(sig0000013c),
.I4(sig000006f1),
.I5(sig0000014c),
.O(sig0000009a)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078d (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012d),
.I3(sig0000013d),
.I4(sig000006f1),
.I5(sig0000014d),
.O(sig00000099)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078e (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012e),
.I3(sig0000013e),
.I4(sig000006f1),
.I5(sig0000014e),
.O(sig00000098)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078f (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012f),
.I3(sig0000013f),
.I4(sig000006f1),
.I5(sig0000014f),
.O(sig00000097)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000790 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000130),
.I3(sig00000140),
.I4(sig000006f1),
.I5(sig00000150),
.O(sig00000096)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000791 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000131),
.I3(sig00000141),
.I4(sig000006f1),
.I5(sig00000151),
.O(sig00000095)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000792 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000132),
.I3(sig00000142),
.I4(sig000006f1),
.I5(sig00000152),
.O(sig00000094)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000793 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000133),
.I3(sig00000143),
.I4(sig000006f1),
.I5(sig00000153),
.O(sig00000093)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000794 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000134),
.I3(sig00000144),
.I4(sig000006f1),
.I5(sig00000154),
.O(sig00000092)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000795 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000125),
.I3(sig00000135),
.I4(sig000006f1),
.I5(sig00000145),
.O(sig000000a1)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000796 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000126),
.I3(sig00000136),
.I4(sig000006f1),
.I5(sig00000146),
.O(sig000000a0)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFEEE0444 ))
blk00000797 (
.I0(sig0000027b),
.I1(sig000001f6),
.I2(sig0000027a),
.I3(sig0000027c),
.I4(sig0000022a),
.I5(sig0000023f),
.O(sig00000542)
);
LUT6 #(
.INIT ( 64'hAAA8A8A800202020 ))
blk00000798 (
.I0(sig0000023f),
.I1(sig0000027b),
.I2(sig000001c3),
.I3(sig0000027a),
.I4(sig0000027c),
.I5(sig000001f7),
.O(sig0000050e)
);
LUT2 #(
.INIT ( 4'h7 ))
blk00000799 (
.I0(sig0000030f),
.I1(sig00000312),
.O(sig00000579)
);
LUT3 #(
.INIT ( 8'h01 ))
blk0000079a (
.I0(sig000004cb),
.I1(sig000004cd),
.I2(sig00000544),
.O(sig000004b7)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000079b (
.I0(sig000004cd),
.I1(sig00000544),
.I2(sig000004cb),
.O(sig000004b8)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000079c (
.I0(sig000004cd),
.I1(sig00000544),
.I2(sig000004b4),
.O(sig000004ba)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk0000079d (
.I0(sig000001c3),
.I1(sig000001f7),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000545)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk0000079e (
.I0(sig000001cd),
.I1(sig00000201),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054f)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk0000079f (
.I0(sig000001ce),
.I1(sig00000202),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000550)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a0 (
.I0(sig000001cf),
.I1(sig00000203),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000551)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a1 (
.I0(sig000001d0),
.I1(sig00000204),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000552)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a2 (
.I0(sig000001d1),
.I1(sig00000205),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000553)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a3 (
.I0(sig000001d2),
.I1(sig00000206),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000554)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a4 (
.I0(sig000001d3),
.I1(sig00000207),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000555)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a5 (
.I0(sig000001d4),
.I1(sig00000208),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000556)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a6 (
.I0(sig000001d5),
.I1(sig00000209),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000557)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a7 (
.I0(sig000001d6),
.I1(sig0000020a),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000558)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a8 (
.I0(sig000001c4),
.I1(sig000001f8),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000546)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a9 (
.I0(sig000001d7),
.I1(sig0000020b),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000559)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007aa (
.I0(sig000001d8),
.I1(sig0000020c),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055a)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ab (
.I0(sig000001d9),
.I1(sig0000020d),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055b)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ac (
.I0(sig000001da),
.I1(sig0000020e),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055c)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ad (
.I0(sig000001db),
.I1(sig0000020f),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055d)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ae (
.I0(sig000001dc),
.I1(sig00000210),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055e)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007af (
.I0(sig000001dd),
.I1(sig00000211),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055f)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b0 (
.I0(sig000001de),
.I1(sig00000212),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000560)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b1 (
.I0(sig000001df),
.I1(sig00000213),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000561)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b2 (
.I0(sig000001e0),
.I1(sig00000214),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000562)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b3 (
.I0(sig000001c5),
.I1(sig000001f9),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000547)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b4 (
.I0(sig000001e1),
.I1(sig00000215),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000563)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b5 (
.I0(sig000001e2),
.I1(sig00000216),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000564)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b6 (
.I0(sig000001e3),
.I1(sig00000217),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000565)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b7 (
.I0(sig000001e4),
.I1(sig00000218),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000566)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b8 (
.I0(sig000001e5),
.I1(sig00000219),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000567)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b9 (
.I0(sig000001e6),
.I1(sig0000021a),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000568)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ba (
.I0(sig000001e7),
.I1(sig0000021b),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000569)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007bb (
.I0(sig000001e8),
.I1(sig0000021c),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056a)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007bc (
.I0(sig000001e9),
.I1(sig0000021d),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056b)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007bd (
.I0(sig000001ea),
.I1(sig0000021e),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056c)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007be (
.I0(sig000001c6),
.I1(sig000001fa),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000548)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007bf (
.I0(sig000001eb),
.I1(sig0000021f),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056d)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c0 (
.I0(sig000001ec),
.I1(sig00000220),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056e)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c1 (
.I0(sig000001ed),
.I1(sig00000221),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056f)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c2 (
.I0(sig000001ee),
.I1(sig00000222),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000570)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c3 (
.I0(sig000001ef),
.I1(sig00000223),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000571)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c4 (
.I0(sig000001f0),
.I1(sig00000224),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000572)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c5 (
.I0(sig000001f1),
.I1(sig00000225),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000573)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c6 (
.I0(sig000001f2),
.I1(sig00000226),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000574)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c7 (
.I0(sig000001f3),
.I1(sig00000227),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000575)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c8 (
.I0(sig000001f4),
.I1(sig00000228),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000576)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c9 (
.I0(sig000001c7),
.I1(sig000001fb),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000549)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ca (
.I0(sig000001f5),
.I1(sig00000229),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000577)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007cb (
.I0(sig000001f6),
.I1(sig0000022a),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000578)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007cc (
.I0(sig000001c8),
.I1(sig000001fc),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054a)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007cd (
.I0(sig000001c9),
.I1(sig000001fd),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054b)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ce (
.I0(sig000001ca),
.I1(sig000001fe),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054c)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007cf (
.I0(sig000001cb),
.I1(sig000001ff),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054d)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007d0 (
.I0(sig000001cc),
.I1(sig00000200),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054e)
);
LUT1 #(
.INIT ( 2'h2 ))
blk000007d1 (
.I0(sig0000023f),
.O(sig00000828)
);
INV blk000007d2 (
.I(sig0000023f),
.O(sig00000543)
);
INV blk000007d3 (
.I(sig000002d1),
.O(sig0000024c)
);
INV blk000007d4 (
.I(sig000002cd),
.O(sig00000254)
);
INV blk000007d5 (
.I(sig000002ce),
.O(sig00000252)
);
INV blk000007d6 (
.I(sig000002cf),
.O(sig00000250)
);
INV blk000007d7 (
.I(sig000002d0),
.O(sig0000024e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007d8 (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000027f),
.Q(sig00000829),
.Q15(NLW_blk000007d8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d9 (
.C(clk),
.CE(sig00000001),
.D(sig00000829),
.Q(sig0000030d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007da (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003b0),
.Q(sig0000082a),
.Q15(NLW_blk000007da_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007db (
.C(clk),
.CE(sig00000001),
.D(sig0000082a),
.Q(sig000002ec)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007dc (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003af),
.Q(sig0000082b),
.Q15(NLW_blk000007dc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007dd (
.C(clk),
.CE(sig00000001),
.D(sig0000082b),
.Q(sig000002eb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007de (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003b1),
.Q(sig0000082c),
.Q15(NLW_blk000007de_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007df (
.C(clk),
.CE(sig00000001),
.D(sig0000082c),
.Q(sig000002ea)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e0 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002dc),
.Q(sig0000082d),
.Q15(NLW_blk000007e0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e1 (
.C(clk),
.CE(sig00000001),
.D(sig0000082d),
.Q(sig000002d1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e2 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002db),
.Q(sig0000082e),
.Q15(NLW_blk000007e2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e3 (
.C(clk),
.CE(sig00000001),
.D(sig0000082e),
.Q(sig000002d0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e4 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002da),
.Q(sig0000082f),
.Q15(NLW_blk000007e4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e5 (
.C(clk),
.CE(sig00000001),
.D(sig0000082f),
.Q(sig000002cf)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e6 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d9),
.Q(sig00000830),
.Q15(NLW_blk000007e6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e7 (
.C(clk),
.CE(sig00000001),
.D(sig00000830),
.Q(sig000002ce)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e8 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d8),
.Q(sig00000831),
.Q15(NLW_blk000007e8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e9 (
.C(clk),
.CE(sig00000001),
.D(sig00000831),
.Q(sig000002cd)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007ea (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d7),
.Q(sig00000832),
.Q15(NLW_blk000007ea_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007eb (
.C(clk),
.CE(sig00000001),
.D(sig00000832),
.Q(sig000002cc)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007ec (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d6),
.Q(sig00000833),
.Q15(NLW_blk000007ec_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ed (
.C(clk),
.CE(sig00000001),
.D(sig00000833),
.Q(sig000002cb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007ee (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d3),
.Q(sig00000834),
.Q15(NLW_blk000007ee_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ef (
.C(clk),
.CE(sig00000001),
.D(sig00000834),
.Q(sig000002c8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f0 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d5),
.Q(sig00000835),
.Q15(NLW_blk000007f0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f1 (
.C(clk),
.CE(sig00000001),
.D(sig00000835),
.Q(sig000002ca)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f2 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d4),
.Q(sig00000836),
.Q15(NLW_blk000007f2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f3 (
.C(clk),
.CE(sig00000001),
.D(sig00000836),
.Q(sig000002c9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f4 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d2),
.Q(sig00000837),
.Q15(NLW_blk000007f4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f5 (
.C(clk),
.CE(sig00000001),
.D(sig00000837),
.Q(sig000002c7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f6 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003bd),
.Q(sig00000838),
.Q15(NLW_blk000007f6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f7 (
.C(clk),
.CE(sig00000001),
.D(sig00000838),
.Q(sig000002c6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f8 (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003d3),
.Q(sig00000839),
.Q15(NLW_blk000007f8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f9 (
.C(clk),
.CE(sig00000001),
.D(sig00000839),
.Q(sig0000018a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007fa (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000004cb),
.Q(sig0000083a),
.Q15(NLW_blk000007fa_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007fb (
.C(clk),
.CE(sig00000001),
.D(sig0000083a),
.Q(sig000005f8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007fc (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069d),
.Q(sig0000083b),
.Q15(NLW_blk000007fc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007fd (
.C(clk),
.CE(sig00000001),
.D(sig0000083b),
.Q(sig00000606)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007fe (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069f),
.Q(sig0000083c),
.Q15(NLW_blk000007fe_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ff (
.C(clk),
.CE(sig00000001),
.D(sig0000083c),
.Q(sig00000608)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000800 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069e),
.Q(sig0000083d),
.Q15(NLW_blk00000800_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000801 (
.C(clk),
.CE(sig00000001),
.D(sig0000083d),
.Q(sig00000607)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000802 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069c),
.Q(sig0000083e),
.Q15(NLW_blk00000802_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000803 (
.C(clk),
.CE(sig00000001),
.D(sig0000083e),
.Q(sig00000605)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000804 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069b),
.Q(sig0000083f),
.Q15(NLW_blk00000804_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000805 (
.C(clk),
.CE(sig00000001),
.D(sig0000083f),
.Q(sig00000604)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000806 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069a),
.Q(sig00000840),
.Q15(NLW_blk00000806_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000807 (
.C(clk),
.CE(sig00000001),
.D(sig00000840),
.Q(sig00000603)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000808 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig00000699),
.Q(sig00000841),
.Q15(NLW_blk00000808_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000809 (
.C(clk),
.CE(sig00000001),
.D(sig00000841),
.Q(sig00000602)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000080a (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig00000119),
.Q(sig00000842),
.Q15(NLW_blk0000080a_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000080b (
.C(clk),
.CE(sig00000001),
.D(sig00000842),
.Q(sig00000188)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000080c (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig00000698),
.Q(sig00000843),
.Q15(NLW_blk0000080c_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000080d (
.C(clk),
.CE(sig00000001),
.D(sig00000843),
.Q(sig00000601)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000080e (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig00000118),
.Q(sig00000844),
.Q15(NLW_blk0000080e_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000080f (
.C(clk),
.CE(sig00000001),
.D(sig00000844),
.Q(sig00000189)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000810 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000018a),
.Q(sig00000845),
.Q15(NLW_blk00000810_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000811 (
.C(clk),
.CE(sig00000001),
.D(sig00000845),
.Q(sig00000155)
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 0 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "NONE" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000812 (
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000812_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig000006c3),
.CEB1(sig00000001),
.MULTSIGNOUT(NLW_blk00000812_MULTSIGNOUT_UNCONNECTED),
.CEC(sig000006c3),
.RSTM(sig000006c3),
.MULTSIGNIN(sig000006c3),
.CEB2(sig00000001),
.RSTCTRL(sig000006c3),
.CEP(sig00000001),
.CARRYCASCOUT(NLW_blk00000812_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig000006c3),
.CECARRYIN(sig000006c3),
.UNDERFLOW(NLW_blk00000812_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000812_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig000006c3),
.RSTALLCARRYIN(sig000006c3),
.CEALUMODE(sig000006c3),
.CEA2(sig00000001),
.CEA1(sig00000001),
.RSTB(sig000006c3),
.CEMULTCARRYIN(sig000006c3),
.OVERFLOW(NLW_blk00000812_OVERFLOW_UNCONNECTED),
.CECTRL(sig000006c3),
.CEM(sig000006c3),
.CARRYIN(sig000006c3),
.CARRYCASCIN(sig000006c3),
.RSTP(sig000006c3),
.CARRYINSEL({sig000006c3, sig000006c3, sig000006c3}),
.OPMODE({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig00000001, sig00000001}),
.B({sig00000648, sig00000647, sig00000646, sig00000645, sig00000644, sig00000643, sig00000642, sig00000641, sig00000640, sig0000063f, sig0000063e
, sig0000063d, sig0000063c, sig0000063b, sig0000063a, sig00000639, sig000006c3, sig000006c3}),
.A({sig000006c3, sig00000665, sig00000664, sig00000663, sig00000662, sig00000661, sig00000660, sig0000065f, sig0000065e, sig0000065d, sig0000065c
, sig0000065b, sig0000065a, sig00000659, sig00000658, sig00000657, sig00000656, sig00000655, sig00000654, sig00000653, sig00000652, sig00000651,
sig00000650, sig0000064f, sig0000064e, sig0000064d, sig0000064c, sig0000064b, sig0000064a, sig00000649}),
.PCOUT({sig00000638, sig00000637, sig00000636, sig00000635, sig00000634, sig00000633, sig00000632, sig00000631, sig00000630, sig0000062f,
sig0000062e, sig0000062d, sig0000062c, sig0000062b, sig0000062a, sig00000629, sig00000628, sig00000627, sig00000626, sig00000625, sig00000624,
sig00000623, sig00000622, sig00000621, sig00000620, sig0000061f, sig0000061e, sig0000061d, sig0000061c, sig0000061b, sig0000061a, sig00000619,
sig00000618, sig00000617, sig00000616, sig00000615, sig00000614, sig00000613, sig00000612, sig00000611, sig00000610, sig0000060f, sig0000060e,
sig0000060d, sig0000060c, sig0000060b, sig0000060a, sig00000609}),
.ACOUT({\NLW_blk00000812_ACOUT<29>_UNCONNECTED , \NLW_blk00000812_ACOUT<28>_UNCONNECTED , \NLW_blk00000812_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<26>_UNCONNECTED , \NLW_blk00000812_ACOUT<25>_UNCONNECTED , \NLW_blk00000812_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<23>_UNCONNECTED , \NLW_blk00000812_ACOUT<22>_UNCONNECTED , \NLW_blk00000812_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<20>_UNCONNECTED , \NLW_blk00000812_ACOUT<19>_UNCONNECTED , \NLW_blk00000812_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<17>_UNCONNECTED , \NLW_blk00000812_ACOUT<16>_UNCONNECTED , \NLW_blk00000812_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<14>_UNCONNECTED , \NLW_blk00000812_ACOUT<13>_UNCONNECTED , \NLW_blk00000812_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<11>_UNCONNECTED , \NLW_blk00000812_ACOUT<10>_UNCONNECTED , \NLW_blk00000812_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<8>_UNCONNECTED , \NLW_blk00000812_ACOUT<7>_UNCONNECTED , \NLW_blk00000812_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<5>_UNCONNECTED , \NLW_blk00000812_ACOUT<4>_UNCONNECTED , \NLW_blk00000812_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<2>_UNCONNECTED , \NLW_blk00000812_ACOUT<1>_UNCONNECTED , \NLW_blk00000812_ACOUT<0>_UNCONNECTED }),
.PCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.ALUMODE({sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.C({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3
, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.CARRYOUT({\NLW_blk00000812_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000812_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000812_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000812_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.BCOUT({\NLW_blk00000812_BCOUT<17>_UNCONNECTED , \NLW_blk00000812_BCOUT<16>_UNCONNECTED , \NLW_blk00000812_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<14>_UNCONNECTED , \NLW_blk00000812_BCOUT<13>_UNCONNECTED , \NLW_blk00000812_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<11>_UNCONNECTED , \NLW_blk00000812_BCOUT<10>_UNCONNECTED , \NLW_blk00000812_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<8>_UNCONNECTED , \NLW_blk00000812_BCOUT<7>_UNCONNECTED , \NLW_blk00000812_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<5>_UNCONNECTED , \NLW_blk00000812_BCOUT<4>_UNCONNECTED , \NLW_blk00000812_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<2>_UNCONNECTED , \NLW_blk00000812_BCOUT<1>_UNCONNECTED , \NLW_blk00000812_BCOUT<0>_UNCONNECTED }),
.P({\NLW_blk00000812_P<47>_UNCONNECTED , \NLW_blk00000812_P<46>_UNCONNECTED , \NLW_blk00000812_P<45>_UNCONNECTED ,
\NLW_blk00000812_P<44>_UNCONNECTED , \NLW_blk00000812_P<43>_UNCONNECTED , \NLW_blk00000812_P<42>_UNCONNECTED , \NLW_blk00000812_P<41>_UNCONNECTED ,
\NLW_blk00000812_P<40>_UNCONNECTED , \NLW_blk00000812_P<39>_UNCONNECTED , \NLW_blk00000812_P<38>_UNCONNECTED , \NLW_blk00000812_P<37>_UNCONNECTED ,
\NLW_blk00000812_P<36>_UNCONNECTED , \NLW_blk00000812_P<35>_UNCONNECTED , \NLW_blk00000812_P<34>_UNCONNECTED , \NLW_blk00000812_P<33>_UNCONNECTED ,
\NLW_blk00000812_P<32>_UNCONNECTED , \NLW_blk00000812_P<31>_UNCONNECTED , \NLW_blk00000812_P<30>_UNCONNECTED , \NLW_blk00000812_P<29>_UNCONNECTED ,
\NLW_blk00000812_P<28>_UNCONNECTED , \NLW_blk00000812_P<27>_UNCONNECTED , \NLW_blk00000812_P<26>_UNCONNECTED , \NLW_blk00000812_P<25>_UNCONNECTED ,
\NLW_blk00000812_P<24>_UNCONNECTED , \NLW_blk00000812_P<23>_UNCONNECTED , \NLW_blk00000812_P<22>_UNCONNECTED , \NLW_blk00000812_P<21>_UNCONNECTED ,
\NLW_blk00000812_P<20>_UNCONNECTED , \NLW_blk00000812_P<19>_UNCONNECTED , \NLW_blk00000812_P<18>_UNCONNECTED , \NLW_blk00000812_P<17>_UNCONNECTED ,
\NLW_blk00000812_P<16>_UNCONNECTED , \NLW_blk00000812_P<15>_UNCONNECTED , \NLW_blk00000812_P<14>_UNCONNECTED , \NLW_blk00000812_P<13>_UNCONNECTED ,
\NLW_blk00000812_P<12>_UNCONNECTED , \NLW_blk00000812_P<11>_UNCONNECTED , \NLW_blk00000812_P<10>_UNCONNECTED , \NLW_blk00000812_P<9>_UNCONNECTED ,
\NLW_blk00000812_P<8>_UNCONNECTED , \NLW_blk00000812_P<7>_UNCONNECTED , \NLW_blk00000812_P<6>_UNCONNECTED , \NLW_blk00000812_P<5>_UNCONNECTED ,
\NLW_blk00000812_P<4>_UNCONNECTED , \NLW_blk00000812_P<3>_UNCONNECTED , \NLW_blk00000812_P<2>_UNCONNECTED , \NLW_blk00000812_P<1>_UNCONNECTED ,
\NLW_blk00000812_P<0>_UNCONNECTED }),
.ACIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3})
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 1 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 1 ),
.CARRYINSELREG ( 1 ),
.CREG ( 1 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 0 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 1 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "NONE" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000813 (
.RSTALLCARRYIN(sig000004cc),
.CLK(clk),
.CARRYIN(sig0000050d),
.PATTERNBDETECT(NLW_blk00000813_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig000006c3),
.CEB1(sig000006c3),
.MULTSIGNOUT(NLW_blk00000813_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000001),
.RSTM(sig000006c3),
.MULTSIGNIN(sig000006c3),
.CEB2(sig00000001),
.RSTCTRL(sig000006c3),
.CEP(sig00000001),
.CARRYCASCOUT(NLW_blk00000813_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig000006c3),
.CECARRYIN(sig00000001),
.UNDERFLOW(NLW_blk00000813_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000813_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig000006c3),
.CEALUMODE(sig00000001),
.CEA2(sig00000001),
.CEA1(sig000006c3),
.RSTB(sig000006c3),
.CEMULTCARRYIN(sig000006c3),
.OVERFLOW(NLW_blk00000813_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000001),
.CEM(sig000006c3),
.CARRYCASCIN(sig000006c3),
.RSTP(sig000006c3),
.CARRYINSEL({sig000006c3, sig000006c3, sig000006c3}),
.OPMODE({sig000006c3, sig000006c3, sig00000001, sig000004c7, sig000004c7, sig000004c8, sig000004c8}),
.PCIN({sig00000638, sig00000637, sig00000636, sig00000635, sig00000634, sig00000633, sig00000632, sig00000631, sig00000630, sig0000062f,
sig0000062e, sig0000062d, sig0000062c, sig0000062b, sig0000062a, sig00000629, sig00000628, sig00000627, sig00000626, sig00000625, sig00000624,
sig00000623, sig00000622, sig00000621, sig00000620, sig0000061f, sig0000061e, sig0000061d, sig0000061c, sig0000061b, sig0000061a, sig00000619,
sig00000618, sig00000617, sig00000616, sig00000615, sig00000614, sig00000613, sig00000612, sig00000611, sig00000610, sig0000060f, sig0000060e,
sig0000060d, sig0000060c, sig0000060b, sig0000060a, sig00000609}),
.A({sig000004c9, sig00000485, sig00000486, sig00000487, sig00000488, sig00000489, sig0000048a, sig0000048b, sig0000048c, sig0000048d, sig0000048e
, sig0000048f, sig00000490, sig00000491, sig00000492, sig00000493, sig00000494, sig00000495, sig00000496, sig00000497, sig00000498, sig00000499,
sig0000049a, sig0000049b, sig0000049c, sig0000049d, sig0000049e, sig0000049f, sig000004a0, sig000004a1}),
.C({sig000004c9, sig00000483, sig00000484, sig00000485, sig00000486, sig00000487, sig00000488, sig00000489, sig0000048a, sig0000048b, sig0000048c
, sig0000048d, sig0000048e, sig0000048f, sig00000490, sig00000491, sig00000492, sig00000493, sig00000494, sig00000495, sig00000496, sig00000497,
sig00000498, sig00000499, sig0000049a, sig0000049b, sig0000049c, sig0000049d, sig0000049e, sig0000049f, sig000004a0, sig000004a1, sig000004a2,
sig000004a3, sig000004a4, sig000004a5, sig000004a6, sig000004a7, sig000004a8, sig000004a9, sig000004aa, sig000004ab, sig000004ac, sig000004ad,
sig000004ae, sig000004af, sig000004b0, sig000004b1}),
.B({sig000004a2, sig000004a3, sig000004a4, sig000004a5, sig000004a6, sig000004a7, sig000004a8, sig000004a9, sig000004aa, sig000004ab, sig000004ac
, sig000004ad, sig000004ae, sig000004af, sig000004b0, sig000004b1, sig000004b2, sig000004b3}),
.P({sig00000666, sig00000695, sig00000694, sig00000693, sig00000692, sig00000691, sig00000690, sig0000068f, sig0000068e, sig0000068d, sig0000068c
, sig0000068b, sig0000068a, sig00000689, sig00000688, sig00000687, sig00000686, sig00000685, sig00000684, sig00000683, sig00000682, sig00000681,
sig00000680, sig0000067f, sig0000067e, sig0000067d, sig0000067c, sig0000067b, sig0000067a, sig00000679, sig00000678, sig00000677, sig00000676,
sig00000675, sig00000674, sig00000673, sig00000672, sig00000671, sig00000670, sig0000066f, sig0000066e, sig0000066d, sig0000066c, sig0000066b,
sig0000066a, sig00000669, sig00000668, sig00000667}),
.ACOUT({\NLW_blk00000813_ACOUT<29>_UNCONNECTED , \NLW_blk00000813_ACOUT<28>_UNCONNECTED , \NLW_blk00000813_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<26>_UNCONNECTED , \NLW_blk00000813_ACOUT<25>_UNCONNECTED , \NLW_blk00000813_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<23>_UNCONNECTED , \NLW_blk00000813_ACOUT<22>_UNCONNECTED , \NLW_blk00000813_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<20>_UNCONNECTED , \NLW_blk00000813_ACOUT<19>_UNCONNECTED , \NLW_blk00000813_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<17>_UNCONNECTED , \NLW_blk00000813_ACOUT<16>_UNCONNECTED , \NLW_blk00000813_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<14>_UNCONNECTED , \NLW_blk00000813_ACOUT<13>_UNCONNECTED , \NLW_blk00000813_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<11>_UNCONNECTED , \NLW_blk00000813_ACOUT<10>_UNCONNECTED , \NLW_blk00000813_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<8>_UNCONNECTED , \NLW_blk00000813_ACOUT<7>_UNCONNECTED , \NLW_blk00000813_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<5>_UNCONNECTED , \NLW_blk00000813_ACOUT<4>_UNCONNECTED , \NLW_blk00000813_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<2>_UNCONNECTED , \NLW_blk00000813_ACOUT<1>_UNCONNECTED , \NLW_blk00000813_ACOUT<0>_UNCONNECTED }),
.ALUMODE({sig000006c3, sig000006c3, sig000004c9, sig000004c9}),
.CARRYOUT({\NLW_blk00000813_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000813_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000813_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000813_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.BCOUT({\NLW_blk00000813_BCOUT<17>_UNCONNECTED , \NLW_blk00000813_BCOUT<16>_UNCONNECTED , \NLW_blk00000813_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<14>_UNCONNECTED , \NLW_blk00000813_BCOUT<13>_UNCONNECTED , \NLW_blk00000813_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<11>_UNCONNECTED , \NLW_blk00000813_BCOUT<10>_UNCONNECTED , \NLW_blk00000813_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<8>_UNCONNECTED , \NLW_blk00000813_BCOUT<7>_UNCONNECTED , \NLW_blk00000813_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<5>_UNCONNECTED , \NLW_blk00000813_BCOUT<4>_UNCONNECTED , \NLW_blk00000813_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<2>_UNCONNECTED , \NLW_blk00000813_BCOUT<1>_UNCONNECTED , \NLW_blk00000813_BCOUT<0>_UNCONNECTED }),
.PCOUT({\NLW_blk00000813_PCOUT<47>_UNCONNECTED , \NLW_blk00000813_PCOUT<46>_UNCONNECTED , \NLW_blk00000813_PCOUT<45>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<44>_UNCONNECTED , \NLW_blk00000813_PCOUT<43>_UNCONNECTED , \NLW_blk00000813_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<41>_UNCONNECTED , \NLW_blk00000813_PCOUT<40>_UNCONNECTED , \NLW_blk00000813_PCOUT<39>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<38>_UNCONNECTED , \NLW_blk00000813_PCOUT<37>_UNCONNECTED , \NLW_blk00000813_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<35>_UNCONNECTED , \NLW_blk00000813_PCOUT<34>_UNCONNECTED , \NLW_blk00000813_PCOUT<33>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<32>_UNCONNECTED , \NLW_blk00000813_PCOUT<31>_UNCONNECTED , \NLW_blk00000813_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<29>_UNCONNECTED , \NLW_blk00000813_PCOUT<28>_UNCONNECTED , \NLW_blk00000813_PCOUT<27>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<26>_UNCONNECTED , \NLW_blk00000813_PCOUT<25>_UNCONNECTED , \NLW_blk00000813_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<23>_UNCONNECTED , \NLW_blk00000813_PCOUT<22>_UNCONNECTED , \NLW_blk00000813_PCOUT<21>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<20>_UNCONNECTED , \NLW_blk00000813_PCOUT<19>_UNCONNECTED , \NLW_blk00000813_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<17>_UNCONNECTED , \NLW_blk00000813_PCOUT<16>_UNCONNECTED , \NLW_blk00000813_PCOUT<15>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<14>_UNCONNECTED , \NLW_blk00000813_PCOUT<13>_UNCONNECTED , \NLW_blk00000813_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<11>_UNCONNECTED , \NLW_blk00000813_PCOUT<10>_UNCONNECTED , \NLW_blk00000813_PCOUT<9>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<8>_UNCONNECTED , \NLW_blk00000813_PCOUT<7>_UNCONNECTED , \NLW_blk00000813_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<5>_UNCONNECTED , \NLW_blk00000813_PCOUT<4>_UNCONNECTED , \NLW_blk00000813_PCOUT<3>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<2>_UNCONNECTED , \NLW_blk00000813_PCOUT<1>_UNCONNECTED , \NLW_blk00000813_PCOUT<0>_UNCONNECTED }),
.ACIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3})
);
DSP48E #(
.ACASCREG ( 0 ),
.ALUMODEREG ( 1 ),
.AREG ( 0 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 1 ),
.CARRYINSELREG ( 1 ),
.CREG ( 1 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 0 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 1 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "NONE" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000814 (
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000814_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig000006c3),
.CEB1(sig000006c3),
.MULTSIGNOUT(NLW_blk00000814_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000001),
.RSTM(sig000006c3),
.MULTSIGNIN(sig000006c3),
.CEB2(sig00000001),
.RSTCTRL(sig000006c3),
.CEP(sig00000001),
.CARRYCASCOUT(NLW_blk00000814_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig000006c3),
.CECARRYIN(sig00000001),
.UNDERFLOW(NLW_blk00000814_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000814_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig000006c3),
.RSTALLCARRYIN(sig000006c3),
.CEALUMODE(sig00000001),
.CEA2(sig000006c3),
.CEA1(sig000006c3),
.RSTB(sig000006c3),
.CEMULTCARRYIN(sig000006c3),
.OVERFLOW(NLW_blk00000814_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000001),
.CEM(sig000006c3),
.CARRYIN(sig000006c3),
.CARRYCASCIN(sig000006c3),
.RSTP(sig000006c3),
.CARRYINSEL({sig000006c3, sig000006c3, sig000006c3}),
.OPMODE({sig000006c3, sig00000001, sig00000001, sig000006c3, sig000006c3, sig00000001, sig00000001}),
.C({sig000006c3, sig00000752, sig0000079d, sig0000079c, sig0000079b, sig0000079a, sig00000799, sig00000798, sig00000797, sig00000796, sig00000795
, sig00000794, sig00000793, sig00000792, sig00000791, sig00000790, sig0000078f, sig0000078e, sig0000078d, sig0000078c, sig0000078b, sig0000078a,
sig00000789, sig00000788, sig00000787, sig00000786, sig00000785, sig00000784, sig00000783, sig00000782, sig00000781, sig00000780, sig0000077f,
sig0000077e, sig0000077d, sig0000077c, sig0000077b, sig0000077a, sig00000779, sig00000778, sig00000777, sig00000776, sig00000775, sig00000774,
sig00000773, sig00000772, sig00000771, sig00000770}),
.B({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3
, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig00000768, sig000006c3}),
.P({sig00000767, sig00000185, sig00000184, sig00000183, sig00000182, sig00000181, sig00000180, sig0000017f, sig0000017e, sig0000017d, sig0000017c
, sig0000017b, sig0000017a, sig00000179, sig00000178, sig00000177, sig00000176, sig00000175, sig00000174, sig00000173, sig00000172, sig00000171,
sig00000170, sig0000016f, sig0000016e, sig0000016d, sig0000016c, sig0000016b, sig0000016a, sig00000169, sig00000168, sig00000167, sig00000166,
sig00000165, sig00000164, sig00000163, sig00000162, sig00000161, sig00000160, sig0000015f, sig0000015e, sig0000015d, sig0000015c, sig0000015b,
sig0000015a, sig00000159, sig00000158, \NLW_blk00000814_P<0>_UNCONNECTED }),
.ACOUT({\NLW_blk00000814_ACOUT<29>_UNCONNECTED , \NLW_blk00000814_ACOUT<28>_UNCONNECTED , \NLW_blk00000814_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<26>_UNCONNECTED , \NLW_blk00000814_ACOUT<25>_UNCONNECTED , \NLW_blk00000814_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<23>_UNCONNECTED , \NLW_blk00000814_ACOUT<22>_UNCONNECTED , \NLW_blk00000814_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<20>_UNCONNECTED , \NLW_blk00000814_ACOUT<19>_UNCONNECTED , \NLW_blk00000814_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<17>_UNCONNECTED , \NLW_blk00000814_ACOUT<16>_UNCONNECTED , \NLW_blk00000814_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<14>_UNCONNECTED , \NLW_blk00000814_ACOUT<13>_UNCONNECTED , \NLW_blk00000814_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<11>_UNCONNECTED , \NLW_blk00000814_ACOUT<10>_UNCONNECTED , \NLW_blk00000814_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<8>_UNCONNECTED , \NLW_blk00000814_ACOUT<7>_UNCONNECTED , \NLW_blk00000814_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<5>_UNCONNECTED , \NLW_blk00000814_ACOUT<4>_UNCONNECTED , \NLW_blk00000814_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<2>_UNCONNECTED , \NLW_blk00000814_ACOUT<1>_UNCONNECTED , \NLW_blk00000814_ACOUT<0>_UNCONNECTED }),
.PCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.ALUMODE({sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.CARRYOUT({\NLW_blk00000814_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000814_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000814_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000814_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.BCOUT({\NLW_blk00000814_BCOUT<17>_UNCONNECTED , \NLW_blk00000814_BCOUT<16>_UNCONNECTED , \NLW_blk00000814_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<14>_UNCONNECTED , \NLW_blk00000814_BCOUT<13>_UNCONNECTED , \NLW_blk00000814_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<11>_UNCONNECTED , \NLW_blk00000814_BCOUT<10>_UNCONNECTED , \NLW_blk00000814_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<8>_UNCONNECTED , \NLW_blk00000814_BCOUT<7>_UNCONNECTED , \NLW_blk00000814_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<5>_UNCONNECTED , \NLW_blk00000814_BCOUT<4>_UNCONNECTED , \NLW_blk00000814_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<2>_UNCONNECTED , \NLW_blk00000814_BCOUT<1>_UNCONNECTED , \NLW_blk00000814_BCOUT<0>_UNCONNECTED }),
.A({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3
, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.PCOUT({\NLW_blk00000814_PCOUT<47>_UNCONNECTED , \NLW_blk00000814_PCOUT<46>_UNCONNECTED , \NLW_blk00000814_PCOUT<45>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<44>_UNCONNECTED , \NLW_blk00000814_PCOUT<43>_UNCONNECTED , \NLW_blk00000814_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<41>_UNCONNECTED , \NLW_blk00000814_PCOUT<40>_UNCONNECTED , \NLW_blk00000814_PCOUT<39>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<38>_UNCONNECTED , \NLW_blk00000814_PCOUT<37>_UNCONNECTED , \NLW_blk00000814_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<35>_UNCONNECTED , \NLW_blk00000814_PCOUT<34>_UNCONNECTED , \NLW_blk00000814_PCOUT<33>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<32>_UNCONNECTED , \NLW_blk00000814_PCOUT<31>_UNCONNECTED , \NLW_blk00000814_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<29>_UNCONNECTED , \NLW_blk00000814_PCOUT<28>_UNCONNECTED , \NLW_blk00000814_PCOUT<27>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<26>_UNCONNECTED , \NLW_blk00000814_PCOUT<25>_UNCONNECTED , \NLW_blk00000814_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<23>_UNCONNECTED , \NLW_blk00000814_PCOUT<22>_UNCONNECTED , \NLW_blk00000814_PCOUT<21>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<20>_UNCONNECTED , \NLW_blk00000814_PCOUT<19>_UNCONNECTED , \NLW_blk00000814_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<17>_UNCONNECTED , \NLW_blk00000814_PCOUT<16>_UNCONNECTED , \NLW_blk00000814_PCOUT<15>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<14>_UNCONNECTED , \NLW_blk00000814_PCOUT<13>_UNCONNECTED , \NLW_blk00000814_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<11>_UNCONNECTED , \NLW_blk00000814_PCOUT<10>_UNCONNECTED , \NLW_blk00000814_PCOUT<9>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<8>_UNCONNECTED , \NLW_blk00000814_PCOUT<7>_UNCONNECTED , \NLW_blk00000814_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<5>_UNCONNECTED , \NLW_blk00000814_PCOUT<4>_UNCONNECTED , \NLW_blk00000814_PCOUT<3>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<2>_UNCONNECTED , \NLW_blk00000814_PCOUT<1>_UNCONNECTED , \NLW_blk00000814_PCOUT<0>_UNCONNECTED }),
.ACIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3})
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* This file is (C) Copyright 2006-2015 Microsoft Corporation and Inria. *)
(** #<style> .doc { font-family: monospace; white-space: pre; } </style># **)
Require Import ssreflect.
(**
This file contains the basic definitions and notations for working with
functions. The definitions provide for:
- Pair projections:
p.1 == first element of a pair
p.2 == second element of a pair
These notations also apply to p : P /\ Q, via an and >-> pair coercion.
- Simplifying functions, beta-reduced by /= and simpl:
#[#fun : T => E#]# == constant function from type T that returns E
#[#fun x => E#]# == unary function
#[#fun x : T => E#]# == unary function with explicit domain type
#[#fun x y => E#]# == binary function
#[#fun x y : T => E#]# == binary function with common domain type
#[#fun (x : T) y => E#]# \
#[#fun (x : xT) (y : yT) => E#]# | == binary function with (some) explicit,
#[#fun x (y : T) => E#]# / independent domain types for each argument
- Partial functions using option type:
oapp f d ox == if ox is Some x returns f x, d otherwise
odflt d ox == if ox is Some x returns x, d otherwise
obind f ox == if ox is Some x returns f x, None otherwise
omap f ox == if ox is Some x returns Some (f x), None otherwise
- Singleton types:
all_equal_to x0 == x0 is the only value in its type, so any such value
can be rewritten to x0.
- A generic wrapper type:
wrapped T == the inductive type with values Wrap x for x : T.
unwrap w == the projection of w : wrapped T on T.
wrap x == the canonical injection of x : T into wrapped T; it is
equivalent to Wrap x, but is declared as a (default)
Canonical Structure, which lets the Coq HO unification
automatically expand x into unwrap (wrap x). The delta
reduction of wrap x to Wrap can be exploited to
introduce controlled nondeterminism in Canonical
Structure inference, as in the implementation of
the mxdirect predicate in matrix.v.
- The empty type:
void == a notation for the Empty_set type of the standard library.
of_void T == the canonical injection void -> T.
- Sigma types:
tag w == the i of w : {i : I & T i}.
tagged w == the T i component of w : {i : I & T i}.
Tagged T x == the {i : I & T i} with component x : T i.
tag2 w == the i of w : {i : I & T i & U i}.
tagged2 w == the T i component of w : {i : I & T i & U i}.
tagged2' w == the U i component of w : {i : I & T i & U i}.
Tagged2 T U x y == the {i : I & T i} with components x : T i and y : U i.
sval u == the x of u : {x : T | P x}.
s2val u == the x of u : {x : T | P x & Q x}.
The properties of sval u, s2val u are given by lemmas svalP, s2valP, and
s2valP'. We provide coercions sigT2 >-> sigT and sig2 >-> sig >-> sigT.
A suite of lemmas (all_sig, ...) let us skolemize sig, sig2, sigT, sigT2
and pair, e.g.,
have /all_sig#[#f fP#]# (x : T): {y : U | P y} by ...
yields an f : T -> U such that fP : forall x, P (f x).
- Identity functions:
id == NOTATION for the explicit identity function fun x => x.
@id T == notation for the explicit identity at type T.
idfun == an expression with a head constant, convertible to id;
idfun x simplifies to x.
@idfun T == the expression above, specialized to type T.
phant_id x y == the function type phantom _ x -> phantom _ y.
*** In addition to their casual use in functional programming, identity
functions are often used to trigger static unification as part of the
construction of dependent Records and Structures. For example, if we need
a structure sT over a type T, we take as arguments T, sT, and a "dummy"
function T -> sort sT:
Definition foo T sT & T -> sort sT := ...
We can avoid specifying sT directly by calling foo (@id T), or specify
the call completely while still ensuring the consistency of T and sT, by
calling @foo T sT idfun. The phant_id type allows us to extend this trick
to non-Type canonical projections. It also allows us to sidestep
dependent type constraints when building explicit records, e.g., given
Record r := R {x; y : T(x)}.
if we need to build an r from a given y0 while inferring some x0, such
that y0 : T(x0), we pose
Definition mk_r .. y .. (x := ...) y' & phant_id y y' := R x y'.
Calling @mk_r .. y0 .. id will cause Coq to use y' := y0, while checking
the dependent type constraint y0 : T(x0).
- Extensional equality for functions and relations (i.e. functions of two
arguments):
f1 =1 f2 == f1 x is equal to f2 x for all x.
f1 =1 f2 :> A == ... and f2 is explicitly typed.
f1 =2 f2 == f1 x y is equal to f2 x y for all x y.
f1 =2 f2 :> A == ... and f2 is explicitly typed.
- Composition for total and partial functions:
f^~ y == function f with second argument specialised to y,
i.e., fun x => f x y
CAVEAT: conditional (non-maximal) implicit arguments
of f are NOT inserted in this context
@^~ x == application at x, i.e., fun f => f x
#[#eta f#]# == the explicit eta-expansion of f, i.e., fun x => f x
CAVEAT: conditional (non-maximal) implicit arguments
of f are NOT inserted in this context.
fun=> v := the constant function fun _ => v.
f1 \o f2 == composition of f1 and f2.
Note: (f1 \o f2) x simplifies to f1 (f2 x).
f1 \; f2 == categorical composition of f1 and f2. This expands to
to f2 \o f1 and (f1 \; f2) x simplifies to f2 (f1 x).
pcomp f1 f2 == composition of partial functions f1 and f2.
- Properties of functions:
injective f <-> f is injective.
cancel f g <-> g is a left inverse of f / f is a right inverse of g.
pcancel f g <-> g is a left inverse of f where g is partial.
ocancel f g <-> g is a left inverse of f where f is partial.
bijective f <-> f is bijective (has a left and right inverse).
involutive f <-> f is involutive.
- Properties for operations.
left_id e op <-> e is a left identity for op (e op x = x).
right_id e op <-> e is a right identity for op (x op e = x).
left_inverse e inv op <-> inv is a left inverse for op wrt identity e,
i.e., (inv x) op x = e.
right_inverse e inv op <-> inv is a right inverse for op wrt identity e
i.e., x op (i x) = e.
self_inverse e op <-> each x is its own op-inverse (x op x = e).
idempotent op <-> op is idempotent for op (x op x = x).
associative op <-> op is associative, i.e.,
x op (y op z) = (x op y) op z.
commutative op <-> op is commutative (x op y = y op x).
left_commutative op <-> op is left commutative, i.e.,
x op (y op z) = y op (x op z).
right_commutative op <-> op is right commutative, i.e.,
(x op y) op z = (x op z) op y.
left_zero z op <-> z is a left zero for op (z op x = z).
right_zero z op <-> z is a right zero for op (x op z = z).
left_distributive op1 op2 <-> op1 distributes over op2 to the left:
(x op2 y) op1 z = (x op1 z) op2 (y op1 z).
right_distributive op1 op2 <-> op distributes over add to the right:
x op1 (y op2 z) = (x op1 z) op2 (x op1 z).
interchange op1 op2 <-> op1 and op2 satisfy an interchange law:
(x op2 y) op1 (z op2 t) = (x op1 z) op2 (y op1 t).
Note that interchange op op is a commutativity property.
left_injective op <-> op is injective in its left argument:
x op y = z op y -> x = z.
right_injective op <-> op is injective in its right argument:
x op y = x op z -> y = z.
left_loop inv op <-> op, inv obey the inverse loop left axiom:
(inv x) op (x op y) = y for all x, y, i.e.,
op (inv x) is always a left inverse of op x
rev_left_loop inv op <-> op, inv obey the inverse loop reverse left
axiom: x op ((inv x) op y) = y, for all x, y.
right_loop inv op <-> op, inv obey the inverse loop right axiom:
(x op y) op (inv y) = x for all x, y.
rev_right_loop inv op <-> op, inv obey the inverse loop reverse right
axiom: (x op (inv y)) op y = x for all x, y.
Note that familiar "cancellation" identities like x + y - y = x or
x - y + y = x are respectively instances of right_loop and rev_right_loop
The corresponding lemmas will use the K and NK/VK suffixes, respectively.
- Morphisms for functions and relations:
{morph f : x / a >-> r} <-> f is a morphism with respect to functions
(fun x => a) and (fun x => r); if r == R#[#x#]#,
this states that f a = R#[#f x#]# for all x.
{morph f : x / a} <-> f is a morphism with respect to the
function expression (fun x => a). This is
shorthand for {morph f : x / a >-> a}; note
that the two instances of a are often
interpreted at different types.
{morph f : x y / a >-> r} <-> f is a morphism with respect to functions
(fun x y => a) and (fun x y => r).
{morph f : x y / a} <-> f is a morphism with respect to the
function expression (fun x y => a).
{homo f : x / a >-> r} <-> f is a homomorphism with respect to the
predicates (fun x => a) and (fun x => r);
if r == R#[#x#]#, this states that a -> R#[#f x#]#
for all x.
{homo f : x / a} <-> f is a homomorphism with respect to the
predicate expression (fun x => a).
{homo f : x y / a >-> r} <-> f is a homomorphism with respect to the
relations (fun x y => a) and (fun x y => r).
{homo f : x y / a} <-> f is a homomorphism with respect to the
relation expression (fun x y => a).
{mono f : x / a >-> r} <-> f is monotone with respect to projectors
(fun x => a) and (fun x => r); if r == R#[#x#]#,
this states that R#[#f x#]# = a for all x.
{mono f : x / a} <-> f is monotone with respect to the projector
expression (fun x => a).
{mono f : x y / a >-> r} <-> f is monotone with respect to relators
(fun x y => a) and (fun x y => r).
{mono f : x y / a} <-> f is monotone with respect to the relator
expression (fun x y => a).
The file also contains some basic lemmas for the above concepts.
Lemmas relative to cancellation laws use some abbreviated suffixes:
K - a cancellation rule like esymK : cancel (@esym T x y) (@esym T y x).
LR - a lemma moving an operation from the left hand side of a relation to
the right hand side, like canLR: cancel g f -> x = g y -> f x = y.
RL - a lemma moving an operation from the right to the left, e.g., canRL.
Beware that the LR and RL orientations refer to an "apply" (back chaining)
usage; when using the same lemmas with "have" or "move" (forward chaining)
the directions will be reversed!. **)
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
(** Parsing / printing declarations. *)
Reserved Notation "p .1" (at level 2, left associativity, format "p .1").
Reserved Notation "p .2" (at level 2, left associativity, format "p .2").
Reserved Notation "f ^~ y" (at level 10, y at level 8, no associativity,
format "f ^~ y").
Reserved Notation "@^~ x" (at level 10, x at level 8, no associativity,
format "@^~ x").
Reserved Notation "[ 'eta' f ]" (at level 0, format "[ 'eta' f ]").
Reserved Notation "'fun' => E" (at level 200, format "'fun' => E").
Reserved Notation "[ 'fun' : T => E ]" (at level 0,
format "'[hv' [ 'fun' : T => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x => E ]" (at level 0,
x ident, format "'[hv' [ 'fun' x => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x : T => E ]" (at level 0,
x ident, format "'[hv' [ 'fun' x : T => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x y => E ]" (at level 0,
x ident, y ident, format "'[hv' [ 'fun' x y => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x y : T => E ]" (at level 0,
x ident, y ident, format "'[hv' [ 'fun' x y : T => '/ ' E ] ']'").
Reserved Notation "[ 'fun' ( x : T ) y => E ]" (at level 0,
x ident, y ident, format "'[hv' [ 'fun' ( x : T ) y => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x ( y : T ) => E ]" (at level 0,
x ident, y ident, format "'[hv' [ 'fun' x ( y : T ) => '/ ' E ] ']'").
Reserved Notation "[ 'fun' ( x : T ) ( y : U ) => E ]" (at level 0,
x ident, y ident, format "[ 'fun' ( x : T ) ( y : U ) => E ]" ).
Reserved Notation "f =1 g" (at level 70, no associativity).
Reserved Notation "f =1 g :> A" (at level 70, g at next level, A at level 90).
Reserved Notation "f =2 g" (at level 70, no associativity).
Reserved Notation "f =2 g :> A" (at level 70, g at next level, A at level 90).
Reserved Notation "f \o g" (at level 50, format "f \o '/ ' g").
Reserved Notation "f \; g" (at level 60, right associativity,
format "f \; '/ ' g").
Reserved Notation "{ 'morph' f : x / a >-> r }" (at level 0, f at level 99,
x ident, format "{ 'morph' f : x / a >-> r }").
Reserved Notation "{ 'morph' f : x / a }" (at level 0, f at level 99,
x ident, format "{ 'morph' f : x / a }").
Reserved Notation "{ 'morph' f : x y / a >-> r }" (at level 0, f at level 99,
x ident, y ident, format "{ 'morph' f : x y / a >-> r }").
Reserved Notation "{ 'morph' f : x y / a }" (at level 0, f at level 99,
x ident, y ident, format "{ 'morph' f : x y / a }").
Reserved Notation "{ 'homo' f : x / a >-> r }" (at level 0, f at level 99,
x ident, format "{ 'homo' f : x / a >-> r }").
Reserved Notation "{ 'homo' f : x / a }" (at level 0, f at level 99,
x ident, format "{ 'homo' f : x / a }").
Reserved Notation "{ 'homo' f : x y / a >-> r }" (at level 0, f at level 99,
x ident, y ident, format "{ 'homo' f : x y / a >-> r }").
Reserved Notation "{ 'homo' f : x y / a }" (at level 0, f at level 99,
x ident, y ident, format "{ 'homo' f : x y / a }").
Reserved Notation "{ 'homo' f : x y /~ a }" (at level 0, f at level 99,
x ident, y ident, format "{ 'homo' f : x y /~ a }").
Reserved Notation "{ 'mono' f : x / a >-> r }" (at level 0, f at level 99,
x ident, format "{ 'mono' f : x / a >-> r }").
Reserved Notation "{ 'mono' f : x / a }" (at level 0, f at level 99,
x ident, format "{ 'mono' f : x / a }").
Reserved Notation "{ 'mono' f : x y / a >-> r }" (at level 0, f at level 99,
x ident, y ident, format "{ 'mono' f : x y / a >-> r }").
Reserved Notation "{ 'mono' f : x y / a }" (at level 0, f at level 99,
x ident, y ident, format "{ 'mono' f : x y / a }").
Reserved Notation "{ 'mono' f : x y /~ a }" (at level 0, f at level 99,
x ident, y ident, format "{ 'mono' f : x y /~ a }").
Reserved Notation "@ 'id' T" (at level 10, T at level 8, format "@ 'id' T").
Reserved Notation "@ 'sval'" (at level 10, format "@ 'sval'").
(**
Syntax for defining auxiliary recursive function.
Usage:
Section FooDefinition.
Variables (g1 : T1) (g2 : T2). (globals)
Fixoint foo_auxiliary (a3 : T3) ... :=
body, using #[#rec e3, ... #]# for recursive calls
where " #[# 'rec' a3 , a4 , ... #]#" := foo_auxiliary.
Definition foo x y .. := #[#rec e1, ... #]#.
+ proofs about foo
End FooDefinition. **)
Reserved Notation "[ 'rec' a ]" (at level 0,
format "[ 'rec' a ]").
Reserved Notation "[ 'rec' a , b ]" (at level 0,
format "[ 'rec' a , b ]").
Reserved Notation "[ 'rec' a , b , c ]" (at level 0,
format "[ 'rec' a , b , c ]").
Reserved Notation "[ 'rec' a , b , c , d ]" (at level 0,
format "[ 'rec' a , b , c , d ]").
Reserved Notation "[ 'rec' a , b , c , d , e ]" (at level 0,
format "[ 'rec' a , b , c , d , e ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f , g ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f , g ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f , g , h ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f , g , h ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f , g , h , i ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f , g , h , i ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f , g , h , i , j ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f , g , h , i , j ]").
Declare Scope pair_scope.
Delimit Scope pair_scope with PAIR.
Open Scope pair_scope.
(** Notations for pair/conjunction projections **)
Notation "p .1" := (fst p) : pair_scope.
Notation "p .2" := (snd p) : pair_scope.
Coercion pair_of_and P Q (PandQ : P /\ Q) := (proj1 PandQ, proj2 PandQ).
Definition all_pair I T U (w : forall i : I, T i * U i) :=
(fun i => (w i).1, fun i => (w i).2).
(**
Complements on the option type constructor, used below to
encode partial functions. **)
Module Option.
Definition apply aT rT (f : aT -> rT) x u := if u is Some y then f y else x.
Definition default T := apply (fun x : T => x).
Definition bind aT rT (f : aT -> option rT) := apply f None.
Definition map aT rT (f : aT -> rT) := bind (fun x => Some (f x)).
End Option.
Notation oapp := Option.apply.
Notation odflt := Option.default.
Notation obind := Option.bind.
Notation omap := Option.map.
Notation some := (@Some _) (only parsing).
(** Shorthand for some basic equality lemmas. **)
Notation erefl := refl_equal.
Notation ecast i T e x := (let: erefl in _ = i := e return T in x).
Definition esym := sym_eq.
Definition nesym := sym_not_eq.
Definition etrans := trans_eq.
Definition congr1 := f_equal.
Definition congr2 := f_equal2.
(** Force at least one implicit when used as a view. **)
Prenex Implicits esym nesym.
(** A predicate for singleton types. **)
Definition all_equal_to T (x0 : T) := forall x, unkeyed x = x0.
Lemma unitE : all_equal_to tt. Proof. by case. Qed.
(** A generic wrapper type **)
#[universes(template)]
Structure wrapped T := Wrap {unwrap : T}.
Canonical wrap T x := @Wrap T x.
Prenex Implicits unwrap wrap Wrap.
Declare Scope fun_scope.
Delimit Scope fun_scope with FUN.
Open Scope fun_scope.
(** Notations for argument transpose **)
Notation "f ^~ y" := (fun x => f x y) : fun_scope.
Notation "@^~ x" := (fun f => f x) : fun_scope.
(**
Definitions and notation for explicit functions with simplification,
i.e., which simpl and /= beta expand (this is complementary to nosimpl). **)
#[universes(template)]
Variant simpl_fun (aT rT : Type) := SimplFun of aT -> rT.
Section SimplFun.
Variables aT rT : Type.
Definition fun_of_simpl (f : simpl_fun aT rT) := fun x => let: SimplFun lam := f in lam x.
End SimplFun.
Coercion fun_of_simpl : simpl_fun >-> Funclass.
Notation "[ 'fun' : T => E ]" := (SimplFun (fun _ : T => E)) : fun_scope.
Notation "[ 'fun' x => E ]" := (SimplFun (fun x => E)) : fun_scope.
Notation "[ 'fun' x y => E ]" := (fun x => [fun y => E]) : fun_scope.
Notation "[ 'fun' x : T => E ]" := (SimplFun (fun x : T => E))
(only parsing) : fun_scope.
Notation "[ 'fun' x y : T => E ]" := (fun x : T => [fun y : T => E])
(only parsing) : fun_scope.
Notation "[ 'fun' ( x : T ) y => E ]" := (fun x : T => [fun y => E])
(only parsing) : fun_scope.
Notation "[ 'fun' x ( y : T ) => E ]" := (fun x => [fun y : T => E])
(only parsing) : fun_scope.
Notation "[ 'fun' ( x : T ) ( y : U ) => E ]" := (fun x : T => [fun y : U => E])
(only parsing) : fun_scope.
(** For delta functions in eqtype.v. **)
Definition SimplFunDelta aT rT (f : aT -> aT -> rT) := [fun z => f z z].
(**
Extensional equality, for unary and binary functions, including syntactic
sugar. **)
Section ExtensionalEquality.
Variables A B C : Type.
Definition eqfun (f g : B -> A) : Prop := forall x, f x = g x.
Definition eqrel (r s : C -> B -> A) : Prop := forall x y, r x y = s x y.
Lemma frefl f : eqfun f f. Proof. by []. Qed.
Lemma fsym f g : eqfun f g -> eqfun g f. Proof. by move=> eq_fg x. Qed.
Lemma ftrans f g h : eqfun f g -> eqfun g h -> eqfun f h.
Proof. by move=> eq_fg eq_gh x; rewrite eq_fg. Qed.
Lemma rrefl r : eqrel r r. Proof. by []. Qed.
End ExtensionalEquality.
Typeclasses Opaque eqfun.
Typeclasses Opaque eqrel.
Hint Resolve frefl rrefl : core.
Notation "f1 =1 f2" := (eqfun f1 f2) : fun_scope.
Notation "f1 =1 f2 :> A" := (f1 =1 (f2 : A)) : fun_scope.
Notation "f1 =2 f2" := (eqrel f1 f2) : fun_scope.
Notation "f1 =2 f2 :> A" := (f1 =2 (f2 : A)) : fun_scope.
Section Composition.
Variables A B C : Type.
Definition comp (f : B -> A) (g : C -> B) x := f (g x).
Definition catcomp g f := comp f g.
Definition pcomp (f : B -> option A) (g : C -> option B) x := obind f (g x).
Lemma eq_comp f f' g g' : f =1 f' -> g =1 g' -> comp f g =1 comp f' g'.
Proof. by move=> eq_ff' eq_gg' x; rewrite /comp eq_gg' eq_ff'. Qed.
End Composition.
Arguments comp {A B C} f g x /.
Arguments catcomp {A B C} g f x /.
Notation "f1 \o f2" := (comp f1 f2) : fun_scope.
Notation "f1 \; f2" := (catcomp f1 f2) : fun_scope.
Notation "[ 'eta' f ]" := (fun x => f x) : fun_scope.
Notation "'fun' => E" := (fun _ => E) : fun_scope.
Notation id := (fun x => x).
Notation "@ 'id' T" := (fun x : T => x) (only parsing) : fun_scope.
Definition idfun T x : T := x.
Arguments idfun {T} x /.
Definition phant_id T1 T2 v1 v2 := phantom T1 v1 -> phantom T2 v2.
(** The empty type. **)
Notation void := Empty_set.
Definition of_void T (x : void) : T := match x with end.
(** Strong sigma types. **)
Section Tag.
Variables (I : Type) (i : I) (T_ U_ : I -> Type).
Definition tag := projT1.
Definition tagged : forall w, T_(tag w) := @projT2 I [eta T_].
Definition Tagged x := @existT I [eta T_] i x.
Definition tag2 (w : @sigT2 I T_ U_) := let: existT2 _ _ i _ _ := w in i.
Definition tagged2 w : T_(tag2 w) := let: existT2 _ _ _ x _ := w in x.
Definition tagged2' w : U_(tag2 w) := let: existT2 _ _ _ _ y := w in y.
Definition Tagged2 x y := @existT2 I [eta T_] [eta U_] i x y.
End Tag.
Arguments Tagged [I i].
Arguments Tagged2 [I i].
Prenex Implicits tag tagged Tagged tag2 tagged2 tagged2' Tagged2.
Coercion tag_of_tag2 I T_ U_ (w : @sigT2 I T_ U_) :=
Tagged (fun i => T_ i * U_ i)%type (tagged2 w, tagged2' w).
Lemma all_tag I T U :
(forall x : I, {y : T x & U x y}) ->
{f : forall x, T x & forall x, U x (f x)}.
Proof. by move=> fP; exists (fun x => tag (fP x)) => x; case: (fP x). Qed.
Lemma all_tag2 I T U V :
(forall i : I, {y : T i & U i y & V i y}) ->
{f : forall i, T i & forall i, U i (f i) & forall i, V i (f i)}.
Proof. by case/all_tag=> f /all_pair[]; exists f. Qed.
(** Refinement types. **)
(** Prenex Implicits and renaming. **)
Notation sval := (@proj1_sig _ _).
Notation "@ 'sval'" := (@proj1_sig) (at level 10, format "@ 'sval'").
Section Sig.
Variables (T : Type) (P Q : T -> Prop).
Lemma svalP (u : sig P) : P (sval u). Proof. by case: u. Qed.
Definition s2val (u : sig2 P Q) := let: exist2 _ _ x _ _ := u in x.
Lemma s2valP u : P (s2val u). Proof. by case: u. Qed.
Lemma s2valP' u : Q (s2val u). Proof. by case: u. Qed.
End Sig.
Prenex Implicits svalP s2val s2valP s2valP'.
Coercion tag_of_sig I P (u : @sig I P) := Tagged P (svalP u).
Coercion sig_of_sig2 I P Q (u : @sig2 I P Q) :=
exist (fun i => P i /\ Q i) (s2val u) (conj (s2valP u) (s2valP' u)).
Lemma all_sig I T P :
(forall x : I, {y : T x | P x y}) ->
{f : forall x, T x | forall x, P x (f x)}.
Proof. by case/all_tag=> f; exists f. Qed.
Lemma all_sig2 I T P Q :
(forall x : I, {y : T x | P x y & Q x y}) ->
{f : forall x, T x | forall x, P x (f x) & forall x, Q x (f x)}.
Proof. by case/all_sig=> f /all_pair[]; exists f. Qed.
Section Morphism.
Variables (aT rT sT : Type) (f : aT -> rT).
(** Morphism property for unary and binary functions **)
Definition morphism_1 aF rF := forall x, f (aF x) = rF (f x).
Definition morphism_2 aOp rOp := forall x y, f (aOp x y) = rOp (f x) (f y).
(** Homomorphism property for unary and binary relations **)
Definition homomorphism_1 (aP rP : _ -> Prop) := forall x, aP x -> rP (f x).
Definition homomorphism_2 (aR rR : _ -> _ -> Prop) :=
forall x y, aR x y -> rR (f x) (f y).
(** Stability property for unary and binary relations **)
Definition monomorphism_1 (aP rP : _ -> sT) := forall x, rP (f x) = aP x.
Definition monomorphism_2 (aR rR : _ -> _ -> sT) :=
forall x y, rR (f x) (f y) = aR x y.
End Morphism.
Notation "{ 'morph' f : x / a >-> r }" :=
(morphism_1 f (fun x => a) (fun x => r)) : type_scope.
Notation "{ 'morph' f : x / a }" :=
(morphism_1 f (fun x => a) (fun x => a)) : type_scope.
Notation "{ 'morph' f : x y / a >-> r }" :=
(morphism_2 f (fun x y => a) (fun x y => r)) : type_scope.
Notation "{ 'morph' f : x y / a }" :=
(morphism_2 f (fun x y => a) (fun x y => a)) : type_scope.
Notation "{ 'homo' f : x / a >-> r }" :=
(homomorphism_1 f (fun x => a) (fun x => r)) : type_scope.
Notation "{ 'homo' f : x / a }" :=
(homomorphism_1 f (fun x => a) (fun x => a)) : type_scope.
Notation "{ 'homo' f : x y / a >-> r }" :=
(homomorphism_2 f (fun x y => a) (fun x y => r)) : type_scope.
Notation "{ 'homo' f : x y / a }" :=
(homomorphism_2 f (fun x y => a) (fun x y => a)) : type_scope.
Notation "{ 'homo' f : x y /~ a }" :=
(homomorphism_2 f (fun y x => a) (fun x y => a)) : type_scope.
Notation "{ 'mono' f : x / a >-> r }" :=
(monomorphism_1 f (fun x => a) (fun x => r)) : type_scope.
Notation "{ 'mono' f : x / a }" :=
(monomorphism_1 f (fun x => a) (fun x => a)) : type_scope.
Notation "{ 'mono' f : x y / a >-> r }" :=
(monomorphism_2 f (fun x y => a) (fun x y => r)) : type_scope.
Notation "{ 'mono' f : x y / a }" :=
(monomorphism_2 f (fun x y => a) (fun x y => a)) : type_scope.
Notation "{ 'mono' f : x y /~ a }" :=
(monomorphism_2 f (fun y x => a) (fun x y => a)) : type_scope.
(**
In an intuitionistic setting, we have two degrees of injectivity. The
weaker one gives only simplification, and the strong one provides a left
inverse (we show in `fintype' that they coincide for finite types).
We also define an intermediate version where the left inverse is only a
partial function. **)
Section Injections.
Variables (rT aT : Type) (f : aT -> rT).
Definition injective := forall x1 x2, f x1 = f x2 -> x1 = x2.
Definition cancel g := forall x, g (f x) = x.
Definition pcancel g := forall x, g (f x) = Some x.
Definition ocancel (g : aT -> option rT) h := forall x, oapp h x (g x) = x.
Lemma can_pcan g : cancel g -> pcancel (fun y => Some (g y)).
Proof. by move=> fK x; congr (Some _). Qed.
Lemma pcan_inj g : pcancel g -> injective.
Proof. by move=> fK x y /(congr1 g); rewrite !fK => [[]]. Qed.
Lemma can_inj g : cancel g -> injective.
Proof. by move/can_pcan; apply: pcan_inj. Qed.
Lemma canLR g x y : cancel g -> x = f y -> g x = y.
Proof. by move=> fK ->. Qed.
Lemma canRL g x y : cancel g -> f x = y -> x = g y.
Proof. by move=> fK <-. Qed.
End Injections.
Lemma Some_inj {T : nonPropType} : injective (@Some T).
Proof. by move=> x y []. Qed.
Lemma of_voidK T : pcancel (of_void T) [fun _ => None].
Proof. by case. Qed.
(** cancellation lemmas for dependent type casts. **)
Lemma esymK T x y : cancel (@esym T x y) (@esym T y x).
Proof. by case: y /. Qed.
Lemma etrans_id T x y (eqxy : x = y :> T) : etrans (erefl x) eqxy = eqxy.
Proof. by case: y / eqxy. Qed.
Section InjectionsTheory.
Variables (A B C : Type) (f g : B -> A) (h : C -> B).
Lemma inj_id : injective (@id A).
Proof. by []. Qed.
Lemma inj_can_sym f' : cancel f f' -> injective f' -> cancel f' f.
Proof. by move=> fK injf' x; apply: injf'. Qed.
Lemma inj_comp : injective f -> injective h -> injective (f \o h).
Proof. by move=> injf injh x y /injf; apply: injh. Qed.
Lemma inj_compr : injective (f \o h) -> injective h.
Proof. by move=> injfh x y /(congr1 f) /injfh. Qed.
Lemma can_comp f' h' : cancel f f' -> cancel h h' -> cancel (f \o h) (h' \o f').
Proof. by move=> fK hK x; rewrite /= fK hK. Qed.
Lemma pcan_pcomp f' h' :
pcancel f f' -> pcancel h h' -> pcancel (f \o h) (pcomp h' f').
Proof. by move=> fK hK x; rewrite /pcomp fK /= hK. Qed.
Lemma eq_inj : injective f -> f =1 g -> injective g.
Proof. by move=> injf eqfg x y; rewrite -2!eqfg; apply: injf. Qed.
Lemma eq_can f' g' : cancel f f' -> f =1 g -> f' =1 g' -> cancel g g'.
Proof. by move=> fK eqfg eqfg' x; rewrite -eqfg -eqfg'. Qed.
Lemma inj_can_eq f' : cancel f f' -> injective f' -> cancel g f' -> f =1 g.
Proof. by move=> fK injf' gK x; apply: injf'; rewrite fK. Qed.
End InjectionsTheory.
Section Bijections.
Variables (A B : Type) (f : B -> A).
Variant bijective : Prop := Bijective g of cancel f g & cancel g f.
Hypothesis bijf : bijective.
Lemma bij_inj : injective f.
Proof. by case: bijf => g fK _; apply: can_inj fK. Qed.
Lemma bij_can_sym f' : cancel f' f <-> cancel f f'.
Proof.
split=> fK; first exact: inj_can_sym fK bij_inj.
by case: bijf => h _ hK x; rewrite -[x]hK fK.
Qed.
Lemma bij_can_eq f' f'' : cancel f f' -> cancel f f'' -> f' =1 f''.
Proof.
by move=> fK fK'; apply: (inj_can_eq _ bij_inj); apply/bij_can_sym.
Qed.
End Bijections.
Section BijectionsTheory.
Variables (A B C : Type) (f : B -> A) (h : C -> B).
Lemma eq_bij : bijective f -> forall g, f =1 g -> bijective g.
Proof. by case=> f' fK f'K g eqfg; exists f'; eapply eq_can; eauto. Qed.
Lemma bij_comp : bijective f -> bijective h -> bijective (f \o h).
Proof.
by move=> [f' fK f'K] [h' hK h'K]; exists (h' \o f'); apply: can_comp; auto.
Qed.
Lemma bij_can_bij : bijective f -> forall f', cancel f f' -> bijective f'.
Proof. by move=> bijf; exists f; first by apply/(bij_can_sym bijf). Qed.
End BijectionsTheory.
Section Involutions.
Variables (A : Type) (f : A -> A).
Definition involutive := cancel f f.
Hypothesis Hf : involutive.
Lemma inv_inj : injective f. Proof. exact: can_inj Hf. Qed.
Lemma inv_bij : bijective f. Proof. by exists f. Qed.
End Involutions.
Section OperationProperties.
Variables S T R : Type.
Section SopTisR.
Implicit Type op : S -> T -> R.
Definition left_inverse e inv op := forall x, op (inv x) x = e.
Definition right_inverse e inv op := forall x, op x (inv x) = e.
Definition left_injective op := forall x, injective (op^~ x).
Definition right_injective op := forall y, injective (op y).
End SopTisR.
Section SopTisS.
Implicit Type op : S -> T -> S.
Definition right_id e op := forall x, op x e = x.
Definition left_zero z op := forall x, op z x = z.
Definition right_commutative op := forall x y z, op (op x y) z = op (op x z) y.
Definition left_distributive op add :=
forall x y z, op (add x y) z = add (op x z) (op y z).
Definition right_loop inv op := forall y, cancel (op^~ y) (op^~ (inv y)).
Definition rev_right_loop inv op := forall y, cancel (op^~ (inv y)) (op^~ y).
End SopTisS.
Section SopTisT.
Implicit Type op : S -> T -> T.
Definition left_id e op := forall x, op e x = x.
Definition right_zero z op := forall x, op x z = z.
Definition left_commutative op := forall x y z, op x (op y z) = op y (op x z).
Definition right_distributive op add :=
forall x y z, op x (add y z) = add (op x y) (op x z).
Definition left_loop inv op := forall x, cancel (op x) (op (inv x)).
Definition rev_left_loop inv op := forall x, cancel (op (inv x)) (op x).
End SopTisT.
Section SopSisT.
Implicit Type op : S -> S -> T.
Definition self_inverse e op := forall x, op x x = e.
Definition commutative op := forall x y, op x y = op y x.
End SopSisT.
Section SopSisS.
Implicit Type op : S -> S -> S.
Definition idempotent op := forall x, op x x = x.
Definition associative op := forall x y z, op x (op y z) = op (op x y) z.
Definition interchange op1 op2 :=
forall x y z t, op1 (op2 x y) (op2 z t) = op2 (op1 x z) (op1 y t).
End SopSisS.
End OperationProperties.
|
module riscv_core_ex (
input clk,
input rstn,
//CT interface
input [31:0] ct_ex_op1_st2,
input [31:0] ct_ex_op2_st2,
//ID interface
input [9:0] id_ex_funct,
input id_ex_mux1_cntl,
input [31:0] id_ex_pc,
input id_ex_mux2_cntl,
input [31:0] id_ex_immed,
//MEM interface
output ex_mem_result
);
localparam FUNCT_NOP_OH = 10'b0000000000;
localparam FUNCT_ADD_OH = 10'b0000000001;
localparam FUNCT_SUB_OH = 10'b0000000010;
localparam FUNCT_OR_OH = 10'b0000000100;
localparam FUNCT_XOR_OH = 10'b0000001000;
localparam FUNCT_AND_OH = 10'b0000010000;
localparam FUNCT_STL_OH = 10'b0000100000;
localparam FUNCT_STLU_OH = 10'b0001000000;
localparam FUNCT_SLL_OH = 10'b0010000000;
localparam FUNCT_SRL_OH = 10'b0100000000;
localparam FUNCT_SRA_OH = 10'b1000000000;
wire [31:0] op1_st1;
wire [31:0] op2_st1;
wire [31:0] op1_st2;
wire [31:0] op2_st2;
wire [31:0] result_nxt;
wire flip_op2_st2;
wire [31:0] neg_op2_st2;
wire [5:0] shft_amnt;
assign op1_st1 = (id_ex_op1_cntl) ? id_ex_pc : ct_ex_op1;
assign op2_st1 = (id_ex_op2_cntl) ? id_ex_immed : ct_ex_op2;
assign op1_st2 = op1_st1;
assign op2_st2 = (flip_op2) ? neg_op2 : op2_st1;
assign flip_op2 == (id_ex_funct == FUNCT_SUB_OH) ? 1'b1 : 1'b0;
assign neg_op2 = (~op2_st1)+1;
assign shft_amnt = op2_st1 & 'h1f;
assign ex_mem_result = result_ff;
always @ (*) begin
case (id_ex_funct)
FUNCT_ADD_OH ,
FUNCT_SUB_OH : result = op1_st2 + op2_st2;
FUNCT_OR_OH : result = op1_st2 | op2_st2;
FUNCT_XOR_OH : result = op1_st2 ^ op2_st2;
FUNCT_AND_OH : result = op1_st2 & op2_st2;
FUNCT_STL_OH : result = ($signed(op1_st2) < $signed(op2_st2)) ? 1'b1 : 1'b0;
FUNCT_STLU_OH: result = (op1_st2 < op2_st2) ? 1'b1 : 1'b0;
FUNCT_SLL_OH : result = op1_st2 << shft_amnt;
FUNCT_SRL_OH : result = op1_st2 >> shft_amnt;
FUNCT_SRA_OH : result = op1_st2 >>> shft_amnt;
default : result = 32'b0;
endcase
end
always @ (posedge clk, negedge rstn) begin
if (~rstn) begin
result_ff <= 0;
end
else begin
result_ff <= result_nxt;
end
end
endmodule
|
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 05/19/2017 11:15:00 AM
// Design Name: CRC Generator - Slave
// Module Name: crcGenerator
// Project Name: SD2017
// Target Devices: Basys3
// Revision: 1.02
// Revision 1.02 - CRC General generator and length
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// CRC Slave : should be used through CRC Master
// Priority Clear > Enable
module crcGenerator
#(parameter LEN = 7)(
input inputBit,
input clk,
input clear,
input enable, // will not activate on clk input
input [LEN:0] generator,
output reg [LEN - 1:0] crc
);
wire invert;
assign invert = inputBit ^ crc[LEN - 1];
integer _i = 0;
always @ (posedge clk) begin
if (clear) begin
crc = 0;
end
else if (enable) begin
for (_i = LEN - 1; _i > 0; _i = _i - 1) begin
crc[_i] = crc[_i - 1] ^ (invert & generator[_i]);
end
crc[0] = invert;
end
end
endmodule
|
/*
Use this to tell sycamore how to populate the Device ROM table
so that users can interact with your slave
META DATA
identification of your device 0 - 65536
DRT_ID: 1
flags (read drt.txt in the slave/device_rom_table directory 1 means
a standard device
DRT_FLAGS: 1
number of registers this should be equal to the nubmer of ???
parameters
DRT_SIZE: 5
USER_PARAMETER: DEFAULT_INTERRUPT_MASK
USER_PARAMETER: DEFAULT_INTERRUPT_EDGE
*/
module wb_gpio#(
parameter DEFAULT_INTERRUPT_MASK = 0,
parameter DEFAULT_INTERRUPT_EDGE = 0
)(
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
output [34:32] gpio_out,
input [31:0] gpio_in
);
localparam GPIO = 32'h00000000;
localparam GPIO_OUTPUT_ENABLE = 32'h00000001;
localparam INTERRUPTS = 32'h00000002;
localparam INTERRUPT_ENABLE = 32'h00000003;
localparam INTERRUPT_EDGE = 32'h00000004;
//gpio registers
reg [31:0] gpio_direction;
wire [31:0] gpio;
//interrupt registers
reg [31:0] interrupts;
reg [31:0] interrupt_mask;
reg [31:0] interrupt_edge;
reg clear_interrupts;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:26:09 04/28/2016
// Design Name:
// Module Name: enemyPosition
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module enemyPosition(
input clk,
input frameClk,
input isEnemyActive,
input wire [7:0] _randomSeed,
input [3:0] uid,
output reg [9:0] enemyPositionX,
output reg [8:0] enemyPositionY
);
parameter top = 20;
parameter bottom = 440;
parameter center = 220;
parameter left = 20;
parameter right = 600;
parameter middle = 300;
parameter north = 2'b00;
parameter south = 2'b01;
parameter west = 2'b10;
parameter east = 2'b11;
reg [1:0] enemyDirectionFrom;
reg [1:0] enemyDirectionTo;
reg recentEnemyActive;
reg [10:0] randomSeed;
initial begin
enemyPositionX = 'd0;
enemyPositionY = 'd0;
enemyDirectionFrom = 2'b00;
enemyDirectionTo = 2'b00;
recentEnemyActive = 1'b0;
randomSeed = 'd0;
end
always @(posedge frameClk) begin
randomSeed = (_randomSeed[6:0] * uid)+uid;
if(isEnemyActive == 1'b1) begin
case(recentEnemyActive)
1'b0: begin
enemyDirectionFrom <= randomSeed[1:0];
enemyDirectionTo <= randomSeed[3:2];
if(enemyDirectionFrom == enemyDirectionTo) begin
enemyDirectionTo <= enemyDirectionFrom + 1;
end
case(enemyDirectionFrom)
north: begin //from north
if (randomSeed[3] == 1'b1) begin
enemyPositionX <= middle + (randomSeed[2:0] * 30);
end else begin
enemyPositionX <= middle - (randomSeed[2:0] * 30);
end
// enemyPositionX <= middle;
enemyPositionY <= top+1;
end
south: begin //from south
if (randomSeed[3] == 1'b1) begin
enemyPositionX <= middle + (randomSeed[2:0] * 30);
end else begin
enemyPositionX <= middle - (randomSeed[2:0] * 30);
end
// enemyPositionX <= middle;
enemyPositionY <= bottom-1;
end
west: begin //from left
enemyPositionX <= left+1;
if (randomSeed[3] == 1'b1) begin
enemyPositionY <= center + (randomSeed[2:0] * 25);
end else begin
enemyPositionY <= center - (randomSeed[2:0] * 25);
end
// enemyPositionY <= center;
end
east: begin //from right
enemyPositionX <= right-1;
if (randomSeed[3] == 1'b1) begin
enemyPositionY <= center + (randomSeed[2:0] * 25);
end else begin
enemyPositionY <= center - (randomSeed[2:0] * 25);
end
// enemyPositionY <= center;
end
endcase
recentEnemyActive <= 1'b1;
end
1'b1: begin
if (enemyPositionX >= left && enemyPositionX <= right && enemyPositionY >= top && enemyPositionY <= bottom) begin
case(enemyDirectionFrom)
north: begin //from north
enemyPositionY <= enemyPositionY + 1;
end
south: begin //from south
enemyPositionY <= enemyPositionY - 1;
end
west: begin //from left
enemyPositionX <= enemyPositionX + 1;
end
east: begin //from right
enemyPositionX <= enemyPositionX - 1;
end
endcase
case(enemyDirectionTo)
north: begin //to north
// if (enemyDirectionFrom != south) begin
enemyPositionY <= enemyPositionY - 1;
// end
end
south: begin //to south
// if (enemyDirectionFrom != north) begin
enemyPositionY <= enemyPositionY + 1;
// end
end
west: begin //to left
// if (enemyDirectionFrom != east) begin
enemyPositionX <= enemyPositionX - 1;
// end
end
east: begin //to right
// if (enemyDirectionFrom != west) begin
enemyPositionX <= enemyPositionX + 1;
// end
end
endcase
end else begin
enemyDirectionFrom <= enemyDirectionTo;
enemyDirectionTo <= randomSeed[3:2];
if(enemyDirectionFrom == enemyDirectionTo) begin
enemyDirectionTo <= enemyDirectionFrom + 1;
end
if (enemyPositionY > top) begin
enemyPositionY <= enemyPositionY - 2;
end else begin
enemyPositionY <= top + 2;
end
if (enemyPositionX > left) begin
enemyPositionX <= enemyPositionX - 2;
end else begin
enemyPositionX <= left + 2;
end
case(enemyDirectionFrom)
north: begin //from north
enemyPositionY <= enemyPositionY + 2;
end
south: begin //from south
enemyPositionY <= enemyPositionY - 2;
end
west: begin //from left
enemyPositionX <= enemyPositionX + 2;
end
east: begin //from right
enemyPositionX <= enemyPositionX - 2;
end
endcase
end
end
endcase
end else begin
enemyPositionX <= 'd0;
enemyPositionY <= 'd0;
enemyDirectionFrom <= 2'b00;
enemyDirectionTo <= 2'b00;
recentEnemyActive <= 1'b0;
end
end
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
(** $Date$ *)
|
/*
* Titor - System - Miscellaneous debounce circuitry
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Debounce
`else
`define INC_Debounce
`timescale 1 ns / 100 ps
// Sean Moore
module Debounce(
lineout,
linein,
reset,
clk
);
parameter TIME = 0;
`include "definition/Definition.v"
output reg lineout;
input linein;
input clk;
input reset;
reg [WORD-1:0] count;
reg lineina;
reg lineinb;
wire toggle;
assign toggle = lineina ^^ lineinb;
always @(posedge clk) begin
if(reset) count <= 0;
else if(!toggle)
if(count!=TIME) count <= count+1;
else count <= count;
else count <= 0;
end
always @(posedge clk) begin
if(reset) lineout <= lineinb;
else if((count==TIME) && !toggle) lineout <= lineinb;
else lineout <= lineout;
end
always @(posedge clk) begin
lineina <= linein;
lineinb <= lineina;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:54:33 12/16/2015
// Design Name:
// Module Name: uart_unload.v
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_unload #(parameter BYTE_WIDTH = 8, WORD_WIDTH = 13) (
input rst,
input clk,
input byte_rdy,
`ifdef TWO_BYTE_DECODE
input [BYTE_WIDTH-1:0] din,
output reg signed [WORD_WIDTH-1:0] dout,
`endif
output reg unload_uart
);
reg byte_rdy_b = 1'b0;
`ifdef TWO_BYTE_DECODE
reg [WORD_WIDTH-2:0] data_tmp = {BYTE_WIDTH-1{1'b0}};
`endif
always @(posedge clk) begin
if (rst) begin
unload_uart <= 1'b0;
byte_rdy_b <= 1'b0;
`ifdef TWO_BYTE_DECODE
data_tmp <= {BYTE_WIDTH-1{1'b0}};
dout <= {WORD_WIDTH{1'b0}};
`endif
end else begin
byte_rdy_b <= byte_rdy;
unload_uart <= (byte_rdy & ~byte_rdy_b) ? 1'b1 : 1'b0;
`ifdef TWO_BYTE_DECODE
if (din[BYTE_WIDTH-1]) data_out <= {din[BYTE_WIDTH-3:0], data_tmp};
else data_tmp <= din[BYTE_WIDTH-2:0];
`endif
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_1_V
`define SKY130_FD_SC_HD__O2BB2A_1_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR4B_BEHAVIORAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_BEHAVIORAL_PP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:53:58 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top design_1_rst_ps7_0_100M_0 -prefix
// design_1_rst_ps7_0_100M_0_ design_1_rst_ps7_0_100M_0_sim_netlist.v
// Design : design_1_rst_ps7_0_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_rst_ps7_0_100M_0_cdc_sync
(lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module design_1_rst_ps7_0_100M_0_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module design_1_rst_ps7_0_100M_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
design_1_rst_ps7_0_100M_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module design_1_rst_ps7_0_100M_0_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
design_1_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
design_1_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
module design_1_rst_ps7_0_100M_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Core;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire bsr;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire pr;
wire slowest_sync_clk;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr),
.Q(bus_struct_reset),
.R(1'b0));
design_1_rst_ps7_0_100M_0_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\PR_OUT_DFF[0].peripheral_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr),
.Q(peripheral_reset),
.R(1'b0));
design_1_rst_ps7_0_100M_0_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
.Core(Core),
.bsr(bsr),
.lpf_int(lpf_int),
.pr(pr),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
mb_reset_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core),
.Q(mb_reset),
.R(1'b0));
endmodule
module design_1_rst_ps7_0_100M_0_sequence_psr
(Core,
bsr,
pr,
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
lpf_int,
slowest_sync_clk);
output Core;
output bsr;
output pr;
output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
wire Core;
wire Core_i_1_n_0;
wire bsr;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1
(.I0(bsr),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1
(.I0(pr),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(Core),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b0))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(Core),
.S(lpf_int));
design_1_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(bsr),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b0))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(bsr),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(Core),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(pr),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b0))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(pr),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
module design_1_rst_ps7_0_100M_0_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__OR3B_PP_BLACKBOX_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_PP_BLACKBOX_V
|
`define SB_DFF_REG reg Q = 0;
// `define SB_DFF_REG reg Q;
// SiliconBlue IO Cells
module SB_IO (
inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output D_IN_0,
output D_IN_1
);
parameter [5:0] PIN_TYPE = 6'b000000;
parameter [0:0] PULLUP = 1'b0;
parameter [0:0] NEG_TRIGGER = 1'b0;
parameter IO_STANDARD = "SB_LVCMOS";
`ifndef BLACKBOX
reg dout, din_0, din_1;
reg din_q_0, din_q_1;
reg dout_q_0, dout_q_1;
reg outena_q;
generate if (!NEG_TRIGGER) begin
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end else begin
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end endgenerate
always @* begin
if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
din_1 = din_q_1;
end
// work around simulation glitches on dout in DDR mode
reg outclk_delayed_1;
reg outclk_delayed_2;
always @* outclk_delayed_1 <= OUTPUT_CLK;
always @* outclk_delayed_2 <= outclk_delayed_1;
always @* begin
if (PIN_TYPE[3])
dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
else
dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
end
assign D_IN_0 = din_0, D_IN_1 = din_1;
generate
if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
endgenerate
`endif
endmodule
module SB_GB_IO (
inout PACKAGE_PIN,
output GLOBAL_BUFFER_OUTPUT,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output D_IN_0,
output D_IN_1
);
parameter [5:0] PIN_TYPE = 6'b000000;
parameter [0:0] PULLUP = 1'b0;
parameter [0:0] NEG_TRIGGER = 1'b0;
parameter IO_STANDARD = "SB_LVCMOS";
assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
SB_IO #(
.PIN_TYPE(PIN_TYPE),
.PULLUP(PULLUP),
.NEG_TRIGGER(NEG_TRIGGER),
.IO_STANDARD(IO_STANDARD)
) IO (
.PACKAGE_PIN(PACKAGE_PIN),
.LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
.CLOCK_ENABLE(CLOCK_ENABLE),
.INPUT_CLK(INPUT_CLK),
.OUTPUT_CLK(OUTPUT_CLK),
.OUTPUT_ENABLE(OUTPUT_ENABLE),
.D_OUT_0(D_OUT_0),
.D_OUT_1(D_OUT_1),
.D_IN_0(D_IN_0),
.D_IN_1(D_IN_1)
);
endmodule
module SB_GB (
input USER_SIGNAL_TO_GLOBAL_BUFFER,
output GLOBAL_BUFFER_OUTPUT
);
assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
endmodule
// SiliconBlue Logic Cells
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
// Positive Edge SiliconBlue FF Cells
module SB_DFF (output Q, input C, D);
`SB_DFF_REG
always @(posedge C)
Q <= D;
endmodule
module SB_DFFE (output Q, input C, E, D);
`SB_DFF_REG
always @(posedge C)
if (E)
Q <= D;
endmodule
module SB_DFFSR (output Q, input C, R, D);
`SB_DFF_REG
always @(posedge C)
if (R)
Q <= 0;
else
Q <= D;
endmodule
module SB_DFFR (output Q, input C, R, D);
`SB_DFF_REG
always @(posedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
endmodule
module SB_DFFSS (output Q, input C, S, D);
`SB_DFF_REG
always @(posedge C)
if (S)
Q <= 1;
else
Q <= D;
endmodule
module SB_DFFS (output Q, input C, S, D);
`SB_DFF_REG
always @(posedge C, posedge S)
if (S)
Q <= 1;
else
Q <= D;
endmodule
module SB_DFFESR (output Q, input C, E, R, D);
`SB_DFF_REG
always @(posedge C)
if (E) begin
if (R)
Q <= 0;
else
Q <= D;
end
endmodule
module SB_DFFER (output Q, input C, E, R, D);
`SB_DFF_REG
always @(posedge C, posedge R)
if (R)
Q <= 0;
else if (E)
Q <= D;
endmodule
module SB_DFFESS (output Q, input C, E, S, D);
`SB_DFF_REG
always @(posedge C)
if (E) begin
if (S)
Q <= 1;
else
Q <= D;
end
endmodule
module SB_DFFES (output Q, input C, E, S, D);
`SB_DFF_REG
always @(posedge C, posedge S)
if (S)
Q <= 1;
else if (E)
Q <= D;
endmodule
// Negative Edge SiliconBlue FF Cells
module SB_DFFN (output Q, input C, D);
`SB_DFF_REG
always @(negedge C)
Q <= D;
endmodule
module SB_DFFNE (output Q, input C, E, D);
`SB_DFF_REG
always @(negedge C)
if (E)
Q <= D;
endmodule
module SB_DFFNSR (output Q, input C, R, D);
`SB_DFF_REG
always @(negedge C)
if (R)
Q <= 0;
else
Q <= D;
endmodule
module SB_DFFNR (output Q, input C, R, D);
`SB_DFF_REG
always @(negedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
endmodule
module SB_DFFNSS (output Q, input C, S, D);
`SB_DFF_REG
always @(negedge C)
if (S)
Q <= 1;
else
Q <= D;
endmodule
module SB_DFFNS (output Q, input C, S, D);
`SB_DFF_REG
always @(negedge C, posedge S)
if (S)
Q <= 1;
else
Q <= D;
endmodule
module SB_DFFNESR (output Q, input C, E, R, D);
`SB_DFF_REG
always @(negedge C)
if (E) begin
if (R)
Q <= 0;
else
Q <= D;
end
endmodule
module SB_DFFNER (output Q, input C, E, R, D);
`SB_DFF_REG
always @(negedge C, posedge R)
if (R)
Q <= 0;
else if (E)
Q <= D;
endmodule
module SB_DFFNESS (output Q, input C, E, S, D);
`SB_DFF_REG
always @(negedge C)
if (E) begin
if (S)
Q <= 1;
else
Q <= D;
end
endmodule
module SB_DFFNES (output Q, input C, E, S, D);
`SB_DFF_REG
always @(negedge C, posedge S)
if (S)
Q <= 1;
else if (E)
Q <= D;
endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
// MODE 0: 256 x 16
// MODE 1: 512 x 8
// MODE 2: 1024 x 4
// MODE 3: 2048 x 2
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
`ifndef BLACKBOX
wire [15:0] WMASK_I;
wire [15:0] RMASK_I;
reg [15:0] RDATA_I;
wire [15:0] WDATA_I;
generate
case (WRITE_MODE)
0: assign WMASK_I = MASK;
1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
endcase
case (READ_MODE)
0: assign RMASK_I = 16'b 0000_0000_0000_0000;
1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
endcase
case (WRITE_MODE)
0: assign WDATA_I = WDATA;
1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
WDATA[11], WDATA[11], WDATA[11], WDATA[11],
WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
endcase
case (READ_MODE)
0: assign RDATA = RDATA_I;
1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
endcase
endgenerate
integer i;
reg [15:0] memory [0:255];
initial begin
for (i=0; i<16; i=i+1) begin
memory[ 0*16 + i] <= INIT_0[16*i +: 16];
memory[ 1*16 + i] <= INIT_1[16*i +: 16];
memory[ 2*16 + i] <= INIT_2[16*i +: 16];
memory[ 3*16 + i] <= INIT_3[16*i +: 16];
memory[ 4*16 + i] <= INIT_4[16*i +: 16];
memory[ 5*16 + i] <= INIT_5[16*i +: 16];
memory[ 6*16 + i] <= INIT_6[16*i +: 16];
memory[ 7*16 + i] <= INIT_7[16*i +: 16];
memory[ 8*16 + i] <= INIT_8[16*i +: 16];
memory[ 9*16 + i] <= INIT_9[16*i +: 16];
memory[10*16 + i] <= INIT_A[16*i +: 16];
memory[11*16 + i] <= INIT_B[16*i +: 16];
memory[12*16 + i] <= INIT_C[16*i +: 16];
memory[13*16 + i] <= INIT_D[16*i +: 16];
memory[14*16 + i] <= INIT_E[16*i +: 16];
memory[15*16 + i] <= INIT_F[16*i +: 16];
end
end
always @(posedge WCLK) begin
if (WE && WCLKE) begin
if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
end
end
always @(posedge RCLK) begin
if (RE && RCLKE) begin
RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
end
end
`endif
endmodule
module SB_RAM40_4KNR (
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (WCLK ),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
endmodule
module SB_RAM40_4KNW (
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F )
) RAM (
.RDATA(RDATA),
.RCLK (RCLK ),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (~WCLKN),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
endmodule
module SB_RAM40_4KNRNW (
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (~WCLKN),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
endmodule
// Packed IceStorm Logic Cells
module ICESTORM_LC (
input I0, I1, I2, I3, CIN, CLK, CEN, SR,
output LO, O, COUT
);
parameter [15:0] LUT_INIT = 0;
parameter [0:0] NEG_CLK = 0;
parameter [0:0] CARRY_ENABLE = 0;
parameter [0:0] DFF_ENABLE = 0;
parameter [0:0] SET_NORESET = 0;
parameter [0:0] ASYNC_SR = 0;
wire COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx;
wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
assign LO = lut_o;
wire polarized_clk;
assign polarized_clk = CLK ^ NEG_CLK;
reg o_reg;
always @(posedge polarized_clk)
if (CEN)
o_reg <= SR ? SET_NORESET : lut_o;
reg o_reg_async;
always @(posedge polarized_clk, posedge SR)
if (SR)
o_reg <= SET_NORESET;
else if (CEN)
o_reg <= lut_o;
assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
endmodule
// SiliconBlue PLL Cells
(* blackbox *)
module SB_PLL40_CORE (
input REFERENCECLK,
output PLLOUTCORE,
output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
(* blackbox *)
module SB_PLL40_PAD (
input PACKAGEPIN,
output PLLOUTCORE,
output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
(* blackbox *)
module SB_PLL40_2_PAD (
input PACKAGEPIN,
output PLLOUTCOREA,
output PLLOUTGLOBALA,
output PLLOUTCOREB,
output PLLOUTGLOBALB,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT_PORTB = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE_PORTA = 1'b0;
parameter ENABLE_ICEGATE_PORTB = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
(* blackbox *)
module SB_PLL40_2F_CORE (
input REFERENCECLK,
output PLLOUTCOREA,
output PLLOUTGLOBALA,
output PLLOUTCOREB,
output PLLOUTGLOBALB,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT_PORTA = "GENCLK";
parameter PLLOUT_SELECT_PORTB = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE_PORTA = 1'b0;
parameter ENABLE_ICEGATE_PORTB = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
(* blackbox *)
module SB_PLL40_2F_PAD (
input PACKAGEPIN,
output PLLOUTCOREA,
output PLLOUTGLOBALA,
output PLLOUTCOREB,
output PLLOUTGLOBALB,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 2'b00;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT_PORTA = "GENCLK";
parameter PLLOUT_SELECT_PORTB = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE_PORTA = 1'b0;
parameter ENABLE_ICEGATE_PORTB = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
// SiliconBlue Device Configuration Cells
(* blackbox, keep *)
module SB_WARMBOOT (
input BOOT,
input S1,
input S0
);
endmodule
// UltraPlus feature cells
(* blackbox *)
module SB_MAC16 (
input CLK,
input CE,
input [15:0] C,
input [15:0] A,
input [15:0] B,
input [15:0] D,
input AHOLD,
input BHOLD,
input CHOLD,
input DHOLD,
input IRSTTOP,
input IRSTBOT,
input ORSTTOP,
input ORSTBOT,
input OLOADTOP,
input OLOADBOT,
input ADDSUBTOP,
input ADDSUBBOT,
input OHOLDTOP,
input OHOLDBOT,
input CI,
input ACCUMCI,
input SIGNEXTIN,
output [31:0] O,
output CO,
output ACCUMCO,
output SIGNEXTOUT
);
parameter NEG_TRIGGER = 1'b0;
parameter C_REG = 1'b0;
parameter A_REG = 1'b0;
parameter B_REG = 1'b0;
parameter D_REG = 1'b0;
parameter TOP_8x8_MULT_REG = 1'b0;
parameter BOT_8x8_MULT_REG = 1'b0;
parameter PIPELINE_16x16_MULT_REG1 = 1'b0;
parameter PIPELINE_16x16_MULT_REG2 = 1'b0;
parameter TOPOUTPUT_SELECT = 2'b00;
parameter TOPADDSUB_LOWERINPUT = 2'b00;
parameter TOPADDSUB_UPPERINPUT = 1'b0;
parameter TOPADDSUB_CARRYSELECT = 2'b00;
parameter BOTOUTPUT_SELECT = 2'b00;
parameter BOTADDSUB_LOWERINPUT = 2'b00;
parameter BOTADDSUB_UPPERINPUT = 1'b0;
parameter BOTADDSUB_CARRYSELECT = 2'b00;
parameter MODE_8x8 = 1'b0;
parameter A_SIGNED = 1'b0;
parameter B_SIGNED = 1'b0;
endmodule
(* blackbox *)
module SB_SPRAM256KA(
input [13:0] ADDRESS,
input [15:0] DATAIN,
input [3:0] MASKWREN,
input WREN,
input CHIPSELECT,
input CLOCK,
input STANDBY,
input SLEEP,
input POWEROFF,
output [15:0] DATAOUT
);
endmodule
(* blackbox *)
module SB_HFOSC(
input CLKHFPU,
input CLKHFEN,
output CLKHF
);
parameter CLKHF_DIV = "0b00";
endmodule
(* blackbox *)
module SB_LFOSC(
input CLKLFPU,
input CLKLFEN,
output CLKLF
);
endmodule
(* blackbox *)
module SB_RGBA_DRV(
input CURREN,
input RGBLEDEN,
input RGB0PWM,
input RGB1PWM,
input RGB2PWM,
output RGB0,
output RGB1,
output RGB2
);
parameter CURRENT_MODE = "0b0";
parameter RGB0_CURRENT = "0b000000";
parameter RGB1_CURRENT = "0b000000";
parameter RGB2_CURRENT = "0b000000";
endmodule
(* blackbox *)
module SB_I2C(
input SBCLKI,
input SBRWI,
input SBSTBI,
input SBADRI7,
input SBADRI6,
input SBADRI5,
input SBADRI4,
input SBADRI3,
input SBADRI2,
input SBADRI1,
input SBADRI0,
input SBDATI7,
input SBDATI6,
input SBDATI5,
input SBDATI4,
input SBDATI3,
input SBDATI2,
input SBDATI1,
input SBDATI0,
input SCLI,
input SDAI,
output SBDATO7,
output SBDATO6,
output SBDATO5,
output SBDATO4,
output SBDATO3,
output SBDATO2,
output SBDATO1,
output SBDATO0,
output SBACKO,
output I2CIRQ,
output I2CWKUP,
output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
output SCLOE,
output SDAO,
output SDAOE
);
parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
parameter BUS_ADDR74 = "0b0001";
endmodule
(* blackbox *)
module SB_SPI (
input SBCLKI,
input SBRWI,
input SBSTBI,
input SBADRI7,
input SBADRI6,
input SBADRI5,
input SBADRI4,
input SBADRI3,
input SBADRI2,
input SBADRI1,
input SBADRI0,
input SBDATI7,
input SBDATI6,
input SBDATI5,
input SBDATI4,
input SBDATI3,
input SBDATI2,
input SBDATI1,
input SBDATI0,
input MI,
input SI,
input SCKI,
input SCSNI,
output SBDATO7,
output SBDATO6,
output SBDATO5,
output SBDATO4,
output SBDATO3,
output SBDATO2,
output SBDATO1,
output SBDATO0,
output SBACKO,
output SPIIRQ,
output SPIWKUP,
output SO,
output SOE,
output MO,
output MOE,
output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
output SCKOE,
output MCSNO3,
output MCSNO2,
output MCSNO1,
output MCSNO0,
output MCSNOE3,
output MCSNOE2,
output MCSNOE1,
output MCSNOE0
);
parameter BUS_ADDR74 = "0b0000";
endmodule
(* blackbox *)
module SB_LEDDA_IP(
input LEDDCS,
input LEDDCLK,
input LEDDDAT7,
input LEDDDAT6,
input LEDDDAT5,
input LEDDDAT4,
input LEDDDAT3,
input LEDDDAT2,
input LEDDDAT1,
input LEDDDAT0,
input LEDDADDR3,
input LEDDADDR2,
input LEDDADDR1,
input LEDDADDR0,
input LEDDDEN,
input LEDDEXE,
input LEDDRST,
output PWMOUT0,
output PWMOUT1,
output PWMOUT2,
output LEDDON
);
endmodule
(* blackbox *)
module SB_FILTER_50NS(
input FILTERIN,
output FILTEROUT
);
endmodule
module SB_IO_I3C (
inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output D_IN_0,
output D_IN_1,
input PU_ENB,
input WEAK_PU_ENB
);
parameter [5:0] PIN_TYPE = 6'b000000;
parameter [0:0] PULLUP = 1'b0;
parameter [0:0] WEAK_PULLUP = 1'b0;
parameter [0:0] NEG_TRIGGER = 1'b0;
parameter IO_STANDARD = "SB_LVCMOS";
`ifndef BLACKBOX
reg dout, din_0, din_1;
reg din_q_0, din_q_1;
reg dout_q_0, dout_q_1;
reg outena_q;
generate if (!NEG_TRIGGER) begin
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end else begin
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end endgenerate
always @* begin
if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
din_1 = din_q_1;
end
// work around simulation glitches on dout in DDR mode
reg outclk_delayed_1;
reg outclk_delayed_2;
always @* outclk_delayed_1 <= OUTPUT_CLK;
always @* outclk_delayed_2 <= outclk_delayed_1;
always @* begin
if (PIN_TYPE[3])
dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
else
dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
end
assign D_IN_0 = din_0, D_IN_1 = din_1;
generate
if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
endgenerate
`endif
endmodule
module SB_IO_OD (
inout PACKAGEPIN,
input LATCHINPUTVALUE,
input CLOCKENABLE,
input INPUTCLK,
input OUTPUTCLK,
input OUTPUTENABLE,
input DOUT1,
input DOUT0,
output DIN1,
output DIN0,
);
parameter [5:0] PIN_TYPE = 6'b000000;
parameter [0:0] NEG_TRIGGER = 1'b0;
`ifndef BLACKBOX
reg dout, din_0, din_1;
reg din_q_0, din_q_1;
reg dout_q_0, dout_q_1;
reg outena_q;
generate if (!NEG_TRIGGER) begin
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end else begin
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end endgenerate
always @* begin
if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
din_1 = din_q_1;
end
// work around simulation glitches on dout in DDR mode
reg outclk_delayed_1;
reg outclk_delayed_2;
always @* outclk_delayed_1 <= OUTPUT_CLK;
always @* outclk_delayed_2 <= outclk_delayed_1;
always @* begin
if (PIN_TYPE[3])
dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
else
dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
end
assign D_IN_0 = din_0, D_IN_1 = din_1;
generate
if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout ? 1'bz : 1'b0;
if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
endgenerate
`endif
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axis_dma_rx (
// adc interface
adc_clk,
adc_rst,
// dma interface
dma_clk,
dma_rst,
dma_start,
dma_stream,
dma_count,
dma_ovf,
dma_unf,
dma_status,
dma_bw,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter PCORE_VERSION = 32'h00050062;
parameter PCORE_ID = 0;
// adc interface
input adc_clk;
output adc_rst;
// dma interface
input dma_clk;
output dma_rst;
output dma_start;
output dma_stream;
output [31:0] dma_count;
input dma_ovf;
input dma_unf;
input dma_status;
input [31:0] dma_bw;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_dma_stream = 'd0;
reg up_dma_start = 'd0;
reg [31:0] up_dma_count = 'd0;
reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0;
reg dma_start_m1 = 'd0;
reg dma_start_m2 = 'd0;
reg dma_start_m3 = 'd0;
reg dma_start = 'd0;
reg dma_stream = 'd0;
reg [31:0] dma_count = 'd0;
reg [ 5:0] dma_xfer_cnt = 'd0;
reg dma_xfer_toggle = 'd0;
reg dma_xfer_ovf = 'd0;
reg dma_xfer_unf = 'd0;
reg dma_acc_ovf = 'd0;
reg dma_acc_unf = 'd0;
reg up_dma_xfer_toggle_m1 = 'd0;
reg up_dma_xfer_toggle_m2 = 'd0;
reg up_dma_xfer_toggle_m3 = 'd0;
reg up_dma_xfer_ovf = 'd0;
reg up_dma_xfer_unf = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_dma_status_m1 = 'd0;
reg up_dma_status = 'd0;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire up_preset_s;
wire up_dma_xfer_toggle_s;
// decode block select
assign up_sel_s = (up_addr[13:8] == 6'h00) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_scratch <= 'd0;
up_resetn <= 'd0;
up_dma_stream <= 'd0;
up_dma_start <= 'd0;
up_dma_count <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h20)) begin
up_dma_stream <= up_wdata[1];
up_dma_start <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h21)) begin
up_dma_count <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ack <= 'd0;
up_rdata <= 'd0;
end else begin
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'd0, up_resetn};
8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start};
8'h21: up_rdata <= up_dma_count;
8'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status};
8'h23: up_rdata <= dma_bw;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// ADC CONTROL
FDPE #(.INIT(1'b1)) i_adc_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (adc_clk),
.Q (adc_rst));
// DMA CONTROL
FDPE #(.INIT(1'b1)) i_dma_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (dma_clk),
.Q (dma_rst));
// dma control transfer
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_start_m1 <= 'd0;
dma_start_m2 <= 'd0;
dma_start_m3 <= 'd0;
end else begin
dma_start_m1 <= up_dma_start;
dma_start_m2 <= dma_start_m1;
dma_start_m3 <= dma_start_m2;
end
dma_start <= dma_start_m2 & ~dma_start_m3;
if ((dma_start_m2 == 1'b1) && (dma_start_m3 == 1'b0)) begin
dma_stream <= up_dma_stream;
dma_count <= up_dma_count;
end
end
// dma status transfer
always @(posedge dma_clk) begin
dma_xfer_cnt <= dma_xfer_cnt + 1'b1;
if (dma_xfer_cnt == 6'd0) begin
dma_xfer_toggle <= ~dma_xfer_toggle;
dma_xfer_ovf <= dma_acc_ovf;
dma_xfer_unf <= dma_acc_unf;
end
if (dma_xfer_cnt == 6'd0) begin
dma_acc_ovf <= dma_ovf;
dma_acc_unf <= dma_unf;
end else begin
dma_acc_ovf <= dma_acc_ovf | dma_ovf;
dma_acc_unf <= dma_acc_unf | dma_unf;
end
end
assign up_dma_xfer_toggle_s = up_dma_xfer_toggle_m2 ^ up_dma_xfer_toggle_m3;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_xfer_toggle_m1 <= 'd0;
up_dma_xfer_toggle_m2 <= 'd0;
up_dma_xfer_toggle_m3 <= 'd0;
up_dma_xfer_ovf <= 'd0;
up_dma_xfer_unf <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
end else begin
up_dma_xfer_toggle_m1 <= dma_xfer_toggle;
up_dma_xfer_toggle_m2 <= up_dma_xfer_toggle_m1;
up_dma_xfer_toggle_m3 <= up_dma_xfer_toggle_m2;
if (up_dma_xfer_toggle_s == 1'b1) begin
up_dma_xfer_ovf <= dma_xfer_ovf;
up_dma_xfer_unf <= dma_xfer_unf;
end
if (up_dma_xfer_ovf == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h22)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[2];
end
if (up_dma_xfer_unf == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h22)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[1];
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_status_m1 <= 'd0;
up_dma_status <= 'd0;
end else begin
up_dma_status_m1 <= dma_status;
up_dma_status <= up_dma_status_m1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_4_V
`define SKY130_FD_SC_HDLL__O211A_4_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211a_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_4_V
|
// soc_system_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module soc_system_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
soc_system_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction MMU top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Instantiation of all IMMU blocks. ////
//// ////
//// To Do: ////
//// - cache inhibit ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Insn MMU
//
module or1200_immu_top(
// Rst and clk
clk, rst,
// CPU i/f
ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
itlb_uxe, itlb_sxe,
// SR Interface
boot_adr_sel_i,
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// QMEM i/f
qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter boot_adr = `OR1200_BOOT_ADR;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// CPU I/F
//
input ic_en;
input immu_en;
input supv;
input [aw-1:0] icpu_adr_i;
input icpu_cycstb_i;
output [aw-1:0] icpu_adr_o;
output [3:0] icpu_tag_o;
output icpu_rty_o;
output icpu_err_o;
//
// SR Interface
//
input boot_adr_sel_i;
//
// SPR access
//
input spr_cs;
input spr_write;
input [aw-1:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// IC I/F
//
input qmemimmu_rty_i;
input qmemimmu_err_i;
input [3:0] qmemimmu_tag_i;
output [aw-1:0] qmemimmu_adr_o;
output qmemimmu_cycstb_o;
output qmemimmu_ci_o;
//
// Internal wires and regs
//
wire itlb_spr_access;
wire [31:`OR1200_IMMU_PS] itlb_ppn;
wire itlb_hit;
output itlb_uxe;
output itlb_sxe;
wire [31:0] itlb_dat_o;
wire itlb_en;
wire itlb_ci;
wire itlb_done;
wire fault;
wire miss;
wire page_cross;
reg [31:0] icpu_adr_default;
reg icpu_adr_select;
reg [31:0] icpu_adr_o;
reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
`ifdef OR1200_NO_IMMU
`else
reg itlb_en_r;
reg dis_spr_access_frst_clk;
reg dis_spr_access_scnd_clk;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-10 v 0
// itlbwYtrX: ppn
// 31-10 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// icpu_adr_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
wire [31:0] icpu_adr_boot = boot_adr;
always @(`OR1200_RST_EVENT rst or posedge clk)
// default value
if (rst == `OR1200_RST_VALUE) begin
// select async. value due to reset state
icpu_adr_default <= 32'h0000_0100;
icpu_adr_select <= 1'b1;
end
// selected value (different from default) is written
// into FF after reset state
else if (icpu_adr_select) begin
// dynamic value can only be assigned to FF out of reset!
icpu_adr_default <= icpu_adr_boot;
// select FF value
icpu_adr_select <= 1'b0;
end
else begin
icpu_adr_default <= icpu_adr_i;
end
// select async. value for boot address after reset - PC jumps to the address
// selected after boot!
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P :
// `OR1200_EXCEPT_EPH0_P), 12'h100} ;
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
if (icpu_adr_select)
// async. value is selected due to reset state
icpu_adr_o = icpu_adr_boot ;
else
// FF value is selected 2nd clock after reset state
icpu_adr_o = icpu_adr_default ;
`else
Unsupported !!!
`endif
//
// Page cross
//
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
//
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
//
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
else
icpu_vpn_r <= icpu_adr_i[31:`OR1200_IMMU_PS];
`ifdef OR1200_NO_IMMU
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemimmu_adr_o = icpu_adr_i;
assign icpu_tag_o = qmemimmu_tag_i;
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
assign icpu_rty_o = qmemimmu_rty_i;
assign icpu_err_o = qmemimmu_err_i;
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// ITLB SPR access
//
// 1200 - 12FF itlbmr w0
// 1200 - 123F itlbmr w0 [63:0]
//
// 1300 - 13FF itlbtr w0
// 1300 - 133F itlbtr w0 [63:0]
//
assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
//
// Disable ITLB SPR access
//
// This flops are used to mask ITLB miss/fault exception
// during first & second clock cycles of accessing ITLB SPR. In
// subsequent clock cycles it is assumed that ITLB SPR
// access was accomplished and that normal instruction fetching
// can proceed.
//
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and
// icpu_rty_o clears it.
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dis_spr_access_frst_clk <= 1'b0;
else if (!icpu_rty_o)
dis_spr_access_frst_clk <= 1'b0;
else if (spr_cs)
dis_spr_access_frst_clk <= 1'b1;
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dis_spr_access_scnd_clk <= 1'b0;
else if (!icpu_rty_o)
dis_spr_access_scnd_clk <= 1'b0;
else if (dis_spr_access_frst_clk)
dis_spr_access_scnd_clk <= 1'b1;
//
// Tags:
//
// OR1200_ITAG_TE - TLB miss Exception
// OR1200_ITAG_PE - Page fault Exception
//
assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
//
// icpu_rty_o
//
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
assign icpu_rty_o = qmemimmu_rty_i;
//
// icpu_err_o
//
assign icpu_err_o = miss | fault | qmemimmu_err_i;
//
// Assert itlb_en_r after one clock cycle and when there is no
// ITLB SPR access
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
itlb_en_r <= 1'b0;
else
itlb_en_r <= itlb_en & ~itlb_spr_access;
//
// ITLB lookup successful
//
assign itlb_done = itlb_en_r & ~page_cross;
//
// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes
// wrong with translation. If IC is disabled, use delayed signals.
//
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
//
// Cache Inhibit
//
// Cache inhibit is not really needed for instruction memory subsystem.
// If we would doq it, we would doq it like this.
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
// However this causes an async combinatorial loop so we stick to
// no cache inhibit.
//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
// Cache inhibit without an async combinatorial loop
assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
//
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
//
//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
reg [31:0] spr_dat_reg;
//
// Output to SPRS unit
//
// spr_dat_o is registered on the 1st clock of spr read
// so itlb can continue with process during execution of mfspr.
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
spr_dat_reg <= 32'h0000_0000;
else if (spr_cs & !dis_spr_access_scnd_clk)
spr_dat_reg <= itlb_dat_o;
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
//
// Page fault exception logic
//
assign fault = itlb_done &
( (!supv & !itlb_uxe) // Execute in user mode not enabled
|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
//
// TLB Miss exception logic
//
assign miss = itlb_done & !itlb_hit;
//
// ITLB Enable
//
assign itlb_en = immu_en & icpu_cycstb_i;
//
// Instantiation of ITLB
//
or1200_immu_tlb or1200_immu_tlb(
// Rst and clk
.clk(clk),
.rst(rst),
// I/F for translation
.tlb_en(itlb_en),
.vaddr(icpu_adr_i),
.hit(itlb_hit),
.ppn(itlb_ppn),
.uxe(itlb_uxe),
.sxe(itlb_sxe),
.ci(itlb_ci),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// SPR access
.spr_cs(itlb_spr_access),
.spr_write(spr_write),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_i),
.spr_dat_o(itlb_dat_o)
);
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DLRTP_PP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_PP_SYMBOL_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: video_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module video_pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 10,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 13,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "65.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "video_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_wave*.jpg FALSE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD, input [31:0] MEMDAT, output [7:0] MEMADD, output MFA,READ_WRITE,WORD_BYTE);
wire[31:0] IR;
wire IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode;
wire [3:0] CU;
reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;
wire [3:0] SRIN, _SRIN,SROUT;
wire SR29_OUT,S;
wire[31:0] _B;
//ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output[3:0] CU, input MFC, Reset,Clk);
ControlUnit cu(IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SROUT);
always@(IR or CU)
begin
RSLCT = {CU,IR[15:8],IR[3:0], IR[19:16]};
end
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);
//assign S = IR[20]&SRENABLED;
assign _SRIN = {SROUT[3],SR29_OUT,SROUT[1],SROUT[0]};
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(Rn,_B, opcode, _SRIN, Out,SRIN,IR[20],ALUSTORE);
//BarrelShifter(input [31] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
BarrelShifter bs(Rs,Rm,IR,SROUT[3],SR29_OUT,_B);
//IR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register IRR( .IN(Out),
.Clk(Clk),
.Reset(Reset),
.Load(IRLOAD),
.OUT(IR));
//MBR
//Register2Buff(inout [31:0] IN,IN2,input Clk, Reset,Load,Load2,Store,Store2);
Register2Buff register(
.IN(Out),
.IN2(MEMDAT),
.Clk(Clk),
.Reset(Reset),
.Load(MBRLOAD),
.Load2(MEMLOAD),
.Store(MBRSTORE),
.Store2(MEMSTORE));
//MAR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register MAR( .IN(Out),
.Clk(Clk),
.Reset(Reset),
.Load(MARLOAD),
.OUT(MEMADD));
//SR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register SR( .IN(SRIN),
.Clk(Clk),
.Reset(Reset),
.Load(1),
.OUT(SROUT));
endmodule
//iverilog ARM_ALU.v BarrelShifter.v Buffer32_32.v controlunit2.v Decoder4x16.v Multiplexer2x1_32b.v Register.v Register2.v RegisterFile.v Register2Buff.v ARM_CU_ALU.v
|
// file: clk_wiz_v3_3_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_wiz_v3_3_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
clk_wiz_v3_3 clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:52:31 06/18/2014
// Design Name:
// Module Name: counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counter(
input CP,
input CLR_,
input M,
input [7:0] RS,
input LD_,
output reg [7:0] Q,
output QCC_
);
reg TEMP;
initial begin
Q = 8'b00000000;
end
always @(posedge CP)
begin
TEMP = ((~Q[0] & ~Q[1] & ~Q[2] & ~Q[3] & ~Q[4] & ~Q[5] & ~Q[6] & ~Q[7] & ~M) | (Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5] & Q[6] & Q[7] & M)) & CLR_ & LD_;
end
always @(posedge CP or negedge CLR_ or negedge LD_)
begin
if (CP == 1'b1)
begin
if (M == 1'b1)
begin
Q = Q+1'b1;
end
else
begin
Q = Q-1'b1;
end
end
if (CLR_ == 1'b0)
begin
Q = 8'b00000000;
end
if (LD_ == 1'b0)
begin
Q = RS;
end
end
assign QCC_ = TEMP & CP;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05:04:29 04/14/2015
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(clk_50MHz, vs_vga, hs_vga, RED, GREEN, BLUE, SWITCH, BUTTON);
input [3:0] SWITCH;
input [3:0] BUTTON;
input clk_50MHz;
output [2:0] RED;
output [2:0] GREEN;
output [1:0] BLUE;
output vs_vga;
output hs_vga;
wire [9:0] CurrentX;
wire [8:0] CurrentY;
wire [7:0] mapData;
wire clk_vga;
reg [15:0] counter = 0;
reg turn = 0;
//
reg [9:0] playerPosX = 320;
reg [8:0] playerPosY = 380;
reg [7:0] playerColor;
reg [3:0] mapX = 3;
reg [3:0] mapY = 5;
//
reg [1:0] dragState = 0;
reg [9:0] grundleX = 160;
reg [8:0] grundleY = 240;
//Starting Map Locations
reg [3:0] grundleMapX = 1;
reg [3:0] grundleMapY = 2;
//
reg itemGet = 0;
reg [9:0] swordX = 560;
reg [8:0] swordY = 240;
parameter swordMapX = 1;
parameter swordMapY = 4;
//
reg [7:0] color = 0;
reg collision = 0;
vga_driver vga(.clk_50MHz(clk_50MHz),
.vs_vga(vs_vga),
.hs_vga(hs_vga),
.RED(RED),
.GREEN(GREEN),
.BLUE(BLUE),
.CURX(CurrentX),
.CURY(CurrentY),
.CLK_DATA(clk_vga),
.COLOR(color),
.RESET(SWITCH[3])
);
map_generator map(.clk_vga(clk_vga),
.CurrentX(CurrentX),
.CurrentY(CurrentY),
.reset(SWITCH[3]),
.mapData(mapData),
.playerColor(playerColor),
.mapX(mapX),
.mapY(mapY)
);
always @(negedge clk_vga)begin
//Slows the clock down by 16 ticks.
//This is the game progression speed
if(counter < 16'HFFFF)
counter <= counter +1;
else begin
//challiceColor[7:0] <= challiceColor[7:0] ^ CurrentX[7:0];
counter <= 0;
turn = ~turn;
end
end
//Player
//The player, along with all dynamic objects, have their
//datapath in the top module because they are drawn with respect to a point
//that's being manipulated and it's better to reference the register bank in the same module
//it's being controlled in to prevent data corruption
always @(posedge turn) begin
//Movement
//Progress forward until a wall is hit
//Pushes back once collision is detected
if(~(dragState == 1))begin
if(BUTTON[0] && (playerPosX < 624)) begin
if(collision)begin
playerPosX <= playerPosX - 7;
end
else begin
playerPosX <= playerPosX + 1;
end
end
if (BUTTON[1] && (playerPosY < 470)) begin
if(collision) begin
playerPosY <= playerPosY - 7;
end
else begin
playerPosY <= playerPosY + 1;
end
end
if(BUTTON[2] && ~(playerPosY <= 10)) begin
if(collision) begin
playerPosY <= playerPosY + 7;
end
else begin
playerPosY <= playerPosY - 1;
end
end
if(BUTTON[3] && ~(playerPosX <= 16)) begin
if(collision) begin
playerPosX <= playerPosX + 7;
end
else begin
playerPosX <= playerPosX - 1;
end
end
end
//Map Transition
//mapX and mapY are stored as seperate values to create a 'grid'
if(~(playerPosX < 624) && ~(mapX == 8)) begin
//From SCenter -> NCenter
if(mapX == 1 && mapY == 6) begin
mapX <= 1;
mapY <= 4;
end
//ECenter -> Center
else if(mapX == 2 && mapY == 5) begin
mapX <= 1;
mapY <= 5;
end
//SW -> SCenter
else if(mapX == 2 && mapY == 4) begin
mapX <= 1;
mapY <= 6;
end
//Normal Progression
else begin
mapX <= mapX + 1;
end
playerPosX <= 20;
end
else if(~(playerPosY < 470) && ~(mapY == 8)) begin
playerPosY <= 14;
mapY <= mapY + 1;
end
else if(playerPosY <= 10 && ~(mapY == 0)) begin
playerPosY <= 466;
mapY <= mapY - 1;
end
else if(playerPosX <= 16 && ~(mapX == 0)) begin
//SCenter -> SW
if(mapX == 1 && mapY == 6) begin
mapX <= 2;
mapY <= 4;
end
//Center -> ECenter
else if(mapX == 1 && mapY == 5) begin
mapX <= 2;
mapY <= 5;
end
//NCenter -> SCenter
else if(mapX == 1 && mapY == 4) begin
mapX <= 1;
mapY <= 6;
end
//normal transition
else begin
mapX <= mapX - 1;
end
playerPosX <= 619;
end
//Color for specific maps
if(mapX == 3 && mapY <= 5) begin
if(itemGet == 1 && dragState == 2)begin
playerColor[3:0] <= playerPosX[3:0];
playerColor[7:4] <= playerPosY[7:4];
end
else
playerColor[7:0] <= 8'b11111100;
end
//black key room
else if(mapX == 1) begin
//Challice Room
if(mapY == 2)
playerColor[7:0] <= 8'b10000111;
//Black Castle
else if(mapY == 3)
playerColor[7:0] <= 8'b00000000;
//Maze
else
playerColor[7:0] <= 8'b00100111;
end
//Maze
else if(mapX == 2 && mapY < 6)
playerColor[7:0] <= 8'b00100111;
//Left hallway
else if(mapX == 2 && mapY == 6)
playerColor[7:0] <= 8'b01111000;
//Middle hallway
else if(mapX == 3 && mapY == 6)
playerColor[7:0] <= 8'b00011100;
//Color not found
else
playerColor[7:0] <= 8'b11111111;
//Reset
if(SWITCH[3]) begin
playerPosX <= 320;
playerPosY <= 380;
mapX <= 3;
mapY <= 5;
end
end
//Dragon
always @(posedge turn) begin
if(mapX == grundleMapX && mapY == grundleMapY && dragState == 0) begin
if(playerPosX > grundleX)
grundleX <= grundleX + 1;
if(playerPosY > grundleY)
grundleY <= grundleY + 1;
if(playerPosX < grundleX)
grundleX <= grundleX - 1;
if(playerPosY < grundleY)
grundleY <= grundleY - 1;
if(playerPosX == grundleX && playerPosY == grundleY)
if(itemGet == 1)
dragState <= 2;
else
dragState <= 1;
else
dragState <= 0;
end
if(SWITCH[3]) begin
dragState <= 0;
end
end
//Items
always @(posedge turn)begin
if(mapX == swordMapX && mapY == swordMapY) begin
if((playerPosX > swordX -28 && playerPosX < swordX -24) && (playerPosY > swordY -4 && playerPosY < swordY +8))begin
itemGet <= 1;
end
end
if(itemGet == 1) begin
swordX <= playerPosX +32;
swordY <= playerPosY;
end
if(SWITCH[3]) begin
itemGet <= 0;
swordX <= 560;
swordY <= 240;
end
/*
if(mapX == challiceMapX && mapY == challiceMapY) begin
if((playerPosX > challiceX -28 && playerPosX < challiceX +4) && (playerPosY > challiceY && playerPosY < challiceY +36))begin
itemGet <= 2'b11;
end
end
if(itemGet == 2'b11) begin
challiceX <= playerPosX +32;
challiceY <= playerPosY;
end
*/
end
//Render loop
//Draws the dynamic objects within the world
//It overwrites the mapData with current dynamic object
always @(posedge clk_vga) begin
//Draws Grundle advancing
if((mapX == grundleMapX && mapY == grundleMapY && dragState == 0)
&& (
(((CurrentX >= grundleX -12) && (CurrentX < grundleX -8)) && (
((CurrentY >= grundleY) && (CurrentY <= grundleY+8)) ||
((CurrentY >= grundleY + 32) && (CurrentY <= grundleY + 52)) ||
((CurrentY >= grundleY + 60) && (CurrentY <= grundleY + 68))
))
|| (((CurrentX >= grundleX -8) && (CurrentX < grundleX -4)) && (
((CurrentY >= grundleY) && (CurrentY <= grundleY+8)) ||
((CurrentY >= grundleY +28) && (CurrentY <= grundleY +52)) ||
((CurrentY >= grundleY +64) && (CurrentY <= grundleY +68))
))
|| (((CurrentX >= grundleX -4) && (CurrentX < grundleX)) && (
((CurrentY >= grundleY) && (CurrentY <= grundleY+8)) ||
((CurrentY >= grundleY +24) && (CurrentY <= grundleY +36)) ||
((CurrentY >= grundleY +48) && (CurrentY <= grundleY +56)) ||
((CurrentY >= grundleY +64) && (CurrentY <= grundleY +72))
))
|| (((CurrentX >= grundleX) && (CurrentX < grundleX +4)) && (
((CurrentY >= grundleY) && (CurrentY <= grundleY+8)) ||
((CurrentY >= grundleY +20) && (CurrentY <= grundleY +32)) ||
((CurrentY >= grundleY +48) && (CurrentY <= grundleY +56)) ||
((CurrentY >= grundleY +68) && (CurrentY <= grundleY +72))
))
|| (((CurrentX >= grundleX +4) && (CurrentX < grundleX +8)) && (
((CurrentY >= grundleY -4) && (CurrentY <= grundleY)) ||
((CurrentY >= grundleY +4) && (CurrentY <= grundleY +12)) ||
((CurrentY >= grundleY +20) && (CurrentY <= grundleY +32)) ||
((CurrentY >= grundleY +48) && (CurrentY <= grundleY +64)) ||
((CurrentY >= grundleY +68) && (CurrentY <= grundleY +72))
))
|| (((CurrentX >= grundleX +8) && (CurrentX < grundleX +12)) && (
((CurrentY >= grundleY -8) && (CurrentY <= grundleY)) ||
((CurrentY >= grundleY +4) && (CurrentY <= grundleY +32)) ||
((CurrentY >= grundleY +44) && (CurrentY <= grundleY +56)) ||
((CurrentY >= grundleY +60) && (CurrentY <= grundleY +64)) ||
((CurrentY >= grundleY +68) && (CurrentY <= grundleY +72))
))
|| (((CurrentX >= grundleX +12) && (CurrentX < grundleX +16)) && (
((CurrentY >= grundleY -8) && (CurrentY <= grundleY +12)) ||
((CurrentY >= grundleY +20) && (CurrentY <= grundleY +52)) ||
((CurrentY >= grundleY +60) && (CurrentY <= grundleY +72))
))
|| (((CurrentX >= grundleX +16) && (CurrentX < grundleX +20)) && (
((CurrentY >= grundleY -4) && (CurrentY <= grundleY +4)) ||
((CurrentY >= grundleY +24) && (CurrentY <= grundleY +52))
))
)
) begin
color[7:0] <= 8'b00011100;
end
//Draws grundle eating
else if((mapX == grundleMapX && mapY == grundleMapY && dragState == 1)
&& (
(((CurrentX >= grundleX -12) && (CurrentX < grundleX -8)) && (
((CurrentY >= grundleY -16) && (CurrentY <= grundleY -12)) ||
((CurrentY >= grundleY +20) && (CurrentY <= grundleY +24)) ||
((CurrentY >= grundleY +60) && (CurrentY <= grundleY +72))
))
|| (((CurrentX >= grundleX -8) && (CurrentX < grundleX -4)) && (
((CurrentY >= grundleY -12) && (CurrentY <= grundleY -8)) ||
((CurrentY >= grundleY +16) && (CurrentY <= grundleY +20)) ||
((CurrentY >= grundleY +32) && (CurrentY <= grundleY +48)) ||
((CurrentY >= grundleY +60) && (CurrentY <= grundleY +64)) ||
((CurrentY >= grundleY +68) && (CurrentY <= grundleY +72))
))
|| (((CurrentX >= grundleX -4) && (CurrentX < grundleX)) && (
((CurrentY >= grundleY -8) && (CurrentY <= grundleY -4)) ||
((CurrentY >= grundleY +12) && (CurrentY <= grundleY +16)) ||
((CurrentY >= grundleY +28) && (CurrentY <= grundleY +52)) ||
((CurrentY >= grundleY +60) && (CurrentY <= grundleY +64)) ||
((CurrentY >= grundleY +68) && (CurrentY <= grundleY +72))
))
|| (((CurrentX >= grundleX) && (CurrentX < grundleX +4)) && (
((CurrentY >= grundleY -4) && (CurrentY <= grundleY)) ||
((CurrentY >= grundleY +8) && (CurrentY <= grundleY +12)) ||
((CurrentY >= grundleY +24) && (CurrentY <= grundleY +56)) ||
((CurrentY >= grundleY +60) && (CurrentY <= grundleY +64))
))
|| (((CurrentX >= grundleX +4) && (CurrentX < grundleX +8)) && (
((CurrentY >= grundleY -4) && (CurrentY <= grundleY +12)) ||
((CurrentY >= grundleY +20) && (CurrentY <= grundleY +64))
))
|| (((CurrentX >= grundleX +8) && (CurrentX < grundleX +12)) && (
((CurrentY >= grundleY -8) && (CurrentY <= grundleY)) ||
((CurrentY >= grundleY +4) && (CurrentY <= grundleY +56))
))
|| (((CurrentX >= grundleX +12) && (CurrentX < grundleX +16)) && (
((CurrentY >= grundleY -8) && (CurrentY <= grundleY +12)) ||
((CurrentY >= grundleY +20) && (CurrentY <= grundleY +52))
))
|| (((CurrentX >= grundleX +16) && (CurrentX < grundleX +20)) && (
((CurrentY >= grundleY -4) && (CurrentY <= grundleY +4)) ||
((CurrentY >= grundleY +28) && (CurrentY <= grundleY +48))
))
)
) begin
color[7:0] <= 8'b00011100;
end
//Grundle Slain
else if((mapX == grundleMapX && mapY == grundleMapY && dragState == 2)
&& (
(((CurrentX >= grundleX -12) && (CurrentX < grundleX -8)) && (
((CurrentY >= grundleY +16) && (CurrentY <= grundleY +36))
))
|| (((CurrentX >= grundleX -8) && (CurrentX < grundleX -4)) && (
((CurrentY >= grundleY +12) && (CurrentY <= grundleY +20)) ||
((CurrentY >= grundleY +24) && (CurrentY <= grundleY +44)) ||
((CurrentY >= grundleY +48) && (CurrentY <= grundleY +60))
))
|| (((CurrentX >= grundleX -4) && (CurrentX < grundleX)) && (
((CurrentY >= grundleY +12) && (CurrentY <= grundleY +16)) ||
((CurrentY >= grundleY +24) && (CurrentY <= grundleY +52)) ||
((CurrentY >= grundleY +56) && (CurrentY <= grundleY +60))
))
|| (((CurrentX >= grundleX) && (CurrentX < grundleX +4)) && (
((CurrentY >= grundleY +8) && (CurrentY <= grundleY +16)) ||
((CurrentY >= grundleY +24) && (CurrentY <= grundleY +44)) ||
((CurrentY >= grundleY +56) && (CurrentY <= grundleY +60))
))
|| (((CurrentX >= grundleX +4) && (CurrentX < grundleX +8)) && (
((CurrentY >= grundleY -8) && (CurrentY <= grundleY +20)) ||
((CurrentY >= grundleY +24) && (CurrentY <= grundleY +44)) ||
((CurrentY >= grundleY +48) && (CurrentY <= grundleY +52)) ||
((CurrentY >= grundleY +56) && (CurrentY <= grundleY +60))
))
|| (((CurrentX >= grundleX +8) && (CurrentX < grundleX +12)) && (
((CurrentY >= grundleY -8) && (CurrentY <= grundleY +8)) ||
((CurrentY >= grundleY +12) && (CurrentY <= grundleY +20)) ||
((CurrentY >= grundleY +24) && (CurrentY <= grundleY +40)) ||
((CurrentY >= grundleY +48) && (CurrentY <= grundleY +52)) ||
((CurrentY >= grundleY +56) && (CurrentY <= grundleY +60))
))
|| (((CurrentX >= grundleX +12) && (CurrentX < grundleX +16)) && (
((CurrentY >= grundleY +4) && (CurrentY <= grundleY +20)) ||
((CurrentY >= grundleY +28) && (CurrentY <= grundleY +40)) ||
((CurrentY >= grundleY +48) && (CurrentY <= grundleY +60))
))
|| (((CurrentX >= grundleX +16) && (CurrentX < grundleX +20)) && (
((CurrentY >= grundleY +8) && (CurrentY <= grundleY +16))
))
)
) begin
color[7:0] <= 8'b00011100;
end
//Challice
else if((dragState == 2) && (
(((CurrentX >= swordX) && (CurrentX < swordX +4)) && (
((CurrentY >= swordY) && (CurrentY <= swordY +12))
))
|| (((CurrentX >= swordX +4) && (CurrentX < swordX +8)) && (
((CurrentY >= swordY +8) && (CurrentY <= swordY +20)) ||
((CurrentY >= swordY +32) && (CurrentY <= swordY +36))
))
|| (((CurrentX >= swordX +8) && (CurrentX < swordX +12)) && (
((CurrentY >= swordY +12) && (CurrentY <= swordY +24)) ||
((CurrentY >= swordY +32) && (CurrentY <= swordY +36))
))
|| (((CurrentX >= swordX +12) && (CurrentX < swordX +16)) && (
((CurrentY >= swordY +12) && (CurrentY <= swordY +36))
))
|| (((CurrentX >= swordX +16) && (CurrentX < swordX +20)) && (
((CurrentY >= swordY +12) && (CurrentY <= swordY +36))
))
|| (((CurrentX >= swordX +20) && (CurrentX < swordX +24)) && (
((CurrentY >= swordY +12) && (CurrentY <= swordY +24)) ||
((CurrentY >= swordY +32) && (CurrentY <= swordY +36))
))
|| (((CurrentX >= swordX +24) && (CurrentX < swordX +28)) && (
((CurrentY >= swordY +8) && (CurrentY <= swordY +20)) ||
((CurrentY >= swordY +32) && (CurrentY <= swordY +36))
))
|| (((CurrentX >= swordX +28) && (CurrentX < swordX +32)) && (
((CurrentY >= swordY) && (CurrentY <= swordY +12))
))
)
) begin
color[3:0] <= playerPosX[3:0];
color[7:4] <= playerPosY[7:4];
end
else if((((mapX == swordMapX && mapY == swordMapY) || (itemGet == 1)) && ~(dragState == 2)) && (
(((CurrentY >= swordY -8) && (CurrentY < swordY -4)) && (
((CurrentX >= swordX -20) && (CurrentX <= swordX -16))
))
|| (((CurrentY >= swordY -4) && (CurrentY < swordY)) && (
((CurrentX >= swordX -24) && (CurrentX <= swordX -20))
))
|| (((CurrentY >= swordY) && (CurrentY < swordY +4)) && (
((CurrentX >= swordX -28) && (CurrentX <= swordX))
))
|| (((CurrentY >= swordY +4) && (CurrentY < swordY +8)) && (
((CurrentX >= swordX -24) && (CurrentX <= swordX -20))
))
|| (((CurrentY >= swordY +8) && (CurrentY < swordY +12)) && (
((CurrentX >= swordX -20) && (CurrentX <= swordX -16))
))
)
)
color[7:0] <= 8'b11111100;
//Draws the player
else if((CurrentY < playerPosY+9) && (CurrentX < playerPosX+9) && ~(CurrentY < playerPosY-9) && ~(CurrentX < playerPosX-9))begin
color[7:0] <= playerColor[7:0];
//Collision is determined by color rather than hitboxes for memory purposes
if(mapData[7:0] == playerColor[7:0] && ~(mapX == 1 && mapY == 3 && CurrentX > 256 && CurrentX < 384)) begin
collision <= 1;
end
else begin
collision <= 0;
end
end
//Finally draws the map
else
color[7:0] <= mapData;
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_ctlif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
output reg irq,
output reg start,
input busy,
/* Address generator interface */
output reg [28:0] dma_base,
output reg [6:0] hmesh_last,
output reg [6:0] vmesh_last,
/* Register file interface */
output [6:0] cr_addr,
input [31:0] cr_di,
output [31:0] cr_do,
output cr_w_en,
/* Program memory interface */
output reg [1:0] cp_page,
output [8:0] cp_offset,
input [31:0] cp_di,
output [31:0] cp_do,
output cp_w_en,
/* Diagnostic registers */
input vnext,
input err_collision,
input err_stray,
input [10:0] pc,
input [31:0] wbm_adr_o,
input wbm_ack_i
);
reg [31:0] last_dma;
always @(posedge sys_clk)
if(wbm_ack_i)
last_dma <= wbm_adr_o;
reg old_busy;
always @(posedge sys_clk) begin
if(sys_rst)
old_busy <= 1'b0;
else
old_busy <= busy;
end
reg [13:0] vertex_counter;
reg [10:0] collision_counter;
reg [10:0] stray_counter;
wire csr_selected = csr_a[13:10] == csr_addr;
reg [31:0] csr_do_r;
reg csr_do_cont;
reg csr_do_regf;
reg csr_do_prog;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do_r <= 32'd0;
csr_do_cont <= 1'b0;
csr_do_regf <= 1'b0;
csr_do_prog <= 1'b0;
irq <= 1'b0;
start <= 1'b0;
dma_base <= 29'd0;
hmesh_last <= 7'd0;
vmesh_last <= 7'd0;
cp_page <= 2'd0;
vertex_counter <= 14'd0;
collision_counter <= 11'd0;
stray_counter <= 11'd0;
end else begin
irq <= old_busy & ~busy;
if(vnext) vertex_counter <= vertex_counter + 14'd1;
if(err_collision) collision_counter <= collision_counter + 11'd1;
if(err_stray) stray_counter <= stray_counter + 11'd1;
csr_do_cont <= 1'b0;
csr_do_prog <= 1'b0;
csr_do_regf <= 1'b0;
start <= 1'b0;
/* Read control registers */
case(csr_a[3:0])
4'b0000: csr_do_r <= busy;
4'b0001: csr_do_r <= {dma_base, 3'b000};
4'b0010: csr_do_r <= hmesh_last;
4'b0011: csr_do_r <= vmesh_last;
4'b0100: csr_do_r <= cp_page;
4'b0101: csr_do_r <= vertex_counter;
4'b0110: csr_do_r <= collision_counter;
4'b0111: csr_do_r <= stray_counter;
4'b1000: csr_do_r <= last_dma;
4'b1001: csr_do_r <= pc;
default: csr_do_r <= 32'bx;
endcase
if(csr_selected) begin
/* Generate enables for the one-hot mux on csr_do */
csr_do_cont <= ~csr_a[8] & ~csr_a[9];
csr_do_regf <= csr_a[8];
csr_do_prog <= csr_a[9];
/* Write control registers */
if(
csr_we /* if this is a write cycle */
& ~csr_a[8] /* which is not for register file */
& ~csr_a[9] /* nor for program memory */
)
begin
/* then it is for control registers */
case(csr_a[2:0])
3'b000: begin
start <= csr_di[0];
vertex_counter <= 14'd0;
collision_counter <= 11'd0;
stray_counter <= 11'd0;
end
3'b001: dma_base <= csr_di[31:3];
3'b010: hmesh_last <= csr_di[6:0];
3'b011: vmesh_last <= csr_di[6:0];
3'b100: cp_page <= csr_di[1:0];
default:;
endcase
end
end
end
end
/*
* Program memory and register file have synchronous read,
* so we must use some tricks to move the registers into them.
*/
assign csr_do =
({32{csr_do_cont}} & csr_do_r)
|({32{csr_do_prog}} & cp_di)
|({32{csr_do_regf}} & cr_di);
assign cp_offset = csr_a[8:0];
assign cp_w_en = csr_selected & csr_a[9] & csr_we;
assign cp_do = csr_di;
assign cr_addr = csr_a[6:0];
assign cr_w_en = csr_selected & ~csr_a[9] & csr_a[8] & csr_we;
assign cr_do = csr_di;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:53:19 10/26/2014
// Design Name:
// Module Name: tb_uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_uart;
reg clk;
reg reset;
reg tx;
// Outputs
reg rx;
wire led;
parameter CLK_PERIOD=20; //clock period in ns. 20 ns = 50 MHZ
parameter UUT_PERIOD=8'h1A; //57600 baudrate
parameter CLK16X_PERIOD=(CLK_PERIOD*(UUT_PERIOD+1)*2);
parameter CHARACTER_PERIOD = (CLK16X_PERIOD * 16 * 10);
uart u1(
.clk (clk),
.reset (reset),
.rx (rx),
.tx (tx)
);
`define FSIZE 1024
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer errors;
initial begin
clk = 0;
#100 //reset delay
forever #10 clk = ~clk;
end
reg [9:0] shiftdata;
integer i;
task putserialdata;
input [8:0] outdata;
begin
infifo[head] = outdata;
head = head + 1;
if (head == `FSIZE) head = 0;
shiftdata ={1'b1,outdata[7:0],1'b0};
i = 0;
while (i != 10) begin
rx = shiftdata[0];
#(CLK16X_PERIOD*16) //wait one bit time
i = i + 1;
shiftdata = {1'b1,shiftdata[9:1]};
end
end
endtask
initial begin
clk = 0;
reset = 1;
tx = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
putserialdata(9'h0ab);
end
endmodule
|
//caution do not edit this file manually it is a template in tenjin format
`define Buff_size 32
////////////////////////////////////////////
#{MODULE_TEXT}
///////////////////////////////////////////
input clk; // 50MHz
input rst_n; //reset, neg edge.
input rs232_rx; // RS232 rec
//output rs232_tx; // RS232 transfer
/////////////////////////////////////////
#{INOUT_TEXT}
////////////////////////////////////////
output led; // debug led
// state control
parameter IDLE = 3'b000;
parameter S1 = 3'b001;
parameter WAIT = 3'b010;
parameter SAVE = 3'b100;
// commond reg
parameter A=8'h41 ;
parameter B=8'h42 ;
parameter C=8'h43 ;
parameter D=8'h44 ;
parameter E=8'h45 ;
parameter F=8'h46 ;
parameter G=8'h47 ;
parameter H=8'h48 ;
parameter I=8'h49 ;
parameter J=8'h4a ;
parameter K=8'h4b ;
parameter L=8'h4c ;
parameter M=8'h4d ;
parameter N=8'h4e ;
parameter O=8'h4f ;
parameter P=8'h50 ;
parameter Q=8'h51 ;
parameter R=8'h52 ;
parameter S=8'h53 ;
parameter T=8'h54 ;
parameter U=8'h55 ;
parameter V=8'h56 ;
parameter W=8'h57 ;
parameter X=8'h58 ;
parameter Y=8'h59 ;
parameter Z=8'h5a ;
parameter Z0=8'h30 ;
parameter I1=8'h31 ;
parameter II=8'h32 ;
parameter III=8'h33 ;
parameter IV=8'h34 ;
parameter V5=8'h35 ;
parameter VI=8'h36 ;
parameter VII=8'h37 ;
parameter VIII=8'h38 ;
parameter VIIII=8'h39 ;
//definition of inputs/outputs
wire test;
wire Flag; // signal the uart has data
wire rs232_rx;
wire clk,rst_n;
wire bps_start; // start receive
wire bps_start_t; // start tranmit
wire clk_bps; // uart bps
wire clk_bps_t; // uart bps
wire[7:0] rx_data; // receive data to parser
wire rx_int; // receive interrupt
wire rx_error;
wire tx_error;
wire rx_complete;
wire tx_complete;
wire[7:0] tx_data;
wire rs232_tx;
#{WIRE_TEXT}
////////////////////////////////////////////////////////////////////////////////////////////////
//debug led
reg led;
reg cmd_red;
// settings for log register
reg [`Buff_size-1:0] Buff_temp;
reg [`Buff_size-9:0] Rx_cmd;
reg [2:0] Current, Next;
reg Flag_temp;
//build in module enable
reg linkBIM;
reg capture_rst;
#{REG_TEXT}
#{ASSIGN_TEXT}
#{IP_TEXT}
/////////////////////////////////////////////////////////////////////////////////////////////////////
reg flag_reg;
always @ (negedge bps_start or negedge rst_n)
begin
if (!rst_n)
flag_reg <= 1'b0;
else if (!bps_start)
flag_reg <= ~flag_reg;
end
assign Flag = flag_reg;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
Current <= IDLE;
else
Current <= Next;
end
// the state machine for receive data bytes
always @ (*)
begin
Next = IDLE;
case (Current)
IDLE:
if (rx_data == 8'h24) //$
Next = S1;
else
Next = IDLE;
S1:
if (Flag_temp != Flag)
begin
if (rx_data != 8'h0d) //\n
Next = S1;
else
Next = SAVE;
end
else
Next = WAIT;
WAIT:
if (Flag_temp!=Flag)
begin
if (rx_data != 8'h0d)
Next = S1;
else
Next = SAVE;
end
else
Next = WAIT;
default: Next = IDLE;
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
Flag_temp <= 1'b0;
end
else
begin
Flag_temp <= Flag;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
Buff_temp <= `Buff_size'b0;
Rx_cmd <= `Buff_size'b0;
cmd_red <= 1'b0;
end
else
begin
case (Current)
IDLE:
begin
Buff_temp <= `Buff_size'b0;
end
S1:
begin
cmd_red <= 1'b1;
Buff_temp <= {{Buff_temp[`Buff_size - 9 : 0]}, rx_data};
end
WAIT:
begin
Buff_temp <= Buff_temp;
end
SAVE:
begin
Rx_cmd <= Buff_temp[`Buff_size - 9 : 0];
Buff_temp <= `Buff_size'b0;
cmd_red <= 1'b0;
end
default:
begin
end
endcase
end
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
//////////////////add link here////////////////
#{INIT_REG_TEXT}
///////////////////////////////////////////////
led <= 1'b0; // for debug led
linkBIM <= 1'b1;
end
else if(cmd_red) begin
#{RST_REG_TEXT}
led <= 1'b0;
capture_rst <= 1'b0;
end
else
begin
case(Rx_cmd)
///////////////////add case here/////////////
#{CMD_CASE_TEXT}
/////////////////////////////////////////////
{R,S,T}: //RESET
begin
#{RST_REG_TEXT}
led <= 1'b0;
linkBIM <= 1'b1;
capture_rst <= 1'b0;
end
default:
begin
#{DFT_REG_TEXT}
led <= 1'b0;
linkBIM <= 1'b1;
capture_rst <= 1'b0;
end
endcase
end
end
/////////////////////////////////////////////////////////////
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module aes128(clk, state, key, out);
input clk;
input [127:0] state, key;
output [127:0] out;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
always @ (posedge clk)
begin
s0 <= state ^ key;
k0 <= key;
end
expand_key_128
a1 (clk, k0, k1, k0b, 8'h1),
a2 (clk, k1, k2, k1b, 8'h2),
a3 (clk, k2, k3, k2b, 8'h4),
a4 (clk, k3, k4, k3b, 8'h8),
a5 (clk, k4, k5, k4b, 8'h10),
a6 (clk, k5, k6, k5b, 8'h20),
a7 (clk, k6, k7, k6b, 8'h40),
a8 (clk, k7, k8, k7b, 8'h80),
a9 (clk, k8, k9, k8b, 8'h1b),
a10 (clk, k9, , k9b, 8'h36);
one_round
r1 (clk, s0, k0b, s1),
r2 (clk, s1, k1b, s2),
r3 (clk, s2, k2b, s3),
r4 (clk, s3, k3b, s4),
r5 (clk, s4, k4b, s5),
r6 (clk, s5, k5b, s6),
r7 (clk, s6, k6b, s7),
r8 (clk, s7, k7b, s8),
r9 (clk, s8, k8b, s9);
final_round
rf (clk, s9, k9b, out);
endmodule
module expand_key_128(clk, in, out_1, out_2, rcon);
input clk;
input [127:0] in;
input [7:0] rcon;
output reg [127:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
assign {k0, k1, k2, k3} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk)
{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
S4
S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
always @ (posedge clk)
out_1 <= {k0b, k1b, k2b, k3b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
/* one AES round for every two clock cycles */
module one_round (clk, state_in, key, state_out);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, s0, p00, p01, p02, p03),
t1 (clk, s1, p10, p11, p12, p13),
t2 (clk, s2, p20, p21, p22, p23),
t3 (clk, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
/* AES final round for every two clock cycles */
module final_round (clk, state_in, key_in, state_out);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, s0, {p00, p01, p02, p03}),
S4_2 (clk, s1, {p10, p11, p12, p13}),
S4_3 (clk, s2, {p20, p21, p22, p23}),
S4_4 (clk, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
/*http://cs-www.cs.yale.edu/homes/peralta/CircuitStuff/CMT.html*/
module S(
input clk,
input [7:0] in,
output reg [7:0] out
);
wire[0:7] s, x;
assign x = in;
always @ (posedge clk)
out <= s;
wire [21:0] y;
wire [67:0] t;
wire [17:0] z;
assign y[14] = x[3] ^ x[5];
assign y[13] = x[0] ^ x[6];
assign y[9] = x[0] ^ x[3];
assign y[8] = x[0] ^ x[5];
assign t[0] = x[1] ^ x[2];
assign y[1] = t[0] ^ x[7];
assign y[4] = y[1] ^ x[3];
assign y[12] = y[13] ^ y[14];
assign y[2] = y[1] ^ x[0];
assign y[5] = y[1] ^ x[6];
assign y[3] = y[5] ^ y[8];
assign t[1] = x[4] ^ y[12];
assign y[15] = t[1] ^ x[5];
assign y[20] = t[1] ^ x[1];
assign y[6] = y[15] ^ x[7];
assign y[10] = y[15] ^ t[0];
assign y[11] = y[20] ^ y[9];
assign y[7] = x[7] ^ y[11];
assign y[17] = y[10] ^ y[11];
assign y[19] = y[10] ^ y[8];
assign y[16] = t[0] ^ y[11];
assign y[21] = y[13] ^ y[16];
assign y[18] = x[0] ^ y[16];
assign t[2] = y[12] & y[15];
assign t[3] = y[3] & y[6];
assign t[4] = t[3] ^ t[2];
assign t[5] = y[4] & x[7];
assign t[6] = t[5] ^ t[2];
assign t[7] = y[13] & y[16];
assign t[8] = y[5] & y[1];
assign t[9] = t[8] ^ t[7];
assign t[10] = y[2] & y[7];
assign t[11] = t[10] ^ t[7];
assign t[12] = y[9] & y[11];
assign t[13] = y[14] & y[17];
assign t[14] = t[13] ^ t[12];
assign t[15] = y[8] & y[10];
assign t[16] = t[15] ^ t[12];
assign t[17] = t[4] ^ t[14];
assign t[18] = t[6] ^ t[16];
assign t[19] = t[9] ^ t[14];
assign t[20] = t[11] ^ t[16];
assign t[21] = t[17] ^ y[20];
assign t[22] = t[18] ^ y[19];
assign t[23] = t[19] ^ y[21];
assign t[24] = t[20] ^ y[18];
assign t[25] = t[21] ^ t[22];
assign t[26] = t[21] & t[23];
assign t[27] = t[24] ^ t[26];
assign t[28] = t[25] & t[27];
assign t[29] = t[28] ^ t[22];
assign t[30] = t[23] ^ t[24];
assign t[31] = t[22] ^ t[26];
assign t[32] = t[31] & t[30];
assign t[33] = t[32] ^ t[24];
assign t[34] = t[23] ^ t[33];
assign t[35] = t[27] ^ t[33];
assign t[36] = t[24] & t[35];
assign t[37] = t[36] ^ t[34];
assign t[38] = t[27] ^ t[36];
assign t[39] = t[29] & t[38];
assign t[40] = t[25] ^ t[39];
assign t[41] = t[40] ^ t[37];
assign t[42] = t[29] ^ t[33];
assign t[43] = t[29] ^ t[40];
assign t[44] = t[33] ^ t[37];
assign t[45] = t[42] ^ t[41];
assign z[0] = t[44] & y[15];
assign z[1] = t[37] & y[6];
assign z[2] = t[33] & x[7];
assign z[3] = t[43] & y[16];
assign z[4] = t[40] & y[1];
assign z[5] = t[29] & y[7];
assign z[6] = t[42] & y[11];
assign z[7] = t[45] & y[17];
assign z[8] = t[41] & y[10];
assign z[9] = t[44] & y[12];
assign z[10] = t[37] & y[3];
assign z[11] = t[33] & y[4];
assign z[12] = t[43] & y[13];
assign z[13] = t[40] & y[5];
assign z[14] = t[29] & y[2];
assign z[15] = t[42] & y[9];
assign z[16] = t[45] & y[14];
assign z[17] = t[41] & y[8];
assign t[46] = z[15] ^ z[16];
assign t[47] = z[10] ^ z[11];
assign t[48] = z[5] ^ z[13];
assign t[49] = z[9] ^ z[10];
assign t[50] = z[2] ^ z[12];
assign t[51] = z[2] ^ z[5];
assign t[52] = z[7] ^ z[8];
assign t[53] = z[0] ^ z[3];
assign t[54] = z[6] ^ z[7];
assign t[55] = z[16] ^ z[17];
assign t[56] = z[12] ^ t[48];
assign t[57] = t[50] ^ t[53];
assign t[58] = z[4] ^ t[46];
assign t[59] = z[3] ^ t[54];
assign t[60] = t[46] ^ t[57];
assign t[61] = z[14] ^ t[57];
assign t[62] = t[52] ^ t[58];
assign t[63] = t[49] ^ t[58];
assign t[64] = z[4] ^ t[59];
assign t[65] = t[61] ^ t[62];
assign t[66] = z[1] ^ t[63];
assign s[0] = t[59] ^ t[63];
assign s[6] = ~t[56 ] ^ t[62];
assign s[7] = ~t[48 ] ^ t[60];
assign t[67] = t[64] ^ t[65];
assign s[3] = t[53] ^ t[66];
assign s[4] = t[51] ^ t[66];
assign s[5] = t[47] ^ t[65];
assign s[1] = ~t[64 ] ^ s[3];
assign s[2] = ~t[55 ] ^ t[67];
endmodule
module xS (clk, in, out); //this is sbox times 2
input clk;
input [7:0] in;
output [7:0] out;
wire [7:0] out_2;
S S_(
.clk(clk),
.in(in),
.out(out_2)
);
wire dummy;
assign {dummy, out} = out_2[7]? {out_2, 1'b0}^9'h11b : {out_2, 1'b0}; //Finite Field Multiplication: https://www.cs.uaf.edu/2013/spring/cs463/lecture/02_11_groups_fields.html
endmodule
module table_lookup (clk, state, p0, p1, p2, p3);
input clk;
input [31:0] state;
output [31:0] p0, p1, p2, p3;
wire [7:0] b0, b1, b2, b3;
assign {b0, b1, b2, b3} = state;
T
t0 (clk, b0, {p0[23:0], p0[31:24]}),
t1 (clk, b1, {p1[15:0], p1[31:16]}),
t2 (clk, b2, {p2[7:0], p2[31:8]} ),
t3 (clk, b3, p3);
endmodule
/* substitue four bytes in a word */
module S4 (clk, in, out);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (clk, in[31:24], out[31:24]),
S_1 (clk, in[23:16], out[23:16]),
S_2 (clk, in[15:8], out[15:8] ),
S_3 (clk, in[7:0], out[7:0] );
endmodule
/* S_box, S_box, S_box*(x+1), S_box*x */
module T (clk, in, out);
input clk;
input [7:0] in;
output [31:0] out;
S
s0 (clk, in, out[31:24]);
assign out[23:16] = out[31:24];
xS
s4 (clk, in, out[7:0]);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
/* S box */
module S_table (clk, in, out); //uses BRAM, implementation based on logic operations included in sbox.v
input clk;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk)
case (in)
8'h00: out <= 8'h63;
8'h01: out <= 8'h7c;
8'h02: out <= 8'h77;
8'h03: out <= 8'h7b;
8'h04: out <= 8'hf2;
8'h05: out <= 8'h6b;
8'h06: out <= 8'h6f;
8'h07: out <= 8'hc5;
8'h08: out <= 8'h30;
8'h09: out <= 8'h01;
8'h0a: out <= 8'h67;
8'h0b: out <= 8'h2b;
8'h0c: out <= 8'hfe;
8'h0d: out <= 8'hd7;
8'h0e: out <= 8'hab;
8'h0f: out <= 8'h76;
8'h10: out <= 8'hca;
8'h11: out <= 8'h82;
8'h12: out <= 8'hc9;
8'h13: out <= 8'h7d;
8'h14: out <= 8'hfa;
8'h15: out <= 8'h59;
8'h16: out <= 8'h47;
8'h17: out <= 8'hf0;
8'h18: out <= 8'had;
8'h19: out <= 8'hd4;
8'h1a: out <= 8'ha2;
8'h1b: out <= 8'haf;
8'h1c: out <= 8'h9c;
8'h1d: out <= 8'ha4;
8'h1e: out <= 8'h72;
8'h1f: out <= 8'hc0;
8'h20: out <= 8'hb7;
8'h21: out <= 8'hfd;
8'h22: out <= 8'h93;
8'h23: out <= 8'h26;
8'h24: out <= 8'h36;
8'h25: out <= 8'h3f;
8'h26: out <= 8'hf7;
8'h27: out <= 8'hcc;
8'h28: out <= 8'h34;
8'h29: out <= 8'ha5;
8'h2a: out <= 8'he5;
8'h2b: out <= 8'hf1;
8'h2c: out <= 8'h71;
8'h2d: out <= 8'hd8;
8'h2e: out <= 8'h31;
8'h2f: out <= 8'h15;
8'h30: out <= 8'h04;
8'h31: out <= 8'hc7;
8'h32: out <= 8'h23;
8'h33: out <= 8'hc3;
8'h34: out <= 8'h18;
8'h35: out <= 8'h96;
8'h36: out <= 8'h05;
8'h37: out <= 8'h9a;
8'h38: out <= 8'h07;
8'h39: out <= 8'h12;
8'h3a: out <= 8'h80;
8'h3b: out <= 8'he2;
8'h3c: out <= 8'heb;
8'h3d: out <= 8'h27;
8'h3e: out <= 8'hb2;
8'h3f: out <= 8'h75;
8'h40: out <= 8'h09;
8'h41: out <= 8'h83;
8'h42: out <= 8'h2c;
8'h43: out <= 8'h1a;
8'h44: out <= 8'h1b;
8'h45: out <= 8'h6e;
8'h46: out <= 8'h5a;
8'h47: out <= 8'ha0;
8'h48: out <= 8'h52;
8'h49: out <= 8'h3b;
8'h4a: out <= 8'hd6;
8'h4b: out <= 8'hb3;
8'h4c: out <= 8'h29;
8'h4d: out <= 8'he3;
8'h4e: out <= 8'h2f;
8'h4f: out <= 8'h84;
8'h50: out <= 8'h53;
8'h51: out <= 8'hd1;
8'h52: out <= 8'h00;
8'h53: out <= 8'hed;
8'h54: out <= 8'h20;
8'h55: out <= 8'hfc;
8'h56: out <= 8'hb1;
8'h57: out <= 8'h5b;
8'h58: out <= 8'h6a;
8'h59: out <= 8'hcb;
8'h5a: out <= 8'hbe;
8'h5b: out <= 8'h39;
8'h5c: out <= 8'h4a;
8'h5d: out <= 8'h4c;
8'h5e: out <= 8'h58;
8'h5f: out <= 8'hcf;
8'h60: out <= 8'hd0;
8'h61: out <= 8'hef;
8'h62: out <= 8'haa;
8'h63: out <= 8'hfb;
8'h64: out <= 8'h43;
8'h65: out <= 8'h4d;
8'h66: out <= 8'h33;
8'h67: out <= 8'h85;
8'h68: out <= 8'h45;
8'h69: out <= 8'hf9;
8'h6a: out <= 8'h02;
8'h6b: out <= 8'h7f;
8'h6c: out <= 8'h50;
8'h6d: out <= 8'h3c;
8'h6e: out <= 8'h9f;
8'h6f: out <= 8'ha8;
8'h70: out <= 8'h51;
8'h71: out <= 8'ha3;
8'h72: out <= 8'h40;
8'h73: out <= 8'h8f;
8'h74: out <= 8'h92;
8'h75: out <= 8'h9d;
8'h76: out <= 8'h38;
8'h77: out <= 8'hf5;
8'h78: out <= 8'hbc;
8'h79: out <= 8'hb6;
8'h7a: out <= 8'hda;
8'h7b: out <= 8'h21;
8'h7c: out <= 8'h10;
8'h7d: out <= 8'hff;
8'h7e: out <= 8'hf3;
8'h7f: out <= 8'hd2;
8'h80: out <= 8'hcd;
8'h81: out <= 8'h0c;
8'h82: out <= 8'h13;
8'h83: out <= 8'hec;
8'h84: out <= 8'h5f;
8'h85: out <= 8'h97;
8'h86: out <= 8'h44;
8'h87: out <= 8'h17;
8'h88: out <= 8'hc4;
8'h89: out <= 8'ha7;
8'h8a: out <= 8'h7e;
8'h8b: out <= 8'h3d;
8'h8c: out <= 8'h64;
8'h8d: out <= 8'h5d;
8'h8e: out <= 8'h19;
8'h8f: out <= 8'h73;
8'h90: out <= 8'h60;
8'h91: out <= 8'h81;
8'h92: out <= 8'h4f;
8'h93: out <= 8'hdc;
8'h94: out <= 8'h22;
8'h95: out <= 8'h2a;
8'h96: out <= 8'h90;
8'h97: out <= 8'h88;
8'h98: out <= 8'h46;
8'h99: out <= 8'hee;
8'h9a: out <= 8'hb8;
8'h9b: out <= 8'h14;
8'h9c: out <= 8'hde;
8'h9d: out <= 8'h5e;
8'h9e: out <= 8'h0b;
8'h9f: out <= 8'hdb;
8'ha0: out <= 8'he0;
8'ha1: out <= 8'h32;
8'ha2: out <= 8'h3a;
8'ha3: out <= 8'h0a;
8'ha4: out <= 8'h49;
8'ha5: out <= 8'h06;
8'ha6: out <= 8'h24;
8'ha7: out <= 8'h5c;
8'ha8: out <= 8'hc2;
8'ha9: out <= 8'hd3;
8'haa: out <= 8'hac;
8'hab: out <= 8'h62;
8'hac: out <= 8'h91;
8'had: out <= 8'h95;
8'hae: out <= 8'he4;
8'haf: out <= 8'h79;
8'hb0: out <= 8'he7;
8'hb1: out <= 8'hc8;
8'hb2: out <= 8'h37;
8'hb3: out <= 8'h6d;
8'hb4: out <= 8'h8d;
8'hb5: out <= 8'hd5;
8'hb6: out <= 8'h4e;
8'hb7: out <= 8'ha9;
8'hb8: out <= 8'h6c;
8'hb9: out <= 8'h56;
8'hba: out <= 8'hf4;
8'hbb: out <= 8'hea;
8'hbc: out <= 8'h65;
8'hbd: out <= 8'h7a;
8'hbe: out <= 8'hae;
8'hbf: out <= 8'h08;
8'hc0: out <= 8'hba;
8'hc1: out <= 8'h78;
8'hc2: out <= 8'h25;
8'hc3: out <= 8'h2e;
8'hc4: out <= 8'h1c;
8'hc5: out <= 8'ha6;
8'hc6: out <= 8'hb4;
8'hc7: out <= 8'hc6;
8'hc8: out <= 8'he8;
8'hc9: out <= 8'hdd;
8'hca: out <= 8'h74;
8'hcb: out <= 8'h1f;
8'hcc: out <= 8'h4b;
8'hcd: out <= 8'hbd;
8'hce: out <= 8'h8b;
8'hcf: out <= 8'h8a;
8'hd0: out <= 8'h70;
8'hd1: out <= 8'h3e;
8'hd2: out <= 8'hb5;
8'hd3: out <= 8'h66;
8'hd4: out <= 8'h48;
8'hd5: out <= 8'h03;
8'hd6: out <= 8'hf6;
8'hd7: out <= 8'h0e;
8'hd8: out <= 8'h61;
8'hd9: out <= 8'h35;
8'hda: out <= 8'h57;
8'hdb: out <= 8'hb9;
8'hdc: out <= 8'h86;
8'hdd: out <= 8'hc1;
8'hde: out <= 8'h1d;
8'hdf: out <= 8'h9e;
8'he0: out <= 8'he1;
8'he1: out <= 8'hf8;
8'he2: out <= 8'h98;
8'he3: out <= 8'h11;
8'he4: out <= 8'h69;
8'he5: out <= 8'hd9;
8'he6: out <= 8'h8e;
8'he7: out <= 8'h94;
8'he8: out <= 8'h9b;
8'he9: out <= 8'h1e;
8'hea: out <= 8'h87;
8'heb: out <= 8'he9;
8'hec: out <= 8'hce;
8'hed: out <= 8'h55;
8'hee: out <= 8'h28;
8'hef: out <= 8'hdf;
8'hf0: out <= 8'h8c;
8'hf1: out <= 8'ha1;
8'hf2: out <= 8'h89;
8'hf3: out <= 8'h0d;
8'hf4: out <= 8'hbf;
8'hf5: out <= 8'he6;
8'hf6: out <= 8'h42;
8'hf7: out <= 8'h68;
8'hf8: out <= 8'h41;
8'hf9: out <= 8'h99;
8'hfa: out <= 8'h2d;
8'hfb: out <= 8'h0f;
8'hfc: out <= 8'hb0;
8'hfd: out <= 8'h54;
8'hfe: out <= 8'hbb;
8'hff: out <= 8'h16;
endcase
endmodule
/* S box * x */
module xS_table (clk, in, out); //uses BRAM, implementation based on logic operations included in sbox.v
input clk;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk)
case (in)
8'h00: out <= 8'hc6;
8'h01: out <= 8'hf8;
8'h02: out <= 8'hee;
8'h03: out <= 8'hf6;
8'h04: out <= 8'hff;
8'h05: out <= 8'hd6;
8'h06: out <= 8'hde;
8'h07: out <= 8'h91;
8'h08: out <= 8'h60;
8'h09: out <= 8'h02;
8'h0a: out <= 8'hce;
8'h0b: out <= 8'h56;
8'h0c: out <= 8'he7;
8'h0d: out <= 8'hb5;
8'h0e: out <= 8'h4d;
8'h0f: out <= 8'hec;
8'h10: out <= 8'h8f;
8'h11: out <= 8'h1f;
8'h12: out <= 8'h89;
8'h13: out <= 8'hfa;
8'h14: out <= 8'hef;
8'h15: out <= 8'hb2;
8'h16: out <= 8'h8e;
8'h17: out <= 8'hfb;
8'h18: out <= 8'h41;
8'h19: out <= 8'hb3;
8'h1a: out <= 8'h5f;
8'h1b: out <= 8'h45;
8'h1c: out <= 8'h23;
8'h1d: out <= 8'h53;
8'h1e: out <= 8'he4;
8'h1f: out <= 8'h9b;
8'h20: out <= 8'h75;
8'h21: out <= 8'he1;
8'h22: out <= 8'h3d;
8'h23: out <= 8'h4c;
8'h24: out <= 8'h6c;
8'h25: out <= 8'h7e;
8'h26: out <= 8'hf5;
8'h27: out <= 8'h83;
8'h28: out <= 8'h68;
8'h29: out <= 8'h51;
8'h2a: out <= 8'hd1;
8'h2b: out <= 8'hf9;
8'h2c: out <= 8'he2;
8'h2d: out <= 8'hab;
8'h2e: out <= 8'h62;
8'h2f: out <= 8'h2a;
8'h30: out <= 8'h08;
8'h31: out <= 8'h95;
8'h32: out <= 8'h46;
8'h33: out <= 8'h9d;
8'h34: out <= 8'h30;
8'h35: out <= 8'h37;
8'h36: out <= 8'h0a;
8'h37: out <= 8'h2f;
8'h38: out <= 8'h0e;
8'h39: out <= 8'h24;
8'h3a: out <= 8'h1b;
8'h3b: out <= 8'hdf;
8'h3c: out <= 8'hcd;
8'h3d: out <= 8'h4e;
8'h3e: out <= 8'h7f;
8'h3f: out <= 8'hea;
8'h40: out <= 8'h12;
8'h41: out <= 8'h1d;
8'h42: out <= 8'h58;
8'h43: out <= 8'h34;
8'h44: out <= 8'h36;
8'h45: out <= 8'hdc;
8'h46: out <= 8'hb4;
8'h47: out <= 8'h5b;
8'h48: out <= 8'ha4;
8'h49: out <= 8'h76;
8'h4a: out <= 8'hb7;
8'h4b: out <= 8'h7d;
8'h4c: out <= 8'h52;
8'h4d: out <= 8'hdd;
8'h4e: out <= 8'h5e;
8'h4f: out <= 8'h13;
8'h50: out <= 8'ha6;
8'h51: out <= 8'hb9;
8'h52: out <= 8'h00;
8'h53: out <= 8'hc1;
8'h54: out <= 8'h40;
8'h55: out <= 8'he3;
8'h56: out <= 8'h79;
8'h57: out <= 8'hb6;
8'h58: out <= 8'hd4;
8'h59: out <= 8'h8d;
8'h5a: out <= 8'h67;
8'h5b: out <= 8'h72;
8'h5c: out <= 8'h94;
8'h5d: out <= 8'h98;
8'h5e: out <= 8'hb0;
8'h5f: out <= 8'h85;
8'h60: out <= 8'hbb;
8'h61: out <= 8'hc5;
8'h62: out <= 8'h4f;
8'h63: out <= 8'hed;
8'h64: out <= 8'h86;
8'h65: out <= 8'h9a;
8'h66: out <= 8'h66;
8'h67: out <= 8'h11;
8'h68: out <= 8'h8a;
8'h69: out <= 8'he9;
8'h6a: out <= 8'h04;
8'h6b: out <= 8'hfe;
8'h6c: out <= 8'ha0;
8'h6d: out <= 8'h78;
8'h6e: out <= 8'h25;
8'h6f: out <= 8'h4b;
8'h70: out <= 8'ha2;
8'h71: out <= 8'h5d;
8'h72: out <= 8'h80;
8'h73: out <= 8'h05;
8'h74: out <= 8'h3f;
8'h75: out <= 8'h21;
8'h76: out <= 8'h70;
8'h77: out <= 8'hf1;
8'h78: out <= 8'h63;
8'h79: out <= 8'h77;
8'h7a: out <= 8'haf;
8'h7b: out <= 8'h42;
8'h7c: out <= 8'h20;
8'h7d: out <= 8'he5;
8'h7e: out <= 8'hfd;
8'h7f: out <= 8'hbf;
8'h80: out <= 8'h81;
8'h81: out <= 8'h18;
8'h82: out <= 8'h26;
8'h83: out <= 8'hc3;
8'h84: out <= 8'hbe;
8'h85: out <= 8'h35;
8'h86: out <= 8'h88;
8'h87: out <= 8'h2e;
8'h88: out <= 8'h93;
8'h89: out <= 8'h55;
8'h8a: out <= 8'hfc;
8'h8b: out <= 8'h7a;
8'h8c: out <= 8'hc8;
8'h8d: out <= 8'hba;
8'h8e: out <= 8'h32;
8'h8f: out <= 8'he6;
8'h90: out <= 8'hc0;
8'h91: out <= 8'h19;
8'h92: out <= 8'h9e;
8'h93: out <= 8'ha3;
8'h94: out <= 8'h44;
8'h95: out <= 8'h54;
8'h96: out <= 8'h3b;
8'h97: out <= 8'h0b;
8'h98: out <= 8'h8c;
8'h99: out <= 8'hc7;
8'h9a: out <= 8'h6b;
8'h9b: out <= 8'h28;
8'h9c: out <= 8'ha7;
8'h9d: out <= 8'hbc;
8'h9e: out <= 8'h16;
8'h9f: out <= 8'had;
8'ha0: out <= 8'hdb;
8'ha1: out <= 8'h64;
8'ha2: out <= 8'h74;
8'ha3: out <= 8'h14;
8'ha4: out <= 8'h92;
8'ha5: out <= 8'h0c;
8'ha6: out <= 8'h48;
8'ha7: out <= 8'hb8;
8'ha8: out <= 8'h9f;
8'ha9: out <= 8'hbd;
8'haa: out <= 8'h43;
8'hab: out <= 8'hc4;
8'hac: out <= 8'h39;
8'had: out <= 8'h31;
8'hae: out <= 8'hd3;
8'haf: out <= 8'hf2;
8'hb0: out <= 8'hd5;
8'hb1: out <= 8'h8b;
8'hb2: out <= 8'h6e;
8'hb3: out <= 8'hda;
8'hb4: out <= 8'h01;
8'hb5: out <= 8'hb1;
8'hb6: out <= 8'h9c;
8'hb7: out <= 8'h49;
8'hb8: out <= 8'hd8;
8'hb9: out <= 8'hac;
8'hba: out <= 8'hf3;
8'hbb: out <= 8'hcf;
8'hbc: out <= 8'hca;
8'hbd: out <= 8'hf4;
8'hbe: out <= 8'h47;
8'hbf: out <= 8'h10;
8'hc0: out <= 8'h6f;
8'hc1: out <= 8'hf0;
8'hc2: out <= 8'h4a;
8'hc3: out <= 8'h5c;
8'hc4: out <= 8'h38;
8'hc5: out <= 8'h57;
8'hc6: out <= 8'h73;
8'hc7: out <= 8'h97;
8'hc8: out <= 8'hcb;
8'hc9: out <= 8'ha1;
8'hca: out <= 8'he8;
8'hcb: out <= 8'h3e;
8'hcc: out <= 8'h96;
8'hcd: out <= 8'h61;
8'hce: out <= 8'h0d;
8'hcf: out <= 8'h0f;
8'hd0: out <= 8'he0;
8'hd1: out <= 8'h7c;
8'hd2: out <= 8'h71;
8'hd3: out <= 8'hcc;
8'hd4: out <= 8'h90;
8'hd5: out <= 8'h06;
8'hd6: out <= 8'hf7;
8'hd7: out <= 8'h1c;
8'hd8: out <= 8'hc2;
8'hd9: out <= 8'h6a;
8'hda: out <= 8'hae;
8'hdb: out <= 8'h69;
8'hdc: out <= 8'h17;
8'hdd: out <= 8'h99;
8'hde: out <= 8'h3a;
8'hdf: out <= 8'h27;
8'he0: out <= 8'hd9;
8'he1: out <= 8'heb;
8'he2: out <= 8'h2b;
8'he3: out <= 8'h22;
8'he4: out <= 8'hd2;
8'he5: out <= 8'ha9;
8'he6: out <= 8'h07;
8'he7: out <= 8'h33;
8'he8: out <= 8'h2d;
8'he9: out <= 8'h3c;
8'hea: out <= 8'h15;
8'heb: out <= 8'hc9;
8'hec: out <= 8'h87;
8'hed: out <= 8'haa;
8'hee: out <= 8'h50;
8'hef: out <= 8'ha5;
8'hf0: out <= 8'h03;
8'hf1: out <= 8'h59;
8'hf2: out <= 8'h09;
8'hf3: out <= 8'h1a;
8'hf4: out <= 8'h65;
8'hf5: out <= 8'hd7;
8'hf6: out <= 8'h84;
8'hf7: out <= 8'hd0;
8'hf8: out <= 8'h82;
8'hf9: out <= 8'h29;
8'hfa: out <= 8'h5a;
8'hfb: out <= 8'h1e;
8'hfc: out <= 8'h7b;
8'hfd: out <= 8'ha8;
8'hfe: out <= 8'h6d;
8'hff: out <= 8'h2c;
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A32OI_BEHAVIORAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_BEHAVIORAL_PP_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_top_prim_conv11 (
primitive11_0_params_V_read,
primitive11_1_params_V_read,
primitive11_2_params_V_read,
primitive11_3_params_V_read,
primitive11_4_params_V_read,
primitive11_5_params_V_read,
primitive11_0_th_mem_V_read,
primitive11_1_th_mem_V_read,
primitive11_2_th_mem_V_read,
primitive11_3_th_mem_V_read,
primitive11_4_th_mem_V_read,
primitive11_5_th_mem_V_read,
primitive11_6_th_mem_V_read,
primitive11_7_th_mem_V_read,
primitive11_8_th_mem_V_read,
primitive11_9_th_mem_V_read,
primitive11_10_th_mem_V_read,
primitive11_11_th_mem_V_read,
primitive11_12_th_mem_V_read,
primitive11_13_th_mem_V_read,
primitive11_14_th_mem_V_read,
primitive11_15_th_mem_V_read,
primitive11_16_th_mem_V_read,
primitive11_17_th_mem_V_read,
primitive11_18_th_mem_V_read,
primitive11_19_th_mem_V_read,
primitive11_20_th_mem_V_read,
primitive11_21_th_mem_V_read,
primitive11_22_th_mem_V_read,
primitive11_23_th_mem_V_read,
primitive11_24_th_mem_V_read,
primitive11_25_th_mem_V_read,
primitive11_26_th_mem_V_read,
primitive11_27_th_mem_V_read,
primitive11_28_th_mem_V_read,
primitive11_29_th_mem_V_read,
primitive11_30_th_mem_V_read,
primitive11_31_th_mem_V_read,
primitive11_32_th_mem_V_read,
primitive11_33_th_mem_V_read,
primitive11_34_th_mem_V_read,
primitive11_35_th_mem_V_read,
primitive11_36_th_mem_V_read,
primitive11_37_th_mem_V_read,
primitive11_38_th_mem_V_read,
primitive11_39_th_mem_V_read,
primitive11_40_th_mem_V_read,
primitive11_41_th_mem_V_read,
primitive11_42_th_mem_V_read,
primitive11_43_th_mem_V_read,
primitive11_44_th_mem_V_read,
primitive11_45_th_mem_V_read,
primitive11_46_th_mem_V_read,
primitive11_47_th_mem_V_read,
primitive11_48_th_mem_V_read,
primitive11_49_th_mem_V_read,
primitive11_50_th_mem_V_read,
primitive11_51_th_mem_V_read,
primitive11_52_th_mem_V_read,
primitive11_53_th_mem_V_read,
primitive11_54_th_mem_V_read,
primitive11_55_th_mem_V_read,
primitive11_56_th_mem_V_read,
primitive11_57_th_mem_V_read,
primitive11_58_th_mem_V_read,
primitive11_59_th_mem_V_read,
primitive11_60_th_mem_V_read,
primitive11_61_th_mem_V_read,
primitive11_62_th_mem_V_read,
primitive11_63_th_mem_V_read,
primitive11_64_th_mem_V_read,
primitive11_65_th_mem_V_read,
primitive11_66_th_mem_V_read,
primitive11_67_th_mem_V_read,
primitive11_68_th_mem_V_read,
primitive11_69_th_mem_V_read,
primitive11_70_th_mem_V_read,
primitive11_71_th_mem_V_read,
primitive11_72_th_mem_V_read,
primitive11_73_th_mem_V_read,
primitive11_74_th_mem_V_read,
primitive11_75_th_mem_V_read,
primitive11_76_th_mem_V_read,
primitive11_77_th_mem_V_read,
primitive11_78_th_mem_V_read,
primitive11_79_th_mem_V_read,
primitive11_80_th_mem_V_read,
primitive11_81_th_mem_V_read,
primitive11_82_th_mem_V_read,
primitive11_83_th_mem_V_read,
primitive11_84_th_mem_V_read,
primitive11_85_th_mem_V_read,
primitive11_86_th_mem_V_read,
primitive11_87_th_mem_V_read,
primitive11_88_th_mem_V_read,
primitive11_89_th_mem_V_read,
primitive11_90_th_mem_V_read,
primitive11_91_th_mem_V_read,
primitive11_92_th_mem_V_read,
primitive11_93_th_mem_V_read,
primitive11_94_th_mem_V_read,
primitive11_95_th_mem_V_read,
primitive11_96_th_mem_V_read,
primitive11_97_th_mem_V_read,
primitive11_98_th_mem_V_read,
primitive11_99_th_mem_V_read,
primitive11_100_th_mem_V_read,
primitive11_101_th_mem_V_read,
primitive11_102_th_mem_V_read,
primitive11_103_th_mem_V_read,
primitive11_104_th_mem_V_read,
primitive11_105_th_mem_V_read,
primitive11_106_th_mem_V_read,
primitive11_107_th_mem_V_read,
primitive11_108_th_mem_V_read,
primitive11_109_th_mem_V_read,
primitive11_110_th_mem_V_read,
primitive11_111_th_mem_V_read,
primitive11_112_th_mem_V_read,
primitive11_113_th_mem_V_read,
primitive11_114_th_mem_V_read,
primitive11_115_th_mem_V_read,
primitive11_116_th_mem_V_read,
primitive11_117_th_mem_V_read,
primitive11_118_th_mem_V_read,
primitive11_119_th_mem_V_read,
primitive11_120_th_mem_V_read,
primitive11_121_th_mem_V_read,
primitive11_122_th_mem_V_read,
primitive11_123_th_mem_V_read,
primitive11_124_th_mem_V_read,
primitive11_125_th_mem_V_read,
primitive11_126_th_mem_V_read,
primitive11_127_th_mem_V_read,
primitive11_0_th_corr_mem_V_read,
primitive11_1_th_corr_mem_V_read,
primitive11_2_th_corr_mem_V_read,
primitive11_3_th_corr_mem_V_read,
primitive11_4_th_corr_mem_V_read,
primitive11_5_th_corr_mem_V_read,
primitive11_6_th_corr_mem_V_read,
primitive11_7_th_corr_mem_V_read,
primitive11_8_th_corr_mem_V_read,
primitive11_9_th_corr_mem_V_read,
primitive11_10_th_corr_mem_V_read,
primitive11_11_th_corr_mem_V_read,
primitive11_12_th_corr_mem_V_read,
primitive11_13_th_corr_mem_V_read,
primitive11_14_th_corr_mem_V_read,
primitive11_15_th_corr_mem_V_read,
primitive11_16_th_corr_mem_V_read,
primitive11_17_th_corr_mem_V_read,
primitive11_18_th_corr_mem_V_read,
primitive11_19_th_corr_mem_V_read,
primitive11_20_th_corr_mem_V_read,
primitive11_21_th_corr_mem_V_read,
primitive11_22_th_corr_mem_V_read,
primitive11_23_th_corr_mem_V_read,
primitive11_24_th_corr_mem_V_read,
primitive11_25_th_corr_mem_V_read,
primitive11_26_th_corr_mem_V_read,
primitive11_27_th_corr_mem_V_read,
primitive11_28_th_corr_mem_V_read,
primitive11_29_th_corr_mem_V_read,
primitive11_30_th_corr_mem_V_read,
primitive11_31_th_corr_mem_V_read,
primitive11_32_th_corr_mem_V_read,
primitive11_33_th_corr_mem_V_read,
primitive11_34_th_corr_mem_V_read,
primitive11_35_th_corr_mem_V_read,
primitive11_36_th_corr_mem_V_read,
primitive11_37_th_corr_mem_V_read,
primitive11_38_th_corr_mem_V_read,
primitive11_39_th_corr_mem_V_read,
primitive11_40_th_corr_mem_V_read,
primitive11_41_th_corr_mem_V_read,
primitive11_42_th_corr_mem_V_read,
primitive11_43_th_corr_mem_V_read,
primitive11_44_th_corr_mem_V_read,
primitive11_45_th_corr_mem_V_read,
primitive11_46_th_corr_mem_V_read,
primitive11_47_th_corr_mem_V_read,
primitive11_48_th_corr_mem_V_read,
primitive11_49_th_corr_mem_V_read,
primitive11_50_th_corr_mem_V_read,
primitive11_51_th_corr_mem_V_read,
primitive11_52_th_corr_mem_V_read,
primitive11_53_th_corr_mem_V_read,
primitive11_54_th_corr_mem_V_read,
primitive11_55_th_corr_mem_V_read,
primitive11_56_th_corr_mem_V_read,
primitive11_57_th_corr_mem_V_read,
primitive11_58_th_corr_mem_V_read,
primitive11_59_th_corr_mem_V_read,
primitive11_60_th_corr_mem_V_read,
primitive11_61_th_corr_mem_V_read,
primitive11_62_th_corr_mem_V_read,
primitive11_63_th_corr_mem_V_read,
primitive11_64_th_corr_mem_V_read,
primitive11_65_th_corr_mem_V_read,
primitive11_66_th_corr_mem_V_read,
primitive11_67_th_corr_mem_V_read,
primitive11_68_th_corr_mem_V_read,
primitive11_69_th_corr_mem_V_read,
primitive11_70_th_corr_mem_V_read,
primitive11_71_th_corr_mem_V_read,
primitive11_72_th_corr_mem_V_read,
primitive11_73_th_corr_mem_V_read,
primitive11_74_th_corr_mem_V_read,
primitive11_75_th_corr_mem_V_read,
primitive11_76_th_corr_mem_V_read,
primitive11_77_th_corr_mem_V_read,
primitive11_78_th_corr_mem_V_read,
primitive11_79_th_corr_mem_V_read,
primitive11_80_th_corr_mem_V_read,
primitive11_81_th_corr_mem_V_read,
primitive11_82_th_corr_mem_V_read,
primitive11_83_th_corr_mem_V_read,
primitive11_84_th_corr_mem_V_read,
primitive11_85_th_corr_mem_V_read,
primitive11_86_th_corr_mem_V_read,
primitive11_87_th_corr_mem_V_read,
primitive11_88_th_corr_mem_V_read,
primitive11_89_th_corr_mem_V_read,
primitive11_90_th_corr_mem_V_read,
primitive11_91_th_corr_mem_V_read,
primitive11_92_th_corr_mem_V_read,
primitive11_93_th_corr_mem_V_read,
primitive11_94_th_corr_mem_V_read,
primitive11_95_th_corr_mem_V_read,
primitive11_96_th_corr_mem_V_read,
primitive11_97_th_corr_mem_V_read,
primitive11_98_th_corr_mem_V_read,
primitive11_99_th_corr_mem_V_read,
primitive11_100_th_corr_mem_V_read,
primitive11_101_th_corr_mem_V_read,
primitive11_102_th_corr_mem_V_read,
primitive11_103_th_corr_mem_V_read,
primitive11_104_th_corr_mem_V_read,
primitive11_105_th_corr_mem_V_read,
primitive11_106_th_corr_mem_V_read,
primitive11_107_th_corr_mem_V_read,
primitive11_108_th_corr_mem_V_read,
primitive11_109_th_corr_mem_V_read,
primitive11_110_th_corr_mem_V_read,
primitive11_111_th_corr_mem_V_read,
primitive11_112_th_corr_mem_V_read,
primitive11_113_th_corr_mem_V_read,
primitive11_114_th_corr_mem_V_read,
primitive11_115_th_corr_mem_V_read,
primitive11_116_th_corr_mem_V_read,
primitive11_117_th_corr_mem_V_read,
primitive11_118_th_corr_mem_V_read,
primitive11_119_th_corr_mem_V_read,
primitive11_120_th_corr_mem_V_read,
primitive11_121_th_corr_mem_V_read,
primitive11_122_th_corr_mem_V_read,
primitive11_123_th_corr_mem_V_read,
primitive11_124_th_corr_mem_V_read,
primitive11_125_th_corr_mem_V_read,
primitive11_126_th_corr_mem_V_read,
primitive11_127_th_corr_mem_V_read,
quality_0_V_read,
quality_1_V_read,
wiregroup_0_V_read,
wiregroup_1_V_read,
hstrip_0_V_read,
hstrip_1_V_read,
clctpat_0_V_read,
clctpat_1_V_read,
r_in_V,
we_V,
sel_V,
addr_V,
endcap_V,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5,
ap_return_6,
ap_return_7,
ap_return_8,
ap_return_9,
ap_return_10,
ap_return_11,
ap_return_12,
ap_return_13,
ap_return_14,
ap_return_15,
ap_return_16,
ap_return_17,
ap_return_18,
ap_return_19,
ap_return_20,
ap_return_21,
ap_return_22,
ap_return_23,
ap_return_24,
ap_return_25,
ap_return_26,
ap_return_27,
ap_return_28,
ap_return_29,
ap_return_30,
ap_return_31,
ap_return_32,
ap_return_33,
ap_return_34,
ap_return_35,
ap_return_36,
ap_return_37,
ap_return_38,
ap_return_39,
ap_return_40,
ap_return_41,
ap_return_42,
ap_return_43,
ap_return_44,
ap_return_45,
ap_return_46,
ap_return_47,
ap_return_48,
ap_return_49,
ap_return_50,
ap_return_51,
ap_return_52,
ap_return_53,
ap_return_54,
ap_return_55,
ap_return_56,
ap_return_57,
ap_return_58,
ap_return_59,
ap_return_60,
ap_return_61,
ap_return_62,
ap_return_63,
ap_return_64,
ap_return_65,
ap_return_66,
ap_return_67,
ap_return_68,
ap_return_69,
ap_return_70,
ap_return_71,
ap_return_72,
ap_return_73,
ap_return_74,
ap_return_75,
ap_return_76,
ap_return_77,
ap_return_78,
ap_return_79,
ap_return_80,
ap_return_81,
ap_return_82,
ap_return_83,
ap_return_84,
ap_return_85,
ap_return_86,
ap_return_87,
ap_return_88,
ap_return_89,
ap_return_90,
ap_return_91,
ap_return_92,
ap_return_93,
ap_return_94,
ap_return_95,
ap_return_96,
ap_return_97,
ap_return_98,
ap_return_99,
ap_return_100,
ap_return_101,
ap_return_102,
ap_return_103,
ap_return_104,
ap_return_105,
ap_return_106,
ap_return_107,
ap_return_108,
ap_return_109,
ap_return_110,
ap_return_111,
ap_return_112,
ap_return_113,
ap_return_114,
ap_return_115,
ap_return_116,
ap_return_117,
ap_return_118,
ap_return_119,
ap_return_120,
ap_return_121,
ap_return_122,
ap_return_123,
ap_return_124,
ap_return_125,
ap_return_126,
ap_return_127,
ap_return_128,
ap_return_129,
ap_return_130,
ap_return_131,
ap_return_132,
ap_return_133,
ap_return_134,
ap_return_135,
ap_return_136,
ap_return_137,
ap_return_138,
ap_return_139,
ap_return_140,
ap_return_141,
ap_return_142,
ap_return_143,
ap_return_144,
ap_return_145,
ap_return_146,
ap_return_147,
ap_return_148,
ap_return_149,
ap_return_150,
ap_return_151,
ap_return_152,
ap_return_153,
ap_return_154,
ap_return_155,
ap_return_156,
ap_return_157,
ap_return_158,
ap_return_159,
ap_return_160,
ap_return_161,
ap_return_162,
ap_return_163,
ap_return_164,
ap_return_165,
ap_return_166,
ap_return_167,
ap_return_168,
ap_return_169,
ap_return_170,
ap_return_171,
ap_return_172,
ap_return_173,
ap_return_174,
ap_return_175,
ap_return_176,
ap_return_177,
ap_return_178,
ap_return_179,
ap_return_180,
ap_return_181,
ap_return_182,
ap_return_183,
ap_return_184,
ap_return_185,
ap_return_186,
ap_return_187,
ap_return_188,
ap_return_189,
ap_return_190,
ap_return_191,
ap_return_192,
ap_return_193,
ap_return_194,
ap_return_195,
ap_return_196,
ap_return_197,
ap_return_198,
ap_return_199,
ap_return_200,
ap_return_201,
ap_return_202,
ap_return_203,
ap_return_204,
ap_return_205,
ap_return_206,
ap_return_207,
ap_return_208,
ap_return_209,
ap_return_210,
ap_return_211,
ap_return_212,
ap_return_213,
ap_return_214,
ap_return_215,
ap_return_216,
ap_return_217,
ap_return_218,
ap_return_219,
ap_return_220,
ap_return_221,
ap_return_222,
ap_return_223,
ap_return_224,
ap_return_225,
ap_return_226,
ap_return_227,
ap_return_228,
ap_return_229,
ap_return_230,
ap_return_231,
ap_return_232,
ap_return_233,
ap_return_234,
ap_return_235,
ap_return_236,
ap_return_237,
ap_return_238,
ap_return_239,
ap_return_240,
ap_return_241,
ap_return_242,
ap_return_243,
ap_return_244,
ap_return_245,
ap_return_246,
ap_return_247,
ap_return_248,
ap_return_249,
ap_return_250,
ap_return_251,
ap_return_252,
ap_return_253,
ap_return_254,
ap_return_255,
ap_return_256,
ap_return_257,
ap_return_258,
ap_return_259,
ap_return_260,
ap_return_261,
ap_return_262,
ap_return_263,
ap_return_264,
ap_return_265,
ap_return_266,
ap_return_267
);
input [11:0] primitive11_0_params_V_read;
input [11:0] primitive11_1_params_V_read;
input [11:0] primitive11_2_params_V_read;
input [11:0] primitive11_3_params_V_read;
input [11:0] primitive11_4_params_V_read;
input [11:0] primitive11_5_params_V_read;
input [5:0] primitive11_0_th_mem_V_read;
input [5:0] primitive11_1_th_mem_V_read;
input [5:0] primitive11_2_th_mem_V_read;
input [5:0] primitive11_3_th_mem_V_read;
input [5:0] primitive11_4_th_mem_V_read;
input [5:0] primitive11_5_th_mem_V_read;
input [5:0] primitive11_6_th_mem_V_read;
input [5:0] primitive11_7_th_mem_V_read;
input [5:0] primitive11_8_th_mem_V_read;
input [5:0] primitive11_9_th_mem_V_read;
input [5:0] primitive11_10_th_mem_V_read;
input [5:0] primitive11_11_th_mem_V_read;
input [5:0] primitive11_12_th_mem_V_read;
input [5:0] primitive11_13_th_mem_V_read;
input [5:0] primitive11_14_th_mem_V_read;
input [5:0] primitive11_15_th_mem_V_read;
input [5:0] primitive11_16_th_mem_V_read;
input [5:0] primitive11_17_th_mem_V_read;
input [5:0] primitive11_18_th_mem_V_read;
input [5:0] primitive11_19_th_mem_V_read;
input [5:0] primitive11_20_th_mem_V_read;
input [5:0] primitive11_21_th_mem_V_read;
input [5:0] primitive11_22_th_mem_V_read;
input [5:0] primitive11_23_th_mem_V_read;
input [5:0] primitive11_24_th_mem_V_read;
input [5:0] primitive11_25_th_mem_V_read;
input [5:0] primitive11_26_th_mem_V_read;
input [5:0] primitive11_27_th_mem_V_read;
input [5:0] primitive11_28_th_mem_V_read;
input [5:0] primitive11_29_th_mem_V_read;
input [5:0] primitive11_30_th_mem_V_read;
input [5:0] primitive11_31_th_mem_V_read;
input [5:0] primitive11_32_th_mem_V_read;
input [5:0] primitive11_33_th_mem_V_read;
input [5:0] primitive11_34_th_mem_V_read;
input [5:0] primitive11_35_th_mem_V_read;
input [5:0] primitive11_36_th_mem_V_read;
input [5:0] primitive11_37_th_mem_V_read;
input [5:0] primitive11_38_th_mem_V_read;
input [5:0] primitive11_39_th_mem_V_read;
input [5:0] primitive11_40_th_mem_V_read;
input [5:0] primitive11_41_th_mem_V_read;
input [5:0] primitive11_42_th_mem_V_read;
input [5:0] primitive11_43_th_mem_V_read;
input [5:0] primitive11_44_th_mem_V_read;
input [5:0] primitive11_45_th_mem_V_read;
input [5:0] primitive11_46_th_mem_V_read;
input [5:0] primitive11_47_th_mem_V_read;
input [5:0] primitive11_48_th_mem_V_read;
input [5:0] primitive11_49_th_mem_V_read;
input [5:0] primitive11_50_th_mem_V_read;
input [5:0] primitive11_51_th_mem_V_read;
input [5:0] primitive11_52_th_mem_V_read;
input [5:0] primitive11_53_th_mem_V_read;
input [5:0] primitive11_54_th_mem_V_read;
input [5:0] primitive11_55_th_mem_V_read;
input [5:0] primitive11_56_th_mem_V_read;
input [5:0] primitive11_57_th_mem_V_read;
input [5:0] primitive11_58_th_mem_V_read;
input [5:0] primitive11_59_th_mem_V_read;
input [5:0] primitive11_60_th_mem_V_read;
input [5:0] primitive11_61_th_mem_V_read;
input [5:0] primitive11_62_th_mem_V_read;
input [5:0] primitive11_63_th_mem_V_read;
input [5:0] primitive11_64_th_mem_V_read;
input [5:0] primitive11_65_th_mem_V_read;
input [5:0] primitive11_66_th_mem_V_read;
input [5:0] primitive11_67_th_mem_V_read;
input [5:0] primitive11_68_th_mem_V_read;
input [5:0] primitive11_69_th_mem_V_read;
input [5:0] primitive11_70_th_mem_V_read;
input [5:0] primitive11_71_th_mem_V_read;
input [5:0] primitive11_72_th_mem_V_read;
input [5:0] primitive11_73_th_mem_V_read;
input [5:0] primitive11_74_th_mem_V_read;
input [5:0] primitive11_75_th_mem_V_read;
input [5:0] primitive11_76_th_mem_V_read;
input [5:0] primitive11_77_th_mem_V_read;
input [5:0] primitive11_78_th_mem_V_read;
input [5:0] primitive11_79_th_mem_V_read;
input [5:0] primitive11_80_th_mem_V_read;
input [5:0] primitive11_81_th_mem_V_read;
input [5:0] primitive11_82_th_mem_V_read;
input [5:0] primitive11_83_th_mem_V_read;
input [5:0] primitive11_84_th_mem_V_read;
input [5:0] primitive11_85_th_mem_V_read;
input [5:0] primitive11_86_th_mem_V_read;
input [5:0] primitive11_87_th_mem_V_read;
input [5:0] primitive11_88_th_mem_V_read;
input [5:0] primitive11_89_th_mem_V_read;
input [5:0] primitive11_90_th_mem_V_read;
input [5:0] primitive11_91_th_mem_V_read;
input [5:0] primitive11_92_th_mem_V_read;
input [5:0] primitive11_93_th_mem_V_read;
input [5:0] primitive11_94_th_mem_V_read;
input [5:0] primitive11_95_th_mem_V_read;
input [5:0] primitive11_96_th_mem_V_read;
input [5:0] primitive11_97_th_mem_V_read;
input [5:0] primitive11_98_th_mem_V_read;
input [5:0] primitive11_99_th_mem_V_read;
input [5:0] primitive11_100_th_mem_V_read;
input [5:0] primitive11_101_th_mem_V_read;
input [5:0] primitive11_102_th_mem_V_read;
input [5:0] primitive11_103_th_mem_V_read;
input [5:0] primitive11_104_th_mem_V_read;
input [5:0] primitive11_105_th_mem_V_read;
input [5:0] primitive11_106_th_mem_V_read;
input [5:0] primitive11_107_th_mem_V_read;
input [5:0] primitive11_108_th_mem_V_read;
input [5:0] primitive11_109_th_mem_V_read;
input [5:0] primitive11_110_th_mem_V_read;
input [5:0] primitive11_111_th_mem_V_read;
input [5:0] primitive11_112_th_mem_V_read;
input [5:0] primitive11_113_th_mem_V_read;
input [5:0] primitive11_114_th_mem_V_read;
input [5:0] primitive11_115_th_mem_V_read;
input [5:0] primitive11_116_th_mem_V_read;
input [5:0] primitive11_117_th_mem_V_read;
input [5:0] primitive11_118_th_mem_V_read;
input [5:0] primitive11_119_th_mem_V_read;
input [5:0] primitive11_120_th_mem_V_read;
input [5:0] primitive11_121_th_mem_V_read;
input [5:0] primitive11_122_th_mem_V_read;
input [5:0] primitive11_123_th_mem_V_read;
input [5:0] primitive11_124_th_mem_V_read;
input [5:0] primitive11_125_th_mem_V_read;
input [5:0] primitive11_126_th_mem_V_read;
input [5:0] primitive11_127_th_mem_V_read;
input [3:0] primitive11_0_th_corr_mem_V_read;
input [3:0] primitive11_1_th_corr_mem_V_read;
input [3:0] primitive11_2_th_corr_mem_V_read;
input [3:0] primitive11_3_th_corr_mem_V_read;
input [3:0] primitive11_4_th_corr_mem_V_read;
input [3:0] primitive11_5_th_corr_mem_V_read;
input [3:0] primitive11_6_th_corr_mem_V_read;
input [3:0] primitive11_7_th_corr_mem_V_read;
input [3:0] primitive11_8_th_corr_mem_V_read;
input [3:0] primitive11_9_th_corr_mem_V_read;
input [3:0] primitive11_10_th_corr_mem_V_read;
input [3:0] primitive11_11_th_corr_mem_V_read;
input [3:0] primitive11_12_th_corr_mem_V_read;
input [3:0] primitive11_13_th_corr_mem_V_read;
input [3:0] primitive11_14_th_corr_mem_V_read;
input [3:0] primitive11_15_th_corr_mem_V_read;
input [3:0] primitive11_16_th_corr_mem_V_read;
input [3:0] primitive11_17_th_corr_mem_V_read;
input [3:0] primitive11_18_th_corr_mem_V_read;
input [3:0] primitive11_19_th_corr_mem_V_read;
input [3:0] primitive11_20_th_corr_mem_V_read;
input [3:0] primitive11_21_th_corr_mem_V_read;
input [3:0] primitive11_22_th_corr_mem_V_read;
input [3:0] primitive11_23_th_corr_mem_V_read;
input [3:0] primitive11_24_th_corr_mem_V_read;
input [3:0] primitive11_25_th_corr_mem_V_read;
input [3:0] primitive11_26_th_corr_mem_V_read;
input [3:0] primitive11_27_th_corr_mem_V_read;
input [3:0] primitive11_28_th_corr_mem_V_read;
input [3:0] primitive11_29_th_corr_mem_V_read;
input [3:0] primitive11_30_th_corr_mem_V_read;
input [3:0] primitive11_31_th_corr_mem_V_read;
input [3:0] primitive11_32_th_corr_mem_V_read;
input [3:0] primitive11_33_th_corr_mem_V_read;
input [3:0] primitive11_34_th_corr_mem_V_read;
input [3:0] primitive11_35_th_corr_mem_V_read;
input [3:0] primitive11_36_th_corr_mem_V_read;
input [3:0] primitive11_37_th_corr_mem_V_read;
input [3:0] primitive11_38_th_corr_mem_V_read;
input [3:0] primitive11_39_th_corr_mem_V_read;
input [3:0] primitive11_40_th_corr_mem_V_read;
input [3:0] primitive11_41_th_corr_mem_V_read;
input [3:0] primitive11_42_th_corr_mem_V_read;
input [3:0] primitive11_43_th_corr_mem_V_read;
input [3:0] primitive11_44_th_corr_mem_V_read;
input [3:0] primitive11_45_th_corr_mem_V_read;
input [3:0] primitive11_46_th_corr_mem_V_read;
input [3:0] primitive11_47_th_corr_mem_V_read;
input [3:0] primitive11_48_th_corr_mem_V_read;
input [3:0] primitive11_49_th_corr_mem_V_read;
input [3:0] primitive11_50_th_corr_mem_V_read;
input [3:0] primitive11_51_th_corr_mem_V_read;
input [3:0] primitive11_52_th_corr_mem_V_read;
input [3:0] primitive11_53_th_corr_mem_V_read;
input [3:0] primitive11_54_th_corr_mem_V_read;
input [3:0] primitive11_55_th_corr_mem_V_read;
input [3:0] primitive11_56_th_corr_mem_V_read;
input [3:0] primitive11_57_th_corr_mem_V_read;
input [3:0] primitive11_58_th_corr_mem_V_read;
input [3:0] primitive11_59_th_corr_mem_V_read;
input [3:0] primitive11_60_th_corr_mem_V_read;
input [3:0] primitive11_61_th_corr_mem_V_read;
input [3:0] primitive11_62_th_corr_mem_V_read;
input [3:0] primitive11_63_th_corr_mem_V_read;
input [3:0] primitive11_64_th_corr_mem_V_read;
input [3:0] primitive11_65_th_corr_mem_V_read;
input [3:0] primitive11_66_th_corr_mem_V_read;
input [3:0] primitive11_67_th_corr_mem_V_read;
input [3:0] primitive11_68_th_corr_mem_V_read;
input [3:0] primitive11_69_th_corr_mem_V_read;
input [3:0] primitive11_70_th_corr_mem_V_read;
input [3:0] primitive11_71_th_corr_mem_V_read;
input [3:0] primitive11_72_th_corr_mem_V_read;
input [3:0] primitive11_73_th_corr_mem_V_read;
input [3:0] primitive11_74_th_corr_mem_V_read;
input [3:0] primitive11_75_th_corr_mem_V_read;
input [3:0] primitive11_76_th_corr_mem_V_read;
input [3:0] primitive11_77_th_corr_mem_V_read;
input [3:0] primitive11_78_th_corr_mem_V_read;
input [3:0] primitive11_79_th_corr_mem_V_read;
input [3:0] primitive11_80_th_corr_mem_V_read;
input [3:0] primitive11_81_th_corr_mem_V_read;
input [3:0] primitive11_82_th_corr_mem_V_read;
input [3:0] primitive11_83_th_corr_mem_V_read;
input [3:0] primitive11_84_th_corr_mem_V_read;
input [3:0] primitive11_85_th_corr_mem_V_read;
input [3:0] primitive11_86_th_corr_mem_V_read;
input [3:0] primitive11_87_th_corr_mem_V_read;
input [3:0] primitive11_88_th_corr_mem_V_read;
input [3:0] primitive11_89_th_corr_mem_V_read;
input [3:0] primitive11_90_th_corr_mem_V_read;
input [3:0] primitive11_91_th_corr_mem_V_read;
input [3:0] primitive11_92_th_corr_mem_V_read;
input [3:0] primitive11_93_th_corr_mem_V_read;
input [3:0] primitive11_94_th_corr_mem_V_read;
input [3:0] primitive11_95_th_corr_mem_V_read;
input [3:0] primitive11_96_th_corr_mem_V_read;
input [3:0] primitive11_97_th_corr_mem_V_read;
input [3:0] primitive11_98_th_corr_mem_V_read;
input [3:0] primitive11_99_th_corr_mem_V_read;
input [3:0] primitive11_100_th_corr_mem_V_read;
input [3:0] primitive11_101_th_corr_mem_V_read;
input [3:0] primitive11_102_th_corr_mem_V_read;
input [3:0] primitive11_103_th_corr_mem_V_read;
input [3:0] primitive11_104_th_corr_mem_V_read;
input [3:0] primitive11_105_th_corr_mem_V_read;
input [3:0] primitive11_106_th_corr_mem_V_read;
input [3:0] primitive11_107_th_corr_mem_V_read;
input [3:0] primitive11_108_th_corr_mem_V_read;
input [3:0] primitive11_109_th_corr_mem_V_read;
input [3:0] primitive11_110_th_corr_mem_V_read;
input [3:0] primitive11_111_th_corr_mem_V_read;
input [3:0] primitive11_112_th_corr_mem_V_read;
input [3:0] primitive11_113_th_corr_mem_V_read;
input [3:0] primitive11_114_th_corr_mem_V_read;
input [3:0] primitive11_115_th_corr_mem_V_read;
input [3:0] primitive11_116_th_corr_mem_V_read;
input [3:0] primitive11_117_th_corr_mem_V_read;
input [3:0] primitive11_118_th_corr_mem_V_read;
input [3:0] primitive11_119_th_corr_mem_V_read;
input [3:0] primitive11_120_th_corr_mem_V_read;
input [3:0] primitive11_121_th_corr_mem_V_read;
input [3:0] primitive11_122_th_corr_mem_V_read;
input [3:0] primitive11_123_th_corr_mem_V_read;
input [3:0] primitive11_124_th_corr_mem_V_read;
input [3:0] primitive11_125_th_corr_mem_V_read;
input [3:0] primitive11_126_th_corr_mem_V_read;
input [3:0] primitive11_127_th_corr_mem_V_read;
input [3:0] quality_0_V_read;
input [3:0] quality_1_V_read;
input [6:0] wiregroup_0_V_read;
input [6:0] wiregroup_1_V_read;
input [7:0] hstrip_0_V_read;
input [7:0] hstrip_1_V_read;
input [3:0] clctpat_0_V_read;
input [3:0] clctpat_1_V_read;
input [11:0] r_in_V;
input [0:0] we_V;
input [1:0] sel_V;
input [6:0] addr_V;
input [0:0] endcap_V;
output [2:0] ap_return_0;
output [43:0] ap_return_1;
output [11:0] ap_return_2;
output [11:0] ap_return_3;
output [11:0] ap_return_4;
output [11:0] ap_return_5;
output [11:0] ap_return_6;
output [11:0] ap_return_7;
output [11:0] ap_return_8;
output [11:0] ap_return_9;
output [3:0] ap_return_10;
output [3:0] ap_return_11;
output [5:0] ap_return_12;
output [5:0] ap_return_13;
output [5:0] ap_return_14;
output [5:0] ap_return_15;
output [5:0] ap_return_16;
output [5:0] ap_return_17;
output [5:0] ap_return_18;
output [5:0] ap_return_19;
output [5:0] ap_return_20;
output [5:0] ap_return_21;
output [5:0] ap_return_22;
output [5:0] ap_return_23;
output [5:0] ap_return_24;
output [5:0] ap_return_25;
output [5:0] ap_return_26;
output [5:0] ap_return_27;
output [5:0] ap_return_28;
output [5:0] ap_return_29;
output [5:0] ap_return_30;
output [5:0] ap_return_31;
output [5:0] ap_return_32;
output [5:0] ap_return_33;
output [5:0] ap_return_34;
output [5:0] ap_return_35;
output [5:0] ap_return_36;
output [5:0] ap_return_37;
output [5:0] ap_return_38;
output [5:0] ap_return_39;
output [5:0] ap_return_40;
output [5:0] ap_return_41;
output [5:0] ap_return_42;
output [5:0] ap_return_43;
output [5:0] ap_return_44;
output [5:0] ap_return_45;
output [5:0] ap_return_46;
output [5:0] ap_return_47;
output [5:0] ap_return_48;
output [5:0] ap_return_49;
output [5:0] ap_return_50;
output [5:0] ap_return_51;
output [5:0] ap_return_52;
output [5:0] ap_return_53;
output [5:0] ap_return_54;
output [5:0] ap_return_55;
output [5:0] ap_return_56;
output [5:0] ap_return_57;
output [5:0] ap_return_58;
output [5:0] ap_return_59;
output [5:0] ap_return_60;
output [5:0] ap_return_61;
output [5:0] ap_return_62;
output [5:0] ap_return_63;
output [5:0] ap_return_64;
output [5:0] ap_return_65;
output [5:0] ap_return_66;
output [5:0] ap_return_67;
output [5:0] ap_return_68;
output [5:0] ap_return_69;
output [5:0] ap_return_70;
output [5:0] ap_return_71;
output [5:0] ap_return_72;
output [5:0] ap_return_73;
output [5:0] ap_return_74;
output [5:0] ap_return_75;
output [5:0] ap_return_76;
output [5:0] ap_return_77;
output [5:0] ap_return_78;
output [5:0] ap_return_79;
output [5:0] ap_return_80;
output [5:0] ap_return_81;
output [5:0] ap_return_82;
output [5:0] ap_return_83;
output [5:0] ap_return_84;
output [5:0] ap_return_85;
output [5:0] ap_return_86;
output [5:0] ap_return_87;
output [5:0] ap_return_88;
output [5:0] ap_return_89;
output [5:0] ap_return_90;
output [5:0] ap_return_91;
output [5:0] ap_return_92;
output [5:0] ap_return_93;
output [5:0] ap_return_94;
output [5:0] ap_return_95;
output [5:0] ap_return_96;
output [5:0] ap_return_97;
output [5:0] ap_return_98;
output [5:0] ap_return_99;
output [5:0] ap_return_100;
output [5:0] ap_return_101;
output [5:0] ap_return_102;
output [5:0] ap_return_103;
output [5:0] ap_return_104;
output [5:0] ap_return_105;
output [5:0] ap_return_106;
output [5:0] ap_return_107;
output [5:0] ap_return_108;
output [5:0] ap_return_109;
output [5:0] ap_return_110;
output [5:0] ap_return_111;
output [5:0] ap_return_112;
output [5:0] ap_return_113;
output [5:0] ap_return_114;
output [5:0] ap_return_115;
output [5:0] ap_return_116;
output [5:0] ap_return_117;
output [5:0] ap_return_118;
output [5:0] ap_return_119;
output [5:0] ap_return_120;
output [5:0] ap_return_121;
output [5:0] ap_return_122;
output [5:0] ap_return_123;
output [5:0] ap_return_124;
output [5:0] ap_return_125;
output [5:0] ap_return_126;
output [5:0] ap_return_127;
output [5:0] ap_return_128;
output [5:0] ap_return_129;
output [5:0] ap_return_130;
output [5:0] ap_return_131;
output [5:0] ap_return_132;
output [5:0] ap_return_133;
output [5:0] ap_return_134;
output [5:0] ap_return_135;
output [5:0] ap_return_136;
output [5:0] ap_return_137;
output [5:0] ap_return_138;
output [5:0] ap_return_139;
output [3:0] ap_return_140;
output [3:0] ap_return_141;
output [3:0] ap_return_142;
output [3:0] ap_return_143;
output [3:0] ap_return_144;
output [3:0] ap_return_145;
output [3:0] ap_return_146;
output [3:0] ap_return_147;
output [3:0] ap_return_148;
output [3:0] ap_return_149;
output [3:0] ap_return_150;
output [3:0] ap_return_151;
output [3:0] ap_return_152;
output [3:0] ap_return_153;
output [3:0] ap_return_154;
output [3:0] ap_return_155;
output [3:0] ap_return_156;
output [3:0] ap_return_157;
output [3:0] ap_return_158;
output [3:0] ap_return_159;
output [3:0] ap_return_160;
output [3:0] ap_return_161;
output [3:0] ap_return_162;
output [3:0] ap_return_163;
output [3:0] ap_return_164;
output [3:0] ap_return_165;
output [3:0] ap_return_166;
output [3:0] ap_return_167;
output [3:0] ap_return_168;
output [3:0] ap_return_169;
output [3:0] ap_return_170;
output [3:0] ap_return_171;
output [3:0] ap_return_172;
output [3:0] ap_return_173;
output [3:0] ap_return_174;
output [3:0] ap_return_175;
output [3:0] ap_return_176;
output [3:0] ap_return_177;
output [3:0] ap_return_178;
output [3:0] ap_return_179;
output [3:0] ap_return_180;
output [3:0] ap_return_181;
output [3:0] ap_return_182;
output [3:0] ap_return_183;
output [3:0] ap_return_184;
output [3:0] ap_return_185;
output [3:0] ap_return_186;
output [3:0] ap_return_187;
output [3:0] ap_return_188;
output [3:0] ap_return_189;
output [3:0] ap_return_190;
output [3:0] ap_return_191;
output [3:0] ap_return_192;
output [3:0] ap_return_193;
output [3:0] ap_return_194;
output [3:0] ap_return_195;
output [3:0] ap_return_196;
output [3:0] ap_return_197;
output [3:0] ap_return_198;
output [3:0] ap_return_199;
output [3:0] ap_return_200;
output [3:0] ap_return_201;
output [3:0] ap_return_202;
output [3:0] ap_return_203;
output [3:0] ap_return_204;
output [3:0] ap_return_205;
output [3:0] ap_return_206;
output [3:0] ap_return_207;
output [3:0] ap_return_208;
output [3:0] ap_return_209;
output [3:0] ap_return_210;
output [3:0] ap_return_211;
output [3:0] ap_return_212;
output [3:0] ap_return_213;
output [3:0] ap_return_214;
output [3:0] ap_return_215;
output [3:0] ap_return_216;
output [3:0] ap_return_217;
output [3:0] ap_return_218;
output [3:0] ap_return_219;
output [3:0] ap_return_220;
output [3:0] ap_return_221;
output [3:0] ap_return_222;
output [3:0] ap_return_223;
output [3:0] ap_return_224;
output [3:0] ap_return_225;
output [3:0] ap_return_226;
output [3:0] ap_return_227;
output [3:0] ap_return_228;
output [3:0] ap_return_229;
output [3:0] ap_return_230;
output [3:0] ap_return_231;
output [3:0] ap_return_232;
output [3:0] ap_return_233;
output [3:0] ap_return_234;
output [3:0] ap_return_235;
output [3:0] ap_return_236;
output [3:0] ap_return_237;
output [3:0] ap_return_238;
output [3:0] ap_return_239;
output [3:0] ap_return_240;
output [3:0] ap_return_241;
output [3:0] ap_return_242;
output [3:0] ap_return_243;
output [3:0] ap_return_244;
output [3:0] ap_return_245;
output [3:0] ap_return_246;
output [3:0] ap_return_247;
output [3:0] ap_return_248;
output [3:0] ap_return_249;
output [3:0] ap_return_250;
output [3:0] ap_return_251;
output [3:0] ap_return_252;
output [3:0] ap_return_253;
output [3:0] ap_return_254;
output [3:0] ap_return_255;
output [3:0] ap_return_256;
output [3:0] ap_return_257;
output [3:0] ap_return_258;
output [3:0] ap_return_259;
output [3:0] ap_return_260;
output [3:0] ap_return_261;
output [3:0] ap_return_262;
output [3:0] ap_return_263;
output [3:0] ap_return_264;
output [3:0] ap_return_265;
output [3:0] ap_return_266;
output [3:0] ap_return_267;
wire [11:0] call_ret1_sp_mem11_fu_4922_ap_return_0;
wire [11:0] call_ret1_sp_mem11_fu_4922_ap_return_1;
wire [11:0] call_ret1_sp_mem11_fu_4922_ap_return_2;
wire [11:0] call_ret1_sp_mem11_fu_4922_ap_return_3;
wire [11:0] call_ret1_sp_mem11_fu_4922_ap_return_4;
wire [11:0] call_ret1_sp_mem11_fu_4922_ap_return_5;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_6;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_7;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_8;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_9;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_10;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_11;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_12;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_13;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_14;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_15;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_16;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_17;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_18;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_19;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_20;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_21;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_22;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_23;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_24;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_25;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_26;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_27;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_28;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_29;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_30;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_31;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_32;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_33;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_34;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_35;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_36;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_37;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_38;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_39;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_40;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_41;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_42;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_43;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_44;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_45;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_46;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_47;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_48;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_49;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_50;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_51;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_52;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_53;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_54;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_55;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_56;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_57;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_58;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_59;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_60;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_61;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_62;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_63;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_64;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_65;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_66;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_67;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_68;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_69;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_70;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_71;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_72;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_73;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_74;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_75;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_76;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_77;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_78;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_79;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_80;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_81;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_82;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_83;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_84;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_85;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_86;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_87;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_88;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_89;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_90;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_91;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_92;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_93;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_94;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_95;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_96;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_97;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_98;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_99;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_100;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_101;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_102;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_103;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_104;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_105;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_106;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_107;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_108;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_109;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_110;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_111;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_112;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_113;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_114;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_115;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_116;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_117;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_118;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_119;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_120;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_121;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_122;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_123;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_124;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_125;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_126;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_127;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_128;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_129;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_130;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_131;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_132;
wire [5:0] call_ret1_sp_mem11_fu_4922_ap_return_133;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_134;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_135;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_136;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_137;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_138;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_139;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_140;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_141;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_142;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_143;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_144;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_145;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_146;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_147;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_148;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_149;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_150;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_151;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_152;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_153;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_154;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_155;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_156;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_157;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_158;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_159;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_160;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_161;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_162;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_163;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_164;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_165;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_166;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_167;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_168;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_169;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_170;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_171;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_172;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_173;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_174;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_175;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_176;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_177;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_178;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_179;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_180;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_181;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_182;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_183;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_184;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_185;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_186;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_187;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_188;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_189;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_190;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_191;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_192;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_193;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_194;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_195;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_196;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_197;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_198;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_199;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_200;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_201;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_202;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_203;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_204;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_205;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_206;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_207;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_208;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_209;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_210;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_211;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_212;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_213;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_214;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_215;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_216;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_217;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_218;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_219;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_220;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_221;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_222;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_223;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_224;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_225;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_226;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_227;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_228;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_229;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_230;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_231;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_232;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_233;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_234;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_235;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_236;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_237;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_238;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_239;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_240;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_241;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_242;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_243;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_244;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_245;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_246;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_247;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_248;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_249;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_250;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_251;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_252;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_253;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_254;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_255;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_256;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_257;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_258;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_259;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_260;
wire [3:0] call_ret1_sp_mem11_fu_4922_ap_return_261;
wire [2:0] call_ret_sp_prim_conv11_fu_5456_ap_return_0;
wire [43:0] call_ret_sp_prim_conv11_fu_5456_ap_return_1;
wire [11:0] call_ret_sp_prim_conv11_fu_5456_ap_return_2;
wire [11:0] call_ret_sp_prim_conv11_fu_5456_ap_return_3;
wire [3:0] call_ret_sp_prim_conv11_fu_5456_ap_return_4;
wire [3:0] call_ret_sp_prim_conv11_fu_5456_ap_return_5;
reg [5:0] primitive11_6_th_mem_V_write_s_phi_fu_2245_p4;
wire [0:0] we_V_read_read_fu_610_p2;
reg [5:0] primitive11_7_th_mem_V_write_s_phi_fu_2255_p4;
reg [5:0] primitive11_5_th_mem_V_write_s_phi_fu_2265_p4;
reg [5:0] primitive11_8_th_mem_V_write_s_phi_fu_2275_p4;
reg [5:0] primitive11_9_th_mem_V_write_s_phi_fu_2285_p4;
reg [5:0] primitive11_4_th_mem_V_write_s_phi_fu_2295_p4;
reg [5:0] primitive11_10_th_mem_V_write_phi_fu_2305_p4;
reg [5:0] primitive11_11_th_mem_V_write_phi_fu_2315_p4;
reg [5:0] primitive11_3_th_mem_V_write_s_phi_fu_2325_p4;
reg [5:0] primitive11_12_th_mem_V_write_phi_fu_2335_p4;
reg [5:0] primitive11_13_th_mem_V_write_phi_fu_2345_p4;
reg [5:0] primitive11_2_th_mem_V_write_s_phi_fu_2355_p4;
reg [5:0] primitive11_14_th_mem_V_write_phi_fu_2365_p4;
reg [5:0] primitive11_15_th_mem_V_write_phi_fu_2375_p4;
reg [5:0] primitive11_1_th_mem_V_write_s_phi_fu_2385_p4;
reg [5:0] primitive11_16_th_mem_V_write_phi_fu_2395_p4;
reg [5:0] primitive11_17_th_mem_V_write_phi_fu_2405_p4;
reg [5:0] primitive11_0_th_mem_V_write_s_phi_fu_2415_p4;
reg [5:0] primitive11_18_th_mem_V_write_phi_fu_2425_p4;
reg [5:0] primitive11_19_th_mem_V_write_phi_fu_2435_p4;
reg [5:0] primitive11_31_th_mem_V_write_phi_fu_2445_p4;
reg [5:0] primitive11_32_th_mem_V_write_phi_fu_2455_p4;
reg [5:0] primitive11_30_th_mem_V_write_phi_fu_2465_p4;
reg [5:0] primitive11_33_th_mem_V_write_phi_fu_2475_p4;
reg [5:0] primitive11_34_th_mem_V_write_phi_fu_2485_p4;
reg [5:0] primitive11_29_th_mem_V_write_phi_fu_2495_p4;
reg [5:0] primitive11_35_th_mem_V_write_phi_fu_2505_p4;
reg [5:0] primitive11_36_th_mem_V_write_phi_fu_2515_p4;
reg [5:0] primitive11_28_th_mem_V_write_phi_fu_2525_p4;
reg [5:0] primitive11_37_th_mem_V_write_phi_fu_2535_p4;
reg [5:0] primitive11_38_th_mem_V_write_phi_fu_2545_p4;
reg [5:0] primitive11_27_th_mem_V_write_phi_fu_2555_p4;
reg [5:0] primitive11_39_th_mem_V_write_phi_fu_2565_p4;
reg [5:0] primitive11_40_th_mem_V_write_phi_fu_2575_p4;
reg [5:0] primitive11_26_th_mem_V_write_phi_fu_2585_p4;
reg [5:0] primitive11_41_th_mem_V_write_phi_fu_2595_p4;
reg [5:0] primitive11_42_th_mem_V_write_phi_fu_2605_p4;
reg [5:0] primitive11_25_th_mem_V_write_phi_fu_2615_p4;
reg [5:0] primitive11_43_th_mem_V_write_phi_fu_2625_p4;
reg [5:0] primitive11_44_th_mem_V_write_phi_fu_2635_p4;
reg [5:0] primitive11_24_th_mem_V_write_phi_fu_2645_p4;
reg [5:0] primitive11_45_th_mem_V_write_phi_fu_2655_p4;
reg [5:0] primitive11_46_th_mem_V_write_phi_fu_2665_p4;
reg [5:0] primitive11_23_th_mem_V_write_phi_fu_2675_p4;
reg [5:0] primitive11_47_th_mem_V_write_phi_fu_2685_p4;
reg [5:0] primitive11_48_th_mem_V_write_phi_fu_2695_p4;
reg [5:0] primitive11_22_th_mem_V_write_phi_fu_2705_p4;
reg [5:0] primitive11_49_th_mem_V_write_phi_fu_2715_p4;
reg [5:0] primitive11_50_th_mem_V_write_phi_fu_2725_p4;
reg [5:0] primitive11_21_th_mem_V_write_phi_fu_2735_p4;
reg [5:0] primitive11_51_th_mem_V_write_phi_fu_2745_p4;
reg [5:0] primitive11_52_th_mem_V_write_phi_fu_2755_p4;
reg [5:0] primitive11_20_th_mem_V_write_phi_fu_2765_p4;
reg [5:0] primitive11_53_th_mem_V_write_phi_fu_2775_p4;
reg [5:0] primitive11_65_th_mem_V_write_phi_fu_2785_p4;
reg [5:0] primitive11_64_th_mem_V_write_phi_fu_2795_p4;
reg [5:0] primitive11_66_th_mem_V_write_phi_fu_2805_p4;
reg [5:0] primitive11_67_th_mem_V_write_phi_fu_2815_p4;
reg [5:0] primitive11_63_th_mem_V_write_phi_fu_2825_p4;
reg [5:0] primitive11_68_th_mem_V_write_phi_fu_2835_p4;
reg [5:0] primitive11_69_th_mem_V_write_phi_fu_2845_p4;
reg [5:0] primitive11_62_th_mem_V_write_phi_fu_2855_p4;
reg [5:0] primitive11_70_th_mem_V_write_phi_fu_2865_p4;
reg [5:0] primitive11_71_th_mem_V_write_phi_fu_2875_p4;
reg [5:0] primitive11_61_th_mem_V_write_phi_fu_2885_p4;
reg [5:0] primitive11_72_th_mem_V_write_phi_fu_2895_p4;
reg [5:0] primitive11_73_th_mem_V_write_phi_fu_2905_p4;
reg [5:0] primitive11_60_th_mem_V_write_phi_fu_2915_p4;
reg [5:0] primitive11_74_th_mem_V_write_phi_fu_2925_p4;
reg [5:0] primitive11_75_th_mem_V_write_phi_fu_2935_p4;
reg [5:0] primitive11_59_th_mem_V_write_phi_fu_2945_p4;
reg [5:0] primitive11_76_th_mem_V_write_phi_fu_2955_p4;
reg [5:0] primitive11_77_th_mem_V_write_phi_fu_2965_p4;
reg [5:0] primitive11_58_th_mem_V_write_phi_fu_2975_p4;
reg [5:0] primitive11_78_th_mem_V_write_phi_fu_2985_p4;
reg [5:0] primitive11_79_th_mem_V_write_phi_fu_2995_p4;
reg [5:0] primitive11_57_th_mem_V_write_phi_fu_3005_p4;
reg [5:0] primitive11_80_th_mem_V_write_phi_fu_3015_p4;
reg [5:0] primitive11_81_th_mem_V_write_phi_fu_3025_p4;
reg [5:0] primitive11_56_th_mem_V_write_phi_fu_3035_p4;
reg [5:0] primitive11_82_th_mem_V_write_phi_fu_3045_p4;
reg [5:0] primitive11_83_th_mem_V_write_phi_fu_3055_p4;
reg [5:0] primitive11_55_th_mem_V_write_phi_fu_3065_p4;
reg [5:0] primitive11_84_th_mem_V_write_phi_fu_3075_p4;
reg [5:0] primitive11_85_th_mem_V_write_phi_fu_3085_p4;
reg [5:0] primitive11_54_th_mem_V_write_phi_fu_3095_p4;
reg [5:0] primitive11_86_th_mem_V_write_phi_fu_3105_p4;
reg [5:0] primitive11_98_th_mem_V_write_phi_fu_3115_p4;
reg [5:0] primitive11_99_th_mem_V_write_phi_fu_3125_p4;
reg [5:0] primitive11_97_th_mem_V_write_phi_fu_3135_p4;
reg [5:0] primitive11_100_th_mem_V_writ_phi_fu_3145_p4;
reg [5:0] primitive11_101_th_mem_V_writ_phi_fu_3155_p4;
reg [5:0] primitive11_96_th_mem_V_write_phi_fu_3165_p4;
reg [5:0] primitive11_102_th_mem_V_writ_phi_fu_3175_p4;
reg [5:0] primitive11_103_th_mem_V_writ_phi_fu_3185_p4;
reg [5:0] primitive11_95_th_mem_V_write_phi_fu_3195_p4;
reg [5:0] primitive11_104_th_mem_V_writ_phi_fu_3205_p4;
reg [5:0] primitive11_105_th_mem_V_writ_phi_fu_3215_p4;
reg [5:0] primitive11_94_th_mem_V_write_phi_fu_3225_p4;
reg [5:0] primitive11_106_th_mem_V_writ_phi_fu_3235_p4;
reg [5:0] primitive11_107_th_mem_V_writ_phi_fu_3245_p4;
reg [5:0] primitive11_93_th_mem_V_write_phi_fu_3255_p4;
reg [5:0] primitive11_108_th_mem_V_writ_phi_fu_3265_p4;
reg [5:0] primitive11_109_th_mem_V_writ_phi_fu_3275_p4;
reg [5:0] primitive11_92_th_mem_V_write_phi_fu_3285_p4;
reg [5:0] primitive11_110_th_mem_V_writ_phi_fu_3295_p4;
reg [5:0] primitive11_111_th_mem_V_writ_phi_fu_3305_p4;
reg [5:0] primitive11_91_th_mem_V_write_phi_fu_3315_p4;
reg [5:0] primitive11_112_th_mem_V_writ_phi_fu_3325_p4;
reg [5:0] primitive11_113_th_mem_V_writ_phi_fu_3335_p4;
reg [5:0] primitive11_90_th_mem_V_write_phi_fu_3345_p4;
reg [5:0] primitive11_114_th_mem_V_writ_phi_fu_3355_p4;
reg [5:0] primitive11_115_th_mem_V_writ_phi_fu_3365_p4;
reg [5:0] primitive11_89_th_mem_V_write_phi_fu_3375_p4;
reg [5:0] primitive11_116_th_mem_V_writ_phi_fu_3385_p4;
reg [5:0] primitive11_117_th_mem_V_writ_phi_fu_3395_p4;
reg [5:0] primitive11_88_th_mem_V_write_phi_fu_3405_p4;
reg [5:0] primitive11_118_th_mem_V_writ_phi_fu_3415_p4;
reg [5:0] primitive11_119_th_mem_V_writ_phi_fu_3425_p4;
reg [5:0] primitive11_87_th_mem_V_write_phi_fu_3435_p4;
reg [5:0] primitive11_120_th_mem_V_writ_phi_fu_3445_p4;
reg [3:0] primitive11_4_th_corr_mem_V_w_phi_fu_3455_p4;
reg [3:0] primitive11_5_th_corr_mem_V_w_phi_fu_3465_p4;
reg [3:0] primitive11_3_th_corr_mem_V_w_phi_fu_3475_p4;
reg [3:0] primitive11_6_th_corr_mem_V_w_phi_fu_3485_p4;
reg [3:0] primitive11_7_th_corr_mem_V_w_phi_fu_3495_p4;
reg [3:0] primitive11_2_th_corr_mem_V_w_phi_fu_3505_p4;
reg [3:0] primitive11_8_th_corr_mem_V_w_phi_fu_3515_p4;
reg [3:0] primitive11_9_th_corr_mem_V_w_phi_fu_3525_p4;
reg [3:0] primitive11_1_th_corr_mem_V_w_phi_fu_3535_p4;
reg [3:0] primitive11_10_th_corr_mem_V_s_phi_fu_3545_p4;
reg [3:0] primitive11_11_th_corr_mem_V_s_phi_fu_3555_p4;
reg [3:0] primitive11_0_th_corr_mem_V_w_phi_fu_3565_p4;
reg [3:0] primitive11_12_th_corr_mem_V_s_phi_fu_3575_p4;
reg [3:0] primitive11_13_th_corr_mem_V_s_phi_fu_3585_p4;
reg [5:0] primitive11_127_th_mem_V_writ_phi_fu_3595_p4;
reg [3:0] primitive11_14_th_corr_mem_V_s_phi_fu_3605_p4;
reg [3:0] primitive11_15_th_corr_mem_V_s_phi_fu_3615_p4;
reg [5:0] primitive11_126_th_mem_V_writ_phi_fu_3625_p4;
reg [3:0] primitive11_16_th_corr_mem_V_s_phi_fu_3635_p4;
reg [3:0] primitive11_17_th_corr_mem_V_s_phi_fu_3645_p4;
reg [5:0] primitive11_125_th_mem_V_writ_phi_fu_3655_p4;
reg [3:0] primitive11_18_th_corr_mem_V_s_phi_fu_3665_p4;
reg [3:0] primitive11_19_th_corr_mem_V_s_phi_fu_3675_p4;
reg [5:0] primitive11_124_th_mem_V_writ_phi_fu_3685_p4;
reg [3:0] primitive11_20_th_corr_mem_V_s_phi_fu_3695_p4;
reg [3:0] primitive11_21_th_corr_mem_V_s_phi_fu_3705_p4;
reg [5:0] primitive11_123_th_mem_V_writ_phi_fu_3715_p4;
reg [3:0] primitive11_22_th_corr_mem_V_s_phi_fu_3725_p4;
reg [3:0] primitive11_23_th_corr_mem_V_s_phi_fu_3735_p4;
reg [5:0] primitive11_122_th_mem_V_writ_phi_fu_3745_p4;
reg [3:0] primitive11_24_th_corr_mem_V_s_phi_fu_3755_p4;
reg [3:0] primitive11_25_th_corr_mem_V_s_phi_fu_3765_p4;
reg [5:0] primitive11_121_th_mem_V_writ_phi_fu_3775_p4;
reg [3:0] primitive11_26_th_corr_mem_V_s_phi_fu_3785_p4;
reg [3:0] primitive11_38_th_corr_mem_V_s_phi_fu_3795_p4;
reg [3:0] primitive11_37_th_corr_mem_V_s_phi_fu_3805_p4;
reg [3:0] primitive11_39_th_corr_mem_V_s_phi_fu_3815_p4;
reg [3:0] primitive11_40_th_corr_mem_V_s_phi_fu_3825_p4;
reg [3:0] primitive11_36_th_corr_mem_V_s_phi_fu_3835_p4;
reg [3:0] primitive11_41_th_corr_mem_V_s_phi_fu_3845_p4;
reg [3:0] primitive11_42_th_corr_mem_V_s_phi_fu_3855_p4;
reg [3:0] primitive11_35_th_corr_mem_V_s_phi_fu_3865_p4;
reg [3:0] primitive11_43_th_corr_mem_V_s_phi_fu_3875_p4;
reg [3:0] primitive11_44_th_corr_mem_V_s_phi_fu_3885_p4;
reg [3:0] primitive11_34_th_corr_mem_V_s_phi_fu_3895_p4;
reg [3:0] primitive11_45_th_corr_mem_V_s_phi_fu_3905_p4;
reg [3:0] primitive11_46_th_corr_mem_V_s_phi_fu_3915_p4;
reg [3:0] primitive11_33_th_corr_mem_V_s_phi_fu_3925_p4;
reg [3:0] primitive11_47_th_corr_mem_V_s_phi_fu_3935_p4;
reg [3:0] primitive11_48_th_corr_mem_V_s_phi_fu_3945_p4;
reg [3:0] primitive11_32_th_corr_mem_V_s_phi_fu_3955_p4;
reg [3:0] primitive11_49_th_corr_mem_V_s_phi_fu_3965_p4;
reg [3:0] primitive11_50_th_corr_mem_V_s_phi_fu_3975_p4;
reg [3:0] primitive11_31_th_corr_mem_V_s_phi_fu_3985_p4;
reg [3:0] primitive11_51_th_corr_mem_V_s_phi_fu_3995_p4;
reg [3:0] primitive11_52_th_corr_mem_V_s_phi_fu_4005_p4;
reg [3:0] primitive11_30_th_corr_mem_V_s_phi_fu_4015_p4;
reg [3:0] primitive11_53_th_corr_mem_V_s_phi_fu_4025_p4;
reg [3:0] primitive11_54_th_corr_mem_V_s_phi_fu_4035_p4;
reg [3:0] primitive11_29_th_corr_mem_V_s_phi_fu_4045_p4;
reg [3:0] primitive11_55_th_corr_mem_V_s_phi_fu_4055_p4;
reg [3:0] primitive11_56_th_corr_mem_V_s_phi_fu_4065_p4;
reg [3:0] primitive11_28_th_corr_mem_V_s_phi_fu_4075_p4;
reg [3:0] primitive11_57_th_corr_mem_V_s_phi_fu_4085_p4;
reg [3:0] primitive11_58_th_corr_mem_V_s_phi_fu_4095_p4;
reg [3:0] primitive11_27_th_corr_mem_V_s_phi_fu_4105_p4;
reg [3:0] primitive11_59_th_corr_mem_V_s_phi_fu_4115_p4;
reg [3:0] primitive11_71_th_corr_mem_V_s_phi_fu_4125_p4;
reg [3:0] primitive11_72_th_corr_mem_V_s_phi_fu_4135_p4;
reg [3:0] primitive11_70_th_corr_mem_V_s_phi_fu_4145_p4;
reg [3:0] primitive11_73_th_corr_mem_V_s_phi_fu_4155_p4;
reg [3:0] primitive11_74_th_corr_mem_V_s_phi_fu_4165_p4;
reg [3:0] primitive11_69_th_corr_mem_V_s_phi_fu_4175_p4;
reg [3:0] primitive11_75_th_corr_mem_V_s_phi_fu_4185_p4;
reg [3:0] primitive11_76_th_corr_mem_V_s_phi_fu_4195_p4;
reg [3:0] primitive11_68_th_corr_mem_V_s_phi_fu_4205_p4;
reg [3:0] primitive11_77_th_corr_mem_V_s_phi_fu_4215_p4;
reg [3:0] primitive11_78_th_corr_mem_V_s_phi_fu_4225_p4;
reg [3:0] primitive11_67_th_corr_mem_V_s_phi_fu_4235_p4;
reg [3:0] primitive11_79_th_corr_mem_V_s_phi_fu_4245_p4;
reg [3:0] primitive11_80_th_corr_mem_V_s_phi_fu_4255_p4;
reg [3:0] primitive11_66_th_corr_mem_V_s_phi_fu_4265_p4;
reg [3:0] primitive11_81_th_corr_mem_V_s_phi_fu_4275_p4;
reg [3:0] primitive11_82_th_corr_mem_V_s_phi_fu_4285_p4;
reg [3:0] primitive11_65_th_corr_mem_V_s_phi_fu_4295_p4;
reg [3:0] primitive11_83_th_corr_mem_V_s_phi_fu_4305_p4;
reg [3:0] primitive11_84_th_corr_mem_V_s_phi_fu_4315_p4;
reg [3:0] primitive11_64_th_corr_mem_V_s_phi_fu_4325_p4;
reg [3:0] primitive11_85_th_corr_mem_V_s_phi_fu_4335_p4;
reg [3:0] primitive11_86_th_corr_mem_V_s_phi_fu_4345_p4;
reg [3:0] primitive11_63_th_corr_mem_V_s_phi_fu_4355_p4;
reg [3:0] primitive11_87_th_corr_mem_V_s_phi_fu_4365_p4;
reg [3:0] primitive11_88_th_corr_mem_V_s_phi_fu_4375_p4;
reg [3:0] primitive11_62_th_corr_mem_V_s_phi_fu_4385_p4;
reg [3:0] primitive11_89_th_corr_mem_V_s_phi_fu_4395_p4;
reg [3:0] primitive11_90_th_corr_mem_V_s_phi_fu_4405_p4;
reg [3:0] primitive11_61_th_corr_mem_V_s_phi_fu_4415_p4;
reg [3:0] primitive11_91_th_corr_mem_V_s_phi_fu_4425_p4;
reg [3:0] primitive11_92_th_corr_mem_V_s_phi_fu_4435_p4;
reg [3:0] primitive11_60_th_corr_mem_V_s_phi_fu_4445_p4;
reg [3:0] primitive11_93_th_corr_mem_V_s_phi_fu_4455_p4;
reg [3:0] primitive11_105_th_corr_mem_V_phi_fu_4465_p4;
reg [3:0] primitive11_106_th_corr_mem_V_phi_fu_4475_p4;
reg [3:0] primitive11_104_th_corr_mem_V_phi_fu_4485_p4;
reg [3:0] primitive11_107_th_corr_mem_V_phi_fu_4495_p4;
reg [3:0] primitive11_108_th_corr_mem_V_phi_fu_4505_p4;
reg [3:0] primitive11_103_th_corr_mem_V_phi_fu_4515_p4;
reg [3:0] primitive11_109_th_corr_mem_V_phi_fu_4525_p4;
reg [3:0] primitive11_110_th_corr_mem_V_phi_fu_4535_p4;
reg [3:0] primitive11_102_th_corr_mem_V_phi_fu_4545_p4;
reg [3:0] primitive11_111_th_corr_mem_V_phi_fu_4555_p4;
reg [3:0] primitive11_112_th_corr_mem_V_phi_fu_4565_p4;
reg [3:0] primitive11_101_th_corr_mem_V_phi_fu_4575_p4;
reg [3:0] primitive11_113_th_corr_mem_V_phi_fu_4585_p4;
reg [3:0] primitive11_114_th_corr_mem_V_phi_fu_4595_p4;
reg [3:0] primitive11_100_th_corr_mem_V_phi_fu_4605_p4;
reg [3:0] primitive11_115_th_corr_mem_V_phi_fu_4615_p4;
reg [3:0] primitive11_116_th_corr_mem_V_phi_fu_4625_p4;
reg [3:0] primitive11_99_th_corr_mem_V_s_phi_fu_4635_p4;
reg [3:0] primitive11_117_th_corr_mem_V_phi_fu_4645_p4;
reg [3:0] primitive11_118_th_corr_mem_V_phi_fu_4655_p4;
reg [3:0] primitive11_98_th_corr_mem_V_s_phi_fu_4665_p4;
reg [3:0] primitive11_119_th_corr_mem_V_phi_fu_4675_p4;
reg [3:0] primitive11_120_th_corr_mem_V_phi_fu_4685_p4;
reg [3:0] primitive11_97_th_corr_mem_V_s_phi_fu_4695_p4;
reg [3:0] primitive11_121_th_corr_mem_V_phi_fu_4705_p4;
reg [3:0] primitive11_122_th_corr_mem_V_phi_fu_4715_p4;
reg [3:0] primitive11_96_th_corr_mem_V_s_phi_fu_4725_p4;
reg [3:0] primitive11_123_th_corr_mem_V_phi_fu_4735_p4;
reg [3:0] primitive11_124_th_corr_mem_V_phi_fu_4745_p4;
reg [3:0] primitive11_95_th_corr_mem_V_s_phi_fu_4755_p4;
reg [3:0] primitive11_125_th_corr_mem_V_phi_fu_4765_p4;
reg [3:0] primitive11_126_th_corr_mem_V_phi_fu_4775_p4;
reg [3:0] primitive11_94_th_corr_mem_V_s_phi_fu_4785_p4;
reg [3:0] primitive11_127_th_corr_mem_V_phi_fu_4795_p4;
reg [11:0] primitive11_params_V_phi_fu_4805_p4;
reg [11:0] primitive11_params_V1_phi_fu_4815_p4;
reg [11:0] primitive11_params_V2_phi_fu_4825_p4;
reg [11:0] primitive11_params_V3_phi_fu_4835_p4;
reg [11:0] primitive11_params_V4_phi_fu_4845_p4;
reg [11:0] primitive11_params_V5_phi_fu_4855_p4;
sp_mem11 call_ret1_sp_mem11_fu_4922(
.primitive11_0_params_V_read(primitive11_0_params_V_read),
.primitive11_1_params_V_read(primitive11_1_params_V_read),
.primitive11_2_params_V_read(primitive11_2_params_V_read),
.primitive11_3_params_V_read(primitive11_3_params_V_read),
.primitive11_4_params_V_read(primitive11_4_params_V_read),
.primitive11_5_params_V_read(primitive11_5_params_V_read),
.primitive11_0_th_mem_V_read(primitive11_0_th_mem_V_read),
.primitive11_1_th_mem_V_read(primitive11_1_th_mem_V_read),
.primitive11_2_th_mem_V_read(primitive11_2_th_mem_V_read),
.primitive11_3_th_mem_V_read(primitive11_3_th_mem_V_read),
.primitive11_4_th_mem_V_read(primitive11_4_th_mem_V_read),
.primitive11_5_th_mem_V_read(primitive11_5_th_mem_V_read),
.primitive11_6_th_mem_V_read(primitive11_6_th_mem_V_read),
.primitive11_7_th_mem_V_read(primitive11_7_th_mem_V_read),
.primitive11_8_th_mem_V_read(primitive11_8_th_mem_V_read),
.primitive11_9_th_mem_V_read(primitive11_9_th_mem_V_read),
.primitive11_10_th_mem_V_read(primitive11_10_th_mem_V_read),
.primitive11_11_th_mem_V_read(primitive11_11_th_mem_V_read),
.primitive11_12_th_mem_V_read(primitive11_12_th_mem_V_read),
.primitive11_13_th_mem_V_read(primitive11_13_th_mem_V_read),
.primitive11_14_th_mem_V_read(primitive11_14_th_mem_V_read),
.primitive11_15_th_mem_V_read(primitive11_15_th_mem_V_read),
.primitive11_16_th_mem_V_read(primitive11_16_th_mem_V_read),
.primitive11_17_th_mem_V_read(primitive11_17_th_mem_V_read),
.primitive11_18_th_mem_V_read(primitive11_18_th_mem_V_read),
.primitive11_19_th_mem_V_read(primitive11_19_th_mem_V_read),
.primitive11_20_th_mem_V_read(primitive11_20_th_mem_V_read),
.primitive11_21_th_mem_V_read(primitive11_21_th_mem_V_read),
.primitive11_22_th_mem_V_read(primitive11_22_th_mem_V_read),
.primitive11_23_th_mem_V_read(primitive11_23_th_mem_V_read),
.primitive11_24_th_mem_V_read(primitive11_24_th_mem_V_read),
.primitive11_25_th_mem_V_read(primitive11_25_th_mem_V_read),
.primitive11_26_th_mem_V_read(primitive11_26_th_mem_V_read),
.primitive11_27_th_mem_V_read(primitive11_27_th_mem_V_read),
.primitive11_28_th_mem_V_read(primitive11_28_th_mem_V_read),
.primitive11_29_th_mem_V_read(primitive11_29_th_mem_V_read),
.primitive11_30_th_mem_V_read(primitive11_30_th_mem_V_read),
.primitive11_31_th_mem_V_read(primitive11_31_th_mem_V_read),
.primitive11_32_th_mem_V_read(primitive11_32_th_mem_V_read),
.primitive11_33_th_mem_V_read(primitive11_33_th_mem_V_read),
.primitive11_34_th_mem_V_read(primitive11_34_th_mem_V_read),
.primitive11_35_th_mem_V_read(primitive11_35_th_mem_V_read),
.primitive11_36_th_mem_V_read(primitive11_36_th_mem_V_read),
.primitive11_37_th_mem_V_read(primitive11_37_th_mem_V_read),
.primitive11_38_th_mem_V_read(primitive11_38_th_mem_V_read),
.primitive11_39_th_mem_V_read(primitive11_39_th_mem_V_read),
.primitive11_40_th_mem_V_read(primitive11_40_th_mem_V_read),
.primitive11_41_th_mem_V_read(primitive11_41_th_mem_V_read),
.primitive11_42_th_mem_V_read(primitive11_42_th_mem_V_read),
.primitive11_43_th_mem_V_read(primitive11_43_th_mem_V_read),
.primitive11_44_th_mem_V_read(primitive11_44_th_mem_V_read),
.primitive11_45_th_mem_V_read(primitive11_45_th_mem_V_read),
.primitive11_46_th_mem_V_read(primitive11_46_th_mem_V_read),
.primitive11_47_th_mem_V_read(primitive11_47_th_mem_V_read),
.primitive11_48_th_mem_V_read(primitive11_48_th_mem_V_read),
.primitive11_49_th_mem_V_read(primitive11_49_th_mem_V_read),
.primitive11_50_th_mem_V_read(primitive11_50_th_mem_V_read),
.primitive11_51_th_mem_V_read(primitive11_51_th_mem_V_read),
.primitive11_52_th_mem_V_read(primitive11_52_th_mem_V_read),
.primitive11_53_th_mem_V_read(primitive11_53_th_mem_V_read),
.primitive11_54_th_mem_V_read(primitive11_54_th_mem_V_read),
.primitive11_55_th_mem_V_read(primitive11_55_th_mem_V_read),
.primitive11_56_th_mem_V_read(primitive11_56_th_mem_V_read),
.primitive11_57_th_mem_V_read(primitive11_57_th_mem_V_read),
.primitive11_58_th_mem_V_read(primitive11_58_th_mem_V_read),
.primitive11_59_th_mem_V_read(primitive11_59_th_mem_V_read),
.primitive11_60_th_mem_V_read(primitive11_60_th_mem_V_read),
.primitive11_61_th_mem_V_read(primitive11_61_th_mem_V_read),
.primitive11_62_th_mem_V_read(primitive11_62_th_mem_V_read),
.primitive11_63_th_mem_V_read(primitive11_63_th_mem_V_read),
.primitive11_64_th_mem_V_read(primitive11_64_th_mem_V_read),
.primitive11_65_th_mem_V_read(primitive11_65_th_mem_V_read),
.primitive11_66_th_mem_V_read(primitive11_66_th_mem_V_read),
.primitive11_67_th_mem_V_read(primitive11_67_th_mem_V_read),
.primitive11_68_th_mem_V_read(primitive11_68_th_mem_V_read),
.primitive11_69_th_mem_V_read(primitive11_69_th_mem_V_read),
.primitive11_70_th_mem_V_read(primitive11_70_th_mem_V_read),
.primitive11_71_th_mem_V_read(primitive11_71_th_mem_V_read),
.primitive11_72_th_mem_V_read(primitive11_72_th_mem_V_read),
.primitive11_73_th_mem_V_read(primitive11_73_th_mem_V_read),
.primitive11_74_th_mem_V_read(primitive11_74_th_mem_V_read),
.primitive11_75_th_mem_V_read(primitive11_75_th_mem_V_read),
.primitive11_76_th_mem_V_read(primitive11_76_th_mem_V_read),
.primitive11_77_th_mem_V_read(primitive11_77_th_mem_V_read),
.primitive11_78_th_mem_V_read(primitive11_78_th_mem_V_read),
.primitive11_79_th_mem_V_read(primitive11_79_th_mem_V_read),
.primitive11_80_th_mem_V_read(primitive11_80_th_mem_V_read),
.primitive11_81_th_mem_V_read(primitive11_81_th_mem_V_read),
.primitive11_82_th_mem_V_read(primitive11_82_th_mem_V_read),
.primitive11_83_th_mem_V_read(primitive11_83_th_mem_V_read),
.primitive11_84_th_mem_V_read(primitive11_84_th_mem_V_read),
.primitive11_85_th_mem_V_read(primitive11_85_th_mem_V_read),
.primitive11_86_th_mem_V_read(primitive11_86_th_mem_V_read),
.primitive11_87_th_mem_V_read(primitive11_87_th_mem_V_read),
.primitive11_88_th_mem_V_read(primitive11_88_th_mem_V_read),
.primitive11_89_th_mem_V_read(primitive11_89_th_mem_V_read),
.primitive11_90_th_mem_V_read(primitive11_90_th_mem_V_read),
.primitive11_91_th_mem_V_read(primitive11_91_th_mem_V_read),
.primitive11_92_th_mem_V_read(primitive11_92_th_mem_V_read),
.primitive11_93_th_mem_V_read(primitive11_93_th_mem_V_read),
.primitive11_94_th_mem_V_read(primitive11_94_th_mem_V_read),
.primitive11_95_th_mem_V_read(primitive11_95_th_mem_V_read),
.primitive11_96_th_mem_V_read(primitive11_96_th_mem_V_read),
.primitive11_97_th_mem_V_read(primitive11_97_th_mem_V_read),
.primitive11_98_th_mem_V_read(primitive11_98_th_mem_V_read),
.primitive11_99_th_mem_V_read(primitive11_99_th_mem_V_read),
.primitive11_100_th_mem_V_read(primitive11_100_th_mem_V_read),
.primitive11_101_th_mem_V_read(primitive11_101_th_mem_V_read),
.primitive11_102_th_mem_V_read(primitive11_102_th_mem_V_read),
.primitive11_103_th_mem_V_read(primitive11_103_th_mem_V_read),
.primitive11_104_th_mem_V_read(primitive11_104_th_mem_V_read),
.primitive11_105_th_mem_V_read(primitive11_105_th_mem_V_read),
.primitive11_106_th_mem_V_read(primitive11_106_th_mem_V_read),
.primitive11_107_th_mem_V_read(primitive11_107_th_mem_V_read),
.primitive11_108_th_mem_V_read(primitive11_108_th_mem_V_read),
.primitive11_109_th_mem_V_read(primitive11_109_th_mem_V_read),
.primitive11_110_th_mem_V_read(primitive11_110_th_mem_V_read),
.primitive11_111_th_mem_V_read(primitive11_111_th_mem_V_read),
.primitive11_112_th_mem_V_read(primitive11_112_th_mem_V_read),
.primitive11_113_th_mem_V_read(primitive11_113_th_mem_V_read),
.primitive11_114_th_mem_V_read(primitive11_114_th_mem_V_read),
.primitive11_115_th_mem_V_read(primitive11_115_th_mem_V_read),
.primitive11_116_th_mem_V_read(primitive11_116_th_mem_V_read),
.primitive11_117_th_mem_V_read(primitive11_117_th_mem_V_read),
.primitive11_118_th_mem_V_read(primitive11_118_th_mem_V_read),
.primitive11_119_th_mem_V_read(primitive11_119_th_mem_V_read),
.primitive11_120_th_mem_V_read(primitive11_120_th_mem_V_read),
.primitive11_121_th_mem_V_read(primitive11_121_th_mem_V_read),
.primitive11_122_th_mem_V_read(primitive11_122_th_mem_V_read),
.primitive11_123_th_mem_V_read(primitive11_123_th_mem_V_read),
.primitive11_124_th_mem_V_read(primitive11_124_th_mem_V_read),
.primitive11_125_th_mem_V_read(primitive11_125_th_mem_V_read),
.primitive11_126_th_mem_V_read(primitive11_126_th_mem_V_read),
.primitive11_127_th_mem_V_read(primitive11_127_th_mem_V_read),
.primitive11_0_th_corr_mem_V_read(primitive11_0_th_corr_mem_V_read),
.primitive11_1_th_corr_mem_V_read(primitive11_1_th_corr_mem_V_read),
.primitive11_2_th_corr_mem_V_read(primitive11_2_th_corr_mem_V_read),
.primitive11_3_th_corr_mem_V_read(primitive11_3_th_corr_mem_V_read),
.primitive11_4_th_corr_mem_V_read(primitive11_4_th_corr_mem_V_read),
.primitive11_5_th_corr_mem_V_read(primitive11_5_th_corr_mem_V_read),
.primitive11_6_th_corr_mem_V_read(primitive11_6_th_corr_mem_V_read),
.primitive11_7_th_corr_mem_V_read(primitive11_7_th_corr_mem_V_read),
.primitive11_8_th_corr_mem_V_read(primitive11_8_th_corr_mem_V_read),
.primitive11_9_th_corr_mem_V_read(primitive11_9_th_corr_mem_V_read),
.primitive11_10_th_corr_mem_V_read(primitive11_10_th_corr_mem_V_read),
.primitive11_11_th_corr_mem_V_read(primitive11_11_th_corr_mem_V_read),
.primitive11_12_th_corr_mem_V_read(primitive11_12_th_corr_mem_V_read),
.primitive11_13_th_corr_mem_V_read(primitive11_13_th_corr_mem_V_read),
.primitive11_14_th_corr_mem_V_read(primitive11_14_th_corr_mem_V_read),
.primitive11_15_th_corr_mem_V_read(primitive11_15_th_corr_mem_V_read),
.primitive11_16_th_corr_mem_V_read(primitive11_16_th_corr_mem_V_read),
.primitive11_17_th_corr_mem_V_read(primitive11_17_th_corr_mem_V_read),
.primitive11_18_th_corr_mem_V_read(primitive11_18_th_corr_mem_V_read),
.primitive11_19_th_corr_mem_V_read(primitive11_19_th_corr_mem_V_read),
.primitive11_20_th_corr_mem_V_read(primitive11_20_th_corr_mem_V_read),
.primitive11_21_th_corr_mem_V_read(primitive11_21_th_corr_mem_V_read),
.primitive11_22_th_corr_mem_V_read(primitive11_22_th_corr_mem_V_read),
.primitive11_23_th_corr_mem_V_read(primitive11_23_th_corr_mem_V_read),
.primitive11_24_th_corr_mem_V_read(primitive11_24_th_corr_mem_V_read),
.primitive11_25_th_corr_mem_V_read(primitive11_25_th_corr_mem_V_read),
.primitive11_26_th_corr_mem_V_read(primitive11_26_th_corr_mem_V_read),
.primitive11_27_th_corr_mem_V_read(primitive11_27_th_corr_mem_V_read),
.primitive11_28_th_corr_mem_V_read(primitive11_28_th_corr_mem_V_read),
.primitive11_29_th_corr_mem_V_read(primitive11_29_th_corr_mem_V_read),
.primitive11_30_th_corr_mem_V_read(primitive11_30_th_corr_mem_V_read),
.primitive11_31_th_corr_mem_V_read(primitive11_31_th_corr_mem_V_read),
.primitive11_32_th_corr_mem_V_read(primitive11_32_th_corr_mem_V_read),
.primitive11_33_th_corr_mem_V_read(primitive11_33_th_corr_mem_V_read),
.primitive11_34_th_corr_mem_V_read(primitive11_34_th_corr_mem_V_read),
.primitive11_35_th_corr_mem_V_read(primitive11_35_th_corr_mem_V_read),
.primitive11_36_th_corr_mem_V_read(primitive11_36_th_corr_mem_V_read),
.primitive11_37_th_corr_mem_V_read(primitive11_37_th_corr_mem_V_read),
.primitive11_38_th_corr_mem_V_read(primitive11_38_th_corr_mem_V_read),
.primitive11_39_th_corr_mem_V_read(primitive11_39_th_corr_mem_V_read),
.primitive11_40_th_corr_mem_V_read(primitive11_40_th_corr_mem_V_read),
.primitive11_41_th_corr_mem_V_read(primitive11_41_th_corr_mem_V_read),
.primitive11_42_th_corr_mem_V_read(primitive11_42_th_corr_mem_V_read),
.primitive11_43_th_corr_mem_V_read(primitive11_43_th_corr_mem_V_read),
.primitive11_44_th_corr_mem_V_read(primitive11_44_th_corr_mem_V_read),
.primitive11_45_th_corr_mem_V_read(primitive11_45_th_corr_mem_V_read),
.primitive11_46_th_corr_mem_V_read(primitive11_46_th_corr_mem_V_read),
.primitive11_47_th_corr_mem_V_read(primitive11_47_th_corr_mem_V_read),
.primitive11_48_th_corr_mem_V_read(primitive11_48_th_corr_mem_V_read),
.primitive11_49_th_corr_mem_V_read(primitive11_49_th_corr_mem_V_read),
.primitive11_50_th_corr_mem_V_read(primitive11_50_th_corr_mem_V_read),
.primitive11_51_th_corr_mem_V_read(primitive11_51_th_corr_mem_V_read),
.primitive11_52_th_corr_mem_V_read(primitive11_52_th_corr_mem_V_read),
.primitive11_53_th_corr_mem_V_read(primitive11_53_th_corr_mem_V_read),
.primitive11_54_th_corr_mem_V_read(primitive11_54_th_corr_mem_V_read),
.primitive11_55_th_corr_mem_V_read(primitive11_55_th_corr_mem_V_read),
.primitive11_56_th_corr_mem_V_read(primitive11_56_th_corr_mem_V_read),
.primitive11_57_th_corr_mem_V_read(primitive11_57_th_corr_mem_V_read),
.primitive11_58_th_corr_mem_V_read(primitive11_58_th_corr_mem_V_read),
.primitive11_59_th_corr_mem_V_read(primitive11_59_th_corr_mem_V_read),
.primitive11_60_th_corr_mem_V_read(primitive11_60_th_corr_mem_V_read),
.primitive11_61_th_corr_mem_V_read(primitive11_61_th_corr_mem_V_read),
.primitive11_62_th_corr_mem_V_read(primitive11_62_th_corr_mem_V_read),
.primitive11_63_th_corr_mem_V_read(primitive11_63_th_corr_mem_V_read),
.primitive11_64_th_corr_mem_V_read(primitive11_64_th_corr_mem_V_read),
.primitive11_65_th_corr_mem_V_read(primitive11_65_th_corr_mem_V_read),
.primitive11_66_th_corr_mem_V_read(primitive11_66_th_corr_mem_V_read),
.primitive11_67_th_corr_mem_V_read(primitive11_67_th_corr_mem_V_read),
.primitive11_68_th_corr_mem_V_read(primitive11_68_th_corr_mem_V_read),
.primitive11_69_th_corr_mem_V_read(primitive11_69_th_corr_mem_V_read),
.primitive11_70_th_corr_mem_V_read(primitive11_70_th_corr_mem_V_read),
.primitive11_71_th_corr_mem_V_read(primitive11_71_th_corr_mem_V_read),
.primitive11_72_th_corr_mem_V_read(primitive11_72_th_corr_mem_V_read),
.primitive11_73_th_corr_mem_V_read(primitive11_73_th_corr_mem_V_read),
.primitive11_74_th_corr_mem_V_read(primitive11_74_th_corr_mem_V_read),
.primitive11_75_th_corr_mem_V_read(primitive11_75_th_corr_mem_V_read),
.primitive11_76_th_corr_mem_V_read(primitive11_76_th_corr_mem_V_read),
.primitive11_77_th_corr_mem_V_read(primitive11_77_th_corr_mem_V_read),
.primitive11_78_th_corr_mem_V_read(primitive11_78_th_corr_mem_V_read),
.primitive11_79_th_corr_mem_V_read(primitive11_79_th_corr_mem_V_read),
.primitive11_80_th_corr_mem_V_read(primitive11_80_th_corr_mem_V_read),
.primitive11_81_th_corr_mem_V_read(primitive11_81_th_corr_mem_V_read),
.primitive11_82_th_corr_mem_V_read(primitive11_82_th_corr_mem_V_read),
.primitive11_83_th_corr_mem_V_read(primitive11_83_th_corr_mem_V_read),
.primitive11_84_th_corr_mem_V_read(primitive11_84_th_corr_mem_V_read),
.primitive11_85_th_corr_mem_V_read(primitive11_85_th_corr_mem_V_read),
.primitive11_86_th_corr_mem_V_read(primitive11_86_th_corr_mem_V_read),
.primitive11_87_th_corr_mem_V_read(primitive11_87_th_corr_mem_V_read),
.primitive11_88_th_corr_mem_V_read(primitive11_88_th_corr_mem_V_read),
.primitive11_89_th_corr_mem_V_read(primitive11_89_th_corr_mem_V_read),
.primitive11_90_th_corr_mem_V_read(primitive11_90_th_corr_mem_V_read),
.primitive11_91_th_corr_mem_V_read(primitive11_91_th_corr_mem_V_read),
.primitive11_92_th_corr_mem_V_read(primitive11_92_th_corr_mem_V_read),
.primitive11_93_th_corr_mem_V_read(primitive11_93_th_corr_mem_V_read),
.primitive11_94_th_corr_mem_V_read(primitive11_94_th_corr_mem_V_read),
.primitive11_95_th_corr_mem_V_read(primitive11_95_th_corr_mem_V_read),
.primitive11_96_th_corr_mem_V_read(primitive11_96_th_corr_mem_V_read),
.primitive11_97_th_corr_mem_V_read(primitive11_97_th_corr_mem_V_read),
.primitive11_98_th_corr_mem_V_read(primitive11_98_th_corr_mem_V_read),
.primitive11_99_th_corr_mem_V_read(primitive11_99_th_corr_mem_V_read),
.primitive11_100_th_corr_mem_V_read(primitive11_100_th_corr_mem_V_read),
.primitive11_101_th_corr_mem_V_read(primitive11_101_th_corr_mem_V_read),
.primitive11_102_th_corr_mem_V_read(primitive11_102_th_corr_mem_V_read),
.primitive11_103_th_corr_mem_V_read(primitive11_103_th_corr_mem_V_read),
.primitive11_104_th_corr_mem_V_read(primitive11_104_th_corr_mem_V_read),
.primitive11_105_th_corr_mem_V_read(primitive11_105_th_corr_mem_V_read),
.primitive11_106_th_corr_mem_V_read(primitive11_106_th_corr_mem_V_read),
.primitive11_107_th_corr_mem_V_read(primitive11_107_th_corr_mem_V_read),
.primitive11_108_th_corr_mem_V_read(primitive11_108_th_corr_mem_V_read),
.primitive11_109_th_corr_mem_V_read(primitive11_109_th_corr_mem_V_read),
.primitive11_110_th_corr_mem_V_read(primitive11_110_th_corr_mem_V_read),
.primitive11_111_th_corr_mem_V_read(primitive11_111_th_corr_mem_V_read),
.primitive11_112_th_corr_mem_V_read(primitive11_112_th_corr_mem_V_read),
.primitive11_113_th_corr_mem_V_read(primitive11_113_th_corr_mem_V_read),
.primitive11_114_th_corr_mem_V_read(primitive11_114_th_corr_mem_V_read),
.primitive11_115_th_corr_mem_V_read(primitive11_115_th_corr_mem_V_read),
.primitive11_116_th_corr_mem_V_read(primitive11_116_th_corr_mem_V_read),
.primitive11_117_th_corr_mem_V_read(primitive11_117_th_corr_mem_V_read),
.primitive11_118_th_corr_mem_V_read(primitive11_118_th_corr_mem_V_read),
.primitive11_119_th_corr_mem_V_read(primitive11_119_th_corr_mem_V_read),
.primitive11_120_th_corr_mem_V_read(primitive11_120_th_corr_mem_V_read),
.primitive11_121_th_corr_mem_V_read(primitive11_121_th_corr_mem_V_read),
.primitive11_122_th_corr_mem_V_read(primitive11_122_th_corr_mem_V_read),
.primitive11_123_th_corr_mem_V_read(primitive11_123_th_corr_mem_V_read),
.primitive11_124_th_corr_mem_V_read(primitive11_124_th_corr_mem_V_read),
.primitive11_125_th_corr_mem_V_read(primitive11_125_th_corr_mem_V_read),
.primitive11_126_th_corr_mem_V_read(primitive11_126_th_corr_mem_V_read),
.primitive11_127_th_corr_mem_V_read(primitive11_127_th_corr_mem_V_read),
.r_in_V(r_in_V),
.addr_V(addr_V),
.sel_V(sel_V),
.ap_return_0(call_ret1_sp_mem11_fu_4922_ap_return_0),
.ap_return_1(call_ret1_sp_mem11_fu_4922_ap_return_1),
.ap_return_2(call_ret1_sp_mem11_fu_4922_ap_return_2),
.ap_return_3(call_ret1_sp_mem11_fu_4922_ap_return_3),
.ap_return_4(call_ret1_sp_mem11_fu_4922_ap_return_4),
.ap_return_5(call_ret1_sp_mem11_fu_4922_ap_return_5),
.ap_return_6(call_ret1_sp_mem11_fu_4922_ap_return_6),
.ap_return_7(call_ret1_sp_mem11_fu_4922_ap_return_7),
.ap_return_8(call_ret1_sp_mem11_fu_4922_ap_return_8),
.ap_return_9(call_ret1_sp_mem11_fu_4922_ap_return_9),
.ap_return_10(call_ret1_sp_mem11_fu_4922_ap_return_10),
.ap_return_11(call_ret1_sp_mem11_fu_4922_ap_return_11),
.ap_return_12(call_ret1_sp_mem11_fu_4922_ap_return_12),
.ap_return_13(call_ret1_sp_mem11_fu_4922_ap_return_13),
.ap_return_14(call_ret1_sp_mem11_fu_4922_ap_return_14),
.ap_return_15(call_ret1_sp_mem11_fu_4922_ap_return_15),
.ap_return_16(call_ret1_sp_mem11_fu_4922_ap_return_16),
.ap_return_17(call_ret1_sp_mem11_fu_4922_ap_return_17),
.ap_return_18(call_ret1_sp_mem11_fu_4922_ap_return_18),
.ap_return_19(call_ret1_sp_mem11_fu_4922_ap_return_19),
.ap_return_20(call_ret1_sp_mem11_fu_4922_ap_return_20),
.ap_return_21(call_ret1_sp_mem11_fu_4922_ap_return_21),
.ap_return_22(call_ret1_sp_mem11_fu_4922_ap_return_22),
.ap_return_23(call_ret1_sp_mem11_fu_4922_ap_return_23),
.ap_return_24(call_ret1_sp_mem11_fu_4922_ap_return_24),
.ap_return_25(call_ret1_sp_mem11_fu_4922_ap_return_25),
.ap_return_26(call_ret1_sp_mem11_fu_4922_ap_return_26),
.ap_return_27(call_ret1_sp_mem11_fu_4922_ap_return_27),
.ap_return_28(call_ret1_sp_mem11_fu_4922_ap_return_28),
.ap_return_29(call_ret1_sp_mem11_fu_4922_ap_return_29),
.ap_return_30(call_ret1_sp_mem11_fu_4922_ap_return_30),
.ap_return_31(call_ret1_sp_mem11_fu_4922_ap_return_31),
.ap_return_32(call_ret1_sp_mem11_fu_4922_ap_return_32),
.ap_return_33(call_ret1_sp_mem11_fu_4922_ap_return_33),
.ap_return_34(call_ret1_sp_mem11_fu_4922_ap_return_34),
.ap_return_35(call_ret1_sp_mem11_fu_4922_ap_return_35),
.ap_return_36(call_ret1_sp_mem11_fu_4922_ap_return_36),
.ap_return_37(call_ret1_sp_mem11_fu_4922_ap_return_37),
.ap_return_38(call_ret1_sp_mem11_fu_4922_ap_return_38),
.ap_return_39(call_ret1_sp_mem11_fu_4922_ap_return_39),
.ap_return_40(call_ret1_sp_mem11_fu_4922_ap_return_40),
.ap_return_41(call_ret1_sp_mem11_fu_4922_ap_return_41),
.ap_return_42(call_ret1_sp_mem11_fu_4922_ap_return_42),
.ap_return_43(call_ret1_sp_mem11_fu_4922_ap_return_43),
.ap_return_44(call_ret1_sp_mem11_fu_4922_ap_return_44),
.ap_return_45(call_ret1_sp_mem11_fu_4922_ap_return_45),
.ap_return_46(call_ret1_sp_mem11_fu_4922_ap_return_46),
.ap_return_47(call_ret1_sp_mem11_fu_4922_ap_return_47),
.ap_return_48(call_ret1_sp_mem11_fu_4922_ap_return_48),
.ap_return_49(call_ret1_sp_mem11_fu_4922_ap_return_49),
.ap_return_50(call_ret1_sp_mem11_fu_4922_ap_return_50),
.ap_return_51(call_ret1_sp_mem11_fu_4922_ap_return_51),
.ap_return_52(call_ret1_sp_mem11_fu_4922_ap_return_52),
.ap_return_53(call_ret1_sp_mem11_fu_4922_ap_return_53),
.ap_return_54(call_ret1_sp_mem11_fu_4922_ap_return_54),
.ap_return_55(call_ret1_sp_mem11_fu_4922_ap_return_55),
.ap_return_56(call_ret1_sp_mem11_fu_4922_ap_return_56),
.ap_return_57(call_ret1_sp_mem11_fu_4922_ap_return_57),
.ap_return_58(call_ret1_sp_mem11_fu_4922_ap_return_58),
.ap_return_59(call_ret1_sp_mem11_fu_4922_ap_return_59),
.ap_return_60(call_ret1_sp_mem11_fu_4922_ap_return_60),
.ap_return_61(call_ret1_sp_mem11_fu_4922_ap_return_61),
.ap_return_62(call_ret1_sp_mem11_fu_4922_ap_return_62),
.ap_return_63(call_ret1_sp_mem11_fu_4922_ap_return_63),
.ap_return_64(call_ret1_sp_mem11_fu_4922_ap_return_64),
.ap_return_65(call_ret1_sp_mem11_fu_4922_ap_return_65),
.ap_return_66(call_ret1_sp_mem11_fu_4922_ap_return_66),
.ap_return_67(call_ret1_sp_mem11_fu_4922_ap_return_67),
.ap_return_68(call_ret1_sp_mem11_fu_4922_ap_return_68),
.ap_return_69(call_ret1_sp_mem11_fu_4922_ap_return_69),
.ap_return_70(call_ret1_sp_mem11_fu_4922_ap_return_70),
.ap_return_71(call_ret1_sp_mem11_fu_4922_ap_return_71),
.ap_return_72(call_ret1_sp_mem11_fu_4922_ap_return_72),
.ap_return_73(call_ret1_sp_mem11_fu_4922_ap_return_73),
.ap_return_74(call_ret1_sp_mem11_fu_4922_ap_return_74),
.ap_return_75(call_ret1_sp_mem11_fu_4922_ap_return_75),
.ap_return_76(call_ret1_sp_mem11_fu_4922_ap_return_76),
.ap_return_77(call_ret1_sp_mem11_fu_4922_ap_return_77),
.ap_return_78(call_ret1_sp_mem11_fu_4922_ap_return_78),
.ap_return_79(call_ret1_sp_mem11_fu_4922_ap_return_79),
.ap_return_80(call_ret1_sp_mem11_fu_4922_ap_return_80),
.ap_return_81(call_ret1_sp_mem11_fu_4922_ap_return_81),
.ap_return_82(call_ret1_sp_mem11_fu_4922_ap_return_82),
.ap_return_83(call_ret1_sp_mem11_fu_4922_ap_return_83),
.ap_return_84(call_ret1_sp_mem11_fu_4922_ap_return_84),
.ap_return_85(call_ret1_sp_mem11_fu_4922_ap_return_85),
.ap_return_86(call_ret1_sp_mem11_fu_4922_ap_return_86),
.ap_return_87(call_ret1_sp_mem11_fu_4922_ap_return_87),
.ap_return_88(call_ret1_sp_mem11_fu_4922_ap_return_88),
.ap_return_89(call_ret1_sp_mem11_fu_4922_ap_return_89),
.ap_return_90(call_ret1_sp_mem11_fu_4922_ap_return_90),
.ap_return_91(call_ret1_sp_mem11_fu_4922_ap_return_91),
.ap_return_92(call_ret1_sp_mem11_fu_4922_ap_return_92),
.ap_return_93(call_ret1_sp_mem11_fu_4922_ap_return_93),
.ap_return_94(call_ret1_sp_mem11_fu_4922_ap_return_94),
.ap_return_95(call_ret1_sp_mem11_fu_4922_ap_return_95),
.ap_return_96(call_ret1_sp_mem11_fu_4922_ap_return_96),
.ap_return_97(call_ret1_sp_mem11_fu_4922_ap_return_97),
.ap_return_98(call_ret1_sp_mem11_fu_4922_ap_return_98),
.ap_return_99(call_ret1_sp_mem11_fu_4922_ap_return_99),
.ap_return_100(call_ret1_sp_mem11_fu_4922_ap_return_100),
.ap_return_101(call_ret1_sp_mem11_fu_4922_ap_return_101),
.ap_return_102(call_ret1_sp_mem11_fu_4922_ap_return_102),
.ap_return_103(call_ret1_sp_mem11_fu_4922_ap_return_103),
.ap_return_104(call_ret1_sp_mem11_fu_4922_ap_return_104),
.ap_return_105(call_ret1_sp_mem11_fu_4922_ap_return_105),
.ap_return_106(call_ret1_sp_mem11_fu_4922_ap_return_106),
.ap_return_107(call_ret1_sp_mem11_fu_4922_ap_return_107),
.ap_return_108(call_ret1_sp_mem11_fu_4922_ap_return_108),
.ap_return_109(call_ret1_sp_mem11_fu_4922_ap_return_109),
.ap_return_110(call_ret1_sp_mem11_fu_4922_ap_return_110),
.ap_return_111(call_ret1_sp_mem11_fu_4922_ap_return_111),
.ap_return_112(call_ret1_sp_mem11_fu_4922_ap_return_112),
.ap_return_113(call_ret1_sp_mem11_fu_4922_ap_return_113),
.ap_return_114(call_ret1_sp_mem11_fu_4922_ap_return_114),
.ap_return_115(call_ret1_sp_mem11_fu_4922_ap_return_115),
.ap_return_116(call_ret1_sp_mem11_fu_4922_ap_return_116),
.ap_return_117(call_ret1_sp_mem11_fu_4922_ap_return_117),
.ap_return_118(call_ret1_sp_mem11_fu_4922_ap_return_118),
.ap_return_119(call_ret1_sp_mem11_fu_4922_ap_return_119),
.ap_return_120(call_ret1_sp_mem11_fu_4922_ap_return_120),
.ap_return_121(call_ret1_sp_mem11_fu_4922_ap_return_121),
.ap_return_122(call_ret1_sp_mem11_fu_4922_ap_return_122),
.ap_return_123(call_ret1_sp_mem11_fu_4922_ap_return_123),
.ap_return_124(call_ret1_sp_mem11_fu_4922_ap_return_124),
.ap_return_125(call_ret1_sp_mem11_fu_4922_ap_return_125),
.ap_return_126(call_ret1_sp_mem11_fu_4922_ap_return_126),
.ap_return_127(call_ret1_sp_mem11_fu_4922_ap_return_127),
.ap_return_128(call_ret1_sp_mem11_fu_4922_ap_return_128),
.ap_return_129(call_ret1_sp_mem11_fu_4922_ap_return_129),
.ap_return_130(call_ret1_sp_mem11_fu_4922_ap_return_130),
.ap_return_131(call_ret1_sp_mem11_fu_4922_ap_return_131),
.ap_return_132(call_ret1_sp_mem11_fu_4922_ap_return_132),
.ap_return_133(call_ret1_sp_mem11_fu_4922_ap_return_133),
.ap_return_134(call_ret1_sp_mem11_fu_4922_ap_return_134),
.ap_return_135(call_ret1_sp_mem11_fu_4922_ap_return_135),
.ap_return_136(call_ret1_sp_mem11_fu_4922_ap_return_136),
.ap_return_137(call_ret1_sp_mem11_fu_4922_ap_return_137),
.ap_return_138(call_ret1_sp_mem11_fu_4922_ap_return_138),
.ap_return_139(call_ret1_sp_mem11_fu_4922_ap_return_139),
.ap_return_140(call_ret1_sp_mem11_fu_4922_ap_return_140),
.ap_return_141(call_ret1_sp_mem11_fu_4922_ap_return_141),
.ap_return_142(call_ret1_sp_mem11_fu_4922_ap_return_142),
.ap_return_143(call_ret1_sp_mem11_fu_4922_ap_return_143),
.ap_return_144(call_ret1_sp_mem11_fu_4922_ap_return_144),
.ap_return_145(call_ret1_sp_mem11_fu_4922_ap_return_145),
.ap_return_146(call_ret1_sp_mem11_fu_4922_ap_return_146),
.ap_return_147(call_ret1_sp_mem11_fu_4922_ap_return_147),
.ap_return_148(call_ret1_sp_mem11_fu_4922_ap_return_148),
.ap_return_149(call_ret1_sp_mem11_fu_4922_ap_return_149),
.ap_return_150(call_ret1_sp_mem11_fu_4922_ap_return_150),
.ap_return_151(call_ret1_sp_mem11_fu_4922_ap_return_151),
.ap_return_152(call_ret1_sp_mem11_fu_4922_ap_return_152),
.ap_return_153(call_ret1_sp_mem11_fu_4922_ap_return_153),
.ap_return_154(call_ret1_sp_mem11_fu_4922_ap_return_154),
.ap_return_155(call_ret1_sp_mem11_fu_4922_ap_return_155),
.ap_return_156(call_ret1_sp_mem11_fu_4922_ap_return_156),
.ap_return_157(call_ret1_sp_mem11_fu_4922_ap_return_157),
.ap_return_158(call_ret1_sp_mem11_fu_4922_ap_return_158),
.ap_return_159(call_ret1_sp_mem11_fu_4922_ap_return_159),
.ap_return_160(call_ret1_sp_mem11_fu_4922_ap_return_160),
.ap_return_161(call_ret1_sp_mem11_fu_4922_ap_return_161),
.ap_return_162(call_ret1_sp_mem11_fu_4922_ap_return_162),
.ap_return_163(call_ret1_sp_mem11_fu_4922_ap_return_163),
.ap_return_164(call_ret1_sp_mem11_fu_4922_ap_return_164),
.ap_return_165(call_ret1_sp_mem11_fu_4922_ap_return_165),
.ap_return_166(call_ret1_sp_mem11_fu_4922_ap_return_166),
.ap_return_167(call_ret1_sp_mem11_fu_4922_ap_return_167),
.ap_return_168(call_ret1_sp_mem11_fu_4922_ap_return_168),
.ap_return_169(call_ret1_sp_mem11_fu_4922_ap_return_169),
.ap_return_170(call_ret1_sp_mem11_fu_4922_ap_return_170),
.ap_return_171(call_ret1_sp_mem11_fu_4922_ap_return_171),
.ap_return_172(call_ret1_sp_mem11_fu_4922_ap_return_172),
.ap_return_173(call_ret1_sp_mem11_fu_4922_ap_return_173),
.ap_return_174(call_ret1_sp_mem11_fu_4922_ap_return_174),
.ap_return_175(call_ret1_sp_mem11_fu_4922_ap_return_175),
.ap_return_176(call_ret1_sp_mem11_fu_4922_ap_return_176),
.ap_return_177(call_ret1_sp_mem11_fu_4922_ap_return_177),
.ap_return_178(call_ret1_sp_mem11_fu_4922_ap_return_178),
.ap_return_179(call_ret1_sp_mem11_fu_4922_ap_return_179),
.ap_return_180(call_ret1_sp_mem11_fu_4922_ap_return_180),
.ap_return_181(call_ret1_sp_mem11_fu_4922_ap_return_181),
.ap_return_182(call_ret1_sp_mem11_fu_4922_ap_return_182),
.ap_return_183(call_ret1_sp_mem11_fu_4922_ap_return_183),
.ap_return_184(call_ret1_sp_mem11_fu_4922_ap_return_184),
.ap_return_185(call_ret1_sp_mem11_fu_4922_ap_return_185),
.ap_return_186(call_ret1_sp_mem11_fu_4922_ap_return_186),
.ap_return_187(call_ret1_sp_mem11_fu_4922_ap_return_187),
.ap_return_188(call_ret1_sp_mem11_fu_4922_ap_return_188),
.ap_return_189(call_ret1_sp_mem11_fu_4922_ap_return_189),
.ap_return_190(call_ret1_sp_mem11_fu_4922_ap_return_190),
.ap_return_191(call_ret1_sp_mem11_fu_4922_ap_return_191),
.ap_return_192(call_ret1_sp_mem11_fu_4922_ap_return_192),
.ap_return_193(call_ret1_sp_mem11_fu_4922_ap_return_193),
.ap_return_194(call_ret1_sp_mem11_fu_4922_ap_return_194),
.ap_return_195(call_ret1_sp_mem11_fu_4922_ap_return_195),
.ap_return_196(call_ret1_sp_mem11_fu_4922_ap_return_196),
.ap_return_197(call_ret1_sp_mem11_fu_4922_ap_return_197),
.ap_return_198(call_ret1_sp_mem11_fu_4922_ap_return_198),
.ap_return_199(call_ret1_sp_mem11_fu_4922_ap_return_199),
.ap_return_200(call_ret1_sp_mem11_fu_4922_ap_return_200),
.ap_return_201(call_ret1_sp_mem11_fu_4922_ap_return_201),
.ap_return_202(call_ret1_sp_mem11_fu_4922_ap_return_202),
.ap_return_203(call_ret1_sp_mem11_fu_4922_ap_return_203),
.ap_return_204(call_ret1_sp_mem11_fu_4922_ap_return_204),
.ap_return_205(call_ret1_sp_mem11_fu_4922_ap_return_205),
.ap_return_206(call_ret1_sp_mem11_fu_4922_ap_return_206),
.ap_return_207(call_ret1_sp_mem11_fu_4922_ap_return_207),
.ap_return_208(call_ret1_sp_mem11_fu_4922_ap_return_208),
.ap_return_209(call_ret1_sp_mem11_fu_4922_ap_return_209),
.ap_return_210(call_ret1_sp_mem11_fu_4922_ap_return_210),
.ap_return_211(call_ret1_sp_mem11_fu_4922_ap_return_211),
.ap_return_212(call_ret1_sp_mem11_fu_4922_ap_return_212),
.ap_return_213(call_ret1_sp_mem11_fu_4922_ap_return_213),
.ap_return_214(call_ret1_sp_mem11_fu_4922_ap_return_214),
.ap_return_215(call_ret1_sp_mem11_fu_4922_ap_return_215),
.ap_return_216(call_ret1_sp_mem11_fu_4922_ap_return_216),
.ap_return_217(call_ret1_sp_mem11_fu_4922_ap_return_217),
.ap_return_218(call_ret1_sp_mem11_fu_4922_ap_return_218),
.ap_return_219(call_ret1_sp_mem11_fu_4922_ap_return_219),
.ap_return_220(call_ret1_sp_mem11_fu_4922_ap_return_220),
.ap_return_221(call_ret1_sp_mem11_fu_4922_ap_return_221),
.ap_return_222(call_ret1_sp_mem11_fu_4922_ap_return_222),
.ap_return_223(call_ret1_sp_mem11_fu_4922_ap_return_223),
.ap_return_224(call_ret1_sp_mem11_fu_4922_ap_return_224),
.ap_return_225(call_ret1_sp_mem11_fu_4922_ap_return_225),
.ap_return_226(call_ret1_sp_mem11_fu_4922_ap_return_226),
.ap_return_227(call_ret1_sp_mem11_fu_4922_ap_return_227),
.ap_return_228(call_ret1_sp_mem11_fu_4922_ap_return_228),
.ap_return_229(call_ret1_sp_mem11_fu_4922_ap_return_229),
.ap_return_230(call_ret1_sp_mem11_fu_4922_ap_return_230),
.ap_return_231(call_ret1_sp_mem11_fu_4922_ap_return_231),
.ap_return_232(call_ret1_sp_mem11_fu_4922_ap_return_232),
.ap_return_233(call_ret1_sp_mem11_fu_4922_ap_return_233),
.ap_return_234(call_ret1_sp_mem11_fu_4922_ap_return_234),
.ap_return_235(call_ret1_sp_mem11_fu_4922_ap_return_235),
.ap_return_236(call_ret1_sp_mem11_fu_4922_ap_return_236),
.ap_return_237(call_ret1_sp_mem11_fu_4922_ap_return_237),
.ap_return_238(call_ret1_sp_mem11_fu_4922_ap_return_238),
.ap_return_239(call_ret1_sp_mem11_fu_4922_ap_return_239),
.ap_return_240(call_ret1_sp_mem11_fu_4922_ap_return_240),
.ap_return_241(call_ret1_sp_mem11_fu_4922_ap_return_241),
.ap_return_242(call_ret1_sp_mem11_fu_4922_ap_return_242),
.ap_return_243(call_ret1_sp_mem11_fu_4922_ap_return_243),
.ap_return_244(call_ret1_sp_mem11_fu_4922_ap_return_244),
.ap_return_245(call_ret1_sp_mem11_fu_4922_ap_return_245),
.ap_return_246(call_ret1_sp_mem11_fu_4922_ap_return_246),
.ap_return_247(call_ret1_sp_mem11_fu_4922_ap_return_247),
.ap_return_248(call_ret1_sp_mem11_fu_4922_ap_return_248),
.ap_return_249(call_ret1_sp_mem11_fu_4922_ap_return_249),
.ap_return_250(call_ret1_sp_mem11_fu_4922_ap_return_250),
.ap_return_251(call_ret1_sp_mem11_fu_4922_ap_return_251),
.ap_return_252(call_ret1_sp_mem11_fu_4922_ap_return_252),
.ap_return_253(call_ret1_sp_mem11_fu_4922_ap_return_253),
.ap_return_254(call_ret1_sp_mem11_fu_4922_ap_return_254),
.ap_return_255(call_ret1_sp_mem11_fu_4922_ap_return_255),
.ap_return_256(call_ret1_sp_mem11_fu_4922_ap_return_256),
.ap_return_257(call_ret1_sp_mem11_fu_4922_ap_return_257),
.ap_return_258(call_ret1_sp_mem11_fu_4922_ap_return_258),
.ap_return_259(call_ret1_sp_mem11_fu_4922_ap_return_259),
.ap_return_260(call_ret1_sp_mem11_fu_4922_ap_return_260),
.ap_return_261(call_ret1_sp_mem11_fu_4922_ap_return_261)
);
sp_prim_conv11 call_ret_sp_prim_conv11_fu_5456(
.primitive11_0_params_V_read(primitive11_0_params_V_read),
.primitive11_1_params_V_read(primitive11_1_params_V_read),
.primitive11_2_params_V_read(primitive11_2_params_V_read),
.primitive11_3_params_V_read(primitive11_3_params_V_read),
.primitive11_4_params_V_read(primitive11_4_params_V_read),
.primitive11_0_th_mem_V_read(primitive11_0_th_mem_V_read),
.primitive11_1_th_mem_V_read(primitive11_1_th_mem_V_read),
.primitive11_2_th_mem_V_read(primitive11_2_th_mem_V_read),
.primitive11_3_th_mem_V_read(primitive11_3_th_mem_V_read),
.primitive11_4_th_mem_V_read(primitive11_4_th_mem_V_read),
.primitive11_5_th_mem_V_read(primitive11_5_th_mem_V_read),
.primitive11_6_th_mem_V_read(primitive11_6_th_mem_V_read),
.primitive11_7_th_mem_V_read(primitive11_7_th_mem_V_read),
.primitive11_8_th_mem_V_read(primitive11_8_th_mem_V_read),
.primitive11_9_th_mem_V_read(primitive11_9_th_mem_V_read),
.primitive11_10_th_mem_V_read(primitive11_10_th_mem_V_read),
.primitive11_11_th_mem_V_read(primitive11_11_th_mem_V_read),
.primitive11_12_th_mem_V_read(primitive11_12_th_mem_V_read),
.primitive11_13_th_mem_V_read(primitive11_13_th_mem_V_read),
.primitive11_14_th_mem_V_read(primitive11_14_th_mem_V_read),
.primitive11_15_th_mem_V_read(primitive11_15_th_mem_V_read),
.primitive11_16_th_mem_V_read(primitive11_16_th_mem_V_read),
.primitive11_17_th_mem_V_read(primitive11_17_th_mem_V_read),
.primitive11_18_th_mem_V_read(primitive11_18_th_mem_V_read),
.primitive11_19_th_mem_V_read(primitive11_19_th_mem_V_read),
.primitive11_20_th_mem_V_read(primitive11_20_th_mem_V_read),
.primitive11_21_th_mem_V_read(primitive11_21_th_mem_V_read),
.primitive11_22_th_mem_V_read(primitive11_22_th_mem_V_read),
.primitive11_23_th_mem_V_read(primitive11_23_th_mem_V_read),
.primitive11_24_th_mem_V_read(primitive11_24_th_mem_V_read),
.primitive11_25_th_mem_V_read(primitive11_25_th_mem_V_read),
.primitive11_26_th_mem_V_read(primitive11_26_th_mem_V_read),
.primitive11_27_th_mem_V_read(primitive11_27_th_mem_V_read),
.primitive11_28_th_mem_V_read(primitive11_28_th_mem_V_read),
.primitive11_29_th_mem_V_read(primitive11_29_th_mem_V_read),
.primitive11_30_th_mem_V_read(primitive11_30_th_mem_V_read),
.primitive11_31_th_mem_V_read(primitive11_31_th_mem_V_read),
.primitive11_32_th_mem_V_read(primitive11_32_th_mem_V_read),
.primitive11_33_th_mem_V_read(primitive11_33_th_mem_V_read),
.primitive11_34_th_mem_V_read(primitive11_34_th_mem_V_read),
.primitive11_35_th_mem_V_read(primitive11_35_th_mem_V_read),
.primitive11_36_th_mem_V_read(primitive11_36_th_mem_V_read),
.primitive11_37_th_mem_V_read(primitive11_37_th_mem_V_read),
.primitive11_38_th_mem_V_read(primitive11_38_th_mem_V_read),
.primitive11_39_th_mem_V_read(primitive11_39_th_mem_V_read),
.primitive11_40_th_mem_V_read(primitive11_40_th_mem_V_read),
.primitive11_41_th_mem_V_read(primitive11_41_th_mem_V_read),
.primitive11_42_th_mem_V_read(primitive11_42_th_mem_V_read),
.primitive11_43_th_mem_V_read(primitive11_43_th_mem_V_read),
.primitive11_44_th_mem_V_read(primitive11_44_th_mem_V_read),
.primitive11_45_th_mem_V_read(primitive11_45_th_mem_V_read),
.primitive11_46_th_mem_V_read(primitive11_46_th_mem_V_read),
.primitive11_47_th_mem_V_read(primitive11_47_th_mem_V_read),
.primitive11_48_th_mem_V_read(primitive11_48_th_mem_V_read),
.primitive11_49_th_mem_V_read(primitive11_49_th_mem_V_read),
.primitive11_50_th_mem_V_read(primitive11_50_th_mem_V_read),
.primitive11_51_th_mem_V_read(primitive11_51_th_mem_V_read),
.primitive11_52_th_mem_V_read(primitive11_52_th_mem_V_read),
.primitive11_53_th_mem_V_read(primitive11_53_th_mem_V_read),
.primitive11_54_th_mem_V_read(primitive11_54_th_mem_V_read),
.primitive11_55_th_mem_V_read(primitive11_55_th_mem_V_read),
.primitive11_56_th_mem_V_read(primitive11_56_th_mem_V_read),
.primitive11_57_th_mem_V_read(primitive11_57_th_mem_V_read),
.primitive11_58_th_mem_V_read(primitive11_58_th_mem_V_read),
.primitive11_59_th_mem_V_read(primitive11_59_th_mem_V_read),
.primitive11_60_th_mem_V_read(primitive11_60_th_mem_V_read),
.primitive11_61_th_mem_V_read(primitive11_61_th_mem_V_read),
.primitive11_62_th_mem_V_read(primitive11_62_th_mem_V_read),
.primitive11_63_th_mem_V_read(primitive11_63_th_mem_V_read),
.primitive11_64_th_mem_V_read(primitive11_64_th_mem_V_read),
.primitive11_65_th_mem_V_read(primitive11_65_th_mem_V_read),
.primitive11_66_th_mem_V_read(primitive11_66_th_mem_V_read),
.primitive11_67_th_mem_V_read(primitive11_67_th_mem_V_read),
.primitive11_68_th_mem_V_read(primitive11_68_th_mem_V_read),
.primitive11_69_th_mem_V_read(primitive11_69_th_mem_V_read),
.primitive11_70_th_mem_V_read(primitive11_70_th_mem_V_read),
.primitive11_71_th_mem_V_read(primitive11_71_th_mem_V_read),
.primitive11_72_th_mem_V_read(primitive11_72_th_mem_V_read),
.primitive11_73_th_mem_V_read(primitive11_73_th_mem_V_read),
.primitive11_74_th_mem_V_read(primitive11_74_th_mem_V_read),
.primitive11_75_th_mem_V_read(primitive11_75_th_mem_V_read),
.primitive11_76_th_mem_V_read(primitive11_76_th_mem_V_read),
.primitive11_77_th_mem_V_read(primitive11_77_th_mem_V_read),
.primitive11_78_th_mem_V_read(primitive11_78_th_mem_V_read),
.primitive11_79_th_mem_V_read(primitive11_79_th_mem_V_read),
.primitive11_80_th_mem_V_read(primitive11_80_th_mem_V_read),
.primitive11_81_th_mem_V_read(primitive11_81_th_mem_V_read),
.primitive11_82_th_mem_V_read(primitive11_82_th_mem_V_read),
.primitive11_83_th_mem_V_read(primitive11_83_th_mem_V_read),
.primitive11_84_th_mem_V_read(primitive11_84_th_mem_V_read),
.primitive11_85_th_mem_V_read(primitive11_85_th_mem_V_read),
.primitive11_86_th_mem_V_read(primitive11_86_th_mem_V_read),
.primitive11_87_th_mem_V_read(primitive11_87_th_mem_V_read),
.primitive11_88_th_mem_V_read(primitive11_88_th_mem_V_read),
.primitive11_89_th_mem_V_read(primitive11_89_th_mem_V_read),
.primitive11_90_th_mem_V_read(primitive11_90_th_mem_V_read),
.primitive11_91_th_mem_V_read(primitive11_91_th_mem_V_read),
.primitive11_92_th_mem_V_read(primitive11_92_th_mem_V_read),
.primitive11_93_th_mem_V_read(primitive11_93_th_mem_V_read),
.primitive11_94_th_mem_V_read(primitive11_94_th_mem_V_read),
.primitive11_95_th_mem_V_read(primitive11_95_th_mem_V_read),
.primitive11_96_th_mem_V_read(primitive11_96_th_mem_V_read),
.primitive11_97_th_mem_V_read(primitive11_97_th_mem_V_read),
.primitive11_98_th_mem_V_read(primitive11_98_th_mem_V_read),
.primitive11_99_th_mem_V_read(primitive11_99_th_mem_V_read),
.primitive11_100_th_mem_V_read(primitive11_100_th_mem_V_read),
.primitive11_101_th_mem_V_read(primitive11_101_th_mem_V_read),
.primitive11_102_th_mem_V_read(primitive11_102_th_mem_V_read),
.primitive11_103_th_mem_V_read(primitive11_103_th_mem_V_read),
.primitive11_104_th_mem_V_read(primitive11_104_th_mem_V_read),
.primitive11_105_th_mem_V_read(primitive11_105_th_mem_V_read),
.primitive11_106_th_mem_V_read(primitive11_106_th_mem_V_read),
.primitive11_107_th_mem_V_read(primitive11_107_th_mem_V_read),
.primitive11_108_th_mem_V_read(primitive11_108_th_mem_V_read),
.primitive11_109_th_mem_V_read(primitive11_109_th_mem_V_read),
.primitive11_110_th_mem_V_read(primitive11_110_th_mem_V_read),
.primitive11_111_th_mem_V_read(primitive11_111_th_mem_V_read),
.primitive11_112_th_mem_V_read(primitive11_112_th_mem_V_read),
.primitive11_113_th_mem_V_read(primitive11_113_th_mem_V_read),
.primitive11_114_th_mem_V_read(primitive11_114_th_mem_V_read),
.primitive11_115_th_mem_V_read(primitive11_115_th_mem_V_read),
.primitive11_116_th_mem_V_read(primitive11_116_th_mem_V_read),
.primitive11_117_th_mem_V_read(primitive11_117_th_mem_V_read),
.primitive11_118_th_mem_V_read(primitive11_118_th_mem_V_read),
.primitive11_119_th_mem_V_read(primitive11_119_th_mem_V_read),
.primitive11_120_th_mem_V_read(primitive11_120_th_mem_V_read),
.primitive11_121_th_mem_V_read(primitive11_121_th_mem_V_read),
.primitive11_122_th_mem_V_read(primitive11_122_th_mem_V_read),
.primitive11_123_th_mem_V_read(primitive11_123_th_mem_V_read),
.primitive11_124_th_mem_V_read(primitive11_124_th_mem_V_read),
.primitive11_125_th_mem_V_read(primitive11_125_th_mem_V_read),
.primitive11_126_th_mem_V_read(primitive11_126_th_mem_V_read),
.primitive11_127_th_mem_V_read(primitive11_127_th_mem_V_read),
.primitive11_0_th_corr_mem_V_read(primitive11_0_th_corr_mem_V_read),
.primitive11_1_th_corr_mem_V_read(primitive11_1_th_corr_mem_V_read),
.primitive11_2_th_corr_mem_V_read(primitive11_2_th_corr_mem_V_read),
.primitive11_3_th_corr_mem_V_read(primitive11_3_th_corr_mem_V_read),
.primitive11_4_th_corr_mem_V_read(primitive11_4_th_corr_mem_V_read),
.primitive11_5_th_corr_mem_V_read(primitive11_5_th_corr_mem_V_read),
.primitive11_6_th_corr_mem_V_read(primitive11_6_th_corr_mem_V_read),
.primitive11_7_th_corr_mem_V_read(primitive11_7_th_corr_mem_V_read),
.primitive11_8_th_corr_mem_V_read(primitive11_8_th_corr_mem_V_read),
.primitive11_9_th_corr_mem_V_read(primitive11_9_th_corr_mem_V_read),
.primitive11_10_th_corr_mem_V_read(primitive11_10_th_corr_mem_V_read),
.primitive11_11_th_corr_mem_V_read(primitive11_11_th_corr_mem_V_read),
.primitive11_12_th_corr_mem_V_read(primitive11_12_th_corr_mem_V_read),
.primitive11_13_th_corr_mem_V_read(primitive11_13_th_corr_mem_V_read),
.primitive11_14_th_corr_mem_V_read(primitive11_14_th_corr_mem_V_read),
.primitive11_15_th_corr_mem_V_read(primitive11_15_th_corr_mem_V_read),
.primitive11_16_th_corr_mem_V_read(primitive11_16_th_corr_mem_V_read),
.primitive11_17_th_corr_mem_V_read(primitive11_17_th_corr_mem_V_read),
.primitive11_18_th_corr_mem_V_read(primitive11_18_th_corr_mem_V_read),
.primitive11_19_th_corr_mem_V_read(primitive11_19_th_corr_mem_V_read),
.primitive11_20_th_corr_mem_V_read(primitive11_20_th_corr_mem_V_read),
.primitive11_21_th_corr_mem_V_read(primitive11_21_th_corr_mem_V_read),
.primitive11_22_th_corr_mem_V_read(primitive11_22_th_corr_mem_V_read),
.primitive11_23_th_corr_mem_V_read(primitive11_23_th_corr_mem_V_read),
.primitive11_24_th_corr_mem_V_read(primitive11_24_th_corr_mem_V_read),
.primitive11_25_th_corr_mem_V_read(primitive11_25_th_corr_mem_V_read),
.primitive11_26_th_corr_mem_V_read(primitive11_26_th_corr_mem_V_read),
.primitive11_27_th_corr_mem_V_read(primitive11_27_th_corr_mem_V_read),
.primitive11_28_th_corr_mem_V_read(primitive11_28_th_corr_mem_V_read),
.primitive11_29_th_corr_mem_V_read(primitive11_29_th_corr_mem_V_read),
.primitive11_30_th_corr_mem_V_read(primitive11_30_th_corr_mem_V_read),
.primitive11_31_th_corr_mem_V_read(primitive11_31_th_corr_mem_V_read),
.primitive11_32_th_corr_mem_V_read(primitive11_32_th_corr_mem_V_read),
.primitive11_33_th_corr_mem_V_read(primitive11_33_th_corr_mem_V_read),
.primitive11_34_th_corr_mem_V_read(primitive11_34_th_corr_mem_V_read),
.primitive11_35_th_corr_mem_V_read(primitive11_35_th_corr_mem_V_read),
.primitive11_36_th_corr_mem_V_read(primitive11_36_th_corr_mem_V_read),
.primitive11_37_th_corr_mem_V_read(primitive11_37_th_corr_mem_V_read),
.primitive11_38_th_corr_mem_V_read(primitive11_38_th_corr_mem_V_read),
.primitive11_39_th_corr_mem_V_read(primitive11_39_th_corr_mem_V_read),
.primitive11_40_th_corr_mem_V_read(primitive11_40_th_corr_mem_V_read),
.primitive11_41_th_corr_mem_V_read(primitive11_41_th_corr_mem_V_read),
.primitive11_42_th_corr_mem_V_read(primitive11_42_th_corr_mem_V_read),
.primitive11_43_th_corr_mem_V_read(primitive11_43_th_corr_mem_V_read),
.primitive11_44_th_corr_mem_V_read(primitive11_44_th_corr_mem_V_read),
.primitive11_45_th_corr_mem_V_read(primitive11_45_th_corr_mem_V_read),
.primitive11_46_th_corr_mem_V_read(primitive11_46_th_corr_mem_V_read),
.primitive11_47_th_corr_mem_V_read(primitive11_47_th_corr_mem_V_read),
.primitive11_48_th_corr_mem_V_read(primitive11_48_th_corr_mem_V_read),
.primitive11_49_th_corr_mem_V_read(primitive11_49_th_corr_mem_V_read),
.primitive11_50_th_corr_mem_V_read(primitive11_50_th_corr_mem_V_read),
.primitive11_51_th_corr_mem_V_read(primitive11_51_th_corr_mem_V_read),
.primitive11_52_th_corr_mem_V_read(primitive11_52_th_corr_mem_V_read),
.primitive11_53_th_corr_mem_V_read(primitive11_53_th_corr_mem_V_read),
.primitive11_54_th_corr_mem_V_read(primitive11_54_th_corr_mem_V_read),
.primitive11_55_th_corr_mem_V_read(primitive11_55_th_corr_mem_V_read),
.primitive11_56_th_corr_mem_V_read(primitive11_56_th_corr_mem_V_read),
.primitive11_57_th_corr_mem_V_read(primitive11_57_th_corr_mem_V_read),
.primitive11_58_th_corr_mem_V_read(primitive11_58_th_corr_mem_V_read),
.primitive11_59_th_corr_mem_V_read(primitive11_59_th_corr_mem_V_read),
.primitive11_60_th_corr_mem_V_read(primitive11_60_th_corr_mem_V_read),
.primitive11_61_th_corr_mem_V_read(primitive11_61_th_corr_mem_V_read),
.primitive11_62_th_corr_mem_V_read(primitive11_62_th_corr_mem_V_read),
.primitive11_63_th_corr_mem_V_read(primitive11_63_th_corr_mem_V_read),
.primitive11_64_th_corr_mem_V_read(primitive11_64_th_corr_mem_V_read),
.primitive11_65_th_corr_mem_V_read(primitive11_65_th_corr_mem_V_read),
.primitive11_66_th_corr_mem_V_read(primitive11_66_th_corr_mem_V_read),
.primitive11_67_th_corr_mem_V_read(primitive11_67_th_corr_mem_V_read),
.primitive11_68_th_corr_mem_V_read(primitive11_68_th_corr_mem_V_read),
.primitive11_69_th_corr_mem_V_read(primitive11_69_th_corr_mem_V_read),
.primitive11_70_th_corr_mem_V_read(primitive11_70_th_corr_mem_V_read),
.primitive11_71_th_corr_mem_V_read(primitive11_71_th_corr_mem_V_read),
.primitive11_72_th_corr_mem_V_read(primitive11_72_th_corr_mem_V_read),
.primitive11_73_th_corr_mem_V_read(primitive11_73_th_corr_mem_V_read),
.primitive11_74_th_corr_mem_V_read(primitive11_74_th_corr_mem_V_read),
.primitive11_75_th_corr_mem_V_read(primitive11_75_th_corr_mem_V_read),
.primitive11_76_th_corr_mem_V_read(primitive11_76_th_corr_mem_V_read),
.primitive11_77_th_corr_mem_V_read(primitive11_77_th_corr_mem_V_read),
.primitive11_78_th_corr_mem_V_read(primitive11_78_th_corr_mem_V_read),
.primitive11_79_th_corr_mem_V_read(primitive11_79_th_corr_mem_V_read),
.primitive11_80_th_corr_mem_V_read(primitive11_80_th_corr_mem_V_read),
.primitive11_81_th_corr_mem_V_read(primitive11_81_th_corr_mem_V_read),
.primitive11_82_th_corr_mem_V_read(primitive11_82_th_corr_mem_V_read),
.primitive11_83_th_corr_mem_V_read(primitive11_83_th_corr_mem_V_read),
.primitive11_84_th_corr_mem_V_read(primitive11_84_th_corr_mem_V_read),
.primitive11_85_th_corr_mem_V_read(primitive11_85_th_corr_mem_V_read),
.primitive11_86_th_corr_mem_V_read(primitive11_86_th_corr_mem_V_read),
.primitive11_87_th_corr_mem_V_read(primitive11_87_th_corr_mem_V_read),
.primitive11_88_th_corr_mem_V_read(primitive11_88_th_corr_mem_V_read),
.primitive11_89_th_corr_mem_V_read(primitive11_89_th_corr_mem_V_read),
.primitive11_90_th_corr_mem_V_read(primitive11_90_th_corr_mem_V_read),
.primitive11_91_th_corr_mem_V_read(primitive11_91_th_corr_mem_V_read),
.primitive11_92_th_corr_mem_V_read(primitive11_92_th_corr_mem_V_read),
.primitive11_93_th_corr_mem_V_read(primitive11_93_th_corr_mem_V_read),
.primitive11_94_th_corr_mem_V_read(primitive11_94_th_corr_mem_V_read),
.primitive11_95_th_corr_mem_V_read(primitive11_95_th_corr_mem_V_read),
.primitive11_96_th_corr_mem_V_read(primitive11_96_th_corr_mem_V_read),
.primitive11_97_th_corr_mem_V_read(primitive11_97_th_corr_mem_V_read),
.primitive11_98_th_corr_mem_V_read(primitive11_98_th_corr_mem_V_read),
.primitive11_99_th_corr_mem_V_read(primitive11_99_th_corr_mem_V_read),
.primitive11_100_th_corr_mem_V_read(primitive11_100_th_corr_mem_V_read),
.primitive11_101_th_corr_mem_V_read(primitive11_101_th_corr_mem_V_read),
.primitive11_102_th_corr_mem_V_read(primitive11_102_th_corr_mem_V_read),
.primitive11_103_th_corr_mem_V_read(primitive11_103_th_corr_mem_V_read),
.primitive11_104_th_corr_mem_V_read(primitive11_104_th_corr_mem_V_read),
.primitive11_105_th_corr_mem_V_read(primitive11_105_th_corr_mem_V_read),
.primitive11_106_th_corr_mem_V_read(primitive11_106_th_corr_mem_V_read),
.primitive11_107_th_corr_mem_V_read(primitive11_107_th_corr_mem_V_read),
.primitive11_108_th_corr_mem_V_read(primitive11_108_th_corr_mem_V_read),
.primitive11_109_th_corr_mem_V_read(primitive11_109_th_corr_mem_V_read),
.primitive11_110_th_corr_mem_V_read(primitive11_110_th_corr_mem_V_read),
.primitive11_111_th_corr_mem_V_read(primitive11_111_th_corr_mem_V_read),
.primitive11_112_th_corr_mem_V_read(primitive11_112_th_corr_mem_V_read),
.primitive11_113_th_corr_mem_V_read(primitive11_113_th_corr_mem_V_read),
.primitive11_114_th_corr_mem_V_read(primitive11_114_th_corr_mem_V_read),
.primitive11_115_th_corr_mem_V_read(primitive11_115_th_corr_mem_V_read),
.primitive11_116_th_corr_mem_V_read(primitive11_116_th_corr_mem_V_read),
.primitive11_117_th_corr_mem_V_read(primitive11_117_th_corr_mem_V_read),
.primitive11_118_th_corr_mem_V_read(primitive11_118_th_corr_mem_V_read),
.primitive11_119_th_corr_mem_V_read(primitive11_119_th_corr_mem_V_read),
.primitive11_120_th_corr_mem_V_read(primitive11_120_th_corr_mem_V_read),
.primitive11_121_th_corr_mem_V_read(primitive11_121_th_corr_mem_V_read),
.primitive11_122_th_corr_mem_V_read(primitive11_122_th_corr_mem_V_read),
.primitive11_123_th_corr_mem_V_read(primitive11_123_th_corr_mem_V_read),
.primitive11_124_th_corr_mem_V_read(primitive11_124_th_corr_mem_V_read),
.primitive11_125_th_corr_mem_V_read(primitive11_125_th_corr_mem_V_read),
.primitive11_126_th_corr_mem_V_read(primitive11_126_th_corr_mem_V_read),
.primitive11_127_th_corr_mem_V_read(primitive11_127_th_corr_mem_V_read),
.quality_0_V_read(quality_0_V_read),
.quality_1_V_read(quality_1_V_read),
.wiregroup_0_V_read(wiregroup_0_V_read),
.wiregroup_1_V_read(wiregroup_1_V_read),
.hstrip_0_V_read(hstrip_0_V_read),
.hstrip_1_V_read(hstrip_1_V_read),
.clctpat_0_V_read(clctpat_0_V_read),
.clctpat_1_V_read(clctpat_1_V_read),
.endcap_V(endcap_V),
.ap_return_0(call_ret_sp_prim_conv11_fu_5456_ap_return_0),
.ap_return_1(call_ret_sp_prim_conv11_fu_5456_ap_return_1),
.ap_return_2(call_ret_sp_prim_conv11_fu_5456_ap_return_2),
.ap_return_3(call_ret_sp_prim_conv11_fu_5456_ap_return_3),
.ap_return_4(call_ret_sp_prim_conv11_fu_5456_ap_return_4),
.ap_return_5(call_ret_sp_prim_conv11_fu_5456_ap_return_5)
);
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_0_th_corr_mem_V_w_phi_fu_3565_p4 = primitive11_0_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_0_th_corr_mem_V_w_phi_fu_3565_p4 = call_ret1_sp_mem11_fu_4922_ap_return_134;
end else begin
primitive11_0_th_corr_mem_V_w_phi_fu_3565_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_0_th_mem_V_write_s_phi_fu_2415_p4 = primitive11_0_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_0_th_mem_V_write_s_phi_fu_2415_p4 = call_ret1_sp_mem11_fu_4922_ap_return_6;
end else begin
primitive11_0_th_mem_V_write_s_phi_fu_2415_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_100_th_corr_mem_V_phi_fu_4605_p4 = primitive11_100_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_100_th_corr_mem_V_phi_fu_4605_p4 = call_ret1_sp_mem11_fu_4922_ap_return_234;
end else begin
primitive11_100_th_corr_mem_V_phi_fu_4605_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_100_th_mem_V_writ_phi_fu_3145_p4 = primitive11_100_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_100_th_mem_V_writ_phi_fu_3145_p4 = call_ret1_sp_mem11_fu_4922_ap_return_106;
end else begin
primitive11_100_th_mem_V_writ_phi_fu_3145_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_101_th_corr_mem_V_phi_fu_4575_p4 = primitive11_101_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_101_th_corr_mem_V_phi_fu_4575_p4 = call_ret1_sp_mem11_fu_4922_ap_return_235;
end else begin
primitive11_101_th_corr_mem_V_phi_fu_4575_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_101_th_mem_V_writ_phi_fu_3155_p4 = primitive11_101_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_101_th_mem_V_writ_phi_fu_3155_p4 = call_ret1_sp_mem11_fu_4922_ap_return_107;
end else begin
primitive11_101_th_mem_V_writ_phi_fu_3155_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_102_th_corr_mem_V_phi_fu_4545_p4 = primitive11_102_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_102_th_corr_mem_V_phi_fu_4545_p4 = call_ret1_sp_mem11_fu_4922_ap_return_236;
end else begin
primitive11_102_th_corr_mem_V_phi_fu_4545_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_102_th_mem_V_writ_phi_fu_3175_p4 = primitive11_102_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_102_th_mem_V_writ_phi_fu_3175_p4 = call_ret1_sp_mem11_fu_4922_ap_return_108;
end else begin
primitive11_102_th_mem_V_writ_phi_fu_3175_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_103_th_corr_mem_V_phi_fu_4515_p4 = primitive11_103_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_103_th_corr_mem_V_phi_fu_4515_p4 = call_ret1_sp_mem11_fu_4922_ap_return_237;
end else begin
primitive11_103_th_corr_mem_V_phi_fu_4515_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_103_th_mem_V_writ_phi_fu_3185_p4 = primitive11_103_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_103_th_mem_V_writ_phi_fu_3185_p4 = call_ret1_sp_mem11_fu_4922_ap_return_109;
end else begin
primitive11_103_th_mem_V_writ_phi_fu_3185_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_104_th_corr_mem_V_phi_fu_4485_p4 = primitive11_104_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_104_th_corr_mem_V_phi_fu_4485_p4 = call_ret1_sp_mem11_fu_4922_ap_return_238;
end else begin
primitive11_104_th_corr_mem_V_phi_fu_4485_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_104_th_mem_V_writ_phi_fu_3205_p4 = primitive11_104_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_104_th_mem_V_writ_phi_fu_3205_p4 = call_ret1_sp_mem11_fu_4922_ap_return_110;
end else begin
primitive11_104_th_mem_V_writ_phi_fu_3205_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_105_th_corr_mem_V_phi_fu_4465_p4 = primitive11_105_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_105_th_corr_mem_V_phi_fu_4465_p4 = call_ret1_sp_mem11_fu_4922_ap_return_239;
end else begin
primitive11_105_th_corr_mem_V_phi_fu_4465_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_105_th_mem_V_writ_phi_fu_3215_p4 = primitive11_105_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_105_th_mem_V_writ_phi_fu_3215_p4 = call_ret1_sp_mem11_fu_4922_ap_return_111;
end else begin
primitive11_105_th_mem_V_writ_phi_fu_3215_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_106_th_corr_mem_V_phi_fu_4475_p4 = primitive11_106_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_106_th_corr_mem_V_phi_fu_4475_p4 = call_ret1_sp_mem11_fu_4922_ap_return_240;
end else begin
primitive11_106_th_corr_mem_V_phi_fu_4475_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_106_th_mem_V_writ_phi_fu_3235_p4 = primitive11_106_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_106_th_mem_V_writ_phi_fu_3235_p4 = call_ret1_sp_mem11_fu_4922_ap_return_112;
end else begin
primitive11_106_th_mem_V_writ_phi_fu_3235_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_107_th_corr_mem_V_phi_fu_4495_p4 = primitive11_107_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_107_th_corr_mem_V_phi_fu_4495_p4 = call_ret1_sp_mem11_fu_4922_ap_return_241;
end else begin
primitive11_107_th_corr_mem_V_phi_fu_4495_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_107_th_mem_V_writ_phi_fu_3245_p4 = primitive11_107_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_107_th_mem_V_writ_phi_fu_3245_p4 = call_ret1_sp_mem11_fu_4922_ap_return_113;
end else begin
primitive11_107_th_mem_V_writ_phi_fu_3245_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_108_th_corr_mem_V_phi_fu_4505_p4 = primitive11_108_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_108_th_corr_mem_V_phi_fu_4505_p4 = call_ret1_sp_mem11_fu_4922_ap_return_242;
end else begin
primitive11_108_th_corr_mem_V_phi_fu_4505_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_108_th_mem_V_writ_phi_fu_3265_p4 = primitive11_108_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_108_th_mem_V_writ_phi_fu_3265_p4 = call_ret1_sp_mem11_fu_4922_ap_return_114;
end else begin
primitive11_108_th_mem_V_writ_phi_fu_3265_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_109_th_corr_mem_V_phi_fu_4525_p4 = primitive11_109_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_109_th_corr_mem_V_phi_fu_4525_p4 = call_ret1_sp_mem11_fu_4922_ap_return_243;
end else begin
primitive11_109_th_corr_mem_V_phi_fu_4525_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_109_th_mem_V_writ_phi_fu_3275_p4 = primitive11_109_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_109_th_mem_V_writ_phi_fu_3275_p4 = call_ret1_sp_mem11_fu_4922_ap_return_115;
end else begin
primitive11_109_th_mem_V_writ_phi_fu_3275_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_10_th_corr_mem_V_s_phi_fu_3545_p4 = primitive11_10_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_10_th_corr_mem_V_s_phi_fu_3545_p4 = call_ret1_sp_mem11_fu_4922_ap_return_144;
end else begin
primitive11_10_th_corr_mem_V_s_phi_fu_3545_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_10_th_mem_V_write_phi_fu_2305_p4 = primitive11_10_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_10_th_mem_V_write_phi_fu_2305_p4 = call_ret1_sp_mem11_fu_4922_ap_return_16;
end else begin
primitive11_10_th_mem_V_write_phi_fu_2305_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_110_th_corr_mem_V_phi_fu_4535_p4 = primitive11_110_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_110_th_corr_mem_V_phi_fu_4535_p4 = call_ret1_sp_mem11_fu_4922_ap_return_244;
end else begin
primitive11_110_th_corr_mem_V_phi_fu_4535_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_110_th_mem_V_writ_phi_fu_3295_p4 = primitive11_110_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_110_th_mem_V_writ_phi_fu_3295_p4 = call_ret1_sp_mem11_fu_4922_ap_return_116;
end else begin
primitive11_110_th_mem_V_writ_phi_fu_3295_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_111_th_corr_mem_V_phi_fu_4555_p4 = primitive11_111_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_111_th_corr_mem_V_phi_fu_4555_p4 = call_ret1_sp_mem11_fu_4922_ap_return_245;
end else begin
primitive11_111_th_corr_mem_V_phi_fu_4555_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_111_th_mem_V_writ_phi_fu_3305_p4 = primitive11_111_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_111_th_mem_V_writ_phi_fu_3305_p4 = call_ret1_sp_mem11_fu_4922_ap_return_117;
end else begin
primitive11_111_th_mem_V_writ_phi_fu_3305_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_112_th_corr_mem_V_phi_fu_4565_p4 = primitive11_112_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_112_th_corr_mem_V_phi_fu_4565_p4 = call_ret1_sp_mem11_fu_4922_ap_return_246;
end else begin
primitive11_112_th_corr_mem_V_phi_fu_4565_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_112_th_mem_V_writ_phi_fu_3325_p4 = primitive11_112_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_112_th_mem_V_writ_phi_fu_3325_p4 = call_ret1_sp_mem11_fu_4922_ap_return_118;
end else begin
primitive11_112_th_mem_V_writ_phi_fu_3325_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_113_th_corr_mem_V_phi_fu_4585_p4 = primitive11_113_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_113_th_corr_mem_V_phi_fu_4585_p4 = call_ret1_sp_mem11_fu_4922_ap_return_247;
end else begin
primitive11_113_th_corr_mem_V_phi_fu_4585_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_113_th_mem_V_writ_phi_fu_3335_p4 = primitive11_113_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_113_th_mem_V_writ_phi_fu_3335_p4 = call_ret1_sp_mem11_fu_4922_ap_return_119;
end else begin
primitive11_113_th_mem_V_writ_phi_fu_3335_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_114_th_corr_mem_V_phi_fu_4595_p4 = primitive11_114_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_114_th_corr_mem_V_phi_fu_4595_p4 = call_ret1_sp_mem11_fu_4922_ap_return_248;
end else begin
primitive11_114_th_corr_mem_V_phi_fu_4595_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_114_th_mem_V_writ_phi_fu_3355_p4 = primitive11_114_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_114_th_mem_V_writ_phi_fu_3355_p4 = call_ret1_sp_mem11_fu_4922_ap_return_120;
end else begin
primitive11_114_th_mem_V_writ_phi_fu_3355_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_115_th_corr_mem_V_phi_fu_4615_p4 = primitive11_115_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_115_th_corr_mem_V_phi_fu_4615_p4 = call_ret1_sp_mem11_fu_4922_ap_return_249;
end else begin
primitive11_115_th_corr_mem_V_phi_fu_4615_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_115_th_mem_V_writ_phi_fu_3365_p4 = primitive11_115_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_115_th_mem_V_writ_phi_fu_3365_p4 = call_ret1_sp_mem11_fu_4922_ap_return_121;
end else begin
primitive11_115_th_mem_V_writ_phi_fu_3365_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_116_th_corr_mem_V_phi_fu_4625_p4 = primitive11_116_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_116_th_corr_mem_V_phi_fu_4625_p4 = call_ret1_sp_mem11_fu_4922_ap_return_250;
end else begin
primitive11_116_th_corr_mem_V_phi_fu_4625_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_116_th_mem_V_writ_phi_fu_3385_p4 = primitive11_116_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_116_th_mem_V_writ_phi_fu_3385_p4 = call_ret1_sp_mem11_fu_4922_ap_return_122;
end else begin
primitive11_116_th_mem_V_writ_phi_fu_3385_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_117_th_corr_mem_V_phi_fu_4645_p4 = primitive11_117_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_117_th_corr_mem_V_phi_fu_4645_p4 = call_ret1_sp_mem11_fu_4922_ap_return_251;
end else begin
primitive11_117_th_corr_mem_V_phi_fu_4645_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_117_th_mem_V_writ_phi_fu_3395_p4 = primitive11_117_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_117_th_mem_V_writ_phi_fu_3395_p4 = call_ret1_sp_mem11_fu_4922_ap_return_123;
end else begin
primitive11_117_th_mem_V_writ_phi_fu_3395_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_118_th_corr_mem_V_phi_fu_4655_p4 = primitive11_118_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_118_th_corr_mem_V_phi_fu_4655_p4 = call_ret1_sp_mem11_fu_4922_ap_return_252;
end else begin
primitive11_118_th_corr_mem_V_phi_fu_4655_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_118_th_mem_V_writ_phi_fu_3415_p4 = primitive11_118_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_118_th_mem_V_writ_phi_fu_3415_p4 = call_ret1_sp_mem11_fu_4922_ap_return_124;
end else begin
primitive11_118_th_mem_V_writ_phi_fu_3415_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_119_th_corr_mem_V_phi_fu_4675_p4 = primitive11_119_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_119_th_corr_mem_V_phi_fu_4675_p4 = call_ret1_sp_mem11_fu_4922_ap_return_253;
end else begin
primitive11_119_th_corr_mem_V_phi_fu_4675_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_119_th_mem_V_writ_phi_fu_3425_p4 = primitive11_119_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_119_th_mem_V_writ_phi_fu_3425_p4 = call_ret1_sp_mem11_fu_4922_ap_return_125;
end else begin
primitive11_119_th_mem_V_writ_phi_fu_3425_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_11_th_corr_mem_V_s_phi_fu_3555_p4 = primitive11_11_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_11_th_corr_mem_V_s_phi_fu_3555_p4 = call_ret1_sp_mem11_fu_4922_ap_return_145;
end else begin
primitive11_11_th_corr_mem_V_s_phi_fu_3555_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_11_th_mem_V_write_phi_fu_2315_p4 = primitive11_11_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_11_th_mem_V_write_phi_fu_2315_p4 = call_ret1_sp_mem11_fu_4922_ap_return_17;
end else begin
primitive11_11_th_mem_V_write_phi_fu_2315_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_120_th_corr_mem_V_phi_fu_4685_p4 = primitive11_120_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_120_th_corr_mem_V_phi_fu_4685_p4 = call_ret1_sp_mem11_fu_4922_ap_return_254;
end else begin
primitive11_120_th_corr_mem_V_phi_fu_4685_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_120_th_mem_V_writ_phi_fu_3445_p4 = primitive11_120_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_120_th_mem_V_writ_phi_fu_3445_p4 = call_ret1_sp_mem11_fu_4922_ap_return_126;
end else begin
primitive11_120_th_mem_V_writ_phi_fu_3445_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_121_th_corr_mem_V_phi_fu_4705_p4 = primitive11_121_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_121_th_corr_mem_V_phi_fu_4705_p4 = call_ret1_sp_mem11_fu_4922_ap_return_255;
end else begin
primitive11_121_th_corr_mem_V_phi_fu_4705_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_121_th_mem_V_writ_phi_fu_3775_p4 = primitive11_121_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_121_th_mem_V_writ_phi_fu_3775_p4 = call_ret1_sp_mem11_fu_4922_ap_return_127;
end else begin
primitive11_121_th_mem_V_writ_phi_fu_3775_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_122_th_corr_mem_V_phi_fu_4715_p4 = primitive11_122_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_122_th_corr_mem_V_phi_fu_4715_p4 = call_ret1_sp_mem11_fu_4922_ap_return_256;
end else begin
primitive11_122_th_corr_mem_V_phi_fu_4715_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_122_th_mem_V_writ_phi_fu_3745_p4 = primitive11_122_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_122_th_mem_V_writ_phi_fu_3745_p4 = call_ret1_sp_mem11_fu_4922_ap_return_128;
end else begin
primitive11_122_th_mem_V_writ_phi_fu_3745_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_123_th_corr_mem_V_phi_fu_4735_p4 = primitive11_123_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_123_th_corr_mem_V_phi_fu_4735_p4 = call_ret1_sp_mem11_fu_4922_ap_return_257;
end else begin
primitive11_123_th_corr_mem_V_phi_fu_4735_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_123_th_mem_V_writ_phi_fu_3715_p4 = primitive11_123_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_123_th_mem_V_writ_phi_fu_3715_p4 = call_ret1_sp_mem11_fu_4922_ap_return_129;
end else begin
primitive11_123_th_mem_V_writ_phi_fu_3715_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_124_th_corr_mem_V_phi_fu_4745_p4 = primitive11_124_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_124_th_corr_mem_V_phi_fu_4745_p4 = call_ret1_sp_mem11_fu_4922_ap_return_258;
end else begin
primitive11_124_th_corr_mem_V_phi_fu_4745_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_124_th_mem_V_writ_phi_fu_3685_p4 = primitive11_124_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_124_th_mem_V_writ_phi_fu_3685_p4 = call_ret1_sp_mem11_fu_4922_ap_return_130;
end else begin
primitive11_124_th_mem_V_writ_phi_fu_3685_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_125_th_corr_mem_V_phi_fu_4765_p4 = primitive11_125_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_125_th_corr_mem_V_phi_fu_4765_p4 = call_ret1_sp_mem11_fu_4922_ap_return_259;
end else begin
primitive11_125_th_corr_mem_V_phi_fu_4765_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_125_th_mem_V_writ_phi_fu_3655_p4 = primitive11_125_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_125_th_mem_V_writ_phi_fu_3655_p4 = call_ret1_sp_mem11_fu_4922_ap_return_131;
end else begin
primitive11_125_th_mem_V_writ_phi_fu_3655_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_126_th_corr_mem_V_phi_fu_4775_p4 = primitive11_126_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_126_th_corr_mem_V_phi_fu_4775_p4 = call_ret1_sp_mem11_fu_4922_ap_return_260;
end else begin
primitive11_126_th_corr_mem_V_phi_fu_4775_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_126_th_mem_V_writ_phi_fu_3625_p4 = primitive11_126_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_126_th_mem_V_writ_phi_fu_3625_p4 = call_ret1_sp_mem11_fu_4922_ap_return_132;
end else begin
primitive11_126_th_mem_V_writ_phi_fu_3625_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_127_th_corr_mem_V_phi_fu_4795_p4 = primitive11_127_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_127_th_corr_mem_V_phi_fu_4795_p4 = call_ret1_sp_mem11_fu_4922_ap_return_261;
end else begin
primitive11_127_th_corr_mem_V_phi_fu_4795_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_127_th_mem_V_writ_phi_fu_3595_p4 = primitive11_127_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_127_th_mem_V_writ_phi_fu_3595_p4 = call_ret1_sp_mem11_fu_4922_ap_return_133;
end else begin
primitive11_127_th_mem_V_writ_phi_fu_3595_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_12_th_corr_mem_V_s_phi_fu_3575_p4 = primitive11_12_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_12_th_corr_mem_V_s_phi_fu_3575_p4 = call_ret1_sp_mem11_fu_4922_ap_return_146;
end else begin
primitive11_12_th_corr_mem_V_s_phi_fu_3575_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_12_th_mem_V_write_phi_fu_2335_p4 = primitive11_12_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_12_th_mem_V_write_phi_fu_2335_p4 = call_ret1_sp_mem11_fu_4922_ap_return_18;
end else begin
primitive11_12_th_mem_V_write_phi_fu_2335_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_13_th_corr_mem_V_s_phi_fu_3585_p4 = primitive11_13_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_13_th_corr_mem_V_s_phi_fu_3585_p4 = call_ret1_sp_mem11_fu_4922_ap_return_147;
end else begin
primitive11_13_th_corr_mem_V_s_phi_fu_3585_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_13_th_mem_V_write_phi_fu_2345_p4 = primitive11_13_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_13_th_mem_V_write_phi_fu_2345_p4 = call_ret1_sp_mem11_fu_4922_ap_return_19;
end else begin
primitive11_13_th_mem_V_write_phi_fu_2345_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_14_th_corr_mem_V_s_phi_fu_3605_p4 = primitive11_14_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_14_th_corr_mem_V_s_phi_fu_3605_p4 = call_ret1_sp_mem11_fu_4922_ap_return_148;
end else begin
primitive11_14_th_corr_mem_V_s_phi_fu_3605_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_14_th_mem_V_write_phi_fu_2365_p4 = primitive11_14_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_14_th_mem_V_write_phi_fu_2365_p4 = call_ret1_sp_mem11_fu_4922_ap_return_20;
end else begin
primitive11_14_th_mem_V_write_phi_fu_2365_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_15_th_corr_mem_V_s_phi_fu_3615_p4 = primitive11_15_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_15_th_corr_mem_V_s_phi_fu_3615_p4 = call_ret1_sp_mem11_fu_4922_ap_return_149;
end else begin
primitive11_15_th_corr_mem_V_s_phi_fu_3615_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_15_th_mem_V_write_phi_fu_2375_p4 = primitive11_15_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_15_th_mem_V_write_phi_fu_2375_p4 = call_ret1_sp_mem11_fu_4922_ap_return_21;
end else begin
primitive11_15_th_mem_V_write_phi_fu_2375_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_16_th_corr_mem_V_s_phi_fu_3635_p4 = primitive11_16_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_16_th_corr_mem_V_s_phi_fu_3635_p4 = call_ret1_sp_mem11_fu_4922_ap_return_150;
end else begin
primitive11_16_th_corr_mem_V_s_phi_fu_3635_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_16_th_mem_V_write_phi_fu_2395_p4 = primitive11_16_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_16_th_mem_V_write_phi_fu_2395_p4 = call_ret1_sp_mem11_fu_4922_ap_return_22;
end else begin
primitive11_16_th_mem_V_write_phi_fu_2395_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_17_th_corr_mem_V_s_phi_fu_3645_p4 = primitive11_17_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_17_th_corr_mem_V_s_phi_fu_3645_p4 = call_ret1_sp_mem11_fu_4922_ap_return_151;
end else begin
primitive11_17_th_corr_mem_V_s_phi_fu_3645_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_17_th_mem_V_write_phi_fu_2405_p4 = primitive11_17_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_17_th_mem_V_write_phi_fu_2405_p4 = call_ret1_sp_mem11_fu_4922_ap_return_23;
end else begin
primitive11_17_th_mem_V_write_phi_fu_2405_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_18_th_corr_mem_V_s_phi_fu_3665_p4 = primitive11_18_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_18_th_corr_mem_V_s_phi_fu_3665_p4 = call_ret1_sp_mem11_fu_4922_ap_return_152;
end else begin
primitive11_18_th_corr_mem_V_s_phi_fu_3665_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_18_th_mem_V_write_phi_fu_2425_p4 = primitive11_18_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_18_th_mem_V_write_phi_fu_2425_p4 = call_ret1_sp_mem11_fu_4922_ap_return_24;
end else begin
primitive11_18_th_mem_V_write_phi_fu_2425_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_19_th_corr_mem_V_s_phi_fu_3675_p4 = primitive11_19_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_19_th_corr_mem_V_s_phi_fu_3675_p4 = call_ret1_sp_mem11_fu_4922_ap_return_153;
end else begin
primitive11_19_th_corr_mem_V_s_phi_fu_3675_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_19_th_mem_V_write_phi_fu_2435_p4 = primitive11_19_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_19_th_mem_V_write_phi_fu_2435_p4 = call_ret1_sp_mem11_fu_4922_ap_return_25;
end else begin
primitive11_19_th_mem_V_write_phi_fu_2435_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_1_th_corr_mem_V_w_phi_fu_3535_p4 = primitive11_1_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_1_th_corr_mem_V_w_phi_fu_3535_p4 = call_ret1_sp_mem11_fu_4922_ap_return_135;
end else begin
primitive11_1_th_corr_mem_V_w_phi_fu_3535_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_1_th_mem_V_write_s_phi_fu_2385_p4 = primitive11_1_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_1_th_mem_V_write_s_phi_fu_2385_p4 = call_ret1_sp_mem11_fu_4922_ap_return_7;
end else begin
primitive11_1_th_mem_V_write_s_phi_fu_2385_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_20_th_corr_mem_V_s_phi_fu_3695_p4 = primitive11_20_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_20_th_corr_mem_V_s_phi_fu_3695_p4 = call_ret1_sp_mem11_fu_4922_ap_return_154;
end else begin
primitive11_20_th_corr_mem_V_s_phi_fu_3695_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_20_th_mem_V_write_phi_fu_2765_p4 = primitive11_20_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_20_th_mem_V_write_phi_fu_2765_p4 = call_ret1_sp_mem11_fu_4922_ap_return_26;
end else begin
primitive11_20_th_mem_V_write_phi_fu_2765_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_21_th_corr_mem_V_s_phi_fu_3705_p4 = primitive11_21_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_21_th_corr_mem_V_s_phi_fu_3705_p4 = call_ret1_sp_mem11_fu_4922_ap_return_155;
end else begin
primitive11_21_th_corr_mem_V_s_phi_fu_3705_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_21_th_mem_V_write_phi_fu_2735_p4 = primitive11_21_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_21_th_mem_V_write_phi_fu_2735_p4 = call_ret1_sp_mem11_fu_4922_ap_return_27;
end else begin
primitive11_21_th_mem_V_write_phi_fu_2735_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_22_th_corr_mem_V_s_phi_fu_3725_p4 = primitive11_22_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_22_th_corr_mem_V_s_phi_fu_3725_p4 = call_ret1_sp_mem11_fu_4922_ap_return_156;
end else begin
primitive11_22_th_corr_mem_V_s_phi_fu_3725_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_22_th_mem_V_write_phi_fu_2705_p4 = primitive11_22_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_22_th_mem_V_write_phi_fu_2705_p4 = call_ret1_sp_mem11_fu_4922_ap_return_28;
end else begin
primitive11_22_th_mem_V_write_phi_fu_2705_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_23_th_corr_mem_V_s_phi_fu_3735_p4 = primitive11_23_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_23_th_corr_mem_V_s_phi_fu_3735_p4 = call_ret1_sp_mem11_fu_4922_ap_return_157;
end else begin
primitive11_23_th_corr_mem_V_s_phi_fu_3735_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_23_th_mem_V_write_phi_fu_2675_p4 = primitive11_23_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_23_th_mem_V_write_phi_fu_2675_p4 = call_ret1_sp_mem11_fu_4922_ap_return_29;
end else begin
primitive11_23_th_mem_V_write_phi_fu_2675_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_24_th_corr_mem_V_s_phi_fu_3755_p4 = primitive11_24_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_24_th_corr_mem_V_s_phi_fu_3755_p4 = call_ret1_sp_mem11_fu_4922_ap_return_158;
end else begin
primitive11_24_th_corr_mem_V_s_phi_fu_3755_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_24_th_mem_V_write_phi_fu_2645_p4 = primitive11_24_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_24_th_mem_V_write_phi_fu_2645_p4 = call_ret1_sp_mem11_fu_4922_ap_return_30;
end else begin
primitive11_24_th_mem_V_write_phi_fu_2645_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_25_th_corr_mem_V_s_phi_fu_3765_p4 = primitive11_25_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_25_th_corr_mem_V_s_phi_fu_3765_p4 = call_ret1_sp_mem11_fu_4922_ap_return_159;
end else begin
primitive11_25_th_corr_mem_V_s_phi_fu_3765_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_25_th_mem_V_write_phi_fu_2615_p4 = primitive11_25_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_25_th_mem_V_write_phi_fu_2615_p4 = call_ret1_sp_mem11_fu_4922_ap_return_31;
end else begin
primitive11_25_th_mem_V_write_phi_fu_2615_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_26_th_corr_mem_V_s_phi_fu_3785_p4 = primitive11_26_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_26_th_corr_mem_V_s_phi_fu_3785_p4 = call_ret1_sp_mem11_fu_4922_ap_return_160;
end else begin
primitive11_26_th_corr_mem_V_s_phi_fu_3785_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_26_th_mem_V_write_phi_fu_2585_p4 = primitive11_26_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_26_th_mem_V_write_phi_fu_2585_p4 = call_ret1_sp_mem11_fu_4922_ap_return_32;
end else begin
primitive11_26_th_mem_V_write_phi_fu_2585_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_27_th_corr_mem_V_s_phi_fu_4105_p4 = primitive11_27_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_27_th_corr_mem_V_s_phi_fu_4105_p4 = call_ret1_sp_mem11_fu_4922_ap_return_161;
end else begin
primitive11_27_th_corr_mem_V_s_phi_fu_4105_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_27_th_mem_V_write_phi_fu_2555_p4 = primitive11_27_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_27_th_mem_V_write_phi_fu_2555_p4 = call_ret1_sp_mem11_fu_4922_ap_return_33;
end else begin
primitive11_27_th_mem_V_write_phi_fu_2555_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_28_th_corr_mem_V_s_phi_fu_4075_p4 = primitive11_28_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_28_th_corr_mem_V_s_phi_fu_4075_p4 = call_ret1_sp_mem11_fu_4922_ap_return_162;
end else begin
primitive11_28_th_corr_mem_V_s_phi_fu_4075_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_28_th_mem_V_write_phi_fu_2525_p4 = primitive11_28_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_28_th_mem_V_write_phi_fu_2525_p4 = call_ret1_sp_mem11_fu_4922_ap_return_34;
end else begin
primitive11_28_th_mem_V_write_phi_fu_2525_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_29_th_corr_mem_V_s_phi_fu_4045_p4 = primitive11_29_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_29_th_corr_mem_V_s_phi_fu_4045_p4 = call_ret1_sp_mem11_fu_4922_ap_return_163;
end else begin
primitive11_29_th_corr_mem_V_s_phi_fu_4045_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_29_th_mem_V_write_phi_fu_2495_p4 = primitive11_29_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_29_th_mem_V_write_phi_fu_2495_p4 = call_ret1_sp_mem11_fu_4922_ap_return_35;
end else begin
primitive11_29_th_mem_V_write_phi_fu_2495_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_2_th_corr_mem_V_w_phi_fu_3505_p4 = primitive11_2_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_2_th_corr_mem_V_w_phi_fu_3505_p4 = call_ret1_sp_mem11_fu_4922_ap_return_136;
end else begin
primitive11_2_th_corr_mem_V_w_phi_fu_3505_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_2_th_mem_V_write_s_phi_fu_2355_p4 = primitive11_2_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_2_th_mem_V_write_s_phi_fu_2355_p4 = call_ret1_sp_mem11_fu_4922_ap_return_8;
end else begin
primitive11_2_th_mem_V_write_s_phi_fu_2355_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_30_th_corr_mem_V_s_phi_fu_4015_p4 = primitive11_30_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_30_th_corr_mem_V_s_phi_fu_4015_p4 = call_ret1_sp_mem11_fu_4922_ap_return_164;
end else begin
primitive11_30_th_corr_mem_V_s_phi_fu_4015_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_30_th_mem_V_write_phi_fu_2465_p4 = primitive11_30_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_30_th_mem_V_write_phi_fu_2465_p4 = call_ret1_sp_mem11_fu_4922_ap_return_36;
end else begin
primitive11_30_th_mem_V_write_phi_fu_2465_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_31_th_corr_mem_V_s_phi_fu_3985_p4 = primitive11_31_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_31_th_corr_mem_V_s_phi_fu_3985_p4 = call_ret1_sp_mem11_fu_4922_ap_return_165;
end else begin
primitive11_31_th_corr_mem_V_s_phi_fu_3985_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_31_th_mem_V_write_phi_fu_2445_p4 = primitive11_31_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_31_th_mem_V_write_phi_fu_2445_p4 = call_ret1_sp_mem11_fu_4922_ap_return_37;
end else begin
primitive11_31_th_mem_V_write_phi_fu_2445_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_32_th_corr_mem_V_s_phi_fu_3955_p4 = primitive11_32_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_32_th_corr_mem_V_s_phi_fu_3955_p4 = call_ret1_sp_mem11_fu_4922_ap_return_166;
end else begin
primitive11_32_th_corr_mem_V_s_phi_fu_3955_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_32_th_mem_V_write_phi_fu_2455_p4 = primitive11_32_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_32_th_mem_V_write_phi_fu_2455_p4 = call_ret1_sp_mem11_fu_4922_ap_return_38;
end else begin
primitive11_32_th_mem_V_write_phi_fu_2455_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_33_th_corr_mem_V_s_phi_fu_3925_p4 = primitive11_33_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_33_th_corr_mem_V_s_phi_fu_3925_p4 = call_ret1_sp_mem11_fu_4922_ap_return_167;
end else begin
primitive11_33_th_corr_mem_V_s_phi_fu_3925_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_33_th_mem_V_write_phi_fu_2475_p4 = primitive11_33_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_33_th_mem_V_write_phi_fu_2475_p4 = call_ret1_sp_mem11_fu_4922_ap_return_39;
end else begin
primitive11_33_th_mem_V_write_phi_fu_2475_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_34_th_corr_mem_V_s_phi_fu_3895_p4 = primitive11_34_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_34_th_corr_mem_V_s_phi_fu_3895_p4 = call_ret1_sp_mem11_fu_4922_ap_return_168;
end else begin
primitive11_34_th_corr_mem_V_s_phi_fu_3895_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_34_th_mem_V_write_phi_fu_2485_p4 = primitive11_34_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_34_th_mem_V_write_phi_fu_2485_p4 = call_ret1_sp_mem11_fu_4922_ap_return_40;
end else begin
primitive11_34_th_mem_V_write_phi_fu_2485_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_35_th_corr_mem_V_s_phi_fu_3865_p4 = primitive11_35_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_35_th_corr_mem_V_s_phi_fu_3865_p4 = call_ret1_sp_mem11_fu_4922_ap_return_169;
end else begin
primitive11_35_th_corr_mem_V_s_phi_fu_3865_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_35_th_mem_V_write_phi_fu_2505_p4 = primitive11_35_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_35_th_mem_V_write_phi_fu_2505_p4 = call_ret1_sp_mem11_fu_4922_ap_return_41;
end else begin
primitive11_35_th_mem_V_write_phi_fu_2505_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_36_th_corr_mem_V_s_phi_fu_3835_p4 = primitive11_36_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_36_th_corr_mem_V_s_phi_fu_3835_p4 = call_ret1_sp_mem11_fu_4922_ap_return_170;
end else begin
primitive11_36_th_corr_mem_V_s_phi_fu_3835_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_36_th_mem_V_write_phi_fu_2515_p4 = primitive11_36_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_36_th_mem_V_write_phi_fu_2515_p4 = call_ret1_sp_mem11_fu_4922_ap_return_42;
end else begin
primitive11_36_th_mem_V_write_phi_fu_2515_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_37_th_corr_mem_V_s_phi_fu_3805_p4 = primitive11_37_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_37_th_corr_mem_V_s_phi_fu_3805_p4 = call_ret1_sp_mem11_fu_4922_ap_return_171;
end else begin
primitive11_37_th_corr_mem_V_s_phi_fu_3805_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_37_th_mem_V_write_phi_fu_2535_p4 = primitive11_37_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_37_th_mem_V_write_phi_fu_2535_p4 = call_ret1_sp_mem11_fu_4922_ap_return_43;
end else begin
primitive11_37_th_mem_V_write_phi_fu_2535_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_38_th_corr_mem_V_s_phi_fu_3795_p4 = primitive11_38_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_38_th_corr_mem_V_s_phi_fu_3795_p4 = call_ret1_sp_mem11_fu_4922_ap_return_172;
end else begin
primitive11_38_th_corr_mem_V_s_phi_fu_3795_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_38_th_mem_V_write_phi_fu_2545_p4 = primitive11_38_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_38_th_mem_V_write_phi_fu_2545_p4 = call_ret1_sp_mem11_fu_4922_ap_return_44;
end else begin
primitive11_38_th_mem_V_write_phi_fu_2545_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_39_th_corr_mem_V_s_phi_fu_3815_p4 = primitive11_39_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_39_th_corr_mem_V_s_phi_fu_3815_p4 = call_ret1_sp_mem11_fu_4922_ap_return_173;
end else begin
primitive11_39_th_corr_mem_V_s_phi_fu_3815_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_39_th_mem_V_write_phi_fu_2565_p4 = primitive11_39_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_39_th_mem_V_write_phi_fu_2565_p4 = call_ret1_sp_mem11_fu_4922_ap_return_45;
end else begin
primitive11_39_th_mem_V_write_phi_fu_2565_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_3_th_corr_mem_V_w_phi_fu_3475_p4 = primitive11_3_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_3_th_corr_mem_V_w_phi_fu_3475_p4 = call_ret1_sp_mem11_fu_4922_ap_return_137;
end else begin
primitive11_3_th_corr_mem_V_w_phi_fu_3475_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_3_th_mem_V_write_s_phi_fu_2325_p4 = primitive11_3_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_3_th_mem_V_write_s_phi_fu_2325_p4 = call_ret1_sp_mem11_fu_4922_ap_return_9;
end else begin
primitive11_3_th_mem_V_write_s_phi_fu_2325_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_40_th_corr_mem_V_s_phi_fu_3825_p4 = primitive11_40_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_40_th_corr_mem_V_s_phi_fu_3825_p4 = call_ret1_sp_mem11_fu_4922_ap_return_174;
end else begin
primitive11_40_th_corr_mem_V_s_phi_fu_3825_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_40_th_mem_V_write_phi_fu_2575_p4 = primitive11_40_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_40_th_mem_V_write_phi_fu_2575_p4 = call_ret1_sp_mem11_fu_4922_ap_return_46;
end else begin
primitive11_40_th_mem_V_write_phi_fu_2575_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_41_th_corr_mem_V_s_phi_fu_3845_p4 = primitive11_41_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_41_th_corr_mem_V_s_phi_fu_3845_p4 = call_ret1_sp_mem11_fu_4922_ap_return_175;
end else begin
primitive11_41_th_corr_mem_V_s_phi_fu_3845_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_41_th_mem_V_write_phi_fu_2595_p4 = primitive11_41_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_41_th_mem_V_write_phi_fu_2595_p4 = call_ret1_sp_mem11_fu_4922_ap_return_47;
end else begin
primitive11_41_th_mem_V_write_phi_fu_2595_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_42_th_corr_mem_V_s_phi_fu_3855_p4 = primitive11_42_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_42_th_corr_mem_V_s_phi_fu_3855_p4 = call_ret1_sp_mem11_fu_4922_ap_return_176;
end else begin
primitive11_42_th_corr_mem_V_s_phi_fu_3855_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_42_th_mem_V_write_phi_fu_2605_p4 = primitive11_42_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_42_th_mem_V_write_phi_fu_2605_p4 = call_ret1_sp_mem11_fu_4922_ap_return_48;
end else begin
primitive11_42_th_mem_V_write_phi_fu_2605_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_43_th_corr_mem_V_s_phi_fu_3875_p4 = primitive11_43_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_43_th_corr_mem_V_s_phi_fu_3875_p4 = call_ret1_sp_mem11_fu_4922_ap_return_177;
end else begin
primitive11_43_th_corr_mem_V_s_phi_fu_3875_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_43_th_mem_V_write_phi_fu_2625_p4 = primitive11_43_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_43_th_mem_V_write_phi_fu_2625_p4 = call_ret1_sp_mem11_fu_4922_ap_return_49;
end else begin
primitive11_43_th_mem_V_write_phi_fu_2625_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_44_th_corr_mem_V_s_phi_fu_3885_p4 = primitive11_44_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_44_th_corr_mem_V_s_phi_fu_3885_p4 = call_ret1_sp_mem11_fu_4922_ap_return_178;
end else begin
primitive11_44_th_corr_mem_V_s_phi_fu_3885_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_44_th_mem_V_write_phi_fu_2635_p4 = primitive11_44_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_44_th_mem_V_write_phi_fu_2635_p4 = call_ret1_sp_mem11_fu_4922_ap_return_50;
end else begin
primitive11_44_th_mem_V_write_phi_fu_2635_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_45_th_corr_mem_V_s_phi_fu_3905_p4 = primitive11_45_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_45_th_corr_mem_V_s_phi_fu_3905_p4 = call_ret1_sp_mem11_fu_4922_ap_return_179;
end else begin
primitive11_45_th_corr_mem_V_s_phi_fu_3905_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_45_th_mem_V_write_phi_fu_2655_p4 = primitive11_45_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_45_th_mem_V_write_phi_fu_2655_p4 = call_ret1_sp_mem11_fu_4922_ap_return_51;
end else begin
primitive11_45_th_mem_V_write_phi_fu_2655_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_46_th_corr_mem_V_s_phi_fu_3915_p4 = primitive11_46_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_46_th_corr_mem_V_s_phi_fu_3915_p4 = call_ret1_sp_mem11_fu_4922_ap_return_180;
end else begin
primitive11_46_th_corr_mem_V_s_phi_fu_3915_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_46_th_mem_V_write_phi_fu_2665_p4 = primitive11_46_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_46_th_mem_V_write_phi_fu_2665_p4 = call_ret1_sp_mem11_fu_4922_ap_return_52;
end else begin
primitive11_46_th_mem_V_write_phi_fu_2665_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_47_th_corr_mem_V_s_phi_fu_3935_p4 = primitive11_47_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_47_th_corr_mem_V_s_phi_fu_3935_p4 = call_ret1_sp_mem11_fu_4922_ap_return_181;
end else begin
primitive11_47_th_corr_mem_V_s_phi_fu_3935_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_47_th_mem_V_write_phi_fu_2685_p4 = primitive11_47_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_47_th_mem_V_write_phi_fu_2685_p4 = call_ret1_sp_mem11_fu_4922_ap_return_53;
end else begin
primitive11_47_th_mem_V_write_phi_fu_2685_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_48_th_corr_mem_V_s_phi_fu_3945_p4 = primitive11_48_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_48_th_corr_mem_V_s_phi_fu_3945_p4 = call_ret1_sp_mem11_fu_4922_ap_return_182;
end else begin
primitive11_48_th_corr_mem_V_s_phi_fu_3945_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_48_th_mem_V_write_phi_fu_2695_p4 = primitive11_48_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_48_th_mem_V_write_phi_fu_2695_p4 = call_ret1_sp_mem11_fu_4922_ap_return_54;
end else begin
primitive11_48_th_mem_V_write_phi_fu_2695_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_49_th_corr_mem_V_s_phi_fu_3965_p4 = primitive11_49_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_49_th_corr_mem_V_s_phi_fu_3965_p4 = call_ret1_sp_mem11_fu_4922_ap_return_183;
end else begin
primitive11_49_th_corr_mem_V_s_phi_fu_3965_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_49_th_mem_V_write_phi_fu_2715_p4 = primitive11_49_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_49_th_mem_V_write_phi_fu_2715_p4 = call_ret1_sp_mem11_fu_4922_ap_return_55;
end else begin
primitive11_49_th_mem_V_write_phi_fu_2715_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_4_th_corr_mem_V_w_phi_fu_3455_p4 = primitive11_4_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_4_th_corr_mem_V_w_phi_fu_3455_p4 = call_ret1_sp_mem11_fu_4922_ap_return_138;
end else begin
primitive11_4_th_corr_mem_V_w_phi_fu_3455_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_4_th_mem_V_write_s_phi_fu_2295_p4 = primitive11_4_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_4_th_mem_V_write_s_phi_fu_2295_p4 = call_ret1_sp_mem11_fu_4922_ap_return_10;
end else begin
primitive11_4_th_mem_V_write_s_phi_fu_2295_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_50_th_corr_mem_V_s_phi_fu_3975_p4 = primitive11_50_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_50_th_corr_mem_V_s_phi_fu_3975_p4 = call_ret1_sp_mem11_fu_4922_ap_return_184;
end else begin
primitive11_50_th_corr_mem_V_s_phi_fu_3975_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_50_th_mem_V_write_phi_fu_2725_p4 = primitive11_50_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_50_th_mem_V_write_phi_fu_2725_p4 = call_ret1_sp_mem11_fu_4922_ap_return_56;
end else begin
primitive11_50_th_mem_V_write_phi_fu_2725_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_51_th_corr_mem_V_s_phi_fu_3995_p4 = primitive11_51_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_51_th_corr_mem_V_s_phi_fu_3995_p4 = call_ret1_sp_mem11_fu_4922_ap_return_185;
end else begin
primitive11_51_th_corr_mem_V_s_phi_fu_3995_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_51_th_mem_V_write_phi_fu_2745_p4 = primitive11_51_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_51_th_mem_V_write_phi_fu_2745_p4 = call_ret1_sp_mem11_fu_4922_ap_return_57;
end else begin
primitive11_51_th_mem_V_write_phi_fu_2745_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_52_th_corr_mem_V_s_phi_fu_4005_p4 = primitive11_52_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_52_th_corr_mem_V_s_phi_fu_4005_p4 = call_ret1_sp_mem11_fu_4922_ap_return_186;
end else begin
primitive11_52_th_corr_mem_V_s_phi_fu_4005_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_52_th_mem_V_write_phi_fu_2755_p4 = primitive11_52_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_52_th_mem_V_write_phi_fu_2755_p4 = call_ret1_sp_mem11_fu_4922_ap_return_58;
end else begin
primitive11_52_th_mem_V_write_phi_fu_2755_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_53_th_corr_mem_V_s_phi_fu_4025_p4 = primitive11_53_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_53_th_corr_mem_V_s_phi_fu_4025_p4 = call_ret1_sp_mem11_fu_4922_ap_return_187;
end else begin
primitive11_53_th_corr_mem_V_s_phi_fu_4025_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_53_th_mem_V_write_phi_fu_2775_p4 = primitive11_53_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_53_th_mem_V_write_phi_fu_2775_p4 = call_ret1_sp_mem11_fu_4922_ap_return_59;
end else begin
primitive11_53_th_mem_V_write_phi_fu_2775_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_54_th_corr_mem_V_s_phi_fu_4035_p4 = primitive11_54_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_54_th_corr_mem_V_s_phi_fu_4035_p4 = call_ret1_sp_mem11_fu_4922_ap_return_188;
end else begin
primitive11_54_th_corr_mem_V_s_phi_fu_4035_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_54_th_mem_V_write_phi_fu_3095_p4 = primitive11_54_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_54_th_mem_V_write_phi_fu_3095_p4 = call_ret1_sp_mem11_fu_4922_ap_return_60;
end else begin
primitive11_54_th_mem_V_write_phi_fu_3095_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_55_th_corr_mem_V_s_phi_fu_4055_p4 = primitive11_55_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_55_th_corr_mem_V_s_phi_fu_4055_p4 = call_ret1_sp_mem11_fu_4922_ap_return_189;
end else begin
primitive11_55_th_corr_mem_V_s_phi_fu_4055_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_55_th_mem_V_write_phi_fu_3065_p4 = primitive11_55_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_55_th_mem_V_write_phi_fu_3065_p4 = call_ret1_sp_mem11_fu_4922_ap_return_61;
end else begin
primitive11_55_th_mem_V_write_phi_fu_3065_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_56_th_corr_mem_V_s_phi_fu_4065_p4 = primitive11_56_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_56_th_corr_mem_V_s_phi_fu_4065_p4 = call_ret1_sp_mem11_fu_4922_ap_return_190;
end else begin
primitive11_56_th_corr_mem_V_s_phi_fu_4065_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_56_th_mem_V_write_phi_fu_3035_p4 = primitive11_56_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_56_th_mem_V_write_phi_fu_3035_p4 = call_ret1_sp_mem11_fu_4922_ap_return_62;
end else begin
primitive11_56_th_mem_V_write_phi_fu_3035_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_57_th_corr_mem_V_s_phi_fu_4085_p4 = primitive11_57_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_57_th_corr_mem_V_s_phi_fu_4085_p4 = call_ret1_sp_mem11_fu_4922_ap_return_191;
end else begin
primitive11_57_th_corr_mem_V_s_phi_fu_4085_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_57_th_mem_V_write_phi_fu_3005_p4 = primitive11_57_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_57_th_mem_V_write_phi_fu_3005_p4 = call_ret1_sp_mem11_fu_4922_ap_return_63;
end else begin
primitive11_57_th_mem_V_write_phi_fu_3005_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_58_th_corr_mem_V_s_phi_fu_4095_p4 = primitive11_58_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_58_th_corr_mem_V_s_phi_fu_4095_p4 = call_ret1_sp_mem11_fu_4922_ap_return_192;
end else begin
primitive11_58_th_corr_mem_V_s_phi_fu_4095_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_58_th_mem_V_write_phi_fu_2975_p4 = primitive11_58_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_58_th_mem_V_write_phi_fu_2975_p4 = call_ret1_sp_mem11_fu_4922_ap_return_64;
end else begin
primitive11_58_th_mem_V_write_phi_fu_2975_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_59_th_corr_mem_V_s_phi_fu_4115_p4 = primitive11_59_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_59_th_corr_mem_V_s_phi_fu_4115_p4 = call_ret1_sp_mem11_fu_4922_ap_return_193;
end else begin
primitive11_59_th_corr_mem_V_s_phi_fu_4115_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_59_th_mem_V_write_phi_fu_2945_p4 = primitive11_59_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_59_th_mem_V_write_phi_fu_2945_p4 = call_ret1_sp_mem11_fu_4922_ap_return_65;
end else begin
primitive11_59_th_mem_V_write_phi_fu_2945_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_5_th_corr_mem_V_w_phi_fu_3465_p4 = primitive11_5_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_5_th_corr_mem_V_w_phi_fu_3465_p4 = call_ret1_sp_mem11_fu_4922_ap_return_139;
end else begin
primitive11_5_th_corr_mem_V_w_phi_fu_3465_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_5_th_mem_V_write_s_phi_fu_2265_p4 = primitive11_5_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_5_th_mem_V_write_s_phi_fu_2265_p4 = call_ret1_sp_mem11_fu_4922_ap_return_11;
end else begin
primitive11_5_th_mem_V_write_s_phi_fu_2265_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_60_th_corr_mem_V_s_phi_fu_4445_p4 = primitive11_60_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_60_th_corr_mem_V_s_phi_fu_4445_p4 = call_ret1_sp_mem11_fu_4922_ap_return_194;
end else begin
primitive11_60_th_corr_mem_V_s_phi_fu_4445_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_60_th_mem_V_write_phi_fu_2915_p4 = primitive11_60_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_60_th_mem_V_write_phi_fu_2915_p4 = call_ret1_sp_mem11_fu_4922_ap_return_66;
end else begin
primitive11_60_th_mem_V_write_phi_fu_2915_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_61_th_corr_mem_V_s_phi_fu_4415_p4 = primitive11_61_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_61_th_corr_mem_V_s_phi_fu_4415_p4 = call_ret1_sp_mem11_fu_4922_ap_return_195;
end else begin
primitive11_61_th_corr_mem_V_s_phi_fu_4415_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_61_th_mem_V_write_phi_fu_2885_p4 = primitive11_61_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_61_th_mem_V_write_phi_fu_2885_p4 = call_ret1_sp_mem11_fu_4922_ap_return_67;
end else begin
primitive11_61_th_mem_V_write_phi_fu_2885_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_62_th_corr_mem_V_s_phi_fu_4385_p4 = primitive11_62_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_62_th_corr_mem_V_s_phi_fu_4385_p4 = call_ret1_sp_mem11_fu_4922_ap_return_196;
end else begin
primitive11_62_th_corr_mem_V_s_phi_fu_4385_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_62_th_mem_V_write_phi_fu_2855_p4 = primitive11_62_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_62_th_mem_V_write_phi_fu_2855_p4 = call_ret1_sp_mem11_fu_4922_ap_return_68;
end else begin
primitive11_62_th_mem_V_write_phi_fu_2855_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_63_th_corr_mem_V_s_phi_fu_4355_p4 = primitive11_63_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_63_th_corr_mem_V_s_phi_fu_4355_p4 = call_ret1_sp_mem11_fu_4922_ap_return_197;
end else begin
primitive11_63_th_corr_mem_V_s_phi_fu_4355_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_63_th_mem_V_write_phi_fu_2825_p4 = primitive11_63_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_63_th_mem_V_write_phi_fu_2825_p4 = call_ret1_sp_mem11_fu_4922_ap_return_69;
end else begin
primitive11_63_th_mem_V_write_phi_fu_2825_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_64_th_corr_mem_V_s_phi_fu_4325_p4 = primitive11_64_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_64_th_corr_mem_V_s_phi_fu_4325_p4 = call_ret1_sp_mem11_fu_4922_ap_return_198;
end else begin
primitive11_64_th_corr_mem_V_s_phi_fu_4325_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_64_th_mem_V_write_phi_fu_2795_p4 = primitive11_64_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_64_th_mem_V_write_phi_fu_2795_p4 = call_ret1_sp_mem11_fu_4922_ap_return_70;
end else begin
primitive11_64_th_mem_V_write_phi_fu_2795_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_65_th_corr_mem_V_s_phi_fu_4295_p4 = primitive11_65_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_65_th_corr_mem_V_s_phi_fu_4295_p4 = call_ret1_sp_mem11_fu_4922_ap_return_199;
end else begin
primitive11_65_th_corr_mem_V_s_phi_fu_4295_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_65_th_mem_V_write_phi_fu_2785_p4 = primitive11_65_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_65_th_mem_V_write_phi_fu_2785_p4 = call_ret1_sp_mem11_fu_4922_ap_return_71;
end else begin
primitive11_65_th_mem_V_write_phi_fu_2785_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_66_th_corr_mem_V_s_phi_fu_4265_p4 = primitive11_66_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_66_th_corr_mem_V_s_phi_fu_4265_p4 = call_ret1_sp_mem11_fu_4922_ap_return_200;
end else begin
primitive11_66_th_corr_mem_V_s_phi_fu_4265_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_66_th_mem_V_write_phi_fu_2805_p4 = primitive11_66_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_66_th_mem_V_write_phi_fu_2805_p4 = call_ret1_sp_mem11_fu_4922_ap_return_72;
end else begin
primitive11_66_th_mem_V_write_phi_fu_2805_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_67_th_corr_mem_V_s_phi_fu_4235_p4 = primitive11_67_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_67_th_corr_mem_V_s_phi_fu_4235_p4 = call_ret1_sp_mem11_fu_4922_ap_return_201;
end else begin
primitive11_67_th_corr_mem_V_s_phi_fu_4235_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_67_th_mem_V_write_phi_fu_2815_p4 = primitive11_67_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_67_th_mem_V_write_phi_fu_2815_p4 = call_ret1_sp_mem11_fu_4922_ap_return_73;
end else begin
primitive11_67_th_mem_V_write_phi_fu_2815_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_68_th_corr_mem_V_s_phi_fu_4205_p4 = primitive11_68_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_68_th_corr_mem_V_s_phi_fu_4205_p4 = call_ret1_sp_mem11_fu_4922_ap_return_202;
end else begin
primitive11_68_th_corr_mem_V_s_phi_fu_4205_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_68_th_mem_V_write_phi_fu_2835_p4 = primitive11_68_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_68_th_mem_V_write_phi_fu_2835_p4 = call_ret1_sp_mem11_fu_4922_ap_return_74;
end else begin
primitive11_68_th_mem_V_write_phi_fu_2835_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_69_th_corr_mem_V_s_phi_fu_4175_p4 = primitive11_69_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_69_th_corr_mem_V_s_phi_fu_4175_p4 = call_ret1_sp_mem11_fu_4922_ap_return_203;
end else begin
primitive11_69_th_corr_mem_V_s_phi_fu_4175_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_69_th_mem_V_write_phi_fu_2845_p4 = primitive11_69_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_69_th_mem_V_write_phi_fu_2845_p4 = call_ret1_sp_mem11_fu_4922_ap_return_75;
end else begin
primitive11_69_th_mem_V_write_phi_fu_2845_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_6_th_corr_mem_V_w_phi_fu_3485_p4 = primitive11_6_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_6_th_corr_mem_V_w_phi_fu_3485_p4 = call_ret1_sp_mem11_fu_4922_ap_return_140;
end else begin
primitive11_6_th_corr_mem_V_w_phi_fu_3485_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_6_th_mem_V_write_s_phi_fu_2245_p4 = primitive11_6_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_6_th_mem_V_write_s_phi_fu_2245_p4 = call_ret1_sp_mem11_fu_4922_ap_return_12;
end else begin
primitive11_6_th_mem_V_write_s_phi_fu_2245_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_70_th_corr_mem_V_s_phi_fu_4145_p4 = primitive11_70_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_70_th_corr_mem_V_s_phi_fu_4145_p4 = call_ret1_sp_mem11_fu_4922_ap_return_204;
end else begin
primitive11_70_th_corr_mem_V_s_phi_fu_4145_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_70_th_mem_V_write_phi_fu_2865_p4 = primitive11_70_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_70_th_mem_V_write_phi_fu_2865_p4 = call_ret1_sp_mem11_fu_4922_ap_return_76;
end else begin
primitive11_70_th_mem_V_write_phi_fu_2865_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_71_th_corr_mem_V_s_phi_fu_4125_p4 = primitive11_71_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_71_th_corr_mem_V_s_phi_fu_4125_p4 = call_ret1_sp_mem11_fu_4922_ap_return_205;
end else begin
primitive11_71_th_corr_mem_V_s_phi_fu_4125_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_71_th_mem_V_write_phi_fu_2875_p4 = primitive11_71_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_71_th_mem_V_write_phi_fu_2875_p4 = call_ret1_sp_mem11_fu_4922_ap_return_77;
end else begin
primitive11_71_th_mem_V_write_phi_fu_2875_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_72_th_corr_mem_V_s_phi_fu_4135_p4 = primitive11_72_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_72_th_corr_mem_V_s_phi_fu_4135_p4 = call_ret1_sp_mem11_fu_4922_ap_return_206;
end else begin
primitive11_72_th_corr_mem_V_s_phi_fu_4135_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_72_th_mem_V_write_phi_fu_2895_p4 = primitive11_72_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_72_th_mem_V_write_phi_fu_2895_p4 = call_ret1_sp_mem11_fu_4922_ap_return_78;
end else begin
primitive11_72_th_mem_V_write_phi_fu_2895_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_73_th_corr_mem_V_s_phi_fu_4155_p4 = primitive11_73_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_73_th_corr_mem_V_s_phi_fu_4155_p4 = call_ret1_sp_mem11_fu_4922_ap_return_207;
end else begin
primitive11_73_th_corr_mem_V_s_phi_fu_4155_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_73_th_mem_V_write_phi_fu_2905_p4 = primitive11_73_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_73_th_mem_V_write_phi_fu_2905_p4 = call_ret1_sp_mem11_fu_4922_ap_return_79;
end else begin
primitive11_73_th_mem_V_write_phi_fu_2905_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_74_th_corr_mem_V_s_phi_fu_4165_p4 = primitive11_74_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_74_th_corr_mem_V_s_phi_fu_4165_p4 = call_ret1_sp_mem11_fu_4922_ap_return_208;
end else begin
primitive11_74_th_corr_mem_V_s_phi_fu_4165_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_74_th_mem_V_write_phi_fu_2925_p4 = primitive11_74_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_74_th_mem_V_write_phi_fu_2925_p4 = call_ret1_sp_mem11_fu_4922_ap_return_80;
end else begin
primitive11_74_th_mem_V_write_phi_fu_2925_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_75_th_corr_mem_V_s_phi_fu_4185_p4 = primitive11_75_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_75_th_corr_mem_V_s_phi_fu_4185_p4 = call_ret1_sp_mem11_fu_4922_ap_return_209;
end else begin
primitive11_75_th_corr_mem_V_s_phi_fu_4185_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_75_th_mem_V_write_phi_fu_2935_p4 = primitive11_75_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_75_th_mem_V_write_phi_fu_2935_p4 = call_ret1_sp_mem11_fu_4922_ap_return_81;
end else begin
primitive11_75_th_mem_V_write_phi_fu_2935_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_76_th_corr_mem_V_s_phi_fu_4195_p4 = primitive11_76_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_76_th_corr_mem_V_s_phi_fu_4195_p4 = call_ret1_sp_mem11_fu_4922_ap_return_210;
end else begin
primitive11_76_th_corr_mem_V_s_phi_fu_4195_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_76_th_mem_V_write_phi_fu_2955_p4 = primitive11_76_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_76_th_mem_V_write_phi_fu_2955_p4 = call_ret1_sp_mem11_fu_4922_ap_return_82;
end else begin
primitive11_76_th_mem_V_write_phi_fu_2955_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_77_th_corr_mem_V_s_phi_fu_4215_p4 = primitive11_77_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_77_th_corr_mem_V_s_phi_fu_4215_p4 = call_ret1_sp_mem11_fu_4922_ap_return_211;
end else begin
primitive11_77_th_corr_mem_V_s_phi_fu_4215_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_77_th_mem_V_write_phi_fu_2965_p4 = primitive11_77_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_77_th_mem_V_write_phi_fu_2965_p4 = call_ret1_sp_mem11_fu_4922_ap_return_83;
end else begin
primitive11_77_th_mem_V_write_phi_fu_2965_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_78_th_corr_mem_V_s_phi_fu_4225_p4 = primitive11_78_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_78_th_corr_mem_V_s_phi_fu_4225_p4 = call_ret1_sp_mem11_fu_4922_ap_return_212;
end else begin
primitive11_78_th_corr_mem_V_s_phi_fu_4225_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_78_th_mem_V_write_phi_fu_2985_p4 = primitive11_78_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_78_th_mem_V_write_phi_fu_2985_p4 = call_ret1_sp_mem11_fu_4922_ap_return_84;
end else begin
primitive11_78_th_mem_V_write_phi_fu_2985_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_79_th_corr_mem_V_s_phi_fu_4245_p4 = primitive11_79_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_79_th_corr_mem_V_s_phi_fu_4245_p4 = call_ret1_sp_mem11_fu_4922_ap_return_213;
end else begin
primitive11_79_th_corr_mem_V_s_phi_fu_4245_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_79_th_mem_V_write_phi_fu_2995_p4 = primitive11_79_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_79_th_mem_V_write_phi_fu_2995_p4 = call_ret1_sp_mem11_fu_4922_ap_return_85;
end else begin
primitive11_79_th_mem_V_write_phi_fu_2995_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_7_th_corr_mem_V_w_phi_fu_3495_p4 = primitive11_7_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_7_th_corr_mem_V_w_phi_fu_3495_p4 = call_ret1_sp_mem11_fu_4922_ap_return_141;
end else begin
primitive11_7_th_corr_mem_V_w_phi_fu_3495_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_7_th_mem_V_write_s_phi_fu_2255_p4 = primitive11_7_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_7_th_mem_V_write_s_phi_fu_2255_p4 = call_ret1_sp_mem11_fu_4922_ap_return_13;
end else begin
primitive11_7_th_mem_V_write_s_phi_fu_2255_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_80_th_corr_mem_V_s_phi_fu_4255_p4 = primitive11_80_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_80_th_corr_mem_V_s_phi_fu_4255_p4 = call_ret1_sp_mem11_fu_4922_ap_return_214;
end else begin
primitive11_80_th_corr_mem_V_s_phi_fu_4255_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_80_th_mem_V_write_phi_fu_3015_p4 = primitive11_80_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_80_th_mem_V_write_phi_fu_3015_p4 = call_ret1_sp_mem11_fu_4922_ap_return_86;
end else begin
primitive11_80_th_mem_V_write_phi_fu_3015_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_81_th_corr_mem_V_s_phi_fu_4275_p4 = primitive11_81_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_81_th_corr_mem_V_s_phi_fu_4275_p4 = call_ret1_sp_mem11_fu_4922_ap_return_215;
end else begin
primitive11_81_th_corr_mem_V_s_phi_fu_4275_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_81_th_mem_V_write_phi_fu_3025_p4 = primitive11_81_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_81_th_mem_V_write_phi_fu_3025_p4 = call_ret1_sp_mem11_fu_4922_ap_return_87;
end else begin
primitive11_81_th_mem_V_write_phi_fu_3025_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_82_th_corr_mem_V_s_phi_fu_4285_p4 = primitive11_82_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_82_th_corr_mem_V_s_phi_fu_4285_p4 = call_ret1_sp_mem11_fu_4922_ap_return_216;
end else begin
primitive11_82_th_corr_mem_V_s_phi_fu_4285_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_82_th_mem_V_write_phi_fu_3045_p4 = primitive11_82_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_82_th_mem_V_write_phi_fu_3045_p4 = call_ret1_sp_mem11_fu_4922_ap_return_88;
end else begin
primitive11_82_th_mem_V_write_phi_fu_3045_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_83_th_corr_mem_V_s_phi_fu_4305_p4 = primitive11_83_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_83_th_corr_mem_V_s_phi_fu_4305_p4 = call_ret1_sp_mem11_fu_4922_ap_return_217;
end else begin
primitive11_83_th_corr_mem_V_s_phi_fu_4305_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_83_th_mem_V_write_phi_fu_3055_p4 = primitive11_83_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_83_th_mem_V_write_phi_fu_3055_p4 = call_ret1_sp_mem11_fu_4922_ap_return_89;
end else begin
primitive11_83_th_mem_V_write_phi_fu_3055_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_84_th_corr_mem_V_s_phi_fu_4315_p4 = primitive11_84_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_84_th_corr_mem_V_s_phi_fu_4315_p4 = call_ret1_sp_mem11_fu_4922_ap_return_218;
end else begin
primitive11_84_th_corr_mem_V_s_phi_fu_4315_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_84_th_mem_V_write_phi_fu_3075_p4 = primitive11_84_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_84_th_mem_V_write_phi_fu_3075_p4 = call_ret1_sp_mem11_fu_4922_ap_return_90;
end else begin
primitive11_84_th_mem_V_write_phi_fu_3075_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_85_th_corr_mem_V_s_phi_fu_4335_p4 = primitive11_85_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_85_th_corr_mem_V_s_phi_fu_4335_p4 = call_ret1_sp_mem11_fu_4922_ap_return_219;
end else begin
primitive11_85_th_corr_mem_V_s_phi_fu_4335_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_85_th_mem_V_write_phi_fu_3085_p4 = primitive11_85_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_85_th_mem_V_write_phi_fu_3085_p4 = call_ret1_sp_mem11_fu_4922_ap_return_91;
end else begin
primitive11_85_th_mem_V_write_phi_fu_3085_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_86_th_corr_mem_V_s_phi_fu_4345_p4 = primitive11_86_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_86_th_corr_mem_V_s_phi_fu_4345_p4 = call_ret1_sp_mem11_fu_4922_ap_return_220;
end else begin
primitive11_86_th_corr_mem_V_s_phi_fu_4345_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_86_th_mem_V_write_phi_fu_3105_p4 = primitive11_86_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_86_th_mem_V_write_phi_fu_3105_p4 = call_ret1_sp_mem11_fu_4922_ap_return_92;
end else begin
primitive11_86_th_mem_V_write_phi_fu_3105_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_87_th_corr_mem_V_s_phi_fu_4365_p4 = primitive11_87_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_87_th_corr_mem_V_s_phi_fu_4365_p4 = call_ret1_sp_mem11_fu_4922_ap_return_221;
end else begin
primitive11_87_th_corr_mem_V_s_phi_fu_4365_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_87_th_mem_V_write_phi_fu_3435_p4 = primitive11_87_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_87_th_mem_V_write_phi_fu_3435_p4 = call_ret1_sp_mem11_fu_4922_ap_return_93;
end else begin
primitive11_87_th_mem_V_write_phi_fu_3435_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_88_th_corr_mem_V_s_phi_fu_4375_p4 = primitive11_88_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_88_th_corr_mem_V_s_phi_fu_4375_p4 = call_ret1_sp_mem11_fu_4922_ap_return_222;
end else begin
primitive11_88_th_corr_mem_V_s_phi_fu_4375_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_88_th_mem_V_write_phi_fu_3405_p4 = primitive11_88_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_88_th_mem_V_write_phi_fu_3405_p4 = call_ret1_sp_mem11_fu_4922_ap_return_94;
end else begin
primitive11_88_th_mem_V_write_phi_fu_3405_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_89_th_corr_mem_V_s_phi_fu_4395_p4 = primitive11_89_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_89_th_corr_mem_V_s_phi_fu_4395_p4 = call_ret1_sp_mem11_fu_4922_ap_return_223;
end else begin
primitive11_89_th_corr_mem_V_s_phi_fu_4395_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_89_th_mem_V_write_phi_fu_3375_p4 = primitive11_89_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_89_th_mem_V_write_phi_fu_3375_p4 = call_ret1_sp_mem11_fu_4922_ap_return_95;
end else begin
primitive11_89_th_mem_V_write_phi_fu_3375_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_8_th_corr_mem_V_w_phi_fu_3515_p4 = primitive11_8_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_8_th_corr_mem_V_w_phi_fu_3515_p4 = call_ret1_sp_mem11_fu_4922_ap_return_142;
end else begin
primitive11_8_th_corr_mem_V_w_phi_fu_3515_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_8_th_mem_V_write_s_phi_fu_2275_p4 = primitive11_8_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_8_th_mem_V_write_s_phi_fu_2275_p4 = call_ret1_sp_mem11_fu_4922_ap_return_14;
end else begin
primitive11_8_th_mem_V_write_s_phi_fu_2275_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_90_th_corr_mem_V_s_phi_fu_4405_p4 = primitive11_90_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_90_th_corr_mem_V_s_phi_fu_4405_p4 = call_ret1_sp_mem11_fu_4922_ap_return_224;
end else begin
primitive11_90_th_corr_mem_V_s_phi_fu_4405_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_90_th_mem_V_write_phi_fu_3345_p4 = primitive11_90_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_90_th_mem_V_write_phi_fu_3345_p4 = call_ret1_sp_mem11_fu_4922_ap_return_96;
end else begin
primitive11_90_th_mem_V_write_phi_fu_3345_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_91_th_corr_mem_V_s_phi_fu_4425_p4 = primitive11_91_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_91_th_corr_mem_V_s_phi_fu_4425_p4 = call_ret1_sp_mem11_fu_4922_ap_return_225;
end else begin
primitive11_91_th_corr_mem_V_s_phi_fu_4425_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_91_th_mem_V_write_phi_fu_3315_p4 = primitive11_91_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_91_th_mem_V_write_phi_fu_3315_p4 = call_ret1_sp_mem11_fu_4922_ap_return_97;
end else begin
primitive11_91_th_mem_V_write_phi_fu_3315_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_92_th_corr_mem_V_s_phi_fu_4435_p4 = primitive11_92_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_92_th_corr_mem_V_s_phi_fu_4435_p4 = call_ret1_sp_mem11_fu_4922_ap_return_226;
end else begin
primitive11_92_th_corr_mem_V_s_phi_fu_4435_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_92_th_mem_V_write_phi_fu_3285_p4 = primitive11_92_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_92_th_mem_V_write_phi_fu_3285_p4 = call_ret1_sp_mem11_fu_4922_ap_return_98;
end else begin
primitive11_92_th_mem_V_write_phi_fu_3285_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_93_th_corr_mem_V_s_phi_fu_4455_p4 = primitive11_93_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_93_th_corr_mem_V_s_phi_fu_4455_p4 = call_ret1_sp_mem11_fu_4922_ap_return_227;
end else begin
primitive11_93_th_corr_mem_V_s_phi_fu_4455_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_93_th_mem_V_write_phi_fu_3255_p4 = primitive11_93_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_93_th_mem_V_write_phi_fu_3255_p4 = call_ret1_sp_mem11_fu_4922_ap_return_99;
end else begin
primitive11_93_th_mem_V_write_phi_fu_3255_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_94_th_corr_mem_V_s_phi_fu_4785_p4 = primitive11_94_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_94_th_corr_mem_V_s_phi_fu_4785_p4 = call_ret1_sp_mem11_fu_4922_ap_return_228;
end else begin
primitive11_94_th_corr_mem_V_s_phi_fu_4785_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_94_th_mem_V_write_phi_fu_3225_p4 = primitive11_94_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_94_th_mem_V_write_phi_fu_3225_p4 = call_ret1_sp_mem11_fu_4922_ap_return_100;
end else begin
primitive11_94_th_mem_V_write_phi_fu_3225_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_95_th_corr_mem_V_s_phi_fu_4755_p4 = primitive11_95_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_95_th_corr_mem_V_s_phi_fu_4755_p4 = call_ret1_sp_mem11_fu_4922_ap_return_229;
end else begin
primitive11_95_th_corr_mem_V_s_phi_fu_4755_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_95_th_mem_V_write_phi_fu_3195_p4 = primitive11_95_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_95_th_mem_V_write_phi_fu_3195_p4 = call_ret1_sp_mem11_fu_4922_ap_return_101;
end else begin
primitive11_95_th_mem_V_write_phi_fu_3195_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_96_th_corr_mem_V_s_phi_fu_4725_p4 = primitive11_96_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_96_th_corr_mem_V_s_phi_fu_4725_p4 = call_ret1_sp_mem11_fu_4922_ap_return_230;
end else begin
primitive11_96_th_corr_mem_V_s_phi_fu_4725_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_96_th_mem_V_write_phi_fu_3165_p4 = primitive11_96_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_96_th_mem_V_write_phi_fu_3165_p4 = call_ret1_sp_mem11_fu_4922_ap_return_102;
end else begin
primitive11_96_th_mem_V_write_phi_fu_3165_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_97_th_corr_mem_V_s_phi_fu_4695_p4 = primitive11_97_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_97_th_corr_mem_V_s_phi_fu_4695_p4 = call_ret1_sp_mem11_fu_4922_ap_return_231;
end else begin
primitive11_97_th_corr_mem_V_s_phi_fu_4695_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_97_th_mem_V_write_phi_fu_3135_p4 = primitive11_97_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_97_th_mem_V_write_phi_fu_3135_p4 = call_ret1_sp_mem11_fu_4922_ap_return_103;
end else begin
primitive11_97_th_mem_V_write_phi_fu_3135_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_98_th_corr_mem_V_s_phi_fu_4665_p4 = primitive11_98_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_98_th_corr_mem_V_s_phi_fu_4665_p4 = call_ret1_sp_mem11_fu_4922_ap_return_232;
end else begin
primitive11_98_th_corr_mem_V_s_phi_fu_4665_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_98_th_mem_V_write_phi_fu_3115_p4 = primitive11_98_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_98_th_mem_V_write_phi_fu_3115_p4 = call_ret1_sp_mem11_fu_4922_ap_return_104;
end else begin
primitive11_98_th_mem_V_write_phi_fu_3115_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_99_th_corr_mem_V_s_phi_fu_4635_p4 = primitive11_99_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_99_th_corr_mem_V_s_phi_fu_4635_p4 = call_ret1_sp_mem11_fu_4922_ap_return_233;
end else begin
primitive11_99_th_corr_mem_V_s_phi_fu_4635_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_99_th_mem_V_write_phi_fu_3125_p4 = primitive11_99_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_99_th_mem_V_write_phi_fu_3125_p4 = call_ret1_sp_mem11_fu_4922_ap_return_105;
end else begin
primitive11_99_th_mem_V_write_phi_fu_3125_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_9_th_corr_mem_V_w_phi_fu_3525_p4 = primitive11_9_th_corr_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_9_th_corr_mem_V_w_phi_fu_3525_p4 = call_ret1_sp_mem11_fu_4922_ap_return_143;
end else begin
primitive11_9_th_corr_mem_V_w_phi_fu_3525_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_9_th_mem_V_write_s_phi_fu_2285_p4 = primitive11_9_th_mem_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_9_th_mem_V_write_s_phi_fu_2285_p4 = call_ret1_sp_mem11_fu_4922_ap_return_15;
end else begin
primitive11_9_th_mem_V_write_s_phi_fu_2285_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V1_phi_fu_4815_p4 = primitive11_1_params_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V1_phi_fu_4815_p4 = call_ret1_sp_mem11_fu_4922_ap_return_1;
end else begin
primitive11_params_V1_phi_fu_4815_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V2_phi_fu_4825_p4 = primitive11_2_params_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V2_phi_fu_4825_p4 = call_ret1_sp_mem11_fu_4922_ap_return_2;
end else begin
primitive11_params_V2_phi_fu_4825_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V3_phi_fu_4835_p4 = primitive11_3_params_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V3_phi_fu_4835_p4 = call_ret1_sp_mem11_fu_4922_ap_return_3;
end else begin
primitive11_params_V3_phi_fu_4835_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V4_phi_fu_4845_p4 = primitive11_4_params_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V4_phi_fu_4845_p4 = call_ret1_sp_mem11_fu_4922_ap_return_4;
end else begin
primitive11_params_V4_phi_fu_4845_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V5_phi_fu_4855_p4 = primitive11_5_params_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V5_phi_fu_4855_p4 = call_ret1_sp_mem11_fu_4922_ap_return_5;
end else begin
primitive11_params_V5_phi_fu_4855_p4 = 'bx;
end
end
always @ (*) begin
if ((we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V_phi_fu_4805_p4 = primitive11_0_params_V_read;
end else if (~(we_V_read_read_fu_610_p2 == 1'b0)) begin
primitive11_params_V_phi_fu_4805_p4 = call_ret1_sp_mem11_fu_4922_ap_return_0;
end else begin
primitive11_params_V_phi_fu_4805_p4 = 'bx;
end
end
assign ap_return_0 = call_ret_sp_prim_conv11_fu_5456_ap_return_0;
assign ap_return_1 = call_ret_sp_prim_conv11_fu_5456_ap_return_1;
assign ap_return_10 = call_ret_sp_prim_conv11_fu_5456_ap_return_4;
assign ap_return_100 = primitive11_88_th_mem_V_write_phi_fu_3405_p4;
assign ap_return_101 = primitive11_89_th_mem_V_write_phi_fu_3375_p4;
assign ap_return_102 = primitive11_90_th_mem_V_write_phi_fu_3345_p4;
assign ap_return_103 = primitive11_91_th_mem_V_write_phi_fu_3315_p4;
assign ap_return_104 = primitive11_92_th_mem_V_write_phi_fu_3285_p4;
assign ap_return_105 = primitive11_93_th_mem_V_write_phi_fu_3255_p4;
assign ap_return_106 = primitive11_94_th_mem_V_write_phi_fu_3225_p4;
assign ap_return_107 = primitive11_95_th_mem_V_write_phi_fu_3195_p4;
assign ap_return_108 = primitive11_96_th_mem_V_write_phi_fu_3165_p4;
assign ap_return_109 = primitive11_97_th_mem_V_write_phi_fu_3135_p4;
assign ap_return_11 = call_ret_sp_prim_conv11_fu_5456_ap_return_5;
assign ap_return_110 = primitive11_98_th_mem_V_write_phi_fu_3115_p4;
assign ap_return_111 = primitive11_99_th_mem_V_write_phi_fu_3125_p4;
assign ap_return_112 = primitive11_100_th_mem_V_writ_phi_fu_3145_p4;
assign ap_return_113 = primitive11_101_th_mem_V_writ_phi_fu_3155_p4;
assign ap_return_114 = primitive11_102_th_mem_V_writ_phi_fu_3175_p4;
assign ap_return_115 = primitive11_103_th_mem_V_writ_phi_fu_3185_p4;
assign ap_return_116 = primitive11_104_th_mem_V_writ_phi_fu_3205_p4;
assign ap_return_117 = primitive11_105_th_mem_V_writ_phi_fu_3215_p4;
assign ap_return_118 = primitive11_106_th_mem_V_writ_phi_fu_3235_p4;
assign ap_return_119 = primitive11_107_th_mem_V_writ_phi_fu_3245_p4;
assign ap_return_12 = primitive11_0_th_mem_V_write_s_phi_fu_2415_p4;
assign ap_return_120 = primitive11_108_th_mem_V_writ_phi_fu_3265_p4;
assign ap_return_121 = primitive11_109_th_mem_V_writ_phi_fu_3275_p4;
assign ap_return_122 = primitive11_110_th_mem_V_writ_phi_fu_3295_p4;
assign ap_return_123 = primitive11_111_th_mem_V_writ_phi_fu_3305_p4;
assign ap_return_124 = primitive11_112_th_mem_V_writ_phi_fu_3325_p4;
assign ap_return_125 = primitive11_113_th_mem_V_writ_phi_fu_3335_p4;
assign ap_return_126 = primitive11_114_th_mem_V_writ_phi_fu_3355_p4;
assign ap_return_127 = primitive11_115_th_mem_V_writ_phi_fu_3365_p4;
assign ap_return_128 = primitive11_116_th_mem_V_writ_phi_fu_3385_p4;
assign ap_return_129 = primitive11_117_th_mem_V_writ_phi_fu_3395_p4;
assign ap_return_13 = primitive11_1_th_mem_V_write_s_phi_fu_2385_p4;
assign ap_return_130 = primitive11_118_th_mem_V_writ_phi_fu_3415_p4;
assign ap_return_131 = primitive11_119_th_mem_V_writ_phi_fu_3425_p4;
assign ap_return_132 = primitive11_120_th_mem_V_writ_phi_fu_3445_p4;
assign ap_return_133 = primitive11_121_th_mem_V_writ_phi_fu_3775_p4;
assign ap_return_134 = primitive11_122_th_mem_V_writ_phi_fu_3745_p4;
assign ap_return_135 = primitive11_123_th_mem_V_writ_phi_fu_3715_p4;
assign ap_return_136 = primitive11_124_th_mem_V_writ_phi_fu_3685_p4;
assign ap_return_137 = primitive11_125_th_mem_V_writ_phi_fu_3655_p4;
assign ap_return_138 = primitive11_126_th_mem_V_writ_phi_fu_3625_p4;
assign ap_return_139 = primitive11_127_th_mem_V_writ_phi_fu_3595_p4;
assign ap_return_14 = primitive11_2_th_mem_V_write_s_phi_fu_2355_p4;
assign ap_return_140 = primitive11_0_th_corr_mem_V_w_phi_fu_3565_p4;
assign ap_return_141 = primitive11_1_th_corr_mem_V_w_phi_fu_3535_p4;
assign ap_return_142 = primitive11_2_th_corr_mem_V_w_phi_fu_3505_p4;
assign ap_return_143 = primitive11_3_th_corr_mem_V_w_phi_fu_3475_p4;
assign ap_return_144 = primitive11_4_th_corr_mem_V_w_phi_fu_3455_p4;
assign ap_return_145 = primitive11_5_th_corr_mem_V_w_phi_fu_3465_p4;
assign ap_return_146 = primitive11_6_th_corr_mem_V_w_phi_fu_3485_p4;
assign ap_return_147 = primitive11_7_th_corr_mem_V_w_phi_fu_3495_p4;
assign ap_return_148 = primitive11_8_th_corr_mem_V_w_phi_fu_3515_p4;
assign ap_return_149 = primitive11_9_th_corr_mem_V_w_phi_fu_3525_p4;
assign ap_return_15 = primitive11_3_th_mem_V_write_s_phi_fu_2325_p4;
assign ap_return_150 = primitive11_10_th_corr_mem_V_s_phi_fu_3545_p4;
assign ap_return_151 = primitive11_11_th_corr_mem_V_s_phi_fu_3555_p4;
assign ap_return_152 = primitive11_12_th_corr_mem_V_s_phi_fu_3575_p4;
assign ap_return_153 = primitive11_13_th_corr_mem_V_s_phi_fu_3585_p4;
assign ap_return_154 = primitive11_14_th_corr_mem_V_s_phi_fu_3605_p4;
assign ap_return_155 = primitive11_15_th_corr_mem_V_s_phi_fu_3615_p4;
assign ap_return_156 = primitive11_16_th_corr_mem_V_s_phi_fu_3635_p4;
assign ap_return_157 = primitive11_17_th_corr_mem_V_s_phi_fu_3645_p4;
assign ap_return_158 = primitive11_18_th_corr_mem_V_s_phi_fu_3665_p4;
assign ap_return_159 = primitive11_19_th_corr_mem_V_s_phi_fu_3675_p4;
assign ap_return_16 = primitive11_4_th_mem_V_write_s_phi_fu_2295_p4;
assign ap_return_160 = primitive11_20_th_corr_mem_V_s_phi_fu_3695_p4;
assign ap_return_161 = primitive11_21_th_corr_mem_V_s_phi_fu_3705_p4;
assign ap_return_162 = primitive11_22_th_corr_mem_V_s_phi_fu_3725_p4;
assign ap_return_163 = primitive11_23_th_corr_mem_V_s_phi_fu_3735_p4;
assign ap_return_164 = primitive11_24_th_corr_mem_V_s_phi_fu_3755_p4;
assign ap_return_165 = primitive11_25_th_corr_mem_V_s_phi_fu_3765_p4;
assign ap_return_166 = primitive11_26_th_corr_mem_V_s_phi_fu_3785_p4;
assign ap_return_167 = primitive11_27_th_corr_mem_V_s_phi_fu_4105_p4;
assign ap_return_168 = primitive11_28_th_corr_mem_V_s_phi_fu_4075_p4;
assign ap_return_169 = primitive11_29_th_corr_mem_V_s_phi_fu_4045_p4;
assign ap_return_17 = primitive11_5_th_mem_V_write_s_phi_fu_2265_p4;
assign ap_return_170 = primitive11_30_th_corr_mem_V_s_phi_fu_4015_p4;
assign ap_return_171 = primitive11_31_th_corr_mem_V_s_phi_fu_3985_p4;
assign ap_return_172 = primitive11_32_th_corr_mem_V_s_phi_fu_3955_p4;
assign ap_return_173 = primitive11_33_th_corr_mem_V_s_phi_fu_3925_p4;
assign ap_return_174 = primitive11_34_th_corr_mem_V_s_phi_fu_3895_p4;
assign ap_return_175 = primitive11_35_th_corr_mem_V_s_phi_fu_3865_p4;
assign ap_return_176 = primitive11_36_th_corr_mem_V_s_phi_fu_3835_p4;
assign ap_return_177 = primitive11_37_th_corr_mem_V_s_phi_fu_3805_p4;
assign ap_return_178 = primitive11_38_th_corr_mem_V_s_phi_fu_3795_p4;
assign ap_return_179 = primitive11_39_th_corr_mem_V_s_phi_fu_3815_p4;
assign ap_return_18 = primitive11_6_th_mem_V_write_s_phi_fu_2245_p4;
assign ap_return_180 = primitive11_40_th_corr_mem_V_s_phi_fu_3825_p4;
assign ap_return_181 = primitive11_41_th_corr_mem_V_s_phi_fu_3845_p4;
assign ap_return_182 = primitive11_42_th_corr_mem_V_s_phi_fu_3855_p4;
assign ap_return_183 = primitive11_43_th_corr_mem_V_s_phi_fu_3875_p4;
assign ap_return_184 = primitive11_44_th_corr_mem_V_s_phi_fu_3885_p4;
assign ap_return_185 = primitive11_45_th_corr_mem_V_s_phi_fu_3905_p4;
assign ap_return_186 = primitive11_46_th_corr_mem_V_s_phi_fu_3915_p4;
assign ap_return_187 = primitive11_47_th_corr_mem_V_s_phi_fu_3935_p4;
assign ap_return_188 = primitive11_48_th_corr_mem_V_s_phi_fu_3945_p4;
assign ap_return_189 = primitive11_49_th_corr_mem_V_s_phi_fu_3965_p4;
assign ap_return_19 = primitive11_7_th_mem_V_write_s_phi_fu_2255_p4;
assign ap_return_190 = primitive11_50_th_corr_mem_V_s_phi_fu_3975_p4;
assign ap_return_191 = primitive11_51_th_corr_mem_V_s_phi_fu_3995_p4;
assign ap_return_192 = primitive11_52_th_corr_mem_V_s_phi_fu_4005_p4;
assign ap_return_193 = primitive11_53_th_corr_mem_V_s_phi_fu_4025_p4;
assign ap_return_194 = primitive11_54_th_corr_mem_V_s_phi_fu_4035_p4;
assign ap_return_195 = primitive11_55_th_corr_mem_V_s_phi_fu_4055_p4;
assign ap_return_196 = primitive11_56_th_corr_mem_V_s_phi_fu_4065_p4;
assign ap_return_197 = primitive11_57_th_corr_mem_V_s_phi_fu_4085_p4;
assign ap_return_198 = primitive11_58_th_corr_mem_V_s_phi_fu_4095_p4;
assign ap_return_199 = primitive11_59_th_corr_mem_V_s_phi_fu_4115_p4;
assign ap_return_2 = primitive11_params_V_phi_fu_4805_p4;
assign ap_return_20 = primitive11_8_th_mem_V_write_s_phi_fu_2275_p4;
assign ap_return_200 = primitive11_60_th_corr_mem_V_s_phi_fu_4445_p4;
assign ap_return_201 = primitive11_61_th_corr_mem_V_s_phi_fu_4415_p4;
assign ap_return_202 = primitive11_62_th_corr_mem_V_s_phi_fu_4385_p4;
assign ap_return_203 = primitive11_63_th_corr_mem_V_s_phi_fu_4355_p4;
assign ap_return_204 = primitive11_64_th_corr_mem_V_s_phi_fu_4325_p4;
assign ap_return_205 = primitive11_65_th_corr_mem_V_s_phi_fu_4295_p4;
assign ap_return_206 = primitive11_66_th_corr_mem_V_s_phi_fu_4265_p4;
assign ap_return_207 = primitive11_67_th_corr_mem_V_s_phi_fu_4235_p4;
assign ap_return_208 = primitive11_68_th_corr_mem_V_s_phi_fu_4205_p4;
assign ap_return_209 = primitive11_69_th_corr_mem_V_s_phi_fu_4175_p4;
assign ap_return_21 = primitive11_9_th_mem_V_write_s_phi_fu_2285_p4;
assign ap_return_210 = primitive11_70_th_corr_mem_V_s_phi_fu_4145_p4;
assign ap_return_211 = primitive11_71_th_corr_mem_V_s_phi_fu_4125_p4;
assign ap_return_212 = primitive11_72_th_corr_mem_V_s_phi_fu_4135_p4;
assign ap_return_213 = primitive11_73_th_corr_mem_V_s_phi_fu_4155_p4;
assign ap_return_214 = primitive11_74_th_corr_mem_V_s_phi_fu_4165_p4;
assign ap_return_215 = primitive11_75_th_corr_mem_V_s_phi_fu_4185_p4;
assign ap_return_216 = primitive11_76_th_corr_mem_V_s_phi_fu_4195_p4;
assign ap_return_217 = primitive11_77_th_corr_mem_V_s_phi_fu_4215_p4;
assign ap_return_218 = primitive11_78_th_corr_mem_V_s_phi_fu_4225_p4;
assign ap_return_219 = primitive11_79_th_corr_mem_V_s_phi_fu_4245_p4;
assign ap_return_22 = primitive11_10_th_mem_V_write_phi_fu_2305_p4;
assign ap_return_220 = primitive11_80_th_corr_mem_V_s_phi_fu_4255_p4;
assign ap_return_221 = primitive11_81_th_corr_mem_V_s_phi_fu_4275_p4;
assign ap_return_222 = primitive11_82_th_corr_mem_V_s_phi_fu_4285_p4;
assign ap_return_223 = primitive11_83_th_corr_mem_V_s_phi_fu_4305_p4;
assign ap_return_224 = primitive11_84_th_corr_mem_V_s_phi_fu_4315_p4;
assign ap_return_225 = primitive11_85_th_corr_mem_V_s_phi_fu_4335_p4;
assign ap_return_226 = primitive11_86_th_corr_mem_V_s_phi_fu_4345_p4;
assign ap_return_227 = primitive11_87_th_corr_mem_V_s_phi_fu_4365_p4;
assign ap_return_228 = primitive11_88_th_corr_mem_V_s_phi_fu_4375_p4;
assign ap_return_229 = primitive11_89_th_corr_mem_V_s_phi_fu_4395_p4;
assign ap_return_23 = primitive11_11_th_mem_V_write_phi_fu_2315_p4;
assign ap_return_230 = primitive11_90_th_corr_mem_V_s_phi_fu_4405_p4;
assign ap_return_231 = primitive11_91_th_corr_mem_V_s_phi_fu_4425_p4;
assign ap_return_232 = primitive11_92_th_corr_mem_V_s_phi_fu_4435_p4;
assign ap_return_233 = primitive11_93_th_corr_mem_V_s_phi_fu_4455_p4;
assign ap_return_234 = primitive11_94_th_corr_mem_V_s_phi_fu_4785_p4;
assign ap_return_235 = primitive11_95_th_corr_mem_V_s_phi_fu_4755_p4;
assign ap_return_236 = primitive11_96_th_corr_mem_V_s_phi_fu_4725_p4;
assign ap_return_237 = primitive11_97_th_corr_mem_V_s_phi_fu_4695_p4;
assign ap_return_238 = primitive11_98_th_corr_mem_V_s_phi_fu_4665_p4;
assign ap_return_239 = primitive11_99_th_corr_mem_V_s_phi_fu_4635_p4;
assign ap_return_24 = primitive11_12_th_mem_V_write_phi_fu_2335_p4;
assign ap_return_240 = primitive11_100_th_corr_mem_V_phi_fu_4605_p4;
assign ap_return_241 = primitive11_101_th_corr_mem_V_phi_fu_4575_p4;
assign ap_return_242 = primitive11_102_th_corr_mem_V_phi_fu_4545_p4;
assign ap_return_243 = primitive11_103_th_corr_mem_V_phi_fu_4515_p4;
assign ap_return_244 = primitive11_104_th_corr_mem_V_phi_fu_4485_p4;
assign ap_return_245 = primitive11_105_th_corr_mem_V_phi_fu_4465_p4;
assign ap_return_246 = primitive11_106_th_corr_mem_V_phi_fu_4475_p4;
assign ap_return_247 = primitive11_107_th_corr_mem_V_phi_fu_4495_p4;
assign ap_return_248 = primitive11_108_th_corr_mem_V_phi_fu_4505_p4;
assign ap_return_249 = primitive11_109_th_corr_mem_V_phi_fu_4525_p4;
assign ap_return_25 = primitive11_13_th_mem_V_write_phi_fu_2345_p4;
assign ap_return_250 = primitive11_110_th_corr_mem_V_phi_fu_4535_p4;
assign ap_return_251 = primitive11_111_th_corr_mem_V_phi_fu_4555_p4;
assign ap_return_252 = primitive11_112_th_corr_mem_V_phi_fu_4565_p4;
assign ap_return_253 = primitive11_113_th_corr_mem_V_phi_fu_4585_p4;
assign ap_return_254 = primitive11_114_th_corr_mem_V_phi_fu_4595_p4;
assign ap_return_255 = primitive11_115_th_corr_mem_V_phi_fu_4615_p4;
assign ap_return_256 = primitive11_116_th_corr_mem_V_phi_fu_4625_p4;
assign ap_return_257 = primitive11_117_th_corr_mem_V_phi_fu_4645_p4;
assign ap_return_258 = primitive11_118_th_corr_mem_V_phi_fu_4655_p4;
assign ap_return_259 = primitive11_119_th_corr_mem_V_phi_fu_4675_p4;
assign ap_return_26 = primitive11_14_th_mem_V_write_phi_fu_2365_p4;
assign ap_return_260 = primitive11_120_th_corr_mem_V_phi_fu_4685_p4;
assign ap_return_261 = primitive11_121_th_corr_mem_V_phi_fu_4705_p4;
assign ap_return_262 = primitive11_122_th_corr_mem_V_phi_fu_4715_p4;
assign ap_return_263 = primitive11_123_th_corr_mem_V_phi_fu_4735_p4;
assign ap_return_264 = primitive11_124_th_corr_mem_V_phi_fu_4745_p4;
assign ap_return_265 = primitive11_125_th_corr_mem_V_phi_fu_4765_p4;
assign ap_return_266 = primitive11_126_th_corr_mem_V_phi_fu_4775_p4;
assign ap_return_267 = primitive11_127_th_corr_mem_V_phi_fu_4795_p4;
assign ap_return_27 = primitive11_15_th_mem_V_write_phi_fu_2375_p4;
assign ap_return_28 = primitive11_16_th_mem_V_write_phi_fu_2395_p4;
assign ap_return_29 = primitive11_17_th_mem_V_write_phi_fu_2405_p4;
assign ap_return_3 = primitive11_params_V1_phi_fu_4815_p4;
assign ap_return_30 = primitive11_18_th_mem_V_write_phi_fu_2425_p4;
assign ap_return_31 = primitive11_19_th_mem_V_write_phi_fu_2435_p4;
assign ap_return_32 = primitive11_20_th_mem_V_write_phi_fu_2765_p4;
assign ap_return_33 = primitive11_21_th_mem_V_write_phi_fu_2735_p4;
assign ap_return_34 = primitive11_22_th_mem_V_write_phi_fu_2705_p4;
assign ap_return_35 = primitive11_23_th_mem_V_write_phi_fu_2675_p4;
assign ap_return_36 = primitive11_24_th_mem_V_write_phi_fu_2645_p4;
assign ap_return_37 = primitive11_25_th_mem_V_write_phi_fu_2615_p4;
assign ap_return_38 = primitive11_26_th_mem_V_write_phi_fu_2585_p4;
assign ap_return_39 = primitive11_27_th_mem_V_write_phi_fu_2555_p4;
assign ap_return_4 = primitive11_params_V2_phi_fu_4825_p4;
assign ap_return_40 = primitive11_28_th_mem_V_write_phi_fu_2525_p4;
assign ap_return_41 = primitive11_29_th_mem_V_write_phi_fu_2495_p4;
assign ap_return_42 = primitive11_30_th_mem_V_write_phi_fu_2465_p4;
assign ap_return_43 = primitive11_31_th_mem_V_write_phi_fu_2445_p4;
assign ap_return_44 = primitive11_32_th_mem_V_write_phi_fu_2455_p4;
assign ap_return_45 = primitive11_33_th_mem_V_write_phi_fu_2475_p4;
assign ap_return_46 = primitive11_34_th_mem_V_write_phi_fu_2485_p4;
assign ap_return_47 = primitive11_35_th_mem_V_write_phi_fu_2505_p4;
assign ap_return_48 = primitive11_36_th_mem_V_write_phi_fu_2515_p4;
assign ap_return_49 = primitive11_37_th_mem_V_write_phi_fu_2535_p4;
assign ap_return_5 = primitive11_params_V3_phi_fu_4835_p4;
assign ap_return_50 = primitive11_38_th_mem_V_write_phi_fu_2545_p4;
assign ap_return_51 = primitive11_39_th_mem_V_write_phi_fu_2565_p4;
assign ap_return_52 = primitive11_40_th_mem_V_write_phi_fu_2575_p4;
assign ap_return_53 = primitive11_41_th_mem_V_write_phi_fu_2595_p4;
assign ap_return_54 = primitive11_42_th_mem_V_write_phi_fu_2605_p4;
assign ap_return_55 = primitive11_43_th_mem_V_write_phi_fu_2625_p4;
assign ap_return_56 = primitive11_44_th_mem_V_write_phi_fu_2635_p4;
assign ap_return_57 = primitive11_45_th_mem_V_write_phi_fu_2655_p4;
assign ap_return_58 = primitive11_46_th_mem_V_write_phi_fu_2665_p4;
assign ap_return_59 = primitive11_47_th_mem_V_write_phi_fu_2685_p4;
assign ap_return_6 = primitive11_params_V4_phi_fu_4845_p4;
assign ap_return_60 = primitive11_48_th_mem_V_write_phi_fu_2695_p4;
assign ap_return_61 = primitive11_49_th_mem_V_write_phi_fu_2715_p4;
assign ap_return_62 = primitive11_50_th_mem_V_write_phi_fu_2725_p4;
assign ap_return_63 = primitive11_51_th_mem_V_write_phi_fu_2745_p4;
assign ap_return_64 = primitive11_52_th_mem_V_write_phi_fu_2755_p4;
assign ap_return_65 = primitive11_53_th_mem_V_write_phi_fu_2775_p4;
assign ap_return_66 = primitive11_54_th_mem_V_write_phi_fu_3095_p4;
assign ap_return_67 = primitive11_55_th_mem_V_write_phi_fu_3065_p4;
assign ap_return_68 = primitive11_56_th_mem_V_write_phi_fu_3035_p4;
assign ap_return_69 = primitive11_57_th_mem_V_write_phi_fu_3005_p4;
assign ap_return_7 = primitive11_params_V5_phi_fu_4855_p4;
assign ap_return_70 = primitive11_58_th_mem_V_write_phi_fu_2975_p4;
assign ap_return_71 = primitive11_59_th_mem_V_write_phi_fu_2945_p4;
assign ap_return_72 = primitive11_60_th_mem_V_write_phi_fu_2915_p4;
assign ap_return_73 = primitive11_61_th_mem_V_write_phi_fu_2885_p4;
assign ap_return_74 = primitive11_62_th_mem_V_write_phi_fu_2855_p4;
assign ap_return_75 = primitive11_63_th_mem_V_write_phi_fu_2825_p4;
assign ap_return_76 = primitive11_64_th_mem_V_write_phi_fu_2795_p4;
assign ap_return_77 = primitive11_65_th_mem_V_write_phi_fu_2785_p4;
assign ap_return_78 = primitive11_66_th_mem_V_write_phi_fu_2805_p4;
assign ap_return_79 = primitive11_67_th_mem_V_write_phi_fu_2815_p4;
assign ap_return_8 = call_ret_sp_prim_conv11_fu_5456_ap_return_2;
assign ap_return_80 = primitive11_68_th_mem_V_write_phi_fu_2835_p4;
assign ap_return_81 = primitive11_69_th_mem_V_write_phi_fu_2845_p4;
assign ap_return_82 = primitive11_70_th_mem_V_write_phi_fu_2865_p4;
assign ap_return_83 = primitive11_71_th_mem_V_write_phi_fu_2875_p4;
assign ap_return_84 = primitive11_72_th_mem_V_write_phi_fu_2895_p4;
assign ap_return_85 = primitive11_73_th_mem_V_write_phi_fu_2905_p4;
assign ap_return_86 = primitive11_74_th_mem_V_write_phi_fu_2925_p4;
assign ap_return_87 = primitive11_75_th_mem_V_write_phi_fu_2935_p4;
assign ap_return_88 = primitive11_76_th_mem_V_write_phi_fu_2955_p4;
assign ap_return_89 = primitive11_77_th_mem_V_write_phi_fu_2965_p4;
assign ap_return_9 = call_ret_sp_prim_conv11_fu_5456_ap_return_3;
assign ap_return_90 = primitive11_78_th_mem_V_write_phi_fu_2985_p4;
assign ap_return_91 = primitive11_79_th_mem_V_write_phi_fu_2995_p4;
assign ap_return_92 = primitive11_80_th_mem_V_write_phi_fu_3015_p4;
assign ap_return_93 = primitive11_81_th_mem_V_write_phi_fu_3025_p4;
assign ap_return_94 = primitive11_82_th_mem_V_write_phi_fu_3045_p4;
assign ap_return_95 = primitive11_83_th_mem_V_write_phi_fu_3055_p4;
assign ap_return_96 = primitive11_84_th_mem_V_write_phi_fu_3075_p4;
assign ap_return_97 = primitive11_85_th_mem_V_write_phi_fu_3085_p4;
assign ap_return_98 = primitive11_86_th_mem_V_write_phi_fu_3105_p4;
assign ap_return_99 = primitive11_87_th_mem_V_write_phi_fu_3435_p4;
assign we_V_read_read_fu_610_p2 = we_V;
endmodule //sp_top_prim_conv11
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:48:24 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_sim_netlist.v
// Design : system_axi_gpio_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_axi_gpio_0_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_axi_gpio_0_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT" *) output ip2intc_irpt;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [19:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [19:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [19:0]gpio_io_t;
wire [19:0]gpio_io_i;
wire [19:0]gpio_io_o;
wire [19:0]gpio_io_t;
wire ip2intc_irpt;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "artix7" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "20" *)
(* C_INTERRUPT_PRESENT = "1" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
system_axi_gpio_0_0_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2intc_irpt(ip2intc_irpt),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module system_axi_gpio_0_0_GPIO_Core
(ip2bus_data,
GPIO_xferAck_i,
gpio_xferAck_Reg,
GPIO_intr,
Q,
gpio_io_o,
gpio_io_t,
Read_Reg_Rst,
\Not_Dual.gpio_OE_reg[19]_0 ,
s_axi_aclk,
\Not_Dual.gpio_OE_reg[18]_0 ,
\Not_Dual.gpio_OE_reg[17]_0 ,
\Not_Dual.gpio_OE_reg[16]_0 ,
\Not_Dual.gpio_OE_reg[15]_0 ,
\Not_Dual.gpio_OE_reg[14]_0 ,
\Not_Dual.gpio_OE_reg[13]_0 ,
\Not_Dual.gpio_OE_reg[12]_0 ,
\Not_Dual.gpio_OE_reg[11]_0 ,
\Not_Dual.gpio_OE_reg[10]_0 ,
\Not_Dual.gpio_OE_reg[9]_0 ,
\Not_Dual.gpio_OE_reg[8]_0 ,
\Not_Dual.gpio_OE_reg[7]_0 ,
\Not_Dual.gpio_OE_reg[6]_0 ,
\Not_Dual.gpio_OE_reg[5]_0 ,
\Not_Dual.gpio_OE_reg[4]_0 ,
\Not_Dual.gpio_OE_reg[3]_0 ,
\Not_Dual.gpio_OE_reg[2]_0 ,
\Not_Dual.gpio_OE_reg[1]_0 ,
GPIO_DBus_i,
bus2ip_reset,
bus2ip_cs,
gpio_io_i,
E,
D,
bus2ip_rnw_i_reg);
output [19:0]ip2bus_data;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output GPIO_intr;
output [19:0]Q;
output [19:0]gpio_io_o;
output [19:0]gpio_io_t;
input Read_Reg_Rst;
input \Not_Dual.gpio_OE_reg[19]_0 ;
input s_axi_aclk;
input \Not_Dual.gpio_OE_reg[18]_0 ;
input \Not_Dual.gpio_OE_reg[17]_0 ;
input \Not_Dual.gpio_OE_reg[16]_0 ;
input \Not_Dual.gpio_OE_reg[15]_0 ;
input \Not_Dual.gpio_OE_reg[14]_0 ;
input \Not_Dual.gpio_OE_reg[13]_0 ;
input \Not_Dual.gpio_OE_reg[12]_0 ;
input \Not_Dual.gpio_OE_reg[11]_0 ;
input \Not_Dual.gpio_OE_reg[10]_0 ;
input \Not_Dual.gpio_OE_reg[9]_0 ;
input \Not_Dual.gpio_OE_reg[8]_0 ;
input \Not_Dual.gpio_OE_reg[7]_0 ;
input \Not_Dual.gpio_OE_reg[6]_0 ;
input \Not_Dual.gpio_OE_reg[5]_0 ;
input \Not_Dual.gpio_OE_reg[4]_0 ;
input \Not_Dual.gpio_OE_reg[3]_0 ;
input \Not_Dual.gpio_OE_reg[2]_0 ;
input \Not_Dual.gpio_OE_reg[1]_0 ;
input [0:0]GPIO_DBus_i;
input bus2ip_reset;
input [0:0]bus2ip_cs;
input [19:0]gpio_io_i;
input [0:0]E;
input [19:0]D;
input [0:0]bus2ip_rnw_i_reg;
wire [19:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ;
wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ;
wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0 ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ;
wire \Not_Dual.gpio_OE_reg[10]_0 ;
wire \Not_Dual.gpio_OE_reg[11]_0 ;
wire \Not_Dual.gpio_OE_reg[12]_0 ;
wire \Not_Dual.gpio_OE_reg[13]_0 ;
wire \Not_Dual.gpio_OE_reg[14]_0 ;
wire \Not_Dual.gpio_OE_reg[15]_0 ;
wire \Not_Dual.gpio_OE_reg[16]_0 ;
wire \Not_Dual.gpio_OE_reg[17]_0 ;
wire \Not_Dual.gpio_OE_reg[18]_0 ;
wire \Not_Dual.gpio_OE_reg[19]_0 ;
wire \Not_Dual.gpio_OE_reg[1]_0 ;
wire \Not_Dual.gpio_OE_reg[2]_0 ;
wire \Not_Dual.gpio_OE_reg[3]_0 ;
wire \Not_Dual.gpio_OE_reg[4]_0 ;
wire \Not_Dual.gpio_OE_reg[5]_0 ;
wire \Not_Dual.gpio_OE_reg[6]_0 ;
wire \Not_Dual.gpio_OE_reg[7]_0 ;
wire \Not_Dual.gpio_OE_reg[8]_0 ;
wire \Not_Dual.gpio_OE_reg[9]_0 ;
wire [19:0]Q;
wire Read_Reg_Rst;
wire [0:0]bus2ip_cs;
wire bus2ip_reset;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:19]gpio_data_in_xor;
wire [19:0]gpio_io_i;
wire [0:19]gpio_io_i_d2;
wire [19:0]gpio_io_o;
wire [19:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire [19:0]ip2bus_data;
wire or_ints;
wire p_11_in;
wire p_12_in;
wire p_13_in;
wire p_14_in;
wire p_15_in;
wire p_16_in;
wire p_17_in;
wire p_1_in;
wire p_2_in;
wire p_3_in;
wire p_4_in;
wire p_5_in;
wire p_6_in;
wire p_9_in;
wire s_axi_aclk;
LUT5 #(
.INIT(32'hFFFFFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1
(.I0(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ),
.I1(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19] ),
.I2(p_17_in),
.I3(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ),
.I4(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0 ),
.O(or_ints));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2
(.I0(p_12_in),
.I1(p_11_in),
.I2(p_14_in),
.I3(p_13_in),
.I4(p_15_in),
.I5(p_16_in),
.O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3
(.I0(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
.I1(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
.I2(p_2_in),
.I3(p_1_in),
.I4(p_3_in),
.I5(p_4_in),
.O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4
(.I0(p_6_in),
.I1(p_5_in),
.I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ),
.I3(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ),
.I4(p_9_in),
.I5(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ),
.O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0 ));
FDRE \Not_Dual.GEN_INTERRUPT.GPIO_intr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(or_ints),
.Q(GPIO_intr),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[0]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[10]),
.Q(p_9_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[11]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[12]),
.Q(p_11_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[13]),
.Q(p_12_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[14]),
.Q(p_13_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[15]),
.Q(p_14_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[16]),
.Q(p_15_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[17]),
.Q(p_16_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[18]),
.Q(p_17_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[19]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[1]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[2]),
.Q(p_1_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[3]),
.Q(p_2_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[4]),
.Q(p_3_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[5]),
.Q(p_4_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[6]),
.Q(p_5_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[7]),
.Q(p_6_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[8]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[9]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ),
.R(bus2ip_reset));
system_axi_gpio_0_0_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3
(.D({gpio_data_in_xor[0],gpio_data_in_xor[1],gpio_data_in_xor[2],gpio_data_in_xor[3],gpio_data_in_xor[4],gpio_data_in_xor[5],gpio_data_in_xor[6],gpio_data_in_xor[7],gpio_data_in_xor[8],gpio_data_in_xor[9],gpio_data_in_xor[10],gpio_data_in_xor[11],gpio_data_in_xor[12],gpio_data_in_xor[13],gpio_data_in_xor[14],gpio_data_in_xor[15],gpio_data_in_xor[16],gpio_data_in_xor[17],gpio_data_in_xor[18],gpio_data_in_xor[19]}),
.Q(Q),
.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7],gpio_io_i_d2[8],gpio_io_i_d2[9],gpio_io_i_d2[10],gpio_io_i_d2[11],gpio_io_i_d2[12],gpio_io_i_d2[13],gpio_io_i_d2[14],gpio_io_i_d2[15],gpio_io_i_d2[16],gpio_io_i_d2[17],gpio_io_i_d2[18],gpio_io_i_d2[19]}));
FDRE \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus_i),
.Q(ip2bus_data[19]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[10]_0 ),
.Q(ip2bus_data[9]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[11]_0 ),
.Q(ip2bus_data[8]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[12]_0 ),
.Q(ip2bus_data[7]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[13]_0 ),
.Q(ip2bus_data[6]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[14]_0 ),
.Q(ip2bus_data[5]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[15]_0 ),
.Q(ip2bus_data[4]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[16]_0 ),
.Q(ip2bus_data[3]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[17]_0 ),
.Q(ip2bus_data[2]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[18]_0 ),
.Q(ip2bus_data[1]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[19]_0 ),
.Q(ip2bus_data[0]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[1]_0 ),
.Q(ip2bus_data[18]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[2]_0 ),
.Q(ip2bus_data[17]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[3]_0 ),
.Q(ip2bus_data[16]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[4]_0 ),
.Q(ip2bus_data[15]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[5]_0 ),
.Q(ip2bus_data[14]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[6]_0 ),
.Q(ip2bus_data[13]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[7]_0 ),
.Q(ip2bus_data[12]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[8]_0 ),
.Q(ip2bus_data[11]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[9]_0 ),
.Q(ip2bus_data[10]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(Q[19]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[10]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[10]),
.Q(Q[9]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[11]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[11]),
.Q(Q[8]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[12]),
.Q(Q[7]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[13]),
.Q(Q[6]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[14]),
.Q(Q[5]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[15]),
.Q(Q[4]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[16]),
.Q(Q[3]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[17]),
.Q(Q[2]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[18]),
.Q(Q[1]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[19]),
.Q(Q[0]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(Q[18]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(Q[17]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(Q[16]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(Q[15]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[5]),
.Q(Q[14]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[6]),
.Q(Q[13]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[7]),
.Q(Q[12]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[8]),
.Q(Q[11]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[9]),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[19]),
.Q(gpio_io_o[19]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[10]
(.C(s_axi_aclk),
.CE(E),
.D(D[9]),
.Q(gpio_io_o[9]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[11]
(.C(s_axi_aclk),
.CE(E),
.D(D[8]),
.Q(gpio_io_o[8]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[12]
(.C(s_axi_aclk),
.CE(E),
.D(D[7]),
.Q(gpio_io_o[7]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[13]
(.C(s_axi_aclk),
.CE(E),
.D(D[6]),
.Q(gpio_io_o[6]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[14]
(.C(s_axi_aclk),
.CE(E),
.D(D[5]),
.Q(gpio_io_o[5]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[15]
(.C(s_axi_aclk),
.CE(E),
.D(D[4]),
.Q(gpio_io_o[4]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[16]
(.C(s_axi_aclk),
.CE(E),
.D(D[3]),
.Q(gpio_io_o[3]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[17]
(.C(s_axi_aclk),
.CE(E),
.D(D[2]),
.Q(gpio_io_o[2]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[18]
(.C(s_axi_aclk),
.CE(E),
.D(D[1]),
.Q(gpio_io_o[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[19]
(.C(s_axi_aclk),
.CE(E),
.D(D[0]),
.Q(gpio_io_o[0]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[18]),
.Q(gpio_io_o[18]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[17]),
.Q(gpio_io_o[17]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(D[16]),
.Q(gpio_io_o[16]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(D[15]),
.Q(gpio_io_o[15]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(D[14]),
.Q(gpio_io_o[14]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(D[13]),
.Q(gpio_io_o[13]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(D[12]),
.Q(gpio_io_o[12]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[8]
(.C(s_axi_aclk),
.CE(E),
.D(D[11]),
.Q(gpio_io_o[11]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[9]
(.C(s_axi_aclk),
.CE(E),
.D(D[10]),
.Q(gpio_io_o[10]),
.R(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[19]),
.Q(gpio_io_t[19]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[10]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[9]),
.Q(gpio_io_t[9]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[11]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[8]),
.Q(gpio_io_t[8]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[12]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[7]),
.Q(gpio_io_t[7]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[13]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[6]),
.Q(gpio_io_t[6]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[14]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[5]),
.Q(gpio_io_t[5]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[15]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[4]),
.Q(gpio_io_t[4]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[16]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[3]),
.Q(gpio_io_t[3]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[17]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[2]),
.Q(gpio_io_t[2]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[18]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[1]),
.Q(gpio_io_t[1]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[19]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[0]),
.Q(gpio_io_t[0]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[18]),
.Q(gpio_io_t[18]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[17]),
.Q(gpio_io_t[17]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[16]),
.Q(gpio_io_t[16]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[15]),
.Q(gpio_io_t[15]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[14]),
.Q(gpio_io_t[14]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[13]),
.Q(gpio_io_t[13]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[12]),
.Q(gpio_io_t[12]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[8]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[11]),
.Q(gpio_io_t[11]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[9]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[10]),
.Q(gpio_io_t[10]),
.S(bus2ip_reset));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(bus2ip_reset));
LUT3 #(
.INIT(8'h10))
iGPIO_xferAck_i_1
(.I0(gpio_xferAck_Reg),
.I1(GPIO_xferAck_i),
.I2(bus2ip_cs),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module system_axi_gpio_0_0_address_decoder
(\ip2bus_data_i_D1_reg[0] ,
\Not_Dual.gpio_Data_Out_reg[19] ,
\ip_irpt_enable_reg_reg[0] ,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0]_0 ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0]_0 ,
ipif_glbl_irpt_enable_reg_reg,
start2,
s_axi_aclk,
s_axi_aresetn,
Q,
is_read,
ip2bus_rdack_i_D1,
is_write_reg,
ip2bus_wrack_i_D1,
s_axi_wdata,
\bus2ip_addr_i_reg[8] ,
gpio_io_t,
\Not_Dual.gpio_Data_In_reg[0] ,
bus2ip_rnw_i_reg,
bus2ip_reset,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1);
output \ip2bus_data_i_D1_reg[0] ;
output \Not_Dual.gpio_Data_Out_reg[19] ;
output \ip_irpt_enable_reg_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [19:0]D;
output \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ;
output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ;
output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ;
output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ;
output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ;
output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0]_0 ;
output ipif_glbl_irpt_enable_reg_reg;
input start2;
input s_axi_aclk;
input s_axi_aresetn;
input [3:0]Q;
input is_read;
input ip2bus_rdack_i_D1;
input is_write_reg;
input ip2bus_wrack_i_D1;
input [31:0]s_axi_wdata;
input [6:0]\bus2ip_addr_i_reg[8] ;
input [19:0]gpio_io_t;
input [19:0]\Not_Dual.gpio_Data_In_reg[0] ;
input bus2ip_rnw_i_reg;
input bus2ip_reset;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
wire Bus_RNW_reg_i_1_n_0;
wire [19:0]D;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ;
wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ;
wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ;
wire \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ;
wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ;
wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ;
wire [19:0]\Not_Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_Data_Out_reg[19] ;
wire [3:0]Q;
wire Read_Reg_Rst;
wire [6:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_reset;
wire bus2ip_rnw_i_reg;
wire [19:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire \ip2bus_data_i_D1_reg[0] ;
wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire \ip_irpt_enable_reg_reg[0]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_write_reg;
wire [0:0]p_0_in;
wire p_10_in;
wire p_10_out;
wire p_11_in;
wire p_11_out;
wire p_12_in;
wire p_12_out;
wire p_13_in;
wire p_13_out;
wire p_14_in;
wire p_14_out;
wire p_15_in;
wire p_15_out;
wire p_16_in;
wire [0:0]p_1_in;
wire p_2_in;
wire [0:0]p_3_in;
wire p_3_in_0;
wire p_4_in;
wire p_4_out;
wire p_5_in;
wire p_5_out;
wire p_6_in;
wire p_6_out;
wire p_7_in;
wire p_7_out;
wire p_8_out;
wire p_9_in;
wire p_9_out;
wire pselect_hit_i_1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire start2;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(start2),
.I2(\ip_irpt_enable_reg_reg[0] ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\ip_irpt_enable_reg_reg[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0040000000000000))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_9_out));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi_aclk),
.CE(start2),
.D(p_9_out),
.Q(p_10_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h4000000000000000))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_8_out));
FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]
(.C(s_axi_aclk),
.CE(start2),
.D(p_8_out),
.Q(p_9_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_7_out));
FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]
(.C(s_axi_aclk),
.CE(start2),
.D(p_7_out),
.Q(\ip2bus_data_i_D1_reg[0] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_6_out));
FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]
(.C(s_axi_aclk),
.CE(start2),
.D(p_6_out),
.Q(p_7_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_5_out));
FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]
(.C(s_axi_aclk),
.CE(start2),
.D(p_5_out),
.Q(p_6_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_4_out));
FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]
(.C(s_axi_aclk),
.CE(start2),
.D(p_4_out),
.Q(p_5_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ),
.Q(p_4_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ),
.Q(p_3_in_0),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0080000000000000))
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ),
.Q(p_2_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT3 #(
.INIT(8'hFD))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1
(.I0(s_axi_aresetn),
.I1(s_axi_arready),
.I2(s_axi_wready),
.O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_15_out));
FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]
(.C(s_axi_aclk),
.CE(start2),
.D(p_15_out),
.Q(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0001000000000000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
.Q(p_16_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0100000000000000))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_14_out));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(start2),
.D(p_14_out),
.Q(p_15_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0002000000000000))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_13_out));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(start2),
.D(p_13_out),
.Q(p_14_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0200000000000000))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_12_out));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(start2),
.D(p_12_out),
.Q(p_13_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_11_out));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi_aclk),
.CE(start2),
.D(p_11_out),
.Q(p_12_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_10_out));
FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]
(.C(s_axi_aclk),
.CE(start2),
.D(p_10_out),
.Q(p_11_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hFE00))
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(intr_rd_ce_or_reduce));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00FE0000))
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(ip2Bus_RdAck_intr_reg_hole_d1),
.I4(\ip_irpt_enable_reg_reg[0] ),
.O(\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h00FE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(intr_wr_ce_or_reduce));
LUT5 #(
.INIT(32'hFFFFFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2
(.I0(p_16_in),
.I1(p_2_in),
.I2(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
.I3(p_14_in),
.I4(p_15_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3
(.I0(p_12_in),
.I1(p_13_in),
.I2(p_10_in),
.I3(p_11_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4
(.I0(p_5_in),
.I1(p_7_in),
.I2(p_3_in_0),
.I3(p_4_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h000000FE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.I4(ip2Bus_WrAck_intr_reg_hole_d1),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ));
LUT6 #(
.INIT(64'h0000000000000002))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(start2),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [4]),
.I3(\bus2ip_addr_i_reg[8] [5]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.I5(\bus2ip_addr_i_reg[8] [2]),
.O(pselect_hit_i_1));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(start2),
.D(pselect_hit_i_1),
.Q(\Not_Dual.gpio_Data_Out_reg[19] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[12]_i_1
(.I0(gpio_io_t[19]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [19]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(GPIO_DBus_i));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[22]_i_1
(.I0(gpio_io_t[9]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [9]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[23]_i_1
(.I0(gpio_io_t[8]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [8]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[24]_i_1
(.I0(gpio_io_t[7]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [7]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[25]_i_1
(.I0(gpio_io_t[6]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [6]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i[26]_i_1
(.I0(gpio_io_t[5]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [5]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[27]_i_1
(.I0(gpio_io_t[4]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [4]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i[28]_i_1
(.I0(gpio_io_t[3]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i[29]_i_1
(.I0(gpio_io_t[2]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i[30]_i_1
(.I0(gpio_io_t[1]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ));
LUT4 #(
.INIT(16'hFFDF))
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i[31]_i_1
(.I0(\Not_Dual.gpio_Data_Out_reg[19] ),
.I1(GPIO_xferAck_i),
.I2(bus2ip_rnw_i_reg),
.I3(gpio_xferAck_Reg),
.O(Read_Reg_Rst));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i[31]_i_2
(.I0(gpio_io_t[0]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[13]_i_1
(.I0(gpio_io_t[18]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [18]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[14]_i_1
(.I0(gpio_io_t[17]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [17]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[15]_i_1
(.I0(gpio_io_t[16]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [16]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[16]_i_1
(.I0(gpio_io_t[15]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [15]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[17]_i_1
(.I0(gpio_io_t[14]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [14]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[18]_i_1
(.I0(gpio_io_t[13]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [13]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[19]_i_1
(.I0(gpio_io_t[12]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [12]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[20]_i_1
(.I0(gpio_io_t[11]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [11]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[21]_i_1
(.I0(gpio_io_t[10]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [10]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[19] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ));
LUT6 #(
.INIT(64'hFFFFFFFF00000100))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\Not_Dual.gpio_Data_Out_reg[19] ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(bus2ip_reset),
.O(\Not_Dual.gpio_Data_Out_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[31]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[19]),
.O(D[19]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[10]_i_1
(.I0(s_axi_wdata[21]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[9]),
.O(D[9]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[11]_i_1
(.I0(s_axi_wdata[20]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[12]_i_1
(.I0(s_axi_wdata[19]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[13]_i_1
(.I0(s_axi_wdata[18]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[14]_i_1
(.I0(s_axi_wdata[17]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[15]_i_1
(.I0(s_axi_wdata[16]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[16]_i_1
(.I0(s_axi_wdata[15]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[17]_i_1
(.I0(s_axi_wdata[14]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[18]_i_1
(.I0(s_axi_wdata[13]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[19]_i_1
(.I0(s_axi_wdata[12]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[30]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[18]),
.O(D[18]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[29]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[17]),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[28]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[16]),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[27]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[15]),
.O(D[15]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[5]_i_1
(.I0(s_axi_wdata[26]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[14]),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[6]_i_1
(.I0(s_axi_wdata[25]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[13]),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[7]_i_1
(.I0(s_axi_wdata[24]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[12]),
.O(D[12]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[8]_i_1
(.I0(s_axi_wdata[23]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[11]),
.O(D[11]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[9]_i_1
(.I0(s_axi_wdata[22]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[19] ),
.I3(s_axi_wdata[10]),
.O(D[10]));
LUT6 #(
.INIT(64'hFFFFFFFF01000000))
\Not_Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\Not_Dual.gpio_Data_Out_reg[19] ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(bus2ip_reset),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h44444440))
intr2bus_rdack_i_1
(.I0(irpt_rdack_d1),
.I1(\ip_irpt_enable_reg_reg[0] ),
.I2(p_9_in),
.I3(\ip2bus_data_i_D1_reg[0] ),
.I4(p_6_in),
.O(intr2bus_rdack0));
LUT5 #(
.INIT(32'h000000FE))
intr2bus_wrack_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.I4(irpt_wrack_d1),
.O(interrupt_wrce_strb));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000080))
\ip2bus_data_i_D1[0]_i_1
(.I0(p_0_in),
.I1(p_9_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_6_in),
.I4(\ip2bus_data_i_D1_reg[0] ),
.O(\ip2bus_data_i_D1_reg[0]_0 [1]));
LUT6 #(
.INIT(64'hEEEEAAAAFAAAAAAA))
\ip2bus_data_i_D1[31]_i_1
(.I0(ip2bus_data),
.I1(p_3_in),
.I2(p_1_in),
.I3(p_6_in),
.I4(\ip_irpt_enable_reg_reg[0] ),
.I5(\ip2bus_data_i_D1_reg[0] ),
.O(\ip2bus_data_i_D1_reg[0]_0 [0]));
LUT4 #(
.INIT(16'hFB08))
\ip_irpt_enable_reg[0]_i_1
(.I0(s_axi_wdata[0]),
.I1(p_6_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_1_in),
.O(\ip_irpt_enable_reg_reg[0]_0 ));
LUT4 #(
.INIT(16'hFB08))
ipif_glbl_irpt_enable_reg_i_1
(.I0(s_axi_wdata[31]),
.I1(p_9_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_0_in),
.O(ipif_glbl_irpt_enable_reg_reg));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFE00))
irpt_rdack_d1_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(irpt_rdack));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h00FE))
irpt_wrack_d1_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(irpt_wrack));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_read),
.I5(ip2bus_rdack_i_D1),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_write_reg),
.I5(ip2bus_wrack_i_D1),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "artix7" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "20" *)
(* C_INTERRUPT_PRESENT = "1" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module system_axi_gpio_0_0_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [19:0]gpio_io_i;
output [19:0]gpio_io_o;
output [19:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_28;
wire AXI_LITE_IPIF_I_n_29;
wire AXI_LITE_IPIF_I_n_30;
wire AXI_LITE_IPIF_I_n_31;
wire AXI_LITE_IPIF_I_n_32;
wire AXI_LITE_IPIF_I_n_33;
wire AXI_LITE_IPIF_I_n_34;
wire AXI_LITE_IPIF_I_n_35;
wire AXI_LITE_IPIF_I_n_36;
wire AXI_LITE_IPIF_I_n_37;
wire AXI_LITE_IPIF_I_n_38;
wire AXI_LITE_IPIF_I_n_39;
wire AXI_LITE_IPIF_I_n_40;
wire AXI_LITE_IPIF_I_n_41;
wire AXI_LITE_IPIF_I_n_42;
wire AXI_LITE_IPIF_I_n_43;
wire AXI_LITE_IPIF_I_n_44;
wire AXI_LITE_IPIF_I_n_45;
wire AXI_LITE_IPIF_I_n_46;
wire AXI_LITE_IPIF_I_n_48;
wire AXI_LITE_IPIF_I_n_49;
wire AXI_LITE_IPIF_I_n_57;
wire AXI_LITE_IPIF_I_n_59;
wire AXI_LITE_IPIF_I_n_61;
wire AXI_LITE_IPIF_I_n_62;
wire [0:19]DBus_Reg;
wire [12:12]GPIO_DBus_i;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire IP2INTC_Irpt_i;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ;
wire Read_Reg_Rst;
wire [1:1]bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_reset_i_1_n_0;
wire bus2ip_rnw;
wire [0:19]gpio_Data_In;
wire [19:0]gpio_io_i;
wire [19:0]gpio_io_o;
wire [19:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [12:31]ip2bus_data;
wire [31:31]ip2bus_data_i;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i;
wire ip2bus_wrack_i_D1;
wire ip2intc_irpt;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [31:31]p_0_in;
wire [0:0]p_0_out;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [31];
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19:0] = \^s_axi_rdata [19:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
system_axi_gpio_0_0_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13],DBus_Reg[14],DBus_Reg[15],DBus_Reg[16],DBus_Reg[17],DBus_Reg[18],DBus_Reg[19]}),
.E(AXI_LITE_IPIF_I_n_48),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_57),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_59),
.\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] (AXI_LITE_IPIF_I_n_37),
.\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] (AXI_LITE_IPIF_I_n_36),
.\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_35),
.\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] (AXI_LITE_IPIF_I_n_34),
.\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] (AXI_LITE_IPIF_I_n_33),
.\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_32),
.\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_31),
.\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_30),
.\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_29),
.\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_28),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] (AXI_LITE_IPIF_I_n_46),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] (AXI_LITE_IPIF_I_n_45),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] (AXI_LITE_IPIF_I_n_44),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] (AXI_LITE_IPIF_I_n_43),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] (AXI_LITE_IPIF_I_n_42),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] (AXI_LITE_IPIF_I_n_41),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] (AXI_LITE_IPIF_I_n_40),
.\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] (AXI_LITE_IPIF_I_n_39),
.\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] (AXI_LITE_IPIF_I_n_38),
.\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_49),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13],gpio_Data_In[14],gpio_Data_In[15],gpio_Data_In[16],gpio_Data_In[17],gpio_Data_In[18],gpio_Data_In[19]}),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data[31]),
.\ip2bus_data_i_D1_reg[0] ({p_0_out,ip2bus_data_i}),
.\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[12],ip2bus_data_i_D1[13],ip2bus_data_i_D1[14],ip2bus_data_i_D1[15],ip2bus_data_i_D1[16],ip2bus_data_i_D1[17],ip2bus_data_i_D1[18],ip2bus_data_i_D1[19],ip2bus_data_i_D1[20],ip2bus_data_i_D1[21],ip2bus_data_i_D1[22],ip2bus_data_i_D1[23],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (AXI_LITE_IPIF_I_n_61),
.ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_62),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[8:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[8:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [19:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
system_axi_gpio_0_0_interrupt_control \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_62),
.\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] (AXI_LITE_IPIF_I_n_61),
.GPIO_intr(GPIO_intr),
.GPIO_xferAck_i(GPIO_xferAck_i),
.IP2INTC_Irpt_i(IP2INTC_Irpt_i),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole),
.ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i(ip2bus_wrack_i),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[0]));
FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_rd_ce_or_reduce),
.Q(ip2Bus_RdAck_intr_reg_hole_d1),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_57),
.Q(ip2Bus_RdAck_intr_reg_hole),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_wr_ce_or_reduce),
.Q(ip2Bus_WrAck_intr_reg_hole_d1),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_59),
.Q(ip2Bus_WrAck_intr_reg_hole),
.R(bus2ip_reset));
(* sigis = "INTR_LEVEL_HIGH" *)
FDRE \INTR_CTRLR_GEN.ip2intc_irpt_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(IP2INTC_Irpt_i),
.Q(ip2intc_irpt),
.R(bus2ip_reset));
VCC VCC
(.P(\<const1> ));
LUT1 #(
.INIT(2'h1))
bus2ip_reset_i_1
(.I0(s_axi_aresetn),
.O(bus2ip_reset_i_1_n_0));
FDRE bus2ip_reset_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_reset_i_1_n_0),
.Q(bus2ip_reset),
.R(1'b0));
system_axi_gpio_0_0_GPIO_Core gpio_core_1
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13],DBus_Reg[14],DBus_Reg[15],DBus_Reg[16],DBus_Reg[17],DBus_Reg[18],DBus_Reg[19]}),
.E(AXI_LITE_IPIF_I_n_49),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_intr(GPIO_intr),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.gpio_OE_reg[10]_0 (AXI_LITE_IPIF_I_n_37),
.\Not_Dual.gpio_OE_reg[11]_0 (AXI_LITE_IPIF_I_n_36),
.\Not_Dual.gpio_OE_reg[12]_0 (AXI_LITE_IPIF_I_n_35),
.\Not_Dual.gpio_OE_reg[13]_0 (AXI_LITE_IPIF_I_n_34),
.\Not_Dual.gpio_OE_reg[14]_0 (AXI_LITE_IPIF_I_n_33),
.\Not_Dual.gpio_OE_reg[15]_0 (AXI_LITE_IPIF_I_n_32),
.\Not_Dual.gpio_OE_reg[16]_0 (AXI_LITE_IPIF_I_n_31),
.\Not_Dual.gpio_OE_reg[17]_0 (AXI_LITE_IPIF_I_n_30),
.\Not_Dual.gpio_OE_reg[18]_0 (AXI_LITE_IPIF_I_n_29),
.\Not_Dual.gpio_OE_reg[19]_0 (AXI_LITE_IPIF_I_n_28),
.\Not_Dual.gpio_OE_reg[1]_0 (AXI_LITE_IPIF_I_n_46),
.\Not_Dual.gpio_OE_reg[2]_0 (AXI_LITE_IPIF_I_n_45),
.\Not_Dual.gpio_OE_reg[3]_0 (AXI_LITE_IPIF_I_n_44),
.\Not_Dual.gpio_OE_reg[4]_0 (AXI_LITE_IPIF_I_n_43),
.\Not_Dual.gpio_OE_reg[5]_0 (AXI_LITE_IPIF_I_n_42),
.\Not_Dual.gpio_OE_reg[6]_0 (AXI_LITE_IPIF_I_n_41),
.\Not_Dual.gpio_OE_reg[7]_0 (AXI_LITE_IPIF_I_n_40),
.\Not_Dual.gpio_OE_reg[8]_0 (AXI_LITE_IPIF_I_n_39),
.\Not_Dual.gpio_OE_reg[9]_0 (AXI_LITE_IPIF_I_n_38),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13],gpio_Data_In[14],gpio_Data_In[15],gpio_Data_In[16],gpio_Data_In[17],gpio_Data_In[18],gpio_Data_In[19]}),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_48),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_data({ip2bus_data[12],ip2bus_data[13],ip2bus_data[14],ip2bus_data[15],ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[12]),
.Q(ip2bus_data_i_D1[12]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[13]),
.Q(ip2bus_data_i_D1[13]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[14]),
.Q(ip2bus_data_i_D1[14]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[15]),
.Q(ip2bus_data_i_D1[15]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[16]),
.Q(ip2bus_data_i_D1[16]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[17]),
.Q(ip2bus_data_i_D1[17]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[18]),
.Q(ip2bus_data_i_D1[18]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[19]),
.Q(ip2bus_data_i_D1[19]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[20]),
.Q(ip2bus_data_i_D1[20]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[21]),
.Q(ip2bus_data_i_D1[21]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[22]),
.Q(ip2bus_data_i_D1[22]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[23]),
.Q(ip2bus_data_i_D1[23]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data_i),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_i),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module system_axi_gpio_0_0_axi_lite_ipif
(p_8_in,
bus2ip_rnw,
bus2ip_cs,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0] ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0] ,
ipif_glbl_irpt_enable_reg_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
gpio_io_t,
Q,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]_0 );
output p_8_in;
output bus2ip_rnw;
output [0:0]bus2ip_cs;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [19:0]D;
output \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ;
output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ;
output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ;
output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ;
output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ;
output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0] ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0] ;
output ipif_glbl_irpt_enable_reg_reg;
output [20:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [6:0]s_axi_awaddr;
input [6:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [31:0]s_axi_wdata;
input [19:0]gpio_io_t;
input [19:0]Q;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input [20:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire Bus_RNW_reg;
wire [19:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ;
wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ;
wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ;
wire \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ;
wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ;
wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire [19:0]Q;
wire Read_Reg_Rst;
wire [0:0]bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [19:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire [1:0]\ip2bus_data_i_D1_reg[0] ;
wire [20:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
wire p_8_in;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [20:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
system_axi_gpio_0_0_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
.\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] (\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ),
.\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] (\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ),
.\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] (\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ),
.\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ),
.\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ),
.\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ),
.\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ),
.\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] (\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ),
.\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] (\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ),
.\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] (\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] (\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] (\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] (\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] (\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] (\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] (\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] (\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ),
.\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] (\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ),
.\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] (\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_Data_Out_reg[19] (bus2ip_cs),
.\Not_Dual.gpio_OE_reg[0] (bus2ip_rnw),
.Q(Q),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_reset(bus2ip_reset),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data),
.\ip2bus_data_i_D1_reg[0] (p_8_in),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_1 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (Bus_RNW_reg),
.\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0] ),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_axi_gpio_0_0_cdc_sync
(D,
scndry_vect_out,
Q,
gpio_io_i,
s_axi_aclk);
output [19:0]D;
output [19:0]scndry_vect_out;
input [19:0]Q;
input [19:0]gpio_io_i;
input s_axi_aclk;
wire [19:0]D;
wire [19:0]Q;
wire [19:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_10;
wire s_level_out_bus_d1_cdc_to_11;
wire s_level_out_bus_d1_cdc_to_12;
wire s_level_out_bus_d1_cdc_to_13;
wire s_level_out_bus_d1_cdc_to_14;
wire s_level_out_bus_d1_cdc_to_15;
wire s_level_out_bus_d1_cdc_to_16;
wire s_level_out_bus_d1_cdc_to_17;
wire s_level_out_bus_d1_cdc_to_18;
wire s_level_out_bus_d1_cdc_to_19;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d1_cdc_to_8;
wire s_level_out_bus_d1_cdc_to_9;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_10;
wire s_level_out_bus_d2_11;
wire s_level_out_bus_d2_12;
wire s_level_out_bus_d2_13;
wire s_level_out_bus_d2_14;
wire s_level_out_bus_d2_15;
wire s_level_out_bus_d2_16;
wire s_level_out_bus_d2_17;
wire s_level_out_bus_d2_18;
wire s_level_out_bus_d2_19;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d2_8;
wire s_level_out_bus_d2_9;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_10;
wire s_level_out_bus_d3_11;
wire s_level_out_bus_d3_12;
wire s_level_out_bus_d3_13;
wire s_level_out_bus_d3_14;
wire s_level_out_bus_d3_15;
wire s_level_out_bus_d3_16;
wire s_level_out_bus_d3_17;
wire s_level_out_bus_d3_18;
wire s_level_out_bus_d3_19;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire s_level_out_bus_d3_8;
wire s_level_out_bus_d3_9;
wire [19:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_10),
.Q(s_level_out_bus_d2_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_11),
.Q(s_level_out_bus_d2_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_12),
.Q(s_level_out_bus_d2_12),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_13),
.Q(s_level_out_bus_d2_13),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_14),
.Q(s_level_out_bus_d2_14),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_15),
.Q(s_level_out_bus_d2_15),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_16),
.Q(s_level_out_bus_d2_16),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_17),
.Q(s_level_out_bus_d2_17),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_18),
.Q(s_level_out_bus_d2_18),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_19),
.Q(s_level_out_bus_d2_19),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_8),
.Q(s_level_out_bus_d2_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_9),
.Q(s_level_out_bus_d2_9),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_10),
.Q(s_level_out_bus_d3_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_11),
.Q(s_level_out_bus_d3_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_12),
.Q(s_level_out_bus_d3_12),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_13),
.Q(s_level_out_bus_d3_13),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_14),
.Q(s_level_out_bus_d3_14),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_15),
.Q(s_level_out_bus_d3_15),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_16),
.Q(s_level_out_bus_d3_16),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_17),
.Q(s_level_out_bus_d3_17),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_18),
.Q(s_level_out_bus_d3_18),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_19),
.Q(s_level_out_bus_d3_19),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_8),
.Q(s_level_out_bus_d3_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_9),
.Q(s_level_out_bus_d3_9),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_10),
.Q(scndry_vect_out[10]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_11),
.Q(scndry_vect_out[11]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_12),
.Q(scndry_vect_out[12]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_13),
.Q(scndry_vect_out[13]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_14),
.Q(scndry_vect_out[14]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_15),
.Q(scndry_vect_out[15]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_16),
.Q(scndry_vect_out[16]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_17),
.Q(scndry_vect_out[17]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_18),
.Q(scndry_vect_out[18]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_19),
.Q(scndry_vect_out[19]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_8),
.Q(scndry_vect_out[8]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_9),
.Q(scndry_vect_out[9]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[10]),
.Q(s_level_out_bus_d1_cdc_to_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[11]),
.Q(s_level_out_bus_d1_cdc_to_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[12]),
.Q(s_level_out_bus_d1_cdc_to_12),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[13]),
.Q(s_level_out_bus_d1_cdc_to_13),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[14]),
.Q(s_level_out_bus_d1_cdc_to_14),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[15]),
.Q(s_level_out_bus_d1_cdc_to_15),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[16]),
.Q(s_level_out_bus_d1_cdc_to_16),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[17]),
.Q(s_level_out_bus_d1_cdc_to_17),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[18]),
.Q(s_level_out_bus_d1_cdc_to_18),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[19]),
.Q(s_level_out_bus_d1_cdc_to_19),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[8]),
.Q(s_level_out_bus_d1_cdc_to_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[9]),
.Q(s_level_out_bus_d1_cdc_to_9),
.R(1'b0));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1
(.I0(Q[19]),
.I1(scndry_vect_out[19]),
.O(D[19]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1
(.I0(Q[9]),
.I1(scndry_vect_out[9]),
.O(D[9]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1
(.I0(Q[8]),
.I1(scndry_vect_out[8]),
.O(D[8]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1
(.I0(Q[7]),
.I1(scndry_vect_out[7]),
.O(D[7]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1
(.I0(Q[6]),
.I1(scndry_vect_out[6]),
.O(D[6]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[14]_i_1
(.I0(Q[5]),
.I1(scndry_vect_out[5]),
.O(D[5]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[15]_i_1
(.I0(Q[4]),
.I1(scndry_vect_out[4]),
.O(D[4]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[16]_i_1
(.I0(Q[3]),
.I1(scndry_vect_out[3]),
.O(D[3]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[17]_i_1
(.I0(Q[2]),
.I1(scndry_vect_out[2]),
.O(D[2]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[18]_i_1
(.I0(Q[1]),
.I1(scndry_vect_out[1]),
.O(D[1]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[19]_i_1
(.I0(Q[0]),
.I1(scndry_vect_out[0]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1
(.I0(Q[18]),
.I1(scndry_vect_out[18]),
.O(D[18]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1
(.I0(Q[17]),
.I1(scndry_vect_out[17]),
.O(D[17]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1
(.I0(Q[16]),
.I1(scndry_vect_out[16]),
.O(D[16]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1
(.I0(Q[15]),
.I1(scndry_vect_out[15]),
.O(D[15]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1
(.I0(Q[14]),
.I1(scndry_vect_out[14]),
.O(D[14]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1
(.I0(Q[13]),
.I1(scndry_vect_out[13]),
.O(D[13]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1
(.I0(Q[12]),
.I1(scndry_vect_out[12]),
.O(D[12]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1
(.I0(Q[11]),
.I1(scndry_vect_out[11]),
.O(D[11]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1
(.I0(Q[10]),
.I1(scndry_vect_out[10]),
.O(D[10]));
endmodule
(* ORIG_REF_NAME = "interrupt_control" *)
module system_axi_gpio_0_0_interrupt_control
(irpt_wrack_d1,
p_3_in,
irpt_rdack_d1,
p_1_in,
p_0_in,
IP2INTC_Irpt_i,
ip2bus_wrack_i,
ip2bus_rdack_i,
bus2ip_reset,
irpt_wrack,
s_axi_aclk,
GPIO_intr,
interrupt_wrce_strb,
irpt_rdack,
intr2bus_rdack0,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ,
p_8_in,
s_axi_wdata,
Bus_RNW_reg,
ip2Bus_WrAck_intr_reg_hole,
bus2ip_rnw,
GPIO_xferAck_i,
ip2Bus_RdAck_intr_reg_hole);
output irpt_wrack_d1;
output [0:0]p_3_in;
output irpt_rdack_d1;
output [0:0]p_1_in;
output [0:0]p_0_in;
output IP2INTC_Irpt_i;
output ip2bus_wrack_i;
output ip2bus_rdack_i;
input bus2ip_reset;
input irpt_wrack;
input s_axi_aclk;
input GPIO_intr;
input interrupt_wrce_strb;
input irpt_rdack;
input intr2bus_rdack0;
input \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
input \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
input p_8_in;
input [0:0]s_axi_wdata;
input Bus_RNW_reg;
input ip2Bus_WrAck_intr_reg_hole;
input bus2ip_rnw;
input GPIO_xferAck_i;
input ip2Bus_RdAck_intr_reg_hole;
wire Bus_RNW_reg;
wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire IP2INTC_Irpt_i;
wire bus2ip_reset;
wire bus2ip_rnw;
wire interrupt_wrce_strb;
wire intr2bus_rdack;
wire intr2bus_rdack0;
wire intr2bus_wrack;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i;
wire irpt_dly1;
wire irpt_dly2;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
wire p_8_in;
wire s_axi_aclk;
wire [0:0]s_axi_wdata;
FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_intr),
.Q(irpt_dly1),
.S(bus2ip_reset));
FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_dly1),
.Q(irpt_dly2),
.S(bus2ip_reset));
LUT6 #(
.INIT(64'hF4F4F4F44FF4F4F4))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1
(.I0(irpt_dly2),
.I1(irpt_dly1),
.I2(p_3_in),
.I3(p_8_in),
.I4(s_axi_wdata),
.I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2
(.I0(irpt_wrack_d1),
.I1(Bus_RNW_reg),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ));
FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ),
.Q(p_3_in),
.R(bus2ip_reset));
LUT3 #(
.INIT(8'h80))
\INTR_CTRLR_GEN.ip2intc_irpt_i_1
(.I0(p_3_in),
.I1(p_1_in),
.I2(p_0_in),
.O(IP2INTC_Irpt_i));
FDRE intr2bus_rdack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr2bus_rdack0),
.Q(intr2bus_rdack),
.R(bus2ip_reset));
FDRE intr2bus_wrack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(interrupt_wrce_strb),
.Q(intr2bus_wrack),
.R(bus2ip_reset));
LUT4 #(
.INIT(16'hFEEE))
ip2bus_rdack_i_D1_i_1
(.I0(ip2Bus_RdAck_intr_reg_hole),
.I1(intr2bus_rdack),
.I2(bus2ip_rnw),
.I3(GPIO_xferAck_i),
.O(ip2bus_rdack_i));
LUT4 #(
.INIT(16'hEFEE))
ip2bus_wrack_i_D1_i_1
(.I0(ip2Bus_WrAck_intr_reg_hole),
.I1(intr2bus_wrack),
.I2(bus2ip_rnw),
.I3(GPIO_xferAck_i),
.O(ip2bus_wrack_i));
FDRE \ip_irpt_enable_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ),
.Q(p_1_in),
.R(bus2ip_reset));
FDRE ipif_glbl_irpt_enable_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ),
.Q(p_0_in),
.R(bus2ip_reset));
FDRE irpt_rdack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_rdack),
.Q(irpt_rdack_d1),
.R(bus2ip_reset));
FDRE irpt_wrack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_wrack),
.Q(irpt_wrack_d1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module system_axi_gpio_0_0_slave_attachment
(\ip2bus_data_i_D1_reg[0] ,
\Not_Dual.gpio_OE_reg[0] ,
\Not_Dual.gpio_Data_Out_reg[19] ,
\ip_irpt_enable_reg_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0]_0 ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0]_0 ,
ipif_glbl_irpt_enable_reg_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
gpio_io_t,
Q,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]_1 );
output \ip2bus_data_i_D1_reg[0] ;
output \Not_Dual.gpio_OE_reg[0] ;
output \Not_Dual.gpio_Data_Out_reg[19] ;
output \ip_irpt_enable_reg_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [19:0]D;
output \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ;
output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ;
output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ;
output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ;
output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ;
output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0]_0 ;
output ipif_glbl_irpt_enable_reg_reg;
output [20:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [6:0]s_axi_awaddr;
input [6:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [31:0]s_axi_wdata;
input [19:0]gpio_io_t;
input [19:0]Q;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input [20:0]\ip2bus_data_i_D1_reg[0]_1 ;
wire [19:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ;
wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ;
wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ;
wire \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ;
wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ;
wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_Data_Out_reg[19] ;
wire \Not_Dual.gpio_OE_reg[0] ;
wire [19:0]Q;
wire Read_Reg_Rst;
wire [0:6]bus2ip_addr;
wire bus2ip_reset;
wire bus2ip_rnw_i06_out;
wire clear;
wire [19:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire \ip2bus_data_i_D1_reg[0] ;
wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire [20:0]\ip2bus_data_i_D1_reg[0]_1 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire \ip_irpt_enable_reg_reg[0]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [0:0]p_0_in;
wire [1:0]p_0_out__0;
wire [0:0]p_1_in;
wire [8:2]p_1_in__0;
wire [0:0]p_3_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [20:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
system_axi_gpio_0_0_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
.\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] (\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22] ),
.\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] (\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23] ),
.\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] (\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24] ),
.\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25] ),
.\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26] ),
.\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27] ),
.\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28] ),
.\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] (\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29] ),
.\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] (\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30] ),
.\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] (\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31] ),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] (\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13] ),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] (\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14] ),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] (\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15] ),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] (\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16] ),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] (\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17] ),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] (\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18] ),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] (\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19] ),
.\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] (\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20] ),
.\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] (\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21] ),
.\Not_Dual.gpio_Data_In_reg[0] (Q),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_Data_Out_reg[19] (\Not_Dual.gpio_Data_Out_reg[19] ),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Read_Reg_Rst(Read_Reg_Rst),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_OE_reg[0] ),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (\ip_irpt_enable_reg_reg[0] ),
.\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0]_0 ),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2(start2));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[0]),
.O(p_1_in__0[2]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[1]),
.O(p_1_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_awaddr[2]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[2]),
.O(p_1_in__0[4]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[5]_i_1
(.I0(s_axi_awaddr[3]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[3]),
.O(p_1_in__0[5]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[6]_i_1
(.I0(s_axi_awaddr[4]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[4]),
.O(p_1_in__0[6]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[7]_i_1
(.I0(s_axi_awaddr[5]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[5]),
.O(p_1_in__0[7]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_awaddr[6]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[6]),
.O(p_1_in__0[8]));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[2]),
.Q(bus2ip_addr[6]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[3]),
.Q(bus2ip_addr[5]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[4]),
.Q(bus2ip_addr[4]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[5]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[5]),
.Q(bus2ip_addr[3]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[6]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[6]),
.Q(bus2ip_addr[2]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[7]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[7]),
.Q(bus2ip_addr[1]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[8]),
.Q(bus2ip_addr[0]),
.R(bus2ip_reset));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_OE_reg[0] ),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\state[1]_i_2_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(bus2ip_reset));
LUT6 #(
.INIT(64'h1000FFFF10000000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wvalid),
.I3(s_axi_awvalid),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(state[1]),
.I5(state[0]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(bus2ip_reset));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [0]),
.Q(s_axi_rdata[0]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [10]),
.Q(s_axi_rdata[10]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [11]),
.Q(s_axi_rdata[11]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [12]),
.Q(s_axi_rdata[12]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [13]),
.Q(s_axi_rdata[13]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [14]),
.Q(s_axi_rdata[14]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [15]),
.Q(s_axi_rdata[15]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[16]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [16]),
.Q(s_axi_rdata[16]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[17]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [17]),
.Q(s_axi_rdata[17]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[18]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [18]),
.Q(s_axi_rdata[18]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[19]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [19]),
.Q(s_axi_rdata[19]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [1]),
.Q(s_axi_rdata[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [2]),
.Q(s_axi_rdata[2]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [20]),
.Q(s_axi_rdata[20]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [3]),
.Q(s_axi_rdata[3]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [4]),
.Q(s_axi_rdata[4]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [5]),
.Q(s_axi_rdata[5]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [6]),
.Q(s_axi_rdata[6]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [7]),
.Q(s_axi_rdata[7]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [8]),
.Q(s_axi_rdata[8]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [9]),
.Q(s_axi_rdata[9]),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h0FFFAACC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arvalid),
.I2(\state[1]_i_2_n_0 ),
.I3(state[1]),
.I4(state[0]),
.O(p_0_out__0[0]));
LUT6 #(
.INIT(64'h2E2E2E2ECCCCFFCC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(\state[1]_i_3_n_0 ),
.I4(s_axi_arvalid),
.I5(state[0]),
.O(p_0_out__0[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out__0[0]),
.Q(state[0]),
.R(bus2ip_reset));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out__0[1]),
.Q(state[1]),
.R(bus2ip_reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
assign uart_rts = 0;
eth_mac_1g_gmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rx_clk(phy_rx_clk),
.gmii_rxd(phy_rxd),
.gmii_rx_dv(phy_rx_dv),
.gmii_rx_er(phy_rx_er),
.gmii_tx_clk(phy_gtx_clk),
.mii_tx_clk(phy_tx_clk),
.gmii_txd(phy_txd),
.gmii_tx_en(phy_tx_en),
.gmii_tx_er(phy_tx_er),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT_IBUFDISABLE.v
// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 04/04/11 - CR 604808 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT_IBUFDISABLE (O, OB, I, IB, IBUFDISABLE);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
input I;
input IB;
input IBUFDISABLE;
// define constants
localparam MODULE_NAME = "IBUFDS_DIFF_OUT_IBUFDISABLE";
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
wire out_val;
wire out_b_val;
initial begin
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
#1 $finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
end
always @(I or IB or DQS_BIAS_BINARY) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (I === 1'bx || IB === 1'bx)
o_out <= 1'bx;
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
assign out_b_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
assign out_b_val = 1'bx;
end
default : begin
assign out_val = 1'b0;
assign out_b_val = 1'b0;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? o_out : (IBUFDISABLE == 1)? out_val : 1'bx;
assign OB = (IBUFDISABLE == 0)? ~o_out : (IBUFDISABLE == 1)? out_b_val : 1'bx;
end
"FALSE" : begin
assign O = o_out;
assign OB = ~o_out;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module axi_hdmi_tx (
// hdmi interface
hdmi_clk,
hdmi_out_clk,
// 16-bit interface
hdmi_16_hsync,
hdmi_16_vsync,
hdmi_16_data_e,
hdmi_16_data,
hdmi_16_es_data,
// 24-bit interface
hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_data_e,
hdmi_24_data,
// 36-bit interface
hdmi_36_hsync,
hdmi_36_vsync,
hdmi_36_data_e,
hdmi_36_data,
// vdma interface
m_axis_mm2s_clk,
m_axis_mm2s_fsync,
m_axis_mm2s_fsync_ret,
m_axis_mm2s_tvalid,
m_axis_mm2s_tdata,
m_axis_mm2s_tkeep,
m_axis_mm2s_tlast,
m_axis_mm2s_tready,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_Cr_Cb_N = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_EMBEDDED_SYNC = 0;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;
localparam ALTERA_5SERIES = 16;
// hdmi interface
input hdmi_clk;
output hdmi_out_clk;
// 16-bit interface
output hdmi_16_hsync;
output hdmi_16_vsync;
output hdmi_16_data_e;
output [15:0] hdmi_16_data;
output [15:0] hdmi_16_es_data;
// 24-bit interface
output hdmi_24_hsync;
output hdmi_24_vsync;
output hdmi_24_data_e;
output [23:0] hdmi_24_data;
// 36-bit interface
output hdmi_36_hsync;
output hdmi_36_vsync;
output hdmi_36_data_e;
output [35:0] hdmi_36_data;
// vdma interface
input m_axis_mm2s_clk;
output m_axis_mm2s_fsync;
input m_axis_mm2s_fsync_ret;
input m_axis_mm2s_tvalid;
input [63:0] m_axis_mm2s_tdata;
input [ 7:0] m_axis_mm2s_tkeep;
input m_axis_mm2s_tlast;
output m_axis_mm2s_tready;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// reset and clocks
wire up_rstn;
wire up_clk;
wire hdmi_rst;
wire vdma_clk;
wire vdma_rst;
// internal signals
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire hdmi_full_range_s;
wire hdmi_csc_bypass_s;
wire hdmi_ss_bypass_s;
wire [ 1:0] hdmi_srcsel_s;
wire [23:0] hdmi_const_rgb_s;
wire [15:0] hdmi_hl_active_s;
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_hs_width_s;
wire [15:0] hdmi_he_max_s;
wire [15:0] hdmi_he_min_s;
wire [15:0] hdmi_vf_active_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_vs_width_s;
wire [15:0] hdmi_ve_max_s;
wire [15:0] hdmi_ve_min_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
wire hdmi_status_s;
wire vdma_fs_s;
wire vdma_fs_ret_s;
wire vdma_valid_s;
wire [63:0] vdma_data_s;
wire vdma_ready_s;
wire vdma_wr_s;
wire [ 8:0] vdma_waddr_s;
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire vdma_tpm_oos_s;
// signal name changes
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
assign vdma_clk = m_axis_mm2s_clk;
assign vdma_valid_s = m_axis_mm2s_tvalid;
assign vdma_data_s = m_axis_mm2s_tdata;
assign vdma_fs_ret_s = m_axis_mm2s_fsync_ret;
assign m_axis_mm2s_fsync = vdma_fs_s;
assign m_axis_mm2s_tready = vdma_ready_s;
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// processor interface
up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_status (hdmi_status_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_clk_ratio (32'd1),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// vdma interface
axi_hdmi_tx_vdma i_vdma (
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_fs (vdma_fs_s),
.vdma_fs_ret (vdma_fs_ret_s),
.vdma_valid (vdma_valid_s),
.vdma_data (vdma_data_s),
.vdma_ready (vdma_ready_s),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s));
// hdmi interface
axi_hdmi_tx_core #(
.Cr_Cb_N(PCORE_Cr_Cb_N),
.EMBEDDED_SYNC(PCORE_EMBEDDED_SYNC))
i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
.hdmi_16_data (hdmi_16_data),
.hdmi_16_es_data (hdmi_16_es_data),
.hdmi_24_hsync (hdmi_24_hsync),
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
.hdmi_36_data (hdmi_36_data),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_status (hdmi_status_s),
.vdma_clk (vdma_clk),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s));
// hdmi output clock
generate
if (PCORE_DEVICE_TYPE == XILINX_ULTRASCALE) begin
ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
.SR (1'b0),
.D1 (1'b1),
.D2 (1'b0),
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
if (PCORE_DEVICE_TYPE == ALTERA_5SERIES) begin
altddio_out #(.WIDTH(1)) i_clk_oddr (
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.oe (1'b1),
.outclocken (1'b1),
.datain_h (1'b1),
.datain_l (1'b0),
.outclock (hdmi_clk),
.oe_out (),
.dataout (hdmi_out_clk));
end
if (PCORE_DEVICE_TYPE == XILINX_7SERIES) begin
ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_2_V
`define SKY130_FD_SC_HDLL__DLRTN_2_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_2_V
|
`default_nettype none
module uart_rx
(
input wire clk, // 9600hz
input wire rst_n,
input wire rx_in,
output reg [7:0] rx_data,
output reg rx_rdy
);
localparam IDLE = 0;
localparam BIT_0 = 1;
localparam BIT_1 = 2;
localparam BIT_2 = 3;
localparam BIT_3 = 4;
localparam BIT_4 = 5;
localparam BIT_5 = 6;
localparam BIT_6 = 7;
localparam BIT_7 = 8;
localparam READY = 9;
reg [3:0] state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= IDLE;
rx_data <= 0;
rx_rdy <= 0;
end
else begin
case (state)
IDLE: begin
rx_rdy <= 0;
if (rx_in == 1'b0)
state <= BIT_0;
end
BIT_0: begin
rx_data[0] <= rx_in;
state <= BIT_1;
end
BIT_1: begin
rx_data[1] <= rx_in;
state <= BIT_2;
end
BIT_2: begin
rx_data[2] <= rx_in;
state <= BIT_3;
end
BIT_3: begin
rx_data[3] <= rx_in;
state <= BIT_4;
end
BIT_4: begin
rx_data[4] <= rx_in;
state <= BIT_5;
end
BIT_5: begin
rx_data[5] <= rx_in;
state <= BIT_6;
end
BIT_6: begin
rx_data[6] <= rx_in;
state <= BIT_7;
end
BIT_7: begin
rx_data[7] <= rx_in;
state <= READY;
end
READY: begin
rx_rdy <= 1;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
`default_nettype wire
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module drives the vga dac on Altera's DE2 Board. *
* *
******************************************************************************/
module altera_up_avalon_video_vga_timing (
// inputs
clk,
reset,
red_to_vga_display,
green_to_vga_display,
blue_to_vga_display,
color_select,
// bidirectional
// outputs
read_enable,
end_of_active_frame,
end_of_frame,
// dac pins
vga_blank, // VGA BLANK
vga_c_sync, // VGA COMPOSITE SYNC
vga_h_sync, // VGA H_SYNC
vga_v_sync, // VGA V_SYNC
vga_data_enable, // VGA DEN
vga_red, // VGA Red[9:0]
vga_green, // VGA Green[9:0]
vga_blue, // VGA Blue[9:0]
vga_color_data // VGA Color[9:0] for TRDB_LCM
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter PW = 10; // Number of bits for pixels
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
parameter LW = 10; // Number of bits for lines
parameter LINE_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [CW: 0] red_to_vga_display;
input [CW: 0] green_to_vga_display;
input [CW: 0] blue_to_vga_display;
input [ 3: 0] color_select;
// Bidirectionals
// Outputs
output read_enable;
output reg end_of_active_frame;
output reg end_of_frame;
// dac pins
output reg vga_blank; // VGA BLANK
output reg vga_c_sync; // VGA COMPOSITE SYNC
output reg vga_h_sync; // VGA H_SYNC
output reg vga_v_sync; // VGA V_SYNC
output reg vga_data_enable; // VGA DEN
output reg [CW: 0] vga_red; // VGA Red[9:0]
output reg [CW: 0] vga_green; // VGA Green[9:0]
output reg [CW: 0] vga_blue; // VGA Blue[9:0]
output reg [CW: 0] vga_color_data; // VGA Color[9:0] for TRDB_LCM
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
//reg clk_en;
reg [PW:1] pixel_counter;
reg [LW:1] line_counter;
reg early_hsync_pulse;
reg early_vsync_pulse;
reg hsync_pulse;
reg vsync_pulse;
reg csync_pulse;
reg hblanking_pulse;
reg vblanking_pulse;
reg blanking_pulse;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
vga_c_sync <= 1'b1;
vga_blank <= 1'b1;
vga_h_sync <= 1'b1;
vga_v_sync <= 1'b1;
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_blank <= ~blanking_pulse;
vga_c_sync <= ~csync_pulse;
vga_h_sync <= ~hsync_pulse;
vga_v_sync <= ~vsync_pulse;
// vga_data_enable <= hsync_pulse | vsync_pulse;
vga_data_enable <= ~blanking_pulse;
if (blanking_pulse)
begin
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_red <= red_to_vga_display;
vga_green <= green_to_vga_display;
vga_blue <= blue_to_vga_display;
vga_color_data <= ({(CW + 1){color_select[0]}} & red_to_vga_display) |
({(CW + 1){color_select[1]}} & green_to_vga_display) |
({(CW + 1){color_select[2]}} & blue_to_vga_display);
end
end
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
begin
pixel_counter <= H_TOTAL - 3; // {PW{1'b0}};
line_counter <= V_TOTAL - 1; // {LW{1'b0}};
end
else
begin
// last pixel in the line
if (pixel_counter == (H_TOTAL - 1))
begin
pixel_counter <= {PW{1'b0}};
// last pixel in last line of frame
if (line_counter == (V_TOTAL - 1))
line_counter <= {LW{1'b0}};
// last pixel but not last line
else
line_counter <= line_counter + LINE_COUNTER_INCREMENT;
end
else
pixel_counter <= pixel_counter + PIXEL_COUNTER_INCREMENT;
end
end
always @ (posedge clk)
begin
if (reset)
begin
end_of_active_frame <= 1'b0;
end_of_frame <= 1'b0;
end
else
begin
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_ACTIVE - 2)))
end_of_active_frame <= 1'b1;
else
end_of_active_frame <= 1'b0;
if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
end_of_frame <= 1'b1;
else
end_of_frame <= 1'b0;
end
end
always @ (posedge clk)
begin
if (reset)
begin
early_hsync_pulse <= 1'b0;
early_vsync_pulse <= 1'b0;
hsync_pulse <= 1'b0;
vsync_pulse <= 1'b0;
csync_pulse <= 1'b0;
end
else
begin
// start of horizontal sync
if (pixel_counter == (H_ACTIVE + H_FRONT_PORCH - 2))
early_hsync_pulse <= 1'b1;
// end of horizontal sync
else if (pixel_counter == (H_TOTAL - H_BACK_PORCH - 2))
early_hsync_pulse <= 1'b0;
// start of vertical sync
if ((line_counter == (V_ACTIVE + V_FRONT_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b1;
// end of vertical sync
else if ((line_counter == (V_TOTAL - V_BACK_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b0;
hsync_pulse <= early_hsync_pulse;
vsync_pulse <= early_vsync_pulse;
csync_pulse <= early_hsync_pulse ^ early_vsync_pulse;
end
end
always @ (posedge clk)
begin
if (reset)
begin
hblanking_pulse <= 1'b1;
vblanking_pulse <= 1'b1;
blanking_pulse <= 1'b1;
end
else
begin
if (pixel_counter == (H_ACTIVE - 2))
hblanking_pulse <= 1'b1;
else if (pixel_counter == (H_TOTAL - 2))
hblanking_pulse <= 1'b0;
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b1;
else if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b0;
blanking_pulse <= hblanking_pulse | vblanking_pulse;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign read_enable = ~blanking_pulse;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXC Engine (Ultrascale) takes a single stream of
// AXI packets and provides the completion packets on the RXC Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "ultrascale.vh"
module rxc_engine_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10,
// Number of data pipeline registers for metadata and data stages
parameter C_RX_META_STAGES = 0,
parameter C_RX_DATA_STAGES = 1
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: RC
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP
);
`include "functions.vh"
// Width of the Byte Enable Shift register
localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 0;
localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
localparam C_RX_METADW0_CYCLE = (`UPKT_RXC_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`UPKT_RXC_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW2_CYCLE = (`UPKT_RXC_METADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXC_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW2_I%C_PCI_DATA_WIDTH);
localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
// Mask width of the calculated SOF/EOF fields
localparam C_OFFSET_WIDTH = clog2(C_PCI_DATA_WIDTH/32);
wire wMAxisRcSop;
wire wMAxisRcTlast;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrEop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrDataValid;
wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
wire wRxcDataValid;
wire wRxcDataReady; // Pinned High
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire wRxcDataEndFlag;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire wRxcDataStartFlag;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire [`SIG_BYTECNT_W-1:0] wRxcMetaBytesRemaining;
wire [`SIG_CPLID_W-1:0] wRxcMetaCompleterId;
wire [`UPKT_RXC_MAXHDR_W-1:0] wRxcHdr;
wire [`SIG_TYPE_W-1:0] wRxcType;
wire [`SIG_BARDECODE_W-1:0] wRxcBarDecoded;
wire [`UPKT_RXC_MAXHDR_W-1:0] wHdr;
wire [`SIG_TYPE_W-1:0] wType;
wire wHasPayload;
wire _wEndFlag;
wire wEndFlag;
wire wEndFlagLastCycle;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wStartFlag;
wire wStartFlag;
wire [1:0] wStartFlags;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wStartOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [C_OFFSET_WIDTH-1:0] wOffsetMask;
reg rValid,_rValid;
assign wMAxisRcSop = M_AXIS_RC_TUSER[`UPKT_RC_TUSER_SOP_I];
assign wMAxisRcTlast = M_AXIS_RC_TLAST;
// We assert the end flag on the last cycle of a packet, however on single
// cycle packets we need to check that there wasn't an end flag last cycle
// (because wStartFlag will take priority when setting rValid) so we can
// deassert rValid if necessary.
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
/* verilator lint_off WIDTH */
assign wStartOffset = 3;
assign wEndOffset = wHdr[`UPKT_RXC_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXC_MAXHDR_W-32)/32);
/* verilator lint_on WIDTH */
// Output assignments. See the header file derived from the user
// guide for indices.
assign RXC_META_LENGTH = wRxcHdr[`UPKT_RXC_LENGTH_I+:`SIG_LEN_W];
//assign RXC_META_ATTR = wRxcHdr[`UPKT_RXC_ATTR_R];
//assign RXC_META_TC = wRxcHdr[`UPKT_RXC_TC_R];
assign RXC_META_TAG = wRxcHdr[`UPKT_RXC_TAG_R];
assign RXC_META_FDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_LDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_ADDR = wRxcHdr[(`UPKT_RXC_ADDRLOW_I) +: `SIG_LOWADDR_W];
assign RXC_DATA_START_FLAG = wRxcDataStartFlag;
assign RXC_DATA_START_OFFSET = {C_PCI_DATA_WIDTH > 64, 1'b1};
assign RXC_DATA_END_FLAG = wRxcDataEndFlag;
assign RXC_DATA_END_OFFSET = wRxcDataEndOffset;
assign RXC_DATA_VALID = wRxcDataValid;
assign RXC_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXC_META_TYPE = wRxcType;
assign RXC_META_BYTES_REMAINING = wRxcHdr[`UPKT_RXC_BYTECNT_I +: `SIG_BYTECNT_W];
assign RXC_META_COMPLETER_ID = wRxcHdr[`UPKT_RXC_CPLID_R];
assign RXC_META_EP = wRxcHdr[`UPKT_RXC_EP_R];
assign M_AXIS_RC_TREADY = 1'b1;
assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
assign wType = (wHasPayload)? `TRLS_CPL_WD: `TRLS_CPL_ND;
generate
if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[0] = 0;
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1];
//assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end else begin // 256
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(RST_IN) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
register
#(
// Parameters
.C_WIDTH (1),
.C_VALUE (1'b0)
/*AUTOINSTPARAM*/)
start_flag_register
(
// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
register
#(
// Parameters
.C_WIDTH (32))
meta_DW2_register
(
// Outputs
.RD_DATA (wHdr[95:64]),
// Inputs
.WR_DATA (wRxSrData[C_RX_METADW2_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW2_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
register
#(
// Parameters
.C_WIDTH (32+1))
meta_DW1_register
(
// Outputs
.RD_DATA ({wHdr[63:32],wHasPayload}),
// Inputs
.WR_DATA ({wRxSrData[C_RX_METADW1_INDEX +: 32],wRxSrData[C_RX_METADW1_INDEX +: `UPKT_LEN_W] != 0}),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
register
#(
// Parameters
.C_WIDTH (32))
metadata_DW0_register
(
// Outputs
.RD_DATA (wHdr[31:0]),
// Inputs
.WR_DATA (wRxSrData[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Shift register for input data with output taps for each delayed
// cycle.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_PCI_DATA_WIDTH)
/*AUTOINSTPARAM*/)
data_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrData),
// Inputs
.WR_DATA (M_AXIS_RC_TDATA),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (wMAxisRcSop & M_AXIS_RC_TVALID),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// End Flag Shift Register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
eop_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrEop),
// Inputs
.WR_DATA (wMAxisRcTlast),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Data Valid Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
valid_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrDataValid),
// Inputs
.WR_DATA (M_AXIS_RC_TVALID),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset)
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXC_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wHasPayload}};
end else begin
register
#(
// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxcDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wHasPayload),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXC_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxcDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
end
endgenerate
// Shift register for input data with output taps for each delayed
// cycle.
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`UPKT_RXC_MAXHDR_W + 2*(1 + clog2(C_PCI_DATA_WIDTH/32))+`SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxcHdr,wRxcDataStartFlag,wRxcDataStartOffset,wRxcDataEndFlag,wRxcDataEndOffset,wRxcType}),
.RD_DATA_VALID (wRxcDataValid),
// Inputs
.WR_DATA ({wHdr,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wType}),
.WR_DATA_VALID (rValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: dds_adc_input.v
// /___/ /\ Timestamp: Fri Jul 19 09:46:19 2013
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/lerwys/Xilinx_projects/coregen/coregen/ipcore_dir/tmp/_cg/dds_adc_input.ngc /home/lerwys/Xilinx_projects/coregen/coregen/ipcore_dir/tmp/_cg/dds_adc_input.v
// Device : 6vlx240tff1156-1
// Input file : /home/lerwys/Xilinx_projects/coregen/coregen/ipcore_dir/tmp/_cg/dds_adc_input.ngc
// Output file : /home/lerwys/Xilinx_projects/coregen/coregen/ipcore_dir/tmp/_cg/dds_adc_input.v
// # of Modules : 1
// Design Name : dds_adc_input
// Xilinx : /opt/Xilinx/13.4/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module dds_adc_input (
aclk, m_axis_data_tvalid, m_axis_data_tdata
)/* synthesis syn_black_box syn_noprune=1 */;
input aclk;
output m_axis_data_tvalid;
output [31 : 0] m_axis_data_tdata;
// synthesis translate_off
wire \U0/i_synth/i_dds/i_rdy.i_single_channel.i_non_trivial_lat.i_rdy/opt_has_pipe.first_q ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire sig00000149;
wire sig0000014a;
wire sig0000014b;
wire sig0000014c;
wire sig0000014d;
wire sig0000014e;
wire sig0000014f;
wire sig00000150;
wire sig00000151;
wire sig00000152;
wire sig00000153;
wire sig00000154;
wire sig00000155;
wire sig00000156;
wire sig00000157;
wire sig00000158;
wire sig00000159;
wire sig0000015a;
wire sig0000015b;
wire sig0000015c;
wire sig0000015d;
wire sig0000015e;
wire sig0000015f;
wire sig00000160;
wire sig00000161;
wire sig00000162;
wire sig00000163;
wire sig00000164;
wire sig00000165;
wire sig00000166;
wire sig00000167;
wire sig00000168;
wire sig00000169;
wire sig0000016a;
wire sig0000016b;
wire sig0000016c;
wire sig0000016d;
wire sig0000016e;
wire sig0000016f;
wire sig00000170;
wire sig00000171;
wire sig00000172;
wire sig00000173;
wire sig00000174;
wire sig00000175;
wire sig00000176;
wire sig00000177;
wire sig00000178;
wire sig00000179;
wire sig0000017a;
wire sig0000017b;
wire sig0000017c;
wire sig0000017d;
wire sig0000017e;
wire sig0000017f;
wire sig00000180;
wire sig00000181;
wire sig00000182;
wire sig00000183;
wire sig00000184;
wire sig00000185;
wire sig00000186;
wire sig00000187;
wire sig00000188;
wire sig00000189;
wire sig0000018a;
wire sig0000018b;
wire sig0000018c;
wire sig0000018d;
wire sig0000018e;
wire sig0000018f;
wire sig00000190;
wire sig00000191;
wire sig00000192;
wire sig00000193;
wire sig00000194;
wire sig00000195;
wire sig00000196;
wire sig00000197;
wire sig00000198;
wire sig00000199;
wire sig0000019a;
wire sig0000019b;
wire sig0000019c;
wire sig0000019d;
wire sig0000019e;
wire sig0000019f;
wire sig000001a0;
wire sig000001a1;
wire sig000001a2;
wire sig000001a3;
wire sig000001a4;
wire sig000001a5;
wire sig000001a6;
wire sig000001a7;
wire sig000001a8;
wire sig000001a9;
wire sig000001aa;
wire sig000001ab;
wire sig000001ac;
wire sig000001ad;
wire sig000001ae;
wire sig000001af;
wire sig000001b0;
wire sig000001b1;
wire sig000001b2;
wire sig000001b3;
wire sig000001b4;
wire sig000001b5;
wire sig000001b6;
wire sig000001b7;
wire sig000001b8;
wire sig000001b9;
wire sig000001ba;
wire sig000001bb;
wire sig000001bc;
wire sig000001bd;
wire sig000001be;
wire sig000001bf;
wire \blk00000069/sig000002af ;
wire \blk00000069/sig000002ae ;
wire \blk00000069/sig000002ad ;
wire \blk00000069/sig000002ac ;
wire \blk00000069/sig000002ab ;
wire \blk00000069/sig000002aa ;
wire \blk00000069/sig000002a9 ;
wire \blk00000069/sig000002a8 ;
wire \blk00000069/sig000002a7 ;
wire \blk00000069/sig000002a6 ;
wire \blk00000069/sig000002a5 ;
wire \blk00000069/sig000002a4 ;
wire \blk00000069/sig000002a3 ;
wire \blk00000069/sig000002a2 ;
wire \blk00000069/sig000002a1 ;
wire \blk00000069/sig000002a0 ;
wire \blk00000069/sig0000029f ;
wire \blk00000069/sig0000029e ;
wire \blk00000069/sig0000029d ;
wire \blk00000069/sig0000029c ;
wire \blk00000069/sig0000029b ;
wire \blk00000069/sig0000029a ;
wire \blk00000069/sig00000299 ;
wire \blk00000069/sig00000298 ;
wire \blk00000069/sig00000297 ;
wire \blk00000069/sig00000296 ;
wire \blk00000069/sig00000295 ;
wire \blk00000069/sig00000294 ;
wire \blk00000069/sig00000293 ;
wire \blk00000069/sig00000292 ;
wire \blk00000069/sig00000291 ;
wire \blk00000069/sig00000290 ;
wire \blk00000069/sig0000028f ;
wire \blk00000069/sig0000028e ;
wire \blk00000069/sig0000028d ;
wire \blk00000069/sig0000028c ;
wire \blk00000069/sig0000028b ;
wire \blk00000069/sig0000028a ;
wire \blk00000069/sig00000289 ;
wire \blk00000069/sig00000288 ;
wire \blk00000069/sig00000287 ;
wire \blk00000069/sig00000286 ;
wire \blk00000069/sig00000285 ;
wire \blk00000069/sig00000284 ;
wire \blk00000069/sig00000283 ;
wire \blk00000069/sig00000282 ;
wire \blk00000069/sig00000281 ;
wire \blk00000069/sig00000280 ;
wire \blk00000069/sig0000027f ;
wire \blk00000069/sig0000027e ;
wire \blk00000069/sig0000027d ;
wire \blk00000069/sig0000027c ;
wire \blk00000069/sig0000027b ;
wire \blk00000069/sig0000027a ;
wire \blk00000069/sig00000279 ;
wire \blk00000069/sig00000278 ;
wire \blk00000069/sig00000277 ;
wire \blk00000069/sig00000276 ;
wire \blk00000069/sig00000275 ;
wire \blk00000069/sig00000274 ;
wire \blk00000069/sig00000273 ;
wire \blk00000069/sig00000272 ;
wire \blk00000069/sig00000271 ;
wire \blk00000069/sig00000270 ;
wire \blk00000069/sig0000026f ;
wire \blk00000069/sig0000026e ;
wire \blk00000069/sig0000026d ;
wire \blk00000069/sig0000026c ;
wire \blk00000069/sig0000026b ;
wire \blk00000069/sig0000026a ;
wire \blk00000069/sig00000269 ;
wire \blk00000069/sig00000268 ;
wire \blk00000069/sig00000267 ;
wire \blk00000069/sig00000266 ;
wire \blk00000069/sig00000265 ;
wire \blk00000069/sig00000264 ;
wire \blk00000069/sig00000263 ;
wire \blk00000069/sig00000262 ;
wire \blk00000069/sig00000261 ;
wire \blk00000069/sig00000260 ;
wire \blk00000069/sig0000025f ;
wire \blk00000069/sig0000025e ;
wire \blk00000069/sig0000025d ;
wire \blk00000069/sig0000025c ;
wire \blk00000069/sig0000025b ;
wire \blk00000069/sig0000025a ;
wire \blk00000069/sig00000259 ;
wire \blk00000069/sig00000258 ;
wire \blk00000069/sig00000257 ;
wire \blk00000069/sig00000256 ;
wire \blk00000069/sig00000255 ;
wire \blk00000069/sig00000254 ;
wire \blk00000069/sig00000253 ;
wire \blk00000069/sig00000252 ;
wire \blk00000069/sig00000251 ;
wire \blk000000fa/sig000003a0 ;
wire \blk000000fa/sig0000039f ;
wire \blk000000fa/sig0000039e ;
wire \blk000000fa/sig0000039d ;
wire \blk000000fa/sig0000039c ;
wire \blk000000fa/sig0000039b ;
wire \blk000000fa/sig0000039a ;
wire \blk000000fa/sig00000399 ;
wire \blk000000fa/sig00000398 ;
wire \blk000000fa/sig00000397 ;
wire \blk000000fa/sig00000396 ;
wire \blk000000fa/sig00000395 ;
wire \blk000000fa/sig00000394 ;
wire \blk000000fa/sig00000393 ;
wire \blk000000fa/sig00000392 ;
wire \blk000000fa/sig00000391 ;
wire \blk000000fa/sig00000390 ;
wire \blk000000fa/sig0000038f ;
wire \blk000000fa/sig0000038e ;
wire \blk000000fa/sig0000038d ;
wire \blk000000fa/sig0000038c ;
wire \blk000000fa/sig0000038b ;
wire \blk000000fa/sig0000038a ;
wire \blk000000fa/sig00000389 ;
wire \blk000000fa/sig00000388 ;
wire \blk000000fa/sig00000387 ;
wire \blk000000fa/sig00000386 ;
wire \blk000000fa/sig00000385 ;
wire \blk000000fa/sig00000384 ;
wire \blk000000fa/sig00000383 ;
wire \blk000000fa/sig00000382 ;
wire \blk000000fa/sig00000381 ;
wire \blk000000fa/sig00000380 ;
wire \blk000000fa/sig0000037f ;
wire \blk000000fa/sig0000037e ;
wire \blk000000fa/sig0000037d ;
wire \blk000000fa/sig0000037c ;
wire \blk000000fa/sig0000037b ;
wire \blk000000fa/sig0000037a ;
wire \blk000000fa/sig00000379 ;
wire \blk000000fa/sig00000378 ;
wire \blk000000fa/sig00000377 ;
wire \blk000000fa/sig00000376 ;
wire \blk000000fa/sig00000375 ;
wire \blk000000fa/sig00000374 ;
wire \blk000000fa/sig00000373 ;
wire \blk000000fa/sig00000372 ;
wire \blk000000fa/sig00000371 ;
wire \blk000000fa/sig00000370 ;
wire \blk000000fa/sig0000036f ;
wire \blk000000fa/sig0000036e ;
wire \blk000000fa/sig0000036d ;
wire \blk000000fa/sig0000036c ;
wire \blk000000fa/sig0000036b ;
wire \blk000000fa/sig0000036a ;
wire \blk000000fa/sig00000369 ;
wire \blk000000fa/sig00000368 ;
wire \blk000000fa/sig00000367 ;
wire \blk000000fa/sig00000366 ;
wire \blk000000fa/sig00000365 ;
wire \blk000000fa/sig00000364 ;
wire \blk000000fa/sig00000363 ;
wire \blk000000fa/sig00000362 ;
wire \blk000000fa/sig00000361 ;
wire \blk000000fa/sig00000360 ;
wire \blk000000fa/sig0000035f ;
wire \blk000000fa/sig0000035e ;
wire \blk000000fa/sig0000035d ;
wire \blk000000fa/sig0000035c ;
wire \blk000000fa/sig0000035b ;
wire \blk000000fa/sig0000035a ;
wire \blk000000fa/sig00000359 ;
wire \blk000000fa/sig00000358 ;
wire \blk000000fa/sig00000357 ;
wire \blk000000fa/sig00000356 ;
wire \blk000000fa/sig00000355 ;
wire \blk000000fa/sig00000354 ;
wire \blk000000fa/sig00000353 ;
wire \blk000000fa/sig00000352 ;
wire \blk000000fa/sig00000351 ;
wire \blk000000fa/sig00000350 ;
wire \blk000000fa/sig0000034f ;
wire \blk000000fa/sig0000034e ;
wire \blk000000fa/sig0000034d ;
wire \blk000000fa/sig0000034c ;
wire \blk000000fa/sig0000034b ;
wire \blk000000fa/sig0000034a ;
wire \blk000000fa/sig00000349 ;
wire \blk000000fa/sig00000348 ;
wire \blk000000fa/sig00000347 ;
wire \blk000000fa/sig00000346 ;
wire \blk000000fa/sig00000345 ;
wire \blk000000fa/sig00000344 ;
wire \blk000000fa/sig00000343 ;
wire \blk000000fa/sig00000342 ;
wire \blk0000018b/sig000003cf ;
wire \blk0000018b/sig000003ce ;
wire \blk0000018b/sig000003cd ;
wire \blk0000018b/sig000003cc ;
wire \blk0000018b/sig000003cb ;
wire \blk0000018b/sig000003ca ;
wire \blk0000018b/sig000003c9 ;
wire \blk0000018b/sig000003c8 ;
wire \blk0000018b/sig000003c7 ;
wire \blk0000018b/sig000003c6 ;
wire \blk0000018b/sig000003c5 ;
wire \blk0000018b/sig000003c4 ;
wire \blk0000018b/sig000003c3 ;
wire \blk0000018b/sig000003c2 ;
wire \blk0000018b/sig000003c1 ;
wire \blk0000018b/sig000003b6 ;
wire \blk0000018b/sig000003b5 ;
wire \blk0000018b/sig000003b4 ;
wire \blk0000018b/sig000003b3 ;
wire \blk0000018b/sig000003b2 ;
wire \blk0000018b/sig000003b1 ;
wire \blk0000018b/sig000003b0 ;
wire \blk0000018b/sig000003af ;
wire \blk0000018b/sig000003ae ;
wire \blk0000018b/sig000003ad ;
wire \blk0000018b/sig000003ac ;
wire \blk0000018b/sig000003ab ;
wire \blk0000018b/sig000003aa ;
wire \blk0000018b/sig000003a9 ;
wire \blk0000018b/sig000003a8 ;
wire \blk0000018b/sig000003a7 ;
wire \blk0000018b/sig000003a6 ;
wire \blk0000018b/sig000003a5 ;
wire \blk0000018b/sig000003a4 ;
wire \blk0000018b/sig000003a3 ;
wire NLW_blk000002a3_CASCADEINA_UNCONNECTED;
wire NLW_blk000002a3_CASCADEINB_UNCONNECTED;
wire NLW_blk000002a3_CASCADEOUTA_UNCONNECTED;
wire NLW_blk000002a3_CASCADEOUTB_UNCONNECTED;
wire NLW_blk000002a3_DBITERR_UNCONNECTED;
wire NLW_blk000002a3_INJECTDBITERR_UNCONNECTED;
wire NLW_blk000002a3_INJECTSBITERR_UNCONNECTED;
wire NLW_blk000002a3_SBITERR_UNCONNECTED;
wire \NLW_blk000002a3_DIADI<31>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<30>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<29>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<28>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<27>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<26>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<25>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<24>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<23>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<22>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<21>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<20>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<19>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<18>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<17>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<16>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<15>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<14>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<13>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<12>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<11>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<10>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<9>_UNCONNECTED ;
wire \NLW_blk000002a3_DIADI<8>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<31>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<30>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<29>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<28>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<27>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<26>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<25>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<24>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<23>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<22>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<21>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<20>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<19>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<18>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<17>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<16>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<15>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<14>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<13>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<12>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<11>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<10>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<9>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<8>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<7>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<6>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<5>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<4>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<3>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<2>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<1>_UNCONNECTED ;
wire \NLW_blk000002a3_DIBDI<0>_UNCONNECTED ;
wire \NLW_blk000002a3_DIPADIP<3>_UNCONNECTED ;
wire \NLW_blk000002a3_DIPADIP<2>_UNCONNECTED ;
wire \NLW_blk000002a3_DIPADIP<1>_UNCONNECTED ;
wire \NLW_blk000002a3_DIPBDIP<3>_UNCONNECTED ;
wire \NLW_blk000002a3_DIPBDIP<2>_UNCONNECTED ;
wire \NLW_blk000002a3_DIPBDIP<1>_UNCONNECTED ;
wire \NLW_blk000002a3_DIPBDIP<0>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<31>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<30>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<29>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<28>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<27>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<26>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<25>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<24>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<23>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<22>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<21>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<20>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<19>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<18>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<17>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<16>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<15>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<14>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<13>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<12>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<11>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<10>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<9>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<8>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<7>_UNCONNECTED ;
wire \NLW_blk000002a3_DOADO<6>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<31>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<30>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<29>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<28>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<27>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<26>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<25>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<24>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<23>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<22>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<21>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<20>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<19>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<18>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<17>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<16>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<15>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<14>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<13>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<12>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<11>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<10>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<9>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<8>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<7>_UNCONNECTED ;
wire \NLW_blk000002a3_DOBDO<6>_UNCONNECTED ;
wire \NLW_blk000002a3_DOPADOP<3>_UNCONNECTED ;
wire \NLW_blk000002a3_DOPADOP<2>_UNCONNECTED ;
wire \NLW_blk000002a3_DOPADOP<1>_UNCONNECTED ;
wire \NLW_blk000002a3_DOPADOP<0>_UNCONNECTED ;
wire \NLW_blk000002a3_DOPBDOP<3>_UNCONNECTED ;
wire \NLW_blk000002a3_DOPBDOP<2>_UNCONNECTED ;
wire \NLW_blk000002a3_DOPBDOP<1>_UNCONNECTED ;
wire \NLW_blk000002a3_DOPBDOP<0>_UNCONNECTED ;
wire \NLW_blk000002a3_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_blk000002a3_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_blk000002a3_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_blk000002a3_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_blk000002a3_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_blk000002a3_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_blk000002a3_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_blk000002a3_ECCPARITY<0>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<8>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<7>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<6>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<5>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<4>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<3>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<2>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<1>_UNCONNECTED ;
wire \NLW_blk000002a3_RDADDRECC<0>_UNCONNECTED ;
wire NLW_blk000002a4_CASCADEINA_UNCONNECTED;
wire NLW_blk000002a4_CASCADEINB_UNCONNECTED;
wire NLW_blk000002a4_CASCADEOUTA_UNCONNECTED;
wire NLW_blk000002a4_CASCADEOUTB_UNCONNECTED;
wire NLW_blk000002a4_DBITERR_UNCONNECTED;
wire NLW_blk000002a4_INJECTDBITERR_UNCONNECTED;
wire NLW_blk000002a4_INJECTSBITERR_UNCONNECTED;
wire NLW_blk000002a4_SBITERR_UNCONNECTED;
wire \NLW_blk000002a4_DIADI<31>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<30>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<29>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<28>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<27>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<26>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<25>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<24>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<23>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<22>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<21>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<20>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<19>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<18>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<17>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<16>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<15>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<14>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<13>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<12>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<11>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<10>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<9>_UNCONNECTED ;
wire \NLW_blk000002a4_DIADI<8>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<31>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<30>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<29>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<28>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<27>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<26>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<25>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<24>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<23>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<22>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<21>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<20>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<19>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<18>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<17>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<16>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<15>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<14>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<13>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<12>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<11>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<10>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<9>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<8>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<7>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<6>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<5>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<4>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<3>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<2>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<1>_UNCONNECTED ;
wire \NLW_blk000002a4_DIBDI<0>_UNCONNECTED ;
wire \NLW_blk000002a4_DIPADIP<3>_UNCONNECTED ;
wire \NLW_blk000002a4_DIPADIP<2>_UNCONNECTED ;
wire \NLW_blk000002a4_DIPADIP<1>_UNCONNECTED ;
wire \NLW_blk000002a4_DIPBDIP<3>_UNCONNECTED ;
wire \NLW_blk000002a4_DIPBDIP<2>_UNCONNECTED ;
wire \NLW_blk000002a4_DIPBDIP<1>_UNCONNECTED ;
wire \NLW_blk000002a4_DIPBDIP<0>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<31>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<30>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<29>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<28>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<27>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<26>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<25>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<24>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<23>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<22>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<21>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<20>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<19>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<18>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<17>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<16>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<15>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<14>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<13>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<12>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<11>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<10>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<9>_UNCONNECTED ;
wire \NLW_blk000002a4_DOADO<8>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<31>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<30>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<29>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<28>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<27>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<26>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<25>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<24>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<23>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<22>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<21>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<20>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<19>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<18>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<17>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<16>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<15>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<14>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<13>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<12>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<11>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<10>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<9>_UNCONNECTED ;
wire \NLW_blk000002a4_DOBDO<8>_UNCONNECTED ;
wire \NLW_blk000002a4_DOPADOP<3>_UNCONNECTED ;
wire \NLW_blk000002a4_DOPADOP<2>_UNCONNECTED ;
wire \NLW_blk000002a4_DOPADOP<1>_UNCONNECTED ;
wire \NLW_blk000002a4_DOPBDOP<3>_UNCONNECTED ;
wire \NLW_blk000002a4_DOPBDOP<2>_UNCONNECTED ;
wire \NLW_blk000002a4_DOPBDOP<1>_UNCONNECTED ;
wire \NLW_blk000002a4_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_blk000002a4_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_blk000002a4_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_blk000002a4_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_blk000002a4_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_blk000002a4_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_blk000002a4_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_blk000002a4_ECCPARITY<0>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<8>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<7>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<6>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<5>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<4>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<3>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<2>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<1>_UNCONNECTED ;
wire \NLW_blk000002a4_RDADDRECC<0>_UNCONNECTED ;
wire NLW_blk000002a5_Q15_UNCONNECTED;
wire NLW_blk000002a7_Q15_UNCONNECTED;
wire \NLW_blk0000018b/blk000001b7_Q15_UNCONNECTED ;
wire \NLW_blk0000018b/blk000001b5_Q15_UNCONNECTED ;
wire \NLW_blk0000018b/blk000001b3_Q15_UNCONNECTED ;
wire [7 : 0] \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q ;
wire [7 : 0] \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q ;
wire [7 : 0] \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q ;
wire [7 : 0] \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q ;
assign
m_axis_data_tdata[31] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7],
m_axis_data_tdata[30] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6],
m_axis_data_tdata[29] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5],
m_axis_data_tdata[28] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4],
m_axis_data_tdata[27] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3],
m_axis_data_tdata[26] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2],
m_axis_data_tdata[25] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1],
m_axis_data_tdata[24] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0],
m_axis_data_tdata[23] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7],
m_axis_data_tdata[22] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6],
m_axis_data_tdata[21] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5],
m_axis_data_tdata[20] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4],
m_axis_data_tdata[19] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3],
m_axis_data_tdata[18] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2],
m_axis_data_tdata[17] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1],
m_axis_data_tdata[16] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0],
m_axis_data_tdata[15] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [7],
m_axis_data_tdata[14] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [6],
m_axis_data_tdata[13] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [5],
m_axis_data_tdata[12] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [4],
m_axis_data_tdata[11] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [3],
m_axis_data_tdata[10] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [2],
m_axis_data_tdata[9] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [1],
m_axis_data_tdata[8] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [0],
m_axis_data_tdata[7] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [7],
m_axis_data_tdata[6] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [6],
m_axis_data_tdata[5] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [5],
m_axis_data_tdata[4] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [4],
m_axis_data_tdata[3] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [3],
m_axis_data_tdata[2] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [2],
m_axis_data_tdata[1] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [1],
m_axis_data_tdata[0] = \U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [0],
m_axis_data_tvalid = \U0/i_synth/i_dds/i_rdy.i_single_channel.i_non_trivial_lat.i_rdy/opt_has_pipe.first_q ;
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FDE #(
.INIT ( 1'b1 ))
blk00000003 (
.C(aclk),
.CE(sig00000007),
.D(sig00000004),
.Q(sig0000006c)
);
FDE #(
.INIT ( 1'b1 ))
blk00000004 (
.C(aclk),
.CE(sig00000007),
.D(sig00000005),
.Q(sig0000006b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000005 (
.C(aclk),
.CE(sig00000007),
.D(sig00000006),
.Q(sig00000003)
);
FDE #(
.INIT ( 1'b0 ))
blk00000006 (
.C(aclk),
.CE(sig00000001),
.D(sig00000039),
.Q(\U0/i_synth/i_dds/i_rdy.i_single_channel.i_non_trivial_lat.i_rdy/opt_has_pipe.first_q )
);
FDE #(
.INIT ( 1'b0 ))
blk00000007 (
.C(aclk),
.CE(sig00000001),
.D(sig00000008),
.Q(sig000000b5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000008 (
.C(aclk),
.CE(sig00000001),
.D(sig00000009),
.Q(sig000000b4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000009 (
.C(aclk),
.CE(sig00000001),
.D(sig0000000a),
.Q(sig000000b3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000a (
.C(aclk),
.CE(sig00000001),
.D(sig0000000b),
.Q(sig000000b2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000b (
.C(aclk),
.CE(sig00000001),
.D(sig0000000c),
.Q(sig000000b1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000c (
.C(aclk),
.CE(sig00000001),
.D(sig0000000d),
.Q(sig000000b0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000d (
.C(aclk),
.CE(sig00000001),
.D(sig0000000e),
.Q(sig000000af)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000e (
.C(aclk),
.CE(sig00000001),
.D(sig0000000f),
.Q(sig000000ae)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000f (
.C(aclk),
.CE(sig00000001),
.D(sig00000010),
.Q(sig000000ad)
);
FDE #(
.INIT ( 1'b0 ))
blk00000010 (
.C(aclk),
.CE(sig00000001),
.D(sig00000011),
.Q(sig000000ac)
);
FDE #(
.INIT ( 1'b0 ))
blk00000011 (
.C(aclk),
.CE(sig00000001),
.D(sig00000012),
.Q(sig000000ab)
);
FDE #(
.INIT ( 1'b0 ))
blk00000012 (
.C(aclk),
.CE(sig00000001),
.D(sig00000013),
.Q(sig000000aa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000013 (
.C(aclk),
.CE(sig00000001),
.D(sig00000014),
.Q(sig000000a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000014 (
.C(aclk),
.CE(sig00000001),
.D(sig00000015),
.Q(sig000000a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000015 (
.C(aclk),
.CE(sig00000001),
.D(sig00000016),
.Q(sig000000a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000016 (
.C(aclk),
.CE(sig00000001),
.D(sig00000017),
.Q(sig000000a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000017 (
.C(aclk),
.CE(sig00000001),
.D(sig00000018),
.Q(sig000000a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000018 (
.C(aclk),
.CE(sig00000001),
.D(sig00000019),
.Q(sig000000a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000019 (
.C(aclk),
.CE(sig00000001),
.D(sig0000001a),
.Q(sig000000a3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001a (
.C(aclk),
.CE(sig00000001),
.D(sig0000001b),
.Q(sig000000a2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001b (
.C(aclk),
.CE(sig00000001),
.D(sig0000001c),
.Q(sig000000a1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001c (
.C(aclk),
.CE(sig00000001),
.D(sig0000001d),
.Q(sig000000a0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001d (
.C(aclk),
.CE(sig00000001),
.D(sig0000001e),
.Q(sig0000009f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001e (
.C(aclk),
.CE(sig00000001),
.D(sig0000001f),
.Q(sig0000009e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001f (
.C(aclk),
.CE(sig00000001),
.D(sig00000020),
.Q(sig0000009d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000020 (
.C(aclk),
.CE(sig00000001),
.D(sig00000021),
.Q(sig0000009c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000021 (
.C(aclk),
.CE(sig00000001),
.D(sig00000022),
.Q(sig0000009b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000022 (
.C(aclk),
.CE(sig00000001),
.D(sig00000023),
.Q(sig0000009a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000023 (
.C(aclk),
.CE(sig00000001),
.D(sig00000024),
.Q(sig00000099)
);
FDE #(
.INIT ( 1'b0 ))
blk00000024 (
.C(aclk),
.CE(sig00000001),
.D(sig00000025),
.Q(sig00000098)
);
FDE #(
.INIT ( 1'b0 ))
blk00000025 (
.C(aclk),
.CE(sig00000001),
.D(sig00000026),
.Q(sig00000097)
);
FDE #(
.INIT ( 1'b0 ))
blk00000026 (
.C(aclk),
.CE(sig00000001),
.D(sig00000027),
.Q(sig00000096)
);
FDE #(
.INIT ( 1'b0 ))
blk00000027 (
.C(aclk),
.CE(sig00000001),
.D(sig00000028),
.Q(sig00000095)
);
FDE #(
.INIT ( 1'b0 ))
blk00000028 (
.C(aclk),
.CE(sig00000001),
.D(sig00000029),
.Q(sig00000094)
);
FDE #(
.INIT ( 1'b0 ))
blk00000029 (
.C(aclk),
.CE(sig00000001),
.D(sig0000002a),
.Q(sig00000093)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002a (
.C(aclk),
.CE(sig00000001),
.D(sig0000002b),
.Q(sig00000092)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002b (
.C(aclk),
.CE(sig00000001),
.D(sig0000002c),
.Q(sig00000091)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002c (
.C(aclk),
.CE(sig00000001),
.D(sig0000002d),
.Q(sig00000090)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002d (
.C(aclk),
.CE(sig00000001),
.D(sig0000002e),
.Q(sig0000008f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002e (
.C(aclk),
.CE(sig00000001),
.D(sig0000002f),
.Q(sig0000008e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002f (
.C(aclk),
.CE(sig00000001),
.D(sig00000030),
.Q(sig0000008d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000030 (
.C(aclk),
.CE(sig00000001),
.D(sig00000031),
.Q(sig0000008c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000031 (
.C(aclk),
.CE(sig00000001),
.D(sig00000032),
.Q(sig0000008b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000032 (
.C(aclk),
.CE(sig00000001),
.D(sig00000033),
.Q(sig0000008a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000033 (
.C(aclk),
.CE(sig00000001),
.D(sig00000034),
.Q(sig00000089)
);
FDE #(
.INIT ( 1'b0 ))
blk00000034 (
.C(aclk),
.CE(sig00000001),
.D(sig00000035),
.Q(sig00000088)
);
FDE #(
.INIT ( 1'b0 ))
blk00000035 (
.C(aclk),
.CE(sig00000001),
.D(sig00000036),
.Q(sig00000087)
);
FDE #(
.INIT ( 1'b0 ))
blk00000036 (
.C(aclk),
.CE(sig00000001),
.D(sig00000037),
.Q(sig00000086)
);
FDE #(
.INIT ( 1'b0 ))
blk00000037 (
.C(aclk),
.CE(sig00000001),
.D(sig00000038),
.Q(sig00000085)
);
FDE #(
.INIT ( 1'b0 ))
blk00000038 (
.C(aclk),
.CE(sig00000001),
.D(sig0000006a),
.Q(sig000000d8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000039 (
.C(aclk),
.CE(sig00000001),
.D(sig00000069),
.Q(sig0000007a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003a (
.C(aclk),
.CE(sig00000001),
.D(sig00000068),
.Q(sig00000079)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003b (
.C(aclk),
.CE(sig00000001),
.D(sig00000067),
.Q(sig00000078)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003c (
.C(aclk),
.CE(sig00000001),
.D(sig00000066),
.Q(sig00000077)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003d (
.C(aclk),
.CE(sig00000001),
.D(sig00000065),
.Q(sig00000076)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003e (
.C(aclk),
.CE(sig00000001),
.D(sig00000064),
.Q(sig00000075)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003f (
.C(aclk),
.CE(sig00000001),
.D(sig00000063),
.Q(sig00000074)
);
FDE #(
.INIT ( 1'b0 ))
blk00000040 (
.C(aclk),
.CE(sig00000001),
.D(sig00000062),
.Q(sig00000073)
);
FDE #(
.INIT ( 1'b0 ))
blk00000041 (
.C(aclk),
.CE(sig00000001),
.D(sig00000061),
.Q(sig00000072)
);
FDE #(
.INIT ( 1'b0 ))
blk00000042 (
.C(aclk),
.CE(sig00000001),
.D(sig00000060),
.Q(sig00000071)
);
FDE #(
.INIT ( 1'b0 ))
blk00000043 (
.C(aclk),
.CE(sig00000001),
.D(sig0000005f),
.Q(sig00000070)
);
FDE #(
.INIT ( 1'b0 ))
blk00000044 (
.C(aclk),
.CE(sig00000001),
.D(sig0000005e),
.Q(sig0000006f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000045 (
.C(aclk),
.CE(sig00000001),
.D(sig0000005d),
.Q(sig0000006e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000046 (
.C(aclk),
.CE(sig00000001),
.D(sig0000005c),
.Q(sig0000006d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000047 (
.C(aclk),
.CE(sig00000001),
.D(sig0000005b),
.Q(sig000000d7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000048 (
.C(aclk),
.CE(sig00000001),
.D(sig0000005a),
.Q(sig000000d6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000049 (
.C(aclk),
.CE(sig00000001),
.D(sig00000059),
.Q(sig000000d5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004a (
.C(aclk),
.CE(sig00000001),
.D(sig00000058),
.Q(sig000000d4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004b (
.C(aclk),
.CE(sig00000001),
.D(sig00000057),
.Q(sig000000d3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004c (
.C(aclk),
.CE(sig00000001),
.D(sig00000056),
.Q(sig000000d2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004d (
.C(aclk),
.CE(sig00000001),
.D(sig00000055),
.Q(sig000000d1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004e (
.C(aclk),
.CE(sig00000001),
.D(sig00000054),
.Q(sig000000d0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004f (
.C(aclk),
.CE(sig00000001),
.D(sig00000053),
.Q(sig000000cf)
);
FDE #(
.INIT ( 1'b0 ))
blk00000050 (
.C(aclk),
.CE(sig00000001),
.D(sig00000052),
.Q(sig000000ce)
);
FDE #(
.INIT ( 1'b0 ))
blk00000051 (
.C(aclk),
.CE(sig00000001),
.D(sig00000051),
.Q(sig000000cd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000052 (
.C(aclk),
.CE(sig00000001),
.D(sig00000050),
.Q(sig000000cc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000053 (
.C(aclk),
.CE(sig00000001),
.D(sig0000004f),
.Q(sig000000cb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000054 (
.C(aclk),
.CE(sig00000001),
.D(sig0000004e),
.Q(sig000000ca)
);
FDE #(
.INIT ( 1'b0 ))
blk00000055 (
.C(aclk),
.CE(sig00000001),
.D(sig0000004d),
.Q(sig000000c9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000056 (
.C(aclk),
.CE(sig00000001),
.D(sig0000004c),
.Q(sig000000c8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000057 (
.C(aclk),
.CE(sig00000001),
.D(sig0000004b),
.Q(sig000000c7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000058 (
.C(aclk),
.CE(sig00000001),
.D(sig0000004a),
.Q(sig000000c6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000059 (
.C(aclk),
.CE(sig00000001),
.D(sig00000049),
.Q(sig000000c5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005a (
.C(aclk),
.CE(sig00000001),
.D(sig00000048),
.Q(sig000000c4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005b (
.C(aclk),
.CE(sig00000001),
.D(sig00000047),
.Q(sig000000c3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005c (
.C(aclk),
.CE(sig00000001),
.D(sig00000046),
.Q(sig000000c2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005d (
.C(aclk),
.CE(sig00000001),
.D(sig00000045),
.Q(sig000000c1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005e (
.C(aclk),
.CE(sig00000001),
.D(sig00000044),
.Q(sig000000c0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005f (
.C(aclk),
.CE(sig00000001),
.D(sig00000043),
.Q(sig000000bf)
);
FDE #(
.INIT ( 1'b0 ))
blk00000060 (
.C(aclk),
.CE(sig00000001),
.D(sig00000042),
.Q(sig000000be)
);
FDE #(
.INIT ( 1'b0 ))
blk00000061 (
.C(aclk),
.CE(sig00000001),
.D(sig00000041),
.Q(sig000000bd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000062 (
.C(aclk),
.CE(sig00000001),
.D(sig00000040),
.Q(sig000000bc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000063 (
.C(aclk),
.CE(sig00000001),
.D(sig0000003f),
.Q(sig000000bb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000064 (
.C(aclk),
.CE(sig00000001),
.D(sig0000003e),
.Q(sig000000ba)
);
FDE #(
.INIT ( 1'b0 ))
blk00000065 (
.C(aclk),
.CE(sig00000001),
.D(sig0000003d),
.Q(sig000000b9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000066 (
.C(aclk),
.CE(sig00000001),
.D(sig0000003c),
.Q(sig000000b8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000067 (
.C(aclk),
.CE(sig00000001),
.D(sig0000003b),
.Q(sig000000b7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000068 (
.C(aclk),
.CE(sig00000001),
.D(sig0000003a),
.Q(sig000000b6)
);
XORCY blk000001b9 (
.CI(sig000000ec),
.LI(sig0000010c),
.O(sig00000104)
);
MUXCY blk000001ba (
.CI(sig000000ec),
.DI(sig00000002),
.S(sig0000010c),
.O(sig000000eb)
);
XORCY blk000001bb (
.CI(sig000000ed),
.LI(sig0000010b),
.O(sig00000103)
);
MUXCY blk000001bc (
.CI(sig000000ed),
.DI(sig00000002),
.S(sig0000010b),
.O(sig000000ec)
);
XORCY blk000001bd (
.CI(sig000000ee),
.LI(sig0000010a),
.O(sig00000102)
);
MUXCY blk000001be (
.CI(sig000000ee),
.DI(sig00000002),
.S(sig0000010a),
.O(sig000000ed)
);
XORCY blk000001bf (
.CI(sig000000ef),
.LI(sig00000109),
.O(sig00000101)
);
MUXCY blk000001c0 (
.CI(sig000000ef),
.DI(sig00000002),
.S(sig00000109),
.O(sig000000ee)
);
XORCY blk000001c1 (
.CI(sig000000f0),
.LI(sig00000108),
.O(sig00000100)
);
MUXCY blk000001c2 (
.CI(sig000000f0),
.DI(sig00000002),
.S(sig00000108),
.O(sig000000ef)
);
XORCY blk000001c3 (
.CI(sig000000f1),
.LI(sig00000107),
.O(sig000000ff)
);
MUXCY blk000001c4 (
.CI(sig000000f1),
.DI(sig00000002),
.S(sig00000107),
.O(sig000000f0)
);
XORCY blk000001c5 (
.CI(sig000000f2),
.LI(sig00000106),
.O(sig000000fe)
);
MUXCY blk000001c6 (
.CI(sig000000f2),
.DI(sig00000002),
.S(sig00000106),
.O(sig000000f1)
);
XORCY blk000001c7 (
.CI(sig000000f3),
.LI(sig00000105),
.O(sig000000fd)
);
MUXCY blk000001c8 (
.CI(sig000000f3),
.DI(sig00000002),
.S(sig00000105),
.O(sig000000f2)
);
MUXCY blk000001c9 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig000000f4),
.O(sig000000f3)
);
XORCY blk000001ca (
.CI(sig000000f6),
.LI(sig00000123),
.O(sig0000011c)
);
MUXCY blk000001cb (
.CI(sig000000f6),
.DI(sig00000002),
.S(sig00000123),
.O(sig000000f5)
);
XORCY blk000001cc (
.CI(sig000000f7),
.LI(sig00000122),
.O(sig0000011b)
);
MUXCY blk000001cd (
.CI(sig000000f7),
.DI(sig00000002),
.S(sig00000122),
.O(sig000000f6)
);
XORCY blk000001ce (
.CI(sig000000f8),
.LI(sig00000121),
.O(sig0000011a)
);
MUXCY blk000001cf (
.CI(sig000000f8),
.DI(sig00000002),
.S(sig00000121),
.O(sig000000f7)
);
XORCY blk000001d0 (
.CI(sig000000f9),
.LI(sig00000120),
.O(sig00000119)
);
MUXCY blk000001d1 (
.CI(sig000000f9),
.DI(sig00000002),
.S(sig00000120),
.O(sig000000f8)
);
XORCY blk000001d2 (
.CI(sig000000fa),
.LI(sig0000011f),
.O(sig00000118)
);
MUXCY blk000001d3 (
.CI(sig000000fa),
.DI(sig00000002),
.S(sig0000011f),
.O(sig000000f9)
);
XORCY blk000001d4 (
.CI(sig000000fb),
.LI(sig0000011e),
.O(sig00000117)
);
MUXCY blk000001d5 (
.CI(sig000000fb),
.DI(sig00000002),
.S(sig0000011e),
.O(sig000000fa)
);
XORCY blk000001d6 (
.CI(sig000000fc),
.LI(sig0000011d),
.O(sig00000116)
);
MUXCY blk000001d7 (
.CI(sig000000fc),
.DI(sig00000002),
.S(sig0000011d),
.O(sig000000fb)
);
XORCY blk000001d8 (
.CI(sig00000002),
.LI(sig000001bd),
.O(sig00000115)
);
MUXCY blk000001d9 (
.CI(sig00000002),
.DI(sig0000012b),
.S(sig000001bd),
.O(sig000000fc)
);
FDE #(
.INIT ( 1'b0 ))
blk000001da (
.C(aclk),
.CE(sig00000001),
.D(sig00000151),
.Q(sig0000015d)
);
FDE #(
.INIT ( 1'b0 ))
blk000001db (
.C(aclk),
.CE(sig00000001),
.D(sig00000150),
.Q(sig0000015c)
);
FDE #(
.INIT ( 1'b0 ))
blk000001dc (
.C(aclk),
.CE(sig00000001),
.D(sig0000014f),
.Q(sig0000015b)
);
FDE #(
.INIT ( 1'b0 ))
blk000001dd (
.C(aclk),
.CE(sig00000001),
.D(sig0000014e),
.Q(sig0000015a)
);
FDE #(
.INIT ( 1'b0 ))
blk000001de (
.C(aclk),
.CE(sig00000001),
.D(sig0000014d),
.Q(sig00000159)
);
FDE #(
.INIT ( 1'b0 ))
blk000001df (
.C(aclk),
.CE(sig00000001),
.D(sig0000014c),
.Q(sig00000158)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e0 (
.C(aclk),
.CE(sig00000001),
.D(sig0000014b),
.Q(sig00000157)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e1 (
.C(aclk),
.CE(sig00000001),
.D(sig0000014a),
.Q(sig00000156)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e2 (
.C(aclk),
.CE(sig00000001),
.D(sig00000149),
.Q(sig00000155)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e3 (
.C(aclk),
.CE(sig00000001),
.D(sig00000148),
.Q(sig00000154)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e4 (
.C(aclk),
.CE(sig00000001),
.D(sig00000147),
.Q(sig00000153)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e5 (
.C(aclk),
.CE(sig00000001),
.D(sig00000146),
.Q(sig00000152)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e6 (
.C(aclk),
.CE(sig00000001),
.D(sig00000145),
.Q(sig00000187)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e7 (
.C(aclk),
.CE(sig00000001),
.D(sig00000144),
.Q(sig00000186)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e8 (
.C(aclk),
.CE(sig00000001),
.D(sig00000143),
.Q(sig00000185)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e9 (
.C(aclk),
.CE(sig00000001),
.D(sig00000142),
.Q(sig00000184)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ea (
.C(aclk),
.CE(sig00000001),
.D(sig00000141),
.Q(sig00000183)
);
FDE #(
.INIT ( 1'b0 ))
blk000001eb (
.C(aclk),
.CE(sig00000001),
.D(sig00000140),
.Q(sig00000182)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ec (
.C(aclk),
.CE(sig00000001),
.D(sig0000013f),
.Q(sig00000181)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ed (
.C(aclk),
.CE(sig00000001),
.D(sig0000013e),
.Q(sig00000180)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ee (
.C(aclk),
.CE(sig00000001),
.D(sig0000013d),
.Q(sig0000017f)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ef (
.C(aclk),
.CE(sig00000001),
.D(sig0000013c),
.Q(sig0000017e)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f0 (
.C(aclk),
.CE(sig00000001),
.D(sig0000013b),
.Q(sig0000017d)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f1 (
.C(aclk),
.CE(sig00000001),
.D(sig0000013a),
.Q(sig0000017c)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f2 (
.C(aclk),
.CE(sig00000001),
.D(sig0000007a),
.Q(sig000001bc)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f3 (
.C(aclk),
.CE(sig00000001),
.D(sig00000079),
.Q(sig000001bb)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f4 (
.C(aclk),
.CE(sig00000001),
.D(sig0000016c),
.Q(sig000001aa)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f5 (
.C(aclk),
.CE(sig00000001),
.D(sig0000016b),
.Q(sig000001a9)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f6 (
.C(aclk),
.CE(sig00000001),
.D(sig0000016a),
.Q(sig000001a8)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f7 (
.C(aclk),
.CE(sig00000001),
.D(sig00000169),
.Q(sig000001a7)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f8 (
.C(aclk),
.CE(sig00000001),
.D(sig00000168),
.Q(sig000001a6)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f9 (
.C(aclk),
.CE(sig00000001),
.D(sig00000167),
.Q(sig000001a5)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fa (
.C(aclk),
.CE(sig00000001),
.D(sig00000166),
.Q(sig000001a4)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fb (
.C(aclk),
.CE(sig00000001),
.D(sig00000165),
.Q(sig000001a3)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fc (
.C(aclk),
.CE(sig00000001),
.D(sig00000164),
.Q(sig000001a2)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fd (
.C(aclk),
.CE(sig00000001),
.D(sig00000163),
.Q(sig000001a1)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fe (
.C(aclk),
.CE(sig00000001),
.D(sig00000162),
.Q(sig000001a0)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ff (
.C(aclk),
.CE(sig00000001),
.D(sig00000161),
.Q(sig0000019f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000200 (
.C(aclk),
.CE(sig00000001),
.D(sig00000160),
.Q(sig0000019e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000201 (
.C(aclk),
.CE(sig00000001),
.D(sig0000015f),
.Q(sig0000019d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000202 (
.C(aclk),
.CE(sig00000001),
.D(sig0000015e),
.Q(sig0000019c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000203 (
.C(aclk),
.CE(sig00000001),
.D(sig0000017b),
.Q(sig000001b9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000204 (
.C(aclk),
.CE(sig00000001),
.D(sig0000017a),
.Q(sig000001b8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000205 (
.C(aclk),
.CE(sig00000001),
.D(sig00000179),
.Q(sig000001b7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000206 (
.C(aclk),
.CE(sig00000001),
.D(sig00000178),
.Q(sig000001b6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000207 (
.C(aclk),
.CE(sig00000001),
.D(sig00000177),
.Q(sig000001b5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000208 (
.C(aclk),
.CE(sig00000001),
.D(sig00000176),
.Q(sig000001b4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000209 (
.C(aclk),
.CE(sig00000001),
.D(sig00000175),
.Q(sig000001b3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020a (
.C(aclk),
.CE(sig00000001),
.D(sig00000174),
.Q(sig000001b2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020b (
.C(aclk),
.CE(sig00000001),
.D(sig00000173),
.Q(sig000001b1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020c (
.C(aclk),
.CE(sig00000001),
.D(sig00000172),
.Q(sig000001b0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020d (
.C(aclk),
.CE(sig00000001),
.D(sig00000171),
.Q(sig000001af)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020e (
.C(aclk),
.CE(sig00000001),
.D(sig00000170),
.Q(sig000001ae)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020f (
.C(aclk),
.CE(sig00000001),
.D(sig0000016f),
.Q(sig000001ad)
);
FDE #(
.INIT ( 1'b0 ))
blk00000210 (
.C(aclk),
.CE(sig00000001),
.D(sig0000016e),
.Q(sig000001ac)
);
FDE #(
.INIT ( 1'b0 ))
blk00000211 (
.C(aclk),
.CE(sig00000001),
.D(sig0000016d),
.Q(sig000001ab)
);
FDE #(
.INIT ( 1'b0 ))
blk00000212 (
.C(aclk),
.CE(sig00000001),
.D(sig0000018f),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [7])
);
FDE #(
.INIT ( 1'b0 ))
blk00000213 (
.C(aclk),
.CE(sig00000001),
.D(sig0000018e),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [6])
);
FDE #(
.INIT ( 1'b0 ))
blk00000214 (
.C(aclk),
.CE(sig00000001),
.D(sig0000018d),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [5])
);
FDE #(
.INIT ( 1'b0 ))
blk00000215 (
.C(aclk),
.CE(sig00000001),
.D(sig0000018c),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [4])
);
FDE #(
.INIT ( 1'b0 ))
blk00000216 (
.C(aclk),
.CE(sig00000001),
.D(sig0000018b),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [3])
);
FDE #(
.INIT ( 1'b0 ))
blk00000217 (
.C(aclk),
.CE(sig00000001),
.D(sig0000018a),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [2])
);
FDE #(
.INIT ( 1'b0 ))
blk00000218 (
.C(aclk),
.CE(sig00000001),
.D(sig00000189),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [1])
);
FDE #(
.INIT ( 1'b0 ))
blk00000219 (
.C(aclk),
.CE(sig00000001),
.D(sig00000188),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q [0])
);
FDE #(
.INIT ( 1'b0 ))
blk0000021a (
.C(aclk),
.CE(sig00000001),
.D(sig00000132),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [7])
);
FDE #(
.INIT ( 1'b0 ))
blk0000021b (
.C(aclk),
.CE(sig00000001),
.D(sig00000131),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [6])
);
FDE #(
.INIT ( 1'b0 ))
blk0000021c (
.C(aclk),
.CE(sig00000001),
.D(sig00000130),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [5])
);
FDE #(
.INIT ( 1'b0 ))
blk0000021d (
.C(aclk),
.CE(sig00000001),
.D(sig0000012f),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [4])
);
FDE #(
.INIT ( 1'b0 ))
blk0000021e (
.C(aclk),
.CE(sig00000001),
.D(sig0000012e),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [3])
);
FDE #(
.INIT ( 1'b0 ))
blk0000021f (
.C(aclk),
.CE(sig00000001),
.D(sig0000012d),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [2])
);
FDE #(
.INIT ( 1'b0 ))
blk00000220 (
.C(aclk),
.CE(sig00000001),
.D(sig0000012c),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [1])
);
FDE #(
.INIT ( 1'b0 ))
blk00000221 (
.C(aclk),
.CE(sig00000001),
.D(sig000000e2),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q [0])
);
FDE #(
.INIT ( 1'b0 ))
blk00000222 (
.C(aclk),
.CE(sig00000001),
.D(sig00000199),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7])
);
FDE #(
.INIT ( 1'b0 ))
blk00000223 (
.C(aclk),
.CE(sig00000001),
.D(sig00000198),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6])
);
FDE #(
.INIT ( 1'b0 ))
blk00000224 (
.C(aclk),
.CE(sig00000001),
.D(sig00000197),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5])
);
FDE #(
.INIT ( 1'b0 ))
blk00000225 (
.C(aclk),
.CE(sig00000001),
.D(sig00000196),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4])
);
FDE #(
.INIT ( 1'b0 ))
blk00000226 (
.C(aclk),
.CE(sig00000001),
.D(sig00000195),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3])
);
FDE #(
.INIT ( 1'b0 ))
blk00000227 (
.C(aclk),
.CE(sig00000001),
.D(sig00000194),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2])
);
FDE #(
.INIT ( 1'b0 ))
blk00000228 (
.C(aclk),
.CE(sig00000001),
.D(sig00000193),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1])
);
FDE #(
.INIT ( 1'b0 ))
blk00000229 (
.C(aclk),
.CE(sig00000001),
.D(sig00000192),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0])
);
FDE #(
.INIT ( 1'b0 ))
blk0000022a (
.C(aclk),
.CE(sig00000001),
.D(sig00000139),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7])
);
FDE #(
.INIT ( 1'b0 ))
blk0000022b (
.C(aclk),
.CE(sig00000001),
.D(sig00000138),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6])
);
FDE #(
.INIT ( 1'b0 ))
blk0000022c (
.C(aclk),
.CE(sig00000001),
.D(sig00000137),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5])
);
FDE #(
.INIT ( 1'b0 ))
blk0000022d (
.C(aclk),
.CE(sig00000001),
.D(sig00000136),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4])
);
FDE #(
.INIT ( 1'b0 ))
blk0000022e (
.C(aclk),
.CE(sig00000001),
.D(sig00000135),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3])
);
FDE #(
.INIT ( 1'b0 ))
blk0000022f (
.C(aclk),
.CE(sig00000001),
.D(sig00000134),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2])
);
FDE #(
.INIT ( 1'b0 ))
blk00000230 (
.C(aclk),
.CE(sig00000001),
.D(sig00000133),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1])
);
FDE #(
.INIT ( 1'b0 ))
blk00000231 (
.C(aclk),
.CE(sig00000001),
.D(sig000000ea),
.Q(\U0/i_synth/i_dds/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0])
);
FDE #(
.INIT ( 1'b0 ))
blk00000232 (
.C(aclk),
.CE(sig00000001),
.D(sig00000114),
.Q(sig000000db)
);
FDE #(
.INIT ( 1'b0 ))
blk00000233 (
.C(aclk),
.CE(sig00000001),
.D(sig00000113),
.Q(sig000000dc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000234 (
.C(aclk),
.CE(sig00000001),
.D(sig00000112),
.Q(sig000000dd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000235 (
.C(aclk),
.CE(sig00000001),
.D(sig00000111),
.Q(sig000000de)
);
FDE #(
.INIT ( 1'b0 ))
blk00000236 (
.C(aclk),
.CE(sig00000001),
.D(sig00000110),
.Q(sig000000df)
);
FDE #(
.INIT ( 1'b0 ))
blk00000237 (
.C(aclk),
.CE(sig00000001),
.D(sig0000010f),
.Q(sig000000e0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000238 (
.C(aclk),
.CE(sig00000001),
.D(sig0000010e),
.Q(sig000000e1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000239 (
.C(aclk),
.CE(sig00000001),
.D(sig0000010d),
.Q(sig00000191)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023a (
.C(aclk),
.CE(sig00000001),
.D(sig0000012b),
.Q(sig000000e3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023b (
.C(aclk),
.CE(sig00000001),
.D(sig0000012a),
.Q(sig000000e4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023c (
.C(aclk),
.CE(sig00000001),
.D(sig00000129),
.Q(sig000000e5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023d (
.C(aclk),
.CE(sig00000001),
.D(sig00000128),
.Q(sig000000e6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023e (
.C(aclk),
.CE(sig00000001),
.D(sig00000127),
.Q(sig000000e7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023f (
.C(aclk),
.CE(sig00000001),
.D(sig00000126),
.Q(sig000000e8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000240 (
.C(aclk),
.CE(sig00000001),
.D(sig00000125),
.Q(sig000000e9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000241 (
.C(aclk),
.CE(sig00000001),
.D(sig00000124),
.Q(sig0000019b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000242 (
.C(aclk),
.CE(sig00000001),
.D(sig000000eb),
.Q(sig00000190)
);
FDE #(
.INIT ( 1'b0 ))
blk00000243 (
.C(aclk),
.CE(sig00000001),
.D(sig00000104),
.Q(sig0000018f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000244 (
.C(aclk),
.CE(sig00000001),
.D(sig00000103),
.Q(sig0000018e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000245 (
.C(aclk),
.CE(sig00000001),
.D(sig00000102),
.Q(sig0000018d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000246 (
.C(aclk),
.CE(sig00000001),
.D(sig00000101),
.Q(sig0000018c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000247 (
.C(aclk),
.CE(sig00000001),
.D(sig00000100),
.Q(sig0000018b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000248 (
.C(aclk),
.CE(sig00000001),
.D(sig000000ff),
.Q(sig0000018a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000249 (
.C(aclk),
.CE(sig00000001),
.D(sig000000fe),
.Q(sig00000189)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024a (
.C(aclk),
.CE(sig00000001),
.D(sig000000fd),
.Q(sig00000188)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024b (
.C(aclk),
.CE(sig00000001),
.D(sig000000f5),
.Q(sig0000019a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024c (
.C(aclk),
.CE(sig00000001),
.D(sig0000011c),
.Q(sig00000199)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024d (
.C(aclk),
.CE(sig00000001),
.D(sig0000011b),
.Q(sig00000198)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024e (
.C(aclk),
.CE(sig00000001),
.D(sig0000011a),
.Q(sig00000197)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024f (
.C(aclk),
.CE(sig00000001),
.D(sig00000119),
.Q(sig00000196)
);
FDE #(
.INIT ( 1'b0 ))
blk00000250 (
.C(aclk),
.CE(sig00000001),
.D(sig00000118),
.Q(sig00000195)
);
FDE #(
.INIT ( 1'b0 ))
blk00000251 (
.C(aclk),
.CE(sig00000001),
.D(sig00000117),
.Q(sig00000194)
);
FDE #(
.INIT ( 1'b0 ))
blk00000252 (
.C(aclk),
.CE(sig00000001),
.D(sig00000116),
.Q(sig00000193)
);
FDE #(
.INIT ( 1'b0 ))
blk00000253 (
.C(aclk),
.CE(sig00000001),
.D(sig00000115),
.Q(sig00000192)
);
LUT3 #(
.INIT ( 8'hA9 ))
blk00000254 (
.I0(sig0000006c),
.I1(sig00000003),
.I2(sig0000006b),
.O(sig00000004)
);
LUT3 #(
.INIT ( 8'h01 ))
blk00000255 (
.I0(sig0000006c),
.I1(sig00000003),
.I2(sig0000006b),
.O(sig00000039)
);
LUT3 #(
.INIT ( 8'hFE ))
blk00000256 (
.I0(sig0000006c),
.I1(sig00000003),
.I2(sig0000006b),
.O(sig00000007)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000257 (
.I0(sig0000006b),
.I1(sig00000003),
.O(sig00000005)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000258 (
.I0(sig000000e5),
.I1(sig000000d9),
.O(sig00000137)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000259 (
.I0(sig000000dd),
.I1(sig000000da),
.O(sig00000130)
);
LUT3 #(
.INIT ( 8'h9A ))
blk0000025a (
.I0(sig000000e4),
.I1(sig000000d9),
.I2(sig000000e5),
.O(sig00000138)
);
LUT3 #(
.INIT ( 8'h9A ))
blk0000025b (
.I0(sig000000dc),
.I1(sig000000da),
.I2(sig000000dd),
.O(sig00000131)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk0000025c (
.I0(sig000000e3),
.I1(sig000000e4),
.I2(sig000000e5),
.I3(sig000000d9),
.O(sig00000139)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk0000025d (
.I0(sig000000db),
.I1(sig000000dc),
.I2(sig000000dd),
.I3(sig000000da),
.O(sig00000132)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000025e (
.I0(sig000001ac),
.I1(sig0000012b),
.O(sig0000011d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000025f (
.I0(sig000001ad),
.I1(sig0000012b),
.O(sig0000011e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000260 (
.I0(sig000001ae),
.I1(sig0000012b),
.O(sig0000011f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000261 (
.I0(sig000001af),
.I1(sig0000012b),
.O(sig00000120)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000262 (
.I0(sig000001b0),
.I1(sig0000012b),
.O(sig00000121)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000263 (
.I0(sig000001b1),
.I1(sig0000012b),
.O(sig00000122)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000264 (
.I0(sig000001b2),
.I1(sig0000012b),
.O(sig00000123)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000265 (
.I0(sig000001b3),
.I1(sig0000012b),
.O(sig00000124)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000266 (
.I0(sig000001b4),
.I1(sig0000012b),
.O(sig00000125)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000267 (
.I0(sig000001b5),
.I1(sig0000012b),
.O(sig00000126)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000268 (
.I0(sig000001b6),
.I1(sig0000012b),
.O(sig00000127)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000269 (
.I0(sig000001b7),
.I1(sig0000012b),
.O(sig00000128)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000026a (
.I0(sig000001b8),
.I1(sig0000012b),
.O(sig00000129)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000026b (
.I0(sig000001b9),
.I1(sig0000012b),
.O(sig0000012a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000026c (
.I0(sig0000006d),
.I1(sig00000079),
.O(sig00000146)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000026d (
.I0(sig00000077),
.I1(sig00000079),
.O(sig00000150)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000026e (
.I0(sig00000078),
.I1(sig00000079),
.O(sig00000151)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000026f (
.I0(sig0000006e),
.I1(sig00000079),
.O(sig00000147)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000270 (
.I0(sig0000006f),
.I1(sig00000079),
.O(sig00000148)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000271 (
.I0(sig00000070),
.I1(sig00000079),
.O(sig00000149)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000272 (
.I0(sig00000071),
.I1(sig00000079),
.O(sig0000014a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000273 (
.I0(sig00000072),
.I1(sig00000079),
.O(sig0000014b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000274 (
.I0(sig00000073),
.I1(sig00000079),
.O(sig0000014c)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000275 (
.I0(sig00000074),
.I1(sig00000079),
.O(sig0000014d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000276 (
.I0(sig00000075),
.I1(sig00000079),
.O(sig0000014e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000277 (
.I0(sig00000076),
.I1(sig00000079),
.O(sig0000014f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000278 (
.I0(sig0000012b),
.I1(sig000001ba),
.O(sig00000114)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000279 (
.I0(sig00000191),
.I1(sig00000190),
.O(sig000000e2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000027a (
.I0(sig0000019b),
.I1(sig0000019a),
.O(sig000000ea)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000027b (
.I0(sig0000012b),
.I1(sig000001ba),
.O(sig000000f4)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000027c (
.I0(sig0000019c),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000105)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000027d (
.I0(sig0000019d),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000106)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000027e (
.I0(sig0000019e),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000107)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000027f (
.I0(sig0000019f),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000108)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000280 (
.I0(sig000001a0),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000109)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000281 (
.I0(sig000001a1),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig0000010a)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000282 (
.I0(sig000001a2),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig0000010b)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000283 (
.I0(sig000000e6),
.I1(sig0000019b),
.I2(sig0000019a),
.I3(sig000000e9),
.I4(sig000000e8),
.I5(sig000000e7),
.O(sig000000d9)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000284 (
.I0(sig000000de),
.I1(sig00000191),
.I2(sig00000190),
.I3(sig000000e1),
.I4(sig000000e0),
.I5(sig000000df),
.O(sig000000da)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000285 (
.I0(sig000001a3),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig0000010c)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk00000286 (
.I0(sig000000e7),
.I1(sig0000019b),
.I2(sig0000019a),
.I3(sig000000e9),
.I4(sig000000e8),
.O(sig00000135)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk00000287 (
.I0(sig000000e6),
.I1(sig0000019b),
.I2(sig0000019a),
.I3(sig000000e9),
.I4(sig000000e8),
.I5(sig000000e7),
.O(sig00000136)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk00000288 (
.I0(sig000000e8),
.I1(sig0000019b),
.I2(sig0000019a),
.I3(sig000000e9),
.O(sig00000134)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk00000289 (
.I0(sig000000df),
.I1(sig00000191),
.I2(sig00000190),
.I3(sig000000e1),
.I4(sig000000e0),
.O(sig0000012e)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk0000028a (
.I0(sig000000de),
.I1(sig00000191),
.I2(sig00000190),
.I3(sig000000e1),
.I4(sig000000e0),
.I5(sig000000df),
.O(sig0000012f)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk0000028b (
.I0(sig000000e0),
.I1(sig00000191),
.I2(sig00000190),
.I3(sig000000e1),
.O(sig0000012d)
);
LUT3 #(
.INIT ( 8'h6A ))
blk0000028c (
.I0(sig000000e1),
.I1(sig00000191),
.I2(sig00000190),
.O(sig0000012c)
);
LUT3 #(
.INIT ( 8'h6A ))
blk0000028d (
.I0(sig000000e9),
.I1(sig0000019b),
.I2(sig0000019a),
.O(sig00000133)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000028e (
.I0(sig0000006d),
.I1(sig00000079),
.O(sig0000013a)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000028f (
.I0(sig00000077),
.I1(sig00000079),
.O(sig00000144)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000290 (
.I0(sig00000078),
.I1(sig00000079),
.O(sig00000145)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000291 (
.I0(sig0000006e),
.I1(sig00000079),
.O(sig0000013b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000292 (
.I0(sig0000006f),
.I1(sig00000079),
.O(sig0000013c)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000293 (
.I0(sig00000070),
.I1(sig00000079),
.O(sig0000013d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000294 (
.I0(sig00000071),
.I1(sig00000079),
.O(sig0000013e)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000295 (
.I0(sig00000072),
.I1(sig00000079),
.O(sig0000013f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000296 (
.I0(sig00000073),
.I1(sig00000079),
.O(sig00000140)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000297 (
.I0(sig00000074),
.I1(sig00000079),
.O(sig00000141)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000298 (
.I0(sig00000075),
.I1(sig00000079),
.O(sig00000142)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000299 (
.I0(sig00000076),
.I1(sig00000079),
.O(sig00000143)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000029a (
.I0(sig000001a4),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig0000010d)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000029b (
.I0(sig000001a5),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig0000010e)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000029c (
.I0(sig000001a6),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig0000010f)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000029d (
.I0(sig000001a7),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000110)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000029e (
.I0(sig000001a8),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000111)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000029f (
.I0(sig000001a9),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000112)
);
LUT3 #(
.INIT ( 8'h96 ))
blk000002a0 (
.I0(sig000001aa),
.I1(sig0000012b),
.I2(sig000001ba),
.O(sig00000113)
);
LUT1 #(
.INIT ( 2'h2 ))
blk000002a1 (
.I0(sig000001ab),
.O(sig000001bd)
);
INV blk000002a2 (
.I(sig00000003),
.O(sig00000006)
);
RAMB36E1 #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0101010101010101010101010101010000000000000000000000000000000000 ),
.INIT_03 ( 256'h0101010101010101010101010101010101010101010101010101010101010101 ),
.INIT_04 ( 256'h0101010101010101010101010101010101010101010101010101010101010101 ),
.INIT_05 ( 256'h0202020202020202020202020202020202020202020202020202020202010101 ),
.INIT_06 ( 256'h0202020202020202020202020202020202020202020202020202020202020202 ),
.INIT_07 ( 256'h0303030303030303030303020202020202020202020202020202020202020202 ),
.INIT_08 ( 256'h0303030303030303030303030303030303030303030303030303030303030303 ),
.INIT_09 ( 256'h0303030303030303030303030303030303030303030303030303030303030303 ),
.INIT_0A ( 256'h0404040404040404040404040404040404040404040404040403030303030303 ),
.INIT_0B ( 256'h0404040404040404040404040404040404040404040404040404040404040404 ),
.INIT_0C ( 256'h0505050505050504040404040404040404040404040404040404040404040404 ),
.INIT_0D ( 256'h0505050505050505050505050505050505050505050505050505050505050505 ),
.INIT_0E ( 256'h0505050505050505050505050505050505050505050505050505050505050505 ),
.INIT_0F ( 256'h0606060606060606060606060606060606060606050505050505050505050505 ),
.INIT_10 ( 256'h0606060606060606060606060606060606060606060606060606060606060606 ),
.INIT_11 ( 256'h0706060606060606060606060606060606060606060606060606060606060606 ),
.INIT_12 ( 256'h0707070707070707070707070707070707070707070707070707070707070707 ),
.INIT_13 ( 256'h0707070707070707070707070707070707070707070707070707070707070707 ),
.INIT_14 ( 256'h0808080808080808080808080807070707070707070707070707070707070707 ),
.INIT_15 ( 256'h0808080808080808080808080808080808080808080808080808080808080808 ),
.INIT_16 ( 256'h0808080808080808080808080808080808080808080808080808080808080808 ),
.INIT_17 ( 256'h0909090909090909090909090909090909090909090909090908080808080808 ),
.INIT_18 ( 256'h0909090909090909090909090909090909090909090909090909090909090909 ),
.INIT_19 ( 256'h0A0A0A0909090909090909090909090909090909090909090909090909090909 ),
.INIT_1A ( 256'h0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A ),
.INIT_1B ( 256'h0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A ),
.INIT_1C ( 256'h0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A ),
.INIT_1D ( 256'h0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B ),
.INIT_1E ( 256'h0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B ),
.INIT_1F ( 256'h0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0B0B0B0B0B0B0B0B0B0B ),
.INIT_20 ( 256'h0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C ),
.INIT_21 ( 256'h0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C ),
.INIT_22 ( 256'h0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C ),
.INIT_23 ( 256'h0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D ),
.INIT_24 ( 256'h0E0E0E0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D ),
.INIT_25 ( 256'h0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E ),
.INIT_26 ( 256'h0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E ),
.INIT_27 ( 256'h0F0F0F0F0F0F0F0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E ),
.INIT_28 ( 256'h0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F ),
.INIT_29 ( 256'h0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F ),
.INIT_2A ( 256'h10101010101010101010100F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F ),
.INIT_2B ( 256'h1010101010101010101010101010101010101010101010101010101010101010 ),
.INIT_2C ( 256'h1010101010101010101010101010101010101010101010101010101010101010 ),
.INIT_2D ( 256'h1111111111111111111111111010101010101010101010101010101010101010 ),
.INIT_2E ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_2F ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_30 ( 256'h1212121212121212121211111111111111111111111111111111111111111111 ),
.INIT_31 ( 256'h1212121212121212121212121212121212121212121212121212121212121212 ),
.INIT_32 ( 256'h1212121212121212121212121212121212121212121212121212121212121212 ),
.INIT_33 ( 256'h1313131313131212121212121212121212121212121212121212121212121212 ),
.INIT_34 ( 256'h1313131313131313131313131313131313131313131313131313131313131313 ),
.INIT_35 ( 256'h1313131313131313131313131313131313131313131313131313131313131313 ),
.INIT_36 ( 256'h1313131313131313131313131313131313131313131313131313131313131313 ),
.INIT_37 ( 256'h1414141414141414141414141414141414141414141414141414141414141414 ),
.INIT_38 ( 256'h1414141414141414141414141414141414141414141414141414141414141414 ),
.INIT_39 ( 256'h1414141414141414141414141414141414141414141414141414141414141414 ),
.INIT_3A ( 256'h1515151515151515151515151515151515151515151414141414141414141414 ),
.INIT_3B ( 256'h1515151515151515151515151515151515151515151515151515151515151515 ),
.INIT_3C ( 256'h1515151515151515151515151515151515151515151515151515151515151515 ),
.INIT_3D ( 256'h1616161616161615151515151515151515151515151515151515151515151515 ),
.INIT_3E ( 256'h1616161616161616161616161616161616161616161616161616161616161616 ),
.INIT_3F ( 256'h1616161616161616161616161616161616161616161616161616161616161616 ),
.INIT_40 ( 256'h1616161616161616161616161616161616161616161616161616161616161616 ),
.INIT_41 ( 256'h1717171717171717171717171717171717171717171616161616161616161616 ),
.INIT_42 ( 256'h1717171717171717171717171717171717171717171717171717171717171717 ),
.INIT_43 ( 256'h1717171717171717171717171717171717171717171717171717171717171717 ),
.INIT_44 ( 256'h1717171717171717171717171717171717171717171717171717171717171717 ),
.INIT_45 ( 256'h1818181818181818181818181818181818181818181818181818181818171717 ),
.INIT_46 ( 256'h1818181818181818181818181818181818181818181818181818181818181818 ),
.INIT_47 ( 256'h1818181818181818181818181818181818181818181818181818181818181818 ),
.INIT_48 ( 256'h1818181818181818181818181818181818181818181818181818181818181818 ),
.INIT_49 ( 256'h1919191919191919191919191919191919191919191919191919191919191818 ),
.INIT_4A ( 256'h1919191919191919191919191919191919191919191919191919191919191919 ),
.INIT_4B ( 256'h1919191919191919191919191919191919191919191919191919191919191919 ),
.INIT_4C ( 256'h1919191919191919191919191919191919191919191919191919191919191919 ),
.INIT_4D ( 256'h1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A191919191919191919 ),
.INIT_4E ( 256'h1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A ),
.INIT_4F ( 256'h1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A ),
.INIT_50 ( 256'h1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A ),
.INIT_51 ( 256'h1B1B1B1B1B1B1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A ),
.INIT_52 ( 256'h1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B ),
.INIT_53 ( 256'h1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B ),
.INIT_54 ( 256'h1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B ),
.INIT_55 ( 256'h1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B ),
.INIT_56 ( 256'h1C1C1C1C1C1C1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B ),
.INIT_57 ( 256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C ),
.INIT_58 ( 256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C ),
.INIT_59 ( 256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C ),
.INIT_5A ( 256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C ),
.INIT_5B ( 256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C ),
.INIT_5C ( 256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1C1C1C1C1C1C1C1C1C1C1C1C1C1C ),
.INIT_5D ( 256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D ),
.INIT_5E ( 256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D ),
.INIT_5F ( 256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D ),
.INIT_60 ( 256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D ),
.INIT_61 ( 256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D ),
.INIT_62 ( 256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D ),
.INIT_63 ( 256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1D ),
.INIT_64 ( 256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E ),
.INIT_65 ( 256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E ),
.INIT_66 ( 256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E ),
.INIT_67 ( 256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E ),
.INIT_68 ( 256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E ),
.INIT_69 ( 256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E ),
.INIT_6A ( 256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E ),
.INIT_6B ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E ),
.INIT_6C ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_6D ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_6E ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_6F ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_70 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_71 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_72 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_73 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_74 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_75 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_76 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_77 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_78 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_79 ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_7A ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_7B ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_7C ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_7D ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_7E ( 256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_7F ( 256'h20202020202020202020202020202020202020201F1F1F1F1F1F1F1F1F1F1F1F ),
.INIT_A ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.READ_WIDTH_A ( 9 ),
.READ_WIDTH_B ( 9 ),
.WRITE_WIDTH_A ( 9 ),
.WRITE_WIDTH_B ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_B ( 36'h000000000 ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.RAM_MODE ( "TDP" ),
.RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ),
.RSTREG_PRIORITY_A ( "RSTREG" ),
.RSTREG_PRIORITY_B ( "RSTREG" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.INIT_FILE ( "NONE" ))
blk000002a3 (
.CASCADEINA(NLW_blk000002a3_CASCADEINA_UNCONNECTED),
.CASCADEINB(NLW_blk000002a3_CASCADEINB_UNCONNECTED),
.CASCADEOUTA(NLW_blk000002a3_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_blk000002a3_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(aclk),
.CLKBWRCLK(aclk),
.DBITERR(NLW_blk000002a3_DBITERR_UNCONNECTED),
.ENARDEN(sig00000001),
.ENBWREN(sig00000001),
.INJECTDBITERR(NLW_blk000002a3_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_blk000002a3_INJECTSBITERR_UNCONNECTED),
.REGCEAREGCE(sig00000001),
.REGCEB(sig00000001),
.RSTRAMARSTRAM(sig00000002),
.RSTRAMB(sig00000002),
.RSTREGARSTREG(sig00000002),
.RSTREGB(sig00000002),
.SBITERR(NLW_blk000002a3_SBITERR_UNCONNECTED),
.ADDRARDADDR({sig00000001, sig0000015d, sig0000015c, sig0000015b, sig0000015a, sig00000159, sig00000158, sig00000157, sig00000156, sig00000155,
sig00000154, sig00000153, sig00000152, sig00000001, sig00000001, sig00000001}),
.ADDRBWRADDR({sig00000001, sig00000187, sig00000186, sig00000185, sig00000184, sig00000183, sig00000182, sig00000181, sig00000180, sig0000017f,
sig0000017e, sig0000017d, sig0000017c, sig00000001, sig00000001, sig00000001}),
.DIADI({\NLW_blk000002a3_DIADI<31>_UNCONNECTED , \NLW_blk000002a3_DIADI<30>_UNCONNECTED , \NLW_blk000002a3_DIADI<29>_UNCONNECTED ,
\NLW_blk000002a3_DIADI<28>_UNCONNECTED , \NLW_blk000002a3_DIADI<27>_UNCONNECTED , \NLW_blk000002a3_DIADI<26>_UNCONNECTED ,
\NLW_blk000002a3_DIADI<25>_UNCONNECTED , \NLW_blk000002a3_DIADI<24>_UNCONNECTED , \NLW_blk000002a3_DIADI<23>_UNCONNECTED ,
\NLW_blk000002a3_DIADI<22>_UNCONNECTED , \NLW_blk000002a3_DIADI<21>_UNCONNECTED , \NLW_blk000002a3_DIADI<20>_UNCONNECTED ,
\NLW_blk000002a3_DIADI<19>_UNCONNECTED , \NLW_blk000002a3_DIADI<18>_UNCONNECTED , \NLW_blk000002a3_DIADI<17>_UNCONNECTED ,
\NLW_blk000002a3_DIADI<16>_UNCONNECTED , \NLW_blk000002a3_DIADI<15>_UNCONNECTED , \NLW_blk000002a3_DIADI<14>_UNCONNECTED ,
\NLW_blk000002a3_DIADI<13>_UNCONNECTED , \NLW_blk000002a3_DIADI<12>_UNCONNECTED , \NLW_blk000002a3_DIADI<11>_UNCONNECTED ,
\NLW_blk000002a3_DIADI<10>_UNCONNECTED , \NLW_blk000002a3_DIADI<9>_UNCONNECTED , \NLW_blk000002a3_DIADI<8>_UNCONNECTED , sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.DIBDI({\NLW_blk000002a3_DIBDI<31>_UNCONNECTED , \NLW_blk000002a3_DIBDI<30>_UNCONNECTED , \NLW_blk000002a3_DIBDI<29>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<28>_UNCONNECTED , \NLW_blk000002a3_DIBDI<27>_UNCONNECTED , \NLW_blk000002a3_DIBDI<26>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<25>_UNCONNECTED , \NLW_blk000002a3_DIBDI<24>_UNCONNECTED , \NLW_blk000002a3_DIBDI<23>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<22>_UNCONNECTED , \NLW_blk000002a3_DIBDI<21>_UNCONNECTED , \NLW_blk000002a3_DIBDI<20>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<19>_UNCONNECTED , \NLW_blk000002a3_DIBDI<18>_UNCONNECTED , \NLW_blk000002a3_DIBDI<17>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<16>_UNCONNECTED , \NLW_blk000002a3_DIBDI<15>_UNCONNECTED , \NLW_blk000002a3_DIBDI<14>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<13>_UNCONNECTED , \NLW_blk000002a3_DIBDI<12>_UNCONNECTED , \NLW_blk000002a3_DIBDI<11>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<10>_UNCONNECTED , \NLW_blk000002a3_DIBDI<9>_UNCONNECTED , \NLW_blk000002a3_DIBDI<8>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<7>_UNCONNECTED , \NLW_blk000002a3_DIBDI<6>_UNCONNECTED , \NLW_blk000002a3_DIBDI<5>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<4>_UNCONNECTED , \NLW_blk000002a3_DIBDI<3>_UNCONNECTED , \NLW_blk000002a3_DIBDI<2>_UNCONNECTED ,
\NLW_blk000002a3_DIBDI<1>_UNCONNECTED , \NLW_blk000002a3_DIBDI<0>_UNCONNECTED }),
.DIPADIP({\NLW_blk000002a3_DIPADIP<3>_UNCONNECTED , \NLW_blk000002a3_DIPADIP<2>_UNCONNECTED , \NLW_blk000002a3_DIPADIP<1>_UNCONNECTED ,
sig00000002}),
.DIPBDIP({\NLW_blk000002a3_DIPBDIP<3>_UNCONNECTED , \NLW_blk000002a3_DIPBDIP<2>_UNCONNECTED , \NLW_blk000002a3_DIPBDIP<1>_UNCONNECTED ,
\NLW_blk000002a3_DIPBDIP<0>_UNCONNECTED }),
.DOADO({\NLW_blk000002a3_DOADO<31>_UNCONNECTED , \NLW_blk000002a3_DOADO<30>_UNCONNECTED , \NLW_blk000002a3_DOADO<29>_UNCONNECTED ,
\NLW_blk000002a3_DOADO<28>_UNCONNECTED , \NLW_blk000002a3_DOADO<27>_UNCONNECTED , \NLW_blk000002a3_DOADO<26>_UNCONNECTED ,
\NLW_blk000002a3_DOADO<25>_UNCONNECTED , \NLW_blk000002a3_DOADO<24>_UNCONNECTED , \NLW_blk000002a3_DOADO<23>_UNCONNECTED ,
\NLW_blk000002a3_DOADO<22>_UNCONNECTED , \NLW_blk000002a3_DOADO<21>_UNCONNECTED , \NLW_blk000002a3_DOADO<20>_UNCONNECTED ,
\NLW_blk000002a3_DOADO<19>_UNCONNECTED , \NLW_blk000002a3_DOADO<18>_UNCONNECTED , \NLW_blk000002a3_DOADO<17>_UNCONNECTED ,
\NLW_blk000002a3_DOADO<16>_UNCONNECTED , \NLW_blk000002a3_DOADO<15>_UNCONNECTED , \NLW_blk000002a3_DOADO<14>_UNCONNECTED ,
\NLW_blk000002a3_DOADO<13>_UNCONNECTED , \NLW_blk000002a3_DOADO<12>_UNCONNECTED , \NLW_blk000002a3_DOADO<11>_UNCONNECTED ,
\NLW_blk000002a3_DOADO<10>_UNCONNECTED , \NLW_blk000002a3_DOADO<9>_UNCONNECTED , \NLW_blk000002a3_DOADO<8>_UNCONNECTED ,
\NLW_blk000002a3_DOADO<7>_UNCONNECTED , \NLW_blk000002a3_DOADO<6>_UNCONNECTED , sig0000017b, sig0000017a, sig00000179, sig00000178, sig00000177,
sig00000176}),
.DOBDO({\NLW_blk000002a3_DOBDO<31>_UNCONNECTED , \NLW_blk000002a3_DOBDO<30>_UNCONNECTED , \NLW_blk000002a3_DOBDO<29>_UNCONNECTED ,
\NLW_blk000002a3_DOBDO<28>_UNCONNECTED , \NLW_blk000002a3_DOBDO<27>_UNCONNECTED , \NLW_blk000002a3_DOBDO<26>_UNCONNECTED ,
\NLW_blk000002a3_DOBDO<25>_UNCONNECTED , \NLW_blk000002a3_DOBDO<24>_UNCONNECTED , \NLW_blk000002a3_DOBDO<23>_UNCONNECTED ,
\NLW_blk000002a3_DOBDO<22>_UNCONNECTED , \NLW_blk000002a3_DOBDO<21>_UNCONNECTED , \NLW_blk000002a3_DOBDO<20>_UNCONNECTED ,
\NLW_blk000002a3_DOBDO<19>_UNCONNECTED , \NLW_blk000002a3_DOBDO<18>_UNCONNECTED , \NLW_blk000002a3_DOBDO<17>_UNCONNECTED ,
\NLW_blk000002a3_DOBDO<16>_UNCONNECTED , \NLW_blk000002a3_DOBDO<15>_UNCONNECTED , \NLW_blk000002a3_DOBDO<14>_UNCONNECTED ,
\NLW_blk000002a3_DOBDO<13>_UNCONNECTED , \NLW_blk000002a3_DOBDO<12>_UNCONNECTED , \NLW_blk000002a3_DOBDO<11>_UNCONNECTED ,
\NLW_blk000002a3_DOBDO<10>_UNCONNECTED , \NLW_blk000002a3_DOBDO<9>_UNCONNECTED , \NLW_blk000002a3_DOBDO<8>_UNCONNECTED ,
\NLW_blk000002a3_DOBDO<7>_UNCONNECTED , \NLW_blk000002a3_DOBDO<6>_UNCONNECTED , sig0000016c, sig0000016b, sig0000016a, sig00000169, sig00000168,
sig00000167}),
.DOPADOP({\NLW_blk000002a3_DOPADOP<3>_UNCONNECTED , \NLW_blk000002a3_DOPADOP<2>_UNCONNECTED , \NLW_blk000002a3_DOPADOP<1>_UNCONNECTED ,
\NLW_blk000002a3_DOPADOP<0>_UNCONNECTED }),
.DOPBDOP({\NLW_blk000002a3_DOPBDOP<3>_UNCONNECTED , \NLW_blk000002a3_DOPBDOP<2>_UNCONNECTED , \NLW_blk000002a3_DOPBDOP<1>_UNCONNECTED ,
\NLW_blk000002a3_DOPBDOP<0>_UNCONNECTED }),
.ECCPARITY({\NLW_blk000002a3_ECCPARITY<7>_UNCONNECTED , \NLW_blk000002a3_ECCPARITY<6>_UNCONNECTED , \NLW_blk000002a3_ECCPARITY<5>_UNCONNECTED ,
\NLW_blk000002a3_ECCPARITY<4>_UNCONNECTED , \NLW_blk000002a3_ECCPARITY<3>_UNCONNECTED , \NLW_blk000002a3_ECCPARITY<2>_UNCONNECTED ,
\NLW_blk000002a3_ECCPARITY<1>_UNCONNECTED , \NLW_blk000002a3_ECCPARITY<0>_UNCONNECTED }),
.RDADDRECC({\NLW_blk000002a3_RDADDRECC<8>_UNCONNECTED , \NLW_blk000002a3_RDADDRECC<7>_UNCONNECTED , \NLW_blk000002a3_RDADDRECC<6>_UNCONNECTED ,
\NLW_blk000002a3_RDADDRECC<5>_UNCONNECTED , \NLW_blk000002a3_RDADDRECC<4>_UNCONNECTED , \NLW_blk000002a3_RDADDRECC<3>_UNCONNECTED ,
\NLW_blk000002a3_RDADDRECC<2>_UNCONNECTED , \NLW_blk000002a3_RDADDRECC<1>_UNCONNECTED , \NLW_blk000002a3_RDADDRECC<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.WEBWE({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB36E1 #(
.INITP_00 ( 256'h001FFFFFFFFFF00000000007FFFFFFFFFC0000000001FFFFFFFFFE0000000000 ),
.INITP_01 ( 256'h00000FFFFFFFFFFC0000000001FFFFFFFFFF00000000007FFFFFFFFFC0000000 ),
.INITP_02 ( 256'h0000007FFFFFFFFFE00000000007FFFFFFFFFE00000000007FFFFFFFFFE00000 ),
.INITP_03 ( 256'h000003FFFFFFFFFFC00000000007FFFFFFFFFF00000000001FFFFFFFFFFC0000 ),
.INITP_04 ( 256'h00FFFFFFFFFFFC00000000001FFFFFFFFFFF000000000007FFFFFFFFFFC00000 ),
.INITP_05 ( 256'hFFFFFFE000000000000FFFFFFFFFFFE000000000001FFFFFFFFFFFC000000000 ),
.INITP_06 ( 256'h00000000FFFFFFFFFFFFE0000000000003FFFFFFFFFFFF8000000000003FFFFF ),
.INITP_07 ( 256'hFFFE00000000000001FFFFFFFFFFFFFE00000000000007FFFFFFFFFFFFE00000 ),
.INITP_08 ( 256'hFFFFFFFC0000000000000007FFFFFFFFFFFFFFC000000000000007FFFFFFFFFF ),
.INITP_09 ( 256'hFFFF000000000000000001FFFFFFFFFFFFFFFFF00000000000000003FFFFFFFF ),
.INITP_0A ( 256'h0000000003FFFFFFFFFFFFFFFFFFFF00000000000000000003FFFFFFFFFFFFFF ),
.INITP_0B ( 256'hFFFC0000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFE000000000000 ),
.INITP_0C ( 256'hFFFFFFFFC0000000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFF ),
.INITP_0D ( 256'h000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INITP_0E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000 ),
.INITP_0F ( 256'h00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_00 ( 256'hC6C0B9B3ADA7A09A948D87817B746E68615B554F48423C352F29231C16100903 ),
.INIT_01 ( 256'h8F89827C767069635D56504A443D37312A241E18110B05FEF8F2ECE5DFD9D2CC ),
.INIT_02 ( 256'h58524B453F39322C261F19130D0600FAF3EDE7E1DAD4CEC7C1BBB5AEA8A29C95 ),
.INIT_03 ( 256'h211B140E0801FBF5EFE8E2DCD5CFC9C3BCB6B0AAA39D97908A847E77716B645E ),
.INIT_04 ( 256'hEAE3DDD7D0CAC4BEB7B1ABA59E98928B857F79726C666059534D46403A342D27 ),
.INIT_05 ( 256'hB2ACA69F99938D86807A736D67615A544E48413B352F28221C150F0903FCF6F0 ),
.INIT_06 ( 256'h7B746E68625B554F48423C362F29231D16100A04FDF7F1EBE4DED8D1CBC5BFB8 ),
.INIT_07 ( 256'h433D36302A241D17110A04FEF8F1EBE5DFD8D2CCC6BFB9B3ADA6A09A948D8781 ),
.INIT_08 ( 256'h0B05FEF8F2ECE5DFD9D3CCC6C0BAB3ADA7A19A948E88817B756F68625C564F49 ),
.INIT_09 ( 256'hD2CCC6C0BAB3ADA7A19A948E88817B756F68625C564F49433D36302A241D1711 ),
.INIT_0A ( 256'h9A948D87817B746E68625C554F49433C36302A241D17110B04FEF8F2EBE5DFD9 ),
.INIT_0B ( 256'h615B544E48423C352F29231D16100A04FDF7F1EBE5DED8D2CCC5BFB9B3ADA6A0 ),
.INIT_0C ( 256'h28211B150F0902FCF6F0EAE3DDD7D1CBC4BEB8B2ABA59F99938C86807A746D67 ),
.INIT_0D ( 256'hEEE8E2DBD5CFC9C3BCB6B0AAA49D97918B857E78726C665F59534D47403A342E ),
.INIT_0E ( 256'hB4AEA7A19B958F89827C76706A635D57514B453E38322C261F19130D0701FAF4 ),
.INIT_0F ( 256'h79736D67615A544E48423C352F29231D17100A04FEF8F2EBE5DFD9D3CDC6C0BA ),
.INIT_10 ( 256'h3E38322C261F19130D0701FBF4EEE8E2DCD6D0C9C3BDB7B1ABA49E98928C867F ),
.INIT_11 ( 256'h03FDF6F0EAE4DED8D2CBC5BFB9B3ADA7A19A948E88827C766F69635D57514B44 ),
.INIT_12 ( 256'hC7C0BAB4AEA8A29C969089837D77716B655F58524C46403A342E27211B150F09 ),
.INIT_13 ( 256'h8A847E78726B655F59534D47413B352E28221C16100A04FEF7F1EBE5DFD9D3CD ),
.INIT_14 ( 256'h4D47413A342E28221C16100A04FEF8F1EBE5DFD9D3CDC7C1BBB5AFA8A29C9690 ),
.INIT_15 ( 256'h0F0903FDF7F1EAE4DED8D2CCC6C0BAB4AEA8A29C968F89837D77716B655F5953 ),
.INIT_16 ( 256'hD0CAC4BEB8B2ACA6A09A948E88827C76706A645D57514B453F39332D27211B15 ),
.INIT_17 ( 256'h918B857F79736D67615B554F49433D37312B251F19130D0701FAF4EEE8E2DCD6 ),
.INIT_18 ( 256'h514B453F39332D27211B150F0903FDF7F1EBE5DFD9D3CDC7C1BBB5AFA9A39D97 ),
.INIT_19 ( 256'h100A04FEF9F3EDE7E1DBD5CFC9C3BDB7B1ABA59F99938D87817B756F69635D57 ),
.INIT_1A ( 256'hCFC9C3BDB7B1ABA59F99938E88827C76706A645E58524C46403A342E28221C16 ),
.INIT_1B ( 256'h8D87817B756F69635D57514C46403A342E28221C16100A04FEF8F3EDE7E1DBD5 ),
.INIT_1C ( 256'h4A443E38322C26201A150F0903FDF7F1EBE5DFD9D4CEC8C2BCB6B0AAA49E9893 ),
.INIT_1D ( 256'h0600FAF4EEE8E2DDD7D1CBC5BFB9B3AEA8A29C96908A847F79736D67615B554F ),
.INIT_1E ( 256'hC1BBB5AFA9A49E98928C86817B756F69635D58524C46403A342F29231D17110B ),
.INIT_1F ( 256'h7B756F6A645E58524D47413B352F2A241E18120D0701FBF5EFEAE4DED8D2CCC7 ),
.INIT_20 ( 256'h342F29231D17120C0600FAF5EFE9E3DED8D2CCC6C1BBB5AFA9A49E98928C8781 ),
.INIT_21 ( 256'hEDE7E1DBD6D0CAC4BFB9B3ADA8A29C96918B857F7A746E68625D57514B46403A ),
.INIT_22 ( 256'hA49E98938D87827C76706B655F5A544E48433D37312C26201B150F0904FEF8F2 ),
.INIT_23 ( 256'h5A554F49433E38322D27211C16100B05FFFAF4EEE8E3DDD7D2CCC6C0BBB5AFAA ),
.INIT_24 ( 256'h0F0A04FFF9F3EEE8E2DDD7D1CCC6C0BBB5AFAAA49E99938D88827C77716B6660 ),
.INIT_25 ( 256'hC4BEB8B3ADA8A29C97918B86807B756F6A645E59534E48423D37312C26201B15 ),
.INIT_26 ( 256'h77716C66605B55504A443F39342E28231D18120D0701FCF6F0EBE5E0DAD4CFC9 ),
.INIT_27 ( 256'h29231E18120D0702FCF7F1ECE6E0DBD5D0CAC5BFBAB4AEA9A39E98938D87827C ),
.INIT_28 ( 256'hD9D4CEC9C3BEB8B3ADA8A29D97928C87817C76716B65605A554F4A443F39342E ),
.INIT_29 ( 256'h89837E79736E68635D58524D47423C37312C26211B16100B0500FAF5EFEAE4DF ),
.INIT_2A ( 256'h37322C27221C17110C0601FBF6F1EBE6E0DBD5D0CAC5C0BAB5AFAAA49F99948E ),
.INIT_2B ( 256'hE4DFDAD4CFC9C4BFB9B4AEA9A49E99938E89837E78736D68635D58524D48423D ),
.INIT_2C ( 256'h908B86807B75706B65605B55504B45403A35302A25201A150F0A05FFFAF5EFEA ),
.INIT_2D ( 256'h3B35302B26201B16100B0600FBF6F0EBE6E0DBD6D0CBC6C0BBB6B0ABA6A09B96 ),
.INIT_2E ( 256'hE4DFD9D4CFCAC4BFBAB5AFAAA59F9A95908A85807A75706A65605B55504B4540 ),
.INIT_2F ( 256'h8C87817C77726C67625D58524D48433D38332E28231E19130E0904FEF9F4EFE9 ),
.INIT_30 ( 256'h322D28231E18130E0904FEF9F4EFEAE4DFDAD5D0CAC5C0BBB6B0ABA6A19C9691 ),
.INIT_31 ( 256'hD7D2CDC8C3BEB9B3AEA9A49F9A958F8A85807B76706B66615C57514C47423D38 ),
.INIT_32 ( 256'h7B76716C67625D57524D48433E39342F29241F1A15100B0601FBF6F1ECE7E2DD ),
.INIT_33 ( 256'h1D18130E0904FFFAF5F0EBE6E1DCD7D2CCC7C2BDB8B3AEA9A49F9A95908A8580 ),
.INIT_34 ( 256'hBEB9B4AFAAA5A09B96918C87827D78736E69645F5A55504B46413C37322D2822 ),
.INIT_35 ( 256'h5D59544F4A45403B36312C27221D18130E0904FFFAF5F0EBE6E1DCD7D2CDC8C3 ),
.INIT_36 ( 256'hFBF6F1EDE8E3DED9D4CFCAC5C0BBB6B1ADA8A39E99948F8A85807B76716C6762 ),
.INIT_37 ( 256'h97938E89847F7A75716C67625D58534E4A45403B36312C27221E19140F0A0500 ),
.INIT_38 ( 256'h322D29241F1A15100C0702FDF8F3EFEAE5E0DBD6D2CDC8C3BEB9B5B0ABA6A19C ),
.INIT_39 ( 256'hCBC6C2BDB8B3AFAAA5A09C97928D88847F7A75716C67625D59544F4A45413C37 ),
.INIT_3A ( 256'h635E5955504B46423D38342F2A25211C17120E0904FFFBF6F1ECE8E3DED9D5D0 ),
.INIT_3B ( 256'hF8F4EFEBE6E1DDD8D3CFCAC5C1BCB7B2AEA9A4A09B96928D88847F7A75716C67 ),
.INIT_3C ( 256'h8D88837F7A76716C68635F5A55514C47433E3A35302C27221E1914100B0602FD ),
.INIT_3D ( 256'h1F1B16110D0804FFFBF6F2EDE8E4DFDBD6D2CDC8C4BFBBB6B1ADA8A49F9A9691 ),
.INIT_3E ( 256'hB0ABA7A29E9995908C87837E7A75716C68635F5A56514D48443F3A36312D2824 ),
.INIT_3F ( 256'h3F3B36322D2924201B17120E0A0501FCF8F3EFEAE6E1DDD8D4CFCBC6C2BDB9B4 ),
.INIT_40 ( 256'hCCC8C4BFBBB6B2AEA9A5A09C98938F8A86817D7974706B67635E5A55514C4843 ),
.INIT_41 ( 256'h58544F4B47423E3A35312C28241F1B17120E0A0501FDF8F4EFEBE7E2DED9D5D1 ),
.INIT_42 ( 256'hE2DDD9D5D1CCC8C4BFBBB7B3AEAAA6A19D9994908C87837F7B76726E6965615C ),
.INIT_43 ( 256'h6A65615D5955504C48443F3B37332E2A26221D1915110C080400FBF7F3EEEAE6 ),
.INIT_44 ( 256'hF0ECE7E3DFDBD7D3CECAC6C2BEB9B5B1ADA9A5A09C9894908B87837F7B76726E ),
.INIT_45 ( 256'h74706C6864605B57534F4B47433F3A36322E2A26221D1915110D090500FCF8F4 ),
.INIT_46 ( 256'hF6F2EEEAE6E2DEDAD6D2CECAC6C2BEBAB6B1ADA9A5A19D9995918D8984807C78 ),
.INIT_47 ( 256'h77736F6B67635F5B57534F4B47433F3B37332F2B27231F1B17130F0B0703FFFB ),
.INIT_48 ( 256'hF6F2EEEAE6E2DEDAD6D2CECAC6C2BEBBB7B3AFABA7A39F9B97938F8B87837F7B ),
.INIT_49 ( 256'h726E6B67635F5B57534F4C4844403C3834302C2925211D1915110D090501FDFA ),
.INIT_4A ( 256'hEDE9E5E2DEDAD6D2CFCBC7C3BFBBB8B4B0ACA8A4A19D9995918D8A86827E7A76 ),
.INIT_4B ( 256'h66625E5B57534F4C4844403D3935312E2A26221E1B17130F0B080400FCF8F5F1 ),
.INIT_4C ( 256'hDDD9D5D2CECAC7C3BFBBB8B4B0ADA9A5A29E9A96938F8B8784807C7975716D6A ),
.INIT_4D ( 256'h524E4A47433F3C3834312D2A26221F1B1714100C090501FEFAF6F3EFEBE8E4E0 ),
.INIT_4E ( 256'hC4C1BDBAB6B2AFABA8A4A19D9996928F8B8884807D7976726E6B6764605C5955 ),
.INIT_4F ( 256'h35322E2B2724201D1916120F0B070400FDF9F6F2EFEBE8E4E1DDDAD6D3CFCBC8 ),
.INIT_50 ( 256'hA4A09D9996938F8C8885817E7A7774706D6966625F5B5854514D4A4643403C39 ),
.INIT_51 ( 256'h100D0A060300FCF9F5F2EFEBE8E5E1DEDAD7D4D0CDC9C6C3BFBCB8B5B1AEABA7 ),
.INIT_52 ( 256'h7B7874716E6A6764615D5A5753504D4946433F3C3935322F2B2825211E1A1714 ),
.INIT_53 ( 256'hE3E0DDDAD6D3D0CDC9C6C3C0BCB9B6B3AFACA9A6A29F9C9995928F8B8885827E ),
.INIT_54 ( 256'h4A4743403D3A3734302D2A2724201D1A1714100D0A070400FDFAF7F4F0EDEAE7 ),
.INIT_55 ( 256'hAEABA8A5A29E9B9895928F8C8986827F7C797673706C696663605D5A5653504D ),
.INIT_56 ( 256'h100D0A070401FEFBF8F5F2EFEBE8E5E2DFDCD9D6D3D0CDCAC7C4C1BDBAB7B4B1 ),
.INIT_57 ( 256'h706D6A6764615E5B5855524F4C494643403D3A3734312E2B2825221F1C191613 ),
.INIT_58 ( 256'hCECBC8C5C2BFBCB9B6B4B1AEABA8A5A29F9C999693908D8A8885827F7C797673 ),
.INIT_59 ( 256'h292624211E1B181512100D0A070401FFFCF9F6F3F0EDEAE8E5E2DFDCD9D6D3D1 ),
.INIT_5A ( 256'h83807D7A7775726F6C6A6764615E5C595653514E4B484543403D3A3734322F2C ),
.INIT_5B ( 256'hDAD7D4D2CFCCC9C7C4C1BFBCB9B6B4B1AEACA9A6A3A19E9B989693908E8B8885 ),
.INIT_5C ( 256'h2E2C292724211F1C191714120F0C0A070402FFFCFAF7F4F2EFECEAE7E4E2DFDC ),
.INIT_5D ( 256'h817F7C797774726F6D6A686562605D5B585653504E4B494643413E3C39363431 ),
.INIT_5E ( 256'hD2CFCDCAC8C5C3C0BEBBB9B6B4B1AFACAAA7A5A2A09D9B989593908E8B898684 ),
.INIT_5F ( 256'h201D1B181614110F0C0A07050300FEFBF9F6F4F2EFEDEAE8E5E3E0DEDBD9D6D4 ),
.INIT_60 ( 256'h6B69676462605D5B595654524F4D4B484643413F3C3A383533302E2C29272422 ),
.INIT_61 ( 256'hB5B3B0AEACAAA7A5A3A19E9C9A979593918E8C8A878583807E7C79777572706E ),
.INIT_62 ( 256'hFCFAF8F6F3F1EFEDEBE8E6E4E2E0DDDBD9D7D4D2D0CECCC9C7C5C3C0BEBCBAB7 ),
.INIT_63 ( 256'h413F3D3B39373432302E2C2A282523211F1D1B19161412100E0C0907050301FE ),
.INIT_64 ( 256'h8482807E7C7A777573716F6D6B69676563615F5D5A58565452504E4C4A484543 ),
.INIT_65 ( 256'hC4C2C0BEBCBAB8B6B4B2B0AEACAAA8A6A4A2A09E9C9A98969492908E8C8A8886 ),
.INIT_66 ( 256'h0200FEFCFAF8F7F5F3F1EFEDEBE9E7E5E3E1DFDEDCDAD8D6D4D2D0CECCCAC8C6 ),
.INIT_67 ( 256'h3E3C3A38363433312F2D2B2928262422201E1C1B19171513110F0D0B0A080604 ),
.INIT_68 ( 256'h77757372706E6C6B6967656362605E5C5B5957555352504E4C4A49474543413F ),
.INIT_69 ( 256'hAEACAAA9A7A5A4A2A09E9D9B9998969493918F8D8C8A8886858381807E7C7A79 ),
.INIT_6A ( 256'hE2E1DFDDDCDAD8D7D5D4D2D0CFCDCBCAC8C7C5C3C2C0BEBDBBB9B8B6B4B3B1AF ),
.INIT_6B ( 256'h141311100E0D0B09080605030200FFFDFBFAF8F7F5F4F2F0EFEDECEAE9E7E5E4 ),
.INIT_6C ( 256'h444241403E3D3B3A3837353432312F2E2C2B292826252322201F1D1C1A191716 ),
.INIT_6D ( 256'h71706E6D6C6A696866656362615F5E5C5B595857555452514F4E4D4B4A484745 ),
.INIT_6E ( 256'h9C9B99989796949392908F8E8C8B8A888786848382807F7E7C7B797877757473 ),
.INIT_6F ( 256'hC5C3C2C1C0BEBDBCBBB9B8B7B6B4B3B2B1AFAEADACAAA9A8A6A5A4A3A1A09F9D ),
.INIT_70 ( 256'hEBE9E8E7E6E5E4E3E1E0DFDEDDDBDAD9D8D7D6D4D3D2D1D0CECDCCCBC9C8C7C6 ),
.INIT_71 ( 256'h0E0D0C0B0A090807060403020100FFFEFDFCFBF9F8F7F6F5F4F3F1F0EFEEEDEC ),
.INIT_72 ( 256'h2F2E2D2C2B2A292827262524232221201F1E1D1C1B1A1918171615141311100F ),
.INIT_73 ( 256'h4E4D4C4B4A4A494847464544434241403F3E3D3C3B3A39383736353433323130 ),
.INIT_74 ( 256'h6B6A69686766656564636261605F5E5E5D5C5B5A59585756565554535251504F ),
.INIT_75 ( 256'h848483828181807F7E7D7D7C7B7A797978777675757473727170706F6E6D6C6B ),
.INIT_76 ( 256'h9C9B9A9A99989897969595949393929190908F8E8D8D8C8B8A8A898887878685 ),
.INIT_77 ( 256'hB1B0B0AFAEAEADACACABABAAA9A9A8A7A7A6A5A5A4A3A3A2A1A1A09F9F9E9D9D ),
.INIT_78 ( 256'hC3C3C2C2C1C1C0BFBFBEBEBDBDBCBCBBBABAB9B9B8B7B7B6B6B5B4B4B3B3B2B1 ),
.INIT_79 ( 256'hD3D3D2D2D2D1D1D0D0CFCFCECECDCDCCCCCBCBCACAC9C9C8C8C7C7C6C5C5C4C4 ),
.INIT_7A ( 256'hE1E1E0E0DFDFDFDEDEDDDDDDDCDCDBDBDADADAD9D9D8D8D7D7D7D6D6D5D5D4D4 ),
.INIT_7B ( 256'hECECEBEBEBEBEAEAEAE9E9E9E8E8E8E7E7E7E6E6E5E5E5E4E4E4E3E3E3E2E2E1 ),
.INIT_7C ( 256'hF5F5F4F4F4F4F3F3F3F3F2F2F2F2F1F1F1F0F0F0F0EFEFEFEFEEEEEEEDEDEDEC ),
.INIT_7D ( 256'hFBFBFBFBFAFAFAFAFAF9F9F9F9F9F9F8F8F8F8F8F7F7F7F7F7F6F6F6F6F5F5F5 ),
.INIT_7E ( 256'hFFFFFFFEFEFEFEFEFEFEFEFEFEFEFDFDFDFDFDFDFDFDFCFCFCFCFCFCFCFBFBFB ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.READ_WIDTH_A ( 9 ),
.READ_WIDTH_B ( 9 ),
.WRITE_WIDTH_A ( 9 ),
.WRITE_WIDTH_B ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.RAM_MODE ( "TDP" ),
.RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ),
.RSTREG_PRIORITY_A ( "RSTREG" ),
.RSTREG_PRIORITY_B ( "RSTREG" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.INIT_FILE ( "NONE" ))
blk000002a4 (
.CASCADEINA(NLW_blk000002a4_CASCADEINA_UNCONNECTED),
.CASCADEINB(NLW_blk000002a4_CASCADEINB_UNCONNECTED),
.CASCADEOUTA(NLW_blk000002a4_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_blk000002a4_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(aclk),
.CLKBWRCLK(aclk),
.DBITERR(NLW_blk000002a4_DBITERR_UNCONNECTED),
.ENARDEN(sig00000001),
.ENBWREN(sig00000001),
.INJECTDBITERR(NLW_blk000002a4_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_blk000002a4_INJECTSBITERR_UNCONNECTED),
.REGCEAREGCE(sig00000001),
.REGCEB(sig00000001),
.RSTRAMARSTRAM(sig00000002),
.RSTRAMB(sig00000002),
.RSTREGARSTREG(sig00000002),
.RSTREGB(sig00000002),
.SBITERR(NLW_blk000002a4_SBITERR_UNCONNECTED),
.ADDRARDADDR({sig00000001, sig0000015d, sig0000015c, sig0000015b, sig0000015a, sig00000159, sig00000158, sig00000157, sig00000156, sig00000155,
sig00000154, sig00000153, sig00000152, sig00000001, sig00000001, sig00000001}),
.ADDRBWRADDR({sig00000001, sig00000187, sig00000186, sig00000185, sig00000184, sig00000183, sig00000182, sig00000181, sig00000180, sig0000017f,
sig0000017e, sig0000017d, sig0000017c, sig00000001, sig00000001, sig00000001}),
.DIADI({\NLW_blk000002a4_DIADI<31>_UNCONNECTED , \NLW_blk000002a4_DIADI<30>_UNCONNECTED , \NLW_blk000002a4_DIADI<29>_UNCONNECTED ,
\NLW_blk000002a4_DIADI<28>_UNCONNECTED , \NLW_blk000002a4_DIADI<27>_UNCONNECTED , \NLW_blk000002a4_DIADI<26>_UNCONNECTED ,
\NLW_blk000002a4_DIADI<25>_UNCONNECTED , \NLW_blk000002a4_DIADI<24>_UNCONNECTED , \NLW_blk000002a4_DIADI<23>_UNCONNECTED ,
\NLW_blk000002a4_DIADI<22>_UNCONNECTED , \NLW_blk000002a4_DIADI<21>_UNCONNECTED , \NLW_blk000002a4_DIADI<20>_UNCONNECTED ,
\NLW_blk000002a4_DIADI<19>_UNCONNECTED , \NLW_blk000002a4_DIADI<18>_UNCONNECTED , \NLW_blk000002a4_DIADI<17>_UNCONNECTED ,
\NLW_blk000002a4_DIADI<16>_UNCONNECTED , \NLW_blk000002a4_DIADI<15>_UNCONNECTED , \NLW_blk000002a4_DIADI<14>_UNCONNECTED ,
\NLW_blk000002a4_DIADI<13>_UNCONNECTED , \NLW_blk000002a4_DIADI<12>_UNCONNECTED , \NLW_blk000002a4_DIADI<11>_UNCONNECTED ,
\NLW_blk000002a4_DIADI<10>_UNCONNECTED , \NLW_blk000002a4_DIADI<9>_UNCONNECTED , \NLW_blk000002a4_DIADI<8>_UNCONNECTED , sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.DIBDI({\NLW_blk000002a4_DIBDI<31>_UNCONNECTED , \NLW_blk000002a4_DIBDI<30>_UNCONNECTED , \NLW_blk000002a4_DIBDI<29>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<28>_UNCONNECTED , \NLW_blk000002a4_DIBDI<27>_UNCONNECTED , \NLW_blk000002a4_DIBDI<26>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<25>_UNCONNECTED , \NLW_blk000002a4_DIBDI<24>_UNCONNECTED , \NLW_blk000002a4_DIBDI<23>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<22>_UNCONNECTED , \NLW_blk000002a4_DIBDI<21>_UNCONNECTED , \NLW_blk000002a4_DIBDI<20>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<19>_UNCONNECTED , \NLW_blk000002a4_DIBDI<18>_UNCONNECTED , \NLW_blk000002a4_DIBDI<17>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<16>_UNCONNECTED , \NLW_blk000002a4_DIBDI<15>_UNCONNECTED , \NLW_blk000002a4_DIBDI<14>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<13>_UNCONNECTED , \NLW_blk000002a4_DIBDI<12>_UNCONNECTED , \NLW_blk000002a4_DIBDI<11>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<10>_UNCONNECTED , \NLW_blk000002a4_DIBDI<9>_UNCONNECTED , \NLW_blk000002a4_DIBDI<8>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<7>_UNCONNECTED , \NLW_blk000002a4_DIBDI<6>_UNCONNECTED , \NLW_blk000002a4_DIBDI<5>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<4>_UNCONNECTED , \NLW_blk000002a4_DIBDI<3>_UNCONNECTED , \NLW_blk000002a4_DIBDI<2>_UNCONNECTED ,
\NLW_blk000002a4_DIBDI<1>_UNCONNECTED , \NLW_blk000002a4_DIBDI<0>_UNCONNECTED }),
.DIPADIP({\NLW_blk000002a4_DIPADIP<3>_UNCONNECTED , \NLW_blk000002a4_DIPADIP<2>_UNCONNECTED , \NLW_blk000002a4_DIPADIP<1>_UNCONNECTED ,
sig00000002}),
.DIPBDIP({\NLW_blk000002a4_DIPBDIP<3>_UNCONNECTED , \NLW_blk000002a4_DIPBDIP<2>_UNCONNECTED , \NLW_blk000002a4_DIPBDIP<1>_UNCONNECTED ,
\NLW_blk000002a4_DIPBDIP<0>_UNCONNECTED }),
.DOADO({\NLW_blk000002a4_DOADO<31>_UNCONNECTED , \NLW_blk000002a4_DOADO<30>_UNCONNECTED , \NLW_blk000002a4_DOADO<29>_UNCONNECTED ,
\NLW_blk000002a4_DOADO<28>_UNCONNECTED , \NLW_blk000002a4_DOADO<27>_UNCONNECTED , \NLW_blk000002a4_DOADO<26>_UNCONNECTED ,
\NLW_blk000002a4_DOADO<25>_UNCONNECTED , \NLW_blk000002a4_DOADO<24>_UNCONNECTED , \NLW_blk000002a4_DOADO<23>_UNCONNECTED ,
\NLW_blk000002a4_DOADO<22>_UNCONNECTED , \NLW_blk000002a4_DOADO<21>_UNCONNECTED , \NLW_blk000002a4_DOADO<20>_UNCONNECTED ,
\NLW_blk000002a4_DOADO<19>_UNCONNECTED , \NLW_blk000002a4_DOADO<18>_UNCONNECTED , \NLW_blk000002a4_DOADO<17>_UNCONNECTED ,
\NLW_blk000002a4_DOADO<16>_UNCONNECTED , \NLW_blk000002a4_DOADO<15>_UNCONNECTED , \NLW_blk000002a4_DOADO<14>_UNCONNECTED ,
\NLW_blk000002a4_DOADO<13>_UNCONNECTED , \NLW_blk000002a4_DOADO<12>_UNCONNECTED , \NLW_blk000002a4_DOADO<11>_UNCONNECTED ,
\NLW_blk000002a4_DOADO<10>_UNCONNECTED , \NLW_blk000002a4_DOADO<9>_UNCONNECTED , \NLW_blk000002a4_DOADO<8>_UNCONNECTED , sig00000174, sig00000173,
sig00000172, sig00000171, sig00000170, sig0000016f, sig0000016e, sig0000016d}),
.DOBDO({\NLW_blk000002a4_DOBDO<31>_UNCONNECTED , \NLW_blk000002a4_DOBDO<30>_UNCONNECTED , \NLW_blk000002a4_DOBDO<29>_UNCONNECTED ,
\NLW_blk000002a4_DOBDO<28>_UNCONNECTED , \NLW_blk000002a4_DOBDO<27>_UNCONNECTED , \NLW_blk000002a4_DOBDO<26>_UNCONNECTED ,
\NLW_blk000002a4_DOBDO<25>_UNCONNECTED , \NLW_blk000002a4_DOBDO<24>_UNCONNECTED , \NLW_blk000002a4_DOBDO<23>_UNCONNECTED ,
\NLW_blk000002a4_DOBDO<22>_UNCONNECTED , \NLW_blk000002a4_DOBDO<21>_UNCONNECTED , \NLW_blk000002a4_DOBDO<20>_UNCONNECTED ,
\NLW_blk000002a4_DOBDO<19>_UNCONNECTED , \NLW_blk000002a4_DOBDO<18>_UNCONNECTED , \NLW_blk000002a4_DOBDO<17>_UNCONNECTED ,
\NLW_blk000002a4_DOBDO<16>_UNCONNECTED , \NLW_blk000002a4_DOBDO<15>_UNCONNECTED , \NLW_blk000002a4_DOBDO<14>_UNCONNECTED ,
\NLW_blk000002a4_DOBDO<13>_UNCONNECTED , \NLW_blk000002a4_DOBDO<12>_UNCONNECTED , \NLW_blk000002a4_DOBDO<11>_UNCONNECTED ,
\NLW_blk000002a4_DOBDO<10>_UNCONNECTED , \NLW_blk000002a4_DOBDO<9>_UNCONNECTED , \NLW_blk000002a4_DOBDO<8>_UNCONNECTED , sig00000165, sig00000164,
sig00000163, sig00000162, sig00000161, sig00000160, sig0000015f, sig0000015e}),
.DOPADOP({\NLW_blk000002a4_DOPADOP<3>_UNCONNECTED , \NLW_blk000002a4_DOPADOP<2>_UNCONNECTED , \NLW_blk000002a4_DOPADOP<1>_UNCONNECTED ,
sig00000175}),
.DOPBDOP({\NLW_blk000002a4_DOPBDOP<3>_UNCONNECTED , \NLW_blk000002a4_DOPBDOP<2>_UNCONNECTED , \NLW_blk000002a4_DOPBDOP<1>_UNCONNECTED ,
sig00000166}),
.ECCPARITY({\NLW_blk000002a4_ECCPARITY<7>_UNCONNECTED , \NLW_blk000002a4_ECCPARITY<6>_UNCONNECTED , \NLW_blk000002a4_ECCPARITY<5>_UNCONNECTED ,
\NLW_blk000002a4_ECCPARITY<4>_UNCONNECTED , \NLW_blk000002a4_ECCPARITY<3>_UNCONNECTED , \NLW_blk000002a4_ECCPARITY<2>_UNCONNECTED ,
\NLW_blk000002a4_ECCPARITY<1>_UNCONNECTED , \NLW_blk000002a4_ECCPARITY<0>_UNCONNECTED }),
.RDADDRECC({\NLW_blk000002a4_RDADDRECC<8>_UNCONNECTED , \NLW_blk000002a4_RDADDRECC<7>_UNCONNECTED , \NLW_blk000002a4_RDADDRECC<6>_UNCONNECTED ,
\NLW_blk000002a4_RDADDRECC<5>_UNCONNECTED , \NLW_blk000002a4_RDADDRECC<4>_UNCONNECTED , \NLW_blk000002a4_RDADDRECC<3>_UNCONNECTED ,
\NLW_blk000002a4_RDADDRECC<2>_UNCONNECTED , \NLW_blk000002a4_RDADDRECC<1>_UNCONNECTED , \NLW_blk000002a4_RDADDRECC<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.WEBWE({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002})
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a5 (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(aclk),
.D(sig000001bc),
.Q(sig000001be),
.Q15(NLW_blk000002a5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a6 (
.C(aclk),
.CE(sig00000001),
.D(sig000001be),
.Q(sig0000012b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a7 (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(aclk),
.D(sig000001bb),
.Q(sig000001bf),
.Q15(NLW_blk000002a7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a8 (
.C(aclk),
.CE(sig00000001),
.D(sig000001bf),
.Q(sig000001ba)
);
XORCY \blk00000069/blk000000f9 (
.CI(\blk00000069/sig000002ae ),
.LI(\blk00000069/sig000002af ),
.O(sig00000009)
);
MUXCY \blk00000069/blk000000f8 (
.CI(\blk00000069/sig000002ae ),
.DI(sig000000b4),
.S(\blk00000069/sig000002af ),
.O(sig00000008)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000f7 (
.I0(sig000000b4),
.I1(sig00000002),
.O(\blk00000069/sig000002af )
);
XORCY \blk00000069/blk000000f6 (
.CI(\blk00000069/sig000002ac ),
.LI(\blk00000069/sig000002ad ),
.O(sig0000000a)
);
MUXCY \blk00000069/blk000000f5 (
.CI(\blk00000069/sig000002ac ),
.DI(sig000000b3),
.S(\blk00000069/sig000002ad ),
.O(\blk00000069/sig000002ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000f4 (
.I0(sig000000b3),
.I1(sig00000002),
.O(\blk00000069/sig000002ad )
);
XORCY \blk00000069/blk000000f3 (
.CI(\blk00000069/sig000002aa ),
.LI(\blk00000069/sig000002ab ),
.O(sig0000000b)
);
MUXCY \blk00000069/blk000000f2 (
.CI(\blk00000069/sig000002aa ),
.DI(sig000000b2),
.S(\blk00000069/sig000002ab ),
.O(\blk00000069/sig000002ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000f1 (
.I0(sig000000b2),
.I1(sig00000001),
.O(\blk00000069/sig000002ab )
);
XORCY \blk00000069/blk000000f0 (
.CI(\blk00000069/sig000002a8 ),
.LI(\blk00000069/sig000002a9 ),
.O(sig0000000c)
);
MUXCY \blk00000069/blk000000ef (
.CI(\blk00000069/sig000002a8 ),
.DI(sig000000b1),
.S(\blk00000069/sig000002a9 ),
.O(\blk00000069/sig000002aa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000ee (
.I0(sig000000b1),
.I1(sig00000001),
.O(\blk00000069/sig000002a9 )
);
XORCY \blk00000069/blk000000ed (
.CI(\blk00000069/sig000002a6 ),
.LI(\blk00000069/sig000002a7 ),
.O(sig0000000d)
);
MUXCY \blk00000069/blk000000ec (
.CI(\blk00000069/sig000002a6 ),
.DI(sig000000b0),
.S(\blk00000069/sig000002a7 ),
.O(\blk00000069/sig000002a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000eb (
.I0(sig000000b0),
.I1(sig00000001),
.O(\blk00000069/sig000002a7 )
);
XORCY \blk00000069/blk000000ea (
.CI(\blk00000069/sig000002a4 ),
.LI(\blk00000069/sig000002a5 ),
.O(sig0000000e)
);
MUXCY \blk00000069/blk000000e9 (
.CI(\blk00000069/sig000002a4 ),
.DI(sig000000af),
.S(\blk00000069/sig000002a5 ),
.O(\blk00000069/sig000002a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000e8 (
.I0(sig000000af),
.I1(sig00000002),
.O(\blk00000069/sig000002a5 )
);
XORCY \blk00000069/blk000000e7 (
.CI(\blk00000069/sig000002a2 ),
.LI(\blk00000069/sig000002a3 ),
.O(sig0000000f)
);
MUXCY \blk00000069/blk000000e6 (
.CI(\blk00000069/sig000002a2 ),
.DI(sig000000ae),
.S(\blk00000069/sig000002a3 ),
.O(\blk00000069/sig000002a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000e5 (
.I0(sig000000ae),
.I1(sig00000001),
.O(\blk00000069/sig000002a3 )
);
XORCY \blk00000069/blk000000e4 (
.CI(\blk00000069/sig000002a0 ),
.LI(\blk00000069/sig000002a1 ),
.O(sig00000010)
);
MUXCY \blk00000069/blk000000e3 (
.CI(\blk00000069/sig000002a0 ),
.DI(sig000000ad),
.S(\blk00000069/sig000002a1 ),
.O(\blk00000069/sig000002a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000e2 (
.I0(sig000000ad),
.I1(sig00000002),
.O(\blk00000069/sig000002a1 )
);
XORCY \blk00000069/blk000000e1 (
.CI(\blk00000069/sig0000029e ),
.LI(\blk00000069/sig0000029f ),
.O(sig00000011)
);
MUXCY \blk00000069/blk000000e0 (
.CI(\blk00000069/sig0000029e ),
.DI(sig000000ac),
.S(\blk00000069/sig0000029f ),
.O(\blk00000069/sig000002a0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000df (
.I0(sig000000ac),
.I1(sig00000001),
.O(\blk00000069/sig0000029f )
);
XORCY \blk00000069/blk000000de (
.CI(\blk00000069/sig0000029c ),
.LI(\blk00000069/sig0000029d ),
.O(sig00000012)
);
MUXCY \blk00000069/blk000000dd (
.CI(\blk00000069/sig0000029c ),
.DI(sig000000ab),
.S(\blk00000069/sig0000029d ),
.O(\blk00000069/sig0000029e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000dc (
.I0(sig000000ab),
.I1(sig00000002),
.O(\blk00000069/sig0000029d )
);
XORCY \blk00000069/blk000000db (
.CI(\blk00000069/sig0000029a ),
.LI(\blk00000069/sig0000029b ),
.O(sig00000013)
);
MUXCY \blk00000069/blk000000da (
.CI(\blk00000069/sig0000029a ),
.DI(sig000000aa),
.S(\blk00000069/sig0000029b ),
.O(\blk00000069/sig0000029c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000d9 (
.I0(sig000000aa),
.I1(sig00000002),
.O(\blk00000069/sig0000029b )
);
XORCY \blk00000069/blk000000d8 (
.CI(\blk00000069/sig00000298 ),
.LI(\blk00000069/sig00000299 ),
.O(sig00000014)
);
MUXCY \blk00000069/blk000000d7 (
.CI(\blk00000069/sig00000298 ),
.DI(sig000000a9),
.S(\blk00000069/sig00000299 ),
.O(\blk00000069/sig0000029a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000d6 (
.I0(sig000000a9),
.I1(sig00000002),
.O(\blk00000069/sig00000299 )
);
XORCY \blk00000069/blk000000d5 (
.CI(\blk00000069/sig00000296 ),
.LI(\blk00000069/sig00000297 ),
.O(sig00000015)
);
MUXCY \blk00000069/blk000000d4 (
.CI(\blk00000069/sig00000296 ),
.DI(sig000000a8),
.S(\blk00000069/sig00000297 ),
.O(\blk00000069/sig00000298 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000d3 (
.I0(sig000000a8),
.I1(sig00000002),
.O(\blk00000069/sig00000297 )
);
XORCY \blk00000069/blk000000d2 (
.CI(\blk00000069/sig00000294 ),
.LI(\blk00000069/sig00000295 ),
.O(sig00000016)
);
MUXCY \blk00000069/blk000000d1 (
.CI(\blk00000069/sig00000294 ),
.DI(sig000000a7),
.S(\blk00000069/sig00000295 ),
.O(\blk00000069/sig00000296 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000d0 (
.I0(sig000000a7),
.I1(sig00000002),
.O(\blk00000069/sig00000295 )
);
XORCY \blk00000069/blk000000cf (
.CI(\blk00000069/sig00000292 ),
.LI(\blk00000069/sig00000293 ),
.O(sig00000017)
);
MUXCY \blk00000069/blk000000ce (
.CI(\blk00000069/sig00000292 ),
.DI(sig000000a6),
.S(\blk00000069/sig00000293 ),
.O(\blk00000069/sig00000294 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000cd (
.I0(sig000000a6),
.I1(sig00000001),
.O(\blk00000069/sig00000293 )
);
XORCY \blk00000069/blk000000cc (
.CI(\blk00000069/sig00000290 ),
.LI(\blk00000069/sig00000291 ),
.O(sig00000018)
);
MUXCY \blk00000069/blk000000cb (
.CI(\blk00000069/sig00000290 ),
.DI(sig000000a5),
.S(\blk00000069/sig00000291 ),
.O(\blk00000069/sig00000292 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000ca (
.I0(sig000000a5),
.I1(sig00000001),
.O(\blk00000069/sig00000291 )
);
XORCY \blk00000069/blk000000c9 (
.CI(\blk00000069/sig0000028e ),
.LI(\blk00000069/sig0000028f ),
.O(sig00000019)
);
MUXCY \blk00000069/blk000000c8 (
.CI(\blk00000069/sig0000028e ),
.DI(sig000000a4),
.S(\blk00000069/sig0000028f ),
.O(\blk00000069/sig00000290 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000c7 (
.I0(sig000000a4),
.I1(sig00000001),
.O(\blk00000069/sig0000028f )
);
XORCY \blk00000069/blk000000c6 (
.CI(\blk00000069/sig0000028c ),
.LI(\blk00000069/sig0000028d ),
.O(sig0000001a)
);
MUXCY \blk00000069/blk000000c5 (
.CI(\blk00000069/sig0000028c ),
.DI(sig000000a3),
.S(\blk00000069/sig0000028d ),
.O(\blk00000069/sig0000028e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000c4 (
.I0(sig000000a3),
.I1(sig00000002),
.O(\blk00000069/sig0000028d )
);
XORCY \blk00000069/blk000000c3 (
.CI(\blk00000069/sig0000028a ),
.LI(\blk00000069/sig0000028b ),
.O(sig0000001b)
);
MUXCY \blk00000069/blk000000c2 (
.CI(\blk00000069/sig0000028a ),
.DI(sig000000a2),
.S(\blk00000069/sig0000028b ),
.O(\blk00000069/sig0000028c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000c1 (
.I0(sig000000a2),
.I1(sig00000001),
.O(\blk00000069/sig0000028b )
);
XORCY \blk00000069/blk000000c0 (
.CI(\blk00000069/sig00000288 ),
.LI(\blk00000069/sig00000289 ),
.O(sig0000001c)
);
MUXCY \blk00000069/blk000000bf (
.CI(\blk00000069/sig00000288 ),
.DI(sig000000a1),
.S(\blk00000069/sig00000289 ),
.O(\blk00000069/sig0000028a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000be (
.I0(sig000000a1),
.I1(sig00000002),
.O(\blk00000069/sig00000289 )
);
XORCY \blk00000069/blk000000bd (
.CI(\blk00000069/sig00000286 ),
.LI(\blk00000069/sig00000287 ),
.O(sig0000001d)
);
MUXCY \blk00000069/blk000000bc (
.CI(\blk00000069/sig00000286 ),
.DI(sig000000a0),
.S(\blk00000069/sig00000287 ),
.O(\blk00000069/sig00000288 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000bb (
.I0(sig00000001),
.I1(sig000000a0),
.O(\blk00000069/sig00000287 )
);
XORCY \blk00000069/blk000000ba (
.CI(\blk00000069/sig00000284 ),
.LI(\blk00000069/sig00000285 ),
.O(sig0000001e)
);
MUXCY \blk00000069/blk000000b9 (
.CI(\blk00000069/sig00000284 ),
.DI(sig0000009f),
.S(\blk00000069/sig00000285 ),
.O(\blk00000069/sig00000286 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000b8 (
.I0(sig00000002),
.I1(sig0000009f),
.O(\blk00000069/sig00000285 )
);
XORCY \blk00000069/blk000000b7 (
.CI(\blk00000069/sig00000282 ),
.LI(\blk00000069/sig00000283 ),
.O(sig0000001f)
);
MUXCY \blk00000069/blk000000b6 (
.CI(\blk00000069/sig00000282 ),
.DI(sig0000009e),
.S(\blk00000069/sig00000283 ),
.O(\blk00000069/sig00000284 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000b5 (
.I0(sig00000002),
.I1(sig0000009e),
.O(\blk00000069/sig00000283 )
);
XORCY \blk00000069/blk000000b4 (
.CI(\blk00000069/sig00000280 ),
.LI(\blk00000069/sig00000281 ),
.O(sig00000020)
);
MUXCY \blk00000069/blk000000b3 (
.CI(\blk00000069/sig00000280 ),
.DI(sig0000009d),
.S(\blk00000069/sig00000281 ),
.O(\blk00000069/sig00000282 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000b2 (
.I0(sig00000002),
.I1(sig0000009d),
.O(\blk00000069/sig00000281 )
);
XORCY \blk00000069/blk000000b1 (
.CI(\blk00000069/sig0000027e ),
.LI(\blk00000069/sig0000027f ),
.O(sig00000021)
);
MUXCY \blk00000069/blk000000b0 (
.CI(\blk00000069/sig0000027e ),
.DI(sig0000009c),
.S(\blk00000069/sig0000027f ),
.O(\blk00000069/sig00000280 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000af (
.I0(sig00000002),
.I1(sig0000009c),
.O(\blk00000069/sig0000027f )
);
XORCY \blk00000069/blk000000ae (
.CI(\blk00000069/sig0000027c ),
.LI(\blk00000069/sig0000027d ),
.O(sig00000022)
);
MUXCY \blk00000069/blk000000ad (
.CI(\blk00000069/sig0000027c ),
.DI(sig0000009b),
.S(\blk00000069/sig0000027d ),
.O(\blk00000069/sig0000027e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000ac (
.I0(sig00000002),
.I1(sig0000009b),
.O(\blk00000069/sig0000027d )
);
XORCY \blk00000069/blk000000ab (
.CI(\blk00000069/sig0000027a ),
.LI(\blk00000069/sig0000027b ),
.O(sig00000023)
);
MUXCY \blk00000069/blk000000aa (
.CI(\blk00000069/sig0000027a ),
.DI(sig0000009a),
.S(\blk00000069/sig0000027b ),
.O(\blk00000069/sig0000027c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000a9 (
.I0(sig00000001),
.I1(sig0000009a),
.O(\blk00000069/sig0000027b )
);
XORCY \blk00000069/blk000000a8 (
.CI(\blk00000069/sig00000278 ),
.LI(\blk00000069/sig00000279 ),
.O(sig00000024)
);
MUXCY \blk00000069/blk000000a7 (
.CI(\blk00000069/sig00000278 ),
.DI(sig00000099),
.S(\blk00000069/sig00000279 ),
.O(\blk00000069/sig0000027a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000a6 (
.I0(sig00000001),
.I1(sig00000099),
.O(\blk00000069/sig00000279 )
);
XORCY \blk00000069/blk000000a5 (
.CI(\blk00000069/sig00000276 ),
.LI(\blk00000069/sig00000277 ),
.O(sig00000025)
);
MUXCY \blk00000069/blk000000a4 (
.CI(\blk00000069/sig00000276 ),
.DI(sig00000098),
.S(\blk00000069/sig00000277 ),
.O(\blk00000069/sig00000278 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000a3 (
.I0(sig00000001),
.I1(sig00000098),
.O(\blk00000069/sig00000277 )
);
XORCY \blk00000069/blk000000a2 (
.CI(\blk00000069/sig00000274 ),
.LI(\blk00000069/sig00000275 ),
.O(sig00000026)
);
MUXCY \blk00000069/blk000000a1 (
.CI(\blk00000069/sig00000274 ),
.DI(sig00000097),
.S(\blk00000069/sig00000275 ),
.O(\blk00000069/sig00000276 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk000000a0 (
.I0(sig00000002),
.I1(sig00000097),
.O(\blk00000069/sig00000275 )
);
XORCY \blk00000069/blk0000009f (
.CI(\blk00000069/sig00000272 ),
.LI(\blk00000069/sig00000273 ),
.O(sig00000027)
);
MUXCY \blk00000069/blk0000009e (
.CI(\blk00000069/sig00000272 ),
.DI(sig00000096),
.S(\blk00000069/sig00000273 ),
.O(\blk00000069/sig00000274 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk0000009d (
.I0(sig00000001),
.I1(sig00000096),
.O(\blk00000069/sig00000273 )
);
XORCY \blk00000069/blk0000009c (
.CI(\blk00000069/sig00000270 ),
.LI(\blk00000069/sig00000271 ),
.O(sig00000028)
);
MUXCY \blk00000069/blk0000009b (
.CI(\blk00000069/sig00000270 ),
.DI(sig00000095),
.S(\blk00000069/sig00000271 ),
.O(\blk00000069/sig00000272 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk0000009a (
.I0(sig00000002),
.I1(sig00000095),
.O(\blk00000069/sig00000271 )
);
XORCY \blk00000069/blk00000099 (
.CI(\blk00000069/sig0000026e ),
.LI(\blk00000069/sig0000026f ),
.O(sig00000029)
);
MUXCY \blk00000069/blk00000098 (
.CI(\blk00000069/sig0000026e ),
.DI(sig00000094),
.S(\blk00000069/sig0000026f ),
.O(\blk00000069/sig00000270 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000097 (
.I0(sig00000001),
.I1(sig00000094),
.O(\blk00000069/sig0000026f )
);
XORCY \blk00000069/blk00000096 (
.CI(\blk00000069/sig0000026c ),
.LI(\blk00000069/sig0000026d ),
.O(sig0000002a)
);
MUXCY \blk00000069/blk00000095 (
.CI(\blk00000069/sig0000026c ),
.DI(sig00000093),
.S(\blk00000069/sig0000026d ),
.O(\blk00000069/sig0000026e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000094 (
.I0(sig00000002),
.I1(sig00000093),
.O(\blk00000069/sig0000026d )
);
XORCY \blk00000069/blk00000093 (
.CI(\blk00000069/sig0000026a ),
.LI(\blk00000069/sig0000026b ),
.O(sig0000002b)
);
MUXCY \blk00000069/blk00000092 (
.CI(\blk00000069/sig0000026a ),
.DI(sig00000092),
.S(\blk00000069/sig0000026b ),
.O(\blk00000069/sig0000026c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000091 (
.I0(sig00000002),
.I1(sig00000092),
.O(\blk00000069/sig0000026b )
);
XORCY \blk00000069/blk00000090 (
.CI(\blk00000069/sig00000268 ),
.LI(\blk00000069/sig00000269 ),
.O(sig0000002c)
);
MUXCY \blk00000069/blk0000008f (
.CI(\blk00000069/sig00000268 ),
.DI(sig00000091),
.S(\blk00000069/sig00000269 ),
.O(\blk00000069/sig0000026a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk0000008e (
.I0(sig00000002),
.I1(sig00000091),
.O(\blk00000069/sig00000269 )
);
XORCY \blk00000069/blk0000008d (
.CI(\blk00000069/sig00000266 ),
.LI(\blk00000069/sig00000267 ),
.O(sig0000002d)
);
MUXCY \blk00000069/blk0000008c (
.CI(\blk00000069/sig00000266 ),
.DI(sig00000090),
.S(\blk00000069/sig00000267 ),
.O(\blk00000069/sig00000268 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk0000008b (
.I0(sig00000002),
.I1(sig00000090),
.O(\blk00000069/sig00000267 )
);
XORCY \blk00000069/blk0000008a (
.CI(\blk00000069/sig00000264 ),
.LI(\blk00000069/sig00000265 ),
.O(sig0000002e)
);
MUXCY \blk00000069/blk00000089 (
.CI(\blk00000069/sig00000264 ),
.DI(sig0000008f),
.S(\blk00000069/sig00000265 ),
.O(\blk00000069/sig00000266 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000088 (
.I0(sig00000002),
.I1(sig0000008f),
.O(\blk00000069/sig00000265 )
);
XORCY \blk00000069/blk00000087 (
.CI(\blk00000069/sig00000262 ),
.LI(\blk00000069/sig00000263 ),
.O(sig0000002f)
);
MUXCY \blk00000069/blk00000086 (
.CI(\blk00000069/sig00000262 ),
.DI(sig0000008e),
.S(\blk00000069/sig00000263 ),
.O(\blk00000069/sig00000264 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000085 (
.I0(sig00000001),
.I1(sig0000008e),
.O(\blk00000069/sig00000263 )
);
XORCY \blk00000069/blk00000084 (
.CI(\blk00000069/sig00000260 ),
.LI(\blk00000069/sig00000261 ),
.O(sig00000030)
);
MUXCY \blk00000069/blk00000083 (
.CI(\blk00000069/sig00000260 ),
.DI(sig0000008d),
.S(\blk00000069/sig00000261 ),
.O(\blk00000069/sig00000262 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000082 (
.I0(sig00000001),
.I1(sig0000008d),
.O(\blk00000069/sig00000261 )
);
XORCY \blk00000069/blk00000081 (
.CI(\blk00000069/sig0000025e ),
.LI(\blk00000069/sig0000025f ),
.O(sig00000031)
);
MUXCY \blk00000069/blk00000080 (
.CI(\blk00000069/sig0000025e ),
.DI(sig0000008c),
.S(\blk00000069/sig0000025f ),
.O(\blk00000069/sig00000260 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk0000007f (
.I0(sig00000001),
.I1(sig0000008c),
.O(\blk00000069/sig0000025f )
);
XORCY \blk00000069/blk0000007e (
.CI(\blk00000069/sig0000025c ),
.LI(\blk00000069/sig0000025d ),
.O(sig00000032)
);
MUXCY \blk00000069/blk0000007d (
.CI(\blk00000069/sig0000025c ),
.DI(sig0000008b),
.S(\blk00000069/sig0000025d ),
.O(\blk00000069/sig0000025e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk0000007c (
.I0(sig00000002),
.I1(sig0000008b),
.O(\blk00000069/sig0000025d )
);
XORCY \blk00000069/blk0000007b (
.CI(\blk00000069/sig0000025a ),
.LI(\blk00000069/sig0000025b ),
.O(sig00000033)
);
MUXCY \blk00000069/blk0000007a (
.CI(\blk00000069/sig0000025a ),
.DI(sig0000008a),
.S(\blk00000069/sig0000025b ),
.O(\blk00000069/sig0000025c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000079 (
.I0(sig00000001),
.I1(sig0000008a),
.O(\blk00000069/sig0000025b )
);
XORCY \blk00000069/blk00000078 (
.CI(\blk00000069/sig00000258 ),
.LI(\blk00000069/sig00000259 ),
.O(sig00000034)
);
MUXCY \blk00000069/blk00000077 (
.CI(\blk00000069/sig00000258 ),
.DI(sig00000089),
.S(\blk00000069/sig00000259 ),
.O(\blk00000069/sig0000025a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000076 (
.I0(sig00000002),
.I1(sig00000089),
.O(\blk00000069/sig00000259 )
);
XORCY \blk00000069/blk00000075 (
.CI(\blk00000069/sig00000256 ),
.LI(\blk00000069/sig00000257 ),
.O(sig00000035)
);
MUXCY \blk00000069/blk00000074 (
.CI(\blk00000069/sig00000256 ),
.DI(sig00000088),
.S(\blk00000069/sig00000257 ),
.O(\blk00000069/sig00000258 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000073 (
.I0(sig00000001),
.I1(sig00000088),
.O(\blk00000069/sig00000257 )
);
XORCY \blk00000069/blk00000072 (
.CI(\blk00000069/sig00000254 ),
.LI(\blk00000069/sig00000255 ),
.O(sig00000036)
);
MUXCY \blk00000069/blk00000071 (
.CI(\blk00000069/sig00000254 ),
.DI(sig00000087),
.S(\blk00000069/sig00000255 ),
.O(\blk00000069/sig00000256 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk00000070 (
.I0(sig00000002),
.I1(sig00000087),
.O(\blk00000069/sig00000255 )
);
XORCY \blk00000069/blk0000006f (
.CI(\blk00000069/sig00000252 ),
.LI(\blk00000069/sig00000253 ),
.O(sig00000037)
);
MUXCY \blk00000069/blk0000006e (
.CI(\blk00000069/sig00000252 ),
.DI(sig00000086),
.S(\blk00000069/sig00000253 ),
.O(\blk00000069/sig00000254 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk0000006d (
.I0(sig00000002),
.I1(sig00000086),
.O(\blk00000069/sig00000253 )
);
XORCY \blk00000069/blk0000006c (
.CI(sig00000002),
.LI(\blk00000069/sig00000251 ),
.O(sig00000038)
);
MUXCY \blk00000069/blk0000006b (
.CI(sig00000002),
.DI(sig00000085),
.S(\blk00000069/sig00000251 ),
.O(\blk00000069/sig00000252 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000069/blk0000006a (
.I0(sig00000002),
.I1(sig00000085),
.O(\blk00000069/sig00000251 )
);
XORCY \blk000000fa/blk0000018a (
.CI(\blk000000fa/sig0000039f ),
.LI(\blk000000fa/sig000003a0 ),
.O(sig00000069)
);
MUXCY \blk000000fa/blk00000189 (
.CI(\blk000000fa/sig0000039f ),
.DI(sig000000b4),
.S(\blk000000fa/sig000003a0 ),
.O(sig0000006a)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000188 (
.I0(sig000000b4),
.I1(sig00000084),
.O(\blk000000fa/sig000003a0 )
);
XORCY \blk000000fa/blk00000187 (
.CI(\blk000000fa/sig0000039d ),
.LI(\blk000000fa/sig0000039e ),
.O(sig00000068)
);
MUXCY \blk000000fa/blk00000186 (
.CI(\blk000000fa/sig0000039d ),
.DI(sig000000b3),
.S(\blk000000fa/sig0000039e ),
.O(\blk000000fa/sig0000039f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000185 (
.I0(sig000000b3),
.I1(sig00000084),
.O(\blk000000fa/sig0000039e )
);
XORCY \blk000000fa/blk00000184 (
.CI(\blk000000fa/sig0000039b ),
.LI(\blk000000fa/sig0000039c ),
.O(sig00000067)
);
MUXCY \blk000000fa/blk00000183 (
.CI(\blk000000fa/sig0000039b ),
.DI(sig000000b2),
.S(\blk000000fa/sig0000039c ),
.O(\blk000000fa/sig0000039d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000182 (
.I0(sig000000b2),
.I1(sig00000084),
.O(\blk000000fa/sig0000039c )
);
XORCY \blk000000fa/blk00000181 (
.CI(\blk000000fa/sig00000399 ),
.LI(\blk000000fa/sig0000039a ),
.O(sig00000066)
);
MUXCY \blk000000fa/blk00000180 (
.CI(\blk000000fa/sig00000399 ),
.DI(sig000000b1),
.S(\blk000000fa/sig0000039a ),
.O(\blk000000fa/sig0000039b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000017f (
.I0(sig000000b1),
.I1(sig00000084),
.O(\blk000000fa/sig0000039a )
);
XORCY \blk000000fa/blk0000017e (
.CI(\blk000000fa/sig00000397 ),
.LI(\blk000000fa/sig00000398 ),
.O(sig00000065)
);
MUXCY \blk000000fa/blk0000017d (
.CI(\blk000000fa/sig00000397 ),
.DI(sig000000b0),
.S(\blk000000fa/sig00000398 ),
.O(\blk000000fa/sig00000399 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000017c (
.I0(sig000000b0),
.I1(sig00000084),
.O(\blk000000fa/sig00000398 )
);
XORCY \blk000000fa/blk0000017b (
.CI(\blk000000fa/sig00000395 ),
.LI(\blk000000fa/sig00000396 ),
.O(sig00000064)
);
MUXCY \blk000000fa/blk0000017a (
.CI(\blk000000fa/sig00000395 ),
.DI(sig000000af),
.S(\blk000000fa/sig00000396 ),
.O(\blk000000fa/sig00000397 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000179 (
.I0(sig000000af),
.I1(sig00000084),
.O(\blk000000fa/sig00000396 )
);
XORCY \blk000000fa/blk00000178 (
.CI(\blk000000fa/sig00000393 ),
.LI(\blk000000fa/sig00000394 ),
.O(sig00000063)
);
MUXCY \blk000000fa/blk00000177 (
.CI(\blk000000fa/sig00000393 ),
.DI(sig000000ae),
.S(\blk000000fa/sig00000394 ),
.O(\blk000000fa/sig00000395 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000176 (
.I0(sig000000ae),
.I1(sig00000084),
.O(\blk000000fa/sig00000394 )
);
XORCY \blk000000fa/blk00000175 (
.CI(\blk000000fa/sig00000391 ),
.LI(\blk000000fa/sig00000392 ),
.O(sig00000062)
);
MUXCY \blk000000fa/blk00000174 (
.CI(\blk000000fa/sig00000391 ),
.DI(sig000000ad),
.S(\blk000000fa/sig00000392 ),
.O(\blk000000fa/sig00000393 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000173 (
.I0(sig000000ad),
.I1(sig00000084),
.O(\blk000000fa/sig00000392 )
);
XORCY \blk000000fa/blk00000172 (
.CI(\blk000000fa/sig0000038f ),
.LI(\blk000000fa/sig00000390 ),
.O(sig00000061)
);
MUXCY \blk000000fa/blk00000171 (
.CI(\blk000000fa/sig0000038f ),
.DI(sig000000ac),
.S(\blk000000fa/sig00000390 ),
.O(\blk000000fa/sig00000391 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000170 (
.I0(sig000000ac),
.I1(sig00000084),
.O(\blk000000fa/sig00000390 )
);
XORCY \blk000000fa/blk0000016f (
.CI(\blk000000fa/sig0000038d ),
.LI(\blk000000fa/sig0000038e ),
.O(sig00000060)
);
MUXCY \blk000000fa/blk0000016e (
.CI(\blk000000fa/sig0000038d ),
.DI(sig000000ab),
.S(\blk000000fa/sig0000038e ),
.O(\blk000000fa/sig0000038f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000016d (
.I0(sig000000ab),
.I1(sig00000084),
.O(\blk000000fa/sig0000038e )
);
XORCY \blk000000fa/blk0000016c (
.CI(\blk000000fa/sig0000038b ),
.LI(\blk000000fa/sig0000038c ),
.O(sig0000005f)
);
MUXCY \blk000000fa/blk0000016b (
.CI(\blk000000fa/sig0000038b ),
.DI(sig000000aa),
.S(\blk000000fa/sig0000038c ),
.O(\blk000000fa/sig0000038d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000016a (
.I0(sig000000aa),
.I1(sig00000084),
.O(\blk000000fa/sig0000038c )
);
XORCY \blk000000fa/blk00000169 (
.CI(\blk000000fa/sig00000389 ),
.LI(\blk000000fa/sig0000038a ),
.O(sig0000005e)
);
MUXCY \blk000000fa/blk00000168 (
.CI(\blk000000fa/sig00000389 ),
.DI(sig000000a9),
.S(\blk000000fa/sig0000038a ),
.O(\blk000000fa/sig0000038b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000167 (
.I0(sig000000a9),
.I1(sig00000084),
.O(\blk000000fa/sig0000038a )
);
XORCY \blk000000fa/blk00000166 (
.CI(\blk000000fa/sig00000387 ),
.LI(\blk000000fa/sig00000388 ),
.O(sig0000005d)
);
MUXCY \blk000000fa/blk00000165 (
.CI(\blk000000fa/sig00000387 ),
.DI(sig000000a8),
.S(\blk000000fa/sig00000388 ),
.O(\blk000000fa/sig00000389 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000164 (
.I0(sig000000a8),
.I1(sig00000084),
.O(\blk000000fa/sig00000388 )
);
XORCY \blk000000fa/blk00000163 (
.CI(\blk000000fa/sig00000385 ),
.LI(\blk000000fa/sig00000386 ),
.O(sig0000005c)
);
MUXCY \blk000000fa/blk00000162 (
.CI(\blk000000fa/sig00000385 ),
.DI(sig000000a7),
.S(\blk000000fa/sig00000386 ),
.O(\blk000000fa/sig00000387 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000161 (
.I0(sig000000a7),
.I1(sig00000084),
.O(\blk000000fa/sig00000386 )
);
XORCY \blk000000fa/blk00000160 (
.CI(\blk000000fa/sig00000383 ),
.LI(\blk000000fa/sig00000384 ),
.O(sig0000005b)
);
MUXCY \blk000000fa/blk0000015f (
.CI(\blk000000fa/sig00000383 ),
.DI(sig000000a6),
.S(\blk000000fa/sig00000384 ),
.O(\blk000000fa/sig00000385 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000015e (
.I0(sig000000a6),
.I1(sig00000083),
.O(\blk000000fa/sig00000384 )
);
XORCY \blk000000fa/blk0000015d (
.CI(\blk000000fa/sig00000381 ),
.LI(\blk000000fa/sig00000382 ),
.O(sig0000005a)
);
MUXCY \blk000000fa/blk0000015c (
.CI(\blk000000fa/sig00000381 ),
.DI(sig000000a5),
.S(\blk000000fa/sig00000382 ),
.O(\blk000000fa/sig00000383 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000015b (
.I0(sig000000a5),
.I1(sig00000082),
.O(\blk000000fa/sig00000382 )
);
XORCY \blk000000fa/blk0000015a (
.CI(\blk000000fa/sig0000037f ),
.LI(\blk000000fa/sig00000380 ),
.O(sig00000059)
);
MUXCY \blk000000fa/blk00000159 (
.CI(\blk000000fa/sig0000037f ),
.DI(sig000000a4),
.S(\blk000000fa/sig00000380 ),
.O(\blk000000fa/sig00000381 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000158 (
.I0(sig000000a4),
.I1(sig00000081),
.O(\blk000000fa/sig00000380 )
);
XORCY \blk000000fa/blk00000157 (
.CI(\blk000000fa/sig0000037d ),
.LI(\blk000000fa/sig0000037e ),
.O(sig00000058)
);
MUXCY \blk000000fa/blk00000156 (
.CI(\blk000000fa/sig0000037d ),
.DI(sig000000a3),
.S(\blk000000fa/sig0000037e ),
.O(\blk000000fa/sig0000037f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000155 (
.I0(sig000000a3),
.I1(sig00000080),
.O(\blk000000fa/sig0000037e )
);
XORCY \blk000000fa/blk00000154 (
.CI(\blk000000fa/sig0000037b ),
.LI(\blk000000fa/sig0000037c ),
.O(sig00000057)
);
MUXCY \blk000000fa/blk00000153 (
.CI(\blk000000fa/sig0000037b ),
.DI(sig000000a2),
.S(\blk000000fa/sig0000037c ),
.O(\blk000000fa/sig0000037d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000152 (
.I0(sig000000a2),
.I1(sig0000007f),
.O(\blk000000fa/sig0000037c )
);
XORCY \blk000000fa/blk00000151 (
.CI(\blk000000fa/sig00000379 ),
.LI(\blk000000fa/sig0000037a ),
.O(sig00000056)
);
MUXCY \blk000000fa/blk00000150 (
.CI(\blk000000fa/sig00000379 ),
.DI(sig000000a1),
.S(\blk000000fa/sig0000037a ),
.O(\blk000000fa/sig0000037b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000014f (
.I0(sig000000a1),
.I1(sig0000007e),
.O(\blk000000fa/sig0000037a )
);
XORCY \blk000000fa/blk0000014e (
.CI(\blk000000fa/sig00000377 ),
.LI(\blk000000fa/sig00000378 ),
.O(sig00000055)
);
MUXCY \blk000000fa/blk0000014d (
.CI(\blk000000fa/sig00000377 ),
.DI(sig000000a0),
.S(\blk000000fa/sig00000378 ),
.O(\blk000000fa/sig00000379 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000014c (
.I0(sig000000a0),
.I1(sig0000007d),
.O(\blk000000fa/sig00000378 )
);
XORCY \blk000000fa/blk0000014b (
.CI(\blk000000fa/sig00000375 ),
.LI(\blk000000fa/sig00000376 ),
.O(sig00000054)
);
MUXCY \blk000000fa/blk0000014a (
.CI(\blk000000fa/sig00000375 ),
.DI(sig0000009f),
.S(\blk000000fa/sig00000376 ),
.O(\blk000000fa/sig00000377 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000149 (
.I0(sig0000009f),
.I1(sig0000007c),
.O(\blk000000fa/sig00000376 )
);
XORCY \blk000000fa/blk00000148 (
.CI(\blk000000fa/sig00000373 ),
.LI(\blk000000fa/sig00000374 ),
.O(sig00000053)
);
MUXCY \blk000000fa/blk00000147 (
.CI(\blk000000fa/sig00000373 ),
.DI(sig0000009e),
.S(\blk000000fa/sig00000374 ),
.O(\blk000000fa/sig00000375 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000146 (
.I0(sig0000009e),
.I1(sig0000007b),
.O(\blk000000fa/sig00000374 )
);
XORCY \blk000000fa/blk00000145 (
.CI(\blk000000fa/sig00000371 ),
.LI(\blk000000fa/sig00000372 ),
.O(sig00000052)
);
MUXCY \blk000000fa/blk00000144 (
.CI(\blk000000fa/sig00000371 ),
.DI(sig0000009d),
.S(\blk000000fa/sig00000372 ),
.O(\blk000000fa/sig00000373 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000143 (
.I0(sig00000002),
.I1(sig0000009d),
.O(\blk000000fa/sig00000372 )
);
XORCY \blk000000fa/blk00000142 (
.CI(\blk000000fa/sig0000036f ),
.LI(\blk000000fa/sig00000370 ),
.O(sig00000051)
);
MUXCY \blk000000fa/blk00000141 (
.CI(\blk000000fa/sig0000036f ),
.DI(sig0000009c),
.S(\blk000000fa/sig00000370 ),
.O(\blk000000fa/sig00000371 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000140 (
.I0(sig00000002),
.I1(sig0000009c),
.O(\blk000000fa/sig00000370 )
);
XORCY \blk000000fa/blk0000013f (
.CI(\blk000000fa/sig0000036d ),
.LI(\blk000000fa/sig0000036e ),
.O(sig00000050)
);
MUXCY \blk000000fa/blk0000013e (
.CI(\blk000000fa/sig0000036d ),
.DI(sig0000009b),
.S(\blk000000fa/sig0000036e ),
.O(\blk000000fa/sig0000036f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000013d (
.I0(sig00000002),
.I1(sig0000009b),
.O(\blk000000fa/sig0000036e )
);
XORCY \blk000000fa/blk0000013c (
.CI(\blk000000fa/sig0000036b ),
.LI(\blk000000fa/sig0000036c ),
.O(sig0000004f)
);
MUXCY \blk000000fa/blk0000013b (
.CI(\blk000000fa/sig0000036b ),
.DI(sig0000009a),
.S(\blk000000fa/sig0000036c ),
.O(\blk000000fa/sig0000036d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000013a (
.I0(sig00000002),
.I1(sig0000009a),
.O(\blk000000fa/sig0000036c )
);
XORCY \blk000000fa/blk00000139 (
.CI(\blk000000fa/sig00000369 ),
.LI(\blk000000fa/sig0000036a ),
.O(sig0000004e)
);
MUXCY \blk000000fa/blk00000138 (
.CI(\blk000000fa/sig00000369 ),
.DI(sig00000099),
.S(\blk000000fa/sig0000036a ),
.O(\blk000000fa/sig0000036b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000137 (
.I0(sig00000002),
.I1(sig00000099),
.O(\blk000000fa/sig0000036a )
);
XORCY \blk000000fa/blk00000136 (
.CI(\blk000000fa/sig00000367 ),
.LI(\blk000000fa/sig00000368 ),
.O(sig0000004d)
);
MUXCY \blk000000fa/blk00000135 (
.CI(\blk000000fa/sig00000367 ),
.DI(sig00000098),
.S(\blk000000fa/sig00000368 ),
.O(\blk000000fa/sig00000369 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000134 (
.I0(sig00000002),
.I1(sig00000098),
.O(\blk000000fa/sig00000368 )
);
XORCY \blk000000fa/blk00000133 (
.CI(\blk000000fa/sig00000365 ),
.LI(\blk000000fa/sig00000366 ),
.O(sig0000004c)
);
MUXCY \blk000000fa/blk00000132 (
.CI(\blk000000fa/sig00000365 ),
.DI(sig00000097),
.S(\blk000000fa/sig00000366 ),
.O(\blk000000fa/sig00000367 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000131 (
.I0(sig00000002),
.I1(sig00000097),
.O(\blk000000fa/sig00000366 )
);
XORCY \blk000000fa/blk00000130 (
.CI(\blk000000fa/sig00000363 ),
.LI(\blk000000fa/sig00000364 ),
.O(sig0000004b)
);
MUXCY \blk000000fa/blk0000012f (
.CI(\blk000000fa/sig00000363 ),
.DI(sig00000096),
.S(\blk000000fa/sig00000364 ),
.O(\blk000000fa/sig00000365 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000012e (
.I0(sig00000002),
.I1(sig00000096),
.O(\blk000000fa/sig00000364 )
);
XORCY \blk000000fa/blk0000012d (
.CI(\blk000000fa/sig00000361 ),
.LI(\blk000000fa/sig00000362 ),
.O(sig0000004a)
);
MUXCY \blk000000fa/blk0000012c (
.CI(\blk000000fa/sig00000361 ),
.DI(sig00000095),
.S(\blk000000fa/sig00000362 ),
.O(\blk000000fa/sig00000363 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000012b (
.I0(sig00000002),
.I1(sig00000095),
.O(\blk000000fa/sig00000362 )
);
XORCY \blk000000fa/blk0000012a (
.CI(\blk000000fa/sig0000035f ),
.LI(\blk000000fa/sig00000360 ),
.O(sig00000049)
);
MUXCY \blk000000fa/blk00000129 (
.CI(\blk000000fa/sig0000035f ),
.DI(sig00000094),
.S(\blk000000fa/sig00000360 ),
.O(\blk000000fa/sig00000361 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000128 (
.I0(sig00000002),
.I1(sig00000094),
.O(\blk000000fa/sig00000360 )
);
XORCY \blk000000fa/blk00000127 (
.CI(\blk000000fa/sig0000035d ),
.LI(\blk000000fa/sig0000035e ),
.O(sig00000048)
);
MUXCY \blk000000fa/blk00000126 (
.CI(\blk000000fa/sig0000035d ),
.DI(sig00000093),
.S(\blk000000fa/sig0000035e ),
.O(\blk000000fa/sig0000035f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000125 (
.I0(sig00000002),
.I1(sig00000093),
.O(\blk000000fa/sig0000035e )
);
XORCY \blk000000fa/blk00000124 (
.CI(\blk000000fa/sig0000035b ),
.LI(\blk000000fa/sig0000035c ),
.O(sig00000047)
);
MUXCY \blk000000fa/blk00000123 (
.CI(\blk000000fa/sig0000035b ),
.DI(sig00000092),
.S(\blk000000fa/sig0000035c ),
.O(\blk000000fa/sig0000035d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000122 (
.I0(sig00000002),
.I1(sig00000092),
.O(\blk000000fa/sig0000035c )
);
XORCY \blk000000fa/blk00000121 (
.CI(\blk000000fa/sig00000359 ),
.LI(\blk000000fa/sig0000035a ),
.O(sig00000046)
);
MUXCY \blk000000fa/blk00000120 (
.CI(\blk000000fa/sig00000359 ),
.DI(sig00000091),
.S(\blk000000fa/sig0000035a ),
.O(\blk000000fa/sig0000035b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000011f (
.I0(sig00000002),
.I1(sig00000091),
.O(\blk000000fa/sig0000035a )
);
XORCY \blk000000fa/blk0000011e (
.CI(\blk000000fa/sig00000357 ),
.LI(\blk000000fa/sig00000358 ),
.O(sig00000045)
);
MUXCY \blk000000fa/blk0000011d (
.CI(\blk000000fa/sig00000357 ),
.DI(sig00000090),
.S(\blk000000fa/sig00000358 ),
.O(\blk000000fa/sig00000359 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000011c (
.I0(sig00000002),
.I1(sig00000090),
.O(\blk000000fa/sig00000358 )
);
XORCY \blk000000fa/blk0000011b (
.CI(\blk000000fa/sig00000355 ),
.LI(\blk000000fa/sig00000356 ),
.O(sig00000044)
);
MUXCY \blk000000fa/blk0000011a (
.CI(\blk000000fa/sig00000355 ),
.DI(sig0000008f),
.S(\blk000000fa/sig00000356 ),
.O(\blk000000fa/sig00000357 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000119 (
.I0(sig00000002),
.I1(sig0000008f),
.O(\blk000000fa/sig00000356 )
);
XORCY \blk000000fa/blk00000118 (
.CI(\blk000000fa/sig00000353 ),
.LI(\blk000000fa/sig00000354 ),
.O(sig00000043)
);
MUXCY \blk000000fa/blk00000117 (
.CI(\blk000000fa/sig00000353 ),
.DI(sig0000008e),
.S(\blk000000fa/sig00000354 ),
.O(\blk000000fa/sig00000355 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000116 (
.I0(sig00000002),
.I1(sig0000008e),
.O(\blk000000fa/sig00000354 )
);
XORCY \blk000000fa/blk00000115 (
.CI(\blk000000fa/sig00000351 ),
.LI(\blk000000fa/sig00000352 ),
.O(sig00000042)
);
MUXCY \blk000000fa/blk00000114 (
.CI(\blk000000fa/sig00000351 ),
.DI(sig0000008d),
.S(\blk000000fa/sig00000352 ),
.O(\blk000000fa/sig00000353 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000113 (
.I0(sig00000002),
.I1(sig0000008d),
.O(\blk000000fa/sig00000352 )
);
XORCY \blk000000fa/blk00000112 (
.CI(\blk000000fa/sig0000034f ),
.LI(\blk000000fa/sig00000350 ),
.O(sig00000041)
);
MUXCY \blk000000fa/blk00000111 (
.CI(\blk000000fa/sig0000034f ),
.DI(sig0000008c),
.S(\blk000000fa/sig00000350 ),
.O(\blk000000fa/sig00000351 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000110 (
.I0(sig00000002),
.I1(sig0000008c),
.O(\blk000000fa/sig00000350 )
);
XORCY \blk000000fa/blk0000010f (
.CI(\blk000000fa/sig0000034d ),
.LI(\blk000000fa/sig0000034e ),
.O(sig00000040)
);
MUXCY \blk000000fa/blk0000010e (
.CI(\blk000000fa/sig0000034d ),
.DI(sig0000008b),
.S(\blk000000fa/sig0000034e ),
.O(\blk000000fa/sig0000034f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000010d (
.I0(sig00000002),
.I1(sig0000008b),
.O(\blk000000fa/sig0000034e )
);
XORCY \blk000000fa/blk0000010c (
.CI(\blk000000fa/sig0000034b ),
.LI(\blk000000fa/sig0000034c ),
.O(sig0000003f)
);
MUXCY \blk000000fa/blk0000010b (
.CI(\blk000000fa/sig0000034b ),
.DI(sig0000008a),
.S(\blk000000fa/sig0000034c ),
.O(\blk000000fa/sig0000034d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk0000010a (
.I0(sig00000002),
.I1(sig0000008a),
.O(\blk000000fa/sig0000034c )
);
XORCY \blk000000fa/blk00000109 (
.CI(\blk000000fa/sig00000349 ),
.LI(\blk000000fa/sig0000034a ),
.O(sig0000003e)
);
MUXCY \blk000000fa/blk00000108 (
.CI(\blk000000fa/sig00000349 ),
.DI(sig00000089),
.S(\blk000000fa/sig0000034a ),
.O(\blk000000fa/sig0000034b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000107 (
.I0(sig00000002),
.I1(sig00000089),
.O(\blk000000fa/sig0000034a )
);
XORCY \blk000000fa/blk00000106 (
.CI(\blk000000fa/sig00000347 ),
.LI(\blk000000fa/sig00000348 ),
.O(sig0000003d)
);
MUXCY \blk000000fa/blk00000105 (
.CI(\blk000000fa/sig00000347 ),
.DI(sig00000088),
.S(\blk000000fa/sig00000348 ),
.O(\blk000000fa/sig00000349 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000104 (
.I0(sig00000002),
.I1(sig00000088),
.O(\blk000000fa/sig00000348 )
);
XORCY \blk000000fa/blk00000103 (
.CI(\blk000000fa/sig00000345 ),
.LI(\blk000000fa/sig00000346 ),
.O(sig0000003c)
);
MUXCY \blk000000fa/blk00000102 (
.CI(\blk000000fa/sig00000345 ),
.DI(sig00000087),
.S(\blk000000fa/sig00000346 ),
.O(\blk000000fa/sig00000347 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk00000101 (
.I0(sig00000002),
.I1(sig00000087),
.O(\blk000000fa/sig00000346 )
);
XORCY \blk000000fa/blk00000100 (
.CI(\blk000000fa/sig00000343 ),
.LI(\blk000000fa/sig00000344 ),
.O(sig0000003b)
);
MUXCY \blk000000fa/blk000000ff (
.CI(\blk000000fa/sig00000343 ),
.DI(sig00000086),
.S(\blk000000fa/sig00000344 ),
.O(\blk000000fa/sig00000345 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk000000fe (
.I0(sig00000002),
.I1(sig00000086),
.O(\blk000000fa/sig00000344 )
);
XORCY \blk000000fa/blk000000fd (
.CI(sig00000002),
.LI(\blk000000fa/sig00000342 ),
.O(sig0000003a)
);
MUXCY \blk000000fa/blk000000fc (
.CI(sig00000002),
.DI(sig00000085),
.S(\blk000000fa/sig00000342 ),
.O(\blk000000fa/sig00000343 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk000000fa/blk000000fb (
.I0(sig00000002),
.I1(sig00000085),
.O(\blk000000fa/sig00000342 )
);
FDE #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001b8 (
.C(aclk),
.CE(\blk0000018b/sig000003cc ),
.D(\blk0000018b/sig000003cf ),
.Q(\blk0000018b/sig000003a5 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk0000018b/blk000001b7 (
.A0(\blk0000018b/sig000003cb ),
.A1(\blk0000018b/sig000003cb ),
.A2(\blk0000018b/sig000003cb ),
.A3(\blk0000018b/sig000003cb ),
.CE(\blk0000018b/sig000003cc ),
.CLK(aclk),
.D(\blk0000018b/sig000003b4 ),
.Q(\blk0000018b/sig000003cf ),
.Q15(\NLW_blk0000018b/blk000001b7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001b6 (
.C(aclk),
.CE(\blk0000018b/sig000003cc ),
.D(\blk0000018b/sig000003ce ),
.Q(\blk0000018b/sig000003a7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk0000018b/blk000001b5 (
.A0(\blk0000018b/sig000003cb ),
.A1(\blk0000018b/sig000003cb ),
.A2(\blk0000018b/sig000003cb ),
.A3(\blk0000018b/sig000003cb ),
.CE(\blk0000018b/sig000003cc ),
.CLK(aclk),
.D(\blk0000018b/sig000003b6 ),
.Q(\blk0000018b/sig000003ce ),
.Q15(\NLW_blk0000018b/blk000001b5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001b4 (
.C(aclk),
.CE(\blk0000018b/sig000003cc ),
.D(\blk0000018b/sig000003cd ),
.Q(\blk0000018b/sig000003a3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk0000018b/blk000001b3 (
.A0(\blk0000018b/sig000003cb ),
.A1(\blk0000018b/sig000003cb ),
.A2(\blk0000018b/sig000003cb ),
.A3(\blk0000018b/sig000003cb ),
.CE(\blk0000018b/sig000003cc ),
.CLK(aclk),
.D(\blk0000018b/sig000003b2 ),
.Q(\blk0000018b/sig000003cd ),
.Q15(\NLW_blk0000018b/blk000001b3_Q15_UNCONNECTED )
);
VCC \blk0000018b/blk000001b2 (
.P(\blk0000018b/sig000003cc )
);
GND \blk0000018b/blk000001b1 (
.G(\blk0000018b/sig000003cb )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001b0 (
.I0(\blk0000018b/sig000003b6 ),
.I1(\blk0000018b/sig000003b5 ),
.O(\blk0000018b/sig000003ca )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001af (
.I0(\blk0000018b/sig000003b4 ),
.I1(\blk0000018b/sig000003b3 ),
.O(\blk0000018b/sig000003c9 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001ae (
.I0(\blk0000018b/sig000003b0 ),
.I1(\blk0000018b/sig000003af ),
.O(\blk0000018b/sig000003c7 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001ad (
.I0(\blk0000018b/sig000003ae ),
.I1(\blk0000018b/sig000003ad ),
.O(\blk0000018b/sig000003c6 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001ac (
.I0(\blk0000018b/sig000003b2 ),
.I1(\blk0000018b/sig000003b1 ),
.O(\blk0000018b/sig000003c8 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001ab (
.I0(\blk0000018b/sig000003aa ),
.I1(\blk0000018b/sig000003a9 ),
.O(\blk0000018b/sig000003c4 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001aa (
.I0(\blk0000018b/sig000003a8 ),
.I1(\blk0000018b/sig000003a7 ),
.O(\blk0000018b/sig000003c3 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001a9 (
.I0(\blk0000018b/sig000003ac ),
.I1(\blk0000018b/sig000003ab ),
.O(\blk0000018b/sig000003c5 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001a8 (
.I0(\blk0000018b/sig000003a4 ),
.I1(\blk0000018b/sig000003a3 ),
.O(\blk0000018b/sig000003c1 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000018b/blk000001a7 (
.I0(\blk0000018b/sig000003a6 ),
.I1(\blk0000018b/sig000003a5 ),
.O(\blk0000018b/sig000003c2 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001a6 (
.C(aclk),
.D(\blk0000018b/sig000003a4 ),
.Q(\blk0000018b/sig000003a9 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001a5 (
.C(aclk),
.D(\blk0000018b/sig000003a6 ),
.Q(\blk0000018b/sig000003ab )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001a4 (
.C(aclk),
.D(\blk0000018b/sig000003a8 ),
.Q(\blk0000018b/sig000003ad )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001a3 (
.C(aclk),
.D(\blk0000018b/sig000003aa ),
.Q(\blk0000018b/sig000003af )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001a2 (
.C(aclk),
.D(\blk0000018b/sig000003ac ),
.Q(\blk0000018b/sig000003b1 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001a1 (
.C(aclk),
.D(\blk0000018b/sig000003ae ),
.Q(\blk0000018b/sig000003b3 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk000001a0 (
.C(aclk),
.D(\blk0000018b/sig000003b0 ),
.Q(\blk0000018b/sig000003b5 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000019f (
.C(aclk),
.D(sig00000084),
.Q(\blk0000018b/sig000003a4 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000019e (
.C(aclk),
.D(sig00000083),
.Q(\blk0000018b/sig000003a6 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000019d (
.C(aclk),
.D(sig00000082),
.Q(\blk0000018b/sig000003a8 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000019c (
.C(aclk),
.D(sig00000081),
.Q(\blk0000018b/sig000003aa )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000019b (
.C(aclk),
.D(sig00000080),
.Q(\blk0000018b/sig000003ac )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000019a (
.C(aclk),
.D(sig0000007f),
.Q(\blk0000018b/sig000003ae )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000199 (
.C(aclk),
.D(sig0000007e),
.Q(\blk0000018b/sig000003b0 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000198 (
.C(aclk),
.D(sig0000007d),
.Q(\blk0000018b/sig000003b2 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000197 (
.C(aclk),
.D(sig0000007c),
.Q(\blk0000018b/sig000003b4 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000196 (
.C(aclk),
.D(sig0000007b),
.Q(\blk0000018b/sig000003b6 )
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000195 (
.C(aclk),
.D(\blk0000018b/sig000003c1 ),
.Q(sig00000084)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000194 (
.C(aclk),
.D(\blk0000018b/sig000003c2 ),
.Q(sig00000083)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000193 (
.C(aclk),
.D(\blk0000018b/sig000003c3 ),
.Q(sig00000082)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000192 (
.C(aclk),
.D(\blk0000018b/sig000003c4 ),
.Q(sig00000081)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000191 (
.C(aclk),
.D(\blk0000018b/sig000003c5 ),
.Q(sig00000080)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk00000190 (
.C(aclk),
.D(\blk0000018b/sig000003c6 ),
.Q(sig0000007f)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000018f (
.C(aclk),
.D(\blk0000018b/sig000003c7 ),
.Q(sig0000007e)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000018e (
.C(aclk),
.D(\blk0000018b/sig000003c8 ),
.Q(sig0000007d)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000018d (
.C(aclk),
.D(\blk0000018b/sig000003c9 ),
.Q(sig0000007c)
);
FD #(
.INIT ( 1'b0 ))
\blk0000018b/blk0000018c (
.C(aclk),
.D(\blk0000018b/sig000003ca ),
.Q(sig0000007b)
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
This module instantiates all the logic necessary to form tiles
and pipelines them using block RAM. In addition, it breaks out an
interface for a module higher in the design hierarchy.
*/
`include "DeepGATE_include.v"
module tile_network (
input clk_i,
input en_i, //active high, initiates processing
input [7:0] data_i, //input data
input data_rd_i, //active high, signals reading of network output data
output wire data_rd_o, //active high, signals the module is reading data_i
output wire network_idle_o, //active high if ready to accept input
output wire [7:0] data_o, //network output data
output wire proc_complete_o, //active high, indicates processing is complete
input [7:0] weight_data_i,
input [NUM_TILES - 1'b1 : 0] weight_wr_i,
output wire [NUM_TILES - 1'b1 : 0] pipeline_lock_o
);
`include "param_include.v"
genvar i,j;
generate
for(i = 0; i < NUM_TILES; i = i + 1) begin: TILES
parameter [31:0] TILE_SIZE = TILE_SIZE_ARRAY[`ID32(i)];
parameter [31:0] TILE_LOOP = TILE_LOOP_ARRAY[`ID32(i)];
parameter [31:0] TILE_PRV_SIZE = TILE_PRV_SIZE_ARRAY[`ID32(i)];
parameter [31:0] TILE_PRV_LOOP = TILE_PRV_LOOP_ARRAY[`ID32(i)];
parameter [31:0] TILE_NXT_LOOP = TILE_NXT_LOOP_ARRAY[`ID32(i)];
parameter [31:0] TILE_BIAS = TILE_BIAS_ARRAY[`ID32(i)];
wire [TILE_SIZE*WEIGHT_WIDTH - 1'b1:0] weight_bus;
wire en;
wire ram_wr;
wire ram_rd;
wire proc_unit_rst;
wire ram_full;
wire data_available;
wire [7:0] tile_data;
wire [7:0] buffer_data;
wire [$clog2(TILE_SIZE) - 1'b1:0] sig_mux_sel;
//if first tile, connect idle and route data_available to module port
if(i == 0) begin
tile_control #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP),
.PRV_SIZE (TILE_PRV_SIZE),
.PRV_LOOP (TILE_PRV_LOOP)
)
TILE_CONTROL(
.clk_i (clk_i),
.rst_i (1'd0),
.data_available_i (en_i),
.ram_full_i (ram_full),
.pipeline_lock_i (pipeline_lock_o[i]),
.en_o (en),
.ram_wr_o (ram_wr),
.idle_o (network_idle_o),
.ram_rd_o (ram_rd),
.proc_unit_rst_o (proc_unit_rst),
.sig_mux_sel_o (sig_mux_sel)
);
end
else begin
tile_control #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP),
.PRV_SIZE (TILE_PRV_SIZE),
.PRV_LOOP (TILE_PRV_LOOP)
)
TILE_CONTROL(
.clk_i (clk_i),
.rst_i (1'b0),
.data_available_i (TILES[PREV_INDEX[`ID32(i)]].data_available),
.ram_full_i (ram_full),
.pipeline_lock_i (pipeline_lock_o[i]),
.en_o (en),
.ram_wr_o (ram_wr),
.ram_rd_o (ram_rd),
.proc_unit_rst_o (proc_unit_rst),
.sig_mux_sel_o (sig_mux_sel)
);
end
tile_datapath #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP),
.PRV_SIZE (TILE_PRV_SIZE),
.PRV_LOOP (TILE_PRV_LOOP),
.BIAS (TILE_BIAS),
.WEIGHT_WIDTH (WEIGHT_WIDTH)
)
TILE_DATA(
.clk_i (clk_i),
.rst_i (proc_unit_rst),
.en_i (en),
.weight_bus_i (weight_bus),
.sig_mux_sel_i (sig_mux_sel),
.data_i (i == 0 ? data_i[`ID8(0)] : TILES[PREV_INDEX[`ID32(i)]].buffer_data), //simplifies to TILES[i-1].buffer_data
.data_o (tile_data)
);
weight_RAM #(
.SIZE (TILE_SIZE_ARRAY[`ID32(i)]),
.MAX_DEPTH (MEM_MAX_DEPTH_ARRAY[`ID32(i)]),
.DIVIDER (MEM_DIVIDER_ARRAY[`ID32(i)]),
.WEIGHT_WIDTH (WEIGHT_WIDTH)
)
weight_RAM(
.clk_i (clk_i),
.rd_i (ram_rd),
.wr_i (weight_wr_i[i]),
.data_i (weight_data_i),
.pipeline_lock_o (pipeline_lock_o[i]),
.data_o (weight_bus)
);
if(i != NUM_TILES - 1'b1) begin //connect read signal differently for last layer
parameterized_RAM #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP),
.NXT_LOOP (TILE_NXT_LOOP)
)
TILE_BUFFER(
.clk_i (clk_i),
.rd_i (TILES[NEXT_INDEX[`ID32(i)]].ram_rd),
.wr_i (ram_wr),
.data_i (tile_data),
.data_o (buffer_data),
.ram_full_o (ram_full),
.data_available_o (data_available)
);
end
else begin
parameterized_RAM_last #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP)
)
TILE_BUFFER(
.clk_i (clk_i),
.rd_i (data_rd_i),
.wr_i (ram_wr),
.data_i (tile_data),
.data_o (data_o),
.ram_full_o (ram_full),
.data_available_o (proc_complete_o)
);
/*
output_arbiter #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP)
)
outputBuffer(
.clk (clk_i),
.read (data_rd_i),
.write (transfer),
.data_i (activatedData),
.data_o (networkOut),
.ramFull (ramFull),
.dataAvailable (proc_complete_o)
);
*/
end
end
endgenerate
assign data_rd_o = TILES[0].ram_rd;
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus master interface for tawas core.
* Uses 8 master ids x 4 sequence ids to map to 32-threads.
*
*/
module tawas_rcn_master
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [4:0] seq,
output busy,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output rdone,
output wdone,
output [4:0] rsp_seq,
output [3:0] rsp_mask,
output [23:0] rsp_addr,
output [31:0] rsp_data
);
parameter MASTER_GROUP_8 = 0;
reg [68:0] rin;
reg [68:0] rout;
assign rcn_out = rout;
wire [2:0] my_id = MASTER_GROUP_8;
wire my_resp = rin[68] && !rin[67] && (rin[65:63] == MASTER_GROUP_8);
wire req_valid;
wire [68:0] req;
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 69'd0;
rout <= 69'd0;
end
else
begin
rin <= rcn_in;
rout <= (req_valid) ? req : (my_resp) ? 69'd0 : rin;
end
assign busy = rin[68] && !my_resp;
assign req_valid = cs && !(rin[68] && !my_resp);
assign req = {1'b1, 1'b1, wr, my_id, seq[4:2], mask, addr[23:2], seq[1:0], wdata};
assign rdone = my_resp && !rin[66];
assign wdone = my_resp && rin[66];
assign rsp_seq = {rin[62:60], rin[33:32]};
assign rsp_mask = rin[59:56];
assign rsp_addr = {rin[55:34], 2'd0};
assign rsp_data = rin[31:0];
endmodule
|
`timescale 1ns / 1ps
/*
Group Members: Nikita Eisenhauer and Warren Seto
Lab Name: Adder Design
Design Description: Verilog test fixture to test the 64-bit ripple adder
*/
module ripple_adder_64_test;
// Inputs
reg [63:0] A;
reg [63:0] B;
// Outputs
wire [63:0] SUM;
wire CARRY;
// Instantiate two counter variables for the test loop
integer count;
integer count2;
// Instantiate the Unit Under Test (UUT)
ripple_adder_64 uut
(
.A(A),
.B(B),
.SUM(SUM),
.CARRY(CARRY)
);
initial begin
$monitor("%d + %d = %d and carry %d", A, B, SUM, CARRY);
// Iterate through all possible combination of 0-32
count = 0;
count2 = 0;
A = 0;
B = 0;
// Loops over the possible combinations for the inputs A and B
for (count = 0; count <= 32; count = count + 1) begin
{A} = count;
for (count2 = 0; count2 <= 32; count2 = count2 + 1) begin
{B} = count2;
#1;
end
end
end
initial #4000 $finish; // The test will run for a total interval of 4000 nanoseconds
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fx2_to_bus
#(
parameter WIDTH = 16 // 16 bit bus from FX2
) (
input wire [WIDTH-1:0] ADD,
input wire RD_B, // neg active, two clock cycles
input wire WR_B, // neg active
input wire BUS_CLK, // FCLK
output wire [WIDTH-1:0] BUS_ADD,
output wire BUS_RD,
output wire BUS_WR,
output wire CS_FPGA
);
// remove offset from FX2
assign BUS_ADD = ADD - 16'h4000;
// chip select FPGA
assign CS_FPGA = ~ADD[15] & ADD[14];
// generate read strobe which one clock cycle long
// this is very important to prevent corrupted data
reg RD_B_FF;
always @ (posedge BUS_CLK) begin
RD_B_FF <= RD_B;
end
assign BUS_RD = ~RD_B & RD_B_FF;
assign BUS_WR = ~WR_B;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_TB_V
`define SKY130_FD_SC_LP__NOR4_TB_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_TB_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: n_cpci_top.v
// Description: Based on NetFPGA's original cpci_top module.
//
///////////////////////////////////////////////////////////////////////////////
module n_cpci_top
#(parameter DMA_DATA_WIDTH=32)
(
//xCG
//PCIe interface ports
output wire txs_chip_select,
output wire txs_read,
output wire txs_write,
output wire [31:0] txs_address,
output wire [9:0] txs_burst_count,
output wire [31:0] txs_writedata,
output wire [3:0] txs_byteenable,
input wire txs_read_valid,
input wire [31:0] txs_readdata,
input wire txs_wait_request,
input wire rxm_read_bar_1,
input wire rxm_write_bar_1,
input wire [31:0] rxm_address_bar_1,
input wire [31:0] rxm_writedata_bar_1,
output wire rxm_wait_request_bar_1,
output wire [31:0] rxm_readdata_bar_1,
output wire rxm_read_valid_bar_1,
output wire interrupt_request,
//Other signals
input nclk, // CNET core clock
output reg cnet_reset, // Reset signal to CNET
input phy_int_b, // Interrupt signal from PHY
output cpci_rd_wr_L, // Read/Write signal
output cpci_req, // I/O request signal
//output [`CPCI_CNET_ADDR_WIDTH-1:0] cpci_addr,
output [31:0] cpci_addr, //xCG
inout [`CPCI_CNET_DATA_WIDTH-1:0] cpci_data,
input cpci_wr_rdy, // Write ready from CNET
input cpci_rd_rdy, // Read ready from CNET
input cnet_err, // Error signal from CNET
//here
// --- CPCI DMA handshake signals
output [1:0] cpci_dma_op_code_req,
output [3:0] cpci_dma_op_queue_id,
input [1:0] cpci_dma_op_code_ack,
// DMA data and flow control
output cpci_dma_vld_c2n,
input cpci_dma_vld_n2c,
inout [DMA_DATA_WIDTH-1:0] cpci_dma_data,
input cpci_dma_q_nearly_full_n2c,
output cpci_dma_q_nearly_full_c2n,
//to here
// Reprogramming signals xCG
//output rp_cclk,
//output rp_prog_b,
//input rp_init_b,
//output rp_cs_b,
//output rp_rdwr_b,
//output [7:0] rp_data,
//input rp_done,
// Debug signals
//output cpci_led,
//output reg [28:0] cpci_debug_data,
//output [1:0] cpci_debug_clk,
// Allow reprogramming
//output allow_reprog,
// CNET clock speed
output cnet_clk_sel, // 1 = 125 MHz, 0 = 62.5 MHz
// Board identification
input cpci_jmpr, // Jumper on board
input [3:0] cpci_id, // Rotary switch on board
input reset
);
// synthesis syn_edif_bit_format = "%u<%i>"
// synthesis syn_edif_scalar_format = "%u"
// synthesis syn_noclockbuf = 1
// synthesis syn_hier = "hard"
//
// ==================================================================
// Local signals
// ==================================================================
wire [`PCI_ADDR_WIDTH - 1:0] pci_addr;
wire [`PCI_BE_WIDTH - 1:0] pci_be;
wire [`PCI_DATA_WIDTH - 1:0] pci_data;
wire [`PCI_DATA_WIDTH - 1:0] pci_data_to_dma;
wire [`PCI_DATA_WIDTH - 1:0] reg_data;
wire [`PCI_DATA_WIDTH - 1:0] cnet_data;
wire [`PCI_DATA_WIDTH - 1:0] dma_data;
wire [`PCI_BE_WIDTH - 1:0] dma_cbe;
wire [`CPCI_CNET_DATA_WIDTH - 1:0] p2n_data; // cnet_reg
wire [`CPCI_CNET_ADDR_WIDTH - 1:0] p2n_addr; // cnet_reg
wire [`CPCI_CNET_DATA_WIDTH - 1:0] n2p_data;
wire [31:0] cnet_rd_time;
wire [`CPCI_CNET_DATA_WIDTH - 1:0] cpci_data_wr;
wire [`PCI_DATA_WIDTH - 1:0] prog_data;
wire [15:0] dma_pkt_avail;
wire dma_rd_request;
wire [3:0] dma_rd_request_q;
wire [15:0] dma_tx_full;
wire [`PCI_ADDR_WIDTH - 1:0] dma_data_frm_cnet;
wire [`PCI_ADDR_WIDTH - 1:0] dma_data_to_cnet;
wire dma_wr_en;
wire dma_wr_rdy;
wire [3:0] mac_wr_request;
wire dma_wr_store_size;
wire [`PCI_ADDR_WIDTH - 1:0] dma_rd_addr;
wire [3:0] dma_rd_mac;
wire [`PCI_DATA_WIDTH - 1:0] dma_rd_size;
wire [`PCI_ADDR_WIDTH - 1:0] dma_wr_addr;
wire [3:0] dma_wr_mac;
wire [`PCI_DATA_WIDTH - 1:0] dma_wr_size;
wire [31:0] dma_time;
wire [15:0] dma_retries;
wire [`CPCI_CNET_DATA_WIDTH - 1:0] dma_data_buf;
wire [`CPCI_CNET_ADDR_WIDTH - 1:0] dma_addr_buf;
reg cnet_reset_1;
reg cnet_err_d1, cnet_err_sync;
reg phy_int_d1, phy_int_sync;
wire [31:0] n_clk_count;
wire [31:0] clk_chk_p_max;
wire [31:0] clk_chk_n_exp;
wire nclk_int;
reg startup_reset;
//reg reset; xCG
wire [8:0] dma_xfer_cnt;
// Following are temp assignments to prevent signals being removed in synthesis
//
wire clk;
assign clk = nclk; //xCG
//xCG
// assign cpci_debug_clk[1:0] = {~nclk_int, ~clk};
// always @(posedge clk)
// cpci_debug_data <= pci_data;
// clock_checker checks the relative frequencies of the PCI clock and
// the sys_clk
cpci_clock_checker cc (
.error (clock_checker_led), // drive LED
.n_clk_count (n_clk_count),
.clk_chk_p_max (clk_chk_p_max),
.clk_chk_n_exp (clk_chk_n_exp),
.reset (reset),
.shift_amount (cpci_id),
.p_clk (clk),
.n_clk (nclk_int)
);
// synthesis attribute keep_hierarchy of cc is false;
// ==================================================================
// DLL to deskew the nclk
// ==================================================================
// BUFGDLL nclk_dll(
// .I(nclk),
// .O(nclk_int)
// ); xCG
assign nclk_int = nclk;
// synthesis attribute keep_hierarchy of nclk_dll is false;
// ==================================================================
// Instantiate the PCI TOP module
// ==================================================================
// pcim_top pcim_top (
// .AD( AD ),
// .CBE( CBE ),
// .PAR( PAR ),
// .FRAME_N( FRAME_N ),
// .TRDY_N( TRDY_N ),
// .IRDY_N( IRDY_N ),
// .STOP_N( STOP_N ),
// .DEVSEL_N( DEVSEL_N ),
// .IDSEL( IDSEL ),
// .INTR_A( INTR_A ),
// .PERR_N( PERR_N ),
// .SERR_N( SERR_N ),
// .REQ_N( REQ_N ),
// .GNT_N( GNT_N ),
// .RST_N( RST_N ),
// .PCLK( PCLK ),
//
// // Additional ports
// .reg_hit (reg_hit),
// .cnet_hit (cnet_hit),
//
// .reg_we (reg_we),
// .cnet_we (cnet_we),
//
// .pci_addr (pci_addr),
// .pci_data (pci_data),
// .pci_data_vld (pci_data_vld),
// .pci_be (pci_be),
//
// .pci_retry (pci_retry),
// .pci_fatal (pci_fatal),
//
//
// .reg_data (reg_data),
// .cnet_data (cnet_data),
//
// .cnet_retry (cnet_retry),
// .cnet_reprog (cnet_reprog),
//
// .reg_vld (reg_vld),
// .cnet_vld (cnet_vld),
// .dma_vld (dma_vld),
//
// .intr_req (intr_req),
//
// .dma_request (dma_request),
//
// .dma_data (dma_data),
// .dma_cbe (dma_cbe),
//
// .dma_data_vld (dma_data_vld),
// .dma_src_en (dma_src_en),
//
//
// .dma_wrdn (dma_wrdn),
//
// .dma_complete (dma_complete),
//
// .dma_lat_timeout (dma_lat_timeout),
// .dma_addr_st (dma_addr_st),
//
// .dma_data_st (dma_data_st),
//
//
// .clk (clk),
// .pci_reset (pci_reset)
// );
pcie_interface pcie_i
(
.clk (clk),
.reset(reset),
.txs_chip_select (txs_chip_select),
.txs_read (txs_read),
.txs_write (txs_write),
.txs_address (txs_address),
.txs_burst_count (txs_burst_count),
.txs_writedata (txs_writedata),
.txs_byteenable (txs_byteenable),
.txs_read_valid (txs_read_valid),
.txs_readdata (txs_readdata),
.txs_wait_request (txs_wait_request),
.rxm_read (rxm_read_bar_1),
.rxm_write (rxm_write_bar_1),
.rxm_address (rxm_address_bar_1),
.rxm_writedata (rxm_writedata_bar_1),
.rxm_wait_request (rxm_wait_request_bar_1),
.rxm_readdata (rxm_readdata_bar_1),
.rxm_read_valid (rxm_read_valid_bar_1),
.interrupt_request (interrupt_request),
.reg_hit (reg_hit),
.cnet_hit (cnet_hit),
.reg_we (reg_we),
.cnet_we (cnet_we),
.pci_addr (pci_addr),
.pci_data (pci_data),
.pci_data_vld (pci_data_vld),
.pci_be (pci_be),
.pci_retry (pci_retry),
.pci_fatal (pci_fatal),
.reg_data (reg_data),
.cnet_data (cnet_data),
.cnet_retry (cnet_retry),
.cnet_reprog (cnet_reprog),
.reg_vld (reg_vld),
.cnet_vld (cnet_vld),
.dma_vld (dma_vld),
.intr_req (intr_req),
.dma_request (dma_request),
.dma_data (dma_data),
.dma_cbe (dma_cbe),
.dma_data_vld (dma_data_vld),
.dma_src_en (dma_src_en),
.dma_wrdn (dma_wrdn),
.dma_complete (dma_complete),
.dma_lat_timeout (dma_lat_timeout),
.dma_addr_st (dma_addr_st),
.dma_data_st (dma_data_st),
.pci_data_to_dma (pci_data_to_dma),
.dma_xfer_cnt (dma_xfer_cnt)
);
// ==================================================================
// Instantiate the register file
// ==================================================================
reg_file reg_file (
.pci_addr (pci_addr),
.reg_hit (reg_hit),
.reg_we (reg_we),
.pci_be (pci_be),
.pci_data (pci_data),
.pci_data_vld (pci_data_vld),
.reg_data (reg_data),
.reg_vld (reg_vld),
.reg_reset (reg_reset),
.prog_data (prog_data),
.prog_data_vld (prog_data_vld),
.prog_reset (prog_reset),
.intr_req (intr_req),
.cnet_hit (cnet_hit),
.cnet_we (cnet_we),
.empty (empty),
.prog_init (prog_init),
.prog_done (prog_done),
.cnet_reprog (cnet_reprog),
.dma_rd_addr (dma_rd_addr),
.dma_wr_addr (dma_wr_addr),
.dma_rd_mac (dma_rd_mac),
.dma_wr_mac (dma_wr_mac),
.dma_rd_size (dma_rd_size),
.dma_wr_size (dma_wr_size),
.dma_rd_owner (dma_rd_owner),
.dma_wr_owner (dma_wr_owner),
.dma_rd_done (dma_rd_done),
.dma_wr_done (dma_wr_done),
.dma_in_progress (dma_in_progress),
.dma_time (dma_time),
.dma_retries (dma_retries),
.cnet_rd_time (cnet_rd_time),
.cpci_jmpr (cpci_jmpr),
.cpci_id (cpci_id),
.prog_overflow (prog_overflow),
.prog_error (prog_error),
.dma_buf_overflow (dma_buf_overflow),
.dma_rd_size_err (dma_rd_size_err),
.dma_wr_size_err (dma_wr_size_err),
.dma_rd_addr_err (dma_rd_addr_err),
.dma_wr_addr_err (dma_wr_addr_err),
.dma_rd_mac_err (dma_rd_mac_err),
.dma_wr_mac_err (dma_wr_mac_err),
.dma_timeout (dma_xfer_timeout),
.dma_retry_expire (dma_retry_expire),
.dma_fatal_err (dma_fatal_err),
.cnet_rd_timeout (cnet_rd_timeout),
.cnet_err (cnet_err_sync),
.dma_rd_intr (dma_rd_intr),
.dma_wr_intr (dma_wr_intr),
.phy_intr (phy_int_sync),
.dma_pkt_avail (dma_pkt_avail),
.cnet_clk_sel (cnet_clk_sel),
.cpci_led (cpci_led_reg),
.n_clk_count(n_clk_count),
.clk_chk_p_max (clk_chk_p_max),
.clk_chk_n_exp (clk_chk_n_exp),
.try_cnet_reset (try_cnet_reset),
.host_is_le (host_is_le),
//.pci_reset (pci_reset), xCG
.pci_reset(reset),
.clk (clk)
);
// synthesis attribute keep_hierarchy of reg_file is false;
// ==================================================================
// CNET register access module
// ==================================================================
cnet_reg_access cnet_reg_access(
.pci_addr (pci_addr),
.pci_be (pci_be),
.pci_data (pci_data),
.pci_data_vld (pci_data_vld),
.cnet_we (cnet_we),
.cnet_hit (cnet_hit),
.cnet_data (cnet_data),
.cnet_vld (cnet_vld),
.cnet_retry (cnet_retry),
.p2n_data (p2n_data),
.p2n_addr (p2n_addr),
.p2n_we (p2n_we),
.p2n_req (p2n_req),
.p2n_full (p2n_full),
.n2p_data (n2p_data),
.n2p_rd_rdy (n2p_rd_rdy),
.cnet_reprog (cnet_reprog),
.reset (reset),
.clk (clk)
);
// synthesis attribute keep_hierarchy of cnet_reg_access is false;
// ==================================================================
// CNET register interface module (handles clock domain crossing)
// ==================================================================
cnet_reg_iface cnet_reg_iface (
.p2n_data (p2n_data),
.p2n_addr (p2n_addr),
.p2n_we (p2n_we),
.p2n_req (p2n_req),
.p2n_full (p2n_full),
.p2n_almost_full (p2n_almost_full),
.n2p_data (n2p_data),
.n2p_rd_rdy (n2p_rd_rdy),
.cnet_reprog (cnet_reprog),
.cnet_hit (cnet_hit),
.cnet_rd_time (cnet_rd_time),
.cnet_rd_timeout (cnet_rd_timeout),
.cpci_rd_wr_L (cpci_rd_wr_L),
.cpci_req (cpci_req),
.cpci_addr (cpci_addr),
.cpci_data_wr (cpci_data_wr),
.cpci_data_rd (cpci_data),
.cpci_data_tri_en (cpci_data_tri_en),
.cpci_wr_rdy (cpci_wr_rdy),
.cpci_rd_rdy (cpci_rd_rdy),
.reset (reset),
.pclk (clk),
.nclk (nclk_int)
);
// synthesis attribute keep_hierarchy of cnet_reg_iface is false;
// synthesis attribute iob of cpci_data_tri_en is true;
// synthesis attribute iob of cpci_data_wr is true;
// synthesis attribute iob of cpci_addr is true;
// synthesis attribute iob of cpci_rd_rdy is true;
// synthesis attribute iob of cpci_wr_rdy is true;
// synthesis attribute iob of cpci_req is true;
// synthesis attribute iob of cpci_data is true;
// synthesis attribute iob of cpci_rd_wr_L is true;
// synthesis attribute iob of cpci_tx_full is true;
// ==================================================================
// CNET reprogramming module
// ==================================================================
cnet_reprogram cnet_reprogram(
.prog_data (prog_data),
.prog_data_vld (prog_data_vld),
.prog_reset (prog_reset),
.cnet_reprog (cnet_reprog),
.overflow (prog_overflow),
.error (prog_error),
.empty (empty),
.init (prog_init),
.done (), //xCG
.rp_prog_b (rp_prog_b),
.rp_init_b (rp_init_b),
.rp_cclk (rp_cclk),
.rp_cs_b (rp_cs_b),
.rp_rdwr_b (rp_rdwr_b),
.rp_data (rp_data),
.rp_done (rp_done),
.reset (reset),
.clk (clk)
);
assign prog_done = 1'b1;
// synthesis attribute keep_hierarchy of cnet_reprogram is false;
// ==================================================================
// Clock-domain crossing buffer for DMA
// ==================================================================
wire [31:0] cpci_dma_data_c2n;
wire cpci_dma_data_tri_en;
assign cpci_dma_data = cpci_dma_data_tri_en ? cpci_dma_data_c2n :'b z;
//assign dma_pkt_avail = 4'hffff; //xCG TESTING
cnet_dma_bus_master cnet_dma_bus_master
(
.dma_pkt_avail (dma_pkt_avail),
.dma_rd_request (dma_rd_request),
.dma_rd_request_q (dma_rd_request_q),
.dma_rd_data (dma_data_frm_cnet),
.dma_rd_en (dma_rd_en),
.dma_tx_full (dma_tx_full),
.dma_nearly_empty (dma_nearly_empty),
.dma_empty (dma_empty),
.dma_all_in_buf (dma_all_in_buf),
.overflow (dma_buf_overflow),
.cnet_reprog (cnet_reprog),
.dma_wr_data (dma_data_to_cnet),
.dma_wr_en (dma_wr_en),
.dma_wr_rdy (dma_wr_rdy),
// --- CPCI DMA handshake signals
//outputs:
.cpci_dma_op_code_req ( cpci_dma_op_code_req ),
.cpci_dma_op_queue_id ( cpci_dma_op_queue_id ),
//inputs:
.cpci_dma_op_code_ack ( cpci_dma_op_code_ack ),
// DMA data and flow control
// data transfer in:
//inputs:
.cpci_dma_vld_n2c ( cpci_dma_vld_n2c ),
.cpci_dma_data_n2c ( cpci_dma_data ),
//outputs:
.cpci_dma_q_nearly_full_c2n ( cpci_dma_q_nearly_full_c2n ),
// data transfer out:
//outputs:
.cpci_dma_vld_c2n ( cpci_dma_vld_c2n ),
.cpci_dma_data_c2n ( cpci_dma_data_c2n ),
.cpci_dma_data_tri_en ( cpci_dma_data_tri_en ),
//inputs:
.cpci_dma_q_nearly_full_n2c ( cpci_dma_q_nearly_full_n2c ),
//misc:
.reset (reset),
.pclk (clk),
.nclk (nclk_int)
);
// synthesis attribute keep_hierarchy of cnet_dma_bus_master is false;
// synthesis attribute iob of cpci_dma_op_code_req is true;
// synthesis attribute iob of cpci_dma_op_queue_id is true;
// synthesis attribute iob of cpci_dma_op_code_ack is true;
// synthesis attribute iob of cpci_dma_vld_n2c is true;
// synthesis attribute iob of cpci_dma_data is true;
// synthesis attribute iob of cpci_dma_q_nearly_full_c2n is true;
// synthesis attribute iob of cpci_dma_vld_c2n is true;
// synthesis attribute iob of cpci_dma_data_c2n is true;
// synthesis attribute iob of cpci_dma_data_tri_en is true;
// synthesis attribute iob of cpci_dma_q_nearly_full_n2c is true;
// ==================================================================
// DMA Engine
// ==================================================================
dma_engine dma_engine(
.pci_data (pci_data_to_dma), //xCG
.dma_data (dma_data),
.dma_cbe (dma_cbe),
.dma_vld (dma_vld),
.dma_wrdn (dma_wrdn),
.dma_request (dma_request),
.dma_complete (dma_complete),
.dma_data_vld (dma_data_vld),
.dma_src_en (dma_src_en),
.dma_lat_timeout (dma_lat_timeout),
.dma_addr_st (dma_addr_st),
.dma_data_st (dma_data_st),
.dma_rd_intr (dma_rd_intr),
.dma_wr_intr (dma_wr_intr),
.pci_retry (pci_retry),
.pci_fatal (pci_fatal),
.dma_rd_addr (dma_rd_addr),
.dma_wr_addr (dma_wr_addr),
.dma_rd_mac (dma_rd_mac),
.dma_wr_mac (dma_wr_mac),
.dma_rd_size (dma_rd_size),
.dma_wr_size (dma_wr_size),
.dma_rd_owner (dma_rd_owner),
.dma_wr_owner (dma_wr_owner),
.dma_rd_done (dma_rd_done),
.dma_wr_done (dma_wr_done),
.dma_time (dma_time),
.dma_timeout (dma_xfer_timeout),
.dma_retries (dma_retries),
.dma_retry_expire (dma_retry_expire),
.dma_rd_size_err (dma_rd_size_err),
.dma_wr_size_err (dma_wr_size_err),
.dma_rd_addr_err (dma_rd_addr_err),
.dma_wr_addr_err (dma_wr_addr_err),
.dma_rd_mac_err (dma_rd_mac_err),
.dma_wr_mac_err (dma_wr_mac_err),
.dma_fatal_err (dma_fatal_err),
.dma_in_progress (dma_in_progress),
.host_is_le (host_is_le),
.dma_pkt_avail (dma_pkt_avail),
.dma_rd_request (dma_rd_request),
.dma_rd_request_q (dma_rd_request_q),
.dma_data_frm_cnet (dma_data_frm_cnet),
.dma_rd_en (dma_rd_en),
.dma_data_to_cnet (dma_data_to_cnet),
.dma_wr_en (dma_wr_en),
.dma_wr_rdy (dma_wr_rdy),
.dma_tx_full (dma_tx_full),
.dma_nearly_empty (dma_nearly_empty),
.dma_empty (dma_empty),
.dma_all_in_buf (dma_all_in_buf),
.cnet_reprog (cnet_reprog),
.reset (reset),
.clk (clk),
.xfer_cnt (dma_xfer_cnt) //xCG
);
// synthesis attribute keep_hierarchy of dma_engine is false;
// ==================================================================
// Heartbeat
// ==================================================================
cpci_heartbeat cpci_heartbeat (
.heartbeat(heartbeat_led),
.reset (reset),
.clk (clk)
);
// synthesis attribute keep_hierarchy of cpci_heartbeat is false;
// ==================================================================
// Chipscope
// ==================================================================
/*chipscope chipscope(
.cpci_jmpr (cpci_jmpr),
.cpci_id (cpci_id),
.empty (empty),
.prog_init (prog_init),
.prog_done (prog_done),
.cnet_reprog (cnet_reprog),
.pci_addr (pci_addr),
.pci_data (pci_data),
.pci_data_vld (pci_data_vld),
.reg_hit (reg_hit),
.reg_we (reg_we),
.reg_vld (reg_vld),
.pci_reset (pci_reset),
.clk (clk)
);*/
// Generate the global reset signal
//
// Force the chip to reset on startup
initial
begin
startup_reset = 1;
end
always @(posedge clk)
begin
startup_reset <= 1'b0;
//reset <= pci_reset || reg_reset || startup_reset; xCG
end
// Generate the cpci_data signal
assign cpci_data = cpci_data_tri_en ? cpci_data_wr : 'bz;
// Generate the cnet_reset signal
always @(posedge nclk_int)
begin
//cnet_reset <= cnet_reset_1;
//cnet_reset_1 <= pci_reset || try_cnet_reset;
cnet_reset <= reset; //xCG, changed this because was getting x in simulation.
end
// Generate the cnet_err_sync signal
always @(posedge clk)
begin
//if (pci_reset) begin //xCG
if (reset) begin
cnet_err_d1 <= 1'b0;
cnet_err_sync <= 1'b0;
end
else begin
cnet_err_d1 <= cnet_err;
cnet_err_sync <= cnet_err_d1;
end
end
// Generate the phy_int_sync signal
always @(posedge clk)
begin
//if (pci_reset) begin xCG
if (reset) begin
phy_int_d1 <= 1'b0;
phy_int_sync <= 1'b0;
end
else begin
phy_int_d1 <= ~phy_int_b;
phy_int_sync <= phy_int_d1;
end
end
// assign cpci_led = heartbeat_led;
assign cpci_led = (cpci_id == 4'h0) ? heartbeat_led : ~clock_checker_led;
// Disallow reprogramming
assign allow_reprog = 1'b1;
endmodule // cpci_top
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dec_table.v when simulating
// the core, dec_table. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dec_table(
clka,
addra,
douta
);
input clka;
input [7 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("dec_table.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
// iverilog -o tb_i2c.vvp tb_i2c.v i2c_mock_master.v i2c_slave.v && vvp tb_i2c.vvp
// gtkwave.exe tb_i2c.vcd
`timescale 1ns/1ps
`define period 10
module tb_i2c();
reg clk;
reg start;
reg reset;
reg write;
reg [7:0] write_data;
reg [6:0] address;
wire error;
wire ready;
wire [7:0] read_data;
wire [7:0] curr_data [3:0];
reg [6:0] slave_addrs [3:0];
reg [2:0] slave_sel;
reg [7:0] saved_data;
wire [6:0] rcvd_addr [3:0];
wire rcvd_mode[3:0];
wire [2:0] state [3:0];
wire [7:0] curr_data1;
wire [7:0] curr_data2;
wire [7:0] curr_data3;
wire [7:0] curr_data4;
wire [6:0] slave_address1;
wire [6:0] slave_address2;
wire [6:0] slave_address3;
wire [6:0] slave_address4;
assign curr_data0 = curr_data[0];
assign curr_data1 = curr_data[1];
assign curr_data2 = curr_data[2];
assign curr_data3 = curr_data[3];
assign slave_address0 = slave_addrs[0];
assign slave_address1 = slave_addrs[1];
assign slave_address2 = slave_addrs[2];
assign slave_address3 = slave_addrs[3];
integer txn_no;
wire scl;
tri1 sda;
i2c_mock_master uut_mock_master (.clock(clk), .start(start), .reset(reset), .write(write), .write_data(write_data), .read_data(read_data), .address(address), .ready(ready), .error(error), .sda(sda), .scl(scl));
i2c_slave s0 (.sda(sda), .scl(scl), .my_addr(slave_addrs[0]), .curr_data(curr_data[0]), .rcvd_addr(rcvd_addr[0]), .rcvd_mode(rcvd_mode[0]), .state(state[0]));
i2c_slave s1 (.sda(sda), .scl(scl), .my_addr(slave_addrs[1]), .curr_data(curr_data[1]), .rcvd_addr(rcvd_addr[1]), .rcvd_mode(rcvd_mode[1]), .state(state[1]));
i2c_slave s2 (.sda(sda), .scl(scl), .my_addr(slave_addrs[2]), .curr_data(curr_data[2]), .rcvd_addr(rcvd_addr[2]), .rcvd_mode(rcvd_mode[2]), .state(state[2]));
i2c_slave s3 (.sda(sda), .scl(scl), .my_addr(slave_addrs[3]), .curr_data(curr_data[3]), .rcvd_addr(rcvd_addr[3]), .rcvd_mode(rcvd_mode[3]), .state(state[3]));
always begin
#(`period/2)
clk = ~clk;
end
initial begin
//$vcdplusfile("tb_I2C_master_writeread_mapped.vpd");
//$vcdpluson;
$dumpfile("tb_i2c.vcd");
$dumpvars;
reset = 1;
start = 0;
clk = 0;
write = 1;
slave_sel = 0;
txn_no = 1;
slave_addrs[0] = 80; //You can edit
slave_addrs[1] = 81; //these addresses
slave_addrs[2] = 82;
slave_addrs[3] = 83;//if you want.
#(`period * 5)
reset = 0;
//new test
write = 1;
write_data = 8'h21;
slave_sel = 0;
address = slave_addrs[slave_sel];
#`period
$display("--- Transaction %0d ---", txn_no);
txn_no = txn_no + 1;
start = 1;
#`period
start = 0;
#(`period * 100)
//new test
write = 1;
write_data = 8'h56;
slave_sel = 1;
address = slave_addrs[slave_sel];
#`period
$display("--- Transaction %0d ---", txn_no);
txn_no = txn_no + 1;
start = 1;
#`period
start = 0;
#(`period * 100)
//new test
write = 1;
write_data = 8'h18;
slave_sel = 2;
address = slave_addrs[slave_sel];
#`period
$display("--- Transaction %0d ---", txn_no);
txn_no = txn_no + 1;
start = 1;
#`period
start = 0;
#(`period * 100)
//new test
write = 0;
write_data = 8'h21;
slave_sel = 3;
address = slave_addrs[slave_sel];
#`period
$display("--- Transaction %0d ---", txn_no);
txn_no = txn_no + 1;
start = 1;
#`period
start = 0;
#(`period * 100)
write = 0;
write_data = 8'h21;
slave_sel = 0;
address = slave_addrs[slave_sel];
#`period
$display("--- Transaction %0d ---", txn_no);
txn_no = txn_no + 1;
start = 1;
#`period
start = 0;
#(`period * 100)
write = 0;
write_data = 8'h86;
slave_sel = 1;
address = slave_addrs[slave_sel];
#`period
$display("--- Transaction %0d ---", txn_no);
txn_no = txn_no + 1;
start = 1;
#`period
start = 0;
#(`period * 100)
// Add more test cases here. You should
// be able to write to all slaves.
$finish();
end
// This is needed to sample the data
// that will be read by the wrapper
always @(negedge ready) begin
saved_data = curr_data[slave_sel];
end
always @(posedge ready) begin
if (reset == 0) begin
$display("--- New Transaction ---");
if (write == 1)
$display("Flow: write");
else
$display("Flow: read");
if (error == 1) begin
$display("Error: yes");
$display("Reason: no ack");
end else begin
if (write == 1) begin
if (write_data != curr_data[slave_sel]) begin
$display("Error: yes");
$display("Reason: wrong data");
end else begin
$display("No error.");
end
end else begin
if (read_data != saved_data) begin
$display("Error: yes");
$display("Reason: wrong data");
end else begin
$display("No error.");
end
end
end
end
end
endmodule
|
//wb_logic_analyzer.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000010
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_logic_analyzer
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0D
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:16
*/
`include "project_defines.v"
`include "logic_analyzer_defines.v"
`define CONTROL_RESET 0
`define CONTROL_ENABLE_INTERRUPT 1
`define CONTROL_ENABLE_LA 2
`define CONTROL_RESTART_LA 3
`define CONTROL_FORCE_STB 4
`define CONTROL_ENABLE_UART 5
`define STATUS_FINISHED 0
`define SLEEP_COUNT 4
`define CAPTURE_WIDTH 32
module wb_logic_analyzer # (
parameter CAPTURE_DEPTH = 10,
parameter DEFAULT_BAUDRATE = 115200
) (
input clk,
input rst,
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
output reg o_wbs_int,
//logic anayzer signals
input i_la_clk,
input [`CAPTURE_WIDTH - 1:0] i_la_data,
input i_la_ext_trig,
input i_phy_rx,
output o_phy_tx
);
//Local Parameters
localparam CONTROL = 32'h00000000;
localparam STATUS = 32'h00000001;
localparam TRIGGER = 32'h00000002;
localparam TRIGGER_MASK = 32'h00000003;
localparam TRIGGER_AFTER = 32'h00000004;
localparam TRIGGER_EDGE = 32'h00000005;
localparam BOTH_EDGES = 32'h00000006;
localparam REPEAT_COUNT = 32'h00000007;
localparam DATA_COUNT = 32'h00000008;
localparam START_POS = 32'h00000009;
localparam CLOCK_RATE = 32'h0000000A;
localparam READ_DATA = 32'h0000000B;
//Local Registers/Wires
reg [31:0] r_trigger;
reg [31:0] r_trigger_mask;
reg [31:0] r_trigger_after;
reg [31:0] r_trigger_edge;
reg [31:0] r_repeat_count;
reg [31:0] r_both_edges;
reg [31:0] r_clock_divider;
wire [31:0] w_cap_data_size;
wire w_finished;
reg r_uart_en = 1;
reg r_force_stb;
wire w_force_stb;
reg r_data_read_en;
reg r_data_read_count;
reg r_ctr_rst;
reg r_ctr_int_en;
reg r_ctr_en_la;
reg r_ctr_restart_la;
reg [31:0] r_bram_read_addr;
wire [31:0] w_bram_read_data;
reg [3:0] r_bram_sleep;
reg r_prev_cyc;
wire w_posedge_cyc;
wire [31:0] w_start_pos;
wire w_la_reset;
//data interface
wire [31:0] data_read_size;
wire [31:0] data_read_addr;
wire data_read_strobe;
wire [31:0] data;
wire [31:0] w_uart_trigger;
wire [31:0] w_uart_trigger_mask;
wire [31:0] w_uart_trigger_after;
wire [31:0] w_uart_trigger_edge;
wire [31:0] w_uart_both_edges;
wire [31:0] w_uart_repeat_count;
wire w_uart_la_reset;
wire w_uart_la_force_trig;
wire w_uart_set_stb;
wire w_uart_la_en;
wire uart_la_reset;
wire [31:0] w_uart_read_addr;
wire [31:0] w_la_read_addr;
assign w_la_read_addr = (r_uart_en) ? w_uart_read_addr : r_bram_read_addr;
cross_clock_enable en_la_rst (
.rst (rst ),
.in_en (r_ctr_rst ),
.out_clk (i_la_clk ),
.out_en (w_la_reset )
);
cross_clock_strobe en_la_force_stb (
.rst (rst ),
.in_stb (r_force_stb ),
.in_clk (clk ),
.out_clk (i_la_clk ),
.out_stb (w_force_stb )
);
uart_la_interface # (
.DEFAULT_BAUDRATE (DEFAULT_BAUDRATE )
) ula (
.clk (clk ),
.rst (rst ),
.o_en_la (w_uart_la_en ),
.o_la_reset (w_uart_la_reset ),
.o_force_trigger (w_uart_force_trig ),
.i_finished (w_uart_la_en && w_finished ),
.i_start_pos (w_start_pos ),
.o_uart_set_value_stb (w_uart_set_stb ),
//logic analyzer control
.o_trigger (w_uart_trigger ),
.o_trigger_mask (w_uart_trigger_mask ),
.o_trigger_after (w_uart_trigger_after ),
.o_trigger_edge (w_uart_trigger_edge ),
.o_both_edges (w_uart_both_edges ),
.o_repeat_count (w_uart_repeat_count ),
//data interface
.i_la_rd_size (w_cap_data_size ),
.o_la_rd_addr (w_uart_read_addr ),
.i_la_rd_data (w_bram_read_data ),
.i_phy_rx (i_phy_rx ),
.o_phy_tx (o_phy_tx )
);
//Submodules
logic_analyzer # (
.CAPTURE_WIDTH (`CAPTURE_WIDTH ),
.CAPTURE_DEPTH (CAPTURE_DEPTH )
) la (
.clk (clk ),
.rst (w_la_reset ),
.i_cap_clk (i_la_clk ),
.i_cap_ext_trig (i_la_ext_trig ),
.i_cap_data (i_la_data ),
.i_trigger (r_trigger ),
.i_trigger_mask (r_trigger_mask ),
.i_trigger_after (r_trigger_after ),
.i_trigger_edge (r_trigger_edge ),
.i_both_edges (r_both_edges ),
.i_repeat_count (r_repeat_count ),
.i_enable (r_ctr_en_la ),
.i_restart (r_ctr_restart_la ),
.o_capture_start (w_start_pos ),
.o_finished (w_finished ),
.o_capture_size (w_cap_data_size ),
.i_force_stb (w_force_stb ),
.i_bram_addr (w_la_read_addr ),
.o_bram_data (w_bram_read_data )
);
//Asynchronous Logic
assign w_posedge_cyc = ( i_wbs_cyc & !r_prev_cyc);
//Synchronous Logic
always @ (posedge clk) begin
r_ctr_restart_la <= 0;
r_force_stb <= 0;
r_ctr_rst <= 0;
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
r_trigger <= 0;
r_trigger_mask <= 0;
r_trigger_after <= 0;
r_trigger_edge <= 0;
r_both_edges <= 0;
r_clock_divider <= 0;
r_repeat_count <= 0;
r_data_read_en <= 0;
r_data_read_count <= 0;
r_ctr_int_en <= 0;
r_ctr_en_la <= 0;
r_bram_read_addr <= 0;
r_bram_sleep <= 0;
r_prev_cyc <= 0;
r_uart_en <= 1;
end
else begin
if (r_ctr_restart_la) begin
r_ctr_en_la <= 1;
end
if (r_ctr_rst) begin
r_ctr_en_la <= 0;
end
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
CONTROL: begin
r_ctr_rst <= i_wbs_dat[`CONTROL_RESET];
r_ctr_int_en <= i_wbs_dat[`CONTROL_ENABLE_INTERRUPT];
r_ctr_en_la <= i_wbs_dat[`CONTROL_ENABLE_LA];
r_ctr_restart_la <= i_wbs_dat[`CONTROL_RESTART_LA];
r_force_stb <= i_wbs_dat[`CONTROL_FORCE_STB];
r_uart_en <= i_wbs_dat[`CONTROL_ENABLE_UART];
end
TRIGGER: begin
r_trigger <= i_wbs_dat;
end
TRIGGER_MASK: begin
r_trigger_mask <= i_wbs_dat;
end
TRIGGER_AFTER: begin
r_trigger_after <= i_wbs_dat;
end
TRIGGER_EDGE: begin
r_trigger_edge <= i_wbs_dat;
end
BOTH_EDGES: begin
r_both_edges <= i_wbs_dat;
end
REPEAT_COUNT: begin
r_repeat_count <= i_wbs_dat;
end
default: begin
end
endcase
o_wbs_ack <= 1;
end
else begin
//read request
case (i_wbs_adr)
CONTROL: begin
o_wbs_dat <= 0;
o_wbs_dat[`CONTROL_RESET] <= r_ctr_rst;
o_wbs_dat[`CONTROL_ENABLE_INTERRUPT] <= r_ctr_int_en;
o_wbs_dat[`CONTROL_ENABLE_LA] <= r_ctr_en_la;
o_wbs_dat[`CONTROL_RESTART_LA] <= r_ctr_restart_la;
o_wbs_dat[`CONTROL_ENABLE_UART] <= r_uart_en;
o_wbs_ack <= 1;
end
STATUS: begin
o_wbs_dat <= 0;
o_wbs_dat[`STATUS_FINISHED] <= w_finished;
o_wbs_ack <= 1;
end
TRIGGER: begin
o_wbs_dat <= r_trigger;
o_wbs_ack <= 1;
end
TRIGGER_MASK: begin
o_wbs_dat <= r_trigger_mask;
o_wbs_ack <= 1;
end
TRIGGER_AFTER: begin
o_wbs_dat <= r_trigger_after;
o_wbs_ack <= 1;
end
TRIGGER_EDGE: begin
o_wbs_dat <= r_trigger_edge;
o_wbs_ack <= 1;
end
BOTH_EDGES: begin
o_wbs_dat <= r_both_edges;
o_wbs_ack <= 1;
end
REPEAT_COUNT: begin
o_wbs_dat <= r_repeat_count;
o_wbs_ack <= 1;
end
DATA_COUNT: begin
o_wbs_dat <= w_cap_data_size;
o_wbs_ack <= 1;
end
START_POS: begin
o_wbs_dat <= w_start_pos;
o_wbs_ack <= 1;
end
CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
o_wbs_ack <= 1;
end
READ_DATA: begin
if (!r_data_read_en) begin
r_bram_sleep <= 0;
r_data_read_en <= 1;
end
else begin
if (r_bram_sleep < `SLEEP_COUNT) begin
r_bram_sleep <= r_bram_sleep + 1;
end
else begin
o_wbs_dat <= w_bram_read_data;
r_bram_read_addr <= r_bram_read_addr + 1;
r_data_read_en <= 0;
o_wbs_ack <= 1;
end
end
end
default: begin
o_wbs_dat <= 0;
o_wbs_ack <= 1;
end
endcase
end
end
end
r_prev_cyc <= i_wbs_cyc;
if (w_posedge_cyc) begin
//At the beginning of a cycle reset the data read count
r_data_read_count <= 0;
r_bram_read_addr <= 0;
end
o_wbs_int <= 0;
if (r_ctr_int_en && w_finished) begin
o_wbs_int <= 1;
end
if (r_uart_en) begin
r_ctr_en_la <= w_uart_la_en;
r_ctr_rst <= w_uart_la_reset;
r_force_stb <= w_uart_force_trig;
if (w_uart_set_stb) begin
r_trigger <= w_uart_trigger;
r_trigger_mask <= w_uart_trigger_mask;
r_trigger_after <= w_uart_trigger_after;
r_trigger_edge <= w_uart_trigger_edge;
r_both_edges <= w_uart_both_edges;
r_repeat_count <= w_uart_repeat_count;
end
end
end
end
endmodule
|
//======================================================================
//
// tb_vndecorrelator.v
// -------------------
// Testbench for the von Neumann decorrelator.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_vndecorrelator();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_data_in;
reg tb_syn_in;
wire tb_data_out;
wire tb_syn_out;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
vndecorrelator dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.data_in(tb_data_in),
.syn_in(tb_syn_in),
.data_out(tb_data_out),
.syn_out(tb_syn_out)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (DEBUG)
begin
$display("cycle = %016x:", cycle_ctr);
$display("reset_n = 0x%01x", dut.reset_n);
$display("data_in = 0x%01x, syn_in = 0x%01x", dut.data_in, dut.syn_in);
$display("data_out = 0x%01x, syn_out = 0x%01x", dut.data_out, dut.syn_out);
$display("ctrl = 0x%01x", dut.vndecorr_ctrl_reg);
$display("");
end
end // dut_monitor
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_data_in = 0;
tb_syn_in = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// decorrelation_test
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : decorrelation_test
$display(" -= Testbench for the vpn Neumann decorrelator =-");
$display(" ===============================================");
$display("");
init_sim();
reset_dut();
// TC1: 1, 0 directly after eachother. Should emit 0.
#(10 *CLK_PERIOD);
$display("TC1: 1 directly followed by 0. Should emit 0.");
tb_data_in = 1;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_data_in = 0;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
// TC2: 0, 1 directly after eachother. Should generate 1.
#(10 *CLK_PERIOD);
$display("TC2: 0 directly followed by 1. Should emit 1.");
tb_data_in = 0;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_data_in = 1;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
// TC3: 0, 0 directly after eachother. Should emit nothing.
#(10 *CLK_PERIOD);
$display("TC3: 0 directly followed by 0. Should emit nothing.");
tb_data_in = 0;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_data_in = 0;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
// TC4: 1, 1 directly after eachother. Should enmit nothing.
#(10 *CLK_PERIOD);
$display("TC4: 1 directly followed by 1. Should emit nothing.");
tb_data_in = 1;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_data_in = 1;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
// TC5: 1, 0 with 10 cycles in between. Should emit 0.
#(10 *CLK_PERIOD);
$display("TC5: 1 and later 0. Should emit 0.");
tb_data_in = 1;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
#(10 *CLK_PERIOD);
tb_data_in = 0;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
// TC6: 0, 1 with 10 cycles in between. Should emit 1.
#(10 *CLK_PERIOD);
$display("TC6: 0 and later 1. Should emit 1.");
tb_data_in = 0;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
#(10 *CLK_PERIOD);
tb_data_in = 1;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
// TC7: 0, 0 with 10 cycles in between. Should emit nothing.
#(10 *CLK_PERIOD);
$display("TC7: 0 and later 0. Should emit nothing.");
tb_data_in = 0;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
#(10 *CLK_PERIOD);
tb_data_in = 0;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
// TC8: 1, 1 with 10 cycles in between. Should emit nothing.
#(10 *CLK_PERIOD);
$display("TC8: 1 and later 1. Should emit nothing.");
tb_data_in = 1;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
#(10 *CLK_PERIOD);
tb_data_in = 1;
tb_syn_in = 1;
#(CLK_PERIOD);
tb_syn_in = 0;
$display("");
$display("*** von Neumann decorrelation simulation done. ***");
$finish;
end // decorrelation_test
endmodule // tb_vndecorrelator
//======================================================================
// EOF tb_vndecorrelator.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O221AI_BEHAVIORAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_BEHAVIORAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Xess Traffic Cop ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// This block connectes the RISC and peripheral controller ////
//// cores together. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 OpenCores ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: tc_top.v,v $
// Revision 1.2 2006-12-22 17:16:26 vak
// Added comments and copyrights.
//
// Revision 1.1 2006/12/21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.4 2004/04/05 08:44:34 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2 2002/03/29 20:57:30 lampret
// Removed unused ports wb_clki and wb_rst_i
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
//
// Width of address bus
//
`define TC_AW 32
//
// Width of data bus
//
`define TC_DW 32
//
// Width of byte select bus
//
`define TC_BSW 4
//
// Width of WB target inputs (coming from WB slave)
//
// data bus width + ack + err
//
`define TC_TIN_W `TC_DW+1+1
//
// Width of WB initiator inputs (coming from WB masters)
//
// cyc + stb + cab + address bus width +
// byte select bus width + we + data bus width
//
`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
//
// Traffic Cop Top
//
module tc_top (
wb_clk_i,
wb_rst_i,
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_cab_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
i0_wb_dat_i,
i0_wb_dat_o,
i0_wb_ack_o,
i0_wb_err_o,
i1_wb_cyc_i,
i1_wb_stb_i,
i1_wb_cab_i,
i1_wb_adr_i,
i1_wb_sel_i,
i1_wb_we_i,
i1_wb_dat_i,
i1_wb_dat_o,
i1_wb_ack_o,
i1_wb_err_o,
i2_wb_cyc_i,
i2_wb_stb_i,
i2_wb_cab_i,
i2_wb_adr_i,
i2_wb_sel_i,
i2_wb_we_i,
i2_wb_dat_i,
i2_wb_dat_o,
i2_wb_ack_o,
i2_wb_err_o,
i3_wb_cyc_i,
i3_wb_stb_i,
i3_wb_cab_i,
i3_wb_adr_i,
i3_wb_sel_i,
i3_wb_we_i,
i3_wb_dat_i,
i3_wb_dat_o,
i3_wb_ack_o,
i3_wb_err_o,
i4_wb_cyc_i,
i4_wb_stb_i,
i4_wb_cab_i,
i4_wb_adr_i,
i4_wb_sel_i,
i4_wb_we_i,
i4_wb_dat_i,
i4_wb_dat_o,
i4_wb_ack_o,
i4_wb_err_o,
i5_wb_cyc_i,
i5_wb_stb_i,
i5_wb_cab_i,
i5_wb_adr_i,
i5_wb_sel_i,
i5_wb_we_i,
i5_wb_dat_i,
i5_wb_dat_o,
i5_wb_ack_o,
i5_wb_err_o,
i6_wb_cyc_i,
i6_wb_stb_i,
i6_wb_cab_i,
i6_wb_adr_i,
i6_wb_sel_i,
i6_wb_we_i,
i6_wb_dat_i,
i6_wb_dat_o,
i6_wb_ack_o,
i6_wb_err_o,
i7_wb_cyc_i,
i7_wb_stb_i,
i7_wb_cab_i,
i7_wb_adr_i,
i7_wb_sel_i,
i7_wb_we_i,
i7_wb_dat_i,
i7_wb_dat_o,
i7_wb_ack_o,
i7_wb_err_o,
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_cab_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
t0_wb_dat_o,
t0_wb_dat_i,
t0_wb_ack_i,
t0_wb_err_i,
t1_wb_cyc_o,
t1_wb_stb_o,
t1_wb_cab_o,
t1_wb_adr_o,
t1_wb_sel_o,
t1_wb_we_o,
t1_wb_dat_o,
t1_wb_dat_i,
t1_wb_ack_i,
t1_wb_err_i,
t2_wb_cyc_o,
t2_wb_stb_o,
t2_wb_cab_o,
t2_wb_adr_o,
t2_wb_sel_o,
t2_wb_we_o,
t2_wb_dat_o,
t2_wb_dat_i,
t2_wb_ack_i,
t2_wb_err_i,
t3_wb_cyc_o,
t3_wb_stb_o,
t3_wb_cab_o,
t3_wb_adr_o,
t3_wb_sel_o,
t3_wb_we_o,
t3_wb_dat_o,
t3_wb_dat_i,
t3_wb_ack_i,
t3_wb_err_i,
t4_wb_cyc_o,
t4_wb_stb_o,
t4_wb_cab_o,
t4_wb_adr_o,
t4_wb_sel_o,
t4_wb_we_o,
t4_wb_dat_o,
t4_wb_dat_i,
t4_wb_ack_i,
t4_wb_err_i,
t5_wb_cyc_o,
t5_wb_stb_o,
t5_wb_cab_o,
t5_wb_adr_o,
t5_wb_sel_o,
t5_wb_we_o,
t5_wb_dat_o,
t5_wb_dat_i,
t5_wb_ack_i,
t5_wb_err_i,
t6_wb_cyc_o,
t6_wb_stb_o,
t6_wb_cab_o,
t6_wb_adr_o,
t6_wb_sel_o,
t6_wb_we_o,
t6_wb_dat_o,
t6_wb_dat_i,
t6_wb_ack_i,
t6_wb_err_i,
t7_wb_cyc_o,
t7_wb_stb_o,
t7_wb_cab_o,
t7_wb_adr_o,
t7_wb_sel_o,
t7_wb_we_o,
t7_wb_dat_o,
t7_wb_dat_i,
t7_wb_ack_i,
t7_wb_err_i,
t8_wb_cyc_o,
t8_wb_stb_o,
t8_wb_cab_o,
t8_wb_adr_o,
t8_wb_sel_o,
t8_wb_we_o,
t8_wb_dat_o,
t8_wb_dat_i,
t8_wb_ack_i,
t8_wb_err_i
);
//
// Parameters
//
parameter t0_addr_w = 4;
parameter t0_addr = 4'd8;
parameter t1_addr_w = 4;
parameter t1_addr = 4'd0;
parameter t28c_addr_w = 4;
parameter t28_addr = 4'd0;
parameter t28i_addr_w = 4;
parameter t2_addr = 4'd1;
parameter t3_addr = 4'd2;
parameter t4_addr = 4'd3;
parameter t5_addr = 4'd4;
parameter t6_addr = 4'd5;
parameter t7_addr = 4'd6;
parameter t8_addr = 4'd7;
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f connecting initiator 0
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input i0_wb_cab_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
input [`TC_DW-1:0] i0_wb_dat_i;
output [`TC_DW-1:0] i0_wb_dat_o;
output i0_wb_ack_o;
output i0_wb_err_o;
//
// WB slave i/f connecting initiator 1
//
input i1_wb_cyc_i;
input i1_wb_stb_i;
input i1_wb_cab_i;
input [`TC_AW-1:0] i1_wb_adr_i;
input [`TC_BSW-1:0] i1_wb_sel_i;
input i1_wb_we_i;
input [`TC_DW-1:0] i1_wb_dat_i;
output [`TC_DW-1:0] i1_wb_dat_o;
output i1_wb_ack_o;
output i1_wb_err_o;
//
// WB slave i/f connecting initiator 2
//
input i2_wb_cyc_i;
input i2_wb_stb_i;
input i2_wb_cab_i;
input [`TC_AW-1:0] i2_wb_adr_i;
input [`TC_BSW-1:0] i2_wb_sel_i;
input i2_wb_we_i;
input [`TC_DW-1:0] i2_wb_dat_i;
output [`TC_DW-1:0] i2_wb_dat_o;
output i2_wb_ack_o;
output i2_wb_err_o;
//
// WB slave i/f connecting initiator 3
//
input i3_wb_cyc_i;
input i3_wb_stb_i;
input i3_wb_cab_i;
input [`TC_AW-1:0] i3_wb_adr_i;
input [`TC_BSW-1:0] i3_wb_sel_i;
input i3_wb_we_i;
input [`TC_DW-1:0] i3_wb_dat_i;
output [`TC_DW-1:0] i3_wb_dat_o;
output i3_wb_ack_o;
output i3_wb_err_o;
//
// WB slave i/f connecting initiator 4
//
input i4_wb_cyc_i;
input i4_wb_stb_i;
input i4_wb_cab_i;
input [`TC_AW-1:0] i4_wb_adr_i;
input [`TC_BSW-1:0] i4_wb_sel_i;
input i4_wb_we_i;
input [`TC_DW-1:0] i4_wb_dat_i;
output [`TC_DW-1:0] i4_wb_dat_o;
output i4_wb_ack_o;
output i4_wb_err_o;
//
// WB slave i/f connecting initiator 5
//
input i5_wb_cyc_i;
input i5_wb_stb_i;
input i5_wb_cab_i;
input [`TC_AW-1:0] i5_wb_adr_i;
input [`TC_BSW-1:0] i5_wb_sel_i;
input i5_wb_we_i;
input [`TC_DW-1:0] i5_wb_dat_i;
output [`TC_DW-1:0] i5_wb_dat_o;
output i5_wb_ack_o;
output i5_wb_err_o;
//
// WB slave i/f connecting initiator 6
//
input i6_wb_cyc_i;
input i6_wb_stb_i;
input i6_wb_cab_i;
input [`TC_AW-1:0] i6_wb_adr_i;
input [`TC_BSW-1:0] i6_wb_sel_i;
input i6_wb_we_i;
input [`TC_DW-1:0] i6_wb_dat_i;
output [`TC_DW-1:0] i6_wb_dat_o;
output i6_wb_ack_o;
output i6_wb_err_o;
//
// WB slave i/f connecting initiator 7
//
input i7_wb_cyc_i;
input i7_wb_stb_i;
input i7_wb_cab_i;
input [`TC_AW-1:0] i7_wb_adr_i;
input [`TC_BSW-1:0] i7_wb_sel_i;
input i7_wb_we_i;
input [`TC_DW-1:0] i7_wb_dat_i;
output [`TC_DW-1:0] i7_wb_dat_o;
output i7_wb_ack_o;
output i7_wb_err_o;
//
// WB master i/f connecting target 0
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output t0_wb_cab_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
output [`TC_DW-1:0] t0_wb_dat_o;
input [`TC_DW-1:0] t0_wb_dat_i;
input t0_wb_ack_i;
input t0_wb_err_i;
//
// WB master i/f connecting target 1
//
output t1_wb_cyc_o;
output t1_wb_stb_o;
output t1_wb_cab_o;
output [`TC_AW-1:0] t1_wb_adr_o;
output [`TC_BSW-1:0] t1_wb_sel_o;
output t1_wb_we_o;
output [`TC_DW-1:0] t1_wb_dat_o;
input [`TC_DW-1:0] t1_wb_dat_i;
input t1_wb_ack_i;
input t1_wb_err_i;
//
// WB master i/f connecting target 2
//
output t2_wb_cyc_o;
output t2_wb_stb_o;
output t2_wb_cab_o;
output [`TC_AW-1:0] t2_wb_adr_o;
output [`TC_BSW-1:0] t2_wb_sel_o;
output t2_wb_we_o;
output [`TC_DW-1:0] t2_wb_dat_o;
input [`TC_DW-1:0] t2_wb_dat_i;
input t2_wb_ack_i;
input t2_wb_err_i;
//
// WB master i/f connecting target 3
//
output t3_wb_cyc_o;
output t3_wb_stb_o;
output t3_wb_cab_o;
output [`TC_AW-1:0] t3_wb_adr_o;
output [`TC_BSW-1:0] t3_wb_sel_o;
output t3_wb_we_o;
output [`TC_DW-1:0] t3_wb_dat_o;
input [`TC_DW-1:0] t3_wb_dat_i;
input t3_wb_ack_i;
input t3_wb_err_i;
//
// WB master i/f connecting target 4
//
output t4_wb_cyc_o;
output t4_wb_stb_o;
output t4_wb_cab_o;
output [`TC_AW-1:0] t4_wb_adr_o;
output [`TC_BSW-1:0] t4_wb_sel_o;
output t4_wb_we_o;
output [`TC_DW-1:0] t4_wb_dat_o;
input [`TC_DW-1:0] t4_wb_dat_i;
input t4_wb_ack_i;
input t4_wb_err_i;
//
// WB master i/f connecting target 5
//
output t5_wb_cyc_o;
output t5_wb_stb_o;
output t5_wb_cab_o;
output [`TC_AW-1:0] t5_wb_adr_o;
output [`TC_BSW-1:0] t5_wb_sel_o;
output t5_wb_we_o;
output [`TC_DW-1:0] t5_wb_dat_o;
input [`TC_DW-1:0] t5_wb_dat_i;
input t5_wb_ack_i;
input t5_wb_err_i;
//
// WB master i/f connecting target 6
//
output t6_wb_cyc_o;
output t6_wb_stb_o;
output t6_wb_cab_o;
output [`TC_AW-1:0] t6_wb_adr_o;
output [`TC_BSW-1:0] t6_wb_sel_o;
output t6_wb_we_o;
output [`TC_DW-1:0] t6_wb_dat_o;
input [`TC_DW-1:0] t6_wb_dat_i;
input t6_wb_ack_i;
input t6_wb_err_i;
//
// WB master i/f connecting target 7
//
output t7_wb_cyc_o;
output t7_wb_stb_o;
output t7_wb_cab_o;
output [`TC_AW-1:0] t7_wb_adr_o;
output [`TC_BSW-1:0] t7_wb_sel_o;
output t7_wb_we_o;
output [`TC_DW-1:0] t7_wb_dat_o;
input [`TC_DW-1:0] t7_wb_dat_i;
input t7_wb_ack_i;
input t7_wb_err_i;
//
// WB master i/f connecting target 8
//
output t8_wb_cyc_o;
output t8_wb_stb_o;
output t8_wb_cab_o;
output [`TC_AW-1:0] t8_wb_adr_o;
output [`TC_BSW-1:0] t8_wb_sel_o;
output t8_wb_we_o;
output [`TC_DW-1:0] t8_wb_dat_o;
input [`TC_DW-1:0] t8_wb_dat_i;
input t8_wb_ack_i;
input t8_wb_err_i;
//
// Internal wires & registers
//
//
// Outputs for initiators from both mi_to_st blocks
//
wire [`TC_DW-1:0] xi0_wb_dat_o;
wire xi0_wb_ack_o;
wire xi0_wb_err_o;
wire [`TC_DW-1:0] xi1_wb_dat_o;
wire xi1_wb_ack_o;
wire xi1_wb_err_o;
wire [`TC_DW-1:0] xi2_wb_dat_o;
wire xi2_wb_ack_o;
wire xi2_wb_err_o;
wire [`TC_DW-1:0] xi3_wb_dat_o;
wire xi3_wb_ack_o;
wire xi3_wb_err_o;
wire [`TC_DW-1:0] xi4_wb_dat_o;
wire xi4_wb_ack_o;
wire xi4_wb_err_o;
wire [`TC_DW-1:0] xi5_wb_dat_o;
wire xi5_wb_ack_o;
wire xi5_wb_err_o;
wire [`TC_DW-1:0] xi6_wb_dat_o;
wire xi6_wb_ack_o;
wire xi6_wb_err_o;
wire [`TC_DW-1:0] xi7_wb_dat_o;
wire xi7_wb_ack_o;
wire xi7_wb_err_o;
wire [`TC_DW-1:0] yi0_wb_dat_o;
wire yi0_wb_ack_o;
wire yi0_wb_err_o;
wire [`TC_DW-1:0] yi1_wb_dat_o;
wire yi1_wb_ack_o;
wire yi1_wb_err_o;
wire [`TC_DW-1:0] yi2_wb_dat_o;
wire yi2_wb_ack_o;
wire yi2_wb_err_o;
wire [`TC_DW-1:0] yi3_wb_dat_o;
wire yi3_wb_ack_o;
wire yi3_wb_err_o;
wire [`TC_DW-1:0] yi4_wb_dat_o;
wire yi4_wb_ack_o;
wire yi4_wb_err_o;
wire [`TC_DW-1:0] yi5_wb_dat_o;
wire yi5_wb_ack_o;
wire yi5_wb_err_o;
wire [`TC_DW-1:0] yi6_wb_dat_o;
wire yi6_wb_ack_o;
wire yi6_wb_err_o;
wire [`TC_DW-1:0] yi7_wb_dat_o;
wire yi7_wb_ack_o;
wire yi7_wb_err_o;
//
// Intermediate signals connecting peripheral channel's
// mi_to_st and si_to_mt blocks.
//
wire z_wb_cyc_i;
wire z_wb_stb_i;
wire z_wb_cab_i;
wire [`TC_AW-1:0] z_wb_adr_i;
wire [`TC_BSW-1:0] z_wb_sel_i;
wire z_wb_we_i;
wire [`TC_DW-1:0] z_wb_dat_i;
wire [`TC_DW-1:0] z_wb_dat_t;
wire z_wb_ack_t;
wire z_wb_err_t;
//
// Outputs for initiators are ORed from both mi_to_st blocks
//
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o;
assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o;
assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o;
assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o;
assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o;
assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o;
assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o;
assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o;
assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o;
assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o;
assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o;
assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o;
assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o;
assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o;
assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o;
assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o;
assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o;
assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o;
assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o;
assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o;
assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o;
assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o;
//
// From initiators to target 0
//
tc_mi_to_st #(t0_addr_w, t0_addr,
0, t0_addr_w, t0_addr) t0_ch(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.i0_wb_cyc_i(i0_wb_cyc_i),
.i0_wb_stb_i(i0_wb_stb_i),
.i0_wb_cab_i(i0_wb_cab_i),
.i0_wb_adr_i(i0_wb_adr_i),
.i0_wb_sel_i(i0_wb_sel_i),
.i0_wb_we_i(i0_wb_we_i),
.i0_wb_dat_i(i0_wb_dat_i),
.i0_wb_dat_o(xi0_wb_dat_o),
.i0_wb_ack_o(xi0_wb_ack_o),
.i0_wb_err_o(xi0_wb_err_o),
.i1_wb_cyc_i(i1_wb_cyc_i),
.i1_wb_stb_i(i1_wb_stb_i),
.i1_wb_cab_i(i1_wb_cab_i),
.i1_wb_adr_i(i1_wb_adr_i),
.i1_wb_sel_i(i1_wb_sel_i),
.i1_wb_we_i(i1_wb_we_i),
.i1_wb_dat_i(i1_wb_dat_i),
.i1_wb_dat_o(xi1_wb_dat_o),
.i1_wb_ack_o(xi1_wb_ack_o),
.i1_wb_err_o(xi1_wb_err_o),
.i2_wb_cyc_i(i2_wb_cyc_i),
.i2_wb_stb_i(i2_wb_stb_i),
.i2_wb_cab_i(i2_wb_cab_i),
.i2_wb_adr_i(i2_wb_adr_i),
.i2_wb_sel_i(i2_wb_sel_i),
.i2_wb_we_i(i2_wb_we_i),
.i2_wb_dat_i(i2_wb_dat_i),
.i2_wb_dat_o(xi2_wb_dat_o),
.i2_wb_ack_o(xi2_wb_ack_o),
.i2_wb_err_o(xi2_wb_err_o),
.i3_wb_cyc_i(i3_wb_cyc_i),
.i3_wb_stb_i(i3_wb_stb_i),
.i3_wb_cab_i(i3_wb_cab_i),
.i3_wb_adr_i(i3_wb_adr_i),
.i3_wb_sel_i(i3_wb_sel_i),
.i3_wb_we_i(i3_wb_we_i),
.i3_wb_dat_i(i3_wb_dat_i),
.i3_wb_dat_o(xi3_wb_dat_o),
.i3_wb_ack_o(xi3_wb_ack_o),
.i3_wb_err_o(xi3_wb_err_o),
.i4_wb_cyc_i(i4_wb_cyc_i),
.i4_wb_stb_i(i4_wb_stb_i),
.i4_wb_cab_i(i4_wb_cab_i),
.i4_wb_adr_i(i4_wb_adr_i),
.i4_wb_sel_i(i4_wb_sel_i),
.i4_wb_we_i(i4_wb_we_i),
.i4_wb_dat_i(i4_wb_dat_i),
.i4_wb_dat_o(xi4_wb_dat_o),
.i4_wb_ack_o(xi4_wb_ack_o),
.i4_wb_err_o(xi4_wb_err_o),
.i5_wb_cyc_i(i5_wb_cyc_i),
.i5_wb_stb_i(i5_wb_stb_i),
.i5_wb_cab_i(i5_wb_cab_i),
.i5_wb_adr_i(i5_wb_adr_i),
.i5_wb_sel_i(i5_wb_sel_i),
.i5_wb_we_i(i5_wb_we_i),
.i5_wb_dat_i(i5_wb_dat_i),
.i5_wb_dat_o(xi5_wb_dat_o),
.i5_wb_ack_o(xi5_wb_ack_o),
.i5_wb_err_o(xi5_wb_err_o),
.i6_wb_cyc_i(i6_wb_cyc_i),
.i6_wb_stb_i(i6_wb_stb_i),
.i6_wb_cab_i(i6_wb_cab_i),
.i6_wb_adr_i(i6_wb_adr_i),
.i6_wb_sel_i(i6_wb_sel_i),
.i6_wb_we_i(i6_wb_we_i),
.i6_wb_dat_i(i6_wb_dat_i),
.i6_wb_dat_o(xi6_wb_dat_o),
.i6_wb_ack_o(xi6_wb_ack_o),
.i6_wb_err_o(xi6_wb_err_o),
.i7_wb_cyc_i(i7_wb_cyc_i),
.i7_wb_stb_i(i7_wb_stb_i),
.i7_wb_cab_i(i7_wb_cab_i),
.i7_wb_adr_i(i7_wb_adr_i),
.i7_wb_sel_i(i7_wb_sel_i),
.i7_wb_we_i(i7_wb_we_i),
.i7_wb_dat_i(i7_wb_dat_i),
.i7_wb_dat_o(xi7_wb_dat_o),
.i7_wb_ack_o(xi7_wb_ack_o),
.i7_wb_err_o(xi7_wb_err_o),
.t0_wb_cyc_o(t0_wb_cyc_o),
.t0_wb_stb_o(t0_wb_stb_o),
.t0_wb_cab_o(t0_wb_cab_o),
.t0_wb_adr_o(t0_wb_adr_o),
.t0_wb_sel_o(t0_wb_sel_o),
.t0_wb_we_o(t0_wb_we_o),
.t0_wb_dat_o(t0_wb_dat_o),
.t0_wb_dat_i(t0_wb_dat_i),
.t0_wb_ack_i(t0_wb_ack_i),
.t0_wb_err_i(t0_wb_err_i)
);
//
// From initiators to targets 1-8 (upper part)
//
tc_mi_to_st #(t1_addr_w, t1_addr,
1, t28c_addr_w, t28_addr) t18_ch_upper(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.i0_wb_cyc_i(i0_wb_cyc_i),
.i0_wb_stb_i(i0_wb_stb_i),
.i0_wb_cab_i(i0_wb_cab_i),
.i0_wb_adr_i(i0_wb_adr_i),
.i0_wb_sel_i(i0_wb_sel_i),
.i0_wb_we_i(i0_wb_we_i),
.i0_wb_dat_i(i0_wb_dat_i),
.i0_wb_dat_o(yi0_wb_dat_o),
.i0_wb_ack_o(yi0_wb_ack_o),
.i0_wb_err_o(yi0_wb_err_o),
.i1_wb_cyc_i(i1_wb_cyc_i),
.i1_wb_stb_i(i1_wb_stb_i),
.i1_wb_cab_i(i1_wb_cab_i),
.i1_wb_adr_i(i1_wb_adr_i),
.i1_wb_sel_i(i1_wb_sel_i),
.i1_wb_we_i(i1_wb_we_i),
.i1_wb_dat_i(i1_wb_dat_i),
.i1_wb_dat_o(yi1_wb_dat_o),
.i1_wb_ack_o(yi1_wb_ack_o),
.i1_wb_err_o(yi1_wb_err_o),
.i2_wb_cyc_i(i2_wb_cyc_i),
.i2_wb_stb_i(i2_wb_stb_i),
.i2_wb_cab_i(i2_wb_cab_i),
.i2_wb_adr_i(i2_wb_adr_i),
.i2_wb_sel_i(i2_wb_sel_i),
.i2_wb_we_i(i2_wb_we_i),
.i2_wb_dat_i(i2_wb_dat_i),
.i2_wb_dat_o(yi2_wb_dat_o),
.i2_wb_ack_o(yi2_wb_ack_o),
.i2_wb_err_o(yi2_wb_err_o),
.i3_wb_cyc_i(i3_wb_cyc_i),
.i3_wb_stb_i(i3_wb_stb_i),
.i3_wb_cab_i(i3_wb_cab_i),
.i3_wb_adr_i(i3_wb_adr_i),
.i3_wb_sel_i(i3_wb_sel_i),
.i3_wb_we_i(i3_wb_we_i),
.i3_wb_dat_i(i3_wb_dat_i),
.i3_wb_dat_o(yi3_wb_dat_o),
.i3_wb_ack_o(yi3_wb_ack_o),
.i3_wb_err_o(yi3_wb_err_o),
.i4_wb_cyc_i(i4_wb_cyc_i),
.i4_wb_stb_i(i4_wb_stb_i),
.i4_wb_cab_i(i4_wb_cab_i),
.i4_wb_adr_i(i4_wb_adr_i),
.i4_wb_sel_i(i4_wb_sel_i),
.i4_wb_we_i(i4_wb_we_i),
.i4_wb_dat_i(i4_wb_dat_i),
.i4_wb_dat_o(yi4_wb_dat_o),
.i4_wb_ack_o(yi4_wb_ack_o),
.i4_wb_err_o(yi4_wb_err_o),
.i5_wb_cyc_i(i5_wb_cyc_i),
.i5_wb_stb_i(i5_wb_stb_i),
.i5_wb_cab_i(i5_wb_cab_i),
.i5_wb_adr_i(i5_wb_adr_i),
.i5_wb_sel_i(i5_wb_sel_i),
.i5_wb_we_i(i5_wb_we_i),
.i5_wb_dat_i(i5_wb_dat_i),
.i5_wb_dat_o(yi5_wb_dat_o),
.i5_wb_ack_o(yi5_wb_ack_o),
.i5_wb_err_o(yi5_wb_err_o),
.i6_wb_cyc_i(i6_wb_cyc_i),
.i6_wb_stb_i(i6_wb_stb_i),
.i6_wb_cab_i(i6_wb_cab_i),
.i6_wb_adr_i(i6_wb_adr_i),
.i6_wb_sel_i(i6_wb_sel_i),
.i6_wb_we_i(i6_wb_we_i),
.i6_wb_dat_i(i6_wb_dat_i),
.i6_wb_dat_o(yi6_wb_dat_o),
.i6_wb_ack_o(yi6_wb_ack_o),
.i6_wb_err_o(yi6_wb_err_o),
.i7_wb_cyc_i(i7_wb_cyc_i),
.i7_wb_stb_i(i7_wb_stb_i),
.i7_wb_cab_i(i7_wb_cab_i),
.i7_wb_adr_i(i7_wb_adr_i),
.i7_wb_sel_i(i7_wb_sel_i),
.i7_wb_we_i(i7_wb_we_i),
.i7_wb_dat_i(i7_wb_dat_i),
.i7_wb_dat_o(yi7_wb_dat_o),
.i7_wb_ack_o(yi7_wb_ack_o),
.i7_wb_err_o(yi7_wb_err_o),
.t0_wb_cyc_o(z_wb_cyc_i),
.t0_wb_stb_o(z_wb_stb_i),
.t0_wb_cab_o(z_wb_cab_i),
.t0_wb_adr_o(z_wb_adr_i),
.t0_wb_sel_o(z_wb_sel_i),
.t0_wb_we_o(z_wb_we_i),
.t0_wb_dat_o(z_wb_dat_i),
.t0_wb_dat_i(z_wb_dat_t),
.t0_wb_ack_i(z_wb_ack_t),
.t0_wb_err_i(z_wb_err_t)
);
//
// From initiators to targets 1-8 (lower part)
//
tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,
t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(
.i0_wb_cyc_i(z_wb_cyc_i),
.i0_wb_stb_i(z_wb_stb_i),
.i0_wb_cab_i(z_wb_cab_i),
.i0_wb_adr_i(z_wb_adr_i),
.i0_wb_sel_i(z_wb_sel_i),
.i0_wb_we_i(z_wb_we_i),
.i0_wb_dat_i(z_wb_dat_i),
.i0_wb_dat_o(z_wb_dat_t),
.i0_wb_ack_o(z_wb_ack_t),
.i0_wb_err_o(z_wb_err_t),
.t0_wb_cyc_o(t1_wb_cyc_o),
.t0_wb_stb_o(t1_wb_stb_o),
.t0_wb_cab_o(t1_wb_cab_o),
.t0_wb_adr_o(t1_wb_adr_o),
.t0_wb_sel_o(t1_wb_sel_o),
.t0_wb_we_o(t1_wb_we_o),
.t0_wb_dat_o(t1_wb_dat_o),
.t0_wb_dat_i(t1_wb_dat_i),
.t0_wb_ack_i(t1_wb_ack_i),
.t0_wb_err_i(t1_wb_err_i),
.t1_wb_cyc_o(t2_wb_cyc_o),
.t1_wb_stb_o(t2_wb_stb_o),
.t1_wb_cab_o(t2_wb_cab_o),
.t1_wb_adr_o(t2_wb_adr_o),
.t1_wb_sel_o(t2_wb_sel_o),
.t1_wb_we_o(t2_wb_we_o),
.t1_wb_dat_o(t2_wb_dat_o),
.t1_wb_dat_i(t2_wb_dat_i),
.t1_wb_ack_i(t2_wb_ack_i),
.t1_wb_err_i(t2_wb_err_i),
.t2_wb_cyc_o(t3_wb_cyc_o),
.t2_wb_stb_o(t3_wb_stb_o),
.t2_wb_cab_o(t3_wb_cab_o),
.t2_wb_adr_o(t3_wb_adr_o),
.t2_wb_sel_o(t3_wb_sel_o),
.t2_wb_we_o(t3_wb_we_o),
.t2_wb_dat_o(t3_wb_dat_o),
.t2_wb_dat_i(t3_wb_dat_i),
.t2_wb_ack_i(t3_wb_ack_i),
.t2_wb_err_i(t3_wb_err_i),
.t3_wb_cyc_o(t4_wb_cyc_o),
.t3_wb_stb_o(t4_wb_stb_o),
.t3_wb_cab_o(t4_wb_cab_o),
.t3_wb_adr_o(t4_wb_adr_o),
.t3_wb_sel_o(t4_wb_sel_o),
.t3_wb_we_o(t4_wb_we_o),
.t3_wb_dat_o(t4_wb_dat_o),
.t3_wb_dat_i(t4_wb_dat_i),
.t3_wb_ack_i(t4_wb_ack_i),
.t3_wb_err_i(t4_wb_err_i),
.t4_wb_cyc_o(t5_wb_cyc_o),
.t4_wb_stb_o(t5_wb_stb_o),
.t4_wb_cab_o(t5_wb_cab_o),
.t4_wb_adr_o(t5_wb_adr_o),
.t4_wb_sel_o(t5_wb_sel_o),
.t4_wb_we_o(t5_wb_we_o),
.t4_wb_dat_o(t5_wb_dat_o),
.t4_wb_dat_i(t5_wb_dat_i),
.t4_wb_ack_i(t5_wb_ack_i),
.t4_wb_err_i(t5_wb_err_i),
.t5_wb_cyc_o(t6_wb_cyc_o),
.t5_wb_stb_o(t6_wb_stb_o),
.t5_wb_cab_o(t6_wb_cab_o),
.t5_wb_adr_o(t6_wb_adr_o),
.t5_wb_sel_o(t6_wb_sel_o),
.t5_wb_we_o(t6_wb_we_o),
.t5_wb_dat_o(t6_wb_dat_o),
.t5_wb_dat_i(t6_wb_dat_i),
.t5_wb_ack_i(t6_wb_ack_i),
.t5_wb_err_i(t6_wb_err_i),
.t6_wb_cyc_o(t7_wb_cyc_o),
.t6_wb_stb_o(t7_wb_stb_o),
.t6_wb_cab_o(t7_wb_cab_o),
.t6_wb_adr_o(t7_wb_adr_o),
.t6_wb_sel_o(t7_wb_sel_o),
.t6_wb_we_o(t7_wb_we_o),
.t6_wb_dat_o(t7_wb_dat_o),
.t6_wb_dat_i(t7_wb_dat_i),
.t6_wb_ack_i(t7_wb_ack_i),
.t6_wb_err_i(t7_wb_err_i),
.t7_wb_cyc_o(t8_wb_cyc_o),
.t7_wb_stb_o(t8_wb_stb_o),
.t7_wb_cab_o(t8_wb_cab_o),
.t7_wb_adr_o(t8_wb_adr_o),
.t7_wb_sel_o(t8_wb_sel_o),
.t7_wb_we_o(t8_wb_we_o),
.t7_wb_dat_o(t8_wb_dat_o),
.t7_wb_dat_i(t8_wb_dat_i),
.t7_wb_ack_i(t8_wb_ack_i),
.t7_wb_err_i(t8_wb_err_i)
);
endmodule
//
// Multiple initiator to single target
//
module tc_mi_to_st (
wb_clk_i,
wb_rst_i,
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_cab_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
i0_wb_dat_i,
i0_wb_dat_o,
i0_wb_ack_o,
i0_wb_err_o,
i1_wb_cyc_i,
i1_wb_stb_i,
i1_wb_cab_i,
i1_wb_adr_i,
i1_wb_sel_i,
i1_wb_we_i,
i1_wb_dat_i,
i1_wb_dat_o,
i1_wb_ack_o,
i1_wb_err_o,
i2_wb_cyc_i,
i2_wb_stb_i,
i2_wb_cab_i,
i2_wb_adr_i,
i2_wb_sel_i,
i2_wb_we_i,
i2_wb_dat_i,
i2_wb_dat_o,
i2_wb_ack_o,
i2_wb_err_o,
i3_wb_cyc_i,
i3_wb_stb_i,
i3_wb_cab_i,
i3_wb_adr_i,
i3_wb_sel_i,
i3_wb_we_i,
i3_wb_dat_i,
i3_wb_dat_o,
i3_wb_ack_o,
i3_wb_err_o,
i4_wb_cyc_i,
i4_wb_stb_i,
i4_wb_cab_i,
i4_wb_adr_i,
i4_wb_sel_i,
i4_wb_we_i,
i4_wb_dat_i,
i4_wb_dat_o,
i4_wb_ack_o,
i4_wb_err_o,
i5_wb_cyc_i,
i5_wb_stb_i,
i5_wb_cab_i,
i5_wb_adr_i,
i5_wb_sel_i,
i5_wb_we_i,
i5_wb_dat_i,
i5_wb_dat_o,
i5_wb_ack_o,
i5_wb_err_o,
i6_wb_cyc_i,
i6_wb_stb_i,
i6_wb_cab_i,
i6_wb_adr_i,
i6_wb_sel_i,
i6_wb_we_i,
i6_wb_dat_i,
i6_wb_dat_o,
i6_wb_ack_o,
i6_wb_err_o,
i7_wb_cyc_i,
i7_wb_stb_i,
i7_wb_cab_i,
i7_wb_adr_i,
i7_wb_sel_i,
i7_wb_we_i,
i7_wb_dat_i,
i7_wb_dat_o,
i7_wb_ack_o,
i7_wb_err_o,
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_cab_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
t0_wb_dat_o,
t0_wb_dat_i,
t0_wb_ack_i,
t0_wb_err_i
);
//
// Parameters
//
parameter t0_addr_w = 2;
parameter t0_addr = 2'b00;
parameter multitarg = 1'b0;
parameter t17_addr_w = 2;
parameter t17_addr = 2'b00;
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f connecting initiator 0
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input i0_wb_cab_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
input [`TC_DW-1:0] i0_wb_dat_i;
output [`TC_DW-1:0] i0_wb_dat_o;
output i0_wb_ack_o;
output i0_wb_err_o;
//
// WB slave i/f connecting initiator 1
//
input i1_wb_cyc_i;
input i1_wb_stb_i;
input i1_wb_cab_i;
input [`TC_AW-1:0] i1_wb_adr_i;
input [`TC_BSW-1:0] i1_wb_sel_i;
input i1_wb_we_i;
input [`TC_DW-1:0] i1_wb_dat_i;
output [`TC_DW-1:0] i1_wb_dat_o;
output i1_wb_ack_o;
output i1_wb_err_o;
//
// WB slave i/f connecting initiator 2
//
input i2_wb_cyc_i;
input i2_wb_stb_i;
input i2_wb_cab_i;
input [`TC_AW-1:0] i2_wb_adr_i;
input [`TC_BSW-1:0] i2_wb_sel_i;
input i2_wb_we_i;
input [`TC_DW-1:0] i2_wb_dat_i;
output [`TC_DW-1:0] i2_wb_dat_o;
output i2_wb_ack_o;
output i2_wb_err_o;
//
// WB slave i/f connecting initiator 3
//
input i3_wb_cyc_i;
input i3_wb_stb_i;
input i3_wb_cab_i;
input [`TC_AW-1:0] i3_wb_adr_i;
input [`TC_BSW-1:0] i3_wb_sel_i;
input i3_wb_we_i;
input [`TC_DW-1:0] i3_wb_dat_i;
output [`TC_DW-1:0] i3_wb_dat_o;
output i3_wb_ack_o;
output i3_wb_err_o;
//
// WB slave i/f connecting initiator 4
//
input i4_wb_cyc_i;
input i4_wb_stb_i;
input i4_wb_cab_i;
input [`TC_AW-1:0] i4_wb_adr_i;
input [`TC_BSW-1:0] i4_wb_sel_i;
input i4_wb_we_i;
input [`TC_DW-1:0] i4_wb_dat_i;
output [`TC_DW-1:0] i4_wb_dat_o;
output i4_wb_ack_o;
output i4_wb_err_o;
//
// WB slave i/f connecting initiator 5
//
input i5_wb_cyc_i;
input i5_wb_stb_i;
input i5_wb_cab_i;
input [`TC_AW-1:0] i5_wb_adr_i;
input [`TC_BSW-1:0] i5_wb_sel_i;
input i5_wb_we_i;
input [`TC_DW-1:0] i5_wb_dat_i;
output [`TC_DW-1:0] i5_wb_dat_o;
output i5_wb_ack_o;
output i5_wb_err_o;
//
// WB slave i/f connecting initiator 6
//
input i6_wb_cyc_i;
input i6_wb_stb_i;
input i6_wb_cab_i;
input [`TC_AW-1:0] i6_wb_adr_i;
input [`TC_BSW-1:0] i6_wb_sel_i;
input i6_wb_we_i;
input [`TC_DW-1:0] i6_wb_dat_i;
output [`TC_DW-1:0] i6_wb_dat_o;
output i6_wb_ack_o;
output i6_wb_err_o;
//
// WB slave i/f connecting initiator 7
//
input i7_wb_cyc_i;
input i7_wb_stb_i;
input i7_wb_cab_i;
input [`TC_AW-1:0] i7_wb_adr_i;
input [`TC_BSW-1:0] i7_wb_sel_i;
input i7_wb_we_i;
input [`TC_DW-1:0] i7_wb_dat_i;
output [`TC_DW-1:0] i7_wb_dat_o;
output i7_wb_ack_o;
output i7_wb_err_o;
//
// WB master i/f connecting target
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output t0_wb_cab_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
output [`TC_DW-1:0] t0_wb_dat_o;
input [`TC_DW-1:0] t0_wb_dat_i;
input t0_wb_ack_i;
input t0_wb_err_i;
//
// Internal wires & registers
//
wire [`TC_IIN_W-1:0] i0_in, i1_in,
i2_in, i3_in,
i4_in, i5_in,
i6_in, i7_in;
wire [`TC_TIN_W-1:0] i0_out, i1_out,
i2_out, i3_out,
i4_out, i5_out,
i6_out, i7_out;
wire [`TC_IIN_W-1:0] t0_out;
wire [`TC_TIN_W-1:0] t0_in;
wire [7:0] req_i;
wire [2:0] req_won;
reg req_cont;
reg [2:0] req_r;
//
// Group WB initiator 0 i/f inputs and outputs
//
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_cab_i, i0_wb_adr_i,
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i};
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
//
// Group WB initiator 1 i/f inputs and outputs
//
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_cab_i, i1_wb_adr_i,
i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i};
assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out;
//
// Group WB initiator 2 i/f inputs and outputs
//
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_cab_i, i2_wb_adr_i,
i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i};
assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out;
//
// Group WB initiator 3 i/f inputs and outputs
//
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_cab_i, i3_wb_adr_i,
i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i};
assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out;
//
// Group WB initiator 4 i/f inputs and outputs
//
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_cab_i, i4_wb_adr_i,
i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i};
assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out;
//
// Group WB initiator 5 i/f inputs and outputs
//
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_cab_i, i5_wb_adr_i,
i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i};
assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out;
//
// Group WB initiator 6 i/f inputs and outputs
//
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_cab_i, i6_wb_adr_i,
i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i};
assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out;
//
// Group WB initiator 7 i/f inputs and outputs
//
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_cab_i, i7_wb_adr_i,
i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i};
assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out;
//
// Group WB target 0 i/f inputs and outputs
//
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_cab_o, t0_wb_adr_o,
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out;
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
//
// Assign to WB initiator i/f outputs
//
// Either inputs from the target are assigned or zeros.
//
assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}};
assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}};
assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}};
assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}};
assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}};
assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}};
assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}};
assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}};
//
// Assign to WB target i/f outputs
//
// Assign inputs from initiator to target outputs according to
// which initiator has won. If there is no request for the target,
// assign zeros.
//
assign t0_out = (req_won == 3'd0) ? i0_in :
(req_won == 3'd1) ? i1_in :
(req_won == 3'd2) ? i2_in :
(req_won == 3'd3) ? i3_in :
(req_won == 3'd4) ? i4_in :
(req_won == 3'd5) ? i5_in :
(req_won == 3'd6) ? i6_in :
(req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}};
//
// Determine if an initiator has address of the target.
//
assign req_i[0] = i0_wb_cyc_i &
((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[1] = i1_wb_cyc_i &
((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[2] = i2_wb_cyc_i &
((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[3] = i3_wb_cyc_i &
((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[4] = i4_wb_cyc_i &
((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[5] = i5_wb_cyc_i &
((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[6] = i6_wb_cyc_i &
((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[7] = i7_wb_cyc_i &
((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
//
// Determine who gets current access to the target.
//
// If current initiator still asserts request, do nothing
// (keep current initiator).
// Otherwise check each initiator's request, starting from initiator 0
// (highest priority).
// If there is no requests from initiators, park initiator 0.
//
assign req_won = req_cont ? req_r :
req_i[0] ? 3'd0 :
req_i[1] ? 3'd1 :
req_i[2] ? 3'd2 :
req_i[3] ? 3'd3 :
req_i[4] ? 3'd4 :
req_i[5] ? 3'd5 :
req_i[6] ? 3'd6 :
req_i[7] ? 3'd7 : 3'd0;
//
// Check if current initiator still wants access to the target and if
// it does, assert req_cont.
//
always @(req_r or req_i)
case (req_r) // synopsys parallel_case
3'd0: req_cont = req_i[0];
3'd1: req_cont = req_i[1];
3'd2: req_cont = req_i[2];
3'd3: req_cont = req_i[3];
3'd4: req_cont = req_i[4];
3'd5: req_cont = req_i[5];
3'd6: req_cont = req_i[6];
3'd7: req_cont = req_i[7];
endcase
//
// Register who has current access to the target.
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
req_r <= #1 3'd0;
else
req_r <= #1 req_won;
endmodule
//
// Single initiator to multiple targets
//
module tc_si_to_mt (
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_cab_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
i0_wb_dat_i,
i0_wb_dat_o,
i0_wb_ack_o,
i0_wb_err_o,
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_cab_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
t0_wb_dat_o,
t0_wb_dat_i,
t0_wb_ack_i,
t0_wb_err_i,
t1_wb_cyc_o,
t1_wb_stb_o,
t1_wb_cab_o,
t1_wb_adr_o,
t1_wb_sel_o,
t1_wb_we_o,
t1_wb_dat_o,
t1_wb_dat_i,
t1_wb_ack_i,
t1_wb_err_i,
t2_wb_cyc_o,
t2_wb_stb_o,
t2_wb_cab_o,
t2_wb_adr_o,
t2_wb_sel_o,
t2_wb_we_o,
t2_wb_dat_o,
t2_wb_dat_i,
t2_wb_ack_i,
t2_wb_err_i,
t3_wb_cyc_o,
t3_wb_stb_o,
t3_wb_cab_o,
t3_wb_adr_o,
t3_wb_sel_o,
t3_wb_we_o,
t3_wb_dat_o,
t3_wb_dat_i,
t3_wb_ack_i,
t3_wb_err_i,
t4_wb_cyc_o,
t4_wb_stb_o,
t4_wb_cab_o,
t4_wb_adr_o,
t4_wb_sel_o,
t4_wb_we_o,
t4_wb_dat_o,
t4_wb_dat_i,
t4_wb_ack_i,
t4_wb_err_i,
t5_wb_cyc_o,
t5_wb_stb_o,
t5_wb_cab_o,
t5_wb_adr_o,
t5_wb_sel_o,
t5_wb_we_o,
t5_wb_dat_o,
t5_wb_dat_i,
t5_wb_ack_i,
t5_wb_err_i,
t6_wb_cyc_o,
t6_wb_stb_o,
t6_wb_cab_o,
t6_wb_adr_o,
t6_wb_sel_o,
t6_wb_we_o,
t6_wb_dat_o,
t6_wb_dat_i,
t6_wb_ack_i,
t6_wb_err_i,
t7_wb_cyc_o,
t7_wb_stb_o,
t7_wb_cab_o,
t7_wb_adr_o,
t7_wb_sel_o,
t7_wb_we_o,
t7_wb_dat_o,
t7_wb_dat_i,
t7_wb_ack_i,
t7_wb_err_i
);
//
// Parameters
//
parameter t0_addr_w = 3;
parameter t0_addr = 3'd0;
parameter t17_addr_w = 3;
parameter t1_addr = 3'd1;
parameter t2_addr = 3'd2;
parameter t3_addr = 3'd3;
parameter t4_addr = 3'd4;
parameter t5_addr = 3'd5;
parameter t6_addr = 3'd6;
parameter t7_addr = 3'd7;
//
// I/O Ports
//
//
// WB slave i/f connecting initiator 0
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input i0_wb_cab_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
input [`TC_DW-1:0] i0_wb_dat_i;
output [`TC_DW-1:0] i0_wb_dat_o;
output i0_wb_ack_o;
output i0_wb_err_o;
//
// WB master i/f connecting target 0
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output t0_wb_cab_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
output [`TC_DW-1:0] t0_wb_dat_o;
input [`TC_DW-1:0] t0_wb_dat_i;
input t0_wb_ack_i;
input t0_wb_err_i;
//
// WB master i/f connecting target 1
//
output t1_wb_cyc_o;
output t1_wb_stb_o;
output t1_wb_cab_o;
output [`TC_AW-1:0] t1_wb_adr_o;
output [`TC_BSW-1:0] t1_wb_sel_o;
output t1_wb_we_o;
output [`TC_DW-1:0] t1_wb_dat_o;
input [`TC_DW-1:0] t1_wb_dat_i;
input t1_wb_ack_i;
input t1_wb_err_i;
//
// WB master i/f connecting target 2
//
output t2_wb_cyc_o;
output t2_wb_stb_o;
output t2_wb_cab_o;
output [`TC_AW-1:0] t2_wb_adr_o;
output [`TC_BSW-1:0] t2_wb_sel_o;
output t2_wb_we_o;
output [`TC_DW-1:0] t2_wb_dat_o;
input [`TC_DW-1:0] t2_wb_dat_i;
input t2_wb_ack_i;
input t2_wb_err_i;
//
// WB master i/f connecting target 3
//
output t3_wb_cyc_o;
output t3_wb_stb_o;
output t3_wb_cab_o;
output [`TC_AW-1:0] t3_wb_adr_o;
output [`TC_BSW-1:0] t3_wb_sel_o;
output t3_wb_we_o;
output [`TC_DW-1:0] t3_wb_dat_o;
input [`TC_DW-1:0] t3_wb_dat_i;
input t3_wb_ack_i;
input t3_wb_err_i;
//
// WB master i/f connecting target 4
//
output t4_wb_cyc_o;
output t4_wb_stb_o;
output t4_wb_cab_o;
output [`TC_AW-1:0] t4_wb_adr_o;
output [`TC_BSW-1:0] t4_wb_sel_o;
output t4_wb_we_o;
output [`TC_DW-1:0] t4_wb_dat_o;
input [`TC_DW-1:0] t4_wb_dat_i;
input t4_wb_ack_i;
input t4_wb_err_i;
//
// WB master i/f connecting target 5
//
output t5_wb_cyc_o;
output t5_wb_stb_o;
output t5_wb_cab_o;
output [`TC_AW-1:0] t5_wb_adr_o;
output [`TC_BSW-1:0] t5_wb_sel_o;
output t5_wb_we_o;
output [`TC_DW-1:0] t5_wb_dat_o;
input [`TC_DW-1:0] t5_wb_dat_i;
input t5_wb_ack_i;
input t5_wb_err_i;
//
// WB master i/f connecting target 6
//
output t6_wb_cyc_o;
output t6_wb_stb_o;
output t6_wb_cab_o;
output [`TC_AW-1:0] t6_wb_adr_o;
output [`TC_BSW-1:0] t6_wb_sel_o;
output t6_wb_we_o;
output [`TC_DW-1:0] t6_wb_dat_o;
input [`TC_DW-1:0] t6_wb_dat_i;
input t6_wb_ack_i;
input t6_wb_err_i;
//
// WB master i/f connecting target 7
//
output t7_wb_cyc_o;
output t7_wb_stb_o;
output t7_wb_cab_o;
output [`TC_AW-1:0] t7_wb_adr_o;
output [`TC_BSW-1:0] t7_wb_sel_o;
output t7_wb_we_o;
output [`TC_DW-1:0] t7_wb_dat_o;
input [`TC_DW-1:0] t7_wb_dat_i;
input t7_wb_ack_i;
input t7_wb_err_i;
//
// Internal wires & registers
//
wire [`TC_IIN_W-1:0] i0_in;
wire [`TC_TIN_W-1:0] i0_out;
wire [`TC_IIN_W-1:0] t0_out, t1_out,
t2_out, t3_out,
t4_out, t5_out,
t6_out, t7_out;
wire [`TC_TIN_W-1:0] t0_in, t1_in,
t2_in, t3_in,
t4_in, t5_in,
t6_in, t7_in;
wire [7:0] req_t;
//
// Group WB initiator 0 i/f inputs and outputs
//
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_cab_i, i0_wb_adr_i,
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i};
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
//
// Group WB target 0 i/f inputs and outputs
//
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_cab_o, t0_wb_adr_o,
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out;
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
//
// Group WB target 1 i/f inputs and outputs
//
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_cab_o, t1_wb_adr_o,
t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out;
assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i};
//
// Group WB target 2 i/f inputs and outputs
//
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_cab_o, t2_wb_adr_o,
t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out;
assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i};
//
// Group WB target 3 i/f inputs and outputs
//
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_cab_o, t3_wb_adr_o,
t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out;
assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i};
//
// Group WB target 4 i/f inputs and outputs
//
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_cab_o, t4_wb_adr_o,
t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out;
assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i};
//
// Group WB target 5 i/f inputs and outputs
//
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_cab_o, t5_wb_adr_o,
t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out;
assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i};
//
// Group WB target 6 i/f inputs and outputs
//
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_cab_o, t6_wb_adr_o,
t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out;
assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i};
//
// Group WB target 7 i/f inputs and outputs
//
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_cab_o, t7_wb_adr_o,
t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out;
assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i};
//
// Assign to WB target i/f outputs
//
// Either inputs from the initiator are assigned or zeros.
//
assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}};
assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}};
assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}};
assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}};
assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}};
assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}};
assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}};
assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}};
//
// Assign to WB initiator i/f outputs
//
// Assign inputs from target to initiator outputs according to
// which target is accessed. If there is no request for a target,
// assign zeros.
//
assign i0_out = req_t[0] ? t0_in :
req_t[1] ? t1_in :
req_t[2] ? t2_in :
req_t[3] ? t3_in :
req_t[4] ? t4_in :
req_t[5] ? t5_in :
req_t[6] ? t6_in :
req_t[7] ? t7_in : {`TC_TIN_W{1'b0}};
//
// Determine which target is being accessed.
//
assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr);
assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr);
assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr);
assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr);
assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr);
assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr);
assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr);
assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr);
endmodule
|
module Data_Memory
(
clk_i,
rst_i,
addr_i,
data_i,
enable_i,
write_i,
ack_o,
data_o
);
// Interface
input clk_i;
input rst_i;
input [31:0] addr_i;
input [255:0] data_i;
input enable_i;
input write_i;
output ack_o;
output [255:0] data_o;
// Memory
reg [255:0] memory [0:511]; //16KB
reg [3:0] count;
reg ack;
reg ok;
reg [255:0] data;
wire [26:0] addr;
parameter STATE_IDLE = 3'h0,
STATE_WAIT = 3'h1,
STATE_ACK = 3'h2,
STATE_FINISH = 3'h3;
reg [1:0] state;
assign ack_o = ack;
assign addr = addr_i>>5;
assign data_o = data;
//Controller
always@(posedge clk_i or negedge rst_i) begin
if(~rst_i) begin
count <= 4'b0;
ok <= 1'b0;
ack <= 1'b0;
state <= STATE_IDLE;
end
else begin
case(state)
STATE_IDLE: begin
if(enable_i) begin
count <= count + 1;
state <= STATE_WAIT;
end
else begin
state <= STATE_IDLE;
end
end
STATE_WAIT: begin
if(count == 4'd6) begin
ok <= 1'b1;
state <= STATE_ACK;
end
else begin
count <= count + 1;
state <= STATE_WAIT;
end
end
STATE_ACK: begin
count <= 4'b0;
ok <= 1'b0;
ack <= 1'b1;
state <= STATE_FINISH;
end
STATE_FINISH: begin
ack <= 1'b0;
state <= STATE_IDLE;
end
endcase
end
end
// Read Data
always@(posedge clk_i) begin
if(ok && !write_i) begin
data = memory[addr];
end
end
// Write Data
always@(posedge clk_i) begin
if(ok && write_i) begin
memory[addr] <= data_i;
end
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The decode module to decode the instruction details
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_decode(
//////////////////////////////////////////////////////////////
// The IR stage to Decoder
input [`E203_INSTR_SIZE-1:0] i_instr,
input [`E203_PC_SIZE-1:0] i_pc,
input i_prdt_taken,
input i_misalgn, // The fetch misalign
input i_buserr, // The fetch bus error
input i_muldiv_b2b, // The back2back case for mul/div
input dbg_mode,
//////////////////////////////////////////////////////////////
// The Decoded Info-Bus
output dec_rs1x0,
output dec_rs2x0,
output dec_rs1en,
output dec_rs2en,
output dec_rdwen,
output [`E203_RFIDX_WIDTH-1:0] dec_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] dec_rs2idx,
output [`E203_RFIDX_WIDTH-1:0] dec_rdidx,
output [`E203_DECINFO_WIDTH-1:0] dec_info,
output [`E203_XLEN-1:0] dec_imm,
output [`E203_PC_SIZE-1:0] dec_pc,
output dec_misalgn,
output dec_buserr,
output dec_ilegl,
output dec_mulhsu,
output dec_mul ,
output dec_div ,
output dec_rem ,
output dec_divu ,
output dec_remu ,
output dec_rv32,
output dec_bjp,
output dec_jal,
output dec_jalr,
output dec_bxx,
output [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,
output [`E203_XLEN-1:0] dec_bjp_imm
);
wire [32-1:0] rv32_instr = i_instr;
wire [16-1:0] rv16_instr = i_instr[15:0];
wire [6:0] opcode = rv32_instr[6:0];
wire opcode_1_0_00 = (opcode[1:0] == 2'b00);
wire opcode_1_0_01 = (opcode[1:0] == 2'b01);
wire opcode_1_0_10 = (opcode[1:0] == 2'b10);
wire opcode_1_0_11 = (opcode[1:0] == 2'b11);
wire rv32 = (~(i_instr[4:2] == 3'b111)) & opcode_1_0_11;
wire [4:0] rv32_rd = rv32_instr[11:7];
wire [2:0] rv32_func3 = rv32_instr[14:12];
wire [4:0] rv32_rs1 = rv32_instr[19:15];
wire [4:0] rv32_rs2 = rv32_instr[24:20];
wire [6:0] rv32_func7 = rv32_instr[31:25];
wire [4:0] rv16_rd = rv32_rd;
wire [4:0] rv16_rs1 = rv16_rd;
wire [4:0] rv16_rs2 = rv32_instr[6:2];
wire [4:0] rv16_rdd = {2'b01,rv32_instr[4:2]};
wire [4:0] rv16_rss1 = {2'b01,rv32_instr[9:7]};
wire [4:0] rv16_rss2 = rv16_rdd;
wire [2:0] rv16_func3 = rv32_instr[15:13];
// We generate the signals and reused them as much as possible to save gatecounts
wire opcode_4_2_000 = (opcode[4:2] == 3'b000);
wire opcode_4_2_001 = (opcode[4:2] == 3'b001);
wire opcode_4_2_010 = (opcode[4:2] == 3'b010);
wire opcode_4_2_011 = (opcode[4:2] == 3'b011);
wire opcode_4_2_100 = (opcode[4:2] == 3'b100);
wire opcode_4_2_101 = (opcode[4:2] == 3'b101);
wire opcode_4_2_110 = (opcode[4:2] == 3'b110);
wire opcode_4_2_111 = (opcode[4:2] == 3'b111);
wire opcode_6_5_00 = (opcode[6:5] == 2'b00);
wire opcode_6_5_01 = (opcode[6:5] == 2'b01);
wire opcode_6_5_10 = (opcode[6:5] == 2'b10);
wire opcode_6_5_11 = (opcode[6:5] == 2'b11);
wire rv32_func3_000 = (rv32_func3 == 3'b000);
wire rv32_func3_001 = (rv32_func3 == 3'b001);
wire rv32_func3_010 = (rv32_func3 == 3'b010);
wire rv32_func3_011 = (rv32_func3 == 3'b011);
wire rv32_func3_100 = (rv32_func3 == 3'b100);
wire rv32_func3_101 = (rv32_func3 == 3'b101);
wire rv32_func3_110 = (rv32_func3 == 3'b110);
wire rv32_func3_111 = (rv32_func3 == 3'b111);
wire rv16_func3_000 = (rv16_func3 == 3'b000);
wire rv16_func3_001 = (rv16_func3 == 3'b001);
wire rv16_func3_010 = (rv16_func3 == 3'b010);
wire rv16_func3_011 = (rv16_func3 == 3'b011);
wire rv16_func3_100 = (rv16_func3 == 3'b100);
wire rv16_func3_101 = (rv16_func3 == 3'b101);
wire rv16_func3_110 = (rv16_func3 == 3'b110);
wire rv16_func3_111 = (rv16_func3 == 3'b111);
wire rv32_func7_0000000 = (rv32_func7 == 7'b0000000);
wire rv32_func7_0100000 = (rv32_func7 == 7'b0100000);
wire rv32_func7_0000001 = (rv32_func7 == 7'b0000001);
wire rv32_func7_0000101 = (rv32_func7 == 7'b0000101);
wire rv32_func7_0001001 = (rv32_func7 == 7'b0001001);
wire rv32_func7_0001101 = (rv32_func7 == 7'b0001101);
wire rv32_func7_0010101 = (rv32_func7 == 7'b0010101);
wire rv32_func7_0100001 = (rv32_func7 == 7'b0100001);
wire rv32_func7_0010001 = (rv32_func7 == 7'b0010001);
wire rv32_func7_0101101 = (rv32_func7 == 7'b0101101);
wire rv32_func7_1111111 = (rv32_func7 == 7'b1111111);
wire rv32_func7_0000100 = (rv32_func7 == 7'b0000100);
wire rv32_func7_0001000 = (rv32_func7 == 7'b0001000);
wire rv32_func7_0001100 = (rv32_func7 == 7'b0001100);
wire rv32_func7_0101100 = (rv32_func7 == 7'b0101100);
wire rv32_func7_0010000 = (rv32_func7 == 7'b0010000);
wire rv32_func7_0010100 = (rv32_func7 == 7'b0010100);
wire rv32_func7_1100000 = (rv32_func7 == 7'b1100000);
wire rv32_func7_1110000 = (rv32_func7 == 7'b1110000);
wire rv32_func7_1010000 = (rv32_func7 == 7'b1010000);
wire rv32_func7_1101000 = (rv32_func7 == 7'b1101000);
wire rv32_func7_1111000 = (rv32_func7 == 7'b1111000);
wire rv32_func7_1010001 = (rv32_func7 == 7'b1010001);
wire rv32_func7_1110001 = (rv32_func7 == 7'b1110001);
wire rv32_func7_1100001 = (rv32_func7 == 7'b1100001);
wire rv32_func7_1101001 = (rv32_func7 == 7'b1101001);
wire rv32_rs1_x0 = (rv32_rs1 == 5'b00000);
wire rv32_rs2_x0 = (rv32_rs2 == 5'b00000);
wire rv32_rs2_x1 = (rv32_rs2 == 5'b00001);
wire rv32_rd_x0 = (rv32_rd == 5'b00000);
wire rv32_rd_x2 = (rv32_rd == 5'b00010);
wire rv16_rs1_x0 = (rv16_rs1 == 5'b00000);
wire rv16_rs2_x0 = (rv16_rs2 == 5'b00000);
wire rv16_rd_x0 = (rv16_rd == 5'b00000);
wire rv16_rd_x2 = (rv16_rd == 5'b00010);
wire rv32_rs1_x31 = (rv32_rs1 == 5'b11111);
wire rv32_rs2_x31 = (rv32_rs2 == 5'b11111);
wire rv32_rd_x31 = (rv32_rd == 5'b11111);
wire rv32_load = opcode_6_5_00 & opcode_4_2_000 & opcode_1_0_11;
wire rv32_store = opcode_6_5_01 & opcode_4_2_000 & opcode_1_0_11;
wire rv32_madd = opcode_6_5_10 & opcode_4_2_000 & opcode_1_0_11;
wire rv32_branch = opcode_6_5_11 & opcode_4_2_000 & opcode_1_0_11;
wire rv32_load_fp = opcode_6_5_00 & opcode_4_2_001 & opcode_1_0_11;
wire rv32_store_fp = opcode_6_5_01 & opcode_4_2_001 & opcode_1_0_11;
wire rv32_msub = opcode_6_5_10 & opcode_4_2_001 & opcode_1_0_11;
wire rv32_jalr = opcode_6_5_11 & opcode_4_2_001 & opcode_1_0_11;
wire rv32_custom0 = opcode_6_5_00 & opcode_4_2_010 & opcode_1_0_11;
wire rv32_custom1 = opcode_6_5_01 & opcode_4_2_010 & opcode_1_0_11;
wire rv32_nmsub = opcode_6_5_10 & opcode_4_2_010 & opcode_1_0_11;
wire rv32_resved0 = opcode_6_5_11 & opcode_4_2_010 & opcode_1_0_11;
wire rv32_miscmem = opcode_6_5_00 & opcode_4_2_011 & opcode_1_0_11;
`ifdef E203_SUPPORT_AMO//{
wire rv32_amo = opcode_6_5_01 & opcode_4_2_011 & opcode_1_0_11;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
wire rv32_amo = 1'b0;
`endif//}
wire rv32_nmadd = opcode_6_5_10 & opcode_4_2_011 & opcode_1_0_11;
wire rv32_jal = opcode_6_5_11 & opcode_4_2_011 & opcode_1_0_11;
wire rv32_op_imm = opcode_6_5_00 & opcode_4_2_100 & opcode_1_0_11;
wire rv32_op = opcode_6_5_01 & opcode_4_2_100 & opcode_1_0_11;
wire rv32_op_fp = opcode_6_5_10 & opcode_4_2_100 & opcode_1_0_11;
wire rv32_system = opcode_6_5_11 & opcode_4_2_100 & opcode_1_0_11;
wire rv32_auipc = opcode_6_5_00 & opcode_4_2_101 & opcode_1_0_11;
wire rv32_lui = opcode_6_5_01 & opcode_4_2_101 & opcode_1_0_11;
wire rv32_resved1 = opcode_6_5_10 & opcode_4_2_101 & opcode_1_0_11;
wire rv32_resved2 = opcode_6_5_11 & opcode_4_2_101 & opcode_1_0_11;
wire rv32_op_imm_32= opcode_6_5_00 & opcode_4_2_110 & opcode_1_0_11;
wire rv32_op_32 = opcode_6_5_01 & opcode_4_2_110 & opcode_1_0_11;
wire rv32_custom2 = opcode_6_5_10 & opcode_4_2_110 & opcode_1_0_11;
wire rv32_custom3 = opcode_6_5_11 & opcode_4_2_110 & opcode_1_0_11;
wire rv16_addi4spn = opcode_1_0_00 & rv16_func3_000;//
wire rv16_lw = opcode_1_0_00 & rv16_func3_010;//
wire rv16_sw = opcode_1_0_00 & rv16_func3_110;//
wire rv16_addi = opcode_1_0_01 & rv16_func3_000;//
wire rv16_jal = opcode_1_0_01 & rv16_func3_001;//
wire rv16_li = opcode_1_0_01 & rv16_func3_010;//
wire rv16_lui_addi16sp = opcode_1_0_01 & rv16_func3_011;//--
wire rv16_miscalu = opcode_1_0_01 & rv16_func3_100;//--
wire rv16_j = opcode_1_0_01 & rv16_func3_101;//
wire rv16_beqz = opcode_1_0_01 & rv16_func3_110;//
wire rv16_bnez = opcode_1_0_01 & rv16_func3_111;//
wire rv16_slli = opcode_1_0_10 & rv16_func3_000;//
wire rv16_lwsp = opcode_1_0_10 & rv16_func3_010;//
wire rv16_jalr_mv_add = opcode_1_0_10 & rv16_func3_100;//--
wire rv16_swsp = opcode_1_0_10 & rv16_func3_110;//
`ifndef E203_HAS_FPU//{
wire rv16_flw = 1'b0;
wire rv16_fld = 1'b0;
wire rv16_fsw = 1'b0;
wire rv16_fsd = 1'b0;
wire rv16_fldsp = 1'b0;
wire rv16_flwsp = 1'b0;
wire rv16_fsdsp = 1'b0;
wire rv16_fswsp = 1'b0;
`endif//}
wire rv16_lwsp_ilgl = rv16_lwsp & rv16_rd_x0;//(RES, rd=0)
wire rv16_nop = rv16_addi
& (~rv16_instr[12]) & (rv16_rd_x0) & (rv16_rs2_x0);
wire rv16_srli = rv16_miscalu & (rv16_instr[11:10] == 2'b00);
wire rv16_srai = rv16_miscalu & (rv16_instr[11:10] == 2'b01);
wire rv16_andi = rv16_miscalu & (rv16_instr[11:10] == 2'b10);
wire rv16_instr_12_is0 = (rv16_instr[12] == 1'b0);
wire rv16_instr_6_2_is0s = (rv16_instr[6:2] == 5'b0);
wire rv16_sxxi_shamt_legl =
rv16_instr_12_is0 //shamt[5] must be zero for RV32C
& (~(rv16_instr_6_2_is0s)) //shamt[4:0] must be non-zero for RV32C
;
wire rv16_sxxi_shamt_ilgl = (rv16_slli | rv16_srli | rv16_srai) & (~rv16_sxxi_shamt_legl);
wire rv16_addi16sp = rv16_lui_addi16sp & rv32_rd_x2;//
wire rv16_lui = rv16_lui_addi16sp & (~rv32_rd_x0) & (~rv32_rd_x2);//
//C.LI is only valid when rd!=x0.
wire rv16_li_ilgl = rv16_li & (rv16_rd_x0);
//C.LUI is only valid when rd!=x0 or x2, and when the immediate is not equal to zero.
wire rv16_lui_ilgl = rv16_lui & (rv16_rd_x0 | rv16_rd_x2 | (rv16_instr_6_2_is0s & rv16_instr_12_is0));
wire rv16_li_lui_ilgl = rv16_li_ilgl | rv16_lui_ilgl;
wire rv16_addi4spn_ilgl = rv16_addi4spn & (rv16_instr_12_is0 & rv16_rd_x0 & opcode_6_5_00);//(RES, nzimm=0, bits[12:5])
wire rv16_addi16sp_ilgl = rv16_addi16sp & rv16_instr_12_is0 & rv16_instr_6_2_is0s; //(RES, nzimm=0, bits 12,6:2)
wire rv16_subxororand = rv16_miscalu & (rv16_instr[12:10] == 3'b011);//
wire rv16_sub = rv16_subxororand & (rv16_instr[6:5] == 2'b00);//
wire rv16_xor = rv16_subxororand & (rv16_instr[6:5] == 2'b01);//
wire rv16_or = rv16_subxororand & (rv16_instr[6:5] == 2'b10);//
wire rv16_and = rv16_subxororand & (rv16_instr[6:5] == 2'b11);//
wire rv16_jr = rv16_jalr_mv_add //
& (~rv16_instr[12]) & (~rv16_rs1_x0) & (rv16_rs2_x0);// The RES rs1=0 illegal is already covered here
wire rv16_mv = rv16_jalr_mv_add //
& (~rv16_instr[12]) & (~rv16_rd_x0) & (~rv16_rs2_x0);
wire rv16_ebreak = rv16_jalr_mv_add //
& (rv16_instr[12]) & (rv16_rd_x0) & (rv16_rs2_x0);
wire rv16_jalr = rv16_jalr_mv_add //
& (rv16_instr[12]) & (~rv16_rs1_x0) & (rv16_rs2_x0);
wire rv16_add = rv16_jalr_mv_add //
& (rv16_instr[12]) & (~rv16_rd_x0) & (~rv16_rs2_x0);
// ===========================================================================
// Branch Instructions
wire rv32_beq = rv32_branch & rv32_func3_000;
wire rv32_bne = rv32_branch & rv32_func3_001;
wire rv32_blt = rv32_branch & rv32_func3_100;
wire rv32_bgt = rv32_branch & rv32_func3_101;
wire rv32_bltu = rv32_branch & rv32_func3_110;
wire rv32_bgtu = rv32_branch & rv32_func3_111;
// ===========================================================================
// System Instructions
wire rv32_ecall = rv32_system & rv32_func3_000 & (rv32_instr[31:20] == 12'b0000_0000_0000);
wire rv32_ebreak = rv32_system & rv32_func3_000 & (rv32_instr[31:20] == 12'b0000_0000_0001);
wire rv32_mret = rv32_system & rv32_func3_000 & (rv32_instr[31:20] == 12'b0011_0000_0010);
wire rv32_dret = rv32_system & rv32_func3_000 & (rv32_instr[31:20] == 12'b0111_1011_0010);
wire rv32_wfi = rv32_system & rv32_func3_000 & (rv32_instr[31:20] == 12'b0001_0000_0101);
// We dont implement the WFI and MRET illegal exception when the rs and rd is not zeros
wire rv32_csrrw = rv32_system & rv32_func3_001;
wire rv32_csrrs = rv32_system & rv32_func3_010;
wire rv32_csrrc = rv32_system & rv32_func3_011;
wire rv32_csrrwi = rv32_system & rv32_func3_101;
wire rv32_csrrsi = rv32_system & rv32_func3_110;
wire rv32_csrrci = rv32_system & rv32_func3_111;
wire rv32_dret_ilgl = rv32_dret & (~dbg_mode);
wire rv32_ecall_ebreak_ret_wfi = rv32_system & rv32_func3_000;
wire rv32_csr = rv32_system & (~rv32_func3_000);
// ===========================================================================
// The Branch and system group of instructions will be handled by BJP
assign dec_jal = rv32_jal | rv16_jal | rv16_j;
assign dec_jalr = rv32_jalr | rv16_jalr | rv16_jr;
assign dec_bxx = rv32_branch | rv16_beqz | rv16_bnez;
assign dec_bjp = dec_jal | dec_jalr | dec_bxx;
wire rv32_fence ;
wire rv32_fence_i;
wire rv32_fence_fencei;
wire bjp_op = dec_bjp | rv32_mret | (rv32_dret & (~rv32_dret_ilgl)) | rv32_fence_fencei;
wire [`E203_DECINFO_BJP_WIDTH-1:0] bjp_info_bus;
assign bjp_info_bus[`E203_DECINFO_GRP ] = `E203_DECINFO_GRP_BJP;
assign bjp_info_bus[`E203_DECINFO_RV32 ] = rv32;
assign bjp_info_bus[`E203_DECINFO_BJP_JUMP ] = dec_jal | dec_jalr;
assign bjp_info_bus[`E203_DECINFO_BJP_BPRDT] = i_prdt_taken;
assign bjp_info_bus[`E203_DECINFO_BJP_BEQ ] = rv32_beq | rv16_beqz;
assign bjp_info_bus[`E203_DECINFO_BJP_BNE ] = rv32_bne | rv16_bnez;
assign bjp_info_bus[`E203_DECINFO_BJP_BLT ] = rv32_blt;
assign bjp_info_bus[`E203_DECINFO_BJP_BGT ] = rv32_bgt ;
assign bjp_info_bus[`E203_DECINFO_BJP_BLTU ] = rv32_bltu;
assign bjp_info_bus[`E203_DECINFO_BJP_BGTU ] = rv32_bgtu;
assign bjp_info_bus[`E203_DECINFO_BJP_BXX ] = dec_bxx;
assign bjp_info_bus[`E203_DECINFO_BJP_MRET ] = rv32_mret;
assign bjp_info_bus[`E203_DECINFO_BJP_DRET ] = rv32_dret;
assign bjp_info_bus[`E203_DECINFO_BJP_FENCE ] = rv32_fence;
assign bjp_info_bus[`E203_DECINFO_BJP_FENCEI] = rv32_fence_i;
// ===========================================================================
// ALU Instructions
wire rv32_addi = rv32_op_imm & rv32_func3_000;
wire rv32_slti = rv32_op_imm & rv32_func3_010;
wire rv32_sltiu = rv32_op_imm & rv32_func3_011;
wire rv32_xori = rv32_op_imm & rv32_func3_100;
wire rv32_ori = rv32_op_imm & rv32_func3_110;
wire rv32_andi = rv32_op_imm & rv32_func3_111;
wire rv32_slli = rv32_op_imm & rv32_func3_001 & (rv32_instr[31:26] == 6'b000000);
wire rv32_srli = rv32_op_imm & rv32_func3_101 & (rv32_instr[31:26] == 6'b000000);
wire rv32_srai = rv32_op_imm & rv32_func3_101 & (rv32_instr[31:26] == 6'b010000);
wire rv32_sxxi_shamt_legl = (rv32_instr[25] == 1'b0); //shamt[5] must be zero for RV32I
wire rv32_sxxi_shamt_ilgl = (rv32_slli | rv32_srli | rv32_srai) & (~rv32_sxxi_shamt_legl);
wire rv32_add = rv32_op & rv32_func3_000 & rv32_func7_0000000;
wire rv32_sub = rv32_op & rv32_func3_000 & rv32_func7_0100000;
wire rv32_sll = rv32_op & rv32_func3_001 & rv32_func7_0000000;
wire rv32_slt = rv32_op & rv32_func3_010 & rv32_func7_0000000;
wire rv32_sltu = rv32_op & rv32_func3_011 & rv32_func7_0000000;
wire rv32_xor = rv32_op & rv32_func3_100 & rv32_func7_0000000;
wire rv32_srl = rv32_op & rv32_func3_101 & rv32_func7_0000000;
wire rv32_sra = rv32_op & rv32_func3_101 & rv32_func7_0100000;
wire rv32_or = rv32_op & rv32_func3_110 & rv32_func7_0000000;
wire rv32_and = rv32_op & rv32_func3_111 & rv32_func7_0000000;
wire rv32_nop = rv32_addi & rv32_rs1_x0 & rv32_rd_x0 & (~(|rv32_instr[31:20]));
// The ALU group of instructions will be handled by 1cycle ALU-datapath
wire ecall_ebreak = rv32_ecall | rv32_ebreak | rv16_ebreak;
wire alu_op = (~rv32_sxxi_shamt_ilgl) & (~rv16_sxxi_shamt_ilgl)
& (~rv16_li_lui_ilgl) & (~rv16_addi4spn_ilgl) & (~rv16_addi16sp_ilgl) &
( rv32_op_imm
| rv32_op & (~rv32_func7_0000001) // Exclude the MULDIV
| rv32_auipc
| rv32_lui
| rv16_addi4spn
| rv16_addi
| rv16_lui_addi16sp
| rv16_li | rv16_mv
| rv16_slli
| rv16_miscalu
| rv16_add
| rv16_nop | rv32_nop
| rv32_wfi // We just put WFI into ALU and do nothing in ALU
| ecall_ebreak)
;
wire need_imm;
wire [`E203_DECINFO_ALU_WIDTH-1:0] alu_info_bus;
assign alu_info_bus[`E203_DECINFO_GRP ] = `E203_DECINFO_GRP_ALU;
assign alu_info_bus[`E203_DECINFO_RV32 ] = rv32;
assign alu_info_bus[`E203_DECINFO_ALU_ADD] = rv32_add | rv32_addi | rv32_auipc |
rv16_addi4spn | rv16_addi | rv16_addi16sp | rv16_add |
// We also decode LI and MV as the add instruction, becuase
// they all add x0 with a RS2 or Immeidate, and then write into RD
rv16_li | rv16_mv;
assign alu_info_bus[`E203_DECINFO_ALU_SUB] = rv32_sub | rv16_sub;
assign alu_info_bus[`E203_DECINFO_ALU_SLT] = rv32_slt | rv32_slti;
assign alu_info_bus[`E203_DECINFO_ALU_SLTU] = rv32_sltu | rv32_sltiu;
assign alu_info_bus[`E203_DECINFO_ALU_XOR] = rv32_xor | rv32_xori | rv16_xor;
assign alu_info_bus[`E203_DECINFO_ALU_SLL] = rv32_sll | rv32_slli | rv16_slli;
assign alu_info_bus[`E203_DECINFO_ALU_SRL] = rv32_srl | rv32_srli | rv16_srli;
assign alu_info_bus[`E203_DECINFO_ALU_SRA] = rv32_sra | rv32_srai | rv16_srai;
assign alu_info_bus[`E203_DECINFO_ALU_OR ] = rv32_or | rv32_ori | rv16_or;
assign alu_info_bus[`E203_DECINFO_ALU_AND] = rv32_and | rv32_andi | rv16_andi | rv16_and;
assign alu_info_bus[`E203_DECINFO_ALU_LUI] = rv32_lui | rv16_lui;
assign alu_info_bus[`E203_DECINFO_ALU_OP2IMM] = need_imm;
assign alu_info_bus[`E203_DECINFO_ALU_OP1PC ] = rv32_auipc;
assign alu_info_bus[`E203_DECINFO_ALU_NOP ] = rv16_nop | rv32_nop;
assign alu_info_bus[`E203_DECINFO_ALU_ECAL ] = rv32_ecall;
assign alu_info_bus[`E203_DECINFO_ALU_EBRK ] = rv32_ebreak | rv16_ebreak;
assign alu_info_bus[`E203_DECINFO_ALU_WFI ] = rv32_wfi;
wire csr_op = rv32_csr;
wire [`E203_DECINFO_CSR_WIDTH-1:0] csr_info_bus;
assign csr_info_bus[`E203_DECINFO_GRP ] = `E203_DECINFO_GRP_CSR;
assign csr_info_bus[`E203_DECINFO_RV32 ] = rv32;
assign csr_info_bus[`E203_DECINFO_CSR_CSRRW ] = rv32_csrrw | rv32_csrrwi;
assign csr_info_bus[`E203_DECINFO_CSR_CSRRS ] = rv32_csrrs | rv32_csrrsi;
assign csr_info_bus[`E203_DECINFO_CSR_CSRRC ] = rv32_csrrc | rv32_csrrci;
assign csr_info_bus[`E203_DECINFO_CSR_RS1IMM] = rv32_csrrwi | rv32_csrrsi | rv32_csrrci;
assign csr_info_bus[`E203_DECINFO_CSR_ZIMMM ] = rv32_rs1;
assign csr_info_bus[`E203_DECINFO_CSR_RS1IS0] = rv32_rs1_x0;
assign csr_info_bus[`E203_DECINFO_CSR_CSRIDX] = rv32_instr[31:20];
// ===========================================================================
// Memory Order Instructions
assign rv32_fence = rv32_miscmem & rv32_func3_000;
assign rv32_fence_i = rv32_miscmem & rv32_func3_001;
assign rv32_fence_fencei = rv32_miscmem;
// ===========================================================================
// MUL/DIV Instructions
wire rv32_mul = rv32_op & rv32_func3_000 & rv32_func7_0000001;
wire rv32_mulh = rv32_op & rv32_func3_001 & rv32_func7_0000001;
wire rv32_mulhsu = rv32_op & rv32_func3_010 & rv32_func7_0000001;
wire rv32_mulhu = rv32_op & rv32_func3_011 & rv32_func7_0000001;
wire rv32_div = rv32_op & rv32_func3_100 & rv32_func7_0000001;
wire rv32_divu = rv32_op & rv32_func3_101 & rv32_func7_0000001;
wire rv32_rem = rv32_op & rv32_func3_110 & rv32_func7_0000001;
wire rv32_remu = rv32_op & rv32_func3_111 & rv32_func7_0000001;
// The MULDIV group of instructions will be handled by MUL-DIV-datapath
`ifdef E203_SUPPORT_MULDIV//{
wire muldiv_op = rv32_op & rv32_func7_0000001;
`endif//}
`ifndef E203_SUPPORT_MULDIV//{
wire muldiv_op = 1'b0;
`endif//}
wire [`E203_DECINFO_MULDIV_WIDTH-1:0] muldiv_info_bus;
assign muldiv_info_bus[`E203_DECINFO_GRP ] = `E203_DECINFO_GRP_MULDIV;
assign muldiv_info_bus[`E203_DECINFO_RV32 ] = rv32 ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_MUL ] = rv32_mul ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_MULH ] = rv32_mulh ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_MULHSU] = rv32_mulhsu ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_MULHU ] = rv32_mulhu ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_DIV ] = rv32_div ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_DIVU ] = rv32_divu ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_REM ] = rv32_rem ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_REMU ] = rv32_remu ;
assign muldiv_info_bus[`E203_DECINFO_MULDIV_B2B ] = i_muldiv_b2b;
assign dec_mulhsu = rv32_mulh | rv32_mulhsu | rv32_mulhu;
assign dec_mul = rv32_mul;
assign dec_div = rv32_div ;
assign dec_divu = rv32_divu;
assign dec_rem = rv32_rem;
assign dec_remu = rv32_remu;
// ===========================================================================
// Load/Store Instructions
wire rv32_lb = rv32_load & rv32_func3_000;
wire rv32_lh = rv32_load & rv32_func3_001;
wire rv32_lw = rv32_load & rv32_func3_010;
wire rv32_lbu = rv32_load & rv32_func3_100;
wire rv32_lhu = rv32_load & rv32_func3_101;
wire rv32_sb = rv32_store & rv32_func3_000;
wire rv32_sh = rv32_store & rv32_func3_001;
wire rv32_sw = rv32_store & rv32_func3_010;
// ===========================================================================
// Atomic Instructions
`ifdef E203_SUPPORT_AMO//{
wire rv32_lr_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b00010);
wire rv32_sc_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b00011);
wire rv32_amoswap_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b00001);
wire rv32_amoadd_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b00000);
wire rv32_amoxor_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b00100);
wire rv32_amoand_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b01100);
wire rv32_amoor_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b01000);
wire rv32_amomin_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b10000);
wire rv32_amomax_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b10100);
wire rv32_amominu_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b11000);
wire rv32_amomaxu_w = rv32_amo & rv32_func3_010 & (rv32_func7[6:2] == 5'b11100);
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
wire rv32_lr_w = 1'b0;
wire rv32_sc_w = 1'b0;
wire rv32_amoswap_w = 1'b0;
wire rv32_amoadd_w = 1'b0;
wire rv32_amoxor_w = 1'b0;
wire rv32_amoand_w = 1'b0;
wire rv32_amoor_w = 1'b0;
wire rv32_amomin_w = 1'b0;
wire rv32_amomax_w = 1'b0;
wire rv32_amominu_w = 1'b0;
wire rv32_amomaxu_w = 1'b0;
`endif//}
wire amoldst_op = rv32_amo | rv32_load | rv32_store | rv16_lw | rv16_sw | (rv16_lwsp & (~rv16_lwsp_ilgl)) | rv16_swsp;
// The RV16 always is word
wire [1:0] lsu_info_size = rv32 ? rv32_func3[1:0] : 2'b10;
// The RV16 always is signed
wire lsu_info_usign = rv32? rv32_func3[2] : 1'b0;
wire [`E203_DECINFO_AGU_WIDTH-1:0] agu_info_bus;
assign agu_info_bus[`E203_DECINFO_GRP ] = `E203_DECINFO_GRP_AGU;
assign agu_info_bus[`E203_DECINFO_RV32 ] = rv32;
assign agu_info_bus[`E203_DECINFO_AGU_LOAD ] = rv32_load | rv32_lr_w | rv16_lw | rv16_lwsp;
assign agu_info_bus[`E203_DECINFO_AGU_STORE ] = rv32_store | rv32_sc_w | rv16_sw | rv16_swsp;
assign agu_info_bus[`E203_DECINFO_AGU_SIZE ] = lsu_info_size;
assign agu_info_bus[`E203_DECINFO_AGU_USIGN ] = lsu_info_usign;
assign agu_info_bus[`E203_DECINFO_AGU_EXCL ] = rv32_lr_w | rv32_sc_w;
assign agu_info_bus[`E203_DECINFO_AGU_AMO ] = rv32_amo & (~(rv32_lr_w | rv32_sc_w));// We seperated the EXCL out of AMO in LSU handling
assign agu_info_bus[`E203_DECINFO_AGU_AMOSWAP] = rv32_amoswap_w;
assign agu_info_bus[`E203_DECINFO_AGU_AMOADD ] = rv32_amoadd_w ;
assign agu_info_bus[`E203_DECINFO_AGU_AMOAND ] = rv32_amoand_w ;
assign agu_info_bus[`E203_DECINFO_AGU_AMOOR ] = rv32_amoor_w ;
assign agu_info_bus[`E203_DECINFO_AGU_AMOXOR ] = rv32_amoxor_w ;
assign agu_info_bus[`E203_DECINFO_AGU_AMOMAX ] = rv32_amomax_w ;
assign agu_info_bus[`E203_DECINFO_AGU_AMOMIN ] = rv32_amomin_w ;
assign agu_info_bus[`E203_DECINFO_AGU_AMOMAXU] = rv32_amomaxu_w;
assign agu_info_bus[`E203_DECINFO_AGU_AMOMINU] = rv32_amominu_w;
assign agu_info_bus[`E203_DECINFO_AGU_OP2IMM ] = need_imm;
// Reuse the common signals as much as possible to save gatecounts
wire rv32_all0s_ilgl = rv32_func7_0000000
& rv32_rs2_x0
& rv32_rs1_x0
& rv32_func3_000
& rv32_rd_x0
& opcode_6_5_00
& opcode_4_2_000
& (opcode[1:0] == 2'b00);
wire rv32_all1s_ilgl = rv32_func7_1111111
& rv32_rs2_x31
& rv32_rs1_x31
& rv32_func3_111
& rv32_rd_x31
& opcode_6_5_11
& opcode_4_2_111
& (opcode[1:0] == 2'b11);
wire rv16_all0s_ilgl = rv16_func3_000 //rv16_func3 = rv32_instr[15:13];
& rv32_func3_000 //rv32_func3 = rv32_instr[14:12];
& rv32_rd_x0 //rv32_rd = rv32_instr[11:7];
& opcode_6_5_00
& opcode_4_2_000
& (opcode[1:0] == 2'b00);
wire rv16_all1s_ilgl = rv16_func3_111
& rv32_func3_111
& rv32_rd_x31
& opcode_6_5_11
& opcode_4_2_111
& (opcode[1:0] == 2'b11);
wire rv_all0s1s_ilgl = rv32 ? (rv32_all0s_ilgl | rv32_all1s_ilgl)
: (rv16_all0s_ilgl | rv16_all1s_ilgl);
//
// All the RV32IMA need RD register except the
// * Branch, Store,
// * fence, fence_i
// * ecall, ebreak
wire rv32_need_rd =
(~rv32_rd_x0) & (
(
(~rv32_branch) & (~rv32_store)
& (~rv32_fence_fencei)
& (~rv32_ecall_ebreak_ret_wfi)
)
);
// All the RV32IMA need RS1 register except the
// * lui
// * auipc
// * jal
// * fence, fence_i
// * ecall, ebreak
// * csrrwi
// * csrrsi
// * csrrci
wire rv32_need_rs1 =
(~rv32_rs1_x0) & (
(
(~rv32_lui)
& (~rv32_auipc)
& (~rv32_jal)
& (~rv32_fence_fencei)
& (~rv32_ecall_ebreak_ret_wfi)
& (~rv32_csrrwi)
& (~rv32_csrrsi)
& (~rv32_csrrci)
)
);
// Following RV32IMA instructions need RS2 register
// * branch
// * store
// * rv32_op
// * rv32_amo except the rv32_lr_w
wire rv32_need_rs2 = (~rv32_rs2_x0) & (
(
(rv32_branch)
| (rv32_store)
| (rv32_op)
| (rv32_amo & (~rv32_lr_w))
)
);
wire [31:0] rv32_i_imm = {
{20{rv32_instr[31]}}
, rv32_instr[31:20]
};
wire [31:0] rv32_s_imm = {
{20{rv32_instr[31]}}
, rv32_instr[31:25]
, rv32_instr[11:7]
};
wire [31:0] rv32_b_imm = {
{19{rv32_instr[31]}}
, rv32_instr[31]
, rv32_instr[7]
, rv32_instr[30:25]
, rv32_instr[11:8]
, 1'b0
};
wire [31:0] rv32_u_imm = {rv32_instr[31:12],12'b0};
wire [31:0] rv32_j_imm = {
{11{rv32_instr[31]}}
, rv32_instr[31]
, rv32_instr[19:12]
, rv32_instr[20]
, rv32_instr[30:21]
, 1'b0
};
// It will select i-type immediate when
// * rv32_op_imm
// * rv32_jalr
// * rv32_load
wire rv32_imm_sel_i = rv32_op_imm | rv32_jalr | rv32_load;
wire rv32_imm_sel_jalr = rv32_jalr;
wire [31:0] rv32_jalr_imm = rv32_i_imm;
// It will select u-type immediate when
// * rv32_lui, rv32_auipc
wire rv32_imm_sel_u = rv32_lui | rv32_auipc;
// It will select j-type immediate when
// * rv32_jal
wire rv32_imm_sel_j = rv32_jal;
wire rv32_imm_sel_jal = rv32_jal;
wire [31:0] rv32_jal_imm = rv32_j_imm;
// It will select b-type immediate when
// * rv32_branch
wire rv32_imm_sel_b = rv32_branch;
wire rv32_imm_sel_bxx = rv32_branch;
wire [31:0] rv32_bxx_imm = rv32_b_imm;
// It will select s-type immediate when
// * rv32_store
wire rv32_imm_sel_s = rv32_store;
// * Note: this CIS/CILI/CILUI/CI16SP-type is named by myself, because in
// ISA doc, the CI format for LWSP is different
// with other CI formats in terms of immediate
// It will select CIS-type immediate when
// * rv16_lwsp
wire rv16_imm_sel_cis = rv16_lwsp;
wire [31:0] rv16_cis_imm ={
24'b0
, rv16_instr[3:2]
, rv16_instr[12]
, rv16_instr[6:4]
, 2'b0
};
wire [31:0] rv16_cis_d_imm ={
23'b0
, rv16_instr[4:2]
, rv16_instr[12]
, rv16_instr[6:5]
, 3'b0
};
// It will select CILI-type immediate when
// * rv16_li
// * rv16_addi
// * rv16_slli
// * rv16_srai
// * rv16_srli
// * rv16_andi
wire rv16_imm_sel_cili = rv16_li | rv16_addi | rv16_slli
| rv16_srai | rv16_srli | rv16_andi;
wire [31:0] rv16_cili_imm ={
{26{rv16_instr[12]}}
, rv16_instr[12]
, rv16_instr[6:2]
};
// It will select CILUI-type immediate when
// * rv16_lui
wire rv16_imm_sel_cilui = rv16_lui;
wire [31:0] rv16_cilui_imm ={
{14{rv16_instr[12]}}
, rv16_instr[12]
, rv16_instr[6:2]
, 12'b0
};
// It will select CI16SP-type immediate when
// * rv16_addi16sp
wire rv16_imm_sel_ci16sp = rv16_addi16sp;
wire [31:0] rv16_ci16sp_imm ={
{22{rv16_instr[12]}}
, rv16_instr[12]
, rv16_instr[4]
, rv16_instr[3]
, rv16_instr[5]
, rv16_instr[2]
, rv16_instr[6]
, 4'b0
};
// It will select CSS-type immediate when
// * rv16_swsp
wire rv16_imm_sel_css = rv16_swsp;
wire [31:0] rv16_css_imm ={
24'b0
, rv16_instr[8:7]
, rv16_instr[12:9]
, 2'b0
};
wire [31:0] rv16_css_d_imm ={
23'b0
, rv16_instr[9:7]
, rv16_instr[12:10]
, 3'b0
};
// It will select CIW-type immediate when
// * rv16_addi4spn
wire rv16_imm_sel_ciw = rv16_addi4spn;
wire [31:0] rv16_ciw_imm ={
22'b0
, rv16_instr[10:7]
, rv16_instr[12]
, rv16_instr[11]
, rv16_instr[5]
, rv16_instr[6]
, 2'b0
};
// It will select CL-type immediate when
// * rv16_lw
wire rv16_imm_sel_cl = rv16_lw;
wire [31:0] rv16_cl_imm ={
25'b0
, rv16_instr[5]
, rv16_instr[12]
, rv16_instr[11]
, rv16_instr[10]
, rv16_instr[6]
, 2'b0
};
wire [31:0] rv16_cl_d_imm ={
24'b0
, rv16_instr[6]
, rv16_instr[5]
, rv16_instr[12]
, rv16_instr[11]
, rv16_instr[10]
, 3'b0
};
// It will select CS-type immediate when
// * rv16_sw
wire rv16_imm_sel_cs = rv16_sw;
wire [31:0] rv16_cs_imm ={
25'b0
, rv16_instr[5]
, rv16_instr[12]
, rv16_instr[11]
, rv16_instr[10]
, rv16_instr[6]
, 2'b0
};
wire [31:0] rv16_cs_d_imm ={
24'b0
, rv16_instr[6]
, rv16_instr[5]
, rv16_instr[12]
, rv16_instr[11]
, rv16_instr[10]
, 3'b0
};
// It will select CB-type immediate when
// * rv16_beqz
// * rv16_bnez
wire rv16_imm_sel_cb = rv16_beqz | rv16_bnez;
wire [31:0] rv16_cb_imm ={
{23{rv16_instr[12]}}
, rv16_instr[12]
, rv16_instr[6:5]
, rv16_instr[2]
, rv16_instr[11:10]
, rv16_instr[4:3]
, 1'b0
};
wire [31:0] rv16_bxx_imm = rv16_cb_imm;
// It will select CJ-type immediate when
// * rv16_j
// * rv16_jal
wire rv16_imm_sel_cj = rv16_j | rv16_jal;
wire [31:0] rv16_cj_imm ={
{20{rv16_instr[12]}}
, rv16_instr[12]
, rv16_instr[8]
, rv16_instr[10:9]
, rv16_instr[6]
, rv16_instr[7]
, rv16_instr[2]
, rv16_instr[11]
, rv16_instr[5:3]
, 1'b0
};
wire [31:0] rv16_jjal_imm = rv16_cj_imm;
// It will select CR-type register (no-imm) when
// * rv16_jalr_mv_add
wire [31:0] rv16_jrjalr_imm = 32'b0;
// It will select CSR-type register (no-imm) when
// * rv16_subxororand
wire [31:0] rv32_load_fp_imm = rv32_i_imm;
wire [31:0] rv32_store_fp_imm = rv32_s_imm;
wire [31:0] rv32_imm =
({32{rv32_imm_sel_i}} & rv32_i_imm)
| ({32{rv32_imm_sel_s}} & rv32_s_imm)
| ({32{rv32_imm_sel_b}} & rv32_b_imm)
| ({32{rv32_imm_sel_u}} & rv32_u_imm)
| ({32{rv32_imm_sel_j}} & rv32_j_imm)
;
wire rv32_need_imm =
rv32_imm_sel_i
| rv32_imm_sel_s
| rv32_imm_sel_b
| rv32_imm_sel_u
| rv32_imm_sel_j
;
wire [31:0] rv16_imm =
({32{rv16_imm_sel_cis }} & rv16_cis_imm)
| ({32{rv16_imm_sel_cili }} & rv16_cili_imm)
| ({32{rv16_imm_sel_cilui }} & rv16_cilui_imm)
| ({32{rv16_imm_sel_ci16sp}} & rv16_ci16sp_imm)
| ({32{rv16_imm_sel_css }} & rv16_css_imm)
| ({32{rv16_imm_sel_ciw }} & rv16_ciw_imm)
| ({32{rv16_imm_sel_cl }} & rv16_cl_imm)
| ({32{rv16_imm_sel_cs }} & rv16_cs_imm)
| ({32{rv16_imm_sel_cb }} & rv16_cb_imm)
| ({32{rv16_imm_sel_cj }} & rv16_cj_imm)
;
wire rv16_need_imm =
rv16_imm_sel_cis
| rv16_imm_sel_cili
| rv16_imm_sel_cilui
| rv16_imm_sel_ci16sp
| rv16_imm_sel_css
| rv16_imm_sel_ciw
| rv16_imm_sel_cl
| rv16_imm_sel_cs
| rv16_imm_sel_cb
| rv16_imm_sel_cj
;
assign need_imm = rv32 ? rv32_need_imm : rv16_need_imm;
assign dec_imm = rv32 ? rv32_imm : rv16_imm;
assign dec_pc = i_pc;
assign dec_info =
({`E203_DECINFO_WIDTH{alu_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_ALU_WIDTH{1'b0}},alu_info_bus})
| ({`E203_DECINFO_WIDTH{amoldst_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_AGU_WIDTH{1'b0}},agu_info_bus})
| ({`E203_DECINFO_WIDTH{bjp_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_BJP_WIDTH{1'b0}},bjp_info_bus})
| ({`E203_DECINFO_WIDTH{csr_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_CSR_WIDTH{1'b0}},csr_info_bus})
| ({`E203_DECINFO_WIDTH{muldiv_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_CSR_WIDTH{1'b0}},muldiv_info_bus})
;
wire legl_ops =
alu_op
| amoldst_op
| bjp_op
| csr_op
| muldiv_op
;
// To decode the registers for Rv16, divided into 8 groups
wire rv16_format_cr = rv16_jalr_mv_add;
wire rv16_format_ci = rv16_lwsp | rv16_flwsp | rv16_fldsp | rv16_li | rv16_lui_addi16sp | rv16_addi | rv16_slli;
wire rv16_format_css = rv16_swsp | rv16_fswsp | rv16_fsdsp;
wire rv16_format_ciw = rv16_addi4spn;
wire rv16_format_cl = rv16_lw | rv16_flw | rv16_fld;
wire rv16_format_cs = rv16_sw | rv16_fsw | rv16_fsd | rv16_subxororand;
wire rv16_format_cb = rv16_beqz | rv16_bnez | rv16_srli | rv16_srai | rv16_andi;
wire rv16_format_cj = rv16_j | rv16_jal;
// In CR Cases:
// * JR: rs1= rs1(coded), rs2= x0 (coded), rd = x0 (implicit)
// * JALR: rs1= rs1(coded), rs2= x0 (coded), rd = x1 (implicit)
// * MV: rs1= x0 (implicit), rs2= rs2(coded), rd = rd (coded)
// * ADD: rs1= rs1(coded), rs2= rs2(coded), rd = rd (coded)
// * eBreak: rs1= rs1(coded), rs2= x0 (coded), rd = x0 (coded)
wire rv16_need_cr_rs1 = rv16_format_cr & 1'b1;
wire rv16_need_cr_rs2 = rv16_format_cr & 1'b1;
wire rv16_need_cr_rd = rv16_format_cr & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cr_rs1 = rv16_mv ? `E203_RFIDX_WIDTH'd0 : rv16_rs1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cr_rs2 = rv16_rs2[`E203_RFIDX_WIDTH-1:0];
// The JALR and JR difference in encoding is just the rv16_instr[12]
wire [`E203_RFIDX_WIDTH-1:0] rv16_cr_rd = (rv16_jalr | rv16_jr)?
{{`E203_RFIDX_WIDTH-1{1'b0}},rv16_instr[12]} : rv16_rd[`E203_RFIDX_WIDTH-1:0];
// In CI Cases:
// * LWSP: rs1= x2 (implicit), rd = rd
// * LI/LUI: rs1= x0 (implicit), rd = rd
// * ADDI: rs1= rs1(implicit), rd = rd
// * ADDI16SP: rs1= rs1(implicit), rd = rd
// * SLLI: rs1= rs1(implicit), rd = rd
wire rv16_need_ci_rs1 = rv16_format_ci & 1'b1;
wire rv16_need_ci_rs2 = rv16_format_ci & 1'b0;
wire rv16_need_ci_rd = rv16_format_ci & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ci_rs1 = (rv16_lwsp | rv16_flwsp | rv16_fldsp) ? `E203_RFIDX_WIDTH'd2 :
(rv16_li | rv16_lui) ? `E203_RFIDX_WIDTH'd0 : rv16_rs1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_ci_rs2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ci_rd = rv16_rd[`E203_RFIDX_WIDTH-1:0];
// In CSS Cases:
// * SWSP: rs1 = x2 (implicit), rs2= rs2
wire rv16_need_css_rs1 = rv16_format_css & 1'b1;
wire rv16_need_css_rs2 = rv16_format_css & 1'b1;
wire rv16_need_css_rd = rv16_format_css & 1'b0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_css_rs1 = `E203_RFIDX_WIDTH'd2;
wire [`E203_RFIDX_WIDTH-1:0] rv16_css_rs2 = rv16_rs2[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_css_rd = `E203_RFIDX_WIDTH'd0;
// In CIW cases:
// * ADDI4SPN: rdd = rdd, rss1= x2 (implicit)
wire rv16_need_ciw_rss1 = rv16_format_ciw & 1'b1;
wire rv16_need_ciw_rss2 = rv16_format_ciw & 1'b0;
wire rv16_need_ciw_rdd = rv16_format_ciw & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ciw_rss1 = `E203_RFIDX_WIDTH'd2;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ciw_rss2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ciw_rdd = rv16_rdd[`E203_RFIDX_WIDTH-1:0];
// In CL cases:
// * LW: rss1 = rss1, rdd= rdd
wire rv16_need_cl_rss1 = rv16_format_cl & 1'b1;
wire rv16_need_cl_rss2 = rv16_format_cl & 1'b0;
wire rv16_need_cl_rdd = rv16_format_cl & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cl_rss1 = rv16_rss1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cl_rss2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cl_rdd = rv16_rdd[`E203_RFIDX_WIDTH-1:0];
// In CS cases:
// * SW: rdd = none(implicit), rss1= rss1 , rss2=rss2
// * SUBXORORAND: rdd = rss1, rss1= rss1(coded), rss2=rss2
wire rv16_need_cs_rss1 = rv16_format_cs & 1'b1;
wire rv16_need_cs_rss2 = rv16_format_cs & 1'b1;
wire rv16_need_cs_rdd = rv16_format_cs & rv16_subxororand;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cs_rss1 = rv16_rss1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cs_rss2 = rv16_rss2[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cs_rdd = rv16_rss1[`E203_RFIDX_WIDTH-1:0];
// In CB cases:
// * BEQ/BNE: rdd = none(implicit), rss1= rss1, rss2=x0(implicit)
// * SRLI/SRAI/ANDI: rdd = rss1 , rss1= rss1, rss2=none(implicit)
wire rv16_need_cb_rss1 = rv16_format_cb & 1'b1;
wire rv16_need_cb_rss2 = rv16_format_cb & (rv16_beqz | rv16_bnez);
wire rv16_need_cb_rdd = rv16_format_cb & (~(rv16_beqz | rv16_bnez));
wire [`E203_RFIDX_WIDTH-1:0] rv16_cb_rss1 = rv16_rss1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cb_rss2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cb_rdd = rv16_rss1[`E203_RFIDX_WIDTH-1:0];
// In CJ cases:
// * J: rdd = x0(implicit)
// * JAL: rdd = x1(implicit)
wire rv16_need_cj_rss1 = rv16_format_cj & 1'b0;
wire rv16_need_cj_rss2 = rv16_format_cj & 1'b0;
wire rv16_need_cj_rdd = rv16_format_cj & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cj_rss1 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cj_rss2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cj_rdd = rv16_j ? `E203_RFIDX_WIDTH'd0 : `E203_RFIDX_WIDTH'd1;
// rv16_format_cr
// rv16_format_ci
// rv16_format_css
// rv16_format_ciw
// rv16_format_cl
// rv16_format_cs
// rv16_format_cb
// rv16_format_cj
wire rv16_need_rs1 = rv16_need_cr_rs1 | rv16_need_ci_rs1 | rv16_need_css_rs1;
wire rv16_need_rs2 = rv16_need_cr_rs2 | rv16_need_ci_rs2 | rv16_need_css_rs2;
wire rv16_need_rd = rv16_need_cr_rd | rv16_need_ci_rd | rv16_need_css_rd;
wire rv16_need_rss1 = rv16_need_ciw_rss1|rv16_need_cl_rss1|rv16_need_cs_rss1|rv16_need_cb_rss1|rv16_need_cj_rss1;
wire rv16_need_rss2 = rv16_need_ciw_rss2|rv16_need_cl_rss2|rv16_need_cs_rss2|rv16_need_cb_rss2|rv16_need_cj_rss2;
wire rv16_need_rdd = rv16_need_ciw_rdd |rv16_need_cl_rdd |rv16_need_cs_rdd |rv16_need_cb_rdd |rv16_need_cj_rdd ;
wire rv16_rs1en = (rv16_need_rs1 | rv16_need_rss1);
wire rv16_rs2en = (rv16_need_rs2 | rv16_need_rss2);
wire rv16_rden = (rv16_need_rd | rv16_need_rdd );
wire [`E203_RFIDX_WIDTH-1:0] rv16_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] rv16_rs2idx;
wire [`E203_RFIDX_WIDTH-1:0] rv16_rdidx ;
assign rv16_rs1idx =
({`E203_RFIDX_WIDTH{rv16_need_cr_rs1 }} & rv16_cr_rs1)
| ({`E203_RFIDX_WIDTH{rv16_need_ci_rs1 }} & rv16_ci_rs1)
| ({`E203_RFIDX_WIDTH{rv16_need_css_rs1}} & rv16_css_rs1)
| ({`E203_RFIDX_WIDTH{rv16_need_ciw_rss1}} & rv16_ciw_rss1)
| ({`E203_RFIDX_WIDTH{rv16_need_cl_rss1}} & rv16_cl_rss1)
| ({`E203_RFIDX_WIDTH{rv16_need_cs_rss1}} & rv16_cs_rss1)
| ({`E203_RFIDX_WIDTH{rv16_need_cb_rss1}} & rv16_cb_rss1)
| ({`E203_RFIDX_WIDTH{rv16_need_cj_rss1}} & rv16_cj_rss1)
;
assign rv16_rs2idx =
({`E203_RFIDX_WIDTH{rv16_need_cr_rs2 }} & rv16_cr_rs2)
| ({`E203_RFIDX_WIDTH{rv16_need_ci_rs2 }} & rv16_ci_rs2)
| ({`E203_RFIDX_WIDTH{rv16_need_css_rs2}} & rv16_css_rs2)
| ({`E203_RFIDX_WIDTH{rv16_need_ciw_rss2}} & rv16_ciw_rss2)
| ({`E203_RFIDX_WIDTH{rv16_need_cl_rss2}} & rv16_cl_rss2)
| ({`E203_RFIDX_WIDTH{rv16_need_cs_rss2}} & rv16_cs_rss2)
| ({`E203_RFIDX_WIDTH{rv16_need_cb_rss2}} & rv16_cb_rss2)
| ({`E203_RFIDX_WIDTH{rv16_need_cj_rss2}} & rv16_cj_rss2)
;
assign rv16_rdidx =
({`E203_RFIDX_WIDTH{rv16_need_cr_rd }} & rv16_cr_rd)
| ({`E203_RFIDX_WIDTH{rv16_need_ci_rd }} & rv16_ci_rd)
| ({`E203_RFIDX_WIDTH{rv16_need_css_rd}} & rv16_css_rd)
| ({`E203_RFIDX_WIDTH{rv16_need_ciw_rdd}} & rv16_ciw_rdd)
| ({`E203_RFIDX_WIDTH{rv16_need_cl_rdd}} & rv16_cl_rdd)
| ({`E203_RFIDX_WIDTH{rv16_need_cs_rdd}} & rv16_cs_rdd)
| ({`E203_RFIDX_WIDTH{rv16_need_cb_rdd}} & rv16_cb_rdd)
| ({`E203_RFIDX_WIDTH{rv16_need_cj_rdd}} & rv16_cj_rdd)
;
assign dec_rs1idx = rv32 ? rv32_rs1[`E203_RFIDX_WIDTH-1:0] : rv16_rs1idx;
assign dec_rs2idx = rv32 ? rv32_rs2[`E203_RFIDX_WIDTH-1:0] : rv16_rs2idx;
assign dec_rdidx = rv32 ? rv32_rd [`E203_RFIDX_WIDTH-1:0] : rv16_rdidx ;
assign dec_rs1en = rv32 ? rv32_need_rs1 : (rv16_rs1en & (~(rv16_rs1idx == `E203_RFIDX_WIDTH'b0)));
assign dec_rs2en = rv32 ? rv32_need_rs2 : (rv16_rs2en & (~(rv16_rs2idx == `E203_RFIDX_WIDTH'b0)));
assign dec_rdwen = rv32 ? rv32_need_rd : (rv16_rden & (~(rv16_rdidx == `E203_RFIDX_WIDTH'b0)));
assign dec_rs1x0 = (dec_rs1idx == `E203_RFIDX_WIDTH'b0);
assign dec_rs2x0 = (dec_rs2idx == `E203_RFIDX_WIDTH'b0);
wire rv_index_ilgl;
`ifdef E203_RFREG_NUM_IS_4 //{
assign rv_index_ilgl =
(| dec_rs1idx[`E203_RFIDX_WIDTH-1:2])
|(| dec_rs2idx[`E203_RFIDX_WIDTH-1:2])
|(| dec_rdidx [`E203_RFIDX_WIDTH-1:2])
;
`endif//}
`ifdef E203_RFREG_NUM_IS_8 //{
assign rv_index_ilgl =
(| dec_rs1idx[`E203_RFIDX_WIDTH-1:3])
|(| dec_rs2idx[`E203_RFIDX_WIDTH-1:3])
|(| dec_rdidx [`E203_RFIDX_WIDTH-1:3])
;
`endif//}
`ifdef E203_RFREG_NUM_IS_16 //{
assign rv_index_ilgl =
(| dec_rs1idx[`E203_RFIDX_WIDTH-1:4])
|(| dec_rs2idx[`E203_RFIDX_WIDTH-1:4])
|(| dec_rdidx [`E203_RFIDX_WIDTH-1:4])
;
`endif//}
`ifdef E203_RFREG_NUM_IS_32 //{
//Never happen this illegal exception
assign rv_index_ilgl = 1'b0;
`endif//}
assign dec_rv32 = rv32;
assign dec_bjp_imm =
({32{rv16_jal | rv16_j }} & rv16_jjal_imm)
| ({32{rv16_jalr_mv_add }} & rv16_jrjalr_imm)
| ({32{rv16_beqz | rv16_bnez }} & rv16_bxx_imm)
| ({32{rv32_jal }} & rv32_jal_imm)
| ({32{rv32_jalr }} & rv32_jalr_imm)
| ({32{rv32_branch }} & rv32_bxx_imm)
;
assign dec_jalr_rs1idx = rv32 ? rv32_rs1[`E203_RFIDX_WIDTH-1:0] : rv16_rs1[`E203_RFIDX_WIDTH-1:0];
assign dec_misalgn = i_misalgn;
assign dec_buserr = i_buserr ;
assign dec_ilegl =
(rv_all0s1s_ilgl)
| (rv_index_ilgl)
| (rv16_addi16sp_ilgl)
| (rv16_addi4spn_ilgl)
| (rv16_li_lui_ilgl)
| (rv16_sxxi_shamt_ilgl)
| (rv32_sxxi_shamt_ilgl)
| (rv32_dret_ilgl)
| (rv16_lwsp_ilgl)
| (~legl_ops);
endmodule
|
//sata_link_layer_write.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
//THERE APPEARS TO BE AN ERROR WHEN WRITING TO A HARDDRIVE, IT MANIFESTS AS A CRC ERROR
`include "sata_defines.v"
`define MIN_HOLDA_TIMEOUT 4
`define DHOLD_DELAY 8
`define DHOLD_DELAY_EN 0
module sata_link_layer_write(
input rst, //reset
input clk,
input phy_ready,
output write_ready,
input en,
output idle,
input send_sync_escape,
input detect_align,
input detect_sync,
input detect_x_rdy,
input detect_r_rdy,
input detect_r_ip,
input detect_r_err,
input detect_r_ok,
input detect_cont,
input detect_hold,
input detect_holda,
output reg send_holda,
output [31:0] tx_dout,
output tx_isk,
input [31:0] rx_din,
input [3:0] rx_isk,
input write_start,
output reg write_strobe,
input [31:0] write_data,
input [31:0] write_size, //maximum 2048
input write_hold,
output reg write_finished,
output reg xmit_error,
output reg wsize_z_error,
input write_abort,
input data_scrambler_en,
input is_device,
output reg [3:0] state,
output reg [3:0] fstate,
output reg last_prim,
output reg send_crc,
output reg post_align_write,
output reg [23:0] in_data_addra,
output reg [12:0] d_count,
output reg [12:0] write_count,
output reg [3:0] buffer_pos
);
//Primatives
parameter IDLE = 4'h0;
//fstate
parameter FIRST_DATA = 4'h1;
parameter ENQUEUE = 4'h2;
parameter WRITE_CRC = 4'h3;
parameter WAIT = 4'h4;
//state
parameter WRITE_START = 4'h1;
parameter WRITE = 4'h2;
parameter WRITE_END = 4'h3;
parameter WAIT_RESPONSE = 4'h4;
//Registers/Wires
reg [31:0] post_align_data;
reg send_x_rdy;
reg send_sof;
reg send_eof;
reg send_wtrm;
reg send_cont;
reg send_hold;
//reg send_holda;
reg send_sync;
//Transport
reg [31:0] align_data_out;
reg prev_phy_ready;
wire pos_phy_ready;
wire neg_phy_ready;
reg prev_hold;
//wire pos_hold;
wire neg_holda;
reg [3:0] min_holda_count;
wire min_holda_timeout;
reg [3:0] dhold_delay_cnt;
reg dhold_delay;
//CRC
//XXX: Tie the CRC_EN to the read strobe
wire [31:0] crc_dout;
reg [31:0] crc_data;
//Scrambler
reg scr_rst;
reg scr_en;
reg [31:0] scr_din;
wire [31:0] scr_dout;
//Internal FIFOs
reg [23:0] data_size;
reg wr_en;
wire [31:0] rd_dout;
wire empty;
wire enable_write_transaction;
reg [31:0] bump_buffer [0:3];
reg [3:0] data_pointer;
wire [31:0] d0_buf;
wire [31:0] d1_buf;
wire [31:0] d2_buf;
wire [31:0] d3_buf;
//Sub Modules
blk_mem # (
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (13 )
)br(
.clka (clk ),
.wea (wr_en ),
.addra (in_data_addra[12:0] ),
.dina (scr_dout ),
.clkb (clk ),
.addrb (write_count[12:0] ),
.doutb (rd_dout )
);
scrambler scr (
.rst (scr_rst ),
.clk (clk ),
.prim_scrambler (1'b0 ),
.en (scr_en ),
.din (scr_din ),
.dout (scr_dout )
);
crc c (
//reset the CRC any time we're in IDLE
.rst (scr_rst ),
.clk (clk ),
.en (write_strobe ),
.din (write_data ),
.dout (crc_dout )
);
//Asynchronous Logic
assign idle = (state == IDLE);
assign tx_dout = (send_x_rdy) ? `PRIM_X_RDY :
(send_sof) ? `PRIM_SOF :
(send_eof) ? `PRIM_EOF :
(send_wtrm) ? `PRIM_WTRM :
(send_cont) ? `PRIM_CONT :
(send_hold) ? `PRIM_HOLD :
(send_holda) ? `PRIM_HOLDA :
(send_sync) ? `PRIM_SYNC :
bump_buffer[buffer_pos];
assign tx_isk = ( send_x_rdy ||
send_sof ||
send_eof ||
send_wtrm ||
send_cont ||
send_hold ||
send_holda ||
send_sync);
assign enable_write_transaction = (in_data_addra != 0);
assign empty = (in_data_addra == 0);
assign pos_phy_ready = phy_ready && ~prev_phy_ready;
assign neg_phy_ready = ~phy_ready && prev_phy_ready;
//assign pos_hold = detect_hold && ~prev_hold;
assign min_holda_timeout = (min_holda_count >= `MIN_HOLDA_TIMEOUT);
assign d0_buf = bump_buffer[0];
assign d1_buf = bump_buffer[1];
assign d2_buf = bump_buffer[2];
assign d3_buf = bump_buffer[3];
assign write_ready = phy_ready && !send_holda;
//Synchronous Logic
//Incomming buffer (this is the buffer afte the scrambler and CRC)
always @ (posedge clk) begin
if (rst) begin
fstate <= IDLE;
data_size <= 0;
in_data_addra <= 0;
scr_din <= 0;
scr_en <= 0;
scr_rst <= 1;
wr_en <= 0;
write_strobe <= 0;
crc_data <= 0;
end
else begin
//Strobes
scr_en <= 0;
wr_en <= 0;
write_strobe <= 0;
scr_rst <= 0;
case (fstate)
IDLE: begin
in_data_addra <= 0;
if (write_start) begin
//add an extra space for the CRC
write_strobe <= 1;
data_size <= write_size;
scr_en <= 1;
scr_din <= 0;
fstate <= FIRST_DATA;
end
end
FIRST_DATA: begin
write_strobe <= 1;
wr_en <= 1;
scr_en <= 1;
scr_din <= write_data;
fstate <= ENQUEUE;
end
ENQUEUE: begin
if (data_size == 1) begin
in_data_addra <= in_data_addra + 1;
wr_en <= 1;
scr_en <= 1;
scr_din <= crc_dout;
fstate <= WRITE_CRC;
end
else begin
if (in_data_addra < data_size - 1) begin
// if (in_data_addra < data_size) begin
//Put all the data into the FIFO
write_strobe <= 1;
wr_en <= 1;
scr_en <= 1;
in_data_addra <= in_data_addra + 1;
scr_din <= write_data;
end
else begin
//put the CRC into the FIFO
//in_data_addra <= in_data_addra + 1;
wr_en <= 1;
scr_en <= 1;
in_data_addra <= in_data_addra + 1;
scr_din <= crc_dout;
fstate <= WRITE_CRC;
end
end
end
WRITE_CRC: begin
fstate <= WAIT;
end
WAIT: begin
scr_rst <= 1;
if (state == WRITE) begin
//Because a transaction is in progress and our write buffer is full we can reset the in address to 0
in_data_addra <= 0;
end
if (write_finished) begin
fstate <= IDLE;
data_size <= 0;
end
end
default: begin
fstate <= IDLE;
end
endcase
if (send_sync_escape) begin
fstate <= IDLE;
data_size <= 0;
end
end
end
//Detect Hold Delay
always @ (posedge clk) begin
if (rst) begin
dhold_delay <= 0;
dhold_delay_cnt <= 0;
end
else begin
if (dhold_delay_cnt < `DHOLD_DELAY) begin
dhold_delay_cnt <= dhold_delay_cnt + 1;
end
else begin
dhold_delay <= 1;
end
//Always deassert dhold_delay whenever detect hold goes low
if (!detect_hold) begin
dhold_delay_cnt <= 0;
dhold_delay <= 0;
end
end
end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
post_align_write <= 0;
post_align_data <= 32'h0;
send_x_rdy <= 0;
send_sof <= 0;
send_eof <= 0;
send_wtrm <= 0;
send_cont <= 0;
send_hold <= 0;
send_holda <= 0;
send_crc <= 0;
send_sync <= 0;
write_count <= 0;
//write_strobe <= 0;
write_finished <= 0;
//error strobe
xmit_error <= 0;
wsize_z_error <= 0;
last_prim <= 0;
align_data_out <= 0;
min_holda_count <= `MIN_HOLDA_TIMEOUT;
prev_phy_ready <= 0;
prev_hold <= 0;
bump_buffer[0] <= 0;
bump_buffer[1] <= 0;
bump_buffer[2] <= 0;
bump_buffer[3] <= 0;
d_count <= 0;
buffer_pos <= 0;
end
else begin
if ((state == WRITE_START) || ((state != IDLE) && (d_count != write_count))) begin
bump_buffer[3] <= bump_buffer[2];
bump_buffer[2] <= bump_buffer[1];
bump_buffer[1] <= bump_buffer[0];
bump_buffer[0] <= rd_dout;
d_count <= write_count;
end
//write_strobe <= 0;
write_finished <= 0;
xmit_error <= 0;
wsize_z_error <= 0;
//previous
prev_phy_ready <= phy_ready;
`ifdef DHOLD_DELAY_EN
prev_hold <= dhold_delay;
`else
prev_hold <= detect_hold;
`endif
if (min_holda_count < `MIN_HOLDA_TIMEOUT) begin
min_holda_count <= min_holda_count + 1;
end
if (phy_ready) begin
send_sync <= 0;
send_x_rdy <= 0;
send_sof <= 0;
send_eof <= 0;
send_wtrm <= 0;
send_cont <= 0;
send_hold <= 0;
send_holda <= 0;
send_crc <= 0;
last_prim <= 0;
end
case (state)
IDLE: begin
buffer_pos <= 0;
send_sync <= 1;
if (enable_write_transaction) begin
//There is some data within the input write buffer
state <= WRITE_START;
write_count <= 0;
d_count <= 0;
end
end
WRITE_START: begin
if (phy_ready) begin
send_sync <= 1;
if (!is_device && detect_x_rdy) begin
//hard drive wins the draw :(
state <= IDLE;
end
else if (detect_r_rdy) begin
state <= WRITE;
send_sof <= 1;
//bump_buffer[buffer_pos] <= rd_dout;
write_count <= write_count + 1;
//Send First Read
//read the first packet of data
end
else begin
send_x_rdy <= 1;
end
end
end
WRITE: begin
if (!write_ready) begin
if (neg_phy_ready && (buffer_pos == 0)) begin
buffer_pos <= buffer_pos + 1;
end
`ifdef DHOLD_DELAY_EN
if (dhold_delay || !min_holda_timeout) begin
`else
if (detect_hold || !min_holda_timeout) begin
`endif
//Haven't sent out a holda yet
send_holda <= 1;
end
else begin
//Detect the remote side finishing up with a hold
//if (!detect_hold && min_holda_timeout) begin
if (send_holda && !last_prim) begin
last_prim <= 1;
send_holda <= 1;
end
end
end
else begin
if (write_count <= data_size + 1) begin
if (buffer_pos > 0) begin
buffer_pos <= buffer_pos - 1;
if (buffer_pos == 1) begin
write_count <= write_count + 1;
end
end
else begin
write_count <= write_count + 1;
end
end
else begin
send_eof <= 1;
state <= WAIT_RESPONSE;
end
end
//I can use this to see if the phy is ready too
`ifdef DHOLD_DELAY_EN
if (dhold_delay && (buffer_pos == 0)) begin
`else
if (detect_hold && (buffer_pos == 0)) begin
`endif
min_holda_count <= 0;
//XXX: I may need this to capture holds at the end of a trnasfer
buffer_pos <= buffer_pos + 1;
send_holda <= 1;
end
end
WRITE_END: begin
state <= WAIT_RESPONSE;
end
WAIT_RESPONSE: begin
send_wtrm <= 1;
if (detect_r_err) begin
write_finished <= 1;
xmit_error <= 1;
state <= IDLE;
end
else if (detect_r_ok) begin
write_finished <= 1;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
if (send_sync_escape) begin
send_sync <= 1;
state <= IDLE;
buffer_pos <= 0;
write_count <= 0;
d_count <= 0;
end
end
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_pll (
input rx_clk,
output tx_mining_clk
);
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
assign tx_mining_clk = sub_wire1;
wire sub_wire2 = rx_clk;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/spifsm.v:3" *)
module \$paramod\SPIFSM\SPPRWidth=4\SPRWidth=4\DataWidth=8 (Reset_n_i, Clk_i, Start_i, Done_o, Byte0_o, Byte1_o, SPI_Transmission_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_Data_i, SPI_FIFOFull_i, SPI_FIFOEmpty_i, ADT7310CS_n_o, ParamCounterPreset_i);
(* src = "../../verilog/spifsm.v:187" *)
wire [7:0] \$0\Byte0_o[7:0] ;
(* src = "../../verilog/spifsm.v:187" *)
wire [7:0] \$0\Byte1_o[7:0] ;
(* src = "../../verilog/spifsm.v:217" *)
wire [31:0] \$0\SPI_FSM_Timer[31:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$2\ADT7310CS_n_o[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire [3:0] \$2\SPI_FSM_NextState[3:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$2\SPI_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$2\SPI_ReadNext_o[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire [3:0] \$3\SPI_FSM_NextState[3:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire [3:0] \$4\SPI_FSM_NextState[3:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire [3:0] \$5\SPI_FSM_NextState[3:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$2453 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2455 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2457 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2459 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2461 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2477 ;
wire \$procmux$297_CMP ;
wire \$procmux$298_CMP ;
wire \$procmux$301_CMP ;
wire \$procmux$302_CMP ;
wire \$procmux$305_CMP ;
wire \$procmux$334_CMP ;
wire \$procmux$335_CMP ;
wire \$procmux$336_CMP ;
wire \$procmux$455_CMP ;
wire [31:0] \$procmux$80_Y ;
(* src = "../../verilog/spifsm.v:231" *)
wire [31:0] \$sub$../../verilog/spifsm.v:231$46_Y ;
(* src = "../../verilog/spifsm.v:24" *)
output ADT7310CS_n_o;
(* src = "../../verilog/spifsm.v:13" *)
output [7:0] Byte0_o;
(* src = "../../verilog/spifsm.v:14" *)
output [7:0] Byte1_o;
(* src = "../../verilog/spifsm.v:9" *)
input Clk_i;
(* src = "../../verilog/spifsm.v:12" *)
output Done_o;
(* src = "../../verilog/spifsm.v:26" *)
input [31:0] ParamCounterPreset_i;
(* src = "../../verilog/spifsm.v:8" *)
input Reset_n_i;
(* src = "../../verilog/spifsm.v:20" *)
input [7:0] SPI_Data_i;
(* src = "../../verilog/spifsm.v:19" *)
output [7:0] SPI_Data_o;
(* src = "../../verilog/spifsm.v:22" *)
input SPI_FIFOEmpty_i;
(* src = "../../verilog/spifsm.v:21" *)
input SPI_FIFOFull_i;
(* src = "../../verilog/spifsm.v:42" *)
wire [3:0] SPI_FSM_NextState;
(* src = "../../verilog/spifsm.v:41" *)
wire [3:0] SPI_FSM_State;
(* src = "../../verilog/spifsm.v:215" *)
wire [31:0] SPI_FSM_Timer;
(* src = "../../verilog/spifsm.v:45" *)
wire SPI_FSM_TimerEnable;
(* src = "../../verilog/spifsm.v:43" *)
wire SPI_FSM_TimerOvfl;
(* src = "../../verilog/spifsm.v:44" *)
wire SPI_FSM_TimerPreset;
(* src = "../../verilog/spifsm.v:47" *)
wire SPI_FSM_Wr0;
(* src = "../../verilog/spifsm.v:46" *)
wire SPI_FSM_Wr1;
(* src = "../../verilog/spifsm.v:18" *)
output SPI_ReadNext_o;
(* src = "../../verilog/spifsm.v:16" *)
input SPI_Transmission_i;
(* src = "../../verilog/spifsm.v:17" *)
output SPI_Write_o;
(* src = "../../verilog/spifsm.v:11" *)
input Start_i;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2454 (
.A({ SPI_FSM_Wr1, SPI_FSM_Wr0, \$procmux$298_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2453 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000110),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2456 (
.A({ \$procmux$336_CMP , \$procmux$335_CMP , \$procmux$334_CMP , \$procmux$302_CMP , \$procmux$301_CMP , \$procmux$298_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2455 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000001001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2458 (
.A({ SPI_FSM_Wr1, SPI_FSM_Wr0, \$procmux$336_CMP , \$procmux$335_CMP , \$procmux$334_CMP , \$procmux$302_CMP , \$procmux$301_CMP , \$procmux$298_CMP , \$procmux$297_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2457 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2460 (
.A({ \$procmux$336_CMP , \$procmux$335_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2459 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2462 (
.A({ \$procmux$336_CMP , \$procmux$335_CMP , \$procmux$302_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2461 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2478 (
.A({ \$procmux$334_CMP , \$procmux$301_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2477 )
);
(* src = "../../verilog/spifsm.v:236" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/spifsm.v:236$47 (
.A(SPI_FSM_Timer),
.B(0),
.Y(SPI_FSM_TimerOvfl)
);
(* src = "../../verilog/spifsm.v:187" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2439 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte0_o[7:0] ),
.Q(Byte0_o)
);
(* src = "../../verilog/spifsm.v:187" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2440 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte1_o[7:0] ),
.Q(Byte1_o)
);
(* src = "../../verilog/spifsm.v:217" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$2441 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SPI_FSM_Timer[31:0] ),
.Q(SPI_FSM_Timer)
);
(* src = "../../verilog/spifsm.v:53" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(4'b0000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000000100)
) \$procdff$2442 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(SPI_FSM_NextState),
.Q(SPI_FSM_State)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$296 (
.A(1'b0),
.B({ 1'b1, \$2\SPI_FSM_TimerEnable[0:0] }),
.S({ \$procmux$298_CMP , \$procmux$297_CMP }),
.Y(SPI_FSM_TimerEnable)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$297_CMP0 (
.A(SPI_FSM_State),
.B(4'b0100),
.Y(\$procmux$297_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$298_CMP0 (
.A(SPI_FSM_State),
.B(4'b0011),
.Y(\$procmux$298_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$301_CMP0 (
.A(SPI_FSM_State),
.B(4'b0010),
.Y(\$procmux$301_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$302_CMP0 (
.A(SPI_FSM_State),
.B(4'b0001),
.Y(\$procmux$302_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$305_CMP0 (
.A(SPI_FSM_State),
.B(4'b0000),
.Y(\$procmux$305_CMP )
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$317 (
.A(1'b1),
.B({ 1'b0, SPI_FSM_TimerOvfl }),
.S({ \$procmux$298_CMP , \$procmux$297_CMP }),
.Y(SPI_FSM_TimerPreset)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$330_CMP0 (
.A(SPI_FSM_State),
.B(4'b1001),
.Y(SPI_FSM_Wr0)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$331_CMP0 (
.A(SPI_FSM_State),
.B(4'b1000),
.Y(SPI_FSM_Wr1)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$334_CMP0 (
.A(SPI_FSM_State),
.B(4'b0111),
.Y(\$procmux$334_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$335_CMP0 (
.A(SPI_FSM_State),
.B(4'b0110),
.Y(\$procmux$335_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$336_CMP0 (
.A(SPI_FSM_State),
.B(4'b0101),
.Y(\$procmux$336_CMP )
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$371 (
.A(1'b0),
.B({ \$2\SPI_ReadNext_o[0:0] , 1'b1 }),
.S({ \$auto$opt_reduce.cc:126:opt_mux$2477 , \$auto$opt_reduce.cc:126:opt_mux$2453 }),
.Y(SPI_ReadNext_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$396 (
.A(1'b1),
.B({ \$2\ADT7310CS_n_o[0:0] , \$2\SPI_FSM_TimerEnable[0:0] , 1'b0 }),
.S({ \$procmux$305_CMP , \$procmux$297_CMP , \$auto$opt_reduce.cc:126:opt_mux$2455 }),
.Y(ADT7310CS_n_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$413 (
.A(1'b1),
.B({ \$2\ADT7310CS_n_o[0:0] , 1'b0 }),
.S({ \$procmux$305_CMP , \$auto$opt_reduce.cc:126:opt_mux$2457 }),
.Y(Done_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$439 (
.A(8'b00001000),
.B(24'b001000000101000011111111),
.S({ \$procmux$302_CMP , \$procmux$297_CMP , \$auto$opt_reduce.cc:126:opt_mux$2459 }),
.Y(SPI_Data_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000001011),
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$454 (
.A(SPI_FSM_State),
.B({ \$2\SPI_FSM_NextState[3:0] , 4'b0010, \$3\SPI_FSM_NextState[3:0] , 4'b0100, \$4\SPI_FSM_NextState[3:0] , 8'b01100111, \$5\SPI_FSM_NextState[3:0] , 12'b100110100000 }),
.S({ \$procmux$305_CMP , \$procmux$302_CMP , \$procmux$301_CMP , \$procmux$298_CMP , \$procmux$297_CMP , \$procmux$336_CMP , \$procmux$335_CMP , \$procmux$334_CMP , SPI_FSM_Wr1, SPI_FSM_Wr0, \$procmux$455_CMP }),
.Y(SPI_FSM_NextState)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$455_CMP0 (
.A(SPI_FSM_State),
.B(4'b1010),
.Y(\$procmux$455_CMP )
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$481 (
.A(1'b0),
.B({ Start_i, SPI_FSM_TimerOvfl, 1'b1 }),
.S({ \$procmux$305_CMP , \$procmux$297_CMP , \$auto$opt_reduce.cc:126:opt_mux$2461 }),
.Y(SPI_Write_o)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$513 (
.A(SPI_FSM_State),
.B(4'b0001),
.S(Start_i),
.Y(\$2\SPI_FSM_NextState[3:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$535 (
.A(Start_i),
.Y(\$2\ADT7310CS_n_o[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$619 (
.A(4'b0011),
.B(SPI_FSM_State),
.S(SPI_Transmission_i),
.Y(\$3\SPI_FSM_NextState[3:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$641 (
.A(SPI_Transmission_i),
.Y(\$2\SPI_ReadNext_o[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$659 (
.A(SPI_FSM_TimerOvfl),
.Y(\$2\SPI_FSM_TimerEnable[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$70 (
.A(Byte0_o),
.B(SPI_Data_i),
.S(SPI_FSM_Wr0),
.Y(\$0\Byte0_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$703 (
.A(SPI_FSM_State),
.B(4'b0101),
.S(SPI_FSM_TimerOvfl),
.Y(\$4\SPI_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$77 (
.A(Byte1_o),
.B(SPI_Data_i),
.S(SPI_FSM_Wr1),
.Y(\$0\Byte1_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000100)
) \$procmux$786 (
.A(4'b1000),
.B(SPI_FSM_State),
.S(SPI_Transmission_i),
.Y(\$5\SPI_FSM_NextState[3:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$80 (
.A(SPI_FSM_Timer),
.B(\$sub$../../verilog/spifsm.v:231$46_Y ),
.S(SPI_FSM_TimerEnable),
.Y(\$procmux$80_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$83 (
.A(\$procmux$80_Y ),
.B(ParamCounterPreset_i),
.S(SPI_FSM_TimerPreset),
.Y(\$0\SPI_FSM_Timer[31:0] )
);
(* src = "../../verilog/spifsm.v:231" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/spifsm.v:231$46 (
.A(SPI_FSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/spifsm.v:231$46_Y )
);
endmodule
(* src = "../../verilog/sensorfsm.v:3" *)
module \$paramod\SensorFSM\DataWidth=8 (Reset_n_i, Clk_i, Enable_i, CpuIntr_o, SensorValue_o, MeasureFSM_Start_o, MeasureFSM_Done_i, MeasureFSM_Byte0_i, MeasureFSM_Byte1_i, ParamThreshold_i, ParamCounterPreset_i);
(* src = "../../verilog/sensorfsm.v:130" *)
wire [15:0] \$0\SensorFSM_Timer[15:0] ;
(* src = "../../verilog/sensorfsm.v:153" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$2\MeasureFSM_Start_o[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire [1:0] \$2\SensorFSM_NextState[1:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire [1:0] \$3\SensorFSM_NextState[1:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire [1:0] \$4\SensorFSM_NextState[1:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$4\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire [1:0] \$5\SensorFSM_NextState[1:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire [1:0] \$6\SensorFSM_NextState[1:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$2463 ;
wire \$procmux$1004_CMP ;
wire \$procmux$1007_CMP ;
wire \$procmux$1129_CMP ;
wire [15:0] \$procmux$826_Y ;
(* src = "../../verilog/sensorfsm.v:144" *)
wire [15:0] \$sub$../../verilog/sensorfsm.v:144$59_Y ;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/sensorfsm.v:7" *)
input Clk_i;
(* src = "../../verilog/sensorfsm.v:10" *)
output CpuIntr_o;
(* src = "../../verilog/sensorfsm.v:168" *)
wire [16:0] DiffAB;
(* src = "../../verilog/sensorfsm.v:169" *)
wire [15:0] DiffBA;
(* src = "../../verilog/sensorfsm.v:9" *)
input Enable_i;
(* src = "../../verilog/sensorfsm.v:15" *)
input [7:0] MeasureFSM_Byte0_i;
(* src = "../../verilog/sensorfsm.v:16" *)
input [7:0] MeasureFSM_Byte1_i;
(* src = "../../verilog/sensorfsm.v:14" *)
input MeasureFSM_Done_i;
(* src = "../../verilog/sensorfsm.v:13" *)
output MeasureFSM_Start_o;
(* src = "../../verilog/sensorfsm.v:19" *)
input [15:0] ParamCounterPreset_i;
(* src = "../../verilog/sensorfsm.v:18" *)
input [15:0] ParamThreshold_i;
(* src = "../../verilog/sensorfsm.v:6" *)
input Reset_n_i;
(* src = "../../verilog/sensorfsm.v:32" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/sensorfsm.v:28" *)
wire [1:0] SensorFSM_NextState;
(* src = "../../verilog/sensorfsm.v:27" *)
wire [1:0] SensorFSM_State;
(* src = "../../verilog/sensorfsm.v:33" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/sensorfsm.v:128" *)
wire [15:0] SensorFSM_Timer;
(* src = "../../verilog/sensorfsm.v:31" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/sensorfsm.v:29" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/sensorfsm.v:30" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/sensorfsm.v:37" *)
wire [15:0] SensorValue;
(* src = "../../verilog/sensorfsm.v:11" *)
output [15:0] SensorValue_o;
(* src = "../../verilog/sensorfsm.v:38" *)
wire [15:0] Word0;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2464 (
.A({ \$procmux$1129_CMP , \$procmux$1007_CMP , \$procmux$1004_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2463 )
);
(* src = "../../verilog/sensorfsm.v:149" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/sensorfsm.v:149$60 (
.A(SensorFSM_Timer),
.B(16'b0000000000000000),
.Y(SensorFSM_TimerOvfl)
);
(* src = "../../verilog/sensorfsm.v:174" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/sensorfsm.v:174$67 (
.A(AbsDiffResult),
.B(ParamThreshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/sensorfsm.v:130" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2443 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[15:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/sensorfsm.v:153" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2444 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
(* src = "../../verilog/sensorfsm.v:45" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(2'b00),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000000010)
) \$procdff$2445 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(SensorFSM_NextState),
.Q(SensorFSM_State)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1004_CMP0 (
.A(SensorFSM_State),
.B(2'b01),
.Y(\$procmux$1004_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1007_CMP0 (
.A(SensorFSM_State),
.B(2'b00),
.Y(\$procmux$1007_CMP )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000010)
) \$procmux$1020 (
.A(SensorFSM_State),
.B(2'b01),
.S(Enable_i),
.Y(\$2\SensorFSM_NextState[1:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1036 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1065 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\MeasureFSM_Start_o[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000010)
) \$procmux$1081 (
.A(2'b00),
.B(\$4\SensorFSM_NextState[1:0] ),
.S(Enable_i),
.Y(\$3\SensorFSM_NextState[1:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000010)
) \$procmux$1095 (
.A(SensorFSM_State),
.B(2'b10),
.S(SensorFSM_TimerOvfl),
.Y(\$4\SensorFSM_NextState[1:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000010)
) \$procmux$1126 (
.A(SensorFSM_State),
.B(\$6\SensorFSM_NextState[1:0] ),
.S(MeasureFSM_Done_i),
.Y(\$5\SensorFSM_NextState[1:0] )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1129_CMP0 (
.A(SensorFSM_State),
.B(2'b10),
.Y(\$procmux$1129_CMP )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1142 (
.A(MeasureFSM_Done_i),
.B(SensorFSM_DiffTooLarge),
.Y(\$2\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1174 (
.A(1'b1),
.B(\$4\SensorFSM_TimerPreset[0:0] ),
.S(MeasureFSM_Done_i),
.Y(\$3\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000010)
) \$procmux$1189 (
.A(2'b01),
.B(2'b11),
.S(SensorFSM_DiffTooLarge),
.Y(\$6\SensorFSM_NextState[1:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1206 (
.A(SensorFSM_DiffTooLarge),
.Y(\$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$826 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/sensorfsm.v:144$59_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$826_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$829 (
.A(\$procmux$826_Y ),
.B(ParamCounterPreset_i),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[15:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$832 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.S(SensorFSM_StoreNewValue),
.Y(\$0\Word0[15:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$923 (
.A(\$auto$opt_reduce.cc:126:opt_mux$2463 ),
.Y(CpuIntr_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$943 (
.A(\$procmux$1004_CMP ),
.B(\$2\MeasureFSM_Start_o[0:0] ),
.Y(MeasureFSM_Start_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$953 (
.A(\$procmux$1129_CMP ),
.B(\$2\SensorFSM_StoreNewValue[0:0] ),
.Y(SensorFSM_StoreNewValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000010)
) \$procmux$968 (
.A(2'b01),
.B({ \$2\SensorFSM_NextState[1:0] , \$3\SensorFSM_NextState[1:0] , \$5\SensorFSM_NextState[1:0] }),
.S({ \$procmux$1007_CMP , \$procmux$1004_CMP , \$procmux$1129_CMP }),
.Y(SensorFSM_NextState)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$983 (
.A(1'b0),
.B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$procmux$1007_CMP , \$procmux$1004_CMP , \$procmux$1129_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$998 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$procmux$1007_CMP , \$procmux$1004_CMP , \$procmux$1129_CMP }),
.Y(SensorFSM_TimerPreset)
);
(* src = "../../verilog/sensorfsm.v:144" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/sensorfsm.v:144$59 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/sensorfsm.v:144$59_Y )
);
(* src = "../../verilog/sensorfsm.v:170" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/sensorfsm.v:170$64 (
.A({ 1'b0, MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/sensorfsm.v:171" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/sensorfsm.v:171$65 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.Y(DiffBA)
);
(* src = "../../verilog/sensorfsm.v:172" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/sensorfsm.v:172$66 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
assign SensorValue = { MeasureFSM_Byte1_i, MeasureFSM_Byte0_i };
assign SensorValue_o = Word0;
endmodule
(* src = "../../verilog/adt7310.v:1" *)
module ADT7310(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, ADT7310CS_n_o, SPI_Data_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_FIFOFull_i, SPI_FIFOEmpty_i, SPI_Transmission_i, SPICounterPresetH_i, SPICounterPresetL_i, Threshold_i, PeriodCounterPreset_i, SensorValue_o, SPI_CPOL_o, SPI_CPHA_o, SPI_LSBFE_o);
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/adt7310.v:11" *)
output ADT7310CS_n_o;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/adt7310.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/adt7310.v:9" *)
output CpuIntr_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/adt7310.v:7" *)
input Enable_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPreset_i" *)
(* src = "../../verilog/adt7310.v:33" *)
input [15:0] PeriodCounterPreset_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/adt7310.v:3" *)
input Reset_n_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SPICounterPresetH_i" *)
(* src = "../../verilog/adt7310.v:27" *)
input [15:0] SPICounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SPICounterPresetL_i" *)
(* src = "../../verilog/adt7310.v:29" *)
input [15:0] SPICounterPresetL_i;
(* keep = 1 *)
(* src = "../../verilog/adt7310.v:56" *)
wire [7:0] SPIFSM_Byte0_s;
(* keep = 1 *)
(* src = "../../verilog/adt7310.v:58" *)
wire [7:0] SPIFSM_Byte1_s;
(* keep = 1 *)
(* src = "../../verilog/adt7310.v:54" *)
wire SPIFSM_Done_s;
(* keep = 1 *)
(* src = "../../verilog/adt7310.v:52" *)
wire SPIFSM_Start_s;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPHA" *)
(* src = "../../verilog/adt7310.v:39" *)
output SPI_CPHA_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPOL" *)
(* src = "../../verilog/adt7310.v:37" *)
output SPI_CPOL_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataOut" *)
(* src = "../../verilog/adt7310.v:13" *)
input [7:0] SPI_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataIn" *)
(* src = "../../verilog/adt7310.v:19" *)
output [7:0] SPI_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOEmpty" *)
(* src = "../../verilog/adt7310.v:23" *)
input SPI_FIFOEmpty_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOFull" *)
(* src = "../../verilog/adt7310.v:21" *)
input SPI_FIFOFull_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_LSBFE" *)
(* src = "../../verilog/adt7310.v:41" *)
output SPI_LSBFE_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_ReadNext" *)
(* src = "../../verilog/adt7310.v:17" *)
output SPI_ReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Transmission" *)
(* src = "../../verilog/adt7310.v:25" *)
input SPI_Transmission_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Write" *)
(* src = "../../verilog/adt7310.v:15" *)
output SPI_Write_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/adt7310.v:35" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/adt7310.v:31" *)
input [15:0] Threshold_i;
(* src = "../../verilog/adt7310.v:60" *)
\$paramod\SPIFSM\SPPRWidth=4\SPRWidth=4\DataWidth=8 SPIFSM_1 (
.ADT7310CS_n_o(ADT7310CS_n_o),
.Byte0_o(SPIFSM_Byte0_s),
.Byte1_o(SPIFSM_Byte1_s),
.Clk_i(Clk_i),
.Done_o(SPIFSM_Done_s),
.ParamCounterPreset_i({ SPICounterPresetH_i, SPICounterPresetL_i }),
.Reset_n_i(Reset_n_i),
.SPI_Data_i(SPI_Data_i),
.SPI_Data_o(SPI_Data_o),
.SPI_FIFOEmpty_i(SPI_FIFOEmpty_i),
.SPI_FIFOFull_i(SPI_FIFOFull_i),
.SPI_ReadNext_o(SPI_ReadNext_o),
.SPI_Transmission_i(SPI_Transmission_i),
.SPI_Write_o(SPI_Write_o),
.Start_i(SPIFSM_Start_s)
);
(* src = "../../verilog/adt7310.v:86" *)
\$paramod\SensorFSM\DataWidth=8 SensorFSM_1 (
.Clk_i(Clk_i),
.CpuIntr_o(CpuIntr_o),
.Enable_i(Enable_i),
.MeasureFSM_Byte0_i(SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i(SPIFSM_Byte1_s),
.MeasureFSM_Done_i(SPIFSM_Done_s),
.MeasureFSM_Start_o(SPIFSM_Start_s),
.ParamCounterPreset_i(PeriodCounterPreset_i),
.ParamThreshold_i(Threshold_i),
.Reset_n_i(Reset_n_i),
.SensorValue_o(SensorValue_o)
);
assign SPI_CPHA_o = 1'b1;
assign SPI_CPOL_o = 1'b1;
assign SPI_LSBFE_o = 1'b0;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_3x.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_3x (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire6 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire locked = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "LOW",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 3,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 4,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_3x",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "81.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "108.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_bb.v FALSE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
resetrequest <= 1'b0;
break_on_reset <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 27: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 29: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 31: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 31: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 31: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
itm,
trc_ctrl,
trc_on
)
;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exc_occured;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] eic_addr;
wire [ 31: 0] exc_addr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_external_interrupt;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc_record_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire sync_timer_reached_zero;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exc_occured = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_external_interrupt = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign exc_addr = 32'b0;
assign eic_addr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_timer_reached_zero = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | advanced_exc_occured)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_exc <= 1;
pending_exc_addr <= exc_addr;
pending_exc_record_handler <= 0;
if (is_external_interrupt)
pending_exc_handler <= eic_addr;
else if (is_fast_tlb_miss_exception)
pending_exc_handler <= 32'h0;
else
pending_exc_handler <= 32'h0;
pending_frametype <= 4'b0000;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exc_occured)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
end
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else if (record_itrace & pending_exc)
begin
if (pending_exc_record_handler)
begin
itm <= {4'b0010, pending_exc_handler[31 : 1], 1'b1};
pending_exc <= 1'b0;
pending_exc_record_handler <= 1'b0;
end
else
begin
itm <= {4'b0010, pending_exc_addr[31 : 1], 1'b0};
pending_exc_record_handler <= 1'b1;
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 1'b0;
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 31: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//nios_dut_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
nios_dut_nios2_gen2_0_cpu_nios2_oci_td_mode nios_dut_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else
begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait|cpu_d_read|cpu_d_write;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
)
;
output [ 1: 0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_input_tm_cnt;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
)
;
output [ 3: 0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 3: 0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt)
begin
if (ge3_free & (input_tm_cnt == 3))
fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1)
fifo_wrptr_inc = 1;
else
fifo_wrptr_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
)
;
output [ 4: 0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 4: 0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt)
begin
if (empty)
fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3))
fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1)
fifo_cnt_inc = 0;
else
fifo_cnt_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dtm,
itm,
jrst_n,
reset_n,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_input_tm_cnt;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifo_cnt_inc;
wire [ 35: 0] fifo_head;
reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] fifo_read_mux;
reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifo_wrptr_inc;
wire [ 3: 0] fifo_wrptr_plus1;
wire [ 3: 0] fifo_wrptr_plus2;
wire ge2_free;
wire ge3_free;
wire input_ge1;
wire input_ge2;
wire input_ge3;
wire [ 1: 0] input_tm_cnt;
wire itm_valid;
reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] overflow_pending_atm;
wire [ 35: 0] overflow_pending_dtm;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign ge2_free = ~fifo_cnt[4];
assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
assign empty = ~|fifo_cnt;
assign fifo_wrptr_plus1 = fifo_wrptr + 1;
assign fifo_wrptr_plus2 = fifo_wrptr + 2;
nios_dut_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt the_nios_dut_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt
(
.atm_valid (atm_valid),
.compute_input_tm_cnt (compute_input_tm_cnt),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign input_tm_cnt = compute_input_tm_cnt;
nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc the_nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc
(
.fifo_wrptr_inc (fifo_wrptr_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc the_nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc
(
.empty (empty),
.fifo_cnt_inc (fifo_cnt_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fifo_rdptr <= 0;
fifo_wrptr <= 0;
fifo_cnt <= 0;
overflow_pending <= 1;
end
else
begin
fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
fifo_cnt <= fifo_cnt + fifo_cnt_inc;
if (~empty)
fifo_rdptr <= fifo_rdptr + 1;
if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
overflow_pending <= 1;
else if (atm_valid | dtm_valid)
overflow_pending <= 0;
end
end
assign fifo_head = fifo_read_mux;
assign tw = itm;
assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
(((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
(((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
(((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
(((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
(((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
(((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
(((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
(((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
(((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
(((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
(((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
(((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
(((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
(((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
(((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
(((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign input_ge1 = |input_tm_cnt;
assign input_ge2 = input_tm_cnt[1];
assign input_ge3 = &input_tm_cnt;
assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
(fifo_rdptr == 4'd1)? fifo_1 :
(fifo_rdptr == 4'd2)? fifo_2 :
(fifo_rdptr == 4'd3)? fifo_3 :
(fifo_rdptr == 4'd4)? fifo_4 :
(fifo_rdptr == 4'd5)? fifo_5 :
(fifo_rdptr == 4'd6)? fifo_6 :
(fifo_rdptr == 4'd7)? fifo_7 :
(fifo_rdptr == 4'd8)? fifo_8 :
(fifo_rdptr == 4'd9)? fifo_9 :
(fifo_rdptr == 4'd10)? fifo_10 :
(fifo_rdptr == 4'd11)? fifo_11 :
(fifo_rdptr == 4'd12)? fifo_12 :
(fifo_rdptr == 4'd13)? fifo_13 :
(fifo_rdptr == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
)
;
output [ 35: 0] tr_data;
wire [ 35: 0] tr_data;
assign tr_data = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000001011111;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000001011111);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input reset_req;
input wren;
wire clocken;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.clocken0 (clocken),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
reset_req,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input reset_req;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
//nios_dut_nios2_gen2_0_cpu_ociram_sp_ram, which is an nios_sp_ram
nios_dut_nios2_gen2_0_cpu_ociram_sp_ram_module nios_dut_nios2_gen2_0_cpu_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.reset_req (reset_req),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam nios_dut_nios2_gen2_0_cpu_ociram_sp_ram.lpm_file = "nios_dut_nios2_gen2_0_cpu_ociram_default_contents.dat";
`else
defparam nios_dut_nios2_gen2_0_cpu_ociram_sp_ram.lpm_file = "nios_dut_nios2_gen2_0_cpu_ociram_default_contents.hex";
`endif
//synthesis translate_on
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd1)? 32'h0000201e :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
reset_req,
write_nxt,
writedata_nxt,
// outputs:
debug_mem_slave_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output debug_mem_slave_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 27: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 31: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input reset_req;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire [ 31: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire debug_mem_slave_debugaccess_to_roms;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire [ 35: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
nios_dut_nios2_gen2_0_cpu_nios2_oci_debug the_nios_dut_nios2_gen2_0_cpu_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_break the_nios_dut_nios2_gen2_0_cpu_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_xbrk the_nios_dut_nios2_gen2_0_cpu_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_dbrk the_nios_dut_nios2_gen2_0_cpu_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_itrace the_nios_dut_nios2_gen2_0_cpu_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_dtrace the_nios_dut_nios2_gen2_0_cpu_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo the_nios_dut_nios2_gen2_0_cpu_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.trc_on (trc_on),
.tw (tw)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_pib the_nios_dut_nios2_gen2_0_cpu_nios2_oci_pib
(
.tr_data (tr_data)
);
nios_dut_nios2_gen2_0_cpu_nios2_oci_im the_nios_dut_nios2_gen2_0_cpu_nios2_oci_im
(
.clk (clk),
.jrst_n (jrst_n),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
nios_dut_nios2_gen2_0_cpu_nios2_avalon_reg the_nios_dut_nios2_gen2_0_cpu_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
nios_dut_nios2_gen2_0_cpu_nios2_ocimem the_nios_dut_nios2_gen2_0_cpu_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.reset_req (reset_req),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign debug_mem_slave_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
nios_dut_nios2_gen2_0_cpu_debug_slave_wrapper the_nios_dut_nios2_gen2_0_cpu_debug_slave_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_data |
trigout |
debugack;
assign debugreq = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu (
// inputs:
clk,
d_readdata,
d_waitrequest,
debug_mem_slave_address,
debug_mem_slave_byteenable,
debug_mem_slave_debugaccess,
debug_mem_slave_read,
debug_mem_slave_write,
debug_mem_slave_writedata,
i_readdata,
i_waitrequest,
irq,
reset_n,
reset_req,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
debug_mem_slave_debugaccess_to_roms,
debug_mem_slave_readdata,
debug_mem_slave_waitrequest,
debug_reset_request,
dummy_ci_port,
i_address,
i_read
)
;
output [ 31: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output debug_mem_slave_debugaccess_to_roms;
output [ 31: 0] debug_mem_slave_readdata;
output debug_mem_slave_waitrequest;
output debug_reset_request;
output dummy_ci_port;
output [ 29: 0] i_address;
output i_read;
input clk;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 8: 0] debug_mem_slave_address;
input [ 3: 0] debug_mem_slave_byteenable;
input debug_mem_slave_debugaccess;
input debug_mem_slave_read;
input debug_mem_slave_write;
input [ 31: 0] debug_mem_slave_writedata;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 31: 0] irq;
input reset_n;
input reset_req;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_and;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_intr_inst;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_ex;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_ld_st_ex;
wire D_ctrl_logic;
wire D_ctrl_mem16;
wire D_ctrl_mem32;
wire D_ctrl_mem8;
wire D_ctrl_rd_ctl_reg;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_set_src2_rem_imm;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_signed_imm12;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_src_imm5_shift_rot;
wire D_ctrl_st;
wire D_ctrl_st_ex;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
wire D_is_opx_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 4: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 27: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 71: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 31: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
wire E_rf_ecc_recoverable_valid;
wire E_rf_ecc_unrecoverable_valid;
wire E_rf_ecc_valid_any;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire [ 4: 0] E_shift_rot_shfcnt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
wire E_valid;
reg E_valid_from_R;
wire [ 71: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 4: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire F_is_opx_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 4: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 1: 0] F_jmp_direct_pc_hi;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_op_rsv02;
wire F_op_op_rsv09;
wire F_op_op_rsv10;
wire F_op_op_rsv17;
wire F_op_op_rsv18;
wire F_op_op_rsv25;
wire F_op_op_rsv26;
wire F_op_op_rsv33;
wire F_op_op_rsv34;
wire F_op_op_rsv41;
wire F_op_op_rsv42;
wire F_op_op_rsv49;
wire F_op_op_rsv57;
wire F_op_op_rsv61;
wire F_op_op_rsv62;
wire F_op_op_rsv63;
wire F_op_opx_rsv00;
wire F_op_opx_rsv10;
wire F_op_opx_rsv15;
wire F_op_opx_rsv17;
wire F_op_opx_rsv21;
wire F_op_opx_rsv25;
wire F_op_opx_rsv33;
wire F_op_opx_rsv34;
wire F_op_opx_rsv35;
wire F_op_opx_rsv42;
wire F_op_opx_rsv43;
wire F_op_opx_rsv44;
wire F_op_opx_rsv47;
wire F_op_opx_rsv50;
wire F_op_opx_rsv51;
wire F_op_opx_rsv55;
wire F_op_opx_rsv56;
wire F_op_opx_rsv60;
wire F_op_opx_rsv63;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 27: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 27: 0] F_pc_no_crst_nxt;
wire [ 27: 0] F_pc_nxt;
wire [ 27: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 29: 0] F_pcb;
wire [ 29: 0] F_pcb_nxt;
wire [ 29: 0] F_pcb_plus_four;
wire F_valid;
wire [ 71: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_and;
wire R_ctrl_alu_force_and_nxt;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_intr_inst;
wire R_ctrl_intr_inst_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_ex;
wire R_ctrl_ld_ex_nxt;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_ld_st_ex;
wire R_ctrl_ld_st_ex_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_mem16;
wire R_ctrl_mem16_nxt;
reg R_ctrl_mem32;
wire R_ctrl_mem32_nxt;
reg R_ctrl_mem8;
wire R_ctrl_mem8_nxt;
reg R_ctrl_rd_ctl_reg;
wire R_ctrl_rd_ctl_reg_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_set_src2_rem_imm;
wire R_ctrl_set_src2_rem_imm_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_signed_imm12;
wire R_ctrl_signed_imm12_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_src_imm5_shift_rot;
wire R_ctrl_src_imm5_shift_rot_nxt;
reg R_ctrl_st;
reg R_ctrl_st_ex;
wire R_ctrl_st_ex_nxt;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_a_q;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_rf_b_q;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
wire [ 31: 0] R_stw_data;
reg R_valid;
wire [ 71: 0] R_vinst;
reg R_wr_dst_reg;
reg W1_rf_ecc_recoverable_valid;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg [ 31: 0] W_cdsr_reg;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
wire [ 31: 0] W_cpuid_reg;
wire [ 4: 0] W_dst_regnum;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 31: 0] W_mem_baddr;
reg W_rf_ecc_recoverable_valid;
reg W_rf_ecc_unrecoverable_valid;
wire W_rf_ecc_valid_any;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_up_ex_mon_state;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 71: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 31: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
reg d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
wire debug_mem_slave_clk;
wire debug_mem_slave_debugaccess_to_roms;
wire [ 31: 0] debug_mem_slave_readdata;
wire debug_mem_slave_reset;
wire debug_mem_slave_waitrequest;
wire debug_reset_request;
wire dummy_ci_port;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 29: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_nios_dut_nios2_gen2_0_cpu_test_bench, which is an e_instance
nios_dut_nios2_gen2_0_cpu_test_bench the_nios_dut_nios2_gen2_0_cpu_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[10 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[10 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[10 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_op_rsv02 = F_iw_op == 2;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_op_rsv09 = F_iw_op == 9;
assign F_op_op_rsv10 = F_iw_op == 10;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_op_rsv17 = F_iw_op == 17;
assign F_op_op_rsv18 = F_iw_op == 18;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_op_rsv25 = F_iw_op == 25;
assign F_op_op_rsv26 = F_iw_op == 26;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_op_rsv33 = F_iw_op == 33;
assign F_op_op_rsv34 = F_iw_op == 34;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_op_rsv41 = F_iw_op == 41;
assign F_op_op_rsv42 = F_iw_op == 42;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_op_rsv49 = F_iw_op == 49;
assign F_op_custom = F_iw_op == 50;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_op_rsv57 = F_iw_op == 57;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_op_rsv61 = F_iw_op == 61;
assign F_op_op_rsv62 = F_iw_op == 62;
assign F_op_op_rsv63 = F_iw_op == 63;
assign F_op_opx_rsv00 = (F_iw_opx == 0) & F_is_opx_inst;
assign F_op_eret = (F_iw_opx == 1) & F_is_opx_inst;
assign F_op_roli = (F_iw_opx == 2) & F_is_opx_inst;
assign F_op_rol = (F_iw_opx == 3) & F_is_opx_inst;
assign F_op_flushp = (F_iw_opx == 4) & F_is_opx_inst;
assign F_op_ret = (F_iw_opx == 5) & F_is_opx_inst;
assign F_op_nor = (F_iw_opx == 6) & F_is_opx_inst;
assign F_op_mulxuu = (F_iw_opx == 7) & F_is_opx_inst;
assign F_op_cmpge = (F_iw_opx == 8) & F_is_opx_inst;
assign F_op_bret = (F_iw_opx == 9) & F_is_opx_inst;
assign F_op_opx_rsv10 = (F_iw_opx == 10) & F_is_opx_inst;
assign F_op_ror = (F_iw_opx == 11) & F_is_opx_inst;
assign F_op_flushi = (F_iw_opx == 12) & F_is_opx_inst;
assign F_op_jmp = (F_iw_opx == 13) & F_is_opx_inst;
assign F_op_and = (F_iw_opx == 14) & F_is_opx_inst;
assign F_op_opx_rsv15 = (F_iw_opx == 15) & F_is_opx_inst;
assign F_op_cmplt = (F_iw_opx == 16) & F_is_opx_inst;
assign F_op_opx_rsv17 = (F_iw_opx == 17) & F_is_opx_inst;
assign F_op_slli = (F_iw_opx == 18) & F_is_opx_inst;
assign F_op_sll = (F_iw_opx == 19) & F_is_opx_inst;
assign F_op_wrprs = (F_iw_opx == 20) & F_is_opx_inst;
assign F_op_opx_rsv21 = (F_iw_opx == 21) & F_is_opx_inst;
assign F_op_or = (F_iw_opx == 22) & F_is_opx_inst;
assign F_op_mulxsu = (F_iw_opx == 23) & F_is_opx_inst;
assign F_op_cmpne = (F_iw_opx == 24) & F_is_opx_inst;
assign F_op_opx_rsv25 = (F_iw_opx == 25) & F_is_opx_inst;
assign F_op_srli = (F_iw_opx == 26) & F_is_opx_inst;
assign F_op_srl = (F_iw_opx == 27) & F_is_opx_inst;
assign F_op_nextpc = (F_iw_opx == 28) & F_is_opx_inst;
assign F_op_callr = (F_iw_opx == 29) & F_is_opx_inst;
assign F_op_xor = (F_iw_opx == 30) & F_is_opx_inst;
assign F_op_mulxss = (F_iw_opx == 31) & F_is_opx_inst;
assign F_op_cmpeq = (F_iw_opx == 32) & F_is_opx_inst;
assign F_op_opx_rsv33 = (F_iw_opx == 33) & F_is_opx_inst;
assign F_op_opx_rsv34 = (F_iw_opx == 34) & F_is_opx_inst;
assign F_op_opx_rsv35 = (F_iw_opx == 35) & F_is_opx_inst;
assign F_op_divu = (F_iw_opx == 36) & F_is_opx_inst;
assign F_op_div = (F_iw_opx == 37) & F_is_opx_inst;
assign F_op_rdctl = (F_iw_opx == 38) & F_is_opx_inst;
assign F_op_mul = (F_iw_opx == 39) & F_is_opx_inst;
assign F_op_cmpgeu = (F_iw_opx == 40) & F_is_opx_inst;
assign F_op_initi = (F_iw_opx == 41) & F_is_opx_inst;
assign F_op_opx_rsv42 = (F_iw_opx == 42) & F_is_opx_inst;
assign F_op_opx_rsv43 = (F_iw_opx == 43) & F_is_opx_inst;
assign F_op_opx_rsv44 = (F_iw_opx == 44) & F_is_opx_inst;
assign F_op_trap = (F_iw_opx == 45) & F_is_opx_inst;
assign F_op_wrctl = (F_iw_opx == 46) & F_is_opx_inst;
assign F_op_opx_rsv47 = (F_iw_opx == 47) & F_is_opx_inst;
assign F_op_cmpltu = (F_iw_opx == 48) & F_is_opx_inst;
assign F_op_add = (F_iw_opx == 49) & F_is_opx_inst;
assign F_op_opx_rsv50 = (F_iw_opx == 50) & F_is_opx_inst;
assign F_op_opx_rsv51 = (F_iw_opx == 51) & F_is_opx_inst;
assign F_op_break = (F_iw_opx == 52) & F_is_opx_inst;
assign F_op_hbreak = (F_iw_opx == 53) & F_is_opx_inst;
assign F_op_sync = (F_iw_opx == 54) & F_is_opx_inst;
assign F_op_opx_rsv55 = (F_iw_opx == 55) & F_is_opx_inst;
assign F_op_opx_rsv56 = (F_iw_opx == 56) & F_is_opx_inst;
assign F_op_sub = (F_iw_opx == 57) & F_is_opx_inst;
assign F_op_srai = (F_iw_opx == 58) & F_is_opx_inst;
assign F_op_sra = (F_iw_opx == 59) & F_is_opx_inst;
assign F_op_opx_rsv60 = (F_iw_opx == 60) & F_is_opx_inst;
assign F_op_intr = (F_iw_opx == 61) & F_is_opx_inst;
assign F_op_crst = (F_iw_opx == 62) & F_is_opx_inst;
assign F_op_opx_rsv63 = (F_iw_opx == 63) & F_is_opx_inst;
assign F_is_opx_inst = F_iw_op == 58;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign dummy_ci_port = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = irq[31 : 0] & 32'b00000000000000000000000001011111;
assign F_pc_sel_nxt = (R_ctrl_exception | W_rf_ecc_unrecoverable_valid) ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 0 :
(F_pc_sel_nxt == 2'b01)? 67109384 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[29 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid | W_rf_ecc_unrecoverable_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 134217728;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | W_rf_ecc_unrecoverable_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid | W1_rf_ecc_recoverable_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_is_opx_inst ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 :
D_ctrl_alu_force_and ? 2'b01 :
D_logic_op_raw;
assign D_compare_op = D_is_opx_inst ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign F_jmp_direct_pc_hi = F_pc[27 : 26];
assign D_jmp_direct_target_waddr = {F_jmp_direct_pc_hi, D_iw[31 : 6]};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign E_rf_ecc_valid_any = E_rf_ecc_recoverable_valid|E_rf_ecc_unrecoverable_valid;
assign W_rf_ecc_valid_any = W_rf_ecc_recoverable_valid|W_rf_ecc_unrecoverable_valid;
assign E_rf_ecc_recoverable_valid = 1'b0;
assign E_rf_ecc_unrecoverable_valid = 1'b0;
assign W_dst_regnum = R_dst_regnum;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_rf_ecc_recoverable_valid <= 0;
else
W_rf_ecc_recoverable_valid <= E_rf_ecc_recoverable_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W1_rf_ecc_recoverable_valid <= 0;
else
W1_rf_ecc_recoverable_valid <= W_rf_ecc_recoverable_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_rf_ecc_unrecoverable_valid <= 0;
else
W_rf_ecc_unrecoverable_valid <= E_rf_ecc_unrecoverable_valid & ~E_rf_ecc_recoverable_valid;
end
assign R_rf_a = R_rf_a_q;
assign R_rf_b = R_rf_b_q;
assign W_rf_wren = (R_wr_dst_reg & W_valid) | W_rf_ecc_valid_any | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//nios_dut_nios2_gen2_0_cpu_register_bank_a, which is an nios_sdp_ram
nios_dut_nios2_gen2_0_cpu_register_bank_a_module nios_dut_nios2_gen2_0_cpu_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a_q),
.rdaddress (D_iw_a),
.wraddress (W_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam nios_dut_nios2_gen2_0_cpu_register_bank_a.lpm_file = "nios_dut_nios2_gen2_0_cpu_rf_ram_a.dat";
`else
defparam nios_dut_nios2_gen2_0_cpu_register_bank_a.lpm_file = "nios_dut_nios2_gen2_0_cpu_rf_ram_a.hex";
`endif
//synthesis translate_on
//nios_dut_nios2_gen2_0_cpu_register_bank_b, which is an nios_sdp_ram
nios_dut_nios2_gen2_0_cpu_register_bank_b_module nios_dut_nios2_gen2_0_cpu_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b_q),
.rdaddress (D_iw_b),
.wraddress (W_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam nios_dut_nios2_gen2_0_cpu_register_bank_b.lpm_file = "nios_dut_nios2_gen2_0_cpu_rf_ram_b.dat";
`else
defparam nios_dut_nios2_gen2_0_cpu_register_bank_b.lpm_file = "nios_dut_nios2_gen2_0_cpu_rf_ram_b.hex";
`endif
//synthesis translate_on
assign R_src1 = (((R_ctrl_br & E_valid_from_R) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid_from_R))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
(R_ctrl_src_imm5_shift_rot)? {{11 {1'b0}},D_iw_imm5} :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid_from_R <= 0;
else
E_valid_from_R <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_valid = E_valid_from_R & ~E_rf_ecc_valid_any;
assign E_stall = (E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall) & ~(E_rf_ecc_valid_any|W_rf_ecc_valid_any|W1_rf_ecc_recoverable_valid);
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[31 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_shfcnt = E_src2[4 : 0];
assign E_shift_rot_cnt_nxt = E_new_inst ? E_shift_rot_shfcnt : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 5'd0)? W_status_reg :
(D_iw_control_regnum == 5'd1)? W_estatus_reg :
(D_iw_control_regnum == 5'd2)? W_bstatus_reg :
(D_iw_control_regnum == 5'd3)? W_ienable_reg :
(D_iw_control_regnum == 5'd4)? W_ipending_reg :
(D_iw_control_regnum == 5'd5)? W_cpuid_reg :
W_cdsr_reg;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rd_ctl_reg))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_sth_data = R_rf_b[15 : 0];
assign R_stw_data = R_rf_b[31 : 0];
assign R_stb_data = R_rf_b[7 : 0];
assign E_st_data = (D_ctrl_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_ctrl_mem16)? {R_sth_data, R_sth_data} :
R_stw_data;
assign E_mem_byte_en = ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0001 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0010 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b0100 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1000 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b00})? 4'b0011 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b01})? 4'b0011 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b10})? 4'b1100 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst & ~E_rf_ecc_valid_any) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = ((R_ctrl_st & (~R_ctrl_st_ex | W_up_ex_mon_state)) & E_new_inst & ~E_rf_ecc_valid_any) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_ctrl_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_ctrl_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_ctrl_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_ctrl_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_ctrl_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_up_ex_mon_state <= 0;
else if (R_en)
W_up_ex_mon_state <= (R_ctrl_ld_ex & W_valid) ? 1'b1 :
((D_op_eret & W_valid) | (R_ctrl_st_ex & W_valid)) ? 1'b0 :
W_up_ex_mon_state;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= D_ctrl_intr_inst ? W_status_reg : E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cdsr_reg <= 0;
else
W_cdsr_reg <= 0;
end
assign W_cpuid_reg = 0;
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rd_ctl_reg ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
assign W_mem_baddr = W_alu_result[31 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst | W_rf_ecc_unrecoverable_valid) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception|W_rf_ecc_unrecoverable_valid) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000001011111;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000001011111;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
nios_dut_nios2_gen2_0_cpu_nios2_oci the_nios_dut_nios2_gen2_0_cpu_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (debug_mem_slave_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (debug_mem_slave_byteenable),
.clk (debug_mem_slave_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms),
.debugaccess_nxt (debug_mem_slave_debugaccess),
.hbreak_enabled (hbreak_enabled),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (debug_mem_slave_read),
.readdata (debug_mem_slave_readdata),
.reset (debug_mem_slave_reset),
.reset_n (reset_n),
.reset_req (reset_req),
.resetrequest (debug_reset_request),
.waitrequest (debug_mem_slave_waitrequest),
.write_nxt (debug_mem_slave_write),
.writedata_nxt (debug_mem_slave_writedata)
);
//debug_mem_slave, which is an e_avalon_slave
assign debug_mem_slave_clk = clk;
assign debug_mem_slave_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv02|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv44|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_opx_rsv44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv02|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = 1'b0;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_rd_ctl_reg = D_op_rdctl;
assign R_ctrl_rd_ctl_reg_nxt = D_ctrl_rd_ctl_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rd_ctl_reg <= 0;
else if (R_en)
R_ctrl_rd_ctl_reg <= R_ctrl_rd_ctl_reg_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|D_op_jmpi|D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_opx_rsv44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_ror;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|D_op_srl|D_op_srai|D_op_sra|D_op_ror;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_sll|
D_op_roli|
D_op_rol|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_ror;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_set_src2_rem_imm = 1'b0;
assign R_ctrl_set_src2_rem_imm_nxt = D_ctrl_set_src2_rem_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_set_src2_rem_imm <= 0;
else if (R_en)
R_ctrl_set_src2_rem_imm <= R_ctrl_set_src2_rem_imm_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_slli|
D_op_srli|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_signed_imm12 = 1'b0;
assign R_ctrl_signed_imm12_nxt = D_ctrl_signed_imm12;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_signed_imm12 <= 0;
else if (R_en)
R_ctrl_signed_imm12 <= R_ctrl_signed_imm12_nxt;
end
assign D_ctrl_src_imm5_shift_rot = D_op_roli|D_op_slli|D_op_srli|D_op_srai;
assign R_ctrl_src_imm5_shift_rot_nxt = D_ctrl_src_imm5_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src_imm5_shift_rot <= 0;
else if (R_en)
R_ctrl_src_imm5_shift_rot <= R_ctrl_src_imm5_shift_rot_nxt;
end
assign D_ctrl_br_uncond = D_op_br;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|D_op_bge|D_op_blt|D_op_bne|D_op_beq|D_op_bgeu|D_op_bltu;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_bgeu;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldbio|D_op_ldhio|D_op_ldwio;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_ex = 1'b0;
assign R_ctrl_ld_ex_nxt = D_ctrl_ld_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_ex <= 0;
else if (R_en)
R_ctrl_ld_ex <= R_ctrl_ld_ex_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st_ex = 1'b0;
assign R_ctrl_st_ex_nxt = D_ctrl_st_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st_ex <= 0;
else if (R_en)
R_ctrl_st_ex <= R_ctrl_st_ex_nxt;
end
assign D_ctrl_st = D_op_stb|D_op_sth|D_op_stw|D_op_stbio|D_op_sthio|D_op_stwio;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_st_ex = 1'b0;
assign R_ctrl_ld_st_ex_nxt = D_ctrl_ld_st_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_st_ex <= 0;
else if (R_en)
R_ctrl_ld_st_ex <= R_ctrl_ld_st_ex_nxt;
end
assign D_ctrl_mem8 = D_op_ldb|D_op_ldbu|D_op_ldbio|D_op_ldbuio|D_op_stb|D_op_stbio;
assign R_ctrl_mem8_nxt = D_ctrl_mem8;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem8 <= 0;
else if (R_en)
R_ctrl_mem8 <= R_ctrl_mem8_nxt;
end
assign D_ctrl_mem16 = D_op_ldhu|D_op_ldh|D_op_ldhio|D_op_ldhuio|D_op_sth|D_op_sthio;
assign R_ctrl_mem16_nxt = D_ctrl_mem16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem16 <= 0;
else if (R_en)
R_ctrl_mem16 <= R_ctrl_mem16_nxt;
end
assign D_ctrl_mem32 = D_op_ldw|D_op_ldwio|D_op_stw|D_op_stwio;
assign R_ctrl_mem32_nxt = D_ctrl_mem32;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem32 <= 0;
else if (R_en)
R_ctrl_mem32 <= R_ctrl_mem32_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_jmpi;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_roli|
D_op_slli|
D_op_srli|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_intr_inst = 1'b0;
assign R_ctrl_intr_inst_nxt = D_ctrl_intr_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_intr_inst <= 0;
else if (R_en)
R_ctrl_intr_inst <= R_ctrl_intr_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_opx_rsv44|
D_op_crst|
D_op_ldl|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_ret|
D_op_jmp|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_bgeu|
D_op_beq|
D_op_bne|
D_op_br;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
assign D_ctrl_alu_force_and = 1'b0;
assign R_ctrl_alu_force_and_nxt = D_ctrl_alu_force_and;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_and <= 0;
else if (R_en)
R_ctrl_alu_force_and <= R_ctrl_alu_force_and_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_custom)? 56'h20637573746f6d :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_custom)? 56'h20637573746f6d :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {9{8'h2d}};
assign D_vinst = D_valid ? D_inst : {9{8'h2d}};
assign R_vinst = R_valid ? D_inst : {9{8'h2d}};
assign E_vinst = E_valid ? D_inst : {9{8'h2d}};
assign W_vinst = W_valid ? D_inst : {9{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD0_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSHOLD0_BLACKBOX_V
/**
* bushold0: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates internal node weak driver).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bushold0 (
X ,
RESET
);
inout X ;
input RESET;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD0_BLACKBOX_V
|
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