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// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: reading.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module reading (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/reading.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/reading.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/reading.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module env_io (/*AUTOARG*/
// Outputs
DI,
// Inputs
clk, iorq_n, rd_n, wr_n, addr, DO
);
input clk;
input iorq_n;
input rd_n;
input wr_n;
input [7:0] addr;
input [7:0] DO;
inout [7:0] DI;
reg [7:0] io_data;
reg [7:0] str_buf [0:255];
reg io_cs;
integer buf_ptr, i;
reg [7:0] timeout_ctl;
reg [15:0] cur_timeout;
reg [15:0] max_timeout;
reg [7:0] int_countdown;
reg [7:0] checksum;
reg [7:0] ior_value; // increment-on-read value
assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
initial
begin
io_cs = 0;
buf_ptr = 0;
cur_timeout = 0;
max_timeout = 10000;
timeout_ctl = 1;
int_countdown = 0;
end
always @*
begin
if (!iorq_n & !rd_n)
begin
io_cs = (addr[7:5] == 3'b100);
case (addr)
8'h82 : io_data = timeout_ctl;
8'h83 : io_data = max_timeout[7:0];
8'h84 : io_data = max_timeout[15:8];
8'h90 : io_data = int_countdown;
8'h91 : io_data = checksum;
8'h93 : io_data = ior_value;
8'h94 : io_data = {$random};
default : io_data = 8'hzz;
endcase // case(addr)
end // if (!iorq_n & !rd_n)
end // always @ *
wire wr_stb;
reg last_iowrite;
assign wr_stb = (!iorq_n & !wr_n);
always @(posedge clk)
begin
last_iowrite <= #1 wr_stb;
if (!wr_stb & last_iowrite)
case (addr)
8'h80 :
begin
case (DO)
1 : tb_top.test_pass;
2 : tb_top.test_fail;
3 : tb_top.dumpon;
4 : tb_top.dumpoff;
default :
begin
$display ("%t: ERROR : Unknown I/O command %x", $time, DO);
end
endcase // case(DO)
end // case: :...
8'h81 :
begin
str_buf[buf_ptr] = DO;
buf_ptr = buf_ptr + 1;
//$display ("%t: DEBUG : Detected write of character %x", $time, DO);
if (DO == 8'h0A)
begin
$write ("%t: PROGRAM : ", $time);
for (i=0; i<buf_ptr; i=i+1)
$write ("%s", str_buf[i]);
buf_ptr = 0;
end
end // case: 8'h81
8'h82 :
begin
timeout_ctl = DO;
end
8'h83 : max_timeout[7:0] = DO;
8'h84 : max_timeout[15:8] = DO;
8'h90 : int_countdown = DO;
8'h91 : checksum = DO;
8'h92 : checksum = checksum + DO;
8'h93 : ior_value = DO;
endcase // case(addr)
end // always @ (posedge clk)
always @(posedge clk)
begin
if (timeout_ctl[1])
cur_timeout = 0;
else if (timeout_ctl[0])
cur_timeout = cur_timeout + 1;
if (cur_timeout >= max_timeout)
begin
$display ("%t: ERROR : Reached timeout %d cycles", $time, max_timeout);
tb_top.test_fail;
end
end // always @ (posedge clk)
always @(posedge clk)
begin
if (int_countdown == 1)
begin
tb_top.int_n <= #1 1'b0;
int_countdown = 0;
end
else if (int_countdown > 1)
begin
int_countdown = int_countdown - 1;
tb_top.int_n <= #1 1'b1;
end
end
endmodule // env_io
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR4BB_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_BLACKBOX_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module soc_system_video_vga_controller_0 (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_1_V
`define SKY130_FD_SC_LS__XOR3_1_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_1_V
|
module riscv_core_ref (
input clk,
input rstn,
//Instruction memory interface, combinational
output [31:0] instr_mem_addr,
input [31:0] instr_mem_rdata,
//output branch_taken,
//output illegal_instruction,
//Data memory interface, read data expected combinational
output [31:0] data_mem_addr,
output data_mem_write,
output [31:0] data_mem_wdata,
input [31:0] data_mem_rdata
);
localparam BEQ = 6'h00;
localparam BNE = 6'h01;
localparam BLT = 6'h02;
localparam BGE = 6'h03;
localparam BLTU = 6'h04;
localparam BGEU = 6'h05;
localparam JALR = 6'h06;
localparam JAL = 6'h07;
localparam LUI = 6'h08;
localparam AUIPC = 6'h09;
localparam ADDI = 6'h0A;
localparam SLTI = 6'h0B;
localparam SLTIU = 6'h0C;
localparam XORI = 6'h0D;
localparam ORI = 6'h0E;
localparam ANDI = 6'h0F;
localparam SLLI = 6'h10;
localparam SRLI = 6'h11;
localparam SRAI = 6'h12;
localparam ADD = 6'h13;
localparam SUB = 6'h14;
localparam OR = 6'h15;
localparam XOR = 6'h16;
localparam AND = 6'h17;
localparam SLT = 6'h18;
localparam SLTU = 6'h19;
localparam SLL = 6'h1A;
localparam SRL = 6'h1B;
localparam SRA = 6'h1C;
localparam LB = 6'h1D;
localparam LH = 6'h1E;
localparam LW = 6'h1F;
localparam LBU = 6'h20;
localparam LHU = 6'h21;
localparam SB = 6'h22;
localparam SH = 6'h23;
localparam SW = 6'h24;
reg [31:0] rf [0:31];
reg [31:0] pc_ff;
reg [31:0] data_mem_wdata_l;
wire [31:0] instr_raw;
reg [5:0] instr_e;
reg illegal_instr;
wire [31:0] i_im;
wire [31:0] s_im;
wire [31:0] b_im;
wire [31:0] u_im;
wire [31:0] j_im;
wire sign;
wire [4:0] rsj_sel;
wire [4:0] rsk_sel;
wire [4:0] rsd_sel;
wire [31:0] rsj;
wire [31:0] rsk;
reg [31:0] pc_nxt;
reg [31:0] rf_wdata;
reg [31:0] d_addr;
reg [31:0] d_wdata;
reg [3:0] d_wmask;
reg d_write;
reg take_branch;
reg alu_op;
reg load_op;
assign rsd_sel = instr_raw[11:7];
assign rsj_sel = instr_raw[19:15];
assign rsk_sel = instr_raw[24:20];
assign sign = instr_raw[31];
assign i_im = {{20{sign}}, instr_raw[30:20]};
assign s_im = {{20{sign}}, instr_raw[30:25], instr_raw[11:7]};
assign b_im = {{19{sign}}, instr_raw[7], instr_raw[30:25], instr_raw[11:8], 1'b0};
assign u_im = {sign, instr_raw[30:12], 12'b0};
assign j_im = {{11{sign}}, instr_raw[19:12], instr_raw[20], instr_raw[30:21], 1'b0};
assign rsj = rf[rsj_sel];
assign rsk = rf[rsk_sel];
assign instr_mem_addr = pc_ff;
assign instr_raw = instr_mem_rdata;
always @ (*) begin
illegal_instr = 1'b0;
case (instr_raw)
32'b?????????????????000?????1100011: instr_e = BEQ;
32'b?????????????????001?????1100011: instr_e = BNE;
32'b?????????????????100?????1100011: instr_e = BLT;
32'b?????????????????101?????1100011: instr_e = BGE;
32'b?????????????????110?????1100011: instr_e = BLTU;
32'b?????????????????111?????1100011: instr_e = BGEU;
32'b?????????????????000?????1100111: instr_e = JALR;
32'b?????????????????????????1101111: instr_e = JAL;
32'b?????????????????????????0110111: instr_e = LUI;
32'b?????????????????????????0010111: instr_e = AUIPC;
32'b?????????????????000?????0010011: instr_e = ADDI;
32'b?????????????????010?????0010011: instr_e = SLTI;
32'b?????????????????011?????0010011: instr_e = SLTIU;
32'b?????????????????100?????0010011: instr_e = XORI;
32'b?????????????????110?????0010011: instr_e = ORI;
32'b?????????????????111?????0010011: instr_e = ANDI;
32'b000000???????????001?????0010011: instr_e = SLLI;
32'b000000???????????101?????0010011: instr_e = SRLI;
32'b010000???????????101?????0010011: instr_e = SRAI;
32'b0000000??????????000?????0110011: instr_e = ADD;
32'b0100000??????????000?????0110011: instr_e = SUB;
32'b0000000??????????110?????0110011: instr_e = OR;
32'b0000000??????????100?????0110011: instr_e = XOR;
32'b0000000??????????111?????0110011: instr_e = AND;
32'b0000000??????????010?????0110011: instr_e = SLT;
32'b0000000??????????011?????0110011: instr_e = SLTU;
32'b0000000??????????001?????0110011: instr_e = SLL;
32'b0000000??????????101?????0110011: instr_e = SRL;
32'b0100000??????????101?????0110011: instr_e = SRA;
32'b?????????????????000?????0000011: instr_e = LB;
32'b?????????????????001?????0000011: instr_e = LH;
32'b?????????????????010?????0000011: instr_e = LW;
32'b?????????????????100?????0000011: instr_e = LBU;
32'b?????????????????101?????0000011: instr_e = LHU;
32'b?????????????????000?????0100011: instr_e = SB;
32'b?????????????????001?????0100011: instr_e = SH;
32'b?????????????????010?????0100011: instr_e = SW;
default illegal_instr = 1'b1;
endcase
end
//Branch instruction
always @ (*) begin
case (instr_e)
BEQ: take_branch = (rsj == rsk) ? 1'b1 : 1'b0;
BNE: take_branch = (rsj != rsk) ? 1'b1 : 1'b0;
BLT: take_branch = ($signed(rsj) < $signed(rsk)) ? 1'b1 : 1'b0;
BGE: take_branch = ($signed(rsj) > $signed(rsk)) ? 1'b1 : 1'b0;
BLTU: take_branch = (rsj < rsk) ? 1'b1 : 1'b0;
BGEU: take_branch = (rsj > rsk) ? 1'b1 : 1'b0;
JALR,
JAL: take_branch = 1'b1;
default take_branch = 1'b0;
endcase
end
always @ (*) begin
if (take_branch) begin
case (instr_e)
BEQ,
BNE,
BLT,
BGE,
BLTU,
BGEU: pc_nxt = pc_ff + b_im;
JALR,
JAL: pc_nxt = pc_ff + j_im;
default pc_nxt = pc_ff + 4;
endcase
end
else begin
pc_nxt = pc_ff + 4;
end
end
//ALU instruction
always @ (*) begin
alu_op = 1'b1;
case (instr_e)
JALR,
JAL: rf_wdata = pc_ff + 4;
LUI: rf_wdata = {u_im[31:12], 12'b0};
AUIPC: rf_wdata = pc_ff + u_im;
ADDI: rf_wdata = rsj + i_im;
SLTI: rf_wdata = ($signed(rsj) < $signed(i_im)) ? 1 : 0;
SLTIU: rf_wdata = (rsj < i_im) ? 1 : 0;
XORI: rf_wdata = rsj ^ i_im;
ORI: rf_wdata = rsj | i_im;
ANDI: rf_wdata = rsj & i_im;
SLLI: rf_wdata = rsj << (i_im & 'h1F);
SRLI: rf_wdata = rsj >> (i_im & 'h1F);
SRAI: rf_wdata = rsj >>> (i_im & 'h1F);
ADD: rf_wdata = rsj + rsk;
SUB: rf_wdata = rsj - rsk;
OR: rf_wdata = rsj | rsk;
XOR: rf_wdata = rsj ^ rsk;
AND: rf_wdata = rsj & rsk;
SLT: rf_wdata = ($signed(rsj) < $signed(rsk)) ? 1 : 0;
SLTU: rf_wdata = (rsj < rsk) ? 1 : 0;
SLL: rf_wdata = rsj << (rsk & 'h1F);
SRL: rf_wdata = rsj >> (rsk & 'h1F);
SRA: rf_wdata = rsj >>> (rsk & 'h1F);
default alu_op = 1'b0;
endcase
end
//MEM operation
assign data_mem_addr = {d_addr[31:2], 2'b00};
assign data_mem_wdata = data_mem_wdata_l;
assign data_mem_write = d_write;
always @ (*) begin
d_write = 1;
d_wdata = 0;
d_wmask = 0;
d_addr = i_im + rsj;
case (instr_e)
SB: begin
d_wdata = {4{rsk[7:0]}};
d_wmask = 'h1 << d_addr[1:0];
end
SH: begin
d_wdata = {2{rsk[15:0]}};
d_wmask = 'h3 << d_addr[1:0];
end
SW: begin
d_wdata = rsk;
d_wmask = 'hF << d_addr[1:0];
end
default d_write = 0;
endcase
end
always @ (*) begin
if (d_write) begin
data_mem_wdata_l[7:0] = (d_wmask[0]) ? d_wdata[7:0] : data_mem_rdata[7:0];
data_mem_wdata_l[15:8] = (d_wmask[1]) ? d_wdata[15:8] : data_mem_rdata[15:8];
data_mem_wdata_l[23:16] = (d_wmask[2]) ? d_wdata[23:16] : data_mem_rdata[23:16];
data_mem_wdata_l[31:24] = (d_wmask[3]) ? d_wdata[31:24] : data_mem_rdata[31:24];
end
end
always @ (*) begin
load_op = 1'b1;
case (instr_e)
LBU : rf_wdata <= 32'h000000FF & data_mem_rdata;
LHU : rf_wdata <= 32'h0000FFFF & data_mem_rdata;
LW : rf_wdata <= data_mem_rdata;
LB : rf_wdata <= {{24{data_mem_rdata[7]}}, data_mem_rdata[7:0]};
LH : rf_wdata <= {{16{data_mem_rdata[15]}}, data_mem_rdata[15:8]};
default load_op = 1'b0;
endcase
end
//Assert (!(load_op && alu_op)) else rf_wdata is driven X
integer i;
always @ (posedge clk, negedge rstn) begin
if (~rstn) begin
for (i = 0 ; i < 32; i = i + 1) begin
rf[i] = 0;
end
pc_ff = 0;
end
else begin
pc_ff <= pc_nxt;
if (alu_op || load_op) begin
rf[rsd_sel] <= rf_wdata;
end
end
end
endmodule
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gtwiz_buffbypass_rx #(
parameter integer P_BUFFER_BYPASS_MODE = 0,
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1,
parameter integer P_MASTER_CHANNEL_POINTER = 0
)(
// User interface ports
input wire gtwiz_buffbypass_rx_clk_in,
input wire gtwiz_buffbypass_rx_reset_in,
input wire gtwiz_buffbypass_rx_start_user_in,
input wire gtwiz_buffbypass_rx_resetdone_in,
output reg gtwiz_buffbypass_rx_done_out = 1'b0,
output reg gtwiz_buffbypass_rx_error_out = 1'b0,
// Transceiver interface ports
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphaligndone_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlysresetdone_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncout_in,
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncdone_in,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphdlyreset_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphalign_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphalignen_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphdlypd_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphovrden_out,
output reg [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlysreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}},
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlybypass_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlyen_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlyovrden_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncmode_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncallin_out,
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncin_out
);
// -------------------------------------------------------------------------------------------------------------------
// Receiver buffer bypass conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
localparam [1:0] ST_BUFFBYPASS_RX_IDLE = 2'd0;
localparam [1:0] ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET = 2'd1;
localparam [1:0] ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE = 2'd2;
localparam [1:0] ST_BUFFBYPASS_RX_DONE = 2'd3;
generate if (1) begin: gen_gtwiz_buffbypass_rx_main
// Use auto mode buffer bypass
if (P_BUFFER_BYPASS_MODE == 0) begin : gen_auto_mode
// For single-lane auto mode buffer bypass, perform specified input port tie-offs
if (P_TOTAL_NUMBER_OF_CHANNELS == 1) begin : gen_assign_one_chan
assign rxphdlyreset_out = 1'b0;
assign rxphalign_out = 1'b0;
assign rxphalignen_out = 1'b0;
assign rxphdlypd_out = 1'b0;
assign rxphovrden_out = 1'b0;
assign rxdlybypass_out = 1'b0;
assign rxdlyen_out = 1'b0;
assign rxdlyovrden_out = 1'b0;
assign rxsyncmode_out = 1'b1;
assign rxsyncallin_out = rxphaligndone_in;
assign rxsyncin_out = 1'b0;
end
// For multi-lane auto mode buffer bypass, perform specified master and slave lane input port tie-offs
else begin : gen_assign_multi_chan
assign rxphdlyreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign rxphalign_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign rxphalignen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign rxphdlypd_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign rxphovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign rxdlybypass_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign rxdlyen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
assign rxdlyovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
genvar gi;
for (gi = 0; gi < P_TOTAL_NUMBER_OF_CHANNELS; gi = gi + 1) begin : gen_assign_rxsyncmode
if (gi == P_MASTER_CHANNEL_POINTER)
assign rxsyncmode_out[gi] = 1'b1;
else
assign rxsyncmode_out[gi] = 1'b0;
end
assign rxsyncallin_out = {P_TOTAL_NUMBER_OF_CHANNELS{&rxphaligndone_in}};
assign rxsyncin_out = {P_TOTAL_NUMBER_OF_CHANNELS{rxsyncout_in[P_MASTER_CHANNEL_POINTER]}};
end
// Detect the rising edge of the receiver reset done re-synchronized input. Assign an internal buffer bypass
// start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request.
wire gtwiz_buffbypass_rx_resetdone_sync_int;
gtwizard_ultrascale_v1_7_1_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
.clk_in (gtwiz_buffbypass_rx_clk_in),
.rst_in (gtwiz_buffbypass_rx_resetdone_in),
.rst_out (gtwiz_buffbypass_rx_resetdone_sync_int)
);
reg gtwiz_buffbypass_rx_resetdone_reg = 1'b0;
wire gtwiz_buffbypass_rx_start_int;
always @(posedge gtwiz_buffbypass_rx_clk_in) begin
if (gtwiz_buffbypass_rx_reset_in)
gtwiz_buffbypass_rx_resetdone_reg <= 1'b0;
else
gtwiz_buffbypass_rx_resetdone_reg <= gtwiz_buffbypass_rx_resetdone_sync_int;
end
assign gtwiz_buffbypass_rx_start_int = (gtwiz_buffbypass_rx_resetdone_sync_int &&
~gtwiz_buffbypass_rx_resetdone_reg) || gtwiz_buffbypass_rx_start_user_in;
// Synchronize the master channel's buffer bypass completion output (RXSYNCDONE) into the local clock domain
// and detect its rising edge for purposes of safe state machine transitions
reg gtwiz_buffbypass_rx_master_syncdone_sync_reg = 1'b0;
wire gtwiz_buffbypass_rx_master_syncdone_sync_int;
wire gtwiz_buffbypass_rx_master_syncdone_sync_re;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_mastersyncdone_inst (
.clk_in (gtwiz_buffbypass_rx_clk_in),
.i_in (rxsyncdone_in[P_MASTER_CHANNEL_POINTER]),
.o_out (gtwiz_buffbypass_rx_master_syncdone_sync_int)
);
always @(posedge gtwiz_buffbypass_rx_clk_in)
gtwiz_buffbypass_rx_master_syncdone_sync_reg <= gtwiz_buffbypass_rx_master_syncdone_sync_int;
assign gtwiz_buffbypass_rx_master_syncdone_sync_re = gtwiz_buffbypass_rx_master_syncdone_sync_int &&
~gtwiz_buffbypass_rx_master_syncdone_sync_reg;
// Synchronize the master channel's phase alignment completion output (RXPHALIGNDONE) into the local clock domain
wire gtwiz_buffbypass_rx_master_phaligndone_sync_int;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_masterphaligndone_inst (
.clk_in (gtwiz_buffbypass_rx_clk_in),
.i_in (rxphaligndone_in[P_MASTER_CHANNEL_POINTER]),
.o_out (gtwiz_buffbypass_rx_master_phaligndone_sync_int)
);
// Implement a simple state machine to perform the receiver auto mode buffer bypass procedure
reg [1:0] sm_buffbypass_rx = ST_BUFFBYPASS_RX_IDLE;
always @(posedge gtwiz_buffbypass_rx_clk_in) begin
if (gtwiz_buffbypass_rx_reset_in) begin
gtwiz_buffbypass_rx_done_out <= 1'b0;
gtwiz_buffbypass_rx_error_out <= 1'b0;
rxdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_IDLE;
end
else begin
case (sm_buffbypass_rx)
// Upon assertion of the internal buffer bypass start signal, assert RXDLYSRESET output(s)
default: begin
if (gtwiz_buffbypass_rx_start_int) begin
gtwiz_buffbypass_rx_done_out <= 1'b0;
gtwiz_buffbypass_rx_error_out <= 1'b0;
rxdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b1}};
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET;
end
end
// De-assert the RXDLYSRESET output(s)
ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET: begin
rxdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE;
end
// Upon assertion of the synchronized RXSYNCDONE indicator, transition to the final state
ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE: begin
if (gtwiz_buffbypass_rx_master_syncdone_sync_re)
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_DONE;
end
// Assert the buffer bypass procedure done user indicator, and set the procedure error flag if the
// synchronized RXPHALIGNDONE indicator is not high
ST_BUFFBYPASS_RX_DONE: begin
gtwiz_buffbypass_rx_done_out <= 1'b1;
gtwiz_buffbypass_rx_error_out <= ~gtwiz_buffbypass_rx_master_phaligndone_sync_int;
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_IDLE;
end
endcase
end
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_PP_SYMBOL_V
|
module arbiter(
input wire clk,
input wire reset,
// Slave 0
input wire [17:0] s0_address,
input wire s0_write,
input wire s0_read,
input wire [35:0] s0_writedata,
output reg [35:0] s0_readdata,
output reg s0_waitrequest,
// Slave 1
input wire [17:0] s1_address,
input wire s1_write,
input wire s1_read,
input wire [35:0] s1_writedata,
output reg [35:0] s1_readdata,
output reg s1_waitrequest,
// Master
output reg [17:0] m_address,
output reg m_write,
output reg m_read,
output reg [35:0] m_writedata,
input wire [35:0] m_readdata,
input wire m_waitrequest
);
wire cyc0 = s0_read | s0_write;
wire cyc1 = s1_read | s1_write;
reg sel0, sel1;
wire connected = sel0 | sel1;
always @(posedge clk or negedge reset) begin
if(~reset) begin
sel0 <= 0;
sel1 <= 0;
end else begin
if(sel0 & ~cyc0 | sel1 & ~cyc1) begin
// disconnect if cycle is done
sel0 <= 0;
sel1 <= 0;
end else if(~connected) begin
// connect to master 0 or 1
if(cyc0)
sel0 <= 1;
else if(cyc1)
sel1 <= 1;
end
end
end
// Do the connection
always @(*) begin
if(sel0) begin
m_address <= s0_address;
m_write <= s0_write;
m_read <= s0_read;
m_writedata <= s0_writedata;
s0_readdata <= m_readdata;
s0_waitrequest <= m_waitrequest;
s1_readdata <= 0;
s1_waitrequest <= 1;
end else if(sel1) begin
m_address <= s1_address;
m_write <= s1_write;
m_read <= s1_read;
m_writedata <= s1_writedata;
s1_readdata <= m_readdata;
s1_waitrequest <= m_waitrequest;
s0_readdata <= 0;
s0_waitrequest <= 1;
end else begin
m_address <= 0;
m_write <= 0;
m_read <= 0;
m_writedata <= 0;
s0_readdata <= 0;
s0_waitrequest <= 1;
s1_readdata <= 0;
s1_waitrequest <= 1;
end
end
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A clock divider circuit.
// Division is based on the parameters, where
// Division is upper - lower + 1
// Duty cycle is :
// let half = 1 << (width-1)
// (upper - half) / upper - lower + 1
// E.g., (2,1,3) is a divide by 3 duty cycle 2/3
// (2,0,3) is a divide by 4 duty cycle 2/4
// (1,0,1) is a divide by 2, duty cycle 1/2
// (3,1,5) is a divide by 5 duty cycle 2/5
// (3,2,6) is a divide by 5 duty cycle 3/5
// The offset allow edges for seperate modules to be determined
// relative to each other. a clock divider with offset 1 occurs one
// (fast) clock later than a clock with offset 0.
module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT);
parameter width = 2 ; // must be sufficient to hold upper
parameter lower = 1 ; //
parameter upper = 3 ;
parameter offset = 0; // offset for relative edges.
// (0 <= offset <= (upper - lower)
input CLK_IN; // input clock
input RST_N;
output PREEDGE; // output signal announcing an upcoming edge
output CLK_OUT; // output clock
reg [ width -1 : 0 ] cntr ;
reg PREEDGE ;
// Wire constants for the parameters
wire [width-1:0] upper_w ;
wire [width-1:0] lower_w ;
assign CLK_OUT = cntr[width-1] ;
assign upper_w = upper ;
assign lower_w = lower ;
// The clock is about to tick when counter is about to set its msb
// Note some simulators do not allow 0 width expressions
wire [width-1:0] nexttick = ~ ( 'b01 << (width-1) ) ;
// Combinational block to generate next edge signal
always@( cntr or nexttick )
begin
#0
// The nonblocking assignment use to delay the update of the edge ready signal
// Since this read by other always blocks trigger by the output CLK of this module
PREEDGE <= `BSV_ASSIGNMENT_DELAY (cntr == nexttick) ;
end
always@( posedge CLK_IN or negedge RST_N )
begin
// The use of blocking assignment within this block insures
// that the clock generated from cntr[MSB] occurs before any
// LHS of nonblocking assigments also from CLK_IN occur.
// Basically, this insures that CLK_OUT and CLK_IN occur within
// the same phase of the execution cycle, before any state
// updates occur. see
// http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf
if ( RST_N == 0 )
cntr = upper - offset ;
else
begin
if ( cntr < upper_w )
cntr = cntr + 1 ;
else
cntr = lower_w ;
end // else: !if( RST_N == 0 )
end // always@ ( posedge CLK_IN or negedge RST_N )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
cntr = (upper - offset) ;
PREEDGE = 0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // ClockDiv
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Input Deserializer for Virtex7
// /___/ /\ Filename : ISERDESE2.v
// \ \ / \ Timestamp : Tue Jan 19 16:29:39 PST 2010
// \___\/\___\
//
// Revision:
// 01/19/10 - Initial version.
// 03/24/11 - Sync-up
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ISERDESE2 (
O,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
SHIFTOUT1,
SHIFTOUT2,
BITSLIP,
CE1,
CE2,
CLK,
CLKB,
CLKDIV,
CLKDIVP,
D,
DDLY,
DYNCLKDIVSEL,
DYNCLKSEL,
OCLK,
OCLKB,
OFB,
RST,
SHIFTIN1,
SHIFTIN2
);
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter DYN_CLKDIV_INV_EN = "FALSE";
parameter DYN_CLK_INV_EN = "FALSE";
parameter [0:0] INIT_Q1 = 1'b0;
parameter [0:0] INIT_Q2 = 1'b0;
parameter [0:0] INIT_Q3 = 1'b0;
parameter [0:0] INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter IOBDELAY = "NONE";
parameter [0:0] IS_CLKB_INVERTED = 1'b0;
parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0;
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_OCLKB_INVERTED = 1'b0;
parameter [0:0] IS_OCLK_INVERTED = 1'b0;
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter integer NUM_CE = 2;
parameter OFB_USED = "FALSE";
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_Q1 = 1'b0;
parameter [0:0] SRVAL_Q2 = 1'b0;
parameter [0:0] SRVAL_Q3 = 1'b0;
parameter [0:0] SRVAL_Q4 = 1'b0;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output O;
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output Q7;
output Q8;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKB;
input CLKDIV;
input CLKDIVP;
input D;
input DDLY;
input DYNCLKDIVSEL;
input DYNCLKSEL;
input OCLK;
input OCLKB;
input OFB;
input RST;
input SHIFTIN1;
input SHIFTIN2;
tri0 GSR = glbl.GSR;
reg INTERFACE_TYPE_BINARY;
reg IOBDELAY_BINARY;
reg [0:0] DATA_RATE_BINARY;
reg [0:0] DYN_CLKDIV_INV_EN_BINARY;
reg [0:0] DYN_CLK_INV_EN_BINARY;
reg [0:0] INIT_Q1_BINARY;
reg [0:0] INIT_Q2_BINARY;
reg [0:0] INIT_Q3_BINARY;
reg [0:0] INIT_Q4_BINARY;
reg [0:0] NUM_CE_BINARY;
reg [0:0] SERDES_MODE_BINARY;
reg [1:0] OFB_USED_BINARY;
reg [3:0] DATA_WIDTH_BINARY;
reg data_in = 0;
reg o_out_pre_fb = 0, o_delay_pre_fb = 0;
reg o_out = 0;
reg notifier;
wire O_OUT;
wire Q1_OUT;
wire Q2_OUT;
wire Q3_OUT;
wire Q4_OUT;
wire Q5_OUT;
wire Q6_OUT;
wire Q7_OUT;
wire Q8_OUT;
wire SHIFTOUT1_OUT;
wire SHIFTOUT2_OUT;
wire BITSLIP_IN;
wire CE1_IN;
wire CE2_IN;
wire CLKB_IN;
wire CLKDIVP_IN;
wire CLKDIV_IN;
wire CLK_IN;
wire DDLY_IN;
wire DYNCLKDIVSEL_IN;
wire DYNCLKSEL_IN;
wire D_IN;
wire OCLKB_IN;
wire OCLK_IN;
wire OFB_IN;
wire RST_IN;
wire SHIFTIN1_IN;
wire SHIFTIN2_IN;
wire BITSLIP_INDELAY;
wire CE1_INDELAY;
wire CE2_INDELAY;
wire CLKB_INDELAY;
wire CLKDIVP_INDELAY;
wire CLKDIV_INDELAY;
wire CLK_INDELAY;
wire DDLY_INDELAY;
wire DYNCLKDIVSEL_INDELAY;
wire DYNCLKSEL_INDELAY;
wire D_INDELAY;
wire OCLKB_INDELAY;
wire OCLK_INDELAY;
wire OFB_INDELAY;
wire RST_INDELAY;
wire SHIFTIN1_INDELAY;
wire SHIFTIN2_INDELAY;
//---------------------------------------
buf B_O (O, O_OUT);
buf B_Q1 (Q1, Q1_OUT);
buf B_Q2 (Q2, Q2_OUT);
buf B_Q3 (Q3, Q3_OUT);
buf B_Q4 (Q4, Q4_OUT);
buf B_Q5 (Q5, Q5_OUT);
buf B_Q6 (Q6, Q6_OUT);
buf B_Q7 (Q7, Q7_OUT);
buf B_Q8 (Q8, Q8_OUT);
buf B_SHIFTOUT1 (SHIFTOUT1, SHIFTOUT1_OUT);
buf B_SHIFTOUT2 (SHIFTOUT2, SHIFTOUT2_OUT);
buf B_BITSLIP (BITSLIP_IN, BITSLIP);
buf B_CE1 (CE1_IN, CE1);
buf B_CE2 (CE2_IN, CE2);
buf B_CLK (CLK_IN, CLK);
buf B_CLKB (CLKB_IN, CLKB);
buf B_CLKDIV (CLKDIV_IN, CLKDIV);
buf B_CLKDIVP (CLKDIVP_IN, CLKDIVP);
buf B_D (D_IN, D);
buf B_DDLY (DDLY_IN, DDLY);
buf B_DYNCLKDIVSEL (DYNCLKDIVSEL_IN, DYNCLKDIVSEL);
buf B_DYNCLKSEL (DYNCLKSEL_IN, DYNCLKSEL);
buf B_OCLK (OCLK_IN, OCLK);
buf B_OCLKB (OCLKB_IN, OCLKB);
buf B_OFB (OFB_IN, OFB);
buf B_RST (RST_IN, RST);
buf B_SHIFTIN1 (SHIFTIN1_IN, SHIFTIN1);
buf B_SHIFTIN2 (SHIFTIN2_IN, SHIFTIN2);
wire delay_O;
wire delay_Q1;
wire delay_Q2;
wire delay_Q3;
wire delay_Q4;
wire delay_Q5;
wire delay_Q6;
wire delay_Q7;
wire delay_Q8;
wire delay_SHIFTOUT1;
wire delay_SHIFTOUT2;
wire delay_BITSLIP,BITSLIP_in;
wire delay_CE1,CE1_in;
wire delay_CE2,CE2_in;
wire delay_CLK,CLK_inv,CLK_in;
wire delay_CLKB,CLKB_inv,CLKB_in;
wire delay_CLKDIV,CLKDIV_inv,CLKDIV_in;
wire delay_CLKDIVP,CLKDIVP_inv,CLKDIVP_in;
wire delay_D,D_inv,D_in;
wire delay_DDLY,DDLY_in;
wire delay_DYNCLKDIVSEL,DYNCLKDIVSEL_in;
wire delay_DYNCLKSEL,DYNCLKSEL_in;
wire delay_OCLK,OCLK_inv,OCLK_in;
wire delay_OCLKB,OCLKB_inv,OCLKB_in;
wire delay_OFB,OFB_in;
wire delay_RST,RST_in;
wire delay_SHIFTIN1,SHIFTIN1_in;
wire delay_SHIFTIN2,SHIFTIN2_in;
assign #(out_delay) O_OUT = o_out;
assign #(out_delay) Q1_OUT = delay_Q1;
assign #(out_delay) Q2_OUT = delay_Q2;
assign #(out_delay) Q3_OUT = delay_Q3;
assign #(out_delay) Q4_OUT = delay_Q4;
assign #(out_delay) Q5_OUT = delay_Q5;
assign #(out_delay) Q6_OUT = delay_Q6;
assign #(out_delay) Q7_OUT = delay_Q7;
assign #(out_delay) Q8_OUT = delay_Q8;
assign #(out_delay) SHIFTOUT1_OUT = delay_SHIFTOUT1;
assign #(out_delay) SHIFTOUT2_OUT = delay_SHIFTOUT2;
`ifndef XIL_TIMING // unisim
assign #(in_delay) delay_BITSLIP = BITSLIP;
assign #(in_delay) delay_CE1 = CE1;
assign #(in_delay) delay_CE2 = CE2;
assign #(INCLK_DELAY) delay_CLK = CLK;
assign #(INCLK_DELAY) delay_CLKB = CLKB;
assign #(INCLK_DELAY) delay_CLKDIV = CLKDIV;
assign #(INCLK_DELAY) delay_CLKDIVP = CLKDIVP;
assign #(in_delay) delay_D = D;
assign #(in_delay) delay_DDLY = DDLY;
assign #(in_delay) delay_DYNCLKDIVSEL = DYNCLKDIVSEL;
assign #(in_delay) delay_DYNCLKSEL = DYNCLKSEL;
assign #(INCLK_DELAY) delay_OCLK = OCLK;
assign #(INCLK_DELAY) delay_OCLKB = OCLKB;
assign #(in_delay) delay_OFB = OFB;
assign #(in_delay) delay_RST = RST;
assign #(in_delay) delay_SHIFTIN1 = SHIFTIN1;
assign #(in_delay) delay_SHIFTIN2 = SHIFTIN2;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_DYNCLKDIVSEL = DYNCLKDIVSEL;
assign delay_DYNCLKSEL = DYNCLKSEL;
assign delay_OCLK = OCLK;
assign delay_OCLKB = OCLKB;
assign delay_SHIFTIN1 = SHIFTIN1;
assign delay_SHIFTIN2 = SHIFTIN2;
`endif
//`ifdef XIL_TIMING //Simprim
assign BITSLIP_in = delay_BITSLIP;
assign CE1_in = delay_CE1;
assign CE2_in = delay_CE2;
assign DDLY_in = delay_DDLY;
assign DYNCLKDIVSEL_in = delay_DYNCLKDIVSEL;
assign DYNCLKSEL_in = delay_DYNCLKSEL;
assign OFB_in = delay_OFB;
assign RST_in = delay_RST;
assign SHIFTIN1_in = delay_SHIFTIN1;
assign SHIFTIN2_in = delay_SHIFTIN2;
//`endif
assign CLK_in = IS_CLK_INVERTED ^ delay_CLK;
assign CLKB_in = IS_CLKB_INVERTED ^ delay_CLKB;
assign CLKDIV_in = IS_CLKDIV_INVERTED ^ delay_CLKDIV;
assign CLKDIVP_in = IS_CLKDIVP_INVERTED ^ delay_CLKDIVP;
assign D_in = IS_D_INVERTED ^ delay_D;
assign OCLK_in = IS_OCLK_INVERTED ^ delay_OCLK;
assign OCLKB_in = IS_OCLKB_INVERTED ^ delay_OCLKB;
assign #(INCLK_DELAY) CLKB_INDELAY = CLKB_IN;
assign #(INCLK_DELAY) CLKDIVP_INDELAY = CLKDIVP_IN;
assign #(INCLK_DELAY) CLKDIV_INDELAY = CLKDIV_IN;
assign #(INCLK_DELAY) CLK_INDELAY = CLK_IN;
assign #(INCLK_DELAY) OCLKB_INDELAY = OCLKB_IN;
assign #(INCLK_DELAY) OCLK_INDELAY = OCLK_IN;
assign #(in_delay) BITSLIP_INDELAY = BITSLIP_IN;
assign #(in_delay) CE1_INDELAY = CE1_IN;
assign #(in_delay) CE2_INDELAY = CE2_IN;
assign #(in_delay) DDLY_INDELAY = DDLY_IN;
assign #(in_delay) DYNCLKDIVSEL_INDELAY = DYNCLKDIVSEL_IN;
assign #(in_delay) DYNCLKSEL_INDELAY = DYNCLKSEL_IN;
assign #(in_delay) D_INDELAY = D_IN;
assign #(in_delay) OFB_INDELAY = OFB_IN;
assign #(in_delay) RST_INDELAY = RST_IN;
assign #(in_delay) SHIFTIN1_INDELAY = SHIFTIN1_IN;
assign #(in_delay) SHIFTIN2_INDELAY = SHIFTIN2_IN;
assign delay_DYNCLKDIVSEL = DYNCLKDIVSEL_INDELAY;
assign delay_DYNCLKSEL = DYNCLKSEL_INDELAY;
// assign delay_OCLK = OCLK_INDELAY;
// assign delay_OCLKB = OCLKB_INDELAY;
// assign delay_RST = RST_INDELAY;
// assign delay_SHIFTIN1 = SHIFTIN1_INDELAY;
// assign delay_SHIFTIN2 = SHIFTIN2_INDELAY;
//----------------------------------------------------------
//------------------------- TASKS --------------------------
//----------------------------------------------------------
task INTERFACE_TYPE_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n");
$display("NETWORKING DDR 4, 6, 8, 10, 14\n");
$display("MEMORY DDR 4\n");
end
endtask // INTERFACE_TYPE_msg
task OVERSAMPLE_DDR_SDR_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("OVERSAMPLE SDR 4\n");
$display("OVERSAMPLE DDR 4\n");
end
endtask // OVERSAMPLE_DDR_SDR_msg
//----------------------------------------------------------
//------------------ Parameter Checks ----------------------
//----------------------------------------------------------
initial begin
//-------------------------------------------------
//----- DATA_RATE check
//-------------------------------------------------
case (DATA_RATE)
"SDR", "DDR" :;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE);
#1 $finish;
end
endcase // case(DATA_RATE)
//-------------------------------------------------
//----- DATA_WIDTH check
//-------------------------------------------------
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10, 14 :;
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDESE2 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, 10 or 14", DATA_WIDTH);
#1 $finish;
end
endcase // case(DATA_WIDTH)
//-------------------------------------------------
//----- DYN_CLKDIV_INV_EN check
//-------------------------------------------------
case (DYN_CLKDIV_INV_EN)
"TRUE", "FALSE" :;
default : begin
$display("Attribute Syntax Error : The attribute DYN_CLKDIV_INV_EN on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLKDIV_INV_EN);
#1 $finish;
end
endcase // case(DYN_CLKDIV_INV_EN)
//-------------------------------------------------
//----- DYN_CLK_INV_EN check
//-------------------------------------------------
case (DYN_CLK_INV_EN)
"TRUE", "FALSE" :;
default : begin
$display("Attribute Syntax Error : The attribute DYN_CLK_INV_EN on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLK_INV_EN);
#1 $finish;
end
endcase // case(DYN_CLK_INV_EN)
//-------------------------------------------------
//----- IOBDELAY check
//-------------------------------------------------
case (IOBDELAY)
"NONE", "IBUF", "IFD", "BOTH" :;
default : begin
$display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE2 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY);
#1 $finish;
end
endcase // case(IOBDELAY)
//-------------------------------------------------
//----- OFB_USED check
//-------------------------------------------------
case (OFB_USED)
"TRUE", "FALSE" :;
default : begin
$display("Attribute Syntax Error : The attribute OFB_USED on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", OFB_USED);
#1 $finish;
end
endcase // case(OFB_USED)
//-------------------------------------------------
//----- NUM_CE check
//-------------------------------------------------
case (NUM_CE)
1, 2 :;
default : begin
$display("Attribute Syntax Error : The attribute NUM_CE on ISERDESE2 instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE);
#1 $finish;
end
endcase // case(NUM_CE)
//-------------------------------------------------
//----- INTERFACE_TYPE check
//-------------------------------------------------
case (INTERFACE_TYPE)
"MEMORY" : begin
case(DATA_RATE)
"DDR" :
case(DATA_WIDTH)
4 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
default : INTERFACE_TYPE_msg;
endcase // DATA_RATE
end
"NETWORKING" : begin
case(DATA_RATE)
"SDR" :
case(DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
"DDR" :
case(DATA_WIDTH)
4, 6, 8, 10, 14 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
end
"MEMORY_DDR3" :;
"MEMORY_QDR" :;
"OVERSAMPLE" : begin
case(DATA_RATE)
"SDR" :
case(DATA_WIDTH)
4 : ;
default : OVERSAMPLE_DDR_SDR_msg;
endcase // DATA_WIDTH
"DDR" :
case(DATA_WIDTH)
4 : ;
default : OVERSAMPLE_DDR_SDR_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
end
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are MEMORY, NETWORKING, MEMORY_QDR, MEMORY_DDR3 or OVERSAMPLE", INTERFACE_TYPE);
#1 $finish;
end
endcase // INTERFACE_TYPE
//-------------------------------------------------
//----- SERDES_MODE check
//-------------------------------------------------
case (SERDES_MODE)
"MASTER", "SLAVE" :;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
#1 $finish;
end
endcase // case(SERDES_MODE)
end // initial begin
// CR 574021
//-------------------------------------------------
// Input to ISERDES
//-------------------------------------------------
always @(D_in or DDLY_in) begin
case (IOBDELAY)
"NONE" : begin
o_out_pre_fb <= D_in;
o_delay_pre_fb <= D_in;
end
"IBUF" : begin
o_out_pre_fb <= DDLY_in;
o_delay_pre_fb <= D_in;
end
"IFD" : begin
o_out_pre_fb <= D_in;
o_delay_pre_fb <= DDLY_in;
end
"BOTH" : begin
o_out_pre_fb <= DDLY_in;
o_delay_pre_fb <= DDLY_in;
end
default : begin
$display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE2 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY);
$finish;
end
endcase // case(IOBDELAY)
end // always @ (D_in or DDLY_in)
generate
case (OFB_USED)
"TRUE" : always @(OFB_in)
begin
o_out <= OFB_in;
data_in <= OFB_in;
end
"FALSE" : begin
always @(o_out_pre_fb) o_out <= o_out_pre_fb;
always @(o_delay_pre_fb) data_in <= o_delay_pre_fb;
end
endcase
endgenerate
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
B_ISERDESE2 #(
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
.DYN_CLKDIV_INV_EN (DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN (DYN_CLK_INV_EN),
.INIT_Q1 (INIT_Q1),
.INIT_Q2 (INIT_Q2),
.INIT_Q3 (INIT_Q3),
.INIT_Q4 (INIT_Q4),
.INTERFACE_TYPE (INTERFACE_TYPE),
.IOBDELAY (IOBDELAY),
.NUM_CE (NUM_CE),
.OFB_USED (OFB_USED),
.SERDES_MODE (SERDES_MODE),
.SRVAL_Q1 (SRVAL_Q1),
.SRVAL_Q2 (SRVAL_Q2),
.SRVAL_Q3 (SRVAL_Q3),
.SRVAL_Q4 (SRVAL_Q4))
B_ISERDESE2_INST (
.O (delay_O),
.Q1 (delay_Q1),
.Q2 (delay_Q2),
.Q3 (delay_Q3),
.Q4 (delay_Q4),
.Q5 (delay_Q5),
.Q6 (delay_Q6),
.Q7 (delay_Q7),
.Q8 (delay_Q8),
.SHIFTOUT1 (delay_SHIFTOUT1),
.SHIFTOUT2 (delay_SHIFTOUT2),
.BITSLIP (BITSLIP_in),
.CE1 (CE1_in),
.CE2 (CE2_in),
.CLK (CLK_in),
.CLKB (CLKB_in),
.CLKDIV (CLKDIV_in),
.CLKDIVP (CLKDIVP_in),
.D (data_in),
.DDLY (DDLY_in),
.DYNCLKDIVSEL (DYNCLKDIVSEL_in),
.DYNCLKSEL (DYNCLKSEL_in),
.OCLK (OCLK_in),
.OCLKB (OCLKB_in),
.OFB (OFB_in),
.RST (RST_in),
.SHIFTIN1 (SHIFTIN1_in),
.SHIFTIN2 (SHIFTIN2_in),
.GSR(GSR)
);
`ifdef XIL_TIMING
wire clk_en_n;
wire clk_en_p;
wire clkb_en_n;
wire clkb_en_p;
wire clkdiv_en_p;
wire clkdiv_en_n;
wire clkdivp_en_n;
wire clkdivp_en_p;
assign clk_en_n = IS_CLK_INVERTED;
assign clk_en_p = ~IS_CLK_INVERTED;
assign clkb_en_n = IS_CLKB_INVERTED;
assign clkb_en_p = ~IS_CLKB_INVERTED;
assign clkdiv_en_n = IS_CLKDIV_INVERTED;
assign clkdiv_en_p = ~IS_CLKDIV_INVERTED;
assign clkdivp_en_n = IS_CLKDIVP_INVERTED;
assign clkdivp_en_p = ~IS_CLKDIVP_INVERTED;
`endif
specify
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (negedge CLKB, 0:0:0, notifier);
$period (negedge CLKDIV, 0:0:0, notifier);
$period (negedge CLKDIVP, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKB, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$period (posedge CLKDIVP, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_CE1);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_D);
$setuphold (posedge CLK, negedge DDLY, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_DDLY);
$setuphold (posedge CLK, negedge OFB, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_OFB);
$setuphold (posedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_CE1);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_D);
$setuphold (posedge CLK, posedge DDLY, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_DDLY);
$setuphold (posedge CLK, posedge OFB, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_OFB);
$setuphold (posedge CLKB, negedge CE1, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_CE1);
$setuphold (posedge CLKB, negedge D, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_D);
$setuphold (posedge CLKB, negedge DDLY, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_DDLY);
$setuphold (posedge CLKB, negedge OFB, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_OFB);
$setuphold (posedge CLKB, posedge CE1, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_CE1);
$setuphold (posedge CLKB, posedge D, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_D);
$setuphold (posedge CLKB, posedge DDLY, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_DDLY);
$setuphold (posedge CLKB, posedge OFB, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_OFB);
$setuphold (posedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_BITSLIP);
$setuphold (posedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_CE1);
$setuphold (posedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_CE2);
$setuphold (posedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_BITSLIP);
$setuphold (posedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_CE1);
$setuphold (posedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_CE2);
$setuphold (posedge CLKDIVP, negedge CE1, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_CE1);
$setuphold (posedge CLKDIVP, negedge CE2, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_CE2);
$setuphold (posedge CLKDIVP, posedge CE1, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_CE1);
$setuphold (posedge CLKDIVP, posedge CE2, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_CE2);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_RST);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_RST);
$setuphold (posedge CLKDIVP, negedge RST, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_RST);
$setuphold (posedge CLKDIVP, posedge RST, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_RST);
$setuphold (negedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_CE1);
$setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_D);
$setuphold (negedge CLK, negedge DDLY, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_DDLY);
$setuphold (negedge CLK, negedge OFB, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_OFB);
$setuphold (negedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_CE1);
$setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_D);
$setuphold (negedge CLK, posedge DDLY, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_DDLY);
$setuphold (negedge CLK, posedge OFB, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_OFB);
$setuphold (negedge CLKB, negedge CE1, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_CE1);
$setuphold (negedge CLKB, negedge D, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_D);
$setuphold (negedge CLKB, negedge DDLY, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_DDLY);
$setuphold (negedge CLKB, negedge OFB, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_OFB);
$setuphold (negedge CLKB, posedge CE1, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_CE1);
$setuphold (negedge CLKB, posedge D, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_D);
$setuphold (negedge CLKB, posedge DDLY, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_DDLY);
$setuphold (negedge CLKB, posedge OFB, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_OFB);
$setuphold (negedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_BITSLIP);
$setuphold (negedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_CE1);
$setuphold (negedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_CE2);
$setuphold (negedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_BITSLIP);
$setuphold (negedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_CE1);
$setuphold (negedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_CE2);
$setuphold (negedge CLKDIVP, negedge CE1, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_CE1);
$setuphold (negedge CLKDIVP, negedge CE2, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_CE2);
$setuphold (negedge CLKDIVP, posedge CE1, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_CE1);
$setuphold (negedge CLKDIVP, posedge CE2, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_CE2);
$setuphold (negedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_RST);
$setuphold (negedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_RST);
$setuphold (negedge CLKDIVP, negedge RST, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_RST);
$setuphold (negedge CLKDIVP, posedge RST, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_RST);
`endif
( CLK => Q1) = (100:100:100, 100:100:100);
( CLK => Q2) = (100:100:100, 100:100:100);
( CLK => Q3) = (100:100:100, 100:100:100);
( CLK => Q4) = (100:100:100, 100:100:100);
( CLK => Q5) = (100:100:100, 100:100:100);
( CLK => Q6) = (100:100:100, 100:100:100);
( CLK => Q7) = (100:100:100, 100:100:100);
( CLK => Q8) = (100:100:100, 100:100:100);
( CLKDIV => Q1) = (100:100:100, 100:100:100);
( CLKDIV => Q2) = (100:100:100, 100:100:100);
( CLKDIV => Q3) = (100:100:100, 100:100:100);
( CLKDIV => Q4) = (100:100:100, 100:100:100);
( CLKDIV => Q5) = (100:100:100, 100:100:100);
( CLKDIV => Q6) = (100:100:100, 100:100:100);
( CLKDIV => Q7) = (100:100:100, 100:100:100);
( CLKDIV => Q8) = (100:100:100, 100:100:100);
( CLKDIVP => Q1) = (100:100:100, 100:100:100);
( CLKDIVP => Q2) = (100:100:100, 100:100:100);
( CLKDIVP => Q3) = (100:100:100, 100:100:100);
( CLKDIVP => Q4) = (100:100:100, 100:100:100);
( CLKDIVP => Q5) = (100:100:100, 100:100:100);
( CLKDIVP => Q6) = (100:100:100, 100:100:100);
( CLKDIVP => Q7) = (100:100:100, 100:100:100);
( CLKDIVP => Q8) = (100:100:100, 100:100:100);
( D => O) = (100:100:100, 100:100:100);
( DDLY => O) = (100:100:100, 100:100:100);
( OFB => O) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__AND4_PP_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_PP_BLACKBOX_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:31 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_stub.v
// Design : ip_design_zed_audio_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "i2s_ctrl,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(BCLK, LRCLK, SDATA_I, SDATA_O, S_AXI_ACLK,
S_AXI_ARESETN, S_AXI_AWADDR, S_AXI_AWVALID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WVALID,
S_AXI_BREADY, S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_RREADY, S_AXI_ARREADY, S_AXI_RDATA,
S_AXI_RRESP, S_AXI_RVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_AWREADY)
/* synthesis syn_black_box black_box_pad_pin="BCLK,LRCLK,SDATA_I,SDATA_O,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[31:0],S_AXI_AWVALID,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_BREADY,S_AXI_ARADDR[31:0],S_AXI_ARVALID,S_AXI_RREADY,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_AWREADY" */;
output BCLK;
output LRCLK;
input SDATA_I;
output SDATA_O;
input S_AXI_ACLK;
input S_AXI_ARESETN;
input [31:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input [31:0]S_AXI_WDATA;
input [3:0]S_AXI_WSTRB;
input S_AXI_WVALID;
input S_AXI_BREADY;
input [31:0]S_AXI_ARADDR;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_ARREADY;
output [31:0]S_AXI_RDATA;
output [1:0]S_AXI_RRESP;
output S_AXI_RVALID;
output S_AXI_WREADY;
output [1:0]S_AXI_BRESP;
output S_AXI_BVALID;
output S_AXI_AWREADY;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
parameter WIDTH_START = 2'b00;
parameter WIDTH_CKMIN = 2'b01;
parameter WIDTH_CKMAX = 2'b10;
parameter WIDTH_IDLE = 2'b11;
reg r_test_expr;
reg [1:0] r_state;
integer num_cks;
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=WIDTH_START;
num_cks = 0;
end
`endif
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~(test_expr ^ test_expr);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
always @(posedge clk) begin
r_test_expr <= test_expr;
if (`OVL_RESET_SIGNAL != 1'b0) begin
case (r_state)
WIDTH_START:
if ((r_test_expr == 1'b0) && (test_expr == 1'b1)) begin
num_cks <= 1;
if (min_cks > 0) r_state <= WIDTH_CKMIN;
else if (max_cks > 0) r_state <= WIDTH_CKMAX;
end
WIDTH_CKMIN:
if (test_expr == 1'b1) begin
num_cks <= num_cks + 1;
if (num_cks >= min_cks-1) begin
if (max_cks > 0) r_state <= WIDTH_CKMAX;
else r_state <= WIDTH_IDLE;
end
end
else begin
if (num_cks < min_cks) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression was held TRUE for less than specified minimum min_cks cycles");
end
r_state <= WIDTH_START;
end
WIDTH_CKMAX:
if (test_expr == 1'b1) begin
num_cks <= num_cks + 1;
if (num_cks >= max_cks) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression was held TRUE for more than specified maximum max_cks cycles");
r_state <= WIDTH_IDLE;
end
end
else begin
if (num_cks > max_cks) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression was held TRUE for more than specified maximum max_cks cycles");
end
r_state <= WIDTH_START;
end
WIDTH_IDLE:
if (test_expr == 1'b0) begin
r_state <= WIDTH_START;
end
endcase
end
else begin
r_state <= WIDTH_START;
num_cks <= 0;
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do Nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg r_test_expr_cover;
reg timer_started;
integer num_cks_cover;
`ifdef OVL_SYNTHESIS
`else
initial begin
num_cks_cover = 0;
end
`endif
always @(posedge clk) begin
r_test_expr_cover <= test_expr;
if (`OVL_RESET_SIGNAL != 1'b0 && coverage_level != `OVL_COVER_NONE) begin
if ((r_test_expr_cover == 1'b0) && (test_expr == 1'b1)) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
num_cks_cover <= 1;
timer_started <= 1;
ovl_cover_t("test_expr_asserts covered");
end //basic coverage
end
else if (timer_started && test_expr == 1'b1)
num_cks_cover <= num_cks_cover + 1;
else if (timer_started && (r_test_expr_cover == 1'b1) && (test_expr == 1'b0)) begin
num_cks_cover <= 0;
timer_started <= 0;
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (min_cks > 0 && num_cks_cover == min_cks) begin
ovl_cover_t("test_expr_asserted_for_min_cks covered");
end
if (max_cks > 0 && num_cks_cover == max_cks) begin
ovl_cover_t("test_expr_asserted_for_max_cks covered");
end
end //corner coverage
end
end // OVL_COVER_NONE
else begin // reset condition
num_cks_cover <= 0;
timer_started <= 0;
end // OVL_COVER_NONE
end // always
`endif // OVL_COVER_ON
|
`timescale 1ns / 1ps
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-4-2017
*/
module jt51_mod(
input m1_enters,
input m2_enters,
input c1_enters,
input c2_enters,
input [2:0] alg_I,
output reg use_prevprev1,
output reg use_internal_x,
output reg use_internal_y,
output reg use_prev2,
output reg use_prev1
);
reg [7:0] alg_hot;
always @(*) begin
case( alg_I )
3'd0: alg_hot = 8'h1; // D0
3'd1: alg_hot = 8'h2; // D1
3'd2: alg_hot = 8'h4; // D2
3'd3: alg_hot = 8'h8; // D3
3'd4: alg_hot = 8'h10; // D4
3'd5: alg_hot = 8'h20; // D5
3'd6: alg_hot = 8'h40; // D6
3'd7: alg_hot = 8'h80; // D7
default: alg_hot = 8'hx;
endcase
end
always @(*) begin
use_prevprev1 = m1_enters | (m2_enters&alg_hot[5]);
use_prev2 = (m2_enters&(|alg_hot[2:0])) | (c2_enters&alg_hot[3]);
use_internal_x = c2_enters & alg_hot[2];
use_internal_y = c2_enters & (|{alg_hot[4:3],alg_hot[1:0]});
use_prev1 = m1_enters | (m2_enters&alg_hot[1]) |
(c1_enters&(|{alg_hot[6:3],alg_hot[0]}) )|
(c2_enters&(|{alg_hot[5],alg_hot[2]}));
end
endmodule
|
`timescale 1ns/1ps
`define INDEX(x,y) x*y +: y
module tb_register ;
localparam REGISTER_NUM_REGISTERS = 16 ;
localparam REGISTER_NUM_DATA_IN = 2 ;
localparam REGISTER_NUM_DATA_OUT = 4 ;
localparam REGISTER_NUM_SEL_BITS = $clog2(REGISTER_NUM_REGISTERS) ;
localparam REGISTER_WIDTH_DATA = 32 ;
localparam REGISTER_NUM_WRITE_TESTS = 128 ;
reg r_clk ;
reg [REGISTER_NUM_DATA_IN-1:0] r_we ;
reg [REGISTER_NUM_DATA_OUT-1:0] r_re ;
reg [REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS-1:0] r_data_in_sel ;
reg [REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS-1:0] r_data_out_sel ;
reg [REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA-1:0] r_data_in ;
wire [REGISTER_NUM_DATA_OUT*REGISTER_WIDTH_DATA-1:0] w_data_out ;
register dut (
.i_clk (r_clk),
.i_we (r_we),
.i_re (r_re),
.i_data_in_sel (r_data_in_sel),
.i_data_out_sel (r_data_out_sel),
.i_data_in (r_data_in),
.o_data_out (w_data_out)
) ;
initial begin
r_clk = 0 ;
r_we = {REGISTER_NUM_DATA_IN{1'b0}} ;
r_re = {REGISTER_NUM_DATA_OUT{1'b0}} ;
r_data_in_sel = {REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_out_sel = {REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_in = {REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA{1'b0}} ;
end
initial begin
$dumpfile ("tb_register.dump") ;
$dumpvars ;
end
initial begin
$display("\t|%10s |%4s |%4s |%13s |%18s |%4s |%14s |%34s |","time","clk","we","data_in_sel","data_in","re",
"data_out_sel","data_out") ;
$monitor("\t|%10t |%4h |%4h |%13h |%18h |%4h |%14h |%34h |",$time,r_clk,r_we,r_data_in_sel,r_data_in,r_re,
r_data_out_sel, w_data_out) ;
end
always begin
#50 r_clk = !r_clk ;
end
initial begin : Test_Cases
integer i ;
for (i=0; i<REGISTER_NUM_WRITE_TESTS; i=i+1) begin : Writing_Test
#20 r_we[$urandom%REGISTER_NUM_DATA_IN] = $random ;
r_data_in_sel[`INDEX($clog2(r_we),REGISTER_NUM_SEL_BITS)] = $random ;
r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)] = $random ;
r_re = 1'b1 ;
r_data_out_sel[`INDEX(0,REGISTER_NUM_SEL_BITS)] = r_data_in_sel[`INDEX($clog2(r_we),
REGISTER_NUM_SEL_BITS)] ;
#150 if ((r_we != {REGISTER_NUM_DATA_IN{1'b0}}) && (w_data_out[`INDEX(0,REGISTER_WIDTH_DATA)] !=
r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)])) begin
$display ("Write error at time %0t",$time) ;
$display ("Expected value: %0h, Actual value: %0h", r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)],
w_data_out[`INDEX(0,REGISTER_WIDTH_DATA)]) ;
$stop ;
end
#30 r_we = {REGISTER_NUM_DATA_IN{1'b0}} ;
r_data_in_sel = {REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_in = {REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA{1'b0}} ;
r_re = {REGISTER_NUM_DATA_OUT{1'b0}} ;
r_data_out_sel = {REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS{1'b0}} ;
end
$stop ;
end
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_s_w_channel.v
// Version : v1.0
// Description: slave interface write channel.Write requests are processed
// to write to target location.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
//Specific WARNINGs moved to INFO by Vivado Synthesis Tool
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_s_w_channel #(
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_S_AXI_AWUSER_WIDTH = 8 ,
parameter C_ZERO_INVALID = 1 ,
parameter C_NO_EXCL = 0 ,
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_ATG_AXI4LITE = 0
) (
// system
input Clk ,
input rst_l ,
// AW
input [C_S_AXI_ID_WIDTH-1:0] awid_s ,
input [31:0] awaddr_s ,
input [7:0] awlen_s ,
input [2:0] awsize_s ,
input [1:0] awburst_s ,
input [0:0] awlock_s ,
input [3:0] awcache_s ,
input [2:0] awprot_s ,
input [3:0] awqos_s ,
input [C_S_AXI_AWUSER_WIDTH-1:0] awuser_s ,
input awvalid_s ,
output awready_s ,
// W
input wlast_s ,
input [C_S_AXI_DATA_WIDTH-1:0] wdata_s ,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_s ,
input wvalid_s ,
output wready_s ,
//B
output [C_S_AXI_ID_WIDTH-1:0] bid_s ,
output [1:0] bresp_s ,
output bvalid_s ,
input bready_s ,
// Register module
input reg1_disallow_excl ,
input reg1_sgl_slv_wr ,
input reg1_wrs_block_rds ,
output [15:0] err_new_slv ,
output [15:0] wr_reg_decode ,
output [31:0] wr_reg_data ,
// sr channel
input [71:0] slv_ex_info0_ff ,
output reg slv_ex_valid0_ff ,
input[71:0] slv_ex_info1_ff ,
output reg slv_ex_valid1_ff ,
input slv_ex_new_valid0 ,
input slv_ex_new_valid1 ,
input [15:0] ar_agen_addr ,
output [C_S_AXI_DATA_WIDTH-1:0] slvram_rd_out ,
//slvram
input [63:0] sram_rd_data_a ,
output [10:0] slvram_waddr_ff ,
output [7:0] slvram_we_ff ,
output [63:0] slvram_write_data_ff,
//axi_traffic_gen_v2_0_7_cmdram
output [15:0] aw_agen_addr ,
output aw_agen_valid_out ,
output [15:0] cmdram_we ,
output [64-1:0] slvram_wr_data ,
//paramram
output awfifo_valid ,
output [71:0] awfifo_out ,
output wfifo_valid ,
output [C_S_AXI_DATA_WIDTH*9/8+1-1:0] wfifo_out
);
wire [31:0] base_addr = C_BASEADDR;
wire [31:0] high_addr = C_HIGHADDR;
wire [31:0] addr_mask = base_addr[31:0] ^ high_addr[31:0];
//wire [7:0] awlen8_s = awlen_s[7:0] | { 4'h0, awlen3_s[3:0] };
wire [7:0] awlen8_s = awlen_s[7:0] | { 4'h0, 4'h0 };
wire [15:0] awbuf_id = awid_s[C_S_AXI_ID_WIDTH-1:0];
wire [31:0] aw_addr_masked = awaddr_s[31:0] & addr_mask[31:0];
//Address re-mapped
//wire aw_isslvram = ((aw_addr_masked[22:16] != 'h0 ));
wire aw_isslvram = ((aw_addr_masked[15:14]==2'b11));
wire aw_iscmd = ~aw_isslvram && awaddr_s[15] && ~awaddr_s[13];
wire [71:0] awbuf_rawdata = {
awbuf_id[15:0], //71:56
aw_isslvram, aw_iscmd, awprot_s[2:0], awsize_s[2:0], //55:48
awburst_s[1:0], 1'b0,awlock_s[0:0], awcache_s[3:0], //47:40 //awlock made 1-bit
awlen8_s[7:0], //39:32
awaddr_s[31:0] }; //31:0
wire awbuf_valid = awvalid_s && awready_s;
wire awfifo_notfull;
wire aw_agen_write;
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (72),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Awfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (awbuf_rawdata[71:0]),
.in_push (awbuf_valid ),
.in_pop (aw_agen_write ),
.out_data (awfifo_out[71:0] ),
.is_full ( ),
.is_notfull (awfifo_notfull ),
.is_empty ( ),
.out_valid (awfifo_valid ),
.ex_fifo_dbgout ( )
);
assign awready_s = awfifo_notfull;
wire [15:0] aw_agen_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] aw_agen_be;
wire aw_agen_pop;
wire aw_agen_done;
wire aw_agen_valid;
wire awfifo_out_is_excl ;
wire aw_agen_pause = awfifo_valid && awfifo_out_is_excl && aw_agen_valid;
assign aw_agen_write = awfifo_valid && ~aw_agen_valid && ~aw_agen_pause;
assign aw_agen_valid_out = aw_agen_valid;
wire [71:0] slv_ex_wr_info ;
wire slv_ex_addr_matches0 ;
wire slv_ex_id_matches0 ;
wire slv_ex_wr_matches0 ;
wire slv_ex_addr_matches1 ;
wire slv_ex_id_matches1 ;
wire slv_ex_wr_matches1 ;
wire slv_ex_wr_matches ;
wire [1:0] awfifo_out_excl ;
wire awfifo_out_null ;
wire aw_err ;
generate if(C_NO_EXCL == 0 ) begin : S_W_EXCL_0
assign awfifo_out_is_excl = (awfifo_out[45:44] == 2'b01);
assign slv_ex_wr_info = awfifo_out[71:0];
assign slv_ex_addr_matches0 = (slv_ex_wr_info[19:7] == slv_ex_info0_ff[19:7]);
assign slv_ex_id_matches0 = (slv_ex_wr_info[71:56] == slv_ex_info0_ff[71:56]);
assign slv_ex_wr_matches0 = (slv_ex_wr_info[55:20] ==slv_ex_info0_ff[55:20]) &&
(slv_ex_wr_info[6:0] == slv_ex_info0_ff[6:0]) &&
slv_ex_addr_matches0 && slv_ex_id_matches0 &&
slv_ex_valid0_ff;
assign slv_ex_addr_matches1 = (slv_ex_wr_info[19:7] == slv_ex_info1_ff[19:7]);
assign slv_ex_id_matches1 = (slv_ex_wr_info[71:56] == slv_ex_info1_ff[71:56]);
assign slv_ex_wr_matches1 = (slv_ex_wr_info[55:20] ==slv_ex_info1_ff[55:20]) &&
(slv_ex_wr_info[6:0] == slv_ex_info1_ff[6:0]) &&
slv_ex_addr_matches1 && slv_ex_id_matches1 &&
slv_ex_valid1_ff;
assign slv_ex_wr_matches = (C_NO_EXCL) ? 1'b0 :
slv_ex_wr_matches0 || slv_ex_wr_matches1;
assign awfifo_out_excl = (awfifo_out_is_excl && slv_ex_wr_matches) ? 2'b01 :
2'b00;
assign awfifo_out_null = aw_err ||
(awfifo_out_is_excl && ~reg1_disallow_excl &&
~slv_ex_wr_matches && (C_NO_EXCL == 0));
end
endgenerate
generate if(C_NO_EXCL == 1) begin : S_W_EXCL_1
assign awfifo_out_is_excl = 2'b00;
assign slv_ex_wr_matches = 1'b0 ;
assign awfifo_out_excl = 2'b00;
assign awfifo_out_null = aw_err ;
end
endgenerate
assign aw_err = (awfifo_out[55:54] == 2'b00) && (awfifo_out[5:2] == 4'hd) &&
awfifo_out[7] && ~awfifo_out[12];
// writing to reg13, at 0xb4
// and not 0x1XXX (for special queue ops)
wire [1:0] awfifo_out_resp = (reg1_disallow_excl) ? 2'b00 :
(aw_err) ? 2'b10 : awfifo_out_excl[1:0];
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (0) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Aw_agen (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({awfifo_out[55:54], awfifo_out[13:0]} ),
.in_addr_offset(awfifo_out[8:0] ),
.in_id ({ awfifo_out_resp[1:0], awfifo_out_null, awfifo_out[68:56]}),
.in_len (awfifo_out[39:32] ),
.in_size (awfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (awfifo_out[47:46] ),
.in_push (aw_agen_write ),
.in_pop (aw_agen_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (aw_agen_addr[15:0] ),
.out_id (aw_agen_id[15:0] ),
.out_be (aw_agen_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_done (aw_agen_done ),
.out_valid (aw_agen_valid )
);
wire slv_ex_agen_id_matches0 ;
wire slv_ex_clr_valid0 ;
wire slv_ex_valid0 ;
wire slv_ex_agen_id_matches1 ;
wire slv_ex_clr_valid1 ;
wire slv_ex_valid1 ;
generate if(C_NO_EXCL == 0 ) begin : S_W1_EXCL_0
assign slv_ex_agen_id_matches0 = (aw_agen_id[13:0] == slv_ex_info0_ff[69:56]);
assign slv_ex_clr_valid0 = aw_agen_valid &&
(aw_agen_addr[13:3] == slv_ex_info0_ff[13:3]) &&
~slv_ex_agen_id_matches0 && ~aw_agen_id[13];
// Don't clear if its from the ex master, or if the write is
// nullified (aw_agen_id[13]).
assign slv_ex_valid0 = (C_NO_EXCL) ? 1'b0 :
slv_ex_new_valid0 || (~slv_ex_clr_valid0 && slv_ex_valid0_ff);
assign slv_ex_agen_id_matches1 = (aw_agen_id[13:0] == slv_ex_info1_ff[69:56]);
assign slv_ex_clr_valid1 = aw_agen_valid &&
(aw_agen_addr[13:3] == slv_ex_info1_ff[13:3]) &&
~slv_ex_agen_id_matches1 && ~aw_agen_id[13];
// Don't clear if its from the ex master, or if the write is
// nullified (aw_agen_id[13]).
assign slv_ex_valid1 = (C_NO_EXCL) ? 1'b0 :
slv_ex_new_valid1 || (~slv_ex_clr_valid1 && slv_ex_valid1_ff);
end
endgenerate
generate if(C_NO_EXCL == 1 ) begin : S_W1_EXCL_1
assign slv_ex_valid0 = 1'b0 ;
assign slv_ex_valid1 = 1'b0 ;
end
endgenerate
// Buffer write data in a fifo
wire wbuf_valid = wvalid_s && wready_s;
wire wbuf_pop;
wire wfifo_notfull;
//wire wfifo_valid;
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (C_S_AXI_DATA_WIDTH*9/8+1),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Wfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data({ wlast_s, wstrb_s[C_S_AXI_DATA_WIDTH/8-1:0],
wdata_s[C_S_AXI_DATA_WIDTH-1:0] }),
.in_push (wbuf_valid ),
.in_pop (wbuf_pop ),
.out_data (wfifo_out[C_S_AXI_DATA_WIDTH*9/8+1-1:0] ),
.is_full ( ),
.is_notfull (wfifo_notfull ),
.is_empty ( ),
.out_valid (wfifo_valid ),
.ex_fifo_dbgout ( )
);
assign wready_s = wfifo_notfull;
// Buffer bresps in fifos as well
wire [15:0] bbuf_id = aw_agen_id[15:0];
wire [1:0] bbuf_resp = aw_agen_id[15:14];
wire [19:0] bbuf_rawdata = {
bbuf_id[15:0], //19:4
2'b00, bbuf_resp[1:0] }; //3:0
wire [3:0] btrk_fifo_num, btrk_free;
wire bfifo0_pop, bfifo1_pop, bfifo2_pop, bfifo3_pop;
wire bfifo0_notfull, bfifo1_notfull, bfifo2_notfull, bfifo3_notfull;
wire bfifo0_valid, bfifo1_valid, bfifo2_valid, bfifo3_valid;
wire [19:0] bfifo0_out, bfifo1_out, bfifo2_out, bfifo3_out;
wire [C_S_AXI_ID_WIDTH-1:0] btrk_in_push_id = bbuf_rawdata[19:0];
wire [3:0] b_fifo_valid = { bfifo3_valid, bfifo2_valid,
bfifo1_valid, bfifo0_valid };
wire [3:0] b_fifo_push = ~b_fifo_valid[3:0] & btrk_fifo_num[3:0];
wire [3:0] btrk_clear_pos = ~b_fifo_valid[3:0];
wire btrk_push = aw_agen_pop && aw_agen_done;
wire [C_S_AXI_ID_WIDTH-1:0] dummy_search_id = 32'h0;
wire dis_dis_out_of_order;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W_OOO_YES
assign dis_dis_out_of_order = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W_OOO_NO
assign dis_dis_out_of_order = 1'b1;
end
endgenerate
axi_traffic_gen_v2_0_7_id_track #(
.ID_WIDTH(C_S_AXI_ID_WIDTH)
) B_track (
.Clk (Clk ),
.rst_l (rst_l ),
.in_push_id (btrk_in_push_id[C_S_AXI_ID_WIDTH-1:0]),
.in_push (btrk_push ),
.in_search_id (dummy_search_id[C_S_AXI_ID_WIDTH-1:0]),
.in_clear_pos (btrk_clear_pos[3:0] ),
.in_only_entry0(dis_dis_out_of_order ),
.out_push_pos (btrk_fifo_num[3:0] ),
.out_search_hit( ),
.out_free (btrk_free[3:0] )
);
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo0 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[0] ),
.in_pop (bfifo0_pop ),
.out_data (bfifo0_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo0_notfull ),
.is_empty ( ),
.out_valid (bfifo0_valid ),
.ex_fifo_dbgout ( )
);
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W_OOO_F_NO
assign bfifo1_notfull = 1'b1;
assign bfifo1_valid = 1'b0;
assign bfifo2_notfull = 1'b1;
assign bfifo2_valid = 1'b0;
assign bfifo3_notfull = 1'b1;
assign bfifo3_valid = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W_OOO_F_YES
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo1 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[1] ),
.in_pop (bfifo1_pop ),
.out_data (bfifo1_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo1_notfull ),
.is_empty ( ),
.out_valid (bfifo1_valid ),
.ex_fifo_dbgout ( )
);
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo2 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[2] ),
.in_pop (bfifo2_pop ),
.out_data (bfifo2_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo2_notfull ),
.is_empty ( ),
.out_valid (bfifo2_valid ),
.ex_fifo_dbgout ( )
);
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo3 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[3] ),
.in_pop (bfifo3_pop ),
.out_data (bfifo3_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo3_notfull ),
.is_empty ( ),
.out_valid (bfifo3_valid ),
.ex_fifo_dbgout ( )
);
end
endgenerate
wire [19:0] bfifo_out;
wire bfifo_valid;
wire bfifo_notfull;
wire [3:0] bfifo_sel = (bfifo3_valid) ? 4'h8 :
(bfifo2_valid) ? 4'h4 :
(bfifo1_valid) ? 4'h2 :
(bfifo0_valid) ? 4'h1 : 4'h0;
assign bfifo0_pop = bfifo_notfull && bfifo_sel[0];
assign bfifo1_pop = bfifo_notfull && bfifo_sel[1];
assign bfifo2_pop = bfifo_notfull && bfifo_sel[2];
assign bfifo3_pop = bfifo_notfull && bfifo_sel[3];
wire [19:0] bfifo_in_data ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W1_OOO_YES
assign bfifo_in_data = ((bfifo_sel[0]) ? bfifo0_out[19:0] : 20'h0) |
((bfifo_sel[1]) ? bfifo1_out[19:0] : 20'h0) |
((bfifo_sel[2]) ? bfifo2_out[19:0] : 20'h0) |
((bfifo_sel[3]) ? bfifo3_out[19:0] : 20'h0);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W1_OOO_NO
assign bfifo_in_data = ((bfifo_sel[0]) ? bfifo0_out[19:0] : 20'h0) ;
end
endgenerate
wire bfifo_pop = bfifo_valid && bready_s;
wire bfifo_push = bfifo_notfull && (bfifo_sel[3:0] != 4'h0);
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (20 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Bfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bfifo_in_data[19:0]),
.in_push (bfifo_push ),
.in_pop (bfifo_pop ),
.out_data (bfifo_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo_notfull ),
.is_empty ( ),
.out_valid (bfifo_valid ),
.ex_fifo_dbgout ( )
);
assign wbuf_pop = wfifo_valid && aw_agen_valid &&
bfifo0_notfull && bfifo1_notfull && bfifo2_notfull &&
bfifo3_notfull && (btrk_free[3:0] != 4'h0);
assign aw_agen_pop = wbuf_pop;
wire wfifo_bad_last = wbuf_pop && (aw_agen_done != wfifo_out[C_S_AXI_DATA_WIDTH*9/8]);
wire [C_S_AXI_DATA_WIDTH/8-1:0] wfifo_out_be =
wfifo_out[C_S_AXI_DATA_WIDTH*9/8-1:C_S_AXI_DATA_WIDTH];
wire wfifo_bad_be_pre = (~aw_agen_be[C_S_AXI_DATA_WIDTH/8-1:0] &
wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0]) != 8'h0;
wire wfifo_bad_be = wbuf_pop && wfifo_bad_be_pre;
assign bresp_s[1:0] = bfifo_out[1:0];
assign bid_s[C_S_AXI_ID_WIDTH-1:0] = bfifo_out[19:4];
assign bvalid_s = bfifo_valid;
wire slv_wr_pending = awfifo_valid || aw_agen_valid;
always @(posedge Clk) begin
slv_ex_valid0_ff <= (rst_l) ? slv_ex_valid0 : 1'b0;
slv_ex_valid1_ff <= (rst_l) ? slv_ex_valid1 : 1'b0;
end
//register interface information
wire wr_reg_isreg = (aw_agen_addr[15:14] == 2'b00) && aw_agen_pop &&
~aw_agen_addr[7]
&& ~aw_agen_addr[12]//; // adding this for special_queue
&& ~aw_agen_addr[13]; // adding this for addrram
assign wr_reg_decode = { 15'h0, wr_reg_isreg } << aw_agen_addr[5:2];
wire [11:0] wr_reg_shift = (C_S_AXI_DATA_WIDTH == 32) ? 12'h0 :
(C_S_AXI_DATA_WIDTH == 64) ? { 6'h0, aw_agen_addr[2], 5'h0 } :
(C_S_AXI_DATA_WIDTH == 128) ? { 5'h0, aw_agen_addr[3:2], 5'h0 }:
{ 4'h0, aw_agen_addr[4:2], 5'h0 };
assign wr_reg_data = wfifo_out[C_S_AXI_DATA_WIDTH-1:0] >>
wr_reg_shift[11:0];
//slv/mst ram decode
wire slvram_do_write = wbuf_pop && aw_agen_addr[15] && ~aw_agen_id[13];
wire [7:0] slvram_we = (slvram_do_write) ?
{4'h0,wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0]} : 'h0;
assign slvram_wr_data = (C_S_AXI_DATA_WIDTH == 64) ? wfifo_out[C_S_AXI_DATA_WIDTH-1:0] :
{2{wfifo_out[C_S_AXI_DATA_WIDTH-1:0]}};
wire [63:0] slvram_rd_out_pre;
assign slvram_rd_out_pre[63:0] = sram_rd_data_a;
reg [63:0] slvram_wr_data64_ff;
reg [7:0] slvram_rdwr_mask8_ff;
reg [C_S_AXI_DATA_WIDTH-1:0] slvram_wr_datareg_ff;
reg [31:0] slvram_rdwr_mask_ff;
wire [13:0] rdwr_match_mask =
(C_S_AXI_DATA_WIDTH == 256) ? 14'h3fe0 :
(C_S_AXI_DATA_WIDTH == 128) ? 14'h1ff0 :
(C_S_AXI_DATA_WIDTH == 64) ? 14'h1ffe : 14'h1ffc;
wire slvram_rdwr_match = slvram_do_write &&
((ar_agen_addr[13:0] & rdwr_match_mask[13:0]) ==
(aw_agen_addr[13:0] & rdwr_match_mask[13:0]));
wire [C_S_AXI_DATA_WIDTH-1:0] slvram_wr_datareg = (slvram_rdwr_match) ?
slvram_wr_data[C_S_AXI_DATA_WIDTH-1:0] :
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0];
wire [31:0] slvram_rdwr_mask = (slvram_rdwr_match) ?
wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0] : 'h0;
wire [C_S_AXI_DATA_WIDTH-1:0] slvram_rdwr_mask_exp = {
{ 8 { slvram_rdwr_mask_ff[31] } }, { 8 { slvram_rdwr_mask_ff[30] } },
{ 8 { slvram_rdwr_mask_ff[29] } }, { 8 { slvram_rdwr_mask_ff[28] } },
{ 8 { slvram_rdwr_mask_ff[27] } }, { 8 { slvram_rdwr_mask_ff[26] } },
{ 8 { slvram_rdwr_mask_ff[25] } }, { 8 { slvram_rdwr_mask_ff[24] } },
{ 8 { slvram_rdwr_mask_ff[23] } }, { 8 { slvram_rdwr_mask_ff[22] } },
{ 8 { slvram_rdwr_mask_ff[21] } }, { 8 { slvram_rdwr_mask_ff[20] } },
{ 8 { slvram_rdwr_mask_ff[19] } }, { 8 { slvram_rdwr_mask_ff[18] } },
{ 8 { slvram_rdwr_mask_ff[17] } }, { 8 { slvram_rdwr_mask_ff[16] } },
{ 8 { slvram_rdwr_mask_ff[15] } }, { 8 { slvram_rdwr_mask_ff[14] } },
{ 8 { slvram_rdwr_mask_ff[13] } }, { 8 { slvram_rdwr_mask_ff[12] } },
{ 8 { slvram_rdwr_mask_ff[11] } }, { 8 { slvram_rdwr_mask_ff[10] } },
{ 8 { slvram_rdwr_mask_ff[9] } }, { 8 { slvram_rdwr_mask_ff[8] } },
{ 8 { slvram_rdwr_mask_ff[7] } }, { 8 { slvram_rdwr_mask_ff[6] } },
{ 8 { slvram_rdwr_mask_ff[5] } }, { 8 { slvram_rdwr_mask_ff[4] } },
{ 8 { slvram_rdwr_mask_ff[3] } }, { 8 { slvram_rdwr_mask_ff[2] } },
{ 8 { slvram_rdwr_mask_ff[1] } }, { 8 { slvram_rdwr_mask_ff[0] } } };
assign slvram_rd_out[C_S_AXI_DATA_WIDTH-1:0] =
(slvram_rdwr_mask_exp[C_S_AXI_DATA_WIDTH-1:0] &
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0]) |
(~slvram_rdwr_mask_exp[C_S_AXI_DATA_WIDTH-1:0] &
slvram_rd_out_pre[C_S_AXI_DATA_WIDTH-1:0]);
always @(posedge Clk) begin
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0] <= (rst_l) ?
slvram_wr_datareg[C_S_AXI_DATA_WIDTH-1:0] : 'h0;
slvram_rdwr_mask_ff[31:0] <= (rst_l) ? slvram_rdwr_mask[31:0] : 32'h0;
end
assign err_new_slv[15:0] = { 14'h0, wfifo_bad_be, wfifo_bad_last };
// adding sram regslice for timing closure
wire [82:0] sram_slvramwr_ff;
axi_traffic_gen_v2_0_7_regslice
#(
.DWIDTH (83),
.IDWIDTH (1) ,
.DATADEPTH(1 )
)
sram_slvramwr_regslice
(
.din ({aw_agen_addr[12:2],slvram_we,slvram_wr_data}),
.dout (sram_slvramwr_ff ),
.dout_early ( ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
assign slvram_waddr_ff = sram_slvramwr_ff[82:72];
assign slvram_we_ff = sram_slvramwr_ff[71:64];
assign slvram_write_data_ff = sram_slvramwr_ff[63:0];
//cmdram decode
// sent out aw_agen_addr as output also.
// this is used along with ar_agen0_addr,maw_ptr_new,mar_ptr_new
// to select address to cmdram based on reg0_m_enable_ff
wire [31:0] cmdram_we32 = wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0];
wire [3:0] cmdram_we4 ;
wire [7:0] cmdram_we8 ;
wire [7:0] cmdram_we_pre ;
generate if(C_S_AXI_DATA_WIDTH == 32) begin :CMD_WE_32
assign cmdram_we4 = cmdram_we32[31:28] | cmdram_we32[27:24] |
cmdram_we32[23:20] | cmdram_we32[19:16] |
cmdram_we32[15:12] | cmdram_we32[11:8] |
cmdram_we32[7:4] | cmdram_we32[3:0];
assign cmdram_we_pre = (wbuf_pop && aw_agen_addr[14]) ? cmdram_we4[3:0] :
4'h0;
assign cmdram_we =
(aw_agen_addr[3:2] == 2'b11) ? { cmdram_we_pre[3:0], 12'h0 } :
(aw_agen_addr[3:2] == 2'b10) ? { 4'h0, cmdram_we_pre[3:0], 8'h0 } :
(aw_agen_addr[3:2] == 2'b01) ? { 8'h0, cmdram_we_pre[3:0], 4'h0 } :
{ 12'h0, cmdram_we_pre[3:0] };
end
endgenerate
generate if(C_S_AXI_DATA_WIDTH == 64) begin :CMD_WE_64
assign cmdram_we8 = cmdram_we32[31:24] |
cmdram_we32[23:16] |
cmdram_we32[15:8] |
cmdram_we32[7:0] ;
assign cmdram_we_pre = (wbuf_pop && aw_agen_addr[14]) ? cmdram_we8[7:0] :
8'h0;
assign cmdram_we =
(aw_agen_addr[3] == 1'b1) ? { cmdram_we_pre[7:0], 8'h0 } :
{ 8'h0, cmdram_we_pre[7:0] };
end
endgenerate
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_CS,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK,
/* debug */
output p113_out
);
wire CLK2;
wire dspx_dp_enable;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
//wire [7:0] dac_volume;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [14:0] bsx_regs;
wire [7:0] BSX_SNES_DATA_IN;
wire [7:0] BSX_SNES_DATA_OUT;
wire [7:0] bsx_regs_reset_bits;
wire [7:0] bsx_regs_set_bits;
wire [59:0] rtc_data;
wire [55:0] rtc_data_in;
wire [59:0] srtc_rtc_data_out;
wire [3:0] SRTC_SNES_DATA_IN;
wire [7:0] SRTC_SNES_DATA_OUT;
wire [7:0] DSPX_SNES_DATA_IN;
wire [7:0] DSPX_SNES_DATA_OUT;
wire [23:0] dspx_pgm_data;
wire [10:0] dspx_pgm_addr;
wire dspx_pgm_we;
wire [15:0] dspx_dat_data;
wire [10:0] dspx_dat_addr;
wire dspx_dat_we;
wire [7:0] featurebits;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [9:0] bs_page;
wire [8:0] bs_page_offset;
wire bs_page_enable;
wire [4:0] DBG_srtc_state;
wire DBG_srtc_we_rising;
wire [3:0] DBG_srtc_ptr;
wire [5:0] DBG_srtc_we_sreg;
wire [13:0] DBG_msu_address;
wire DBG_msu_reg_oe_rising;
wire DBG_msu_reg_oe_falling;
wire DBG_msu_reg_we_rising;
wire [2:0] SD_DMA_DBG_clkcnt;
wire [10:0] SD_DMA_DBG_cyclecnt;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
reg [7:0] SNES_PARDr;
reg [7:0] SNES_READr;
reg [7:0] SNES_WRITEr;
reg [7:0] SNES_CPU_CLKr;
reg [23:0] SNES_ADDRr [5:0];
reg [7:0] SNES_DATAr [4:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
wire SNES_PARD_start = ((SNES_PARDr[6:1] | SNES_PARDr[7:2]) == 6'b111110);
wire SNES_RD_start = ((SNES_READr[6:1] | SNES_READr[7:2]) == 6'b111110);
wire SNES_RD_end = ((SNES_READr[6:1] & SNES_READr[7:2]) == 6'b000001);
wire SNES_WR_end = ((SNES_WRITEr[6:1] & SNES_WRITEr[7:2]) == 6'b000001);
wire SNES_cycle_start = ((SNES_CPU_CLKr[5:2] & SNES_CPU_CLKr[4:1]) == 4'b0001);
wire SNES_cycle_end = ((SNES_CPU_CLKr[5:2] | SNES_CPU_CLKr[4:1]) == 4'b1110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire free_slot = SNES_cycle_end | free_strobe;
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= ~ROM_HIT;
end
always @(posedge CLK2) begin
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
end
parameter ST_IDLE = 5'b00001;
parameter ST_MCU_RD_ADDR = 5'b00010;
parameter ST_MCU_RD_END = 5'b00100;
parameter ST_MCU_WR_ADDR = 5'b01000;
parameter ST_MCU_WR_END = 5'b10000;
parameter SNES_DEAD_TIMEOUT = 17'd86000; // 1ms
parameter ROM_CYCLE_LEN = 4'd7;
reg [4:0] STATE;
initial STATE = ST_IDLE;
assign DSPX_SNES_DATA_IN = BUS_DATA;
assign SRTC_SNES_DATA_IN = BUS_DATA[3:0];
assign MSU_SNES_DATA_IN = BUS_DATA;
assign BSX_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk(DAC_MCLK),
.lrck(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset)
);
srtc snes_srtc (
.clkin(CLK2),
.addr_in(SNES_ADDR[0]),
.data_in(SRTC_SNES_DATA_IN),
.data_out(SRTC_SNES_DATA_OUT),
.rtc_data_in(rtc_data),
.enable(srtc_enable),
.rtc_data_out(srtc_rtc_data_out),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.rtc_we(srtc_rtc_we),
.reset(srtc_reset),
.srtc_state(DBG_srtc_state),
.srtc_reg_we_rising(DBG_srtc_we_rising),
.srtc_rtc_ptr(DBG_srtc_ptr),
.srtc_we_sreg(DBG_srtc_we_sreg)
);
rtc snes_rtc (
.clkin(CLKIN),
.rtc_data(rtc_data),
.rtc_data_in(rtc_data_in),
.pgm_we(rtc_pgm_we),
.rtc_data_in1(srtc_rtc_data_out),
.we1(srtc_rtc_we)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
bsx snes_bsx(
.clkin(CLK2),
.use_bsx(use_bsx),
.pgm_we(bsx_regs_reset_we),
.snes_addr(SNES_ADDR),
.reg_data_in(BSX_SNES_DATA_IN),
.reg_data_out(BSX_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.regs_out(bsx_regs),
.reg_reset_bits(bsx_regs_reset_bits),
.reg_set_bits(bsx_regs_set_bits),
.data_ovr(bsx_data_ovr),
.flash_writable(IS_FLASHWR),
.rtc_data(rtc_data[59:0]),
.bs_page_out(bs_page), // support only page 0000-03ff
.bs_page_enable(bs_page_enable),
.bs_page_offset(bs_page_offset)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
wire [15:0] dsp_feat;
upd77c25 snes_dspx (
.DI(DSPX_SNES_DATA_IN),
.DO(DSPX_SNES_DATA_OUT),
.A0(DSPX_A0),
.enable(dspx_enable),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.RST(~dspx_reset),
.CLK(CLK2),
.PGM_WR(dspx_pgm_we),
.PGM_DI(dspx_pgm_data),
.PGM_WR_ADDR(dspx_pgm_addr),
.DAT_WR(dspx_dat_we),
.DAT_DI(dspx_dat_data),
.DAT_WR_ADDR(dspx_dat_addr),
.DP_enable(dspx_dp_enable),
.DP_ADDR(SNES_ADDR[10:0]),
.dsp_feat(dsp_feat)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.bsx_regs_set_out(bsx_regs_set_bits),
.bsx_regs_reset_out(bsx_regs_reset_bits),
.bsx_regs_reset_we(bsx_regs_reset_we),
.rtc_data_out(rtc_data_in),
.rtc_pgm_we(rtc_pgm_we),
.srtc_reset(srtc_reset),
.dspx_pgm_data_out(dspx_pgm_data),
.dspx_pgm_addr_out(dspx_pgm_addr),
.dspx_pgm_we_out(dspx_pgm_we),
.dspx_dat_data_out(dspx_dat_data),
.dspx_dat_addr_out(dspx_dat_addr),
.dspx_dat_we_out(dspx_dat_we),
.dspx_reset_out(dspx_reset),
.featurebits_out(featurebits),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
wire [7:0] DCM_STATUS;
// dcm1: dfs 4x
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT), // want to access RAM0
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
//MSU-1
.msu_enable(msu_enable),
//BS-X
.use_bsx(use_bsx),
.bsx_regs(bsx_regs),
.bs_page_offset(bs_page_offset),
.bs_page(bs_page),
.bs_page_enable(bs_page_enable),
.bsx_tristate(bsx_tristate),
//SRTC
.srtc_enable(srtc_enable),
//uPD77C25
.dspx_enable(dspx_enable),
.dspx_dp_enable(dspx_dp_enable),
.dspx_a0(DSPX_A0),
.r213f_enable(r213f_enable),
.snescmd_enable(snescmd_enable)
);
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.snescmd_wr_strobe(SNES_WR_end & snescmd_enable),
.SNES_cycle_start(SNES_RD_start),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
? (srtc_enable ? SRTC_SNES_DATA_OUT
:dspx_enable ? DSPX_SNES_DATA_OUT
:dspx_dp_enable ? DSPX_SNES_DATA_OUT
:msu_enable ? MSU_SNES_DATA_OUT
:bsx_data_ovr ? BSX_SNES_DATA_OUT
:(snescmd_unlock & snescmd_enable) ? snescmd_dout
:cheat_hit ? cheat_data_out
:(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
wire MCU_WR_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_RD_HIT = |(STATE & ST_MCU_RD_ADDR);
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
endcase
end
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b000;
r213f_state <= 2'b10;
end else if(r213f_state == 2'b10) begin
r213f_delay <= r213f_delay - 1;
if(r213f_delay == 3'b000) begin
r213f_forceread <= 1'b0;
r213f_state <= 2'b01;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & (IS_WRITABLE | IS_FLASHWR) & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WR_HIT ? 1'b0
: 1'b1;
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = !ROM_ADDR0;
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
msu_enable ? 1'b0 :
bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
srtc_enable ? (SNES_READ & SNES_WRITE) :
snescmd_enable ? ((~snescmd_unlock | SNES_READ) & SNES_WRITE) :
bs_page_enable ? (SNES_READ) :
r213f_enable & !SNES_PARD ? 1'b0 :
snoop_4200_enable ? SNES_WRITE :
((IS_ROM & SNES_CS)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
|(SNES_READ & SNES_WRITE)
| bsx_tristate
);
assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & (r213f_enable)))
? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
: 1'b0;
assign SNES_IRQ = 1'b0;
assign p113_out = 1'b0;
wire [8:0] snescmd_addra = snoop_4200_enable ? 9'h1fa : SNES_ADDR[8:0];
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock & snescmd_enable) | snoop_4200_enable)), // input [0 : 0] wea
.addra(snescmd_addra), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
/*
wire [35:0] CONTROL0;
chipscope_icon icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
.TRIG3({bsx_data_ovr, r213f_forceread, r213f_enable, SNES_PARD, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(spi_byte_cnt[3:0])
);
/*
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
.TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
.TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
.TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(ST_MEM_DELAYr)
);
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BLACKBOX_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputisolatch (
Q ,
D ,
SLEEP_B
);
output Q ;
input D ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_TB_V
/**
* udp_dff$PS_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_ps_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
SET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 SET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 SET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 SET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 SET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 SET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN dut (.D(D), .SET(SET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_TB_V
|
module hex_to_seven_seg(B, SSEG_L);
input [3:0] B;
output [6:0] SSEG_L;
reg [6:0] SSEG_L;
// synthesis translate_off
`define SIMULATION_MODE
// synthesis translate_on
`ifdef SIMULATION_MODE
wire [3:0] BB;
assign BB = B;
`else
reg [3:0] BB;
SOFT u1(
.in(B[0]),
.out(BB[0])
);
SOFT u2(
.in(B[1]),
.out(BB[1])
);
SOFT u3(
.in(B[2]),
.out(BB[2])
);
SOFT u4(
.in(B[3]),
.out(BB[3])
);
`endif
always @ (BB)
begin
case (BB)
// segment order: GFEDCBA (active low)
4'h0 : SSEG_L = 7'b1000000;
4'h1 : SSEG_L = 7'b1111001;
4'h2 : SSEG_L = 7'b0100100;
4'h3 : SSEG_L = 7'b0110000;
4'h4 : SSEG_L = 7'b0011001;
4'h5 : SSEG_L = 7'b0010010;
4'h6 : SSEG_L = 7'b0000010;
4'h7 : SSEG_L = 7'b1111000;
4'h8 : SSEG_L = 7'b0000000;
4'h9 : SSEG_L = 7'b0010000;
4'hA : SSEG_L = 7'b0001000;
4'hB : SSEG_L = 7'b0000011;
4'hC : SSEG_L = 7'b1000110;
4'hD : SSEG_L = 7'b0100001;
4'hE : SSEG_L = 7'b0000110;
4'hF : SSEG_L = 7'b0001110;
default : SSEG_L = 7'b1111111;
endcase
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bios.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bios (
address,
clock,
q);
input [10:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./src/rom/BIOS.HEX",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./src/rom/BIOS.HEX"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./src/rom/BIOS.HEX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 11
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "system_auto_us_2,axi_dwidth_converter_v2_1_11_top,{}" *)
(* CORE_GENERATION_INFO = "system_auto_us_2,axi_dwidth_converter_v2_1_11_top,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACK\
ING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_us_2 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_11_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
`include "asserts.vh"
module tx_DS_SE_tb();
reg [11:0] story_tb;
reg TxClk, TxReset, Tx1, Tx0;
wire D_o, S_o;
`DEFIO(TxClk,1,0)
`DEFASSERT0(D,o)
`DEFASSERT0(S,o)
tx_DS_SE transmitter(
.TxClk(TxClk),
.TxReset(TxReset),
.Tx1(Tx1),
.Tx0(Tx0),
.D(D_o),
.S(S_o)
);
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
// R -> O -> O -> R
story_tb <= 12'h000;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h001;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h002;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h003;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> O -> O -> O
story_tb <= 12'h010;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h011;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h012;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h013;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
// R -> O -> O -> Z
story_tb <= 12'h020;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h021;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h022;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h023;
{Tx1, Tx0} = 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
// R -> Z -> O -> R
story_tb <= 12'h030;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h031;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h032;
{Tx0, Tx1} <= 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h033;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> Z -> O -> O
story_tb <= 12'h040;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h041;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h042;
{Tx0, Tx1} <= 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h043;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
// R -> Z -> O -> Z
story_tb <= 12'h050;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h051;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h052;
{Tx0, Tx1} = 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h053;
{Tx1, Tx0} = 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
// R -> Z -> R
story_tb <= 12'h060;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h061;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h062;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> Z -> Z
story_tb <= 12'h070;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h071;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h072;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> O -> R
story_tb <= 12'h080;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h081;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h082;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> O -> Z
story_tb <= 12'h090;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h091;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h092;
{Tx1, Tx0} <= 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
$display("@I Done.");
$stop;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc3_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc3_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
Require Import String.
Require Import bin_rels.
Require Import eq_rel.
Require Import universe.
Require Import LibTactics.
Require Import tactics.
Require Import Coq.Bool.Bool.
Require Import Coq.Program.Tactics.
Require Import Omega.
Require Import Coq.Program.Basics.
Require Import Coq.Lists.List.
Require Import Coq.Init.Notations.
Require Import UsefulTypes.
Require Import Coq.Classes.DecidableClass.
Require Import Coq.Classes.Morphisms.
Require Import list.
Require Import Recdef.
Require Import Eqdep_dec.
Require Import varInterface.
Require Import terms.
Open Scope list_scope.
(** printing # $\times$ #×# *)
(** printing <=> $\Leftrightarrow$ #⇔# *)
(** printing $ $\times$ #×# *)
(** printing & $\times$ #×# *)
(** Here are some handy definitions that will
reduce the verbosity of some of our later definitions
*)
Generalizable Variable Opid.
Section terms2Generic.
Context {NVar VarClass} {deqnvar : Deq NVar} {varcl freshv} {varclass: @VarType NVar VarClass deqnvar varcl freshv}
`{hdeq: Deq Opid} {gts : GenericTermSig Opid}.
Notation NTerm := (@NTerm NVar Opid).
Notation BTerm := (@BTerm NVar Opid).
Definition nobnd (f:NTerm) : BTerm := bterm [] f.
(** %\noindent \\*% We define similar abstractions for other [Opid]s.
This document does not show them. As mentioned before, one can click
at the hyperlinked filename that is closest above to open a
webpage that shows complete contents of this file.
*)
Lemma fold_nobnd :
forall t, bterm [] t = nobnd t.
Proof using.
unfold nobnd; auto.
Qed.
(*
Definition mk_esquash (R : NTerm) :=
oterm (Can NEsquash) [nobnd R].
*)
(* Picks a variable that is not in the set of free variables of a given term *)
Definition newvar (t : NTerm) := fresh_var (free_vars t).
(* Delete. use flat_map instead *)
Fixpoint free_vars_list (terms : list NTerm) :=
match terms with
| [] => []
| t :: ts => free_vars t ++ free_vars_list ts
end.
(* ------ SIMPLE OPERATORS ON TERMS ------ *)
(*
Fixpoint depth (t : NTerm) : nat :=
match t with
| vterm _ => 1
| oterm op bterms => lsum map depth_bterm bterms
end
with depth_bterm (lv : list NVar) (nt : NTerm) :=
match bt with
| bterm lv nt => depth nt
end.
*)
End terms2Generic.
Fixpoint size {NVar:Type} {Opid:Type} (t : @NTerm NVar Opid) : nat :=
match t with
| vterm _ => 1
| oterm op bterms => S (addl (map (@size_bterm NVar _) bterms))
end
with size_bterm {NVar:Type} {Opid:Type} (bt: @BTerm NVar Opid) :nat :=
match bt with
| bterm lv nt => @size NVar Opid nt
end.
Fixpoint wft {NVar:Type} {Opid:Type} {gts : GenericTermSig Opid} (t : @NTerm NVar Opid) : bool :=
match t with
| vterm _ => true
| oterm o bts =>
andb (beq_list deq_nat (map (@num_bvars NVar _) bts) (OpBindings o))
(ball (map wftb bts))
end
with wftb {NVar:Type} {Opid:Type} {gts : GenericTermSig Opid} (bt : @BTerm NVar Opid) : bool :=
match bt with
| bterm vars t => wft t
end.
Scheme Equality for list.
Fixpoint NTerm_beq {NVar:Type} {Opid:Type} `{Deq NVar} `{Deq Opid}
(t1 t2: @NTerm NVar Opid) : bool :=
match (t1, t2) with
| (terms.vterm v1, terms.vterm v2) => decide (v1=v2)
| (terms.oterm o1 lbt1, terms.oterm o2 lbt2)
=> andb (decide (o1=o2)) (list_beq _ (@BTerm_beq NVar Opid _ _) lbt1 lbt2)
|(_,_)=> false
end
with BTerm_beq {NVar:Type} {Opid:Type} `{Deq NVar} `{Deq Opid} (t1 t2:
@BTerm NVar Opid) : bool :=
match (t1, t2) with
| (terms.bterm lv1 t1, terms.bterm lv2 t2) =>
andb (decide (lv1=lv2)) (@NTerm_beq NVar Opid _ _ t1 t2)
end.
(*
Lemma NTerm_beq_correct {NVar:Type} {Opid:Type} `{Deq NVar} `{Deq Opid}
(a b: @terms.NTerm NVar Opid): NTerm_beq a b = true <=> a = b.
Admitted.
*)
Section terms3Generic.
Context {NVar VarClass} {deqnvar : Deq NVar}
{varcl freshv} {varclass: @VarType NVar VarClass deqnvar varcl freshv}
`{hdeq: Deq Opid} {gts : GenericTermSig Opid}.
Notation NTerm := (@NTerm NVar Opid).
Notation BTerm := (@BTerm NVar Opid).
(* ------ INDUCTION ON TERMS ------ *)
Lemma size_subterm2 :
forall (o:Opid) (lb : list BTerm) (b : BTerm) ,
LIn b lb
-> size_bterm b < size (oterm o lb).
Proof using.
simpl. induction lb; intros ? Hin; inverts Hin as; simpl; try omega.
intros Hin. apply IHlb in Hin; omega.
Qed.
Lemma size_subterm3 :
forall (o:Opid) (lb : list BTerm) (nt : NTerm) (lv : list NVar) ,
LIn (bterm lv nt) lb
-> size nt < size (oterm o lb).
Proof using.
introv X.
apply size_subterm2 with (o:=o) in X. auto.
Qed.
Lemma NTerm_better_ind3 :
forall P : NTerm -> Type,
(forall n : NVar, P (vterm n))
-> (forall (o : Opid) (lbt : list BTerm),
(forall (nt: NTerm),
size nt < size (oterm o lbt)
-> P nt
)
-> P (oterm o lbt)
)
-> forall t : NTerm, P t.
Proof using.
intros P Hvar Hbt.
assert (forall n t, size t = n -> P t) as Hass.
Focus 2. intros. apply Hass with (n := size t) ; eauto; fail.
induction n as [n Hind] using comp_ind_type.
intros t Hsz.
destruct t.
apply Hvar.
apply Hbt. introv Hs.
apply Hind with (m := size nt) ; auto.
subst.
assert(size nt < size (oterm o l)); auto.
Qed.
Lemma NTerm_better_ind2 :
forall P : NTerm -> Type,
(forall n : NVar, P (vterm n))
-> (forall (o : Opid) (lbt : list BTerm),
(forall (nt nt': NTerm) (lv: list NVar),
(LIn (bterm lv nt) lbt)
-> size nt' <= size nt
-> P nt'
)
-> P (oterm o lbt)
)
-> forall t : NTerm, P t.
Proof using.
intros P Hvar Hbt.
apply NTerm_better_ind3; eauto.
intros ? ? H.
apply Hbt.
intros ? ? ? Hin Hs. apply H.
eapply le_lt_trans;[apply Hs|].
eapply size_subterm3; eauto.
Qed.
Lemma NTerm_BTerm_ind :
forall (PN : NTerm -> Type) (PB : BTerm -> Type),
(forall n : NVar, PN (vterm n))
-> (forall (o : Opid) (lbt : list BTerm),
(forall b,
(LIn b lbt) -> PB b
)
-> PN (oterm o lbt)
)
-> (forall (lv: list NVar) (nt : NTerm),
PN nt -> PB (bterm lv nt)
)
-> ((forall t : NTerm, PN t) * (forall t : BTerm, PB t)).
Proof using.
introv Hv Hind Hb.
assert (forall A B, A -> (A -> B) -> (A*B)) as H by tauto.
apply H; clear H.
- apply NTerm_better_ind2; auto.
introv Hx. apply Hind. introv Hin. destruct b. eauto.
- intro Hnt. intro b. destruct b. eauto.
Qed.
Lemma NTerm_better_ind :
forall P : NTerm -> Type,
(forall n : NVar, P (vterm n))
-> (forall (o : Opid) (lbt : list BTerm),
(forall (nt : NTerm) (lv: list NVar),
(LIn (bterm lv nt) lbt) -> P nt
)
-> P (oterm o lbt)
)
-> forall t : NTerm, P t.
Proof using.
introv Hv Hind. apply NTerm_better_ind2; auto.
introv Hx. apply Hind. introv Hin. eapply Hx in Hin; eauto.
Qed.
Tactic Notation "nterm_ind" ident(h) ident(c) :=
induction h using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind1" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind1s" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind2;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Lemma num_bvars_on_bterm :
forall (l:list NVar) (n : NTerm),
num_bvars (@bterm NVar Opid l n) = length l.
Proof using.
unfold num_bvars; simpl; sp.
Qed.
Definition wf_term (t : NTerm) := wft t = true.
Definition wf_bterm (bt : BTerm) := wftb bt = true.
Lemma wf_term_proof_irrelevance :
forall t,
forall x y : wf_term t,
x = y.
Proof using.
intros.
apply UIP_dec.
apply bool_dec.
Qed.
Definition wf_term_extract :=
fun (t : NTerm) (x : wf_term t) =>
match x return (x = match x with
| eq_refl => eq_refl (wft t)
end)
with
| eq_refl => eq_refl eq_refl
end.
(*
Definition wf_term_extract1 :=
fun (t : NTerm) (x : wf_term t) =>
match x in _ = b return match b with
| true => x = eq_refl (wft t)
end
with
| eq_refl => eq_refl eq_refl
end.
Lemma wf_term_extract2 :
forall t : NTerm,
forall x : wf_term t,
x = eq_refl (wft t).
*)
(*Lemma yyy : forall A (x : A) (pf : x = x), pf = eq_refl x.
Lemma xxx : forall t (x : wft t = true), x = eq_refl (wft t).*)
Lemma nt_wf_eq :
forall t,
nt_wf t <=> wf_term t.
Proof using.
clear varclass varcl freshv deqnvar VarClass.
unfold wf_term.
nterm_ind t as [|o lbt ind] Case; simpl; intros.
- Case "vterm".
split; sp.
- Case "oterm".
split_iff SCase.
+ SCase "->"; intro w.
inversion w; subst.
allrw.
rewrite beq_list_refl; simpl.
trw ball_true; sp.
alltrewrite in_map_iff; sp; subst.
apply_in_hyp wf; destruct wf; allsimpl.
discover; sp. firstorder.
+ SCase "<-"; sp.
remember (beq_list deq_nat (map num_bvars lbt) (OpBindings o)).
destruct b; allsimpl; sp.
alltrewrite ball_true.
constructor; sp.
destruct l.
apply_in_hyp e.
constructor.
apply e.
apply_hyp.
alltrewrite in_map_iff.
exists (bterm l n); simpl; sp.
remember (OpBindings o).
clear Heql.
revert l Heqb.
Local Opaque deq_nat.
induction lbt; allsimpl.
destruct l; allsimpl; sp.
destruct l; allsimpl; sp.
rewrite decide_decideP in Heqb.
destruct (decideP (num_bvars a = n)); subst; sp.
apply cons_eq.
apply IHlbt; sp.
apply ind with (lv := lv); sp.
Qed.
Lemma nt_wf_implies :
forall t, nt_wf t -> wf_term t.
Proof using.
sp; apply nt_wf_eq; sp.
Qed.
Lemma wf_term_eq :
forall t, wf_term t <=> nt_wf t.
Proof using.
intro; generalize (nt_wf_eq t); sp.
symm; auto.
Qed.
Lemma bt_wf_eq :
forall bt, bt_wf bt <=> wf_bterm bt.
Proof using.
sp; split; intro w.
inversion w; subst; unfold wf_bterm; simpl.
fold (wf_term nt).
apply wf_term_eq; auto.
destruct bt; allunfold wf_bterm; allsimpl.
fold (wf_term n) in w.
constructor.
apply nt_wf_eq; auto.
Qed.
(*
Inductive nt_wfb (t:NTerm) : bool :=
match t with
| vterm _ => true
| bterm _ rt => nt_wfb rt
| oterm o lnt : (eq map (num_bvars) lnt OpBindings o).
*)
Definition closedb (t : NTerm) := nullb (free_vars(t)).
Definition closed_bt (bt : BTerm) := free_vars_bterm bt = [].
Definition isprogram_bt (bt : BTerm) := closed_bt bt # bt_wf bt.
(** Our definition [isprog] below is is logically equivalent to [isprogram],
but unlike [isprogram], it is easy to prove that
for any [t], all members(proofs) of [isprog t] are equal.
An interested reader can look at the lemma
%\coqexternalref{UIP\_dec}
{http://coq.inria.fr/distrib/8.4pl2/stdlib/Coq.Logic.Eqdep\_dec}
{\coqdocdefinition{UIP\_dec}}% from that standard library.
As mentioned before, clicking on the lemma name in
the previous sentence should open
the corresponding webpage of the Coq standard library.
Instead, one can also look at the lemma [isprog_eq] below and
safely ignore these technicalites.
*)
Definition isprog (t : NTerm) := (nullb (free_vars t) && wft t) = true.
Definition isprog_bt (bt : BTerm) :=
(nullb (free_vars_bterm bt) && wftb bt) = true.
Definition isprog_vars (vs : list NVar) (t : NTerm) :=
(sub_vars (free_vars t) vs && wft t) = true.
Lemma closed_nt :
forall op bts,
closed (oterm op bts)
<=>
forall bt, LIn bt bts -> closed_bt bt.
Proof using.
sp; unfold closed, closed_bt; simpl; trw flat_map_empty; split; sp.
Qed.
Lemma closed_nt0 : forall o (nt:NTerm), closed (oterm o [bterm [] nt]) -> closed nt.
Proof using.
intros. unfold closed in H. simpl in H. apply app_eq_nil in H. repnd.
clears_last. unfold closed. assumption.
Qed.
Lemma closed_null_free_vars :
forall (t:NTerm),
closed t <=> null (free_vars t).
Proof using.
unfold closed; sp.
trw null_iff_nil; sp.
Qed.
Lemma isprog_proof_irrelevance :
forall t,
forall x y : isprog t,
x = y.
Proof using.
intros.
apply UIP_dec.
apply bool_dec.
Qed.
Lemma isprog_vars_proof_irrelevance :
forall t vs,
forall x y : isprog_vars vs t,
x = y.
Proof using.
intros.
apply UIP_dec.
apply bool_dec.
Qed.
Require Import tactics.
Lemma isprogram_eq :
forall t,
isprogram t <=> isprog t.
Proof using.
unfold isprog, isprogram.
nterm_ind t Case; simpl; intros.
- Case "vterm".
split; sp. unfold closed in *; allsimpl; sp.
- Case "oterm".
split_iff SCase.
+ SCase "->".
intros i; destruct i as [ cl wf ].
inversion cl; subst.
inversion wf; subst.
repeat (rw andb_eq_true).
rewrite fold_assert.
allrw <- null_iff_nil.
rw ball_map_true.
rw assert_nullb; sp.
rewrite fold_assert.
rw assert_beq_list; auto.
destruct x; allsimpl.
fold (wf_term n).
apply wf_term_eq.
apply_in_hyp p; inversion p; subst; sp.
+ SCase "<-"; intros.
repeat (allrewrite andb_true); repd.
allrw fold_assert.
allrw assert_nullb.
allrw null_iff_nil.
allrw assert_beq_list.
allrw ball_map_true; sp.
constructor; sp.
apply_in_hyp p.
destruct l; allsimpl.
constructor.
allfold (wf_term n).
apply wf_term_eq; auto.
Qed.
Lemma isprogram_implies :
forall t, isprogram t -> isprog t.
Proof using.
sp; apply isprogram_eq; sp.
Qed.
Lemma isprog_implies :
forall t : NTerm, isprog t -> isprogram t.
Proof using.
sp; apply isprogram_eq; sp.
Qed.
Lemma isprog_eq :
forall t, isprog t <=> isprogram t.
Proof using.
intro; symm; apply isprogram_eq; auto.
Qed.
Lemma isprogram_bt_eq :
forall bt,
isprogram_bt bt <=> isprog_bt bt.
Proof using.
intro; unfold isprogram_bt, isprog_bt, closed_bt; split; sp.
allrw; simpl.
fold (wf_bterm bt).
apply bt_wf_eq; auto.
alltrewrite andb_eq_true; sp.
allrewrite fold_assert.
alltrewrite assert_nullb.
alltrewrite null_iff_nil; sp.
destruct bt; constructor.
alltrewrite andb_eq_true; sp; allsimpl.
allfold (wf_term n).
apply nt_wf_eq; auto.
Qed.
Lemma isprog_vars_eq :
forall t vs,
isprog_vars vs t <=> subsetv (free_vars t) vs # nt_wf t.
Proof.
unfold isprog_vars; sp.
rw andb_eq_true.
rewrite fold_assert.
rewrite assert_sub_vars.
rw nt_wf_eq; sp.
Qed.
Lemma isprog_vars_if_isprog :
forall vs t, isprog t -> isprog_vars vs t.
Proof using.
introv ip.
rw isprog_vars_eq.
rw isprog_eq in ip.
destruct ip; sp.
unfold closed in *; allrw; sp.
Qed.
Lemma isprog_vars_app_l :
forall t vs1 vs2,
isprog_vars vs2 t
-> isprog_vars (vs1 ++ vs2) t.
Proof using.
sp; alltrewrite isprog_vars_eq; sp.
unfold subset in *.
apply subset_app_l; sp.
Qed.
Definition areprograms ts := forall t, LIn t ts -> isprogram t.
Lemma areprograms_nil : areprograms [].
Proof using.
unfold areprograms; simpl; sp.
Qed.
Lemma areprograms_snoc :
forall t ts,
areprograms (snoc ts t) <=> areprograms ts # isprogram t.
Proof using.
unfold areprograms; sp; split; sp; try (apply_hyp; rw in_snoc; sp).
alltrewrite in_snoc; sp; subst; sp.
Qed.
Lemma areprograms_cons :
forall t ts, areprograms (t :: ts) <=> isprogram t # areprograms ts.
Proof using.
unfold areprograms; sp; simpl; split; sp; subst; sp.
Qed.
Lemma areprograms_app :
forall ts1 ts2,
areprograms (ts1 ++ ts2) <=> areprograms ts1 # areprograms ts2.
Proof using.
unfold areprograms; sp; split; sp.
apply_hyp; rw in_app_iff; sp.
apply_hyp; rw in_app_iff; sp.
alltrewrite in_app_iff; sp.
Qed.
Lemma isprogram_vterm :
forall v, isprogram (vterm v) <=> False.
Proof using.
unfold isprogram, closed; simpl; sp; split; sp.
Qed.
(*
Ltac repnd :=
repeat match goal with
| [ H : _ # _ |- _ ] =>
let name := fresh H in destruct H as [name H]
| [ H : _ # _ |- _ ] =>
let name := fresh H in destruct H as [name H]
end.
*)
Theorem isprogram_ot_iff :
forall o bts,
isprogram (oterm o bts)
<=>
(map num_bvars bts = OpBindings o
# forall bt, LIn bt bts -> isprogram_bt bt).
Proof using.
intros. sp_iff Case.
- Case "->".
intros Hisp.
unfold isprogram in Hisp. repnd.
inverts Hisp0 as Hflat. inverts Hisp.
split;auto. intros bt Hin.
unfold isprogram_bt.
rw flat_map_empty in Hflat.
apply_in_hyp p; sp.
- Case "<-".
intros eq; destruct eq as [Hmap Hstclose].
unfold isprogram, closed.
split; try (constructor); auto;
try (simpl; apply flat_map_empty);
intros a ain;
apply Hstclose in ain; inversion ain; sp.
Qed.
Theorem nt_wf_ot_implies :
forall lv o (nt1 : NTerm) bts,
nt_wf (oterm o bts)
-> LIn (bterm lv nt1) bts
-> nt_wf nt1.
Proof using. intros ? ? ? ? Hwf Hin. inverts Hwf as Hwf Hmap.
assert (bt_wf (bterm lv nt1)) as Hbf by (apply Hwf; auto).
inverts Hbf. auto.
Qed.
Lemma newvar_prop :
forall (t: NTerm), ! LIn (newvar t) (free_vars t).
Proof using.
unfold newvar; sp.
allapply fresh_var_not_in; sp.
Qed.
(*
Lemma newvar_not_in_free_vars :
forall (t: NTerm),
! LIn nvarx (free_vars t)
-> newvar t = nvarx.
Proof using.
sp.
unfold newvar.
apply fresh_var_nvarx; sp.
Qed.
Lemma newvar_prog :
forall t,
isprog t
-> newvar t = nvarx.
Proof using.
sp.
unfold newvar.
apply isprog_eq in H.
inversion H.
unfold closed in H0.
rewrite H0; sp.
Qed.
*)
(*
(** A value is a program with a canonical operator *)
Inductive isvalue : NTerm -> [univ] :=
| isvl : forall (c : CanonicalOp) (bts : list BTerm ),
isprogram (oterm (Can c) bts)
-> isvalue (oterm (Can c) bts).
Inductive isovalue : NTerm -> Prop :=
| isovl : forall (c : CanonicalOp) (bts : list BTerm),
nt_wf (oterm (Can c) bts)
-> isovalue (oterm (Can c) bts).
Lemma isvalue_closed :
forall t, isvalue t -> closed t.
Proof using.
introv isv; inversion isv.
allunfold isprogram; sp.
unfold isprogram in *.
tauto.
Qed.
Lemma isvalue_program :
forall t, isvalue t -> isprogram t.
Proof using.
introv isv; inversion isv; sp.
Qed.
*)
(* ------ programs ------ *)
Definition WTerm := { t : NTerm | wf_term t }.
Definition WBTerm := { bt : BTerm | wf_bterm bt }.
(*
(* first of all, isprog is NOT a boolean. also, the reader will
be left wondering what UIP_dec is*)
where [isprog] is the Boolean version of [isprogram]
(using a Boolean version of [isprogram] makes it easy to prove that
closed terms are equal by proving that the underlying [NTerm]s are
equals using [UIP_dec]).
*)
(**
The [CTerm] type below is useful in compactly stating definitions
that are only meaningful for closed terms. A [CTerm] is a pair
of an [NTerm] [t] and a proof that [t] is closed.
This [CTerm] type will be handy in compactly
defining the Nuprl type system where types are defined as partial
equivalence relations on closed terms.
*)
Definition CTerm := { t : NTerm | isprog t }.
Definition get_cterm (t : CTerm) := let (a,_) := t in a.
Definition BCTerm := { bt : BTerm | isprog_bt bt }.
(**
We also define a type of terms that specifies what are the possible
free variables of its inhabitants. A term is a [(CVTerm vs)] term
if the set of its free variables is a subset of [vs]. This type is
also useful to define the Nuprl type system. For example, to define
a closed family of types such as a closed function type of the form
$\NUPRLfunction{x}{A}{\NUPRLsuba{B}{z}{x}}$, $A$ has to be closed
and the free variables of $B$ can only be $z$.
*)
Definition CVTerm (vs : list NVar) := { t : NTerm | isprog_vars vs t }.
Definition CVTerm3 := forall a b c, CVTerm [a;b;c].
Definition mk_cvterm (vs : list NVar) (t : NTerm) (p : isprog_vars vs t) :=
exist (isprog_vars vs) t p.
Definition get_wterm (t : WTerm) := let (a,_) := t in a.
Definition get_cvterm (vs : list NVar) (t : CVTerm vs) := let (a,_) := t in a.
Definition get_bcterm (bt : BCTerm) := let (a,_) := bt in a.
Definition selectbt (bts: list BTerm) (n:nat) : BTerm :=
nth n bts (bterm [] (vterm nvarx)).
(*
Definition isnoncan (t: NTerm):=
match t with
| vterm _ => False
| oterm o _ => match o with
| Can _ => False
| NCan _ => True
end
end.
*)
Lemma wf_cterm :
forall t, wf_term (get_cterm t).
Proof.
introv; ( repeat match goal with
| [ H : CTerm |- _ ] => destruct H
| [ H : CVTerm _ |- _ ] => destruct H
end
); simpl.
allrw isprog_eq; unfold isprogram in *; repnd; allrw nt_wf_eq; sp.
Qed.
End terms3Generic.
Ltac irr_step :=
match goal with
| [ H1 : isprog ?a, H2 : isprog ?a |- _ ] =>
assert (H2 = H1) by apply isprog_proof_irrelevance; subst
| [ H1 : isprog_vars ?vs ?a, H2 : isprog_vars ?vs ?a |- _ ] =>
assert (H2 = H1) by apply isprog_vars_proof_irrelevance; subst
end.
Ltac irr := repeat irr_step.
Ltac destruct_cterms :=
repeat match goal with
| [ H : CTerm |- _ ] => destruct H
| [ H : CVTerm _ |- _ ] => destruct H
end.
Ltac dest_cterm H :=
let t := type of H in
match goal with
| [ x : CTerm |- _ ] =>
match t with
| context[x] => destruct x
end
| [ x : CVTerm _ |- _ ] =>
match t with
| context[x] => destruct x
end
end.
(** A faster version of destruct_cterms. We avoid destructing all of them. *)
Ltac dest_cterms H := repeat (dest_cterm H).
Ltac clear_deps h :=
repeat match goal with
| [ H : context[h] |- _ ] => clear H
end.
Tactic Notation "nterm_ind" ident(h) ident(c) :=
induction h using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind1" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind1s" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind2;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Ltac fold_terms_step :=
match goal with
| [ |- context[bterm [] ?x] ] => fold (nobnd x)
| [ |- context[vterm ?v] ] => fold (mk_var v)
end.
Ltac fold_terms := repeat fold_terms_step.
Ltac boolvar_step :=
match goal with
| [ |- context[beq_var ?v ?v] ] => rw <- beq_var_refl
| [ |- context[memvar ?v ?s] ] =>
let name := fresh "b" in
remember (memvar v s) as name;
match goal with
| [ H : name = memvar v s |- _ ] =>
symmetry in H;
destruct name;
[ rewrite fold_assert in H;
trw_h assert_memvar H;
simpl in H
| trw_h not_of_assert H;
trw_h assert_memvar H;
simpl in H
]
end
| [ |- context[beq_var ?v1 ?v2] ] =>
let name := fresh "b" in
remember (beq_var v1 v2) as name;
match goal with
| [ H : name = beq_var v1 v2 |- _ ] =>
destruct name;
[ apply beq_var_true in H; subst
| apply beq_var_false in H
]
end
| [ H : context[beq_var ?v ?v] |- _ ] => rw <- beq_var_refl in H
end.
Ltac boolvar := repeat boolvar_step.
Ltac unfold_all_mk :=
allunfold mk_var
;allunfold nobnd.
Hint Immediate wf_cterm : wf.
(* Hint Constructors isvalue. *)
Hint Constructors nt_wf bt_wf.
Ltac rwselectbt :=
match goal with
|[ H1: bterm ?lv ?nt = selectbt ?lbt ?n , H2 : context [selectbt ?lbt ?n] |- _ ] => rewrite <- H1 in H2
|[ H1: selectbt ?lbt ?n = bterm ?lv ?nt , H2 : context [selectbt ?lbt ?n] |- _ ] => rewrite H1 in H2
|[ H1: bterm ?lv ?nt = selectbt ?lbt ?n |- context [selectbt ?lbt ?n] ] => rewrite <- H1
|[ H1: selectbt ?lbt ?n = bterm ?lv ?nt |- context [selectbt ?lbt ?n] ] => rewrite H1
end.
Tactic Notation "ntermd" ident(h) "as" simple_intropattern(I) ident(c) :=
destruct h as I;
[ Case_aux c "vterm"
| Case_aux c "oterm"
].
Ltac prove_or :=
try (left;cpx;fail);
try (right;cpx;fail);
try (left;left;cpx;fail);
try (left;right;cpx;fail);
try (right;left;cpx;fail);
try (right;right;cpx;fail).
Ltac fold_selectbt :=
match goal with
[ |- context [nth ?n ?lbt (bterm [] (vterm nvarx))] ] =>
fold (selectbt lbt n)
end.
(*
Ltac d_isnoncan H :=
match type of H with
isnoncan ?t => let tlbt := fresh t "lbt" in let tnc := fresh t "nc" in
let tt := fresh "temp" in
destruct t as [tt|tt tlbt];[inverts H as H; fail|];
destruct tt as [tt|tnc]; [inverts H as H; fail|]
end.
*)
Section terms4Generic.
Context {NVar VarClass} {deqnvar : Deq NVar} {varcl freshv}
{varclass: @VarType NVar VarClass deqnvar varcl freshv}
`{hdeq : Deq Opid} {gts : GenericTermSig Opid}.
Notation NTerm := (@NTerm NVar Opid).
Notation BTerm := (@BTerm NVar Opid).
Lemma cterm_eq :
forall t u,
get_cterm t = get_cterm u
-> t = u.
Proof using.
introv; destruct_cterms; simpl; sp; subst.
rewrite dep_pair_eq
with (eq0 := eq_refl)
(pb := i); auto.
apply UIP_dec.
apply bool_dec.
Qed.
Lemma cvterm_eq :
forall vs t u,
get_cvterm vs t = get_cvterm vs u
-> t = u.
Proof using.
introv; destruct_cterms; simpl; sp; subst.
rewrite dep_pair_eq
with (eq0 := eq_refl)
(pb := i); auto.
apply UIP_dec.
apply bool_dec.
Qed.
Lemma free_vars_cterm :
forall t, free_vars (get_cterm t) = [].
Proof using.
introv; destruct_cterms; simpl.
allrw isprog_eq; unfold isprogram in *; repnd; allrw; sp.
Qed.
Definition mk_cterm (t : NTerm) (p : isprogram t) :=
exist isprog t (isprogram_implies t p).
Definition mk_ct (t : NTerm) (p : isprog t) := exist isprog t p.
Definition mk_wterm (t : NTerm) (p : wf_term t) := exist (@wf_term NVar _ _) t p.
Definition mk_wterm' (t : NTerm) (p : nt_wf t) :=
exist wf_term t (nt_wf_implies t p).
(* Definition iscvalue (t : CTerm) : Type :=
isvalue (get_cterm t).
*)
Lemma mk_cv_pf :
forall (vs : list NVar) (t:CTerm),
@isprog_vars NVar _ Opid _ vs (@get_cterm NVar _ Opid _ t).
Proof.
destruct t; simpl.
rw @isprog_eq in i; destruct i.
rw @isprog_vars_eq; simpl; sp.
unfold closed in *.
allrw; sp.
Qed.
(** From a closed term, we can always make a term whose variables
* are contained in vs: *)
Definition mk_cv (vs : list NVar) (t : @CTerm NVar _ Opid _) : @CVTerm NVar _ Opid _ vs :=
exist (isprog_vars vs) (@get_cterm NVar _ Opid _ t) (mk_cv_pf vs t).
Lemma programs_bt_to_program :
forall bts : list BCTerm,
forall op,
map (fun bt => num_bvars (get_bcterm bt)) bts = OpBindings op
-> isprogram (oterm op (map get_bcterm bts)).
Proof using.
sp; unfold isprogram; sp.
rewrite closed_nt in *; sp.
allrw in_map_iff; sp; subst.
destruct a; destruct x; allsimpl.
clear_deps i.
rw <- @isprogram_bt_eq in i.
inversion i; sp.
constructor; sp.
allrw in_map_iff; sp; subst.
destruct a; destruct x; allsimpl.
clear_deps i.
rw <- @isprogram_bt_eq in i.
inversion i; sp.
rewrite <- H.
rewrite map_map; unfold compose; sp.
Qed.
(* ---------------------------------------------------- *)
Definition list_rel {A} {B} (R : A -> B -> Prop) (ll : list A) (lr : list B) :=
(length ll = length lr)
#
forall p1 p2 , LIn (p1, p2) (combine ll lr)
-> R p1 p2.
(** gets the nth element of a list of bterms. if n is out of range, it returns the variable x
*)
(* Howe defines T(L) as B_0(L) (no bterm constructor)
and T_0(L) as closed terms of T(L)
so, a term T_0(L) cannot have the vterm constructor
at the root
This a superset of T_0(L)
*)
Inductive not_vbterm: NTerm -> Type :=
| nvbo : forall (op : Opid) (bts : list BTerm ),
not_vbterm (oterm op bts).
(** this should not be required anymore. a closed NTerm is automatically not_vbterm. Proof below*)
Definition not_vbtermb (t : NTerm) : bool :=
match t with
| oterm _ _ => true
| _ => false
end.
Theorem closed_notvb : forall t: NTerm , (closed t) -> (not_vbterm t).
Proof using.
intros ? Hclose. destruct t.
unfold closed in Hclose. simpl in Hclose.
inversion Hclose. constructor.
Qed.
Theorem selectbt_in :
forall n (bts : list BTerm),
n < length bts -> LIn (selectbt bts n) bts.
Proof using.
intros. unfold selectbt.
apply nth_in; auto.
Qed.
Lemma selectbt_cons :
forall bt (bts : list BTerm) n,
selectbt (bt :: bts) n = if beq_nat n 0 then bt else selectbt bts (n - 1).
Proof using.
unfold selectbt; simpl; sp.
destruct n; simpl; sp.
destruct n; simpl; sp.
Qed.
(* Lemma isvalue_wf :
forall c bts,
isvalue (oterm (Can c) bts)
-> map num_bvars bts = OpBindings (Can c).
Proof using. intros ? ? Hval.
inverts Hval as Hpr. inverts Hpr as Hclose Hwf.
inverts Hwf; auto.
Qed.
*)
(* Lemma isvalue_wf2: forall c bts,
(isvalue (oterm (Can c) bts))
-> length bts= length(OpBindings (Can c)).
Proof using. intros ? ? Hval. apply isvalue_wf in Hval.
(* fequalhyp H length. why does this fail*)
assert (length (map num_bvars bts) = length (OpBindings (Can c)))
as Hlen by (rewrite Hval; reflexivity) .
rewrite map_length in Hlen. auto.
Qed.
*)
Notation bterm := (@bterm NVar Opid).
Lemma isprogram_wf3: forall o bts,
(isprogram (oterm o bts))
-> forall n, (n<length bts) -> (num_bvars (selectbt bts n))= nth n (OpBindings o) 0.
Proof using. intros ? ? Hprog. apply isprogram_ot_iff in Hprog. repnd.
intros ? Hlt.
assert(nth n (map num_bvars bts) 0= nth n (OpBindings o) 0)
as Hnth by (rewrite Hprog0; reflexivity).
unfold selectbt.
instlemma (@map_nth BTerm nat num_bvars
bts (bterm [] (vterm nvarx))) as Hmapn.
assert((num_bvars (bterm [] (vterm nvarx))) =0).
compute; auto . rewrite H in Hmapn. rewrite Hmapn in Hnth. auto.
Qed.
(* Lemma isvalue_wf3: forall o bts,
(isvalue (oterm o bts))
-> forall n, (n<length bts) -> (num_bvars (selectbt bts n))= nth n (OpBindings o) 0.
Proof using. intros ? ? Hval ? Hlt.
inverts Hval as Hprog. apply isprogram_wf3 with (n:=n) in Hprog ; auto.
Qed. *)
Theorem var_not_prog : forall v, (isprogram (vterm v)) -> void.
Proof using.
unfold not. intros v Hpr.
inversion Hpr as [Hclose ?].
unfold closed in Hclose. simpl in Hclose. inversion Hclose.
Qed.
Lemma implies_isprogram_bt :
forall bts,
(forall l : BTerm, LIn l bts -> bt_wf l)
-> flat_map free_vars_bterm bts = []
-> forall bt : BTerm, LIn bt bts -> isprogram_bt bt.
Proof using.
intros bts Hbf Hflat ? Hin.
unfold isprogram_bt, closed_bt; split; auto.
rw flat_map_empty in Hflat. apply Hflat; auto.
Qed.
Theorem ntbf_wf :
forall (nt : NTerm) , (bt_wf (bterm [] nt)) -> nt_wf nt.
Proof using.
introv Hin. inverts Hin. auto.
Qed.
Lemma implies_isprogram_bt0 :
forall t ,
isprogram (t)
-> isprogram_bt (bterm [] t).
Proof using.
unfold isprogram_bt, closed_bt, isprogram, closed; simpl; sp.
Qed.
Theorem is_program_ot_bts0 :
forall o nt,
isprogram nt
-> OpBindings o = [0]
-> isprogram (oterm o [bterm [] nt]).
Proof using.
introv Hpr Hop. unfold isprogram, closed in *; simpl; repnd.
split;auto. autorewrite with list. auto.
constructor; sp; allsimpl; sp; subst; sp.
Qed.
Theorem is_program_ot_nth_nobnd :
forall o nt1 bts,
isprogram (oterm o bts)
-> LIn (bterm [] nt1) bts
-> isprogram nt1.
Proof using. intros ? ? ? Hisp Hin. apply isprogram_ot_iff in Hisp. repnd.
apply Hisp in Hin. inverts Hin as Hclose Hbf. inverts Hbf.
unfold closed_bt in Hclose. simpl in Hclose.
split; auto.
Qed.
Theorem is_program_ot_fst_nobnd :
forall o nt1 bts,
isprogram (oterm o ((bterm [] nt1):: bts))
-> isprogram nt1.
Proof using.
intros ? ? ? Hisp.
apply is_program_ot_nth_nobnd with (nt1:=nt1) in Hisp; sp.
Qed.
Theorem is_program_ot_snd_nobnd :
forall o bt1 nt2 bts, isprogram (oterm o ((bt1)::(bterm [] nt2):: bts))
-> isprogram nt2.
Proof using. intros ? ? ? ? Hisp.
apply is_program_ot_nth_nobnd with (nt1:=nt2) in Hisp; simpl; sp.
Qed.
Theorem is_program_ot_subst1 :
forall o nt1 bts nt1r,
isprogram (oterm o ((bterm [] nt1):: bts))
-> isprogram nt1r
-> isprogram (oterm o ((bterm [] nt1r):: bts)).
Proof using. intros ? ? ? ? Hisp Hispst. unfold isprogram.
unfold closed. simpl.
inverts Hisp as Hclos Hisp. unfold closed in Hclos. simpl in Hclos.
apply app_eq_nil in Hclos. repnd.
inverts Hispst as Hclosst Hispst. unfold closed in Hclosst.
rewrite Hclosst. rewrite Hclos. split;auto.
invertsn Hisp. constructor;auto.
intros ? Hin. inverts Hin. constructor; auto.
apply Hisp. right; auto.
Qed.
Theorem is_program_ot_subst2 :
forall o bt1 nt2 bts nt2r,
isprogram (oterm o (bt1::(bterm [] nt2):: bts))
-> isprogram nt2r
-> isprogram (oterm o (bt1::(bterm [] nt2r):: bts)).
Proof using. intros ? ? ? ? ? Hisp Hispst. unfold isprogram.
unfold closed. simpl.
inverts Hisp as Hclos Hisp. inverts Hispst as Hclosst Hwfst.
unfold closed in *. simpl.
unfold closed in Hclos. allsimpl.
simpl_vlist. rewrite Hclosst. rewrite Hclos0.
simpl. split;auto.
inverts Hisp as Hisp Hm. constructor;simpl; auto.
intros ? Hin. dorn Hin;subst;auto. apply Hisp; auto.
left; auto.
dorn Hin; subst; auto.
apply Hisp. right;right;auto.
Qed.
Theorem is_program_ot_nth_wf :
forall lv o nt1 bts,
isprogram (oterm o bts)
-> LIn (bterm lv nt1) bts
-> nt_wf nt1.
Proof using. intros ? ? ? ? Hisp Hin. apply isprogram_ot_iff in Hisp. repnd.
assert (isprogram_bt (bterm lv nt1)) as Hass by (apply Hisp; auto).
inverts Hass as Hass Hbt. inversion Hbt; auto.
Qed.
Lemma combine_vars_map_sp :
forall vars,
combine vars (map (@vterm NVar Opid) vars) = map (fun v => (v, vterm v)) vars.
Proof using.
induction vars; simpl; sp.
rewrite IHvars; sp.
Qed.
Lemma combine_vars_map :
forall A,
forall f : NVar -> A,
forall vars,
combine vars (map f vars) = map (fun v => (v, f v)) vars.
Proof using.
induction vars; simpl; sp.
rewrite IHvars; sp.
Qed.
Theorem in_selectbt: forall bt (bts : list BTerm), LIn bt bts ->
{n : nat $ n < length bts # selectbt bts n = bt}.
Proof using.
intros ? ? Hin. induction bts. inverts Hin.
invertsn Hin.
- exists 0. split; simpl; auto. omega.
- destruct IHbts; auto. exists (S x). repnd.
split; simpl; try omega. auto.
Qed.
(**useful for rewriting in complicated formulae*)
Theorem ntot_wf_iff: forall o bts, nt_wf (oterm o bts)
<=> map num_bvars bts = OpBindings o # forall n : nat,
n < length bts -> bt_wf (selectbt bts n).
Proof using. introv. sp_iff Case; introv H.
Case "->". inverts H as Hbf Hmap. split; auto.
introv Hlt. apply Hbf. apply selectbt_in; auto.
Case "<-". repnd. constructor; auto.
introv Hin. apply in_selectbt in Hin.
exrepnd. rw <- Hin0;auto.
Qed.
(**useful for rewriting in complicated formulae*)
Theorem bt_wf_iff: forall lv (nt : NTerm), bt_wf (bterm lv nt)
<=> nt_wf nt.
Proof using. sp_iff Case; introv H.
Case "->". inverts H as Hwf; auto.
Case "<-". constructor; auto.
Qed.
Definition nvarxbt := bterm [] (vterm nvarx) .
Lemma isprogram_get_cterm :
forall a, isprogram (get_cterm a).
Proof using.
destruct a; sp; simpl.
rw isprogram_eq; sp.
Qed.
Lemma oterm_eq :
forall o1 o2 l1 l2,
o1 = o2
-> l1 = l2
-> (@oterm NVar Opid) o1 l1 = oterm o2 l2.
Proof using.
sp; allrw; sp.
Qed.
Notation oterm := (@oterm NVar Opid).
Notation vterm := (@vterm NVar Opid).
Inductive liftRBt (R : (NTerm) -> (NTerm) -> Prop)
: (@BTerm) -> (@BTerm) -> Prop :=
liftRbt : forall lv ntl ntr, R ntl ntr
-> liftRBt R
(bterm lv ntl)
(bterm lv ntr).
Require Import SetoidList.
(* Move to SquiggleEq and heterogenize *)
Lemma liftRBTeqlist (R : NTerm -> NTerm -> Prop) es lbt:
eqlistA (liftRBt R) (map (bterm []) es) lbt
-> exists esp, eqlistA R es esp /\ lbt = map (bterm []) esp.
Proof using.
revert es lbt.
induction es; intros ? Heq; inverts Heq.
+ eexists. split. constructor. refl.
+ inverts H1. apply IHes in H3. exrepnd. eexists. split. econstructor; eauto.
subst. auto.
Qed.
Lemma liftRbt_eqlista (R : NTerm -> NTerm -> Prop) vs vsp:
eqlistA R vs vsp ->
eqlistA (liftRBt R) (map (bterm []) vs) (map (bterm []) vsp).
Proof using.
intros H. induction H; constructor; auto.
constructor; auto.
Qed.
Lemma liftRbtsiglist {dcon:Type} (R: NTerm -> NTerm -> Prop):
forall (bs : list (dcon * BTerm)) (lbtp : list BTerm),
eqlistA (liftRBt R) (map snd bs) lbtp ->
map (fun x : dcon * BTerm => num_bvars (snd x)) bs = map num_bvars lbtp.
Proof using.
intros ? ? Heq. remember (map snd bs) as msb. revert dependent bs.
induction Heq; intros; destruct bs; invertsn Heqmsb; auto.
simpl. f_equal; eauto.
inverts H; auto.
Qed.
Lemma bterm_eq :
forall l1 l2 n1 n2,
l1 = l2
-> n1 = n2
-> bterm l1 n1 = bterm l2 n2.
Proof using.
sp; allrw; sp.
Qed.
Theorem selectbt_map {gtsi gtso}: forall lbt n
(f: (@terms.BTerm NVar gtsi) -> (@terms.BTerm NVar gtso)) ,
n<length lbt
-> selectbt (map f lbt) n = f (selectbt lbt n).
Proof using.
induction lbt; introv Hlt. inverts Hlt.
simpl. destruct n; subst. reflexivity.
unfold selectbt in *. allsimpl.
assert (n < (length lbt)) by omega.
auto.
Qed.
Theorem eq_maps_bt: forall (B : Type) (f : BTerm -> B)
(g : BTerm -> B) (la lc : list BTerm),
length la = length lc
-> (forall n : nat, n < length la
-> f (selectbt la n) = g (selectbt lc n))
-> map f la = map g lc.
Proof using. unfold selectbt. introv H2 H3. apply eq_maps2 in H3; auto.
Qed.
Lemma vterm_inj: injective_fun vterm.
Proof using.
introv Hf. inverts Hf. auto.
Qed.
Lemma map_eq_lift_vterm: forall lvi lvo,
map vterm lvi = map vterm lvo -> lvi = lvo.
Proof using.
intros.
apply map_eq_injective with (f:=vterm); auto.
exact vterm_inj.
Qed.
(*
Global Instance deqNterm : Deq NTerm.
Proof.
intros a b. exists (NTerm_beq a b).
apply NTerm_beq_correct.
Defined.
*)
Global Instance deq_nterm : DeqSumbool NTerm.
Proof using deqnvar hdeq.
intros x.
nterm_ind1 x as [v1 | o1 lbt1 Hind] Case; intros y.
- Case "vterm".
destruct y as [v2 | o lbt2]; [ | right; intro Hc; inverts Hc].
destruct (decideP (v1=v2)); subst;
[ left; auto; fail
| right; intro Hc; inverts Hc; sp
].
- Case "oterm".
destruct y as [v2 | o2 lbt2]; [ right; intro Hc; inverts Hc | ].
destruct (decideP (o1=o2)); subst; [ | right; intro Hc; inverts Hc;sp].
assert ((lbt1=lbt2) + (lbt1 <> lbt2)) as Hbt.
Focus 2.
dorn Hbt; subst; [left; auto | right; intro Hc; inverts Hc;sp ]; fail.
revert lbt2.
induction lbt1.
destruct lbt2; [left; auto | right; intro Hc; inverts Hc;sp ]; fail.
destruct lbt2; [ right; intro Hc; inverts Hc; fail | ].
destruct a as [lv1 nt1]. destruct b as [lv2 nt2].
lapply (IHlbt1);
[ | introv Hin; apply Hind with (lv:=lv); eauto; right; auto].
intro bdec.
destruct (bdec lbt2); subst; [ | right; intro Hc; inverts Hc;sp;fail ].
destruct (decideP (lv1=lv2));
subst; [ | right; intro Hc; inverts Hc;sp;fail ].
destruct (Hind nt1 lv2 (injL(eq_refl _) ) nt2); subst;
[left; auto | right; intro Hc; inverts Hc;sp ].
Defined.
Lemma lin_lift_vterm :
forall v lv,
LIn v lv <=> LIn (vterm v) (map vterm lv).
Proof using.
induction lv; [sp | ]. simpl.
rw <- IHlv; split; intros hp; try (dorn hp); sp; subst; sp.
inverts hp. sp.
Qed.
Lemma map_removevars:
forall lvi lvr,
map vterm (remove_nvars lvi lvr)
= @lremove _ _ (map vterm lvi) (map vterm lvr).
Proof using.
(* simpl.
clear gts. *)
intros. apply map_diff_commute.
introv Hc. inverts Hc. auto.
Qed.
Open Scope list_scope.
Definition all_vars_bt (bt : BTerm) := free_vars_bterm bt ++ bound_vars_bterm bt.
Lemma all_vars_ot : forall o lbt,
eq_set
(all_vars (oterm o lbt))
(flat_map all_vars_bt lbt).
Proof using.
intros. unfold all_vars. simpl. unfold all_vars_bt.
rewrite <- flat_map_fapp. refl.
Qed.
Theorem nil_remove_nvars_iff: forall l1 l2 : list NVar,
(remove_nvars l1 l2) = [] <=> (forall x : NVar, LIn x l2 -> LIn x l1).
Proof using.
intros. rw <- null_iff_nil. apply null_remove_nvars.
Qed.
Theorem nil_rv_single_iff: forall lv v ,
(remove_nvars lv [v]) = [] <=> (LIn v lv).
Proof using.
intros. rw <- null_iff_nil. rw null_remove_nvars.
split; intro Hyp.
apply Hyp. left. auto.
introv Hin. apply in_list1 in Hin; subst; auto.
Qed.
Theorem selectbt_eq_in: forall lv nt lbt n,
bterm lv nt = selectbt lbt n
-> n < length lbt
-> LIn (bterm lv nt) lbt.
Proof using.
introv Heq Hlt. rw Heq.
apply selectbt_in; trivial.
Qed.
Lemma flat_map_closed_terms:
forall (lnt : list NTerm), lforall closed lnt
-> flat_map free_vars lnt = [].
Proof using.
unfold lforall, closed. introv Hfr.
apply flat_map_empty. trivial.
Qed.
Lemma flat_map_progs:
forall lnt, lforall isprogram lnt
-> flat_map free_vars lnt = [].
Proof using.
unfold lforall, closed. introv Hfr.
apply flat_map_empty. introv Hin.
apply Hfr in Hin. inverts Hin. auto.
Qed.
Theorem disjoint_lbt_bt :
forall vs lbt lv nt,
disjoint vs (flat_map bound_vars_bterm lbt)
-> LIn (bterm lv nt) lbt
-> disjoint vs lv.
Proof using.
introv Hink1 Hin.
apply disjoint_sym in Hink1; rw disjoint_flat_map_l in Hink1.
apply Hink1 in Hin.
simpl in Hin. rw disjoint_app_l in Hin.
repnd; apply disjoint_sym. trivial.
Qed.
Definition selectnt (n:nat) (lnt : list NTerm): NTerm :=
nth n lnt (vterm nvarx).
Lemma deq_bterm : DeqSumbool BTerm.
Proof using deqnvar hdeq.
intros btx bty. destruct btx as [lvx ntx].
destruct bty as [lvy nty].
destruct (deq_nterm ntx nty);
destruct (decideP (lvx=lvy)); subst;sp;
right; introv Heq;
inverts Heq; cpx.
Qed.
Inductive nt_wf2 : NTerm -> [univ] :=
| wfvt2 : forall nv : NVar, nt_wf2 (vterm nv)
| wfot2 : forall (o : Opid) (lnt : list BTerm),
length lnt = length (OpBindings o)
-> (forall n, n < (length lnt) ->
num_bvars (selectbt lnt n) = nth n (OpBindings o) 0
# bt_wf2 (selectbt lnt n))
-> nt_wf2 (oterm o lnt)
with bt_wf2 : BTerm -> [univ] :=
wfbt2 : forall (lnv : list NVar) (nt : NTerm),
nt_wf2 nt -> bt_wf2 (bterm lnv nt).
(** mainly for convenience in proofs *)
Theorem selectbt_in2: forall (n : nat) (bts : list BTerm),
n < length bts -> { bt : BTerm & (LIn bt bts # (selectbt bts n)=bt) }.
Proof using.
intros. exists (selectbt bts n).
split;auto. apply selectbt_in; trivial.
Defined.
Lemma nt_wf_nt_wf2 : forall t, (nt_wf t) <=> (nt_wf2 t).
Proof using.
assert (0= num_bvars (bterm [] (vterm nvarx))) as XX by auto.
nterm_ind1 t as [?| o lbt Hind] Case; split; introv Hyp; sp.
- inverts Hyp as Hl Hyp. constructor. apply_length Hyp;sp.
introv hlt. unfold selectbt. rw <- Hyp.
rw XX. rw map_nth; sp;[].
fold (selectbt lbt n).
pose proof (selectbt_in2 n lbt hlt) as Hbt.
exrepnd. destruct bt as [lv nt].
applydup Hind in Hbt1.
rw Hbt0. constructor.
apply Hl in Hbt1. inverts Hbt1.
sp3.
- inverts Hyp as Hl Hyp. constructor.
+ introv Hin. apply in_selectbt in Hin; auto;[].
exrepnd. applydup Hyp in Hin1.
rw Hin0 in Hin2. destruct l as [lv nt].
constructor. exrepnd. invertsn Hin2.
applysym selectbt_in in Hin1. rw Hin0 in Hin1.
apply Hind in Hin1. sp3.
+ eapply (tiff_snd (eq_list2 _ 0 _ _)). rw map_length.
split; auto;[]. introv Hlt. apply Hyp in Hlt.
repnd. rw <- Hlt0.
rw XX. rw map_nth. sp.
Qed.
Definition bin_rel_nterm :=
binrel_list (vterm nvarx).
Theorem isprogram_ot_implies_eauto2 :
forall o bts,
isprogram (oterm o bts)
-> (forall n, n< length bts -> isprogram_bt (selectbt bts n)).
Proof using.
introv Hp Hlt. apply isprogram_ot_iff in Hp.
apply selectbt_in in Hlt. exrepnd.
eauto with slow.
Qed.
Lemma isprogram_bt_nobnd :
forall t ,
isprogram_bt (bterm [] t)
-> isprogram (t).
Proof using.
unfold isprogram_bt, closed_bt, isprogram, closed; intros ? Hxx; spc; allsimpl.
match goal with
[H: (bt_wf _) |- _ ] => inverts H
end.
assumption.
Qed.
Lemma free_vars_list_app :
forall (ts1 ts2 : list NTerm),
free_vars_list (ts1 ++ ts2)
= free_vars_list ts1 ++ free_vars_list ts2.
Proof using.
induction ts1; simpl; sp.
rw IHts1; simpl.
rw app_assoc; sp.
Qed.
Lemma isprog_ntwf_eauto : forall t, isprogram t -> nt_wf t.
Proof using. unfold isprogram. spc.
Qed.
Theorem isprogram_ot_if_eauto :
forall o bts,
map num_bvars bts = OpBindings o
-> (forall bt, LIn bt bts -> isprogram_bt bt)
-> isprogram (oterm o bts).
Proof using.
intros. apply isprogram_ot_iff;spc.
Qed.
Definition getOpidBTerms (t: NTerm) : option (Opid * list BTerm):=
match t with
| terms.vterm _ => None
| terms.oterm o lb => Some (o, lb)
end.
Lemma isprogramd :
forall v, isprogram v
-> {o : Opid $ {lbt : list BTerm $ v = oterm o lbt}}.
Proof using.
introv Hpr.
invertsn Hpr.
destruct v; inverts Hpr.
eexists; eexists ; eauto.
Qed.
(* Move *)
Lemma fold_combine : forall {A B} (v:A) (t:B),
[(v,t)] = (combine [v] [t]).
Proof using.
intros. simpl. auto.
Qed.
(* Lemma noncan_not_value : forall e,
isnoncan e
-> isvalue e
-> False.
Proof using.
introv Hisnc Hisv.
destruct e as [?| o lbt]; allsimpl; cpx.
destruct o; cpx.
inverts Hisv.
Qed. *)
Theorem isprogram_ot_if_eauto2 :
forall o bts,
map num_bvars bts = OpBindings o
-> (forall n, n< length bts -> isprogram_bt (selectbt bts n))
-> isprogram (oterm o bts).
Proof using.
introv Hn Hp. apply isprogram_ot_iff; dands; spcf.
introv Hin. apply in_selectbt in Hin. exrepnd.
eauto with slow.
rw <- Hin0.
eauto with slow.
Qed.
Lemma closed_implies:
forall (t : NTerm),
closed t -> (forall x, !LIn x (free_vars t)).
Proof using.
introv cl.
unfold closed in cl.
allrw; simpl; try (complete sp).
Qed.
Lemma list_nil_btwf: forall es,
(forall l : BTerm, LIn l (map (bterm []) es) -> bt_wf l)
<->
(forall l : NTerm, LIn l es -> nt_wf l).
Proof using.
intros ?.
split; intros H ? Hin.
- apply (bt_wf_iff []).
apply H. apply in_map; auto.
- apply in_map_iff in Hin. exrepnd. subst.
constructor; auto.
Qed.
Require Import Coq.Program.Basics.
Open Scope program_scope.
Lemma flat_map_bterm_nil : forall gts lnt,
flat_map free_vars_bterm
(map ((@terms.bterm NVar gts) []) lnt) =
flat_map free_vars lnt.
Proof.
induction lnt; auto.
simpl. f_equal; auto.
Qed.
Lemma flat_map_vterm : forall gts (lv: list NVar),
flat_map free_vars_bterm
(map ((@terms.bterm NVar gts) [] ∘ terms.vterm) lv) = lv.
Proof using.
induction lv; auto.
simpl. f_equal; auto.
Qed.
Lemma subset_flat_map_lbt:
forall lbt (l lv : list NVar) (n : NTerm),
LIn (bterm l n) lbt ->
subsetv (flat_map free_vars_bterm lbt) lv
-> subsetv (free_vars n) (l ++ lv).
Proof using.
intros ? ? ? ? Hin Hs.
rewrite subset_flat_map in Hs.
rewrite subsetv_prop.
apply_clear Hs in Hin.
simpl in Hin.
rewrite subsetv_prop in Hin.
intros x Hn. specialize (Hin x).
rewrite in_remove_nvars in Hin.
rewrite in_app_iff; destruct (dmemvar x l); cpx.
Qed.
Lemma select_selectbt : forall n lbt (b:BTerm),
select n lbt = Some b
<-> (selectbt lbt n = b /\ n < length lbt).
Proof using.
intros ? ? ?.
split; intros Hin.
- pose proof Hin.
apply select_lt in Hin. split;[|assumption].
apply nth_select1 with (def:= bterm [] (vterm nvarx))in Hin.
unfold selectbt.
congruence.
- repnd. eapply nth_select3; auto.
apply Hin0.
Qed.
Lemma size_pos : forall (t:NTerm),
0<(size t).
Proof.
intros. destruct t; simpl; omega.
Qed.
Definition preservesVarclass (ta tb : NTerm) :Prop :=
forall vc,
varsOfClass (all_vars ta) vc
-> varsOfClass (all_vars tb) vc.
Definition preservesVarclassBT (ta tb : BTerm) :Prop :=
forall vc,
varsOfClass (all_vars_bt ta) vc
-> varsOfClass (all_vars_bt tb) vc.
Lemma subsetAllVarsLbt : forall o lbt bt,
LIn bt lbt -> subset (all_vars_bt bt) (all_vars (oterm o lbt)).
Proof.
intros ? ? ? Hin.
rewrite all_vars_ot.
unfold all_vars_bt.
eapply subset_trans;
[|apply subset_flat_map_r; apply Hin].
apply subset_refl.
Qed.
Lemma varsOfClassOT : forall o lbt c,
varsOfClass (all_vars (oterm o lbt)) c
-> forall bt, LIn bt lbt -> varsOfClass (all_vars_bt bt) c.
Proof using.
intros ? ? ? Hv ? Hin ? Hinn.
apply Hv. revert Hinn.
apply subsetAllVarsLbt.
assumption.
Qed.
Lemma map0lbt : forall (lbt: list BTerm),
map num_bvars lbt = repeat 0 (Datatypes.length lbt)
-> lbt = map (bterm []) (map get_nt lbt).
Proof using.
induction lbt; simpl; auto.
intro Hn.
destruct a. inverts Hn as Hn Hnn. unfold num_bvars in Hn.
simpl in Hn. dlist_len_name l Hh.
simpl. f_equal. eauto.
Qed.
Definition allvars_bterm : forall lv nt,
eq_set
(all_vars_bt (bterm lv nt))
(lv ++ all_vars nt).
Proof using.
clear.
intros ? ?. apply eqsetv_prop.
intro. unfold all_vars, all_vars_bt.
simpl.
repeat rewrite in_app_iff.
repeat rewrite in_remove_nvars.
destruct (decideP (LIn x lv)); (* firstorder does not know about decidability *)
firstorder.
Qed.
Lemma flat_map_free_var_vterm: forall lv:list NVar, flat_map free_vars (map vterm lv)=lv.
Proof using.
induction lv;sp;simpl;f_equal;sp.
Qed.
Lemma flat_map_bound_var_vterm: forall lv:list NVar, flat_map bound_vars (map vterm lv)=[].
Proof using.
induction lv;sp;simpl;f_equal;sp.
Qed.
Lemma size_subterm4 :
forall (lb : list (BTerm)) (nt : NTerm) (lv : list NVar),
LIn (bterm lv nt) lb -> size nt < S (addl (map size_bterm lb)).
Proof using.
induction lb; auto; simpl; try tauto;[].
intros ? ? Hin. dorn Hin.
- subst. simpl. omega.
- apply IHlb in Hin. omega.
Qed.
Lemma subsetAllVarsLbt2 : forall lbt lv (nt : NTerm),
LIn (bterm lv nt) lbt -> subset (all_vars nt) (flat_map all_vars_bt lbt).
Proof using.
clear.
intros.
eapply subset_trans;
[|eapply subset_flat_map_r; eauto].
rewrite allvars_bterm.
apply subset_app_l.
refl.
Qed.
Lemma subsetBoundVarsLbt3 : forall (lbt : list BTerm) (lv : list NVar) (nt : NTerm),
LIn (bterm lv nt) lbt -> subset lv (flat_map bound_vars_bterm lbt).
Proof using.
intros.
eapply subset_trans;
[|eapply subset_flat_map_r; eauto].
apply subset_app_r.
refl.
Qed.
Lemma flat_map_bterm_nil_allvars:
forall (lnt : list NTerm),
flat_map all_vars_bt (map (terms.bterm []) lnt) = flat_map all_vars lnt.
Proof using.
intros. rewrite flat_map_map.
apply eq_flat_maps.
intros ? Hin.
unfold compose, all_vars_bt.
simpl.
refl.
Qed.
Lemma subsetAllVarsLbt3
: forall (lbt : list BTerm) (lv : list NVar) (nt : terms.NTerm),
LIn (bterm lv nt) lbt -> subset lv (flat_map all_vars_bt lbt).
Proof.
introv Hin.
eapply transitivity;
[|apply subset_flat_map_r; eauto].
rewrite allvars_bterm.
apply subset_app_r. refl.
Qed.
End terms4Generic.
Ltac varsOfClassSimpl :=
repeat match goal with
[ H: varsOfClass (all_vars (oterm ?o ?lbt)) true |- _ ] =>
specialize (varsOfClassOT _ _ _ H); clear H; intro H;
repeat match goal with
| [HH : LIn _ lbt |- _] => apply (fun lin => (conj lin (H _ lin))) in HH
end; repnd;
repeat match goal with
[H:context [varsOfClass (all_vars_bt (bterm _ _)) true] |- _]
=> setoid_rewrite allvars_bterm in H (* if it fails, continuing may cause a loop *)
end;
repeat rewrite @varsOfClassApp in *
end.
(* Move *)
Hint Rewrite @flat_map_bterm_nil @flat_map_free_var_vterm
remove_nvars_eq : SquiggleEq.
Hint Rewrite @all_vars_ot @allvars_bterm : allvarsSimpl.
Hint Rewrite @all_vars_ot @allvars_bterm @varsOfClassApp : SquiggleEq.
Hint Resolve isprogram_ot_if_eauto : slow.
Hint Immediate isprogram_get_cterm.
Hint Resolve isprog_implies : isprog.
Hint Extern 100 (LIn _ _) => complete (simpl; sp) : isprog.
Hint Resolve nt_wf_implies : slow.
Hint Resolve nt_wf_eq: slow.
Hint Resolve is_program_ot_nth_nobnd : slow.
Hint Resolve deq_bterm.
Hint Immediate deq_nterm.
Hint Immediate isprogram_get_cterm.
Hint Resolve isprog_ntwf_eauto : slow.
Tactic Notation "disjoint_reasoningv" :=
(allunfold all_vars); repeat( progress disjoint_reasoning).
Ltac destruct_bterms:=
repeat match goal with
[bt : BTerm |- _] =>
let btlv := fresh bt "lv" in
let btnt := fresh bt "nt" in
destruct bt as [btlv btnt]
end.
Ltac noRepDis :=
(repeat match goal with
[H: no_repeats [] |- _] => clear H
|[H: no_repeats (_::_) |- _] =>
let Hnrd := fresh "Hnrd" in
apply no_repeats_as_disjoint in H;
destruct H as [Hnrd H]
end); disjoint_reasoningv;
rewrite in_single_iff in *; subst; tauto; try tauto.
(* try to move to list.v . disjoint_reasoningv performs
some non-list-based unfolding which may
be done using a database *)
Ltac inauto:=
(repeat match goal with
[H: no_repeats [] |- _] => clear H
|[H: no_repeats (_::_) |- _] =>
let Hnrd := fresh "Hnrd" in
apply no_repeats_as_disjoint in H;
destruct H as [Hnrd H]
end); disjoint_reasoningv;
unfold subset in *;
unfold disjoint in *;
repeat match goal with
| [H:context[LIn _ (_::_) ] |- _] => simpl in H; try setoid_rewrite or_false_r in H
| [|- context[LIn _ (_::_)]] => simpl; try setoid_rewrite or_false_r
| [H:context[LIn _ (flat_map _ _) ] |- _] => setoid_rewrite in_flat_map in H
| [|- context[LIn _ (flat_map _ _)]] => setoid_rewrite in_flat_map
| [H:context[LIn _ (map _ _)]|- _] => setoid_rewrite in_map_iff in H
| [|- context[LIn _ (map _ _)]] => setoid_rewrite in_map_iff
| [H:context[LIn _ (remove_nvars _ _)]|- _] => setoid_rewrite in_remove_nvars in H; simpl in H
| [|- context[LIn _ (remove_nvars _ _)]] => setoid_rewrite in_remove_nvars; simpl
| [H: _ = []|- _] => apply null_iff_nil in H; unfold null in H; simpl in H
| [|- _ = []] => apply null_iff_nil; unfold null; simpl
| [|- context[LIn _ (map _ _)]] => setoid_rewrite in_map_iff
end;
subst.
Local Ltac
illFormedCase :=
(try reflexivity; try (simpl;rewrite flat_map_vterm; reflexivity)).
(* Move *)
Ltac destructbtdeep2 bt tac :=
let btlv := fresh bt "lv" in
let btnt := fresh bt "nt" in
let btlv1 := fresh btlv "1" in
let btlv2 := fresh btlv "2" in
let btlv3 := fresh btlv "3" in
destruct bt as [btlv btnt];
destruct btlv as [| btlv1]; tac;
try(destruct btlv as [| btlv2]; tac);
try(destruct btlv as [| btlv3]; tac).
Ltac destructlbt lbt tac :=
repeat (
let b := fresh "b" in
destruct lbt as [| b lbt];tac; []).
Hint Rewrite memvar_singleton : SquiggleEq.
Hint Rewrite remove_nvars_cons_r : SquiggleEq2.
Hint Rewrite
<- beq_var_refl : SquiggleEq.
Ltac disjoint_flat_allv :=
repeat match goal with
[ Hdis : disjoint ?lv (flat_map all_vars_bt ?lbt) ,
Hin : LIn _ ?lbt |- _]
=> rewrite disjoint_flat_map_r in Hdis; specialize (Hdis _ Hin); unfold all_vars_bt in Hdis;
simpl in Hdis
end.
Ltac disjoint_reasoning2 :=
match goal with
| [ |- disjoint _ (_ ++ _) ] => apply disjoint_app_r;split
| [ |- disjoint (_ ++ _) _ ] => apply disjoint_app_l;split
| [ |- disjoint _ (_ :: (_ :: _)) ] => apply disjoint_cons_r;split
| [ |- disjoint (_ :: (_ :: _)) _ ] => apply disjoint_cons_l;split
| [ |- disjoint _ (_ :: ?v) ] => notNil v;apply disjoint_cons_r;split
| [ |- disjoint (_ :: ?v) _ ] => notNil v;apply disjoint_cons_l;split
| [ |- disjoint _ _ ] => (sp;fail || apply disjoint_sym; sp;fail)
| [ |- _ <> _] => apply disjoint_neq_iff
| [ |- ! (LIn _ _)] => apply disjoint_singleton_l
(** important to leave it the way it was .. so that repeat progress won't loop*)
| [ H: disjoint _ (_ ++ _) |- _ ] => apply disjoint_app_r in H;sp
| [ H: disjoint (_ ++ _) _ |- _ ] => apply disjoint_app_l in H;sp
| [ H: disjoint _ (_ :: (_ :: _)) |- _ ] => apply disjoint_cons_r in H;sp
| [ H: disjoint (_ :: (_ :: _)) _ |- _ ] => apply disjoint_cons_l in H;sp
| [ H: disjoint _ (_ :: ?v) |- _ ] => notNil v;apply disjoint_cons_r in H;sp
| [ H: disjoint (_ :: ?v) _ |- _ ] => notNil v;apply disjoint_cons_l in H;sp
| [ H: !(disjoint _ []) |- _ ] => provefalse; apply H; apply disjoint_nil_r
| [ H: !(disjoint [] _) |- _ ] => provefalse; apply H; apply disjoint_nil_l
| [ H: (disjoint _ []) |- _ ] => clear H
| [ H: (disjoint [] _) |- _ ] => clear H
| [ H: ! (LIn _ _) |- _] => apply disjoint_singleton_l in H
| [ H: _ <> _ |- _] => apply disjoint_neq_iff in H
end.
Tactic Notation "disjoint_reasoningv2" :=
(unfold all_vars in *); repeat( progress disjoint_reasoning2).
Ltac disjoint_flat2 :=
disjoint_reasoning2; disjoint_flat_allv;disjoint_reasoningv2.
Hint Resolve subsetAllVarsLbt2 : subset.
Hint Rewrite remove_var_nil remove_nvars_nil_r: SquiggleEq.
Ltac rwHyps :=
unfold closed, closed_bt in *;
repeat match goal with
[ H: _ = _ |- _] => repeat rewrite H; hide_hyp H
end; show_hyps.
Hint Resolve @subsetAllVarsLbt3 @subsetBoundVarsLbt3 : subset.
Lemma isProgramLNoBnd {O V} {deqv: Deq V} {gtso : GenericTermSig O}
(lbt: list (@BTerm V O)) m:
map num_bvars lbt = repeat 0 m
-> lforall isprogram_bt lbt
-> lforall isprogram (map get_nt lbt).
Proof using.
revert m.
induction lbt; unfold lforall; simpl in *;[ firstorder; fail | ].
intros ? Hm.
simpl in *.
simpl.
destruct m; [invertsn Hm | ].
simpl in *. inverts Hm as Hma Hm.
rewrite Hma in Hm.
specialize (IHlbt _ Hm).
destruct a as [lv nt].
destruct lv; [ | inverts Hma].
revert IHlbt. revert Hm. unfold lforall. clear.
intros.
pose proof (H _ ltac:(left; refl)).
apply isprogram_bt_nobnd in H1.
firstorder; subst; simpl; firstorder.
Qed.
Lemma map0lbt2 {V O}: forall (lbt: list (@BTerm V O)) m,
map num_bvars lbt = repeat 0 m
-> lbt = map (bterm []) (map get_nt lbt).
Proof using.
induction lbt; simpl; auto.
intros ? Hn.
destruct a. inverts Hn as Hn Hnn. unfold num_bvars in Hn.
simpl in Hn. dlist_len_name l Hh.
destruct m; invertsn Hn.
destruct l; invertsn Hn.
simpl. f_equal. eauto.
Qed.
Hint Rewrite @noDupApp @all_vars_ot @allvars_bterm @varsOfClassConsIff @noDupConsIff: SquiggleEq.
Lemma wft_ntwf {Opid V} {gts : GenericTermSig Opid}: forall t: @NTerm V Opid, wft t =true -> nt_wf t.
Proof using.
induction t as [x | o lbt Hind] using NTerm_better_ind; intros Hwf; try (constructor; fail).
simpl in Hwf.
apply andb_eq_true in Hwf. repnd.
setoid_rewrite assert_beq_list in Hwf0.
constructor; auto.
rewrite ball_map_true in Hwf.
intros l. destruct l. intros. constructor.
eapply Hind; eauto.
specialize (Hwf _ H).
simpl in Hwf. assumption.
Qed.
Hint Rewrite @flat_map_bterm_nil_allvars: SquiggleEq.
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
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// laws.
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// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// (individually and collectively, "Critical
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// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_systeminit_top.v
// Version : v1.0
// Description: static configuration top level module
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_systeminit_top #
(
parameter C_FAMILY = "virtex7" ,
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_M_AXI_AWUSER_WIDTH = 1 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_ATG_DATA_MIF = "atg_data.mif" ,
parameter C_ATG_ADDR_MIF = "atg_addr.mif" ,
parameter C_ATG_CTRL_MIF = "atg_ctrl.mif" ,
parameter C_ATG_MASK_MIF = "atg_mask.mif" ,
parameter C_ATG_MIF_ADDR_BITS = 5 ,// 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_MIF_DATA_DEPTH = 32 ,// 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_SYSTEM_INIT = 0 ,
parameter C_ATG_SYSTEM_TEST = 0 ,
parameter C_ATG_SYSTEM_CMD_MAX_RETRY = 32'h1 ,
parameter C_ATG_SYSTEM_TEST_MAX_CLKS = 32'h0000001A ,
parameter C_ATG_SYSTEM_MAX_CHANNELS = 32'h1 ,
parameter C_ATG_SYSTEM_CH1_LOW = 32'h0000_0000 ,
parameter C_ATG_SYSTEM_CH1_HIGH = 32'h0000_00FF ,
parameter C_ATG_SYSTEM_CH2_LOW = 32'h0000_0100 ,
parameter C_ATG_SYSTEM_CH2_HIGH = 32'h0000_01FF ,
parameter C_ATG_SYSTEM_CH3_LOW = 32'h0000_0200 ,
parameter C_ATG_SYSTEM_CH3_HIGH = 32'h0000_02FF ,
parameter C_ATG_SYSTEM_CH4_LOW = 32'h0000_0300 ,
parameter C_ATG_SYSTEM_CH4_HIGH = 32'h0000_03FF ,
parameter C_ATG_SYSTEM_CH5_LOW = 32'h0000_0400 ,
parameter C_ATG_SYSTEM_CH5_HIGH = 32'h0000_04FF
) (
// system
input Clk ,
input rst_l ,
//Master-write-ch1
output [31:0] ch1_awaddr_m ,
output ch1_awvalid_m ,
input ch1_awready_m ,
output [2:0] ch1_awprot_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch1_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch1_wstrb_m ,
output ch1_wvalid_m ,
input ch1_wready_m ,
input [1:0] ch1_bresp_m ,
input ch1_bvalid_m ,
output ch1_bready_m ,
output [31:0] ch1_araddr_m ,
output ch1_arvalid_m ,
input ch1_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch1_rdata_m ,
input ch1_rvalid_m ,
input [1:0] ch1_rresp_m ,
output ch1_rready_m ,
//Master-write-ch2
output [31:0] ch2_awaddr_m ,
output ch2_awvalid_m ,
input ch2_awready_m ,
output [2:0] ch2_awprot_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch2_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch2_wstrb_m ,
output ch2_wvalid_m ,
input ch2_wready_m ,
input [1:0] ch2_bresp_m ,
input ch2_bvalid_m ,
output ch2_bready_m ,
output [31:0] ch2_araddr_m ,
output ch2_arvalid_m ,
input ch2_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch2_rdata_m ,
input ch2_rvalid_m ,
input [1:0] ch2_rresp_m ,
output ch2_rready_m ,
//Master-write-ch3
output [31:0] ch3_awaddr_m ,
output ch3_awvalid_m ,
input ch3_awready_m ,
output [2:0] ch3_awprot_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch3_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch3_wstrb_m ,
output ch3_wvalid_m ,
input ch3_wready_m ,
input [1:0] ch3_bresp_m ,
input ch3_bvalid_m ,
output ch3_bready_m ,
output [31:0] ch3_araddr_m ,
output ch3_arvalid_m ,
input ch3_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch3_rdata_m ,
input ch3_rvalid_m ,
input [1:0] ch3_rresp_m ,
output ch3_rready_m ,
//Master-write-ch4
output [31:0] ch4_awaddr_m ,
output ch4_awvalid_m ,
input ch4_awready_m ,
output [2:0] ch4_awprot_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch4_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch4_wstrb_m ,
output ch4_wvalid_m ,
input ch4_wready_m ,
input [1:0] ch4_bresp_m ,
input ch4_bvalid_m ,
output ch4_bready_m ,
output [31:0] ch4_araddr_m ,
output ch4_arvalid_m ,
input ch4_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch4_rdata_m ,
input ch4_rvalid_m ,
input [1:0] ch4_rresp_m ,
output ch4_rready_m ,
//Master-write-ch5
output [31:0] ch5_awaddr_m ,
output ch5_awvalid_m ,
input ch5_awready_m ,
output [2:0] ch5_awprot_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch5_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch5_wstrb_m ,
output ch5_wvalid_m ,
input ch5_wready_m ,
input [1:0] ch5_bresp_m ,
input ch5_bvalid_m ,
output ch5_bready_m ,
output [31:0] ch5_araddr_m ,
output ch5_arvalid_m ,
input ch5_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch5_rdata_m ,
input ch5_rvalid_m ,
input [1:0] ch5_rresp_m ,
output ch5_rready_m ,
output irq_out ,
output done ,
output [31:0] status
);
wire done_i;
wire [31:0] status_i;
wire [31:0] rom_data ;
wire [31:0] rom_mask ;
wire [31:0] rom_ctrl ;
wire [31:0] rom_addr ;
wire [9:0] rom_addr_ptr_ff ;
wire [9:0] rom_data_ptr_ff ;
wire [127:0] cmd_out_mw ;
wire [C_M_AXI_DATA_WIDTH-1:0] mram_out;
assign done = done_i;
assign status = status_i;
assign ch1_awprot_m = 3'b000; //Fixed value driven
assign ch2_awprot_m = 3'b000; //Fixed value driven
assign ch3_awprot_m = 3'b000; //Fixed value driven
assign ch4_awprot_m = 3'b000; //Fixed value driven
assign ch5_awprot_m = 3'b000; //Fixed value driven
axi_traffic_gen_v2_0_systeminit_dmg #(
.C_FAMILY (C_FAMILY ) ,
.C_ATG_MIF (C_ATG_ADDR_MIF ) ,
.C_ATG_MIF_ADDR_BITS (C_ATG_MIF_ADDR_BITS ) ,
.C_ATG_MIF_DATA_DEPTH(C_ATG_MIF_DATA_DEPTH)
) systeminit_dmg_addr(
.a (rom_addr_ptr_ff[C_ATG_MIF_ADDR_BITS-1:0] ),
.clk (Clk ),
.qspo_srst (~rst_l ),
.qspo (rom_addr )
);
axi_traffic_gen_v2_0_systeminit_dmg #(
.C_FAMILY (C_FAMILY ) ,
.C_ATG_MIF (C_ATG_DATA_MIF ) ,
.C_ATG_MIF_ADDR_BITS (C_ATG_MIF_ADDR_BITS ) ,
.C_ATG_MIF_DATA_DEPTH(C_ATG_MIF_DATA_DEPTH)
) systeminit_dmg_data(
.a (rom_data_ptr_ff[C_ATG_MIF_ADDR_BITS-1:0] ),
.clk (Clk ),
.qspo_srst (~rst_l ),
.qspo (rom_data )
);
generate if(C_ATG_SYSTEM_TEST ==1 ) begin : ATG_SYSINIT_DMG
axi_traffic_gen_v2_0_systeminit_dmg #(
.C_FAMILY (C_FAMILY ) ,
.C_ATG_MIF (C_ATG_MASK_MIF ) ,
.C_ATG_MIF_ADDR_BITS (C_ATG_MIF_ADDR_BITS ) ,
.C_ATG_MIF_DATA_DEPTH(C_ATG_MIF_DATA_DEPTH)
) systeminit_dmg_mask(
.a (rom_addr_ptr_ff[C_ATG_MIF_ADDR_BITS-1:0] ),
.clk (Clk ),
.qspo_srst (~rst_l ),
.qspo (rom_mask )
);
axi_traffic_gen_v2_0_systeminit_dmg #(
.C_FAMILY (C_FAMILY ) ,
.C_ATG_MIF (C_ATG_CTRL_MIF ) ,
.C_ATG_MIF_ADDR_BITS (C_ATG_MIF_ADDR_BITS ) ,
.C_ATG_MIF_DATA_DEPTH(C_ATG_MIF_DATA_DEPTH)
) systeminit_dmg_ctrl(
.a (rom_addr_ptr_ff[C_ATG_MIF_ADDR_BITS-1:0] ),
.clk (Clk ),
.qspo_srst (~rst_l ),
.qspo (rom_ctrl )
);
end
endgenerate
axi_traffic_gen_v2_0_static_cmdgen # (
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_ATG_SYSTEM_INIT (C_ATG_SYSTEM_INIT ),
.C_ATG_SYSTEM_TEST (C_ATG_SYSTEM_TEST ),
.C_ATG_MIF_ADDR_BITS (C_ATG_MIF_ADDR_BITS )
) systeminit_cmdgen (
.Clk (Clk ),
.rst_l (rst_l ),
.static_ctl_en (1'b0 ),
.static_len (8'h0 ),
.rom_addr_ptr_ff(rom_addr_ptr_ff),
.rom_addr (rom_addr ),
.rom_data (32'h0 ),
.cmd_out_mw (cmd_out_mw ),
.cmd_data ( ),
.cmd_out_mr ( )
);
//generate if(C_ATG_SYSTEM_INIT == 1) begin : ATG_SYSINIT_MWR
//axi_traffic_gen_v2_0_systeminit_mw # (
// .C_M_AXI_THREAD_ID_WIDTH(C_M_AXI_THREAD_ID_WIDTH),
// .C_M_AXI_AWUSER_WIDTH (C_M_AXI_AWUSER_WIDTH ),
// .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH )
//) static_mw (
// .Clk (Clk ),
// .rst_l (rst_l ),
// .awaddr_m (ch1_awaddr_m ),
// .awvalid_m (ch1_awvalid_m ),
// .awready_m (ch1_awready_m ),
// .wdata_m (ch1_wdata_m ),
// .wstrb_m (ch1_wstrb_m ),
// .wvalid_m (ch1_wvalid_m ),
// .wready_m (ch1_wready_m ),
// .bresp_m (ch1_bresp_m ),
// .bvalid_m (ch1_bvalid_m ),
// .bready_m (ch1_bready_m ),
// .rom_addr_ptr (rom_addr_ptr_ff ),
// .rom_data_ptr (rom_data_ptr_ff ),
// .rom_data (rom_data ),
// .cmd_out_mw (cmd_out_mw ),
// .irq_out (irq_out )
//);
//
//end
////assign done_i = 1'b0;
////assign status_i = 32'h0;
//endgenerate
axi_traffic_gen_v2_0_systeminit_mrdwr # (
.C_M_AXI_THREAD_ID_WIDTH (C_M_AXI_THREAD_ID_WIDTH ),
.C_M_AXI_AWUSER_WIDTH (C_M_AXI_AWUSER_WIDTH ),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
.C_ATG_SYSTEM_INIT (C_ATG_SYSTEM_INIT ),
.C_ATG_SYSTEM_TEST (C_ATG_SYSTEM_TEST ),
.C_ATG_SYSTEM_CMD_MAX_RETRY(C_ATG_SYSTEM_CMD_MAX_RETRY),
.C_ATG_SYSTEM_TEST_MAX_CLKS(C_ATG_SYSTEM_TEST_MAX_CLKS),
.C_ATG_SYSTEM_MAX_CHANNELS (C_ATG_SYSTEM_MAX_CHANNELS ),
.C_ATG_SYSTEM_CH1_LOW (C_ATG_SYSTEM_CH1_LOW ),
.C_ATG_SYSTEM_CH1_HIGH (C_ATG_SYSTEM_CH1_HIGH ),
.C_ATG_SYSTEM_CH2_LOW (C_ATG_SYSTEM_CH2_LOW ),
.C_ATG_SYSTEM_CH2_HIGH (C_ATG_SYSTEM_CH2_HIGH ),
.C_ATG_SYSTEM_CH3_LOW (C_ATG_SYSTEM_CH3_LOW ),
.C_ATG_SYSTEM_CH3_HIGH (C_ATG_SYSTEM_CH3_HIGH ),
.C_ATG_SYSTEM_CH4_LOW (C_ATG_SYSTEM_CH4_LOW ),
.C_ATG_SYSTEM_CH4_HIGH (C_ATG_SYSTEM_CH4_HIGH ),
.C_ATG_SYSTEM_CH5_LOW (C_ATG_SYSTEM_CH5_LOW ),
.C_ATG_SYSTEM_CH5_HIGH (C_ATG_SYSTEM_CH5_HIGH )
) static_mrdwr (
.Clk (Clk ),
.rst_l (rst_l ),
.ch1_awaddr_m (ch1_awaddr_m ),
.ch1_awvalid_m (ch1_awvalid_m ),
.ch1_awready_m (ch1_awready_m ),
.ch1_wdata_m (ch1_wdata_m ),
.ch1_wstrb_m (ch1_wstrb_m ),
.ch1_wvalid_m (ch1_wvalid_m ),
.ch1_wready_m (ch1_wready_m ),
.ch1_bresp_m (ch1_bresp_m ),
.ch1_bvalid_m (ch1_bvalid_m ),
.ch1_bready_m (ch1_bready_m ),
.ch1_araddr_m (ch1_araddr_m ),
.ch1_arvalid_m (ch1_arvalid_m ),
.ch1_arready_m (ch1_arready_m ),
.ch1_rdata_m (ch1_rdata_m ),
.ch1_rvalid_m (ch1_rvalid_m ),
.ch1_rresp_m (ch1_rresp_m ),
.ch1_rready_m (ch1_rready_m ),
.ch2_awaddr_m (ch2_awaddr_m ),
.ch2_awvalid_m (ch2_awvalid_m ),
.ch2_awready_m (ch2_awready_m ),
.ch2_wdata_m (ch2_wdata_m ),
.ch2_wstrb_m (ch2_wstrb_m ),
.ch2_wvalid_m (ch2_wvalid_m ),
.ch2_wready_m (ch2_wready_m ),
.ch2_bresp_m (ch2_bresp_m ),
.ch2_bvalid_m (ch2_bvalid_m ),
.ch2_bready_m (ch2_bready_m ),
.ch2_araddr_m (ch2_araddr_m ),
.ch2_arvalid_m (ch2_arvalid_m ),
.ch2_arready_m (ch2_arready_m ),
.ch2_rdata_m (ch2_rdata_m ),
.ch2_rvalid_m (ch2_rvalid_m ),
.ch2_rresp_m (ch2_rresp_m ),
.ch2_rready_m (ch2_rready_m ),
.ch3_awaddr_m (ch3_awaddr_m ),
.ch3_awvalid_m (ch3_awvalid_m ),
.ch3_awready_m (ch3_awready_m ),
.ch3_wdata_m (ch3_wdata_m ),
.ch3_wstrb_m (ch3_wstrb_m ),
.ch3_wvalid_m (ch3_wvalid_m ),
.ch3_wready_m (ch3_wready_m ),
.ch3_bresp_m (ch3_bresp_m ),
.ch3_bvalid_m (ch3_bvalid_m ),
.ch3_bready_m (ch3_bready_m ),
.ch3_araddr_m (ch3_araddr_m ),
.ch3_arvalid_m (ch3_arvalid_m ),
.ch3_arready_m (ch3_arready_m ),
.ch3_rdata_m (ch3_rdata_m ),
.ch3_rvalid_m (ch3_rvalid_m ),
.ch3_rresp_m (ch3_rresp_m ),
.ch3_rready_m (ch3_rready_m ),
.ch4_awaddr_m (ch4_awaddr_m ),
.ch4_awvalid_m (ch4_awvalid_m ),
.ch4_awready_m (ch4_awready_m ),
.ch4_wdata_m (ch4_wdata_m ),
.ch4_wstrb_m (ch4_wstrb_m ),
.ch4_wvalid_m (ch4_wvalid_m ),
.ch4_wready_m (ch4_wready_m ),
.ch4_bresp_m (ch4_bresp_m ),
.ch4_bvalid_m (ch4_bvalid_m ),
.ch4_bready_m (ch4_bready_m ),
.ch4_araddr_m (ch4_araddr_m ),
.ch4_arvalid_m (ch4_arvalid_m ),
.ch4_arready_m (ch4_arready_m ),
.ch4_rdata_m (ch4_rdata_m ),
.ch4_rvalid_m (ch4_rvalid_m ),
.ch4_rresp_m (ch4_rresp_m ),
.ch4_rready_m (ch4_rready_m ),
.ch5_awaddr_m (ch5_awaddr_m ),
.ch5_awvalid_m (ch5_awvalid_m ),
.ch5_awready_m (ch5_awready_m ),
.ch5_wdata_m (ch5_wdata_m ),
.ch5_wstrb_m (ch5_wstrb_m ),
.ch5_wvalid_m (ch5_wvalid_m ),
.ch5_wready_m (ch5_wready_m ),
.ch5_bresp_m (ch5_bresp_m ),
.ch5_bvalid_m (ch5_bvalid_m ),
.ch5_bready_m (ch5_bready_m ),
.ch5_araddr_m (ch5_araddr_m ),
.ch5_arvalid_m (ch5_arvalid_m ),
.ch5_arready_m (ch5_arready_m ),
.ch5_rdata_m (ch5_rdata_m ),
.ch5_rvalid_m (ch5_rvalid_m ),
.ch5_rresp_m (ch5_rresp_m ),
.ch5_rready_m (ch5_rready_m ),
.rom_addr_ptr (rom_addr_ptr_ff ),
.rom_data_ptr (rom_data_ptr_ff ),
.rom_data (rom_data ),
.rom_mask (rom_mask ),
.rom_ctrl (rom_ctrl ),
.cmd_out_mw (cmd_out_mw ),
.irq_out (irq_out ),
.done (done_i ),
.status (status_i )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_TB_V
`define SKY130_FD_SC_MS__FAHCON_TB_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fahcon.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CI;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT_N;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CI = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CI = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CI = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CI = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CI = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CI = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__fahcon dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT_N(COUT_N), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_TB_V
|
module var12_multi (A, B, C, D, E, F, G, H, I, J, K, L, valid);
input A, B, C, D, E, F, G, H, I, J, K, L;
output valid;
wire [7:0] min_value = 8'd107;
wire [7:0] max_weight = 8'd60;
wire [7:0] max_volume = 8'd60;
wire [7:0] total_value =
A * 8'd4
+ B * 8'd8
+ C * 8'd0
+ D * 8'd20
+ E * 8'd10
+ F * 8'd12
+ G * 8'd18
+ H * 8'd14
+ I * 8'd6
+ J * 8'd15
+ K * 8'd30
+ L * 8'd8;
wire [7:0] total_weight =
A * 8'd28
+ B * 8'd8
+ C * 8'd27
+ D * 8'd18
+ E * 8'd27
+ F * 8'd28
+ G * 8'd6
+ H * 8'd1
+ I * 8'd20
+ J * 8'd0
+ K * 8'd5
+ L * 8'd13;
wire [7:0] total_volume =
A * 8'd27
+ B * 8'd27
+ C * 8'd4
+ D * 8'd4
+ E * 8'd0
+ F * 8'd24
+ G * 8'd4
+ H * 8'd20
+ I * 8'd12
+ J * 8'd15
+ K * 8'd5
+ L * 8'd2;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
//
// usb 3.0 endpoint abstract
//
// Copyright (c) 2014 Marshall H.
// All rights reserved.
// This code is released under the terms of the simplified BSD license.
// See LICENSE.TXT for details.
//
module usb3_ep (
input wire slow_clk,
input wire local_clk,
input wire rd_clk,
input wire wr_clk,
input wire reset_n,
input wire [8:0] buf_in_addr,
input wire [31:0] buf_in_data,
input wire buf_in_wren,
output wire buf_in_request,
output wire buf_in_ready,
input wire buf_in_commit,
input wire [10:0] buf_in_commit_len,
output wire buf_in_commit_ack,
input wire [8:0] buf_out_addr,
output wire [31:0] buf_out_q,
output wire [10:0] buf_out_len,
output wire buf_out_hasdata,
input wire buf_out_arm,
output wire buf_out_arm_ack,
input wire [1:0] mode
);
`include "usb3_const.v"
// synchronizers
reg reset_1, reset_2;
reg buf_in_commit_1, buf_in_commit_2, buf_in_commit_3;
reg buf_out_arm_1, buf_out_arm_2, buf_out_arm_3;
// for keeping track of the endpoint double buffering
reg ptr_in;//, ptr_in_;
reg ptr_out;//, ptr_out_;
reg [10:0] len_in;
reg ready_in_a;
reg ready_in_b;
assign buf_in_ready = ptr_in ? ready_in_b : ready_in_a;
assign buf_in_commit_ack = (state_in == ST_IN_COMMIT || state_in == ST_IN_SWAP);
reg [10:0] len_out_a;
reg [10:0] len_out_b;
reg hasdata_out_a;
reg hasdata_out_b;
assign buf_out_len = ptr_out ? len_out_b : len_out_a;
assign buf_out_hasdata = ptr_out ? hasdata_out_b : hasdata_out_a;
assign buf_out_arm_ack = (state_out == ST_OUT_ARM || state_out == ST_OUT_SWAP);
parameter [1:0] EP_MODE_CONTROL = 2'd0,
EP_MODE_ISOCH = 2'd1,
EP_MODE_BULK = 2'd2,
EP_MODE_INTERRUPT = 2'd3;
reg [3:0] dc;
reg [5:0] state_in;
parameter [5:0] ST_RST_0 = 6'd0,
ST_RST_1 = 6'd1,
ST_IDLE = 6'd10,
ST_IN_COMMIT = 6'd11,
ST_IN_SWAP = 6'd12;
reg [5:0] state_out;
parameter [5:0] ST_OUT_ARM = 6'd11,
ST_OUT_SWAP = 6'd12;
always @(posedge local_clk) begin
// synchronizers
{reset_2, reset_1} <= {reset_1, reset_n};
{buf_in_commit_3, buf_in_commit_2, buf_in_commit_1} <=
{buf_in_commit_2, buf_in_commit_1, buf_in_commit};
{buf_out_arm_3, buf_out_arm_2, buf_out_arm_1} <=
{buf_out_arm_2, buf_out_arm_1, buf_out_arm};
dc <= dc + 1'b1;
//ptr_in_ <= ptr_in;
//ptr_out_ <= ptr_out;
// input FSM
//
case(state_in)
ST_RST_0: begin
// reset buffer index
ptr_in <= 0;
ready_in_a <= 1;
ready_in_b <= 1;
// configure default state
state_in <= ST_RST_1;
end
ST_RST_1: begin
state_in <= ST_IDLE;
end
ST_IDLE: begin
// idle state
if(buf_in_commit_2 & ~buf_in_commit_3) begin
// external device has written to this endpoint
len_in <= buf_in_commit_len;
dc <= 0;
state_in <= ST_IN_COMMIT;
end
end
ST_IN_COMMIT: begin
// generate ACK pulse, 4 cycles long for slower clock domains
if(dc == 3) begin
state_in <= ST_IN_SWAP;
end
end
ST_IN_SWAP: begin
// swap the current buffer
ptr_in <= ~ptr_in;
// current buffer is now not ready anymore
case(ptr_in)
0: ready_in_a <= 0;
1: ready_in_b <= 0;
endcase
// tell output FSM this has data
case(ptr_in)
0: hasdata_out_a <= 1;
1: hasdata_out_b <= 1;
endcase
// copy over the amount of data intended to be sent
case(ptr_in)
0: len_out_a <= len_in;
1: len_out_b <= len_in;
endcase
state_in <= ST_IDLE;
end
default: state_in <= ST_RST_0;
endcase
//////////////////////////////////////////////////////
// output FSM
//
case(state_out)
ST_RST_0: begin
// reset buffer index
ptr_out <= 0;
hasdata_out_a <= 0;
hasdata_out_b <= 0;
// configure default state
state_out <= ST_RST_1;
end
ST_RST_1: begin
state_out <= ST_IDLE;
end
ST_IDLE: begin
// idle state
if(buf_out_arm_2 & ~buf_out_arm_3) begin
// free up this endpoint
dc <= 0;
state_out <= ST_OUT_ARM;
end
end
ST_OUT_ARM: begin
// generate ARM_ACK pulse, several cycles for compat with slower FSMs
if(dc == 3) begin
state_out <= ST_OUT_SWAP;
end
end
ST_OUT_SWAP: begin
// swap the current buffer
ptr_out <= ~ptr_out;
// current buffer is now ready for data
case(ptr_out)
0: ready_in_a <= 1;
1: ready_in_b <= 1;
endcase
// update hasdata status
case(ptr_out)
0: hasdata_out_a <= 0;
1: hasdata_out_b <= 0;
endcase
state_out <= ST_IDLE;
end
default: state_out <= ST_RST_0;
endcase
if(~reset_2) begin
// reset
state_in <= ST_RST_0;
state_out <= ST_RST_0;
end
end
// endpoint bram
//
// segment the space into two 1024 byte (256 word) buffers
//
wire [9:0] rd_addr = buf_out_addr + (ptr_out ? 10'd256 : 10'h0);
wire [9:0] wr_addr = buf_in_addr + (ptr_in ? 10'd256 : 10'h0);
usb3_ep_ram iu3ep (
.rd_clk ( rd_clk ),
.rd_adr ( rd_addr ),
.rd_dat_r ( buf_out_q ),
.wr_clk ( wr_clk ),
.wr_adr ( wr_addr ),
.wr_dat_w ( buf_in_data ),
.wr_we ( buf_in_wren )
);
endmodule
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 6
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "gcd_block_design_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "gcd_block_design_processing_system7_0_2,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_\
TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WI\
DTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIF\
IABLE_TXN=0,C_GP1_EN_MODIFIABLE_TXN=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_block_design_processing_system7_0_2 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *)
input wire SDIO0_WP;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_R\
EAD_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [0 : 0] IRQ_F2P;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *)
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"),
.C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"),
.C_PACKAGE_NAME("clg400"),
.C_GP0_EN_MODIFIABLE_TXN(0),
.C_GP1_EN_MODIFIABLE_TXN(0)
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(SDIO0_WP),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
//LCD Code taken from John Loomis
//Speakers code taken from Altera
module control (
input CLOCK_50,
input CLOCK_27,
input [3:0] KEY,
input [3:0] SW,
output [17:0] LEDR,
output [7:6] LEDG,
output [2:0] GPIO_1,
output [6:0] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0,
// LCD Module 16X2
output LCD_ON,
output LCD_BLON,
output LCD_RW,
output LCD_EN,
output LCD_RS,
inout [7:0] LCD_DATA,
// Speakers
input AUD_ADCDAT,
// Bidirectionals
inout AUD_BCLK,
inout AUD_ADCLRCK,
inout AUD_DACLRCK,
inout I2C_SDAT,
// Outputs
output AUD_XCK,
output AUD_DACDAT,
output I2C_SCLK
);
// 1hz Clock
wire Clk_1hz;
clk_convert c0 (CLOCK_50, 1, 1, Clk_1hz);
// reset delay gives some time for peripherals to initialize
wire DLY_RST;
Reset_Delay r0(.iCLK(CLOCK_50),.oRESET(DLY_RST));
// turn LCD ON
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
// assignments to incorporate lcd display
LCD_Display u1(
// Host Side
.iCLK_50MHZ(CLOCK_50),
.iRST_N(DLY_RST),
.state_code(STATE),
// LCD Side
.DATA_BUS(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_E(LCD_EN),
.LCD_RS(LCD_RS)
);
// assignments to incorporate the speakers
DE2_Audio_Example ex1 (
CLOCK_50,
CLOCK_27,
AUD_ADCDAT,
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
I2C_SDAT,
AUD_XCK,
AUD_DACDAT,
I2C_SCLK,
ME
);
//Feed Beep FSM
reg [4:0] STATE;
wire O;
assign O = KEY[0];
parameter [4:0] A = 5'b00000, B = 5'b00001,
C = 5'b00010, D = 5'b00100,
E = 5'b01000, F = 5'b10000;
assign LEDR[16]=STATE[0];//enableB
assign LEDR[15]=STATE[1];//enC
assign LEDR[14]=STATE[2];//enD
assign LEDR[13]=STATE[3];//enE
assign LEDR[12]=STATE[4];//enF
//The FSM controls bellow circuit using the ones of the One-Hot-Encoding
always @(posedge O)
case(STATE)
A:
if(O) STATE=B;
else STATE=A;
B:
if(O) STATE=C;
else STATE=B;
C:
if(O) STATE=D;
else STATE=C;
D:
if(O) STATE=E;
else STATE=D;
E:
if(O) STATE=F;
else STATE=E;
F:
if(O) STATE=A;
else STATE=F;
default: STATE=5'bxxxxx;
endcase
// Operations with state dependance
wire
RExe = KEY[3], Add = KEY[1], RClk = KEY[2], SDispl = SW[0];
// Need different times.
wire [3:0] hour2, hour1, minute2, minute1, second2, second1;//initial time
wire [3:0] chour2, chour1, cminute2, cminute1, csecond2, csecond1;//current time
wire [3:0] mhour2, mhour1, mminute2, mminute1, msecond2, msecond1;//meal time
reg [3:0] dhour2, dhour1, dminute2, dminute1, dsecond2, dsecond1;//display time
// Circuits and variables for Setting Up (initial and meal) Time and Running (current time)))
//SW[5]&~SW[4] to set hours, opposite for setting minutes
set_time s0 (Add, SW[2]&(STATE[0]|STATE[2]), SW[1]&(STATE[0]|STATE[2]), hour2, hour1, minute2, minute1, second2, second1);
set_time s1 (Add, SW[2]&(STATE[0]|STATE[2]), SW[1]&(STATE[0]|STATE[2]), mhour2, mhour1, mminute2, mminute1, msecond2, msecond1);
run_clock rclk0 (RClk, Clk_1hz, hour2, hour1, minute2, minute1, second2, second1, chour2, chour1, cminute2, cminute1, csecond2, csecond1);
// Circuits and variables for Control of motor
// Motor Enable, Motor Terminal 1 & 2
wire ME, MT1, MT2;
assign LEDR[0] = ME; assign LEDG[7] = MT1; assign LEDG[6] = MT2;
assign GPIO_1[2] = ME; assign GPIO_1[1] = MT1; assign GPIO_1[0] = MT2;
reg [31:0] delay;
always @(SW[3])
if(~SW[3]) delay = 32'd100000000;
else delay = 32'd250000000;
executer e0 (CLOCK_50, KEY[3], delay, 2333333,
mhour2, mhour1, mminute2, mminute1, msecond2, msecond1,
chour2, chour1, cminute2, cminute1, csecond2, csecond1,
ME, MT1, MT2);
//Circuits for displaying time
always @ (SDispl)
if (~SDispl)
begin
dhour2 = hour2; dhour1 = hour1; dminute2 = minute2; dminute1 = minute1; dsecond2 = second2; dsecond1 = second1;
end
else
begin
dhour2 = chour2; dhour1 = chour1; dminute2 = cminute2; dminute1 = cminute1; dsecond2 = csecond2; dsecond1 = csecond1;
end
display_time d0 (dhour2, dhour1, dminute2, dminute1, dsecond2, dsecond1, HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0);
endmodule
|
module alu_chkr(clk, reset_n, opcode_valid, opcode, data, result, overflow, done, checker_enable);
parameter DATA_WIDTH = 8;
input clk;
input reset_n;
input opcode_valid;
input opcode;
input [DATA_WIDTH-1:0] data;
input result;
input overflow;
input done;
input [4:0] checker_enable;
reg [DATA_WIDTH:0] result_buf;
reg [DATA_WIDTH-1:0] data_A;
reg [DATA_WIDTH-1:0] data_B;
reg [1:0] opcode_buf;
reg chkr1_State;
reg [1:0] chkr3_State;
reg [1:0] chkr4_State;
reg [1:0] chkr5_State;
parameter chkr1_CHECK = 1'b1;
parameter chkr1_RESET = 1'b0;
parameter chkr3_OPCODE1 = 2'b00;
parameter chkr3_OPCODE2 = 2'b01;
parameter chkr3_COMPUTE = 2'b10;
parameter chkr3_CHECK = 2'b11;
parameter chkr4_OPCODE1 = 2'b00;
parameter chkr4_OPCODE2 = 2'b01;
parameter chkr4_DONE = 2'b10;
parameter chkr5_OPCODE1 = 2'b00;
parameter chkr5_OPCODE2 = 2'b01;
parameter chkr5_DONE = 2'b10;
initial
begin
chkr1_State = chkr1_RESET;
chkr3_State = chkr3_OPCODE1;
chkr4_State = chkr4_OPCODE1;
chkr5_State = chkr5_OPCODE1;
end
always @(posedge clk)
begin
//$display("opcode: %h \t opcode_valid: %h \t data: %h \t result: %h \t overflow: %h \t done: %h",opcode, opcode_valid, data, result, overflow, done);
end
//Checker 1: when reset_n is asserted (driven to 0), all outputs become 0
//within 1 clock cycle.
always @(posedge clk)
begin
case(chkr1_State)
chkr1_RESET:
begin
if(reset_n && checker_enable[0])
begin
chkr1_State = chkr1_CHECK;
end
else
begin
chkr1_State = chkr1_RESET;
end
end
chkr1_CHECK:
begin
if (!data && !overflow && !done)
begin
$display("CHECKER 1 FAILED");
end
else
begin
$display("CHECKER 1 PASSED");
end
chkr1_State = chkr1_RESET;
end
endcase
end
//Checker 2: when opcode_valid is asserted, valid opcode and valid data
//(no X or Z) must be driven on the same cycle.
always @(posedge clk)
begin
if (opcode_valid && checker_enable[1])
begin
if(opcode == "x" || data == "xxxxxxxx")
begin
$display("CHECKER 2 FAILED");
end
else if(opcode == "z" || data == "zzzzzzzz")
begin
$display("CHECKER 2 FAILED");
end
else
begin
$display("CHECKER 2 PASSED");
end
end
end
//Checker 3: Output “done” must be asserted within 2 cycles after both valid data
//have been captured.
always @(posedge clk)
begin
case(chkr3_State)
chkr3_OPCODE1:
begin
if (opcode_valid && checker_enable[2])
begin
chkr3_State = chkr3_OPCODE2;
end
else
begin
chkr3_State = chkr3_OPCODE1;
end
end
chkr3_OPCODE2:
begin
if (opcode_valid)
begin
chkr3_State = chkr3_COMPUTE;
end
else
begin
chkr3_State = chkr3_OPCODE2;
end
end
chkr3_COMPUTE:
begin
chkr3_State = chkr3_CHECK;
end
chkr3_CHECK:
begin
if (done)
begin
$display("CHECKER 3 PASSED");
chkr3_State = chkr3_OPCODE1;
end
else
begin
$display("CHECKER 3 FAILED");
chkr3_State = chkr3_OPCODE1;
end
end
endcase
end
//Checker 4: Once “done’ is asserted, output “result” must be correct
//on the same cycle.
always @(posedge clk or done or opcode_valid or result or data or overflow or checker_enable[3])
begin
case(chkr4_State)
chkr4_OPCODE1:
begin
if(opcode_valid && checker_enable[3])
begin
data_A = data;
opcode_buf[0] = opcode;
chkr4_State = chkr4_OPCODE2;
end
else
begin
chkr4_State = chkr4_OPCODE1;
end
end
chkr4_OPCODE2:
begin
if(opcode_valid)
begin
data_B = data;
opcode_buf[1] = opcode;
chkr4_State = chkr4_DONE;
end
else
begin
chkr4_State = chkr4_OPCODE2;
end
end
chkr4_DONE:
begin
if(done)
begin
case(opcode_buf)
2'b00:
begin
result_buf = data_A + data_B;
end
2'b01:
begin
result_buf = data_A - data_B;
end
2'b10:
begin
result_buf = data_A ^ data_B;
end
2'b11:
begin
result_buf = data_A ~^ data_B;
end
endcase
if (result == result_buf[DATA_WIDTH-1:0])
begin
$display("CHECKER 4 PASSED");
end
else
begin
$display("CHECKER 4 FAILED");
end
chkr4_State = chkr4_OPCODE1;
end
else
begin
chkr4_State = chkr4_OPCODE1;
end
end
endcase
end
//Checker 5: Once “done’ is asserted, output “overflow” must be correct on the
//same cycle.
always @(posedge clk or done or overflow or checker_enable[4])
begin
case(chkr5_State)
chkr5_OPCODE1:
begin
if(opcode_valid && checker_enable[3])
begin
data_A = data;
opcode_buf[0] = opcode;
chkr5_State = chkr5_OPCODE2;
end
else
begin
chkr5_State = chkr5_OPCODE1;
end
end
chkr5_OPCODE2:
begin
if(opcode_valid)
begin
data_B = data;
opcode_buf[1] = opcode;
chkr5_State = chkr5_DONE;
end
else
begin
chkr5_State = chkr5_OPCODE2;
end
end
chkr5_DONE:
begin
if(done)
begin
case(opcode_buf)
2'b00:
begin
result_buf = data_A + data_B;
end
2'b01:
begin
result_buf = data_A - data_B;
end
2'b10:
begin
result_buf = data_A ^ data_B;
end
2'b11:
begin
result_buf = data_A ~^ data_B;
end
endcase
if (overflow == result_buf[DATA_WIDTH])
begin
$display("CHECKER 5 PASSED");
end
else
begin
$display("CHECKER 5 FAILED");
end
chkr5_State = chkr5_OPCODE1;
end
else
begin
chkr5_State = chkr5_OPCODE1;
end
end
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:17:40 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112,
n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134,
n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167,
n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178,
n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266,
n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310,
n311, n312, n313, n314, n315, n316, n317, n318, n319;
NAND2X1TS U35 ( .A(n57), .B(n219), .Y(n220) );
NAND2XLTS U36 ( .A(n52), .B(n267), .Y(n268) );
NAND2XLTS U37 ( .A(n58), .B(n258), .Y(n259) );
NAND2XLTS U38 ( .A(n51), .B(n263), .Y(n264) );
NAND2XLTS U39 ( .A(n249), .B(n248), .Y(n250) );
NAND2XLTS U40 ( .A(n4), .B(n222), .Y(n223) );
NAND2X1TS U41 ( .A(n238), .B(n237), .Y(n239) );
NAND2X1TS U42 ( .A(n245), .B(n244), .Y(n246) );
NAND2X1TS U43 ( .A(n231), .B(n230), .Y(n232) );
CMPR32X2TS U44 ( .A(in1[6]), .B(n100), .C(n79), .CO(n77), .S(res[6]) );
INVX2TS U45 ( .A(n274), .Y(n281) );
OR2X2TS U46 ( .A(n205), .B(in1[29]), .Y(n4) );
NAND2X2TS U47 ( .A(n197), .B(in1[26]), .Y(n244) );
NOR2X2TS U48 ( .A(n196), .B(in1[25]), .Y(n241) );
NAND2X2TS U49 ( .A(n198), .B(in1[27]), .Y(n237) );
NAND2X2TS U50 ( .A(n199), .B(in1[28]), .Y(n230) );
NAND2X2TS U51 ( .A(n206), .B(in1[30]), .Y(n219) );
CLKMX2X2TS U52 ( .A(in2[30]), .B(n202), .S0(n212), .Y(n206) );
NOR2X1TS U53 ( .A(n210), .B(in2[30]), .Y(n211) );
NOR2X2TS U54 ( .A(n288), .B(n283), .Y(n165) );
OR2X4TS U55 ( .A(n190), .B(in1[22]), .Y(n52) );
NAND2XLTS U56 ( .A(n12), .B(in2[28]), .Y(n26) );
OAI21X2TS U57 ( .A0(n7), .A1(n12), .B0(n6), .Y(n314) );
XNOR2X1TS U58 ( .A(n203), .B(in2[29]), .Y(n204) );
XNOR2X2TS U59 ( .A(n132), .B(in2[26]), .Y(n133) );
XNOR2X1TS U60 ( .A(n124), .B(in2[27]), .Y(n125) );
XOR2X2TS U61 ( .A(n28), .B(in2[28]), .Y(n27) );
NOR2X1TS U62 ( .A(n201), .B(n126), .Y(n124) );
MX2X2TS U63 ( .A(in2[21]), .B(n181), .S0(add_sub), .Y(n189) );
NOR2BX2TS U64 ( .AN(n131), .B(n200), .Y(n28) );
NAND2X6TS U65 ( .A(n16), .B(n296), .Y(n14) );
NAND2BX2TS U66 ( .AN(in2[29]), .B(n203), .Y(n210) );
NOR2X2TS U67 ( .A(n201), .B(in2[24]), .Y(n127) );
XNOR2X1TS U68 ( .A(n65), .B(in2[3]), .Y(n7) );
NAND2XLTS U69 ( .A(n12), .B(in2[23]), .Y(n43) );
OA21X2TS U70 ( .A0(n13), .A1(n12), .B0(n11), .Y(n155) );
XNOR2X2TS U71 ( .A(n166), .B(in2[18]), .Y(n160) );
XNOR2X2TS U72 ( .A(n182), .B(in2[20]), .Y(n171) );
XNOR2X1TS U73 ( .A(n201), .B(in2[24]), .Y(n178) );
XOR2X2TS U74 ( .A(n45), .B(in2[23]), .Y(n44) );
INVX2TS U75 ( .A(in2[4]), .Y(n71) );
NOR2X2TS U76 ( .A(n166), .B(in2[18]), .Y(n167) );
NAND2X2TS U77 ( .A(n184), .B(n183), .Y(n185) );
INVX2TS U78 ( .A(in2[21]), .Y(n3) );
NOR2X4TS U79 ( .A(n182), .B(in2[20]), .Y(n180) );
CLKINVX2TS U80 ( .A(n182), .Y(n184) );
NOR2X4TS U81 ( .A(n65), .B(in2[3]), .Y(n72) );
NAND2X1TS U82 ( .A(n130), .B(n134), .Y(n126) );
INVX4TS U83 ( .A(n170), .Y(n156) );
NOR2X2TS U84 ( .A(in2[25]), .B(in2[24]), .Y(n130) );
NAND3X1TS U85 ( .A(n151), .B(n150), .C(n149), .Y(n152) );
NOR2X6TS U86 ( .A(n142), .B(in1[13]), .Y(n145) );
AND2X2TS U87 ( .A(n159), .B(n122), .Y(n169) );
NAND2X2TS U88 ( .A(n142), .B(in1[13]), .Y(n143) );
NAND2X4TS U89 ( .A(n151), .B(n150), .Y(n146) );
XOR2X2TS U90 ( .A(n151), .B(in2[12]), .Y(n112) );
BUFX12TS U91 ( .A(add_sub), .Y(n186) );
NAND2X6TS U92 ( .A(n50), .B(n47), .Y(n98) );
CLKINVX6TS U93 ( .A(n110), .Y(n47) );
CLKINVX6TS U94 ( .A(n109), .Y(n50) );
NOR2X6TS U95 ( .A(in2[3]), .B(in2[2]), .Y(n48) );
CLKINVX6TS U96 ( .A(in2[8]), .Y(n93) );
NOR2XLTS U97 ( .A(in2[23]), .B(in2[22]), .Y(n123) );
NOR2XLTS U98 ( .A(in2[19]), .B(in2[18]), .Y(n122) );
NAND2X4TS U99 ( .A(n93), .B(n92), .Y(n109) );
NOR2X2TS U100 ( .A(n182), .B(n46), .Y(n45) );
NOR2X6TS U101 ( .A(in2[7]), .B(in2[6]), .Y(n49) );
MXI2X2TS U102 ( .A(n149), .B(n147), .S0(n186), .Y(n148) );
MXI2X2TS U103 ( .A(n179), .B(n178), .S0(n186), .Y(n194) );
NOR2X4TS U104 ( .A(n198), .B(in1[27]), .Y(n236) );
NOR2XLTS U105 ( .A(in1[7]), .B(n102), .Y(n87) );
NOR2X4TS U106 ( .A(in1[11]), .B(n137), .Y(n140) );
NAND2X2TS U107 ( .A(n40), .B(n299), .Y(n21) );
NAND2X1TS U108 ( .A(n205), .B(in1[29]), .Y(n222) );
XOR2X1TS U109 ( .A(in1[11]), .B(n106), .Y(n107) );
OAI21XLTS U110 ( .A0(n292), .A1(n288), .B0(n289), .Y(n287) );
INVX4TS U111 ( .A(n224), .Y(n251) );
ADDHXLTS U112 ( .A(in2[0]), .B(in1[0]), .CO(n311), .S(res[0]) );
BUFX4TS U113 ( .A(add_sub), .Y(n212) );
INVX4TS U114 ( .A(n186), .Y(n12) );
INVX2TS U115 ( .A(n219), .Y(n207) );
XOR2X2TS U116 ( .A(in1[9]), .B(n89), .Y(n90) );
OR2X4TS U117 ( .A(n194), .B(in1[24]), .Y(n58) );
NOR2X4TS U118 ( .A(n156), .B(in2[16]), .Y(n157) );
MX2X4TS U119 ( .A(in2[5]), .B(n74), .S0(add_sub), .Y(n319) );
INVX6TS U120 ( .A(in2[2]), .Y(n68) );
NOR2X2TS U121 ( .A(n306), .B(n303), .Y(n307) );
NOR2X4TS U122 ( .A(n38), .B(n262), .Y(n37) );
OAI21X2TS U123 ( .A0(n229), .A1(n237), .B0(n230), .Y(n32) );
INVX2TS U124 ( .A(n229), .Y(n231) );
INVX2TS U125 ( .A(n243), .Y(n245) );
INVX2TS U126 ( .A(n236), .Y(n238) );
OR2X4TS U127 ( .A(n206), .B(in1[30]), .Y(n57) );
NAND2X4TS U128 ( .A(n196), .B(in1[25]), .Y(n248) );
XNOR2X1TS U129 ( .A(n211), .B(in2[31]), .Y(n213) );
NAND2X4TS U130 ( .A(n189), .B(in1[21]), .Y(n270) );
OR2X4TS U131 ( .A(n193), .B(in1[23]), .Y(n51) );
NOR2X4TS U132 ( .A(n189), .B(in1[21]), .Y(n266) );
NAND2X4TS U133 ( .A(n173), .B(in1[19]), .Y(n279) );
MX2X2TS U134 ( .A(in2[29]), .B(n204), .S0(add_sub), .Y(n205) );
NOR3X4TS U135 ( .A(n201), .B(in2[28]), .C(n200), .Y(n203) );
OAI2BB1X2TS U136 ( .A0N(n102), .A1N(in1[7]), .B0(n101), .Y(n103) );
OAI211X2TS U137 ( .A0(in1[7]), .A1(n102), .B0(n100), .C0(in1[6]), .Y(n101)
);
NAND2X6TS U138 ( .A(n170), .B(n29), .Y(n201) );
NAND2X2TS U139 ( .A(n141), .B(in1[12]), .Y(n144) );
MX2X4TS U140 ( .A(in2[7]), .B(n60), .S0(add_sub), .Y(n102) );
OAI21X2TS U141 ( .A0(n273), .A1(n266), .B0(n270), .Y(n269) );
XOR2X1TS U142 ( .A(n273), .B(n272), .Y(res[21]) );
XOR2X1TS U143 ( .A(n278), .B(n277), .Y(res[20]) );
XOR2X1TS U144 ( .A(n292), .B(n291), .Y(res[17]) );
NAND2X2TS U145 ( .A(n215), .B(n304), .Y(n216) );
OA21X2TS U146 ( .A0(n306), .A1(n305), .B0(n304), .Y(n5) );
NAND2X2TS U147 ( .A(n214), .B(in1[31]), .Y(n304) );
MX2X2TS U148 ( .A(in2[31]), .B(n213), .S0(n212), .Y(n214) );
NAND2X4TS U149 ( .A(n51), .B(n58), .Y(n38) );
OR2X4TS U150 ( .A(n173), .B(in1[19]), .Y(n55) );
XOR2X1TS U151 ( .A(n302), .B(n301), .Y(res[14]) );
MX2X2TS U152 ( .A(in2[17]), .B(n158), .S0(add_sub), .Y(n162) );
NAND2X2TS U153 ( .A(n174), .B(in1[20]), .Y(n276) );
NAND2X2TS U154 ( .A(n194), .B(in1[24]), .Y(n258) );
NAND2X2TS U155 ( .A(n163), .B(in1[18]), .Y(n284) );
OR2X4TS U156 ( .A(n155), .B(in1[16]), .Y(n293) );
XOR2X2TS U157 ( .A(n77), .B(in1[7]), .Y(n78) );
NAND2X2TS U158 ( .A(n148), .B(in1[14]), .Y(n300) );
OR2X4TS U159 ( .A(n148), .B(in1[14]), .Y(n299) );
XOR2X1TS U160 ( .A(n319), .B(n318), .Y(res[5]) );
OAI2BB1X2TS U161 ( .A0N(n319), .A1N(in1[5]), .B0(n85), .Y(n86) );
OAI211X1TS U162 ( .A0(in1[5]), .A1(n319), .B0(n316), .C0(in1[4]), .Y(n85) );
MXI2X4TS U163 ( .A(n113), .B(n112), .S0(n186), .Y(n141) );
XNOR2X2TS U164 ( .A(n59), .B(in2[7]), .Y(n60) );
OAI2BB1X2TS U165 ( .A0N(n314), .A1N(in1[3]), .B0(n69), .Y(n70) );
XOR2X2TS U166 ( .A(n73), .B(in2[5]), .Y(n74) );
NAND2X2TS U167 ( .A(n72), .B(n71), .Y(n73) );
NAND2BX2TS U168 ( .AN(n66), .B(n12), .Y(n6) );
AND2X4TS U169 ( .A(n169), .B(n30), .Y(n29) );
NOR2X1TS U170 ( .A(n212), .B(n20), .Y(n19) );
CLKMX2X2TS U171 ( .A(in2[1]), .B(n308), .S0(add_sub), .Y(n312) );
INVX12TS U172 ( .A(in2[9]), .Y(n92) );
NAND2X4TS U173 ( .A(n271), .B(n52), .Y(n262) );
NAND2X2TS U174 ( .A(n8), .B(n5), .Y(res[32]) );
XOR2X4TS U175 ( .A(n180), .B(n3), .Y(n181) );
NAND2X2TS U176 ( .A(n18), .B(n17), .Y(n54) );
AOI21X2TS U177 ( .A0(n275), .A1(n53), .B0(n175), .Y(n176) );
NAND2X6TS U178 ( .A(n136), .B(in1[10]), .Y(n139) );
NAND2X4TS U179 ( .A(n50), .B(n25), .Y(n24) );
NAND2X2TS U180 ( .A(n151), .B(n113), .Y(n23) );
OAI21X4TS U181 ( .A0(n44), .A1(n12), .B0(n43), .Y(n193) );
MXI2X4TS U182 ( .A(n161), .B(n160), .S0(n186), .Y(n163) );
AOI21X2TS U183 ( .A0(n153), .A1(n212), .B0(n19), .Y(n18) );
AOI222X2TS U184 ( .A0(n100), .A1(in1[6]), .B0(n100), .B1(n86), .C0(in1[6]),
.C1(n86), .Y(n88) );
NAND2X4TS U185 ( .A(n80), .B(n68), .Y(n65) );
XOR2X1TS U186 ( .A(n137), .B(n107), .Y(res[11]) );
AOI222X2TS U187 ( .A0(n114), .A1(in1[8]), .B0(n114), .B1(n103), .C0(in1[8]),
.C1(n103), .Y(n105) );
NAND2X4TS U188 ( .A(n155), .B(in1[16]), .Y(n294) );
AOI21X4TS U189 ( .A0(n254), .A1(n58), .B0(n195), .Y(n36) );
NAND2X2TS U190 ( .A(n193), .B(in1[23]), .Y(n263) );
NAND2X8TS U191 ( .A(n294), .B(n10), .Y(n282) );
MXI2X4TS U192 ( .A(n96), .B(n95), .S0(n12), .Y(n137) );
XOR2X4TS U193 ( .A(n94), .B(in2[11]), .Y(n96) );
NOR2X4TS U194 ( .A(n98), .B(in2[10]), .Y(n94) );
OAI21X2TS U195 ( .A0(n273), .A1(n257), .B0(n256), .Y(n260) );
OAI21X2TS U196 ( .A0(n273), .A1(n262), .B0(n261), .Y(n265) );
XNOR2X4TS U197 ( .A(n157), .B(in2[17]), .Y(n158) );
AND2X2TS U198 ( .A(n123), .B(n183), .Y(n30) );
MXI2X4TS U199 ( .A(n97), .B(n99), .S0(n186), .Y(n136) );
XOR2X1TS U200 ( .A(n98), .B(n97), .Y(n99) );
NAND2X2TS U201 ( .A(n137), .B(in1[11]), .Y(n138) );
NOR2X2TS U202 ( .A(n141), .B(in1[12]), .Y(n135) );
NOR2X4TS U203 ( .A(n197), .B(in1[26]), .Y(n243) );
XOR2X1TS U204 ( .A(n152), .B(in2[15]), .Y(n153) );
INVX2TS U205 ( .A(in2[15]), .Y(n20) );
NAND2X1TS U206 ( .A(n12), .B(n154), .Y(n11) );
XNOR2X1TS U207 ( .A(n170), .B(in2[16]), .Y(n13) );
NAND3X6TS U208 ( .A(n22), .B(n21), .C(n300), .Y(n298) );
NAND3X4TS U209 ( .A(n42), .B(n39), .C(n299), .Y(n22) );
INVX2TS U210 ( .A(in1[15]), .Y(n17) );
NAND2X2TS U211 ( .A(n15), .B(in1[15]), .Y(n296) );
INVX2TS U212 ( .A(n18), .Y(n15) );
INVX2TS U213 ( .A(n241), .Y(n249) );
INVX2TS U214 ( .A(n222), .Y(n218) );
INVX2TS U215 ( .A(n303), .Y(n209) );
INVX2TS U216 ( .A(n305), .Y(n208) );
NAND2X2TS U217 ( .A(n57), .B(n4), .Y(n303) );
NOR2X4TS U218 ( .A(n214), .B(in1[31]), .Y(n306) );
NAND2X2TS U219 ( .A(n34), .B(n235), .Y(n33) );
AOI21X2TS U220 ( .A0(n34), .A1(n234), .B0(n32), .Y(n31) );
NOR2X4TS U221 ( .A(n229), .B(n236), .Y(n34) );
NAND2BX1TS U222 ( .AN(in2[22]), .B(n183), .Y(n46) );
NAND2X4TS U223 ( .A(n170), .B(n169), .Y(n182) );
INVX2TS U224 ( .A(n258), .Y(n195) );
NAND2X4TS U225 ( .A(n81), .B(n72), .Y(n61) );
NOR2X2TS U226 ( .A(in2[11]), .B(in2[10]), .Y(n25) );
INVX2TS U227 ( .A(n263), .Y(n254) );
NAND2X1TS U228 ( .A(n55), .B(n53), .Y(n177) );
NAND2X2TS U229 ( .A(n131), .B(n130), .Y(n132) );
NOR2X4TS U230 ( .A(n163), .B(in1[18]), .Y(n283) );
NOR2X4TS U231 ( .A(n162), .B(in1[17]), .Y(n288) );
NAND2X2TS U232 ( .A(n162), .B(in1[17]), .Y(n289) );
INVX2TS U233 ( .A(n282), .Y(n292) );
INVX2TS U234 ( .A(n279), .Y(n275) );
OR2X2TS U235 ( .A(n174), .B(in1[20]), .Y(n53) );
INVX2TS U236 ( .A(n266), .Y(n271) );
INVX2TS U237 ( .A(n267), .Y(n191) );
INVX2TS U238 ( .A(n270), .Y(n192) );
INVX2TS U239 ( .A(n262), .Y(n253) );
AOI21X1TS U240 ( .A0(n255), .A1(n51), .B0(n254), .Y(n256) );
INVX2TS U241 ( .A(n261), .Y(n255) );
INVX2TS U242 ( .A(n252), .Y(n273) );
INVX2TS U243 ( .A(n248), .Y(n242) );
NOR2X4TS U244 ( .A(n241), .B(n243), .Y(n235) );
NOR2X4TS U245 ( .A(n199), .B(in1[28]), .Y(n229) );
OAI21X1TS U246 ( .A0(n226), .A1(n236), .B0(n237), .Y(n227) );
NOR2X1TS U247 ( .A(n225), .B(n236), .Y(n228) );
INVX2TS U248 ( .A(n235), .Y(n225) );
XOR2X1TS U249 ( .A(in1[13]), .B(n119), .Y(n120) );
NAND2X1TS U250 ( .A(n299), .B(n300), .Y(n301) );
AOI21X1TS U251 ( .A0(n41), .A1(n42), .B0(n40), .Y(n302) );
OAI21XLTS U252 ( .A0(n140), .A1(n139), .B0(n138), .Y(n41) );
NAND2X1TS U253 ( .A(n54), .B(n296), .Y(n297) );
NAND2X1TS U254 ( .A(n293), .B(n294), .Y(n295) );
NAND2X1TS U255 ( .A(n290), .B(n289), .Y(n291) );
INVX2TS U256 ( .A(n288), .Y(n290) );
XNOR2X1TS U257 ( .A(n287), .B(n286), .Y(res[18]) );
NAND2X1TS U258 ( .A(n285), .B(n284), .Y(n286) );
INVX2TS U259 ( .A(n283), .Y(n285) );
NAND2X1TS U260 ( .A(n55), .B(n279), .Y(n280) );
NAND2X1TS U261 ( .A(n53), .B(n276), .Y(n277) );
AOI21X1TS U262 ( .A0(n281), .A1(n55), .B0(n275), .Y(n278) );
NAND2X1TS U263 ( .A(n271), .B(n270), .Y(n272) );
XNOR2X1TS U264 ( .A(n265), .B(n264), .Y(res[23]) );
XNOR2X1TS U265 ( .A(n260), .B(n259), .Y(res[24]) );
NAND2X1TS U266 ( .A(n253), .B(n51), .Y(n257) );
XNOR2X1TS U267 ( .A(n251), .B(n250), .Y(res[25]) );
INVX2TS U268 ( .A(n306), .Y(n215) );
OAI2BB2X1TS U269 ( .B0(n76), .B1(n75), .A0N(in1[5]), .A1N(n319), .Y(n79) );
NAND2X4TS U270 ( .A(n298), .B(n54), .Y(n16) );
INVX2TS U271 ( .A(n201), .Y(n131) );
OAI2BB2X1TS U272 ( .B0(n88), .B1(n87), .A0N(in1[7]), .A1N(n102), .Y(n91) );
MXI2X4TS U273 ( .A(n63), .B(n62), .S0(n212), .Y(n100) );
XNOR2X1TS U274 ( .A(n61), .B(in2[6]), .Y(n62) );
MXI2X4TS U275 ( .A(n93), .B(n84), .S0(n186), .Y(n114) );
OAI21X4TS U276 ( .A0(n224), .A1(n33), .B0(n31), .Y(n9) );
AOI21X4TS U277 ( .A0(n9), .A1(n209), .B0(n208), .Y(n217) );
AOI21X4TS U278 ( .A0(n9), .A1(n4), .B0(n218), .Y(n221) );
NAND2X2TS U279 ( .A(n9), .B(n307), .Y(n8) );
XNOR2X1TS U280 ( .A(n9), .B(n223), .Y(res[29]) );
NOR2X8TS U281 ( .A(in2[0]), .B(in2[1]), .Y(n80) );
NAND2X8TS U282 ( .A(n14), .B(n293), .Y(n10) );
XOR2X4TS U283 ( .A(n23), .B(in2[13]), .Y(n111) );
NOR2X8TS U284 ( .A(n24), .B(n110), .Y(n151) );
NAND2X4TS U285 ( .A(n170), .B(n159), .Y(n166) );
OAI21X4TS U286 ( .A0(n27), .A1(n12), .B0(n26), .Y(n199) );
OAI21X4TS U287 ( .A0(n274), .A1(n177), .B0(n176), .Y(n252) );
AOI21X4TS U288 ( .A0(n282), .A1(n165), .B0(n164), .Y(n274) );
AOI21X4TS U289 ( .A0(n252), .A1(n37), .B0(n35), .Y(n224) );
OAI21X4TS U290 ( .A0(n261), .A1(n38), .B0(n36), .Y(n35) );
AOI21X4TS U291 ( .A0(n192), .A1(n52), .B0(n191), .Y(n261) );
NOR2X4TS U292 ( .A(n145), .B(n135), .Y(n42) );
OAI21X4TS U293 ( .A0(n140), .A1(n139), .B0(n138), .Y(n39) );
OAI21X4TS U294 ( .A0(n145), .A1(n144), .B0(n143), .Y(n40) );
NAND4X8TS U295 ( .A(n80), .B(n49), .C(n81), .D(n48), .Y(n110) );
ADDFHX2TS U296 ( .A(in1[8]), .B(n114), .CI(n91), .CO(n89), .S(res[8]) );
ADDFHX2TS U297 ( .A(in1[12]), .B(n141), .CI(n121), .CO(n119), .S(res[12]) );
MXI2X8TS U298 ( .A(n92), .B(n83), .S0(n212), .Y(n116) );
XOR2X1TS U299 ( .A(n233), .B(n232), .Y(res[28]) );
XOR2X1TS U300 ( .A(n247), .B(n246), .Y(res[26]) );
XOR2X1TS U301 ( .A(n240), .B(n239), .Y(res[27]) );
MXI2X4TS U302 ( .A(n172), .B(n171), .S0(n186), .Y(n174) );
ADDFHX2TS U303 ( .A(in1[10]), .B(n136), .CI(n108), .CO(n106), .S(res[10]) );
MX2X4TS U304 ( .A(in2[19]), .B(n168), .S0(add_sub), .Y(n173) );
XNOR2X1TS U305 ( .A(n298), .B(n297), .Y(res[15]) );
NAND2X4TS U306 ( .A(n190), .B(in1[22]), .Y(n267) );
MXI2X2TS U307 ( .A(n68), .B(n67), .S0(n212), .Y(n310) );
MXI2X4TS U308 ( .A(n71), .B(n64), .S0(n212), .Y(n316) );
MX2X4TS U309 ( .A(in2[27]), .B(n125), .S0(add_sub), .Y(n198) );
AOI222X2TS U310 ( .A0(n136), .A1(in1[10]), .B0(n136), .B1(n117), .C0(in1[10]), .C1(n117), .Y(n118) );
OAI2BB1X4TS U311 ( .A0N(n116), .A1N(in1[9]), .B0(n115), .Y(n117) );
XNOR2X4TS U312 ( .A(n167), .B(in2[19]), .Y(n168) );
XNOR2X4TS U313 ( .A(n146), .B(in2[14]), .Y(n147) );
NOR2X8TS U314 ( .A(in2[5]), .B(in2[4]), .Y(n81) );
OAI2BB2X1TS U315 ( .B0(n118), .B1(n140), .A0N(in1[11]), .A1N(n137), .Y(n121)
);
NOR2X4TS U316 ( .A(n61), .B(in2[6]), .Y(n59) );
MXI2X4TS U317 ( .A(n188), .B(n187), .S0(n186), .Y(n190) );
XNOR2X4TS U318 ( .A(n185), .B(in2[22]), .Y(n187) );
MX2X4TS U319 ( .A(in2[13]), .B(n111), .S0(n212), .Y(n142) );
OAI2BB2X2TS U320 ( .B0(n105), .B1(n104), .A0N(in1[9]), .A1N(n116), .Y(n108)
);
XNOR2X4TS U321 ( .A(n82), .B(n92), .Y(n83) );
NOR3X8TS U322 ( .A(n146), .B(in2[15]), .C(in2[14]), .Y(n170) );
INVX2TS U323 ( .A(n276), .Y(n175) );
INVX2TS U324 ( .A(in2[6]), .Y(n63) );
XNOR2X1TS U325 ( .A(n72), .B(n71), .Y(n64) );
INVX2TS U326 ( .A(in2[3]), .Y(n66) );
XNOR2X1TS U327 ( .A(n80), .B(n68), .Y(n67) );
OAI211X1TS U328 ( .A0(in1[3]), .A1(n314), .B0(n310), .C0(in1[2]), .Y(n69) );
AOI222X1TS U329 ( .A0(n316), .A1(in1[4]), .B0(n316), .B1(n70), .C0(in1[4]),
.C1(n70), .Y(n76) );
NOR2X1TS U330 ( .A(in1[5]), .B(n319), .Y(n75) );
XOR2X1TS U331 ( .A(n102), .B(n78), .Y(res[7]) );
NOR2X1TS U332 ( .A(in2[8]), .B(n110), .Y(n82) );
XNOR2X1TS U333 ( .A(n110), .B(in2[8]), .Y(n84) );
XOR2X1TS U334 ( .A(n116), .B(n90), .Y(res[9]) );
INVX2TS U335 ( .A(in2[11]), .Y(n95) );
INVX2TS U336 ( .A(in2[10]), .Y(n97) );
NOR2X1TS U337 ( .A(in1[9]), .B(n116), .Y(n104) );
INVX2TS U338 ( .A(in2[12]), .Y(n113) );
OAI211X1TS U339 ( .A0(in1[9]), .A1(n116), .B0(n114), .C0(in1[8]), .Y(n115)
);
XOR2X1TS U340 ( .A(n142), .B(n120), .Y(res[13]) );
NOR2X2TS U341 ( .A(in2[13]), .B(in2[12]), .Y(n150) );
NOR2X2TS U342 ( .A(in2[17]), .B(in2[16]), .Y(n159) );
NOR2X2TS U343 ( .A(in2[21]), .B(in2[20]), .Y(n183) );
INVX2TS U344 ( .A(in2[26]), .Y(n134) );
OR2X2TS U345 ( .A(n126), .B(in2[27]), .Y(n200) );
XOR2X1TS U346 ( .A(n127), .B(in2[25]), .Y(n129) );
INVX2TS U347 ( .A(in2[25]), .Y(n128) );
MXI2X4TS U348 ( .A(n129), .B(n128), .S0(n12), .Y(n196) );
MXI2X4TS U349 ( .A(n134), .B(n133), .S0(n186), .Y(n197) );
INVX2TS U350 ( .A(in2[14]), .Y(n149) );
INVX2TS U351 ( .A(in2[16]), .Y(n154) );
INVX2TS U352 ( .A(in2[18]), .Y(n161) );
OAI21X4TS U353 ( .A0(n289), .A1(n283), .B0(n284), .Y(n164) );
INVX2TS U354 ( .A(in2[20]), .Y(n172) );
INVX2TS U355 ( .A(in2[24]), .Y(n179) );
INVX2TS U356 ( .A(in2[22]), .Y(n188) );
OAI21X4TS U357 ( .A0(n243), .A1(n248), .B0(n244), .Y(n234) );
XOR2X1TS U358 ( .A(n210), .B(in2[30]), .Y(n202) );
AOI21X4TS U359 ( .A0(n57), .A1(n218), .B0(n207), .Y(n305) );
XOR2X4TS U360 ( .A(n217), .B(n216), .Y(res[31]) );
XOR2X4TS U361 ( .A(n221), .B(n220), .Y(res[30]) );
INVX2TS U362 ( .A(n234), .Y(n226) );
AOI21X4TS U363 ( .A0(n251), .A1(n228), .B0(n227), .Y(n233) );
AOI21X4TS U364 ( .A0(n251), .A1(n235), .B0(n234), .Y(n240) );
AOI21X4TS U365 ( .A0(n251), .A1(n249), .B0(n242), .Y(n247) );
XNOR2X1TS U366 ( .A(n269), .B(n268), .Y(res[22]) );
XNOR2X1TS U367 ( .A(n281), .B(n280), .Y(res[19]) );
XNOR2X1TS U368 ( .A(n14), .B(n295), .Y(res[16]) );
XOR2X1TS U369 ( .A(in2[0]), .B(in2[1]), .Y(n308) );
CMPR32X2TS U370 ( .A(in1[2]), .B(n310), .C(n309), .CO(n313), .S(res[2]) );
CMPR32X2TS U371 ( .A(in1[1]), .B(n312), .C(n311), .CO(n309), .S(res[1]) );
CMPR32X2TS U372 ( .A(in1[3]), .B(n314), .C(n313), .CO(n315), .S(res[3]) );
CMPR32X2TS U373 ( .A(in1[4]), .B(n316), .C(n315), .CO(n317), .S(res[4]) );
XOR2X1TS U374 ( .A(in1[5]), .B(n317), .Y(n318) );
initial $sdf_annotate("Approx_adder_GeArN16R2P4_syn.sdf");
endmodule
|
//-----------------------------------------------------------------------------
// system_axi4lite_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "axi_interconnect_v1_06_a" *)
module system_axi4lite_0_wrapper
(
INTERCONNECT_ACLK,
INTERCONNECT_ARESETN,
S_AXI_ARESET_OUT_N,
M_AXI_ARESET_OUT_N,
IRQ,
S_AXI_ACLK,
S_AXI_AWID,
S_AXI_AWADDR,
S_AXI_AWLEN,
S_AXI_AWSIZE,
S_AXI_AWBURST,
S_AXI_AWLOCK,
S_AXI_AWCACHE,
S_AXI_AWPROT,
S_AXI_AWQOS,
S_AXI_AWUSER,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WLAST,
S_AXI_WUSER,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BID,
S_AXI_BRESP,
S_AXI_BUSER,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARID,
S_AXI_ARADDR,
S_AXI_ARLEN,
S_AXI_ARSIZE,
S_AXI_ARBURST,
S_AXI_ARLOCK,
S_AXI_ARCACHE,
S_AXI_ARPROT,
S_AXI_ARQOS,
S_AXI_ARUSER,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RID,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RLAST,
S_AXI_RUSER,
S_AXI_RVALID,
S_AXI_RREADY,
M_AXI_ACLK,
M_AXI_AWID,
M_AXI_AWADDR,
M_AXI_AWLEN,
M_AXI_AWSIZE,
M_AXI_AWBURST,
M_AXI_AWLOCK,
M_AXI_AWCACHE,
M_AXI_AWPROT,
M_AXI_AWREGION,
M_AXI_AWQOS,
M_AXI_AWUSER,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WID,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WLAST,
M_AXI_WUSER,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BID,
M_AXI_BRESP,
M_AXI_BUSER,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARID,
M_AXI_ARADDR,
M_AXI_ARLEN,
M_AXI_ARSIZE,
M_AXI_ARBURST,
M_AXI_ARLOCK,
M_AXI_ARCACHE,
M_AXI_ARPROT,
M_AXI_ARREGION,
M_AXI_ARQOS,
M_AXI_ARUSER,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RID,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RLAST,
M_AXI_RUSER,
M_AXI_RVALID,
M_AXI_RREADY,
S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA,
S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY,
INTERCONNECT_ARESET_OUT_N,
DEBUG_AW_TRANS_SEQ,
DEBUG_AW_ARB_GRANT,
DEBUG_AR_TRANS_SEQ,
DEBUG_AR_ARB_GRANT,
DEBUG_AW_TRANS_QUAL,
DEBUG_AW_ACCEPT_CNT,
DEBUG_AW_ACTIVE_THREAD,
DEBUG_AW_ACTIVE_TARGET,
DEBUG_AW_ACTIVE_REGION,
DEBUG_AW_ERROR,
DEBUG_AW_TARGET,
DEBUG_AR_TRANS_QUAL,
DEBUG_AR_ACCEPT_CNT,
DEBUG_AR_ACTIVE_THREAD,
DEBUG_AR_ACTIVE_TARGET,
DEBUG_AR_ACTIVE_REGION,
DEBUG_AR_ERROR,
DEBUG_AR_TARGET,
DEBUG_B_TRANS_SEQ,
DEBUG_R_BEAT_CNT,
DEBUG_R_TRANS_SEQ,
DEBUG_AW_ISSUING_CNT,
DEBUG_AR_ISSUING_CNT,
DEBUG_W_BEAT_CNT,
DEBUG_W_TRANS_SEQ,
DEBUG_BID_TARGET,
DEBUG_BID_ERROR,
DEBUG_RID_TARGET,
DEBUG_RID_ERROR,
DEBUG_SR_SC_ARADDR,
DEBUG_SR_SC_ARADDRCONTROL,
DEBUG_SR_SC_AWADDR,
DEBUG_SR_SC_AWADDRCONTROL,
DEBUG_SR_SC_BRESP,
DEBUG_SR_SC_RDATA,
DEBUG_SR_SC_RDATACONTROL,
DEBUG_SR_SC_WDATA,
DEBUG_SR_SC_WDATACONTROL,
DEBUG_SC_SF_ARADDR,
DEBUG_SC_SF_ARADDRCONTROL,
DEBUG_SC_SF_AWADDR,
DEBUG_SC_SF_AWADDRCONTROL,
DEBUG_SC_SF_BRESP,
DEBUG_SC_SF_RDATA,
DEBUG_SC_SF_RDATACONTROL,
DEBUG_SC_SF_WDATA,
DEBUG_SC_SF_WDATACONTROL,
DEBUG_SF_CB_ARADDR,
DEBUG_SF_CB_ARADDRCONTROL,
DEBUG_SF_CB_AWADDR,
DEBUG_SF_CB_AWADDRCONTROL,
DEBUG_SF_CB_BRESP,
DEBUG_SF_CB_RDATA,
DEBUG_SF_CB_RDATACONTROL,
DEBUG_SF_CB_WDATA,
DEBUG_SF_CB_WDATACONTROL,
DEBUG_CB_MF_ARADDR,
DEBUG_CB_MF_ARADDRCONTROL,
DEBUG_CB_MF_AWADDR,
DEBUG_CB_MF_AWADDRCONTROL,
DEBUG_CB_MF_BRESP,
DEBUG_CB_MF_RDATA,
DEBUG_CB_MF_RDATACONTROL,
DEBUG_CB_MF_WDATA,
DEBUG_CB_MF_WDATACONTROL,
DEBUG_MF_MC_ARADDR,
DEBUG_MF_MC_ARADDRCONTROL,
DEBUG_MF_MC_AWADDR,
DEBUG_MF_MC_AWADDRCONTROL,
DEBUG_MF_MC_BRESP,
DEBUG_MF_MC_RDATA,
DEBUG_MF_MC_RDATACONTROL,
DEBUG_MF_MC_WDATA,
DEBUG_MF_MC_WDATACONTROL,
DEBUG_MC_MP_ARADDR,
DEBUG_MC_MP_ARADDRCONTROL,
DEBUG_MC_MP_AWADDR,
DEBUG_MC_MP_AWADDRCONTROL,
DEBUG_MC_MP_BRESP,
DEBUG_MC_MP_RDATA,
DEBUG_MC_MP_RDATACONTROL,
DEBUG_MC_MP_WDATA,
DEBUG_MC_MP_WDATACONTROL,
DEBUG_MP_MR_ARADDR,
DEBUG_MP_MR_ARADDRCONTROL,
DEBUG_MP_MR_AWADDR,
DEBUG_MP_MR_AWADDRCONTROL,
DEBUG_MP_MR_BRESP,
DEBUG_MP_MR_RDATA,
DEBUG_MP_MR_RDATACONTROL,
DEBUG_MP_MR_WDATA,
DEBUG_MP_MR_WDATACONTROL
);
input INTERCONNECT_ACLK;
input INTERCONNECT_ARESETN;
output [0:0] S_AXI_ARESET_OUT_N;
output [4:0] M_AXI_ARESET_OUT_N;
output IRQ;
input [0:0] S_AXI_ACLK;
input [0:0] S_AXI_AWID;
input [31:0] S_AXI_AWADDR;
input [7:0] S_AXI_AWLEN;
input [2:0] S_AXI_AWSIZE;
input [1:0] S_AXI_AWBURST;
input [1:0] S_AXI_AWLOCK;
input [3:0] S_AXI_AWCACHE;
input [2:0] S_AXI_AWPROT;
input [3:0] S_AXI_AWQOS;
input [0:0] S_AXI_AWUSER;
input [0:0] S_AXI_AWVALID;
output [0:0] S_AXI_AWREADY;
input [0:0] S_AXI_WID;
input [31:0] S_AXI_WDATA;
input [3:0] S_AXI_WSTRB;
input [0:0] S_AXI_WLAST;
input [0:0] S_AXI_WUSER;
input [0:0] S_AXI_WVALID;
output [0:0] S_AXI_WREADY;
output [0:0] S_AXI_BID;
output [1:0] S_AXI_BRESP;
output [0:0] S_AXI_BUSER;
output [0:0] S_AXI_BVALID;
input [0:0] S_AXI_BREADY;
input [0:0] S_AXI_ARID;
input [31:0] S_AXI_ARADDR;
input [7:0] S_AXI_ARLEN;
input [2:0] S_AXI_ARSIZE;
input [1:0] S_AXI_ARBURST;
input [1:0] S_AXI_ARLOCK;
input [3:0] S_AXI_ARCACHE;
input [2:0] S_AXI_ARPROT;
input [3:0] S_AXI_ARQOS;
input [0:0] S_AXI_ARUSER;
input [0:0] S_AXI_ARVALID;
output [0:0] S_AXI_ARREADY;
output [0:0] S_AXI_RID;
output [31:0] S_AXI_RDATA;
output [1:0] S_AXI_RRESP;
output [0:0] S_AXI_RLAST;
output [0:0] S_AXI_RUSER;
output [0:0] S_AXI_RVALID;
input [0:0] S_AXI_RREADY;
input [4:0] M_AXI_ACLK;
output [4:0] M_AXI_AWID;
output [159:0] M_AXI_AWADDR;
output [39:0] M_AXI_AWLEN;
output [14:0] M_AXI_AWSIZE;
output [9:0] M_AXI_AWBURST;
output [9:0] M_AXI_AWLOCK;
output [19:0] M_AXI_AWCACHE;
output [14:0] M_AXI_AWPROT;
output [19:0] M_AXI_AWREGION;
output [19:0] M_AXI_AWQOS;
output [4:0] M_AXI_AWUSER;
output [4:0] M_AXI_AWVALID;
input [4:0] M_AXI_AWREADY;
output [4:0] M_AXI_WID;
output [159:0] M_AXI_WDATA;
output [19:0] M_AXI_WSTRB;
output [4:0] M_AXI_WLAST;
output [4:0] M_AXI_WUSER;
output [4:0] M_AXI_WVALID;
input [4:0] M_AXI_WREADY;
input [4:0] M_AXI_BID;
input [9:0] M_AXI_BRESP;
input [4:0] M_AXI_BUSER;
input [4:0] M_AXI_BVALID;
output [4:0] M_AXI_BREADY;
output [4:0] M_AXI_ARID;
output [159:0] M_AXI_ARADDR;
output [39:0] M_AXI_ARLEN;
output [14:0] M_AXI_ARSIZE;
output [9:0] M_AXI_ARBURST;
output [9:0] M_AXI_ARLOCK;
output [19:0] M_AXI_ARCACHE;
output [14:0] M_AXI_ARPROT;
output [19:0] M_AXI_ARREGION;
output [19:0] M_AXI_ARQOS;
output [4:0] M_AXI_ARUSER;
output [4:0] M_AXI_ARVALID;
input [4:0] M_AXI_ARREADY;
input [4:0] M_AXI_RID;
input [159:0] M_AXI_RDATA;
input [9:0] M_AXI_RRESP;
input [4:0] M_AXI_RLAST;
input [4:0] M_AXI_RUSER;
input [4:0] M_AXI_RVALID;
output [4:0] M_AXI_RREADY;
input [31:0] S_AXI_CTRL_AWADDR;
input S_AXI_CTRL_AWVALID;
output S_AXI_CTRL_AWREADY;
input [31:0] S_AXI_CTRL_WDATA;
input S_AXI_CTRL_WVALID;
output S_AXI_CTRL_WREADY;
output [1:0] S_AXI_CTRL_BRESP;
output S_AXI_CTRL_BVALID;
input S_AXI_CTRL_BREADY;
input [31:0] S_AXI_CTRL_ARADDR;
input S_AXI_CTRL_ARVALID;
output S_AXI_CTRL_ARREADY;
output [31:0] S_AXI_CTRL_RDATA;
output [1:0] S_AXI_CTRL_RRESP;
output S_AXI_CTRL_RVALID;
input S_AXI_CTRL_RREADY;
output INTERCONNECT_ARESET_OUT_N;
output [7:0] DEBUG_AW_TRANS_SEQ;
output [7:0] DEBUG_AW_ARB_GRANT;
output [7:0] DEBUG_AR_TRANS_SEQ;
output [7:0] DEBUG_AR_ARB_GRANT;
output [0:0] DEBUG_AW_TRANS_QUAL;
output [7:0] DEBUG_AW_ACCEPT_CNT;
output [15:0] DEBUG_AW_ACTIVE_THREAD;
output [7:0] DEBUG_AW_ACTIVE_TARGET;
output [7:0] DEBUG_AW_ACTIVE_REGION;
output [7:0] DEBUG_AW_ERROR;
output [7:0] DEBUG_AW_TARGET;
output [0:0] DEBUG_AR_TRANS_QUAL;
output [7:0] DEBUG_AR_ACCEPT_CNT;
output [15:0] DEBUG_AR_ACTIVE_THREAD;
output [7:0] DEBUG_AR_ACTIVE_TARGET;
output [7:0] DEBUG_AR_ACTIVE_REGION;
output [7:0] DEBUG_AR_ERROR;
output [7:0] DEBUG_AR_TARGET;
output [7:0] DEBUG_B_TRANS_SEQ;
output [7:0] DEBUG_R_BEAT_CNT;
output [7:0] DEBUG_R_TRANS_SEQ;
output [7:0] DEBUG_AW_ISSUING_CNT;
output [7:0] DEBUG_AR_ISSUING_CNT;
output [7:0] DEBUG_W_BEAT_CNT;
output [7:0] DEBUG_W_TRANS_SEQ;
output [7:0] DEBUG_BID_TARGET;
output DEBUG_BID_ERROR;
output [7:0] DEBUG_RID_TARGET;
output DEBUG_RID_ERROR;
output [31:0] DEBUG_SR_SC_ARADDR;
output [23:0] DEBUG_SR_SC_ARADDRCONTROL;
output [31:0] DEBUG_SR_SC_AWADDR;
output [23:0] DEBUG_SR_SC_AWADDRCONTROL;
output [4:0] DEBUG_SR_SC_BRESP;
output [31:0] DEBUG_SR_SC_RDATA;
output [5:0] DEBUG_SR_SC_RDATACONTROL;
output [31:0] DEBUG_SR_SC_WDATA;
output [6:0] DEBUG_SR_SC_WDATACONTROL;
output [31:0] DEBUG_SC_SF_ARADDR;
output [23:0] DEBUG_SC_SF_ARADDRCONTROL;
output [31:0] DEBUG_SC_SF_AWADDR;
output [23:0] DEBUG_SC_SF_AWADDRCONTROL;
output [4:0] DEBUG_SC_SF_BRESP;
output [31:0] DEBUG_SC_SF_RDATA;
output [5:0] DEBUG_SC_SF_RDATACONTROL;
output [31:0] DEBUG_SC_SF_WDATA;
output [6:0] DEBUG_SC_SF_WDATACONTROL;
output [31:0] DEBUG_SF_CB_ARADDR;
output [23:0] DEBUG_SF_CB_ARADDRCONTROL;
output [31:0] DEBUG_SF_CB_AWADDR;
output [23:0] DEBUG_SF_CB_AWADDRCONTROL;
output [4:0] DEBUG_SF_CB_BRESP;
output [31:0] DEBUG_SF_CB_RDATA;
output [5:0] DEBUG_SF_CB_RDATACONTROL;
output [31:0] DEBUG_SF_CB_WDATA;
output [6:0] DEBUG_SF_CB_WDATACONTROL;
output [31:0] DEBUG_CB_MF_ARADDR;
output [23:0] DEBUG_CB_MF_ARADDRCONTROL;
output [31:0] DEBUG_CB_MF_AWADDR;
output [23:0] DEBUG_CB_MF_AWADDRCONTROL;
output [4:0] DEBUG_CB_MF_BRESP;
output [31:0] DEBUG_CB_MF_RDATA;
output [5:0] DEBUG_CB_MF_RDATACONTROL;
output [31:0] DEBUG_CB_MF_WDATA;
output [6:0] DEBUG_CB_MF_WDATACONTROL;
output [31:0] DEBUG_MF_MC_ARADDR;
output [23:0] DEBUG_MF_MC_ARADDRCONTROL;
output [31:0] DEBUG_MF_MC_AWADDR;
output [23:0] DEBUG_MF_MC_AWADDRCONTROL;
output [4:0] DEBUG_MF_MC_BRESP;
output [31:0] DEBUG_MF_MC_RDATA;
output [5:0] DEBUG_MF_MC_RDATACONTROL;
output [31:0] DEBUG_MF_MC_WDATA;
output [6:0] DEBUG_MF_MC_WDATACONTROL;
output [31:0] DEBUG_MC_MP_ARADDR;
output [23:0] DEBUG_MC_MP_ARADDRCONTROL;
output [31:0] DEBUG_MC_MP_AWADDR;
output [23:0] DEBUG_MC_MP_AWADDRCONTROL;
output [4:0] DEBUG_MC_MP_BRESP;
output [31:0] DEBUG_MC_MP_RDATA;
output [5:0] DEBUG_MC_MP_RDATACONTROL;
output [31:0] DEBUG_MC_MP_WDATA;
output [6:0] DEBUG_MC_MP_WDATACONTROL;
output [31:0] DEBUG_MP_MR_ARADDR;
output [23:0] DEBUG_MP_MR_ARADDRCONTROL;
output [31:0] DEBUG_MP_MR_AWADDR;
output [23:0] DEBUG_MP_MR_AWADDRCONTROL;
output [4:0] DEBUG_MP_MR_BRESP;
output [31:0] DEBUG_MP_MR_RDATA;
output [5:0] DEBUG_MP_MR_RDATACONTROL;
output [31:0] DEBUG_MP_MR_WDATA;
output [6:0] DEBUG_MP_MR_WDATACONTROL;
axi_interconnect
#(
.C_BASEFAMILY ( "spartan6" ),
.C_NUM_SLAVE_SLOTS ( 1 ),
.C_NUM_MASTER_SLOTS ( 5 ),
.C_AXI_ID_WIDTH ( 1 ),
.C_AXI_ADDR_WIDTH ( 32 ),
.C_AXI_DATA_MAX_WIDTH ( 32 ),
.C_S_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_M_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_INTERCONNECT_DATA_WIDTH ( 32 ),
.C_S_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002 ),
.C_M_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000002000000020000000200000002 ),
.C_M_AXI_BASE_ADDR ( 16384'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040040000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041400000 ),
.C_M_AXI_HIGH_ADDR ( 16384'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004004ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004140ffff ),
.C_S_AXI_BASE_ID ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_THREAD_ID_WIDTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_IS_INTERCONNECT ( 16'b0000000000000000 ),
.C_S_AXI_ACLK_RATIO ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000102faf080 ),
.C_S_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_M_AXI_ACLK_RATIO ( 512'h000000010000000100000001000000010000000100000001000000010000000100000001000000010000000102faf08002faf08002faf08002faf08002faf080 ),
.C_M_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_INTERCONNECT_ACLK_RATIO ( 50000000 ),
.C_S_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ),
.C_AXI_AWUSER_WIDTH ( 1 ),
.C_AXI_ARUSER_WIDTH ( 1 ),
.C_AXI_WUSER_WIDTH ( 1 ),
.C_AXI_RUSER_WIDTH ( 1 ),
.C_AXI_BUSER_WIDTH ( 1 ),
.C_AXI_CONNECTIVITY ( 512'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ),
.C_S_AXI_SINGLE_THREAD ( 16'b0000000000000000 ),
.C_M_AXI_SUPPORTS_REORDERING ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111110 ),
.C_M_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_S_AXI_READ_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_M_AXI_WRITE_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_M_AXI_READ_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_S_AXI_ARB_PRIORITY ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_SECURE ( 16'b0000000000000000 ),
.C_S_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_INTERCONNECT_R_REGISTER ( 0 ),
.C_INTERCONNECT_CONNECTIVITY_MODE ( 0 ),
.C_USE_CTRL_PORT ( 0 ),
.C_USE_INTERRUPT ( 1 ),
.C_RANGE_CHECK ( 1 ),
.C_S_AXI_CTRL_ADDR_WIDTH ( 32 ),
.C_S_AXI_CTRL_DATA_WIDTH ( 32 ),
.C_DEBUG ( 0 ),
.C_S_AXI_DEBUG_SLOT ( 0 ),
.C_M_AXI_DEBUG_SLOT ( 0 ),
.C_MAX_DEBUG_THREADS ( 1 )
)
axi4lite_0 (
.INTERCONNECT_ACLK ( INTERCONNECT_ACLK ),
.INTERCONNECT_ARESETN ( INTERCONNECT_ARESETN ),
.S_AXI_ARESET_OUT_N ( S_AXI_ARESET_OUT_N ),
.M_AXI_ARESET_OUT_N ( M_AXI_ARESET_OUT_N ),
.IRQ ( IRQ ),
.S_AXI_ACLK ( S_AXI_ACLK ),
.S_AXI_AWID ( S_AXI_AWID ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWLEN ( S_AXI_AWLEN ),
.S_AXI_AWSIZE ( S_AXI_AWSIZE ),
.S_AXI_AWBURST ( S_AXI_AWBURST ),
.S_AXI_AWLOCK ( S_AXI_AWLOCK ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWQOS ( S_AXI_AWQOS ),
.S_AXI_AWUSER ( S_AXI_AWUSER ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WID ( S_AXI_WID ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WLAST ( S_AXI_WLAST ),
.S_AXI_WUSER ( S_AXI_WUSER ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BID ( S_AXI_BID ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BUSER ( S_AXI_BUSER ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARID ( S_AXI_ARID ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARLEN ( S_AXI_ARLEN ),
.S_AXI_ARSIZE ( S_AXI_ARSIZE ),
.S_AXI_ARBURST ( S_AXI_ARBURST ),
.S_AXI_ARLOCK ( S_AXI_ARLOCK ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARQOS ( S_AXI_ARQOS ),
.S_AXI_ARUSER ( S_AXI_ARUSER ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RID ( S_AXI_RID ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RLAST ( S_AXI_RLAST ),
.S_AXI_RUSER ( S_AXI_RUSER ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.M_AXI_ACLK ( M_AXI_ACLK ),
.M_AXI_AWID ( M_AXI_AWID ),
.M_AXI_AWADDR ( M_AXI_AWADDR ),
.M_AXI_AWLEN ( M_AXI_AWLEN ),
.M_AXI_AWSIZE ( M_AXI_AWSIZE ),
.M_AXI_AWBURST ( M_AXI_AWBURST ),
.M_AXI_AWLOCK ( M_AXI_AWLOCK ),
.M_AXI_AWCACHE ( M_AXI_AWCACHE ),
.M_AXI_AWPROT ( M_AXI_AWPROT ),
.M_AXI_AWREGION ( M_AXI_AWREGION ),
.M_AXI_AWQOS ( M_AXI_AWQOS ),
.M_AXI_AWUSER ( M_AXI_AWUSER ),
.M_AXI_AWVALID ( M_AXI_AWVALID ),
.M_AXI_AWREADY ( M_AXI_AWREADY ),
.M_AXI_WID ( M_AXI_WID ),
.M_AXI_WDATA ( M_AXI_WDATA ),
.M_AXI_WSTRB ( M_AXI_WSTRB ),
.M_AXI_WLAST ( M_AXI_WLAST ),
.M_AXI_WUSER ( M_AXI_WUSER ),
.M_AXI_WVALID ( M_AXI_WVALID ),
.M_AXI_WREADY ( M_AXI_WREADY ),
.M_AXI_BID ( M_AXI_BID ),
.M_AXI_BRESP ( M_AXI_BRESP ),
.M_AXI_BUSER ( M_AXI_BUSER ),
.M_AXI_BVALID ( M_AXI_BVALID ),
.M_AXI_BREADY ( M_AXI_BREADY ),
.M_AXI_ARID ( M_AXI_ARID ),
.M_AXI_ARADDR ( M_AXI_ARADDR ),
.M_AXI_ARLEN ( M_AXI_ARLEN ),
.M_AXI_ARSIZE ( M_AXI_ARSIZE ),
.M_AXI_ARBURST ( M_AXI_ARBURST ),
.M_AXI_ARLOCK ( M_AXI_ARLOCK ),
.M_AXI_ARCACHE ( M_AXI_ARCACHE ),
.M_AXI_ARPROT ( M_AXI_ARPROT ),
.M_AXI_ARREGION ( M_AXI_ARREGION ),
.M_AXI_ARQOS ( M_AXI_ARQOS ),
.M_AXI_ARUSER ( M_AXI_ARUSER ),
.M_AXI_ARVALID ( M_AXI_ARVALID ),
.M_AXI_ARREADY ( M_AXI_ARREADY ),
.M_AXI_RID ( M_AXI_RID ),
.M_AXI_RDATA ( M_AXI_RDATA ),
.M_AXI_RRESP ( M_AXI_RRESP ),
.M_AXI_RLAST ( M_AXI_RLAST ),
.M_AXI_RUSER ( M_AXI_RUSER ),
.M_AXI_RVALID ( M_AXI_RVALID ),
.M_AXI_RREADY ( M_AXI_RREADY ),
.S_AXI_CTRL_AWADDR ( S_AXI_CTRL_AWADDR ),
.S_AXI_CTRL_AWVALID ( S_AXI_CTRL_AWVALID ),
.S_AXI_CTRL_AWREADY ( S_AXI_CTRL_AWREADY ),
.S_AXI_CTRL_WDATA ( S_AXI_CTRL_WDATA ),
.S_AXI_CTRL_WVALID ( S_AXI_CTRL_WVALID ),
.S_AXI_CTRL_WREADY ( S_AXI_CTRL_WREADY ),
.S_AXI_CTRL_BRESP ( S_AXI_CTRL_BRESP ),
.S_AXI_CTRL_BVALID ( S_AXI_CTRL_BVALID ),
.S_AXI_CTRL_BREADY ( S_AXI_CTRL_BREADY ),
.S_AXI_CTRL_ARADDR ( S_AXI_CTRL_ARADDR ),
.S_AXI_CTRL_ARVALID ( S_AXI_CTRL_ARVALID ),
.S_AXI_CTRL_ARREADY ( S_AXI_CTRL_ARREADY ),
.S_AXI_CTRL_RDATA ( S_AXI_CTRL_RDATA ),
.S_AXI_CTRL_RRESP ( S_AXI_CTRL_RRESP ),
.S_AXI_CTRL_RVALID ( S_AXI_CTRL_RVALID ),
.S_AXI_CTRL_RREADY ( S_AXI_CTRL_RREADY ),
.INTERCONNECT_ARESET_OUT_N ( INTERCONNECT_ARESET_OUT_N ),
.DEBUG_AW_TRANS_SEQ ( DEBUG_AW_TRANS_SEQ ),
.DEBUG_AW_ARB_GRANT ( DEBUG_AW_ARB_GRANT ),
.DEBUG_AR_TRANS_SEQ ( DEBUG_AR_TRANS_SEQ ),
.DEBUG_AR_ARB_GRANT ( DEBUG_AR_ARB_GRANT ),
.DEBUG_AW_TRANS_QUAL ( DEBUG_AW_TRANS_QUAL ),
.DEBUG_AW_ACCEPT_CNT ( DEBUG_AW_ACCEPT_CNT ),
.DEBUG_AW_ACTIVE_THREAD ( DEBUG_AW_ACTIVE_THREAD ),
.DEBUG_AW_ACTIVE_TARGET ( DEBUG_AW_ACTIVE_TARGET ),
.DEBUG_AW_ACTIVE_REGION ( DEBUG_AW_ACTIVE_REGION ),
.DEBUG_AW_ERROR ( DEBUG_AW_ERROR ),
.DEBUG_AW_TARGET ( DEBUG_AW_TARGET ),
.DEBUG_AR_TRANS_QUAL ( DEBUG_AR_TRANS_QUAL ),
.DEBUG_AR_ACCEPT_CNT ( DEBUG_AR_ACCEPT_CNT ),
.DEBUG_AR_ACTIVE_THREAD ( DEBUG_AR_ACTIVE_THREAD ),
.DEBUG_AR_ACTIVE_TARGET ( DEBUG_AR_ACTIVE_TARGET ),
.DEBUG_AR_ACTIVE_REGION ( DEBUG_AR_ACTIVE_REGION ),
.DEBUG_AR_ERROR ( DEBUG_AR_ERROR ),
.DEBUG_AR_TARGET ( DEBUG_AR_TARGET ),
.DEBUG_B_TRANS_SEQ ( DEBUG_B_TRANS_SEQ ),
.DEBUG_R_BEAT_CNT ( DEBUG_R_BEAT_CNT ),
.DEBUG_R_TRANS_SEQ ( DEBUG_R_TRANS_SEQ ),
.DEBUG_AW_ISSUING_CNT ( DEBUG_AW_ISSUING_CNT ),
.DEBUG_AR_ISSUING_CNT ( DEBUG_AR_ISSUING_CNT ),
.DEBUG_W_BEAT_CNT ( DEBUG_W_BEAT_CNT ),
.DEBUG_W_TRANS_SEQ ( DEBUG_W_TRANS_SEQ ),
.DEBUG_BID_TARGET ( DEBUG_BID_TARGET ),
.DEBUG_BID_ERROR ( DEBUG_BID_ERROR ),
.DEBUG_RID_TARGET ( DEBUG_RID_TARGET ),
.DEBUG_RID_ERROR ( DEBUG_RID_ERROR ),
.DEBUG_SR_SC_ARADDR ( DEBUG_SR_SC_ARADDR ),
.DEBUG_SR_SC_ARADDRCONTROL ( DEBUG_SR_SC_ARADDRCONTROL ),
.DEBUG_SR_SC_AWADDR ( DEBUG_SR_SC_AWADDR ),
.DEBUG_SR_SC_AWADDRCONTROL ( DEBUG_SR_SC_AWADDRCONTROL ),
.DEBUG_SR_SC_BRESP ( DEBUG_SR_SC_BRESP ),
.DEBUG_SR_SC_RDATA ( DEBUG_SR_SC_RDATA ),
.DEBUG_SR_SC_RDATACONTROL ( DEBUG_SR_SC_RDATACONTROL ),
.DEBUG_SR_SC_WDATA ( DEBUG_SR_SC_WDATA ),
.DEBUG_SR_SC_WDATACONTROL ( DEBUG_SR_SC_WDATACONTROL ),
.DEBUG_SC_SF_ARADDR ( DEBUG_SC_SF_ARADDR ),
.DEBUG_SC_SF_ARADDRCONTROL ( DEBUG_SC_SF_ARADDRCONTROL ),
.DEBUG_SC_SF_AWADDR ( DEBUG_SC_SF_AWADDR ),
.DEBUG_SC_SF_AWADDRCONTROL ( DEBUG_SC_SF_AWADDRCONTROL ),
.DEBUG_SC_SF_BRESP ( DEBUG_SC_SF_BRESP ),
.DEBUG_SC_SF_RDATA ( DEBUG_SC_SF_RDATA ),
.DEBUG_SC_SF_RDATACONTROL ( DEBUG_SC_SF_RDATACONTROL ),
.DEBUG_SC_SF_WDATA ( DEBUG_SC_SF_WDATA ),
.DEBUG_SC_SF_WDATACONTROL ( DEBUG_SC_SF_WDATACONTROL ),
.DEBUG_SF_CB_ARADDR ( DEBUG_SF_CB_ARADDR ),
.DEBUG_SF_CB_ARADDRCONTROL ( DEBUG_SF_CB_ARADDRCONTROL ),
.DEBUG_SF_CB_AWADDR ( DEBUG_SF_CB_AWADDR ),
.DEBUG_SF_CB_AWADDRCONTROL ( DEBUG_SF_CB_AWADDRCONTROL ),
.DEBUG_SF_CB_BRESP ( DEBUG_SF_CB_BRESP ),
.DEBUG_SF_CB_RDATA ( DEBUG_SF_CB_RDATA ),
.DEBUG_SF_CB_RDATACONTROL ( DEBUG_SF_CB_RDATACONTROL ),
.DEBUG_SF_CB_WDATA ( DEBUG_SF_CB_WDATA ),
.DEBUG_SF_CB_WDATACONTROL ( DEBUG_SF_CB_WDATACONTROL ),
.DEBUG_CB_MF_ARADDR ( DEBUG_CB_MF_ARADDR ),
.DEBUG_CB_MF_ARADDRCONTROL ( DEBUG_CB_MF_ARADDRCONTROL ),
.DEBUG_CB_MF_AWADDR ( DEBUG_CB_MF_AWADDR ),
.DEBUG_CB_MF_AWADDRCONTROL ( DEBUG_CB_MF_AWADDRCONTROL ),
.DEBUG_CB_MF_BRESP ( DEBUG_CB_MF_BRESP ),
.DEBUG_CB_MF_RDATA ( DEBUG_CB_MF_RDATA ),
.DEBUG_CB_MF_RDATACONTROL ( DEBUG_CB_MF_RDATACONTROL ),
.DEBUG_CB_MF_WDATA ( DEBUG_CB_MF_WDATA ),
.DEBUG_CB_MF_WDATACONTROL ( DEBUG_CB_MF_WDATACONTROL ),
.DEBUG_MF_MC_ARADDR ( DEBUG_MF_MC_ARADDR ),
.DEBUG_MF_MC_ARADDRCONTROL ( DEBUG_MF_MC_ARADDRCONTROL ),
.DEBUG_MF_MC_AWADDR ( DEBUG_MF_MC_AWADDR ),
.DEBUG_MF_MC_AWADDRCONTROL ( DEBUG_MF_MC_AWADDRCONTROL ),
.DEBUG_MF_MC_BRESP ( DEBUG_MF_MC_BRESP ),
.DEBUG_MF_MC_RDATA ( DEBUG_MF_MC_RDATA ),
.DEBUG_MF_MC_RDATACONTROL ( DEBUG_MF_MC_RDATACONTROL ),
.DEBUG_MF_MC_WDATA ( DEBUG_MF_MC_WDATA ),
.DEBUG_MF_MC_WDATACONTROL ( DEBUG_MF_MC_WDATACONTROL ),
.DEBUG_MC_MP_ARADDR ( DEBUG_MC_MP_ARADDR ),
.DEBUG_MC_MP_ARADDRCONTROL ( DEBUG_MC_MP_ARADDRCONTROL ),
.DEBUG_MC_MP_AWADDR ( DEBUG_MC_MP_AWADDR ),
.DEBUG_MC_MP_AWADDRCONTROL ( DEBUG_MC_MP_AWADDRCONTROL ),
.DEBUG_MC_MP_BRESP ( DEBUG_MC_MP_BRESP ),
.DEBUG_MC_MP_RDATA ( DEBUG_MC_MP_RDATA ),
.DEBUG_MC_MP_RDATACONTROL ( DEBUG_MC_MP_RDATACONTROL ),
.DEBUG_MC_MP_WDATA ( DEBUG_MC_MP_WDATA ),
.DEBUG_MC_MP_WDATACONTROL ( DEBUG_MC_MP_WDATACONTROL ),
.DEBUG_MP_MR_ARADDR ( DEBUG_MP_MR_ARADDR ),
.DEBUG_MP_MR_ARADDRCONTROL ( DEBUG_MP_MR_ARADDRCONTROL ),
.DEBUG_MP_MR_AWADDR ( DEBUG_MP_MR_AWADDR ),
.DEBUG_MP_MR_AWADDRCONTROL ( DEBUG_MP_MR_AWADDRCONTROL ),
.DEBUG_MP_MR_BRESP ( DEBUG_MP_MR_BRESP ),
.DEBUG_MP_MR_RDATA ( DEBUG_MP_MR_RDATA ),
.DEBUG_MP_MR_RDATACONTROL ( DEBUG_MP_MR_RDATACONTROL ),
.DEBUG_MP_MR_WDATA ( DEBUG_MP_MR_WDATA ),
.DEBUG_MP_MR_WDATACONTROL ( DEBUG_MP_MR_WDATACONTROL )
);
endmodule
|
(** * ProofObjects: Working with Explicit Evidence in Coq *)
Require Export Logic.
(* ##################################################### *)
(** We have seen that Coq has mechanisms both for _programming_,
using inductive data types (like [nat] or [list]) and functions
over these types, and for _proving_ properties of these programs,
using inductive propositions (like [ev] or [eq]), implication, and
universal quantification. So far, we have treated these mechanisms
as if they were quite separate, and for many purposes this is
a good way to think. But we have also seen hints that Coq's programming and
proving facilities are closely related. For example, the
keyword [Inductive] is used to declare both data types and
propositions, and [->] is used both to describe the type of
functions on data and logical implication. This is not just a
syntactic accident! In fact, programs and proofs in Coq are almost
the same thing. In this chapter we will study how this works.
We have already seen the fundamental idea: provability in Coq is
represented by concrete _evidence_. When we construct the proof
of a basic proposition, we are actually building a tree of evidence,
which can be thought of as a data structure. If the proposition
is an implication like [A -> B], then its proof will be an
evidence _transformer_: a recipe for converting evidence for
A into evidence for B. So at a fundamental level, proofs are simply
programs that manipulate evidence.
*)
(**
Q. If evidence is data, what are propositions themselves?
A. They are types!
Look again at the formal definition of the [beautiful] property. *)
Print beautiful.
(* ==>
Inductive beautiful : nat -> Prop :=
b_0 : beautiful 0
| b_3 : beautiful 3
| b_5 : beautiful 5
| b_sum : forall n m : nat, beautiful n -> beautiful m -> beautiful (n + m)
*)
(** The trick is to introduce an alternative pronunciation of "[:]".
Instead of "has type," we can also say "is a proof of." For
example, the second line in the definition of [beautiful] declares
that [b_0 : beautiful 0]. Instead of "[b_0] has type
[beautiful 0]," we can say that "[b_0] is a proof of [beautiful 0]."
Similarly for [b_3] and [b_5]. *)
(** This pun between types and propositions (between [:] as "has type"
and [:] as "is a proof of" or "is evidence for") is called the
_Curry-Howard correspondence_. It proposes a deep connection
between the world of logic and the world of computation.
<<
propositions ~ types
proofs ~ data values
>>
Many useful insights follow from this connection. To begin with, it
gives us a natural interpretation of the type of [b_sum] constructor: *)
Check b_sum.
(* ===> b_sum : forall n m,
beautiful n ->
beautiful m ->
beautiful (n+m) *)
(** This can be read "[b_sum] is a constructor that takes four
arguments -- two numbers, [n] and [m], and two values, of types
[beautiful n] and [beautiful m] -- and yields evidence for the
proposition [beautiful (n+m)]." *)
(** Now let's look again at a previous proof involving [beautiful]. *)
Theorem eight_is_beautiful: beautiful 8.
Proof.
apply b_sum with (n := 3) (m := 5).
apply b_3.
apply b_5. Qed.
(** Just as with ordinary data values and functions, we can use the [Print]
command to see the _proof object_ that results from this proof script. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5
: beautiful 8 *)
(** In view of this, we might wonder whether we can write such
an expression ourselves. Indeed, we can: *)
Check (b_sum 3 5 b_3 b_5).
(* ===> beautiful (3 + 5) *)
(** The expression [b_sum 3 5 b_3 b_5] can be thought of as
instantiating the parameterized constructor [b_sum] with the
specific arguments [3] [5] and the corresponding proof objects for
its premises [beautiful 3] and [beautiful 5] (Coq is smart enough
to figure out that 3+5=8). Alternatively, we can think of [b_sum]
as a primitive "evidence constructor" that, when applied to two
particular numbers, wants to be further applied to evidence that
those two numbers are beautiful; its type,
[[
forall n m, beautiful n -> beautiful m -> beautiful (n+m),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] in the previous chapter expressed the fact
that the constructor [nil] can be thought of as a function from
types to empty lists with elements of that type. *)
(** This gives us an alternative way to write the proof that [8] is
beautiful: *)
Theorem eight_is_beautiful': beautiful 8.
Proof.
apply (b_sum 3 5 b_3 b_5).
Qed.
(** Notice that we're using [apply] here in a new way: instead of just
supplying the _name_ of a hypothesis or previously proved theorem
whose type matches the current goal, we are supplying an
_expression_ that directly builds evidence with the required
type. *)
(* ##################################################### *)
(** ** Proof Scripts and Proof Objects *)
(** These proof objects lie at the core of how Coq operates.
When Coq is following a proof script, what is happening internally
is that it is gradually constructing a proof object -- a term
whose type is the proposition being proved. The tactics between
the [Proof] command and the [Qed] instruct Coq how to build up a
term of the required type. To see this process in action, let's
use the [Show Proof] command to display the current state of the
proof tree at various points in the following tactic proof. *)
Theorem eight_is_beautiful'': beautiful 8.
Proof.
Show Proof.
apply b_sum with (n:=3) (m:=5).
Show Proof.
apply b_3.
Show Proof.
apply b_5.
Show Proof.
Qed.
(** At any given moment, Coq has constructed a term with some
"holes" (indicated by [?1], [?2], and so on), and it knows what
type of evidence is needed at each hole. *)
(**
Each of the holes corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
[Theorem] command gives a name to the evidence we've built and
stores it in the global context. *)
(** Tactic proofs are useful and convenient, but they are not
essential: in principle, we can always construct the required
evidence by hand, as shown above. Then we can use [Definition]
(rather than [Theorem]) to give a global name directly to a
piece of evidence. *)
Definition eight_is_beautiful''' : beautiful 8 :=
b_sum 3 5 b_3 b_5.
(** All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'.
(* ===> eight_is_beautiful' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful''.
(* ===> eight_is_beautiful'' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'''.
(* ===> eight_is_beautiful''' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
(** **** Exercise: 1 star (six_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [6] is [beautiful]. *)
Theorem six_is_beautiful :
beautiful 6.
Proof.
apply b_sum with (n:=3)(m:=3).
apply b_3.
apply b_3.
Qed.
(* FILL IN HERE *)
Definition six_is_beautiful' : beautiful 6 :=
b_sum 3 3 b_3 b_3.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 1 star (nine_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [9] is [beautiful]. *)
Theorem nine_is_beautiful :
beautiful 9.
Proof.
apply b_sum with (n:=3)(m:=6).
apply b_3.
apply six_is_beautiful.
Qed.
Print nine_is_beautiful.
(* FILL IN HERE *)
Definition nine_is_beautiful' : beautiful 9 :=
b_sum 3 6 b_3 (b_sum 3 3 b_3 b_3).
Print nine_is_beautiful'.
(* FILL IN HERE *)
(** [] *)
(* ##################################################### *)
(** ** Quantification, Implications and Functions *)
(** In Coq's computational universe (where we've mostly been living
until this chapter), there are two sorts of values with arrows in
their types: _constructors_ introduced by [Inductive]-ly defined
data types, and _functions_.
Similarly, in Coq's logical universe, there are two ways of giving
evidence for an implication: constructors introduced by
[Inductive]-ly defined propositions, and... functions!
For example, consider this statement: *)
Theorem b_plus3: forall n, beautiful n -> beautiful (3+n).
Proof.
intros n H.
apply b_sum.
apply b_3.
apply H.
Qed.
(** What is the proof object corresponding to [b_plus3]?
We're looking for an expression whose _type_ is [forall n,
beautiful n -> beautiful (3+n)] -- that is, a _function_ that
takes two arguments (one number and a piece of evidence) and
returns a piece of evidence! Here it is: *)
Definition b_plus3' : forall n, beautiful n -> beautiful (3+n) :=
fun (n : nat) => fun (H : beautiful n) =>
b_sum 3 n b_3 H.
Check b_plus3'.
(* ===> b_plus3' : forall n : nat, beautiful n -> beautiful (3+n) *)
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]." Another equivalent way to write this definition is: *)
Definition b_plus3'' (n : nat) (H : beautiful n) : beautiful (3+n) :=
b_sum 3 n b_3 H.
Check b_plus3''.
(* ===> b_plus3'' : forall n : nat, beautiful n -> beautiful (3+n) *)
(** When we view the proposition being proved by [b_plus3] as a function type,
one aspect of it may seem a little unusual. The second argument's
type, [beautiful n], mentions the _value_ of the first argument, [n].
While such _dependent types_ are not commonly found in programming
languages, even functional ones like ML or Haskell, they can
be useful there too.
Notice that both implication ([->]) and quantification ([forall])
correspond to functions on evidence. In fact, they are really the
same thing: [->] is just a shorthand for a degenerate use of
[forall] where there is no dependency, i.e., no need to give a name
to the type on the LHS of the arrow. *)
(** For example, consider this proposition: *)
Definition beautiful_plus3 : Prop :=
forall n, forall (E : beautiful n), beautiful (n+3).
(** A proof term inhabiting this proposition would be a function
with two arguments: a number [n] and some evidence [E] that [n] is
beautiful. But the name [E] for this evidence is not used in the
rest of the statement of [funny_prop1], so it's a bit silly to
bother making up a name for it. We could write it like this
instead, using the dummy identifier [_] in place of a real
name: *)
Definition beautiful_plus3' : Prop :=
forall n, forall (_ : beautiful n), beautiful (n+3).
(** Or, equivalently, we can write it in more familiar notation: *)
Definition beatiful_plus3'' : Prop :=
forall n, beautiful n -> beautiful (n+3).
(** In general, "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(** **** Exercise: 3 stars (b_times2) *)
(** First prove this theorem using tactics. *)
Theorem b_times2: forall n, beautiful n -> beautiful (2*n).
Proof.
intros.
apply b_sum.
apply H.
rewrite->plus_0_r.
apply H.
Qed.
(* FILL IN HERE *)
(** [] *)
Print b_times2.
(** Now write a corresponding proof object directly. *)
Definition b_times2': forall n, beautiful n -> beautiful (2*n) :=
fun (n : nat) (H : beautiful n) =>
b_sum n (n + 0) H (eq_ind_r (fun n0 : nat => beautiful n0) H (plus_0_r n)).
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (gorgeous_plus13_po) *)
(** Give a proof object corresponding to the theorem [gorgeous_plus13] from Prop.v *)
Definition gorgeous_plus13_po: forall n, gorgeous n -> gorgeous (13+n):=
fun (n:nat)(H:gorgeous n)=>
g_plus3 (10+n) (g_plus5 (5+n) (g_plus5 n H)).
(* FILL IN HERE *)
(** [] *)
(** It is particularly revealing to look at proof objects involving the
logical connectives that we defined with inductive propositions in Logic.v. *)
Theorem and_example :
(beautiful 0) /\ (beautiful 3).
Proof.
apply conj.
(* Case "left". *) apply b_0.
(* Case "right". *) apply b_3. Qed.
(** Let's take a look at the proof object for the above theorem. *)
Print and_example.
(* ===> conj (beautiful 0) (beautiful 3) b_0 b_3
: beautiful 0 /\ beautiful 3 *)
(** Note that the proof is of the form
conj (beautiful 0) (beautiful 3)
(...pf of beautiful 3...) (...pf of beautiful 3...)
as you'd expect, given the type of [conj]. *)
(** **** Exercise: 1 star, optional (case_proof_objects) *)
(** The [Case] tactics were commented out in the proof of
[and_example] to avoid cluttering the proof object. What would
you guess the proof object will look like if we uncomment them?
Try it and see. *)
Theorem and_example' :
(beautiful 0) /\ (beautiful 3).
Proof.
apply conj.
Case "left". apply b_0.
Case "right". apply b_3. Qed.
Print and_example'.
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros P Q H.
inversion H as [HP HQ].
split.
(* Case "left". *) apply HQ.
(* Case "right". *) apply HP. Qed.
(** Once again, we have commented out the [Case] tactics to make the
proof object for this theorem easier to understand. It is still
a little complicated, but after performing some simple reduction
steps, we can see that all that is really happening is taking apart
a record containing evidence for [P] and [Q] and rebuilding it in the
opposite order: *)
Print and_commut.
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
(fun H0 : Q /\ P => H0)
match H with
| conj HP HQ => (fun (HP0 : P) (HQ0 : Q) => conj Q P HQ0 HP0) HP HQ
end
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** After simplifying some direct application of [fun] expressions to arguments,
we get: *)
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
match H with
| conj HP HQ => conj Q P HQ HP
end
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** **** Exercise: 2 stars, optional (conj_fact) *)
(** Construct a proof object demonstrating the following proposition. *)
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R :=
fun(P Q R:Prop)(H1:P/\Q)(H2:Q/\R)=>
(fun H : P /\ R => H)
match H1 with
| conj H1P H1Q =>
(fun (H1P0 : P) (_ : Q) =>
(fun H : P /\ R => H)
match H2 with
| conj H2Q H2R =>
(fun (_ : Q) (H2R0 : R) => conj P R H1P0 H2R0) H2Q H2R
end) H1P H1Q
end.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, advanced (beautiful_iff_gorgeous) *)
(** We have seen that the families of propositions [beautiful] and
[gorgeous] actually characterize the same set of numbers.
Prove that [beautiful n <-> gorgeous n] for all [n]. Just for
fun, write your proof as an explicit proof object, rather than
using tactics. (_Hint_: if you make use of previously defined
theorems, you should only need a single line!) *)
Definition beautiful_iff_gorgeous :
forall n, beautiful n <-> gorgeous n :=
fun n:nat=>
conj(beautiful n -> gorgeous n)(gorgeous n -> beautiful n)
(beautiful__gorgeous n)(gorgeous__beautiful n).
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (or_commut'') *)
(** Try to write down an explicit proof object for [or_commut] (without
using [Print] to peek at the ones we already defined!). *)
Definition or_commut:=
fun (P Q : Prop) (H : P \/ Q) =>
match H with
| or_introl H0 => or_intror Q P H0
| or_intror H0 => or_introl Q P H0
end.
(* FILL IN HERE *)
(** [] *)
(** Recall that we model an existential for a property as a pair consisting of
a witness value and a proof that the witness obeys that property.
We can choose to construct the proof explicitly.
For example, consider this existentially quantified proposition: *)
Definition some_nat_is_even : Prop :=
ex nat ev.
(** To prove this proposition, we need to choose a particular number
as witness -- say, 4 -- and give some evidence that that number is
even. *)
Definition snie : some_nat_is_even :=
ex_intro _ ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** **** Exercise: 2 stars (ex_beautiful_Sn) *)
(** Complete the definition of the following proof object: *)
Definition p : ex nat (fun n => beautiful (S n)) :=
ex_intro nat (fun n:nat => beautiful (S n)) 2 b_3.
(* FILL IN HERE *)
(** [] *)
(* ##################################################### *)
(** ** Giving Explicit Arguments to Lemmas and Hypotheses *)
(** Even when we are using tactic-based proof, it can be very useful to
understand the underlying functional nature of implications and quantification.
For example, it is often convenient to [apply] or [rewrite]
using a lemma or hypothesis with one or more quantifiers or
assumptions already instantiated in order to direct what
happens. For example: *)
Check plus_comm.
(* ==>
plus_comm
: forall n m : nat, n + m = m + n *)
Lemma plus_comm_r : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
(* rewrite plus_comm. *)
(* rewrites in the first possible spot; not what we want *)
rewrite (plus_comm b a). (* directs rewriting to the right spot *)
reflexivity. Qed.
(** In this case, giving just one argument would be sufficient. *)
Lemma plus_comm_r' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite (plus_comm b).
reflexivity. Qed.
(** Arguments must be given in order, but wildcards (_)
may be used to skip arguments that Coq can infer. *)
Lemma plus_comm_r'' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite (plus_comm _ a).
reflexivity. Qed.
(** The author of a lemma can choose to declare easily inferable arguments
to be implicit, just as with functions and constructors.
The [with] clauses we've already seen is really just a way of
specifying selected arguments by name rather than position: *)
Lemma plus_comm_r''' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite plus_comm with (n := b).
reflexivity. Qed.
(** **** Exercise: 2 stars (trans_eq_example_redux) *)
(** Redo the proof of the following theorem (from MoreCoq.v) using
an [apply] of [trans_eq] but _not_ using a [with] clause. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros.
apply (trans_eq (list nat) [a;b] [c;d] [e;f]).
apply H.
apply H0.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ##################################################### *)
(** ** Programming with Tactics *)
(** If we can build proofs with explicit terms rather than
tactics, you may be wondering if we can build programs using
tactics rather than explicit terms. Sure! *)
Definition add1 : nat -> nat.
Show Proof.
intro n.
Show Proof.
apply S.
Show Proof.
apply n. Show Proof. Defined.
Print add1.
(* ==>
add1 = fun n : nat => S n
: nat -> nat
*)
Eval compute in add1 2.
(* ==> 3 : nat *)
(** Notice that we terminate the [Definition] with a [.] rather than with
[:=] followed by a term. This tells Coq to enter proof scripting mode
to build an object of type [nat -> nat]. Also, we terminate the proof
with [Defined] rather than [Qed]; this makes the definition _transparent_
so that it can be used in computation like a normally-defined function.
This feature is mainly useful for writing functions with dependent types,
which we won't explore much further in this book.
But it does illustrate the uniformity and orthogonality of the basic ideas in Coq. *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t;
wire d1 = 1'b1;
wire d2 = 1'b1;
wire d3 = 1'b1;
wire o1,o2,o3;
add1 add1 (d1,o1);
add2 add2 (d2,o2);
`define ls left_side
`define rs right_side
`define noarg na//note extra space
`define thru(x) x
`define thruthru `ls `rs // Doesn't expand
`define msg(x,y) `"x: `\`"y`\`"`"
`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string
initial begin
//$display(`msg( \`, \`)); // Illegal
$display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
$display(`msg(left side,right side));
$display(`msg( left side , right side ));
$display(`msg( `ls , `rs ));
$display(`msg( `noarg , `rs ));
$display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
$display(`msg(`noarg,`noarg`noarg));
$display(`msg( `thruthru , `thruthru )); // Results vary between simulators
$display(`left(`msg( left side , right side ), left_replaced));
//$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error
`ifndef VCS // Sim bug - wrong number of arguments, but we're right
$display(`msg(`thru(),)); // Empty
`endif
$display(`msg(`thru(left side),`thru(right side)));
$display(`msg( `thru( left side ) , `thru( right side ) ));
`ifndef NC
$display(`"standalone`");
`endif
`ifdef VERILATOR
// Illegal on some simulators, as the "..." crosses two lines
`define twoline first \
second
$display(`msg(twoline, `twoline));
`endif
$display("Line %0d File \"%s\"",`__LINE__,`__FILE__);
//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define ADD_UP(a,c) \
wire tmp_``a = a; \
wire tmp_``c = tmp_``a + 1; \
assign c = tmp_``c ;
module add1 ( input wire d1, output wire o1);
`ADD_UP(d1,o1) // expansion is OK
endmodule
module add2 ( input wire d2, output wire o2);
`ADD_UP( d2 , o2 ) // expansion is bad
endmodule
// `ADD_UP( \d3 , \o3 ) // This really is illegal
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a22oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.07.2017 21:09:25
// Design Name:
// Module Name: t_scp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module t_scp;
// Inputs
reg clk, reset;
// Initialise the Unit Under Test
singlecycleprocessor uut (
.clk( clk ),
.reset( reset)
);
// Initialise the clock
initial begin
clk = 0;
#20;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
// Stimulus here
initial begin
$display(t_scp.uut.ID.jumpaddr);
$display(t_scp.uut.ID.WAinstrD);
$display(t_scp.uut.IF.WAinstrF);
$display(t_scp.uut.IF.PCPrime);
$display(t_scp.uut.IF.PC);
$display(t_scp.uut.IF.PCJump);
reset = 0;
//#30 reset = 1;
//#20 reset = 0;
end
endmodule
|
// Part of NeoGS project
//
// FPGA early and on-the-fly configuration, Z80 clock switch,
// 3.3v RAM buffer
//
// (c) 2008-2010 NedoPC
module GS_cpld(
output reg config_n, // ACEX1K config pins
input wire status_n, //
input wire conf_done, //
output wire cs, //
input wire init_done, //
input wire clk24in, // 24mhz in
input wire clk20in, // 20mhz in
input wire clksel0, // clock select 0 (1=divide by 2, 0=no divide)
input wire clksel1, // clock select 1 (1=clk20in, 0=clk24in)
output wire clkout, // clock out
input wire clkin, // input of clkout signal, buffered, same as for Z80
input wire coldres_n, // resets
output reg warmres_n,
input wire iorq_n, // Z80 control signals
input wire mreq_n,
input wire rd_n,
input wire wr_n,
inout wire [ 7:0] d, // Z80 data bus
input wire a6, // some Z80 addresses
input wire a7,
input wire a10,
input wire a11,
input wire a12,
input wire a13,
input wire a14,
input wire a15,
output wire mema14,
output wire mema15,
output wire mema19,
inout wire romcs_n,
inout wire memoe_n,
inout wire memwe_n,
input wire in_ramcs0_n,
input wire in_ramcs1_n,
input wire in_ramcs2_n,
input wire in_ramcs3_n,
output wire out_ramcs0_n,
output wire out_ramcs1_n,
output wire ra6, // some buffered memory addresses
output wire ra7,
output wire ra10,
output wire ra11,
output wire ra12,
output wire ra13,
inout wire [ 7:0] rd // memory data bus
);
reg int_mema14,int_mema15;
reg int_romcs_n,int_ramcs_n;
wire int_memoe_n,int_memwe_n;
wire int_cs;
wire ext_romcs_n,
ext_memoe_n,
ext_memwe_n;
reg [1:0] memcfg; // memcfg[1]: 1 ram, 0 roms
// memcfg[0]: 0 page0, 1 page1 -> in 8000-ffff region
reg disbl; // =1 - cpld disabled, =0 - enabled
reg was_cold_reset_n; // 1 - no cold reset, 0 - was cold reset
reg [1:0] dbout;
wire [1:0] dbin;
wire memcfg_write_n;
wire rescfg_write_n;
wire coldrstf_read_n;
wire fpgastat_read_n;
assign dbin[1] = d[7];
assign dbin[0] = d[0];
reg [3:0] rstcount; // counter for warm reset period
reg [2:0] disbl_sync;
// PORTS:
// {a7,a6}
// 00 - fpga ports
// 01,WR - write memcfg: d7=RAM(1)/ROM(0), d0=32k page(0/1)
// 01,RD - read cold_reset_n flag: d7=(0:was cold reset,1:no cold reset)
// 10,WR - set cold_reset_n flag & write FPGA nCONFIG: d7=1: set cold_reset_n flag, d0: nCONFIG
// 10,RD - read FPGA status: d7=nSTATUS, d0=CONF_DONE
// 11,WR - write to FPGA
// 11,RD - read from FPGA
// clock selector
clocker clk( .clk1(clk24in),
.clk2(clk20in),
.clksel(clksel1),
.divsel(clksel0),
.clkout(clkout)
);
// disable control
always @(negedge config_n,posedge init_done)
begin
if( !config_n ) // asynchronous reset
disbl <= 0;
else // posedge of init_done, synchronous set
disbl <= 1;
end
// memory control pins when running without configured FPGA
assign mema14 = disbl ? 1'bZ : int_mema14;
assign mema15 = disbl ? 1'bZ : int_mema15;
assign romcs_n = disbl ? 1'bZ : int_romcs_n;
assign memoe_n = disbl ? 1'bZ : int_memoe_n;
assign memwe_n = disbl ? 1'bZ : int_memwe_n;
assign cs = disbl ? 1'bZ : int_cs;
assign ext_romcs_n = romcs_n;
assign ext_memoe_n = memoe_n;
assign ext_memwe_n = memwe_n;
// controlling memory paging
always @*
begin
casex( {a15,a14,memcfg[1]} )
3'b00x:
{int_mema15,int_mema14,int_romcs_n,int_ramcs_n} <= 4'b0001;
3'b01x:
{int_mema15,int_mema14,int_romcs_n,int_ramcs_n} <= 4'b0010;
3'b1x0:
{int_mema15,int_mema14,int_romcs_n,int_ramcs_n} <= {memcfg[0],a14,2'b01};
3'b1x1:
{int_mema15,int_mema14,int_romcs_n,int_ramcs_n} <= {memcfg[0],a14,2'b10};
endcase
end
// controlling memory /OE, /WE
assign int_memoe_n = mreq_n | rd_n;
assign int_memwe_n = mreq_n | wr_n;
// writing paging register [1:0] memcfg
assign memcfg_write_n = iorq_n | wr_n | a7 | ~a6; // {a7,a6}==01
always @(negedge coldres_n, posedge memcfg_write_n)
begin
if( !coldres_n ) // reset on coldres_n
memcfg <= 2'b00;
else // write on memcfg_write_n
memcfg <= dbin;
end
// writing nCONFIG and cold reset "register"
assign rescfg_write_n = iorq_n | wr_n | ~a7 | a6; // {a7,a6}==10
always @(posedge rescfg_write_n, negedge coldres_n)
begin
if( !coldres_n ) // async reset
begin
was_cold_reset_n <= 0; // there was!
config_n <= 0; // start FPGA config
end
else // sync set/load
begin
config_n <= dbin[0];
was_cold_reset_n <= dbin[1] | was_cold_reset_n;
end
end
// controlling positive CS pin to FPGA
assign int_cs = a7 & a6; // {a7,a6}==11
// reading control
assign coldrstf_read_n = iorq_n | rd_n | a7 | ~a6; // {a7,a6}=01
assign fpgastat_read_n = iorq_n | rd_n | ~a7 | a6; // {a7,a6}=10
always @*
begin
case( {coldrstf_read_n,fpgastat_read_n} )
2'b01:
dbout = { was_cold_reset_n, 1'bX };
2'b10:
dbout = { status_n, conf_done };
default:
dbout = 2'bXX;
endcase
end
// warm resetter control
always @(posedge clkin)
begin
disbl_sync[2:0]={disbl_sync[1:0],disbl};
end
always @(negedge coldres_n,posedge clkin)
begin
if( coldres_n==0 ) // async reset
begin
rstcount <= (-1);
warmres_n <= 0;
end
else // posedge clkin
begin
if( disbl_sync[2]==0 && disbl_sync[1]==1 ) // positive pulse
begin
warmres_n <= 0;
rstcount <= (-1);
end
else // no disbl_sync positive pulse
begin
rstcount <= rstcount - 1;
if( |rstcount == 0 )
warmres_n <= 1'bZ;
end
end
end
// Z80 data bus control
assign d = ( (!coldrstf_read_n)||(!fpgastat_read_n) ) ?
{ dbout[1], 6'bXXXXXX, dbout[0] } :
( (ext_romcs_n&&(!ext_memoe_n)) ? rd : 8'bZZZZZZZZ ) ;
// memory data bus control
assign rd = (ext_romcs_n&&(!ext_memwe_n)) ? d : 8'bZZZZZZZZ;
// memory addresses buffering
assign ra6 = a6;
assign ra7 = a7;
assign ra10 = a10;
assign ra11 = a11;
assign ra12 = a12;
assign ra13 = a13;
// memory CS'ing
assign out_ramcs0_n = disbl ? ( in_ramcs0_n & in_ramcs1_n ) : int_ramcs_n;
assign out_ramcs1_n = disbl ? ( in_ramcs2_n & in_ramcs3_n ) : 1'b1;
assign mema19 = disbl ? ( in_ramcs0_n & in_ramcs2_n ) : 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFXBP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxbp (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_BLACKBOX_V
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Generated by harness_gen.py
* From: VexRiscv.v
*/
module top(input wire clk, input wire stb, input wire di, output wire do);
localparam integer DIN_N = 134;
localparam integer DOUT_N = 148;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
VexRiscv dut(
.externalResetVector(din[31:0]),
.timerInterrupt(din[32]),
.externalInterruptArray(din[64:33]),
.iBusWishbone_CYC(dout[0]),
.iBusWishbone_STB(dout[1]),
.iBusWishbone_ACK(din[65]),
.iBusWishbone_WE(dout[2]),
.iBusWishbone_ADR(dout[32:3]),
.iBusWishbone_DAT_MISO(din[97:66]),
.iBusWishbone_DAT_MOSI(dout[64:33]),
.iBusWishbone_SEL(dout[68:65]),
.iBusWishbone_ERR(din[98]),
.iBusWishbone_BTE(dout[70:69]),
.iBusWishbone_CTI(dout[73:71]),
.dBusWishbone_CYC(dout[74]),
.dBusWishbone_STB(dout[75]),
.dBusWishbone_ACK(din[99]),
.dBusWishbone_WE(dout[76]),
.dBusWishbone_ADR(dout[106:77]),
.dBusWishbone_DAT_MISO(din[131:100]),
.dBusWishbone_DAT_MOSI(dout[138:107]),
.dBusWishbone_SEL(dout[142:139]),
.dBusWishbone_ERR(din[132]),
.dBusWishbone_BTE(dout[144:143]),
.dBusWishbone_CTI(dout[147:145]),
.clk(clk),
.reset(din[133])
);
endmodule
|
/**************************************************************************
UART Receiver Module
-Sampling speed
x4
-parameter BAUDRATE_COUNTER
Uart Baudrate Parameter (Clock / Baudrate)/4-1
BAUDRATE_COUNTER is must be greater than 4. (BAUDRATE_COUNTER >= 20'h4)
Example : Clock : 50MHz
9600bps : 13'd1301
115.2Kbps : 13'd108
-SDF Settings
Asynchronus Clock : b_bd_clock
-Make : 2013/2/21
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032sa_uart_receiver #(
parameter BAUDRATE_FIXED = 1'b1, //0:Use iEXTBAUD_COUNT | 1:Use Parameter BAUDRATE_COUNTER
parameter BAUDRATE_COUNTER = 20'd108 //(Clock / Baudrate) / 4 - 1
)(
//Clock
input wire iCLOCK,
input wire inRESET,
//External Baudrate Timing
input wire [19:0] iEXTBAUD_COUNT,
//R Data
output wire oRX_VALID,
output wire [7:0] oRX_DATA,
//UART
input wire iUART_RXD
);
/**************************************************************
Parameter & Wire & Register
**************************************************************/
localparam IF_IDLE = 2'h0;
localparam IF_RECEIVED = 2'h1;
localparam IF_IDLEWAIT = 2'h2;
localparam RXD_IDLE = 2'h0;
localparam RXD_RECEIVING = 2'h1;
localparam RXD_RECEIVED = 2'h2;
//UART Metastable Cancel
wire uart_rxd;
//RXD Module
reg bn_rxd_init;
reg [1:0] b_rxd_state;
reg [7:0] b_rxd_buffer;
reg [5:0] b_rxd_counter;
reg b_rxd_data_req;
reg b_rxd_idle_req;
//Metastable Cancel
wire dflipflop_idle_req;
wire dflipflop_data_req;
//Async 2 Sync
wire sync_idle_req;
wire sync_data_req;
//Interface
reg [1:0] b_if_state;
reg [7:0] b_if_data;
reg b_if_end;
//Baudrate
reg [19:0] b_bd_wait_counter;
reg b_bd_clock;
/**************************************************************
RxD
**************************************************************/
//Metastable Cancel
mist1032sa_uart_receiver_double_flipflop #(1) RXD_DOUBLE_FLIPFLOP(
.iCLOCK(b_bd_clock),
.inRESET(inRESET),
//Input
.iREQ_DATA(iUART_RXD),
//Output
.oOUT_DATA(uart_rxd)
);
//Uart State
always@(posedge b_bd_clock or negedge inRESET)begin
if(!inRESET)begin
bn_rxd_init <= 1'b0;
b_rxd_state <= RXD_IDLE;
b_rxd_buffer <= 8'h0;
b_rxd_counter <= 6'h0;
b_rxd_data_req <= 1'b0;
b_rxd_idle_req <= 1'b0;
end
else if(!bn_rxd_init)begin
bn_rxd_init = 1'b1;
b_rxd_buffer <= 8'hFF;
end
else begin
case(b_rxd_state)
RXD_IDLE:
begin
//Stat bit Check
if(b_rxd_buffer[5:4] == 2'h0)begin
b_rxd_state <= RXD_RECEIVING;
end
b_rxd_buffer <= {uart_rxd, b_rxd_buffer[7:1]};
b_rxd_counter <= 6'h0;
b_rxd_data_req <= 1'b0;
b_rxd_idle_req <= 1'b0;
end
RXD_RECEIVING:
begin
b_rxd_idle_req <= 1'b0;
if(b_rxd_counter == 6'd32)begin
b_rxd_state <= RXD_RECEIVED;
b_rxd_data_req <= 1'b1;
end
else begin
if(b_rxd_counter[1:0] == 2'h1)begin //Uart center pickup
b_rxd_buffer <= {uart_rxd, b_rxd_buffer[7:1]};
end
b_rxd_counter <= b_rxd_counter + 6'h1;
end
end
RXD_RECEIVED:
begin
b_rxd_state <= RXD_IDLE;
b_rxd_buffer <= 8'hFF;
b_rxd_data_req <= 1'b0;
b_rxd_idle_req <= 1'b1;
end
endcase
end
end
//Metastable Cancel
mist1032sa_uart_receiver_double_flipflop #(2) DOUBLE_FLIPFLOP(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iREQ_DATA({b_rxd_idle_req, b_rxd_data_req}),
//Output
.oOUT_DATA({dflipflop_idle_req, dflipflop_data_req})
);
//Async 2 Sync
mist1032sa_uart_receiver_async2sync #(2) ASYNC2SYNC(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Ena-Signal
.iSIGNAL({dflipflop_idle_req, dflipflop_data_req}),
.oSIGNAL({sync_idle_req, sync_data_req})
);
//Interface State
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if_state <= IF_IDLE;
b_if_data <= 8'h0;
b_if_end <= 1'b0;
end
else begin
case(b_if_state)
IF_IDLE:
begin
if(sync_data_req)begin
b_if_state <= IF_RECEIVED;
b_if_data <= b_rxd_buffer;//dflipflop_data;
b_if_end <= 1'b1;
end
end
IF_RECEIVED:
begin
b_if_state <= IF_IDLEWAIT;
b_if_end <= 1'b0;
end
IF_IDLEWAIT:
begin
if(sync_idle_req)begin
b_if_state <= IF_IDLE;
end
end
default:
begin
b_if_state <= IF_IDLE;
b_if_data <= 8'h0;
b_if_end <= 1'b0;
end
endcase
end
end
/**************************************************************
Baudrate Counter
**************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_bd_wait_counter <= 20'h0;
b_bd_clock <= 1'b0;
end
else begin
if((BAUDRATE_FIXED && b_bd_wait_counter == BAUDRATE_COUNTER) || (!BAUDRATE_FIXED && b_bd_wait_counter == iEXTBAUD_COUNT))begin
b_bd_wait_counter <= 20'h0;
b_bd_clock <= 1'b1;
end
else begin
b_bd_wait_counter <= b_bd_wait_counter + 20'h1;
b_bd_clock <= 1'b0;
end
end
end
assign oRX_VALID = b_if_end;
assign oRX_DATA = b_if_data;
endmodule
`default_nettype wire
|
// system1_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module system1_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [20:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [20:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
system1_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
/**
* This is written by Andrew Mattheisen
* and Zhiyang Ong
*/
module conv_encoder (output [1:0] c, input b, input clk, input reset);
// Output signals for the design module
// Input signals for the design module
// Declare "reg" signals...
// Output bus that will be assigned values
reg [1:0] c;
/*
* Output of flip-flops in the convolutional encoder
* D_0 is the output of the first flip-flop
* D_1 is the output of the second flip-flop
*/
reg D_0, D_1;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// First flip-flop of the convolutional encoder
always @ (posedge clk)
begin
// If the reset signal is HIGH
if (reset)
begin
// Ground the output signal of the first flip-flop
D_0 <= 1'b0;
end
else
begin
// Assign the output of the 1st flip-flop to the signal b
D_0 <= b;
end
end
// Second flip-flop of the convolutional encoder
always @ (posedge clk)
begin
// If the reset signal is HIGH
if (reset)
begin
// Ground the output signal of the 2nd flip-flop
D_1 <= 1'b0;
end
else
begin
// Assign the output of the 2nd flip-flop to the signal b
D_1 <= D_0;
end
end
always @ (D_0 or D_1 or b)
begin
// 3-input XOR gate of the convolutional encoder
c[0] <= b^D_0^D_1;
// 2-input XOR gate of the convolutional encoder
c[1] <= b^D_1;
end // always @ (D_0 or D_1 or b)
endmodule
|
/*
Single BiQuad IIR Filter. Uses a single DSP block and
Scaling factor = 17-clog2(max(abs(COEFF)))
Multiply COEFFs by 2^SCALING
*/
module BiquadCascade #(
parameter WIDTH_D = 18, // Data path width
parameter WIDTH_C = 18, // Coeffecient bit width
parameter COEFF_B0 = 0, // Coeffecient B0
parameter COEFF_B1 = 0, // Coeffecient B1
parameter COEFF_B2 = 0, // Coeffecient B2
parameter COEFF_A1 = 0, // Coeffecient A1
parameter COEFF_A2 = 0, // Coeffecient A2
parameter SCALING = 0 // Output downscaling
)
(
input clk, // System clock
input rst, // Reset, active high & synchronous
input inStrobe, // Strobe on new dataIn
input signed [WIDTH_D-1:0] dataIn, // Input to filter
output reg outStrobe, // Strobes on new dataOut
output signed [WIDTH_D-1:0] dataOut // Output from filter
);
localparam ST_IDLE = 0;
localparam ST_X_B0 = 1;
localparam ST_X_B1 = 2;
localparam ST_X_B2 = 3;
localparam ST_Y_A1 = 4;
localparam ST_Y_A2 = 5;
// Calculation Engine Registers
reg signed [WIDTH_D-1:0] multInA;
reg signed [WIDTH_C-1:0] multInB;
reg signed [WIDTH_D+WIDTH_C-1:0] multOut;
reg signed [WIDTH_D+WIDTH_C+2:0] adderOut; // Allocate for multiply + 3 bits adder growth
reg signed [WIDTH_D-1:0] y;
reg signed [WIDTH_D-1:0] yD1;
reg signed [WIDTH_D-1:0] x;
reg signed [WIDTH_D-1:0] xD1;
reg signed [WIDTH_D-1:0] xD2;
// State Machine Registers
reg [2:0] state;
reg [2:0] stateD1;
reg [2:0] stateD2;
reg storeY;
// Zero out everything for initialization
initial begin
y = 'd0;
yD1 = 'd0;
x = 'd0;
xD1 = 'd0;
xD2 = 'd0;
multInA = 'd0;
multInB = 'd0;
multOut = 'd0;
adderOut = 'd0;
state = ST_IDLE;
stateD1 = ST_IDLE;
stateD2 = ST_IDLE;
storeY = 1'b0;
outStrobe = 1'b0;
end
assign dataOut = y;
// Calculation Engine - Should infer to DSP48 in Xilinx
always @(posedge clk) begin
if (rst) begin
y <= 'd0;
yD1 <= 'd0;
x <= 'd0;
xD1 <= 'd0;
xD2 <= 'd0;
multInA <= 'd0;
multInB <= 'd0;
multOut <= 'd0;
adderOut <= 'd0;
outStrobe <= 1'b0;
end
else begin
// Register X & delayed X on enable strobe
if (inStrobe) begin
x <= dataIn;
xD1 <= x;
xD2 <= xD1;
end
// Register Y & delayed Y on output strobe
if (storeY) begin
y <= adderOut[SCALING+:WIDTH_D];
yD1 <= y;
end
outStrobe <= storeY;
// Determine inputs into multiplier (DSP48)
case (state)
ST_IDLE : begin
multInA <= x;
multInB <= COEFF_B0;
end
ST_X_B0 : begin
multInA <= x;
multInB <= COEFF_B0;
end
ST_X_B1 : begin
multInA <= xD1;
multInB <= COEFF_B1;
end
ST_X_B2 : begin
multInA <= xD2;
multInB <= COEFF_B2;
end
ST_Y_A1 : begin
multInA <= y;
multInB <= COEFF_A1;
end
ST_Y_A2 : begin
multInA <= yD1;
multInB <= COEFF_A2;
end
endcase
// Determine Adder Function (DSP48)
case (stateD2)
ST_IDLE : begin
adderOut <= multOut;
end
ST_X_B0 : begin
adderOut <= multOut;
end
ST_X_B1 : begin
adderOut <= multOut + adderOut;
end
ST_X_B2 : begin
adderOut <= multOut + adderOut;
end
ST_Y_A1 : begin
adderOut <= multOut + adderOut;
end
ST_Y_A2 : begin
adderOut <= multOut + adderOut;
end
endcase
multOut <= multInA * multInB;
end
end
// State Machine to drive inputs to calculation engine
always @(posedge clk) begin
if (rst) begin
state <= ST_IDLE;
stateD1 <= ST_IDLE;
stateD2 <= ST_IDLE;
end
else begin
stateD1 <= state;
stateD2 <= stateD1;
storeY <= (stateD2 == ST_Y_A2);
case (state)
ST_IDLE : state <= (inStrobe) ? ST_X_B0 : ST_IDLE;
ST_X_B0 : state <= ST_X_B1;
ST_X_B1 : state <= ST_X_B2;
ST_X_B2 : state <= ST_Y_A1;
ST_Y_A1 : state <= ST_Y_A2;
ST_Y_A2 : state <= (inStrobe) ? ST_X_B0 : ST_IDLE;
default : state <= ST_IDLE;
endcase
end
end
endmodule
|
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream MT19937 Mersenne Twister
*/
module axis_mt19937
(
input wire clk,
input wire rst,
/*
* AXI output
*/
output wire [31:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [31:0] seed_val,
input wire seed_start
);
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_SEED = 2'd1;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [31:0] mt [623:0];
reg [31:0] mt_save_reg = 0, mt_save_next;
reg [9:0] mti_reg = 625, mti_next;
reg [31:0] y1, y2, y3, y4, y5;
reg [9:0] mt_wr_ptr;
reg [31:0] mt_wr_data;
reg mt_wr_en;
reg [9:0] mt_rd_a_ptr_reg = 0, mt_rd_a_ptr_next;
reg [31:0] mt_rd_a_data = 0;
reg [9:0] mt_rd_b_ptr_reg = 0, mt_rd_b_ptr_next;
reg [31:0] mt_rd_b_data = 0;
reg [31:0] product_reg = 0, product_next;
reg [31:0] factor1_reg = 0, factor1_next;
reg [31:0] factor2_reg = 0, factor2_next;
reg [4:0] mul_cnt_reg = 0, mul_cnt_next;
reg [31:0] output_axis_tdata_reg = 0, output_axis_tdata_next;
reg output_axis_tvalid_reg = 0, output_axis_tvalid_next;
reg busy_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign busy = busy_reg;
always @* begin
state_next = 2'bz;
mt_save_next = mt_save_reg;
mti_next = mti_reg;
mt_wr_data = 0;
mt_wr_ptr = 0;
mt_wr_en = 0;
y1 = 32'bz;
y2 = 32'bz;
y3 = 32'bz;
y4 = 32'bz;
y5 = 32'bz;
mt_rd_a_ptr_next = mt_rd_a_ptr_reg;
mt_rd_b_ptr_next = mt_rd_b_ptr_reg;
product_next = product_reg;
factor1_next = factor1_reg;
factor2_next = factor2_reg;
mul_cnt_next = mul_cnt_reg;
output_axis_tdata_next = output_axis_tdata_reg;
output_axis_tvalid_next = output_axis_tvalid_reg & ~output_axis_tready;
case (state_reg)
STATE_IDLE: begin
// idle state
if (seed_start) begin
mt_save_next = seed_val;
product_next = 0;
factor1_next = mt_save_next ^ (mt_save_next >> 30);
factor2_next = 32'd1812433253;
mul_cnt_next = 31;
mt_wr_data = mt_save_next;
mt_wr_ptr = 0;
mt_wr_en = 1;
mti_next = 1;
state_next = STATE_SEED;
end else if (output_axis_tready) begin
if (mti_reg == 625) begin
mt_save_next = 32'd5489;
product_next = 0;
factor1_next = mt_save_next ^ (mt_save_next >> 30);
factor2_next = 32'd1812433253;
mul_cnt_next = 31;
mt_wr_data = mt_save_next;
mt_wr_ptr = 0;
mt_wr_en = 1;
mti_next = 1;
state_next = STATE_SEED;
end else begin
if (mti_reg < 623)
mti_next = mti_reg + 1;
else
mti_next = 0;
if (mt_rd_a_ptr_reg < 623)
mt_rd_a_ptr_next = mt_rd_a_ptr_reg + 1;
else
mt_rd_a_ptr_next = 0;
if (mt_rd_b_ptr_reg < 623)
mt_rd_b_ptr_next = mt_rd_b_ptr_reg + 1;
else
mt_rd_b_ptr_next = 0;
mt_save_next = mt_rd_a_data;
y1 = {mt_save_reg[31], mt_rd_a_data[30:0]};
y2 = mt_rd_b_data ^ (y1 >> 1) ^ (y1[0] ? 32'h9908b0df : 32'h0);
y3 = y2 ^ (y2 >> 11);
y4 = y3 ^ ((y3 << 7) & 32'h9d2c5680);
y5 = y4 ^ ((y4 << 15) & 32'hefc60000);
output_axis_tdata_next = y5 ^ (y5 >> 18);
output_axis_tvalid_next = 1;
mt_wr_data = y2;
mt_wr_ptr = mti_reg;
mt_wr_en = 1;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_SEED: begin
if (mul_cnt_reg == 0) begin
if (mti_reg < 624) begin
//mt_save_next = 32'd1812433253 * (mt_save_reg ^ (mt_save_reg >> 30)) + mti_reg;
mt_save_next = product_reg + mti_reg;
product_next = 0;
factor1_next = mt_save_next ^ (mt_save_next >> 30);
factor2_next = 32'd1812433253;
mul_cnt_next = 31;
mt_wr_data = mt_save_next;
mt_wr_ptr = mti_reg;
mt_wr_en = 1;
mti_next = mti_reg + 1;
mt_rd_a_ptr_next = 0;
state_next = STATE_SEED;
end else begin
mti_next = 0;
mt_save_next = mt_rd_a_data;
mt_rd_a_ptr_next = 1;
mt_rd_b_ptr_next = 397;
state_next = STATE_IDLE;
end
end else begin
mul_cnt_next = mul_cnt_reg - 1;
factor1_next = factor1_reg << 1;
factor2_next = factor2_reg >> 1;
if (factor2_reg[0]) product_next = product_reg + factor1_reg;
state_next = STATE_SEED;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
mti_reg <= 625;
mt_rd_a_ptr_reg <= 0;
mt_rd_b_ptr_reg <= 0;
product_reg <= 0;
factor1_reg <= 0;
factor2_reg <= 0;
mul_cnt_reg <= 0;
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
mt_save_reg = mt_save_next;
mti_reg <= mti_next;
mt_rd_a_ptr_reg <= mt_rd_a_ptr_next;
mt_rd_b_ptr_reg <= mt_rd_b_ptr_next;
product_reg <= product_next;
factor1_reg <= factor1_next;
factor2_reg <= factor2_next;
mul_cnt_reg <= mul_cnt_next;
output_axis_tdata_reg <= output_axis_tdata_next;
output_axis_tvalid_reg <= output_axis_tvalid_next;
busy_reg <= state_next != STATE_IDLE;
if (mt_wr_en) begin
mt[mt_wr_ptr] <= mt_wr_data;
end
mt_rd_a_data <= mt[mt_rd_a_ptr_next];
mt_rd_b_data <= mt[mt_rd_b_ptr_next];
end
end
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pll (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.256000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "0.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.25600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3125"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DECAP_PP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__decap (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__AND2B_PP_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
`define SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_hd__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_hd__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file asfifo9_4.v when simulating
// the core, asfifo9_4. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module asfifo9_4(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full);
input [8 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [8 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(9),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(9),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(13),
.C_PROG_FULL_THRESH_NEGATE_VAL(12),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_RESPONSE_LATENCY(1))
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Replace all 32 by total_bits and check for signal width mismatch
module fft16(ED,RST,CLK,START,ifft,DIImag,DIReal,DOImag,DOReal,RDY);
parameter total_bits = 32;
input ED;
input RST;
input CLK;
input START;
input ifft;
input [total_bits-1:0] DIImag;
input [total_bits-1:0] DIReal;
output [total_bits+3:0] DOImag;
output [total_bits+3:0] DOReal;
output reg RDY;
reg [3:0] ct; //main phase counter
reg [5:0] ctd; //delay counter
always @( posedge CLK) begin //Control counter
//
if (RST) begin
ct<=0;
ctd<=63;
RDY<=0; end
else if (START) begin
ct<=0;
ctd<=0;
RDY<=0; end
else if (ED) begin
RDY<=0;
ct<=ct+1;
if (ctd !=6'b111111)
ctd<=ctd+1;
if (ctd==44-16 )
RDY<=1;
end
end
reg signed [total_bits-1: 0] dr,d1r,d2r,d3r,d4r,d5r,d6r,d7r,d8r,di,d1i,d2i,d3i,d4i,d5i,d6i,d7i,d8i;
always @(posedge CLK) // input register file
begin
if (ED) begin
dr<=DIReal;
d1r<=dr; d2r<=d1r; d3r<=d2r;d4r<=d3r;
d5r<=d4r;d6r<=d5r; d7r<=d6r; d8r<=d7r;
di<=DIImag;
d1i<=di; d2i<=d1i; d3i<=d2i; d4i<=d3i;
d5i<=d4i; d6i<=d5i;d7i<=d6i; d8i<=d7i;
end
end
reg signed [total_bits:0] s1r,s1d1r,s1d2r,s1d3r,s1d4r,s1d5r,s1d6r,s1d7r,s1d8r; //even result sums
reg signed [total_bits:0] s1i,s1d1i,s1d2i,s1d3i,s1d4i,s1d5i,s1d6i,s1d7i,s1d8i; //even result sums
reg signed [total_bits:0] s2r,s2d1r,s2d2r,s2d3r,s2d4r,s2d5r,s2d6r,s2d7r,s2d8r,m4_12r; //odd result sums
reg signed [total_bits:0] s2i,s2d1i,s2d2i,s2d3i,s2d4i,s2d5i,s2d6i,s2d7i,s2d8i,m4_12i; //odd result sums
always @(posedge CLK) begin // S1,S2 =t1-t14,m4,m12' and delayed
if (ED && ((ct==9) || (ct==10) || (ct==11) ||(ct==12) ||
(ct==13) || (ct==14) ||(ct==15) || (ct==0))) begin
s1r<=d8r + dr ;
s1i<=d8i + di ;
s2r<=d8r - dr ;
s2i<= d8i - di;
end
if (ED) begin //delayed results
s1d1r<=s1r; s1d2r<=s1d1r; s1d1i<=s1i; s1d2i<=s1d1i;
s1d3r<=s1d2r; s1d3i<=s1d2i; s1d4r<=s1d3r; s1d4i<=s1d3i;
s1d5r<=s1d4r; s1d5i<=s1d4i; s1d6r<=s1d5r; s1d6i<=s1d5i;
s1d7r<=s1d6r; s1d7i<=s1d6i; s1d8r<=s1d7r; s1d8i<=s1d7i;
s2d1r<=s2r; s2d2r<=s2d1r; s2d1i<=s2i; s2d2i<=s2d1i;
s2d3r<=s2d2r; s2d3i<=s2d2i; s2d4r<=s2d3r; s2d4i<=s2d3i;
s2d5r<=s2d4r; s2d5i<=s2d4i; s2d6r<=s2d5r; s2d6i<=s2d5i;
s2d7r<=s2d6r; s2d7i<=s2d6i; s2d8r<=s2d7r; s2d8i<=s2d7i;
if (ct==2) begin
m4_12r<=s2d8r; m4_12i<=s2d8i; end
else if (ct==6) begin
m4_12r<=s2d8i; m4_12i<= 0 - s2d8r;
end
end
end
///////////////////////////////////////////
//arm of even result calculations
////////////////////////////////////////////
reg signed [total_bits+1:0] s3r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r;
reg signed [total_bits+1:0] s3i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i;
always @(posedge CLK) begin //ALU S3:
if (ED) begin
case (ct)
14 ,15 : begin s3r<= s1d4r+s1r; //t15 //t18
s3i<= s1d4i+ s1i ;end
0 ,1 : begin s3r<= s1d6r - s1d2r; //m3, t19
s3i<= s1d6i - s1d2i ;end
2 ,3 : begin s3r<= s1d6r +s1d2r; //t16 ,t20
s3i<= s1d6i+ s1d2i ; end
4 ,5 : begin s3r<= s1d8r - s1d4r; // m11',t21
s3i<= s1d8i - s1d4i ; end
endcase
s3d1r<=s3r; s3d1i<=s3i; s3d2r<=s3d1r; s3d2i<=s3d1i;
s3d3r<=s3d2r; s3d3i<=s3d2i; s3d4r<=s3d3r; s3d4i<=s3d3i;
s3d5r<=s3d4r; s3d5i<=s3d4i; s3d6r<=s3d5r; s3d6i<=s3d5i;
end
end
reg signed [total_bits+2:0] s4r,s4d1r,s4d2r,s4d3r,s4d4r,s4d5r,s4d6r,s4d7r,m3r;
reg signed [total_bits+2:0] s4i,s4d1i,s4d2i,s4d3i,s4d4i,s4d5i,s4d6i,s4d7i,m3i;
always @ (posedge CLK) begin // S4
if (ED) begin
if ((ct==3) | (ct==4)) begin
s4r<= s3d4r + s3r; //t17 ,t22
s4i<= s3d4i + s3i; end
else if ((ct==5) | (ct==6) | (ct==8) ) begin
s4r<=s3d6r - s3d2r; //m2,m10', m5'
s4i<= s3d6i - s3d2i; end
else if (ct==7) begin
s4r<=s3d1r + s3d5r; //m13
s4i<= s3d1i + s3d5i;
end
s4d1r<=s4r; s4d1i<=s4i; s4d2r<=s4d1r; s4d2i<=s4d1i;
s4d3r<=s4d2r; s4d3i<=s4d2i; s4d4r<=s4d3r; s4d4i<=s4d3i;
s4d5r<=s4d4r; s4d5i<=s4d4i; s4d6r<=s4d5r; s4d6i<=s4d5i;
s4d7r<=s4d6r; s4d7i<=s4d6i;
if (ct==7) begin
m3r<=s3d6r; //m3
m3i<=s3d6i; end
end
end
wire em707,mpyj7;
assign em707 = ((ct==8) || (ct==10 )||(ct==1) || (ct==5)); //control signals for the multiplier
assign mpyj7 = ((ct==8) || (ct==5));
reg signed [total_bits+2:0] s7r,s7d1r;
reg signed [total_bits+2:0] s7i,s7d1i;
wire signed [total_bits+2:0] m707r,m707i,m70r,m70i;
assign m70r = ((ct==1) || (ct==5))? s7r :s4r; //multiplexor at the multiplier input
assign m70i = ((ct==1) || (ct==5))? s7i :s4i;
MPUC707 #(total_bits+3) UM707( .CLK(CLK),.ED(ED),.DS(em707), .MPYJ(mpyj7), //multiplier by 0.707
.DR(m70r),.DI(m70i) ,.DOR(m707r) ,.DOI(m707i));
reg signed [total_bits+2:0] s3jr,s3ji, m10r,m10i;
always @ (posedge CLK) begin //multiply by J
if (ED) begin
case (ct)
11: begin s3jr<= s3d6i; //m11
s3ji<=0 - s3d6r; end
14: begin s3jr<= s4d7i; //m10
s3ji<=0 - s4d7r; end
endcase
if (ct==1) begin
m10r<=s3jr; //m10
m10i<=s3ji;
end
end
end
reg signed [total_bits+3:0] s5r,s5d1r,s5d2r,s5d3r,s5d4r,s5d5r,s5d6r,s5d7r,s5d8r,s5d9r, s5d10r,m2r,m2dr;
reg signed [total_bits+3:0] s5i,s5d1i,s5d2i,s5d3i,s5d4i,s5d5i,s5d6i,s5d7i,s5d8i,s5d9i,s5d10i,m2i,m2di;
always @ (posedge CLK) // S5:
if (ED) begin
case (ct)
10: begin s5r<=s4d5r + s4d6r; //m0
s5i<=s4d5i + s4d6i; end
11: begin s5r<=s4d7r - s4d6r; //m1
s5i<=s4d7i - s4d6i; end
12: begin s5r<=m707r + s3jr; //S3
s5i<= m707i+s3ji;end
13: begin s5r<=m707r - s3jr; //S4
s5i<= m707i - s3ji;end
14: begin s5r<= m3r+m707r; //S1
s5i<= m3i+m707i ;end
15: begin s5r<=m3r-m707r ; //S2
s5i<= m3i -m707i ;end
6: begin //S2
s5d10r<=s5d9r ; //S2
s5d10i<=s5d9i ;end
endcase
if ((ct==4)||(ct==5)||(ct==6)||(ct==7)) begin
s5d9r<=s5d8r ; s5d9i<=s5d8i ; end
s5d1r<=s5r; s5d1i<=s5i; s5d2r<=s5d1r; s5d2i<=s5d1i;
s5d3r<=s5d2r; s5d3i<=s5d2i; s5d4r<=s5d3r; s5d4i<=s5d3i;
s5d5r<=s5d4r; s5d5i<=s5d4i; s5d6r<=s5d5r; s5d6i<=s5d5i;
s5d7r<=s5d6r; s5d7i<=s5d6i; s5d8r<=s5d7r; s5d8i<=s5d7i;
if (ct==13) begin
m2r<=s4d7r; m2i<=s4d7i; end
if (ct==1) begin
m2dr<=m2r; m2di<=m2i; end
end
reg signed [total_bits+3:0] s6r,s6i ;
// For IFFT
always @ (posedge CLK) begin // S6-- result adder
if (ED&ifft)
case (ct)
13: begin s6r<=s5d2r; // -- Y0
s6i<=(s5d2i);end //-- Y0
15: begin
s6r<=s5d2r - s5r ; //Y2
s6i<=s5d2i - s5i ; end
1: begin
s6r<=m2r - s3jr ; //Y4
s6i<=m2i - s3ji ; end
3: begin
s6r<=s5d3r - s5d5r ; //Y6
s6i<= s5d3i -s5d5i ; end
5:begin s6r<=(s5d9r) ; //-- Y8
s6i<=(s5d9i) ; end
7: begin
s6r<= s5d7r + s5d9r ; // Y10
s6i<= s5d7i + s5d9i ; end
9: begin // Y12
s6r<=m2dr +m10r ;
s6i<=m2di + m10i ;
end
11: begin // Y14
s6r<= s5d9r + s5d10r ;
s6i<= s5d9i + s5d10i ;
end
endcase
if (ED&~ifft)
case (ct)
13: begin s6r<=s5d2r; // -- Y0
s6i<=s5d2i;end //-- Y0
15: begin
s6r<=s5d2r + s5r ; //Y2
s6i<=s5d2i + s5i ; end
1: begin
s6r<=m2r + s3jr ; //Y4
s6i<=m2i + s3ji ; end
3: begin
s6r<=s5d3r + s5d5r ; //Y6
s6i<= s5d3i +s5d5i ; end
5:begin s6r<=s5d9r; //-- Y8
s6i<=s5d9i; end
7: begin
s6r<= s5d7r - s5d9r ; // Y10
s6i<= s5d7i - s5d9i ; end
9: begin // Y12
s6r<=m2dr -m10r ;
s6i<=m2di - m10i ;
end
11: begin // Y14
s6r<= s5d9r - s5d10r ;
s6i<= s5d9i - s5d10i ;
end
endcase
end
///////////////////////////////////////////////////////////
//arm of odd result calculations
//////////////////////////////////////////////////////////
always @(posedge CLK) begin //ALU S7:
if (ED)
case (ct)
15:begin s7r<= s2d2r-s2r; //t26
s7i<= s2d2i- s2i ;end
0: begin s7r<= s2d4r-s2r; //m6'
s7i<= s2d4i- s2i ;
s7d1r<=s7r;
s7d1i<=s7i;end
1: begin s7r<= s2d6r - s2r; //t24
s7i<= s2d6i - s2i; end
2: begin s7r<= s7r -s7d1r; //m7'
s7i<= s7i- s7d1i ; end
3: begin s7r<= s2d8r + s2d2r; // t23
s7i<= s2d8i + s2d2i ; end
4: begin s7r<= s2d8r + s2d4r; // m14'
s7i<= s2d8i + s2d4i ;
s7d1r<=s7r;
s7d1i<=s7i;end
5: begin s7r<= s2d8r + s2d6r; // t25
s7i<= s2d8i + s2d6i ; end
6: begin s7r<= s7r + s7d1r; //m15'
s7i<= s7i + s7d1i ; end
endcase
end
wire em541,mpyj541;
wire signed [total_bits+2:0] m541r,m541i;
assign em541 = ((ct==0) || (ct==4)); //control signals for the multiplier
assign mpyj541 = ((ct==4));
MPUC541 #(total_bits+3) UM541( .CLK(CLK),.ED(ED),.DS(em541), .MPYJ(mpyj541), //multiplier by 0.383
.DR(s7r),.DI(s7i) ,.DOR(m541r) ,.DOI(m541i));
wire em1307,mpyj1307;
wire signed [total_bits+2:0] m1307r,m1307i;
assign em1307 = ((ct==2) || (ct==6)); //control signals for the multiplier
assign mpyj1307 = ((ct==6));
MPUC1307 #(total_bits+3) UM1307( .CLK(CLK),.ED(ED),.DS(em1307), .MPYJ(mpyj1307), //multiplier by 1.306
.DR(s7r),.DI(s7i) ,.DOR(m1307r) ,.DOI(m1307i));
wire em383,mpyj383,c383;
wire signed [total_bits+2:0] m383r,m383i;
assign em383 = ((ct==3) || (ct==7)); //control signals for the multiplier
assign mpyj383 = ((ct==7));
assign c383 = (ct==3);
MPUC924_383 #(total_bits+3) UM383(.CLK(CLK),.ED(ED),.DS(em383),.MPYJ(mpyj383),.C383(c383), //multiplier by 0.383
.DR(s7r),.DI(s7i) ,.DOR(m383r) ,.DOI(m383i));
reg signed [total_bits+2:0] m8_17r,m8_17i,m9_16r,m9_16i;
always @(posedge CLK) begin //Reg-s
if (ED) begin
if (ct==4 || ct==8) begin
m9_16r<=m541r; //M9_ M16
m9_16i<=m541i;
end
if ( ct==6 || ct==10) begin
m8_17r<=m1307r; //M8_ M17
m8_17i<=m1307i;
end
end
end
reg signed [total_bits+2:0] s8r,s8i,s8d1r,s8d2r,s8d3r,s8d4r,s8d1i,s8d2i,s8d3i,s8d4i ;
always @ (posedge CLK) begin // S8-- adder
if (ED)
case (ct)
5,9: begin s8r<=m4_12r +m707r ; // -- S5 S13
s8i<=m4_12i +m707i ;end //--
6,10: begin
s8r<=m4_12r - m707r ; // -- S6 , S14
s8i<=m4_12i - m707i ; end
7: begin
s8r<=m8_17r - m383r ; // -- S7 ,S15
s8i<=m8_17i -m383i ; end
8: begin
s8r<=m9_16r - m383r ; // -- S8 , S16
s8i<=m9_16i -m383i ; end
11: begin
s8r<=m383r - m9_16r ; // -- S7 ,S15
s8i<=m383i - m9_16i; end
12: begin
s8r<=m383r - m8_17r; // -- S8 , S16
s8i<=m383i - m8_17i; end
endcase
s8d1r<=s8r; s8d1i<=s8i; s8d2r<=s8d1r; s8d2i<=s8d1i;
s8d3r<=s8d2r; s8d3i<=s8d2i; s8d4r<=s8d3r; s8d4i<=s8d3i;
end
reg signed [total_bits+3:0] s9r,s9d1r,s9d2r,s9d3r,s9d4r,s9d5r,s9d6r,s9d7r,s9d8r,s9d9r, s9d10r,s9d11r,s9d12r,s9d13r;
reg signed [total_bits+3:0] s9i,s9d1i,s9d2i,s9d3i,s9d4i,s9d5i,s9d6i,s9d7i,s9d8i,s9d9i,s9d10i,s9d11i,s9d12i,s9d13i;
always @ (posedge CLK) // ALU s9:
if (ED) begin
case (ct)
8,9,12: begin s9r<= s8r + s8d2r; // S9,S11 , S17
s9i<=s8i + s8d2i ; end
13: begin s9r<= s8d2r - s8r; // S20
s9i<=s8d2i - s8i ; end
10,11,14: begin s9r<=s8d4r - s8d2r; //S10, S12,S18
s9i<=s8d4i - s8d2i; end
15: begin s9r<=s8d4r + s8d2r; //S19
s9i<=s8d4i + s8d2i; end
endcase
s9d1r<=s9r; s9d1i<=s9i; s9d2r<=s9d1r; s9d2i<=s9d1i;
s9d3r<=s9d2r; s9d3i<=s9d2i; s9d4r<=s9d3r; s9d4i<=s9d3i;
s9d5r<=s9d4r; s9d5i<=s9d4i; s9d6r<=s9d5r; s9d6i<=s9d5i;
s9d7r<=s9d6r; s9d7i<=s9d6i; s9d8r<=s9d7r; s9d8i<=s9d7i;
s9d9r<=s9d8r ; s9d9i<=s9d8i ;
if ((ct!=8)) begin
s9d10r<=s9d9r ; s9d10i<=s9d9i ;
s9d11r<=s9d10r ; s9d11i<=s9d10i ; end
if ((ct==4) ||(ct==5) ||(ct==7) ||(ct==9) ) begin
s9d12r<=s9d11r ; s9d12i<=s9d11i ; end
if ((ct==5))begin
s9d13r<=s9d12r ; s9d13i<=s9d12i ; end
end
reg signed [total_bits+3:0] s10r,s10i;
reg signed [total_bits+3:0] s10dr,s10di;
//For IFFT
always @ (posedge CLK) begin // S10-- result adder
if (ED&ifft)
case (ct)
13: begin s10r<=s9d4r -s9r ; // -- Y1
s10i<=s9d4i -s9i ;end //
15: begin
s10r<=s9d3r + s9d1r ; //-- Y3
s10i<=s9d3i + s9d1i ; end
1: begin
s10r<=s9d7r - s9d1r ; //-- Y5
s10i<=s9d7i - s9d1i ; end
3: begin
s10r<=s9d8r + s9d4r ; // -- Y7
s10i<= s9d8i + s9d4i ;end
5:begin s10r<=s9d10r - s9d6r ; //-- Y9
s10i<=s9d10i - s9d6i ; end
7: begin
s10r<=s9d12r + s9d7r ; //-- Y11
s10i<=s9d12i + s9d7i ; end
9: begin
s10r<= s9d12r - s9d10r ; // Y13
s10i<=s9d12i - s9d10i ; end
11: begin
s10r<= s9d13r + s9d12r ; // Y15
s10i<= s9d13i + s9d12i ; end
endcase
if (ED&~ifft)
case (ct)
13: begin s10r<=s9d4r +s9r ; // -- Y0
s10i<=s9d4i +s9i ;end //
15: begin
s10r<=s9d3r - s9d1r ; //-- Y3
s10i<=s9d3i - s9d1i ; end
1: begin
s10r<=s9d7r +s9d1r ; //-- Y5
s10i<=s9d7i +s9d1i ; end
3: begin
s10r<=s9d8r - s9d4r ; // -- Y7
s10i<= s9d8i - s9d4i ;end
5:begin s10r<=s9d10r + s9d6r ; //-- Y9
s10i<=s9d10i + s9d6i ; end
7: begin
s10r<=s9d12r - s9d7r ; //-- Y11
s10i<=s9d12i - s9d7i ; end
9: begin
s10r<= s9d12r + s9d10r ; // Y13
s10i<=s9d12i + s9d10i ; end
11: begin
s10r<= s9d13r - s9d12r ; // Y15
s10i<= s9d13i - s9d12i ; end
endcase
s10dr<=s10r; s10di<=s10i;
end
//wire signed [nb+3:0] s6sr,s6si; //saturation of results
// assign s6sr = (~s6r[nb+4]&&s6r[nb+3])? ((1'b1 <<(nb+3))-1) : s6r[nb+3:0];
// assign s6si = (~s6i[nb+4]&&s6i[nb+3])? ((1'b1<<(nb+3))-1) : s6i[nb+3:0];
//
wire selo;
assign selo = ct-(ct/2)*2;
assign #1 DOReal=selo? s10dr:s6r;
assign #1 DOImag= selo? s10di:s6i;
endmodule
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// A qa_wrapper with a buffer_AA.
module qa_wrapper
#(
parameter WDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WDTH-1:0] in_data,
input wire in_nd,
output reg [WDTH-1:0] out_data,
output reg out_nd
);
wire rst_n;
assign rst_n = ~reset;
reg read_delete;
wire read_full;
wire [WDTH-1:0] read_data;
wire write_error;
wire read_error;
buffer_AA #(WDTH, `BUFFER_LENGTH, `LOG_BUFFER_LENGTH)
the_buffer
(.clk(clk),
.rst_n(rst_n),
.write_strobe(in_nd),
.write_data(in_data),
.read_delete(read_delete),
.read_full(read_full),
.read_data(read_data),
.write_error(write_error),
.read_error(read_error)
);
always @ (posedge clk)
begin
if (!rst_n)
begin
read_delete <= 1'b0;
out_data <= {WDTH{1'b0}};
out_nd <= 1'b0;
end
else
if (write_error)
begin
out_nd <= 1'b1;
out_data <= `WRITEERRORCODE;
read_delete <= 1'b0;
end
else if (read_error)
begin
out_nd <= 1'b1;
out_data <= `READERRORCODE;
read_delete <= 1'b0;
end
else
begin
if (!read_delete && read_full)
begin
read_delete <= 1'b1;
out_nd <= 1'b1;
out_data <= read_data;
end
else
begin
read_delete <= 1'b0;
out_nd <= 1'b0;
end
end
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_clock_module.v
//
// *Module Description:
// Basic clock module implementation.
// Since the openMSP430 mainly targets FPGA and hobby
// designers. The clock structure has been greatly
// symplified in order to ease integration.
// See online wiki for more info.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 34 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_clock_module (
// OUTPUTs
aclk_en, // ACLK enable
mclk, // Main system clock
per_dout, // Peripheral data output
por, // Power-on reset
puc, // Main system reset
smclk_en, // SMCLK enable
// INPUTs
dbg_reset, // Reset CPU from debug interface
dco_clk, // Fast oscillator (fast clock)
lfxt_clk, // Low frequency oscillator (typ 32kHz)
oscoff, // Turns off LFXT1 clock input
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
reset_n, // Reset Pin (low active)
scg1, // System clock generator 1. Turns off the SMCLK
wdt_reset // Watchdog-timer reset
);
// OUTPUTs
//=========
output aclk_en; // ACLK enable
output mclk; // Main system clock
output [15:0] per_dout; // Peripheral data output
output por; // Power-on reset
output puc; // Main system reset
output smclk_en; // SMCLK enable
// INPUTs
//=========
input dbg_reset; // Reset CPU from debug interface
input dco_clk; // Fast oscillator (fast clock)
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input oscoff; // Turns off LFXT1 clock input
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input reset_n; // Reset Pin (low active)
input scg1; // System clock generator 1. Turns off the SMCLK
input wdt_reset; // Watchdog-timer reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register addresses
parameter BCSCTL1 = 9'h057;
parameter BCSCTL2 = 9'h058;
// Register one-hot decoder
parameter BCSCTL1_D = (256'h1 << (BCSCTL1 /2));
parameter BCSCTL2_D = (256'h1 << (BCSCTL2 /2));
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Register address decode
reg [255:0] reg_dec;
always @(per_addr)
case (per_addr)
(BCSCTL1 /2): reg_dec = BCSCTL1_D;
(BCSCTL2 /2): reg_dec = BCSCTL2_D;
default : reg_dec = {256{1'b0}};
endcase
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
wire [255:0] reg_rd = reg_dec & {256{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// BCSCTL1 Register
//--------------
reg [7:0] bcsctl1;
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1/2] : reg_lo_wr[BCSCTL1/2];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc)
if (puc) bcsctl1 <= 8'h00;
else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & 8'h30; // Mask unused bits
// BCSCTL2 Register
//--------------
reg [7:0] bcsctl2;
wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2/2] : reg_lo_wr[BCSCTL2/2];
wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc)
if (puc) bcsctl2 <= 8'h00;
else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & 8'h0e; // Mask unused bits
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] bcsctl1_rd = (bcsctl1 & {8{reg_rd[BCSCTL1/2]}}) << (8 & {4{BCSCTL1[0]}});
wire [15:0] bcsctl2_rd = (bcsctl2 & {8{reg_rd[BCSCTL2/2]}}) << (8 & {4{BCSCTL2[0]}});
wire [15:0] per_dout = bcsctl1_rd |
bcsctl2_rd;
//=============================================================================
// 5) CLOCK GENERATION
//=============================================================================
// Synchronize LFXT_CLK & edge detection
//---------------------------------------
reg [2:0] lfxt_clk_s;
always @ (posedge mclk or posedge puc)
if (puc) lfxt_clk_s <= 3'b000;
else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk};
wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]);
// Generate main system clock
//----------------------------
wire mclk = dco_clk;
wire mclk_n = !dco_clk;
// Generate ACLK
//----------------------------
reg [2:0] aclk_div;
wire aclk_en = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 :
(bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] :
(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
&aclk_div[2:0]);
always @ (posedge mclk or posedge puc)
if (puc) aclk_div <= 3'h0;
else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
// Generate SMCLK
//----------------------------
reg [2:0] smclk_div;
wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1);
wire smclk_en = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 :
(bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] :
(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
&smclk_div[2:0]);
always @ (posedge mclk or posedge puc)
if (puc) smclk_div <= 3'h0;
else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
//=============================================================================
// 6) RESET GENERATION
//=============================================================================
// Generate synchronized POR
wire por_reset = !reset_n;
reg [1:0] por_s;
always @(posedge mclk_n or posedge por_reset)
if (por_reset) por_s <= 2'b11;
else por_s <= {por_s[0], 1'b0};
wire por = por_s[1];
// Generate main system reset
wire puc_reset = por_reset | wdt_reset | dbg_reset;
reg [1:0] puc_s;
always @(posedge mclk_n or posedge puc_reset)
if (puc_reset) puc_s <= 2'b11;
else puc_s <= {puc_s[0], 1'b0};
wire puc = puc_s[1];
endmodule // omsp_clock_module
`include "openMSP430_undefines.v"
|
module premuat(
inverse,
i_transize,
i_0 ,
i_1 ,
i_2 ,
i_3 ,
i_4 ,
i_5 ,
i_6 ,
i_7 ,
i_8 ,
i_9 ,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0 ,
o_1 ,
o_2 ,
o_3 ,
o_4 ,
o_5 ,
o_6 ,
o_7 ,
o_8 ,
o_9 ,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input inverse;
input [1:0] i_transize;
input signed [27:0] i_0 ;
input signed [27:0] i_1 ;
input signed [27:0] i_2 ;
input signed [27:0] i_3 ;
input signed [27:0] i_4 ;
input signed [27:0] i_5 ;
input signed [27:0] i_6 ;
input signed [27:0] i_7 ;
input signed [27:0] i_8 ;
input signed [27:0] i_9 ;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
input signed [27:0] i_16;
input signed [27:0] i_17;
input signed [27:0] i_18;
input signed [27:0] i_19;
input signed [27:0] i_20;
input signed [27:0] i_21;
input signed [27:0] i_22;
input signed [27:0] i_23;
input signed [27:0] i_24;
input signed [27:0] i_25;
input signed [27:0] i_26;
input signed [27:0] i_27;
input signed [27:0] i_28;
input signed [27:0] i_29;
input signed [27:0] i_30;
input signed [27:0] i_31;
output signed [27:0] o_0 ;
output signed [27:0] o_1 ;
output signed [27:0] o_2 ;
output signed [27:0] o_3 ;
output signed [27:0] o_4 ;
output signed [27:0] o_5 ;
output signed [27:0] o_6 ;
output signed [27:0] o_7 ;
output signed [27:0] o_8 ;
output signed [27:0] o_9 ;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
output signed [27:0] o_16;
output signed [27:0] o_17;
output signed [27:0] o_18;
output signed [27:0] o_19;
output signed [27:0] o_20;
output signed [27:0] o_21;
output signed [27:0] o_22;
output signed [27:0] o_23;
output signed [27:0] o_24;
output signed [27:0] o_25;
output signed [27:0] o_26;
output signed [27:0] o_27;
output signed [27:0] o_28;
output signed [27:0] o_29;
output signed [27:0] o_30;
output signed [27:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire enable_80;
wire enable_81;
wire enable_82;
wire enable_160;
wire enable_161;
wire enable_320;
wire signed [27:0] ip80_0;
wire signed [27:0] ip80_1;
wire signed [27:0] ip80_2;
wire signed [27:0] ip80_3;
wire signed [27:0] ip80_4;
wire signed [27:0] ip80_5;
wire signed [27:0] ip80_6;
wire signed [27:0] ip80_7;
wire signed [27:0] ip81_0;
wire signed [27:0] ip81_1;
wire signed [27:0] ip81_2;
wire signed [27:0] ip81_3;
wire signed [27:0] ip81_4;
wire signed [27:0] ip81_5;
wire signed [27:0] ip81_6;
wire signed [27:0] ip81_7;
wire signed [27:0] ip82_0;
wire signed [27:0] ip82_1;
wire signed [27:0] ip82_2;
wire signed [27:0] ip82_3;
wire signed [27:0] ip82_4;
wire signed [27:0] ip82_5;
wire signed [27:0] ip82_6;
wire signed [27:0] ip82_7;
wire signed [27:0] ip83_0;
wire signed [27:0] ip83_1;
wire signed [27:0] ip83_2;
wire signed [27:0] ip83_3;
wire signed [27:0] ip83_4;
wire signed [27:0] ip83_5;
wire signed [27:0] ip83_6;
wire signed [27:0] ip83_7;
wire signed [27:0] ip160_0 ;
wire signed [27:0] ip160_1 ;
wire signed [27:0] ip160_2 ;
wire signed [27:0] ip160_3 ;
wire signed [27:0] ip160_4 ;
wire signed [27:0] ip160_5 ;
wire signed [27:0] ip160_6 ;
wire signed [27:0] ip160_7 ;
wire signed [27:0] ip160_8 ;
wire signed [27:0] ip160_9 ;
wire signed [27:0] ip160_10;
wire signed [27:0] ip160_11;
wire signed [27:0] ip160_12;
wire signed [27:0] ip160_13;
wire signed [27:0] ip160_14;
wire signed [27:0] ip160_15;
wire signed [27:0] ip161_0 ;
wire signed [27:0] ip161_1 ;
wire signed [27:0] ip161_2 ;
wire signed [27:0] ip161_3 ;
wire signed [27:0] ip161_4 ;
wire signed [27:0] ip161_5 ;
wire signed [27:0] ip161_6 ;
wire signed [27:0] ip161_7 ;
wire signed [27:0] ip161_8 ;
wire signed [27:0] ip161_9 ;
wire signed [27:0] ip161_10;
wire signed [27:0] ip161_11;
wire signed [27:0] ip161_12;
wire signed [27:0] ip161_13;
wire signed [27:0] ip161_14;
wire signed [27:0] ip161_15;
wire signed [27:0] ip320_0 ;
wire signed [27:0] ip320_1 ;
wire signed [27:0] ip320_2 ;
wire signed [27:0] ip320_3 ;
wire signed [27:0] ip320_4 ;
wire signed [27:0] ip320_5 ;
wire signed [27:0] ip320_6 ;
wire signed [27:0] ip320_7 ;
wire signed [27:0] ip320_8 ;
wire signed [27:0] ip320_9 ;
wire signed [27:0] ip320_10;
wire signed [27:0] ip320_11;
wire signed [27:0] ip320_12;
wire signed [27:0] ip320_13;
wire signed [27:0] ip320_14;
wire signed [27:0] ip320_15;
wire signed [27:0] ip320_16;
wire signed [27:0] ip320_17;
wire signed [27:0] ip320_18;
wire signed [27:0] ip320_19;
wire signed [27:0] ip320_20;
wire signed [27:0] ip320_21;
wire signed [27:0] ip320_22;
wire signed [27:0] ip320_23;
wire signed [27:0] ip320_24;
wire signed [27:0] ip320_25;
wire signed [27:0] ip320_26;
wire signed [27:0] ip320_27;
wire signed [27:0] ip320_28;
wire signed [27:0] ip320_29;
wire signed [27:0] ip320_30;
wire signed [27:0] ip320_31;
wire signed [27:0] op80_0;
wire signed [27:0] op80_1;
wire signed [27:0] op80_2;
wire signed [27:0] op80_3;
wire signed [27:0] op80_4;
wire signed [27:0] op80_5;
wire signed [27:0] op80_6;
wire signed [27:0] op80_7;
wire signed [27:0] op81_0;
wire signed [27:0] op81_1;
wire signed [27:0] op81_2;
wire signed [27:0] op81_3;
wire signed [27:0] op81_4;
wire signed [27:0] op81_5;
wire signed [27:0] op81_6;
wire signed [27:0] op81_7;
wire signed [27:0] op82_0;
wire signed [27:0] op82_1;
wire signed [27:0] op82_2;
wire signed [27:0] op82_3;
wire signed [27:0] op82_4;
wire signed [27:0] op82_5;
wire signed [27:0] op82_6;
wire signed [27:0] op82_7;
wire signed [27:0] op83_0;
wire signed [27:0] op83_1;
wire signed [27:0] op83_2;
wire signed [27:0] op83_3;
wire signed [27:0] op83_4;
wire signed [27:0] op83_5;
wire signed [27:0] op83_6;
wire signed [27:0] op83_7;
wire signed [27:0] op160_0 ;
wire signed [27:0] op160_1 ;
wire signed [27:0] op160_2 ;
wire signed [27:0] op160_3 ;
wire signed [27:0] op160_4 ;
wire signed [27:0] op160_5 ;
wire signed [27:0] op160_6 ;
wire signed [27:0] op160_7 ;
wire signed [27:0] op160_8 ;
wire signed [27:0] op160_9 ;
wire signed [27:0] op160_10;
wire signed [27:0] op160_11;
wire signed [27:0] op160_12;
wire signed [27:0] op160_13;
wire signed [27:0] op160_14;
wire signed [27:0] op160_15;
wire signed [27:0] op161_0 ;
wire signed [27:0] op161_1 ;
wire signed [27:0] op161_2 ;
wire signed [27:0] op161_3 ;
wire signed [27:0] op161_4 ;
wire signed [27:0] op161_5 ;
wire signed [27:0] op161_6 ;
wire signed [27:0] op161_7 ;
wire signed [27:0] op161_8 ;
wire signed [27:0] op161_9 ;
wire signed [27:0] op161_10;
wire signed [27:0] op161_11;
wire signed [27:0] op161_12;
wire signed [27:0] op161_13;
wire signed [27:0] op161_14;
wire signed [27:0] op161_15;
wire signed [27:0] op320_0 ;
wire signed [27:0] op320_1 ;
wire signed [27:0] op320_2 ;
wire signed [27:0] op320_3 ;
wire signed [27:0] op320_4 ;
wire signed [27:0] op320_5 ;
wire signed [27:0] op320_6 ;
wire signed [27:0] op320_7 ;
wire signed [27:0] op320_8 ;
wire signed [27:0] op320_9 ;
wire signed [27:0] op320_10;
wire signed [27:0] op320_11;
wire signed [27:0] op320_12;
wire signed [27:0] op320_13;
wire signed [27:0] op320_14;
wire signed [27:0] op320_15;
wire signed [27:0] op320_16;
wire signed [27:0] op320_17;
wire signed [27:0] op320_18;
wire signed [27:0] op320_19;
wire signed [27:0] op320_20;
wire signed [27:0] op320_21;
wire signed [27:0] op320_22;
wire signed [27:0] op320_23;
wire signed [27:0] op320_24;
wire signed [27:0] op320_25;
wire signed [27:0] op320_26;
wire signed [27:0] op320_27;
wire signed [27:0] op320_28;
wire signed [27:0] op320_29;
wire signed [27:0] op320_30;
wire signed [27:0] op320_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign enable_80=(i_transize[1]||i_transize[0]);
assign enable_81=((~i_transize[1])&i_transize[0]);
assign enable_82=(enable_81||enable_161);
assign enable_160=i_transize[1];
assign enable_161=((~i_transize[0])&i_transize[1]);
assign enable_320=(i_transize[1]&i_transize[0]);
assign ip320_0 =inverse?i_0 :op160_0 ;
assign ip320_1 =inverse?i_1 :op160_1 ;
assign ip320_2 =inverse?i_2 :op160_2 ;
assign ip320_3 =inverse?i_3 :op160_3 ;
assign ip320_4 =inverse?i_4 :op160_4 ;
assign ip320_5 =inverse?i_5 :op160_5 ;
assign ip320_6 =inverse?i_6 :op160_6 ;
assign ip320_7 =inverse?i_7 :op160_7 ;
assign ip320_8 =inverse?i_8 :op160_8 ;
assign ip320_9 =inverse?i_9 :op160_9 ;
assign ip320_10=inverse?i_10:op160_10;
assign ip320_11=inverse?i_11:op160_11;
assign ip320_12=inverse?i_12:op160_12;
assign ip320_13=inverse?i_13:op160_13;
assign ip320_14=inverse?i_14:op160_14;
assign ip320_15=inverse?i_15:op160_15;
assign ip320_16=inverse?i_16:op161_0 ;
assign ip320_17=inverse?i_17:op161_1 ;
assign ip320_18=inverse?i_18:op161_2 ;
assign ip320_19=inverse?i_19:op161_3 ;
assign ip320_20=inverse?i_20:op161_4 ;
assign ip320_21=inverse?i_21:op161_5 ;
assign ip320_22=inverse?i_22:op161_6 ;
assign ip320_23=inverse?i_23:op161_7 ;
assign ip320_24=inverse?i_24:op161_8 ;
assign ip320_25=inverse?i_25:op161_9 ;
assign ip320_26=inverse?i_26:op161_10;
assign ip320_27=inverse?i_27:op161_11;
assign ip320_28=inverse?i_28:op161_12;
assign ip320_29=inverse?i_29:op161_13;
assign ip320_30=inverse?i_30:op161_14;
assign ip320_31=inverse?i_31:op161_15;
assign ip160_0 =inverse?op320_0 :op80_0;
assign ip160_1 =inverse?op320_1 :op80_1;
assign ip160_2 =inverse?op320_2 :op80_2;
assign ip160_3 =inverse?op320_3 :op80_3;
assign ip160_4 =inverse?op320_4 :op80_4;
assign ip160_5 =inverse?op320_5 :op80_5;
assign ip160_6 =inverse?op320_6 :op80_6;
assign ip160_7 =inverse?op320_7 :op80_7;
assign ip160_8 =inverse?op320_8 :op81_0;
assign ip160_9 =inverse?op320_9 :op81_1;
assign ip160_10=inverse?op320_10:op81_2;
assign ip160_11=inverse?op320_11:op81_3;
assign ip160_12=inverse?op320_12:op81_4;
assign ip160_13=inverse?op320_13:op81_5;
assign ip160_14=inverse?op320_14:op81_6;
assign ip160_15=inverse?op320_15:op81_7;
assign ip161_0 =inverse?op320_16:op82_0;
assign ip161_1 =inverse?op320_17:op82_1;
assign ip161_2 =inverse?op320_18:op82_2;
assign ip161_3 =inverse?op320_19:op82_3;
assign ip161_4 =inverse?op320_20:op82_4;
assign ip161_5 =inverse?op320_21:op82_5;
assign ip161_6 =inverse?op320_22:op82_6;
assign ip161_7 =inverse?op320_23:op82_7;
assign ip161_8 =inverse?op320_24:op83_0;
assign ip161_9 =inverse?op320_25:op83_1;
assign ip161_10=inverse?op320_26:op83_2;
assign ip161_11=inverse?op320_27:op83_3;
assign ip161_12=inverse?op320_28:op83_4;
assign ip161_13=inverse?op320_29:op83_5;
assign ip161_14=inverse?op320_30:op83_6;
assign ip161_15=inverse?op320_31:op83_7;
assign ip80_0=inverse?op160_0 :i_0 ;
assign ip80_1=inverse?op160_1 :i_1 ;
assign ip80_2=inverse?op160_2 :i_2 ;
assign ip80_3=inverse?op160_3 :i_3 ;
assign ip80_4=inverse?op160_4 :i_4 ;
assign ip80_5=inverse?op160_5 :i_5 ;
assign ip80_6=inverse?op160_6 :i_6 ;
assign ip80_7=inverse?op160_7 :i_7 ;
assign ip81_0=inverse?op160_8 :i_8 ;
assign ip81_1=inverse?op160_9 :i_9 ;
assign ip81_2=inverse?op160_10:i_10;
assign ip81_3=inverse?op160_11:i_11;
assign ip81_4=inverse?op160_12:i_12;
assign ip81_5=inverse?op160_13:i_13;
assign ip81_6=inverse?op160_14:i_14;
assign ip81_7=inverse?op160_15:i_15;
assign ip82_0=inverse?op161_0 :i_16;
assign ip82_1=inverse?op161_1 :i_17;
assign ip82_2=inverse?op161_2 :i_18;
assign ip82_3=inverse?op161_3 :i_19;
assign ip82_4=inverse?op161_4 :i_20;
assign ip82_5=inverse?op161_5 :i_21;
assign ip82_6=inverse?op161_6 :i_22;
assign ip82_7=inverse?op161_7 :i_23;
assign ip83_0=inverse?op161_8 :i_24;
assign ip83_1=inverse?op161_9 :i_25;
assign ip83_2=inverse?op161_10:i_26;
assign ip83_3=inverse?op161_11:i_27;
assign ip83_4=inverse?op161_12:i_28;
assign ip83_5=inverse?op161_13:i_29;
assign ip83_6=inverse?op161_14:i_30;
assign ip83_7=inverse?op161_15:i_31;
assign o_0 =inverse?op80_0:op320_0 ;
assign o_1 =inverse?op80_1:op320_1 ;
assign o_2 =inverse?op80_2:op320_2 ;
assign o_3 =inverse?op80_3:op320_3 ;
assign o_4 =inverse?op80_4:op320_4 ;
assign o_5 =inverse?op80_5:op320_5 ;
assign o_6 =inverse?op80_6:op320_6 ;
assign o_7 =inverse?op80_7:op320_7 ;
assign o_8 =inverse?op81_0:op320_8 ;
assign o_9 =inverse?op81_1:op320_9 ;
assign o_10=inverse?op81_2:op320_10;
assign o_11=inverse?op81_3:op320_11;
assign o_12=inverse?op81_4:op320_12;
assign o_13=inverse?op81_5:op320_13;
assign o_14=inverse?op81_6:op320_14;
assign o_15=inverse?op81_7:op320_15;
assign o_16=inverse?op82_0:op320_16;
assign o_17=inverse?op82_1:op320_17;
assign o_18=inverse?op82_2:op320_18;
assign o_19=inverse?op82_3:op320_19;
assign o_20=inverse?op82_4:op320_20;
assign o_21=inverse?op82_5:op320_21;
assign o_22=inverse?op82_6:op320_22;
assign o_23=inverse?op82_7:op320_23;
assign o_24=inverse?op83_0:op320_24;
assign o_25=inverse?op83_1:op320_25;
assign o_26=inverse?op83_2:op320_26;
assign o_27=inverse?op83_3:op320_27;
assign o_28=inverse?op83_4:op320_28;
assign o_29=inverse?op83_5:op320_29;
assign o_30=inverse?op83_6:op320_30;
assign o_31=inverse?op83_7:op320_31;
// ********************************************
//
// Sub Modules
//
// ********************************************
premuat_8 p80(
enable_80,
inverse,
ip80_0,
ip80_1,
ip80_2,
ip80_3,
ip80_4,
ip80_5,
ip80_6,
ip80_7,
op80_0,
op80_1,
op80_2,
op80_3,
op80_4,
op80_5,
op80_6,
op80_7
);
premuat_8 p81(
enable_81,
inverse,
ip81_0,
ip81_1,
ip81_2,
ip81_3,
ip81_4,
ip81_5,
ip81_6,
ip81_7,
op81_0,
op81_1,
op81_2,
op81_3,
op81_4,
op81_5,
op81_6,
op81_7
);
premuat_8 p82(
enable_82,
inverse,
ip82_0,
ip82_1,
ip82_2,
ip82_3,
ip82_4,
ip82_5,
ip82_6,
ip82_7,
op82_0,
op82_1,
op82_2,
op82_3,
op82_4,
op82_5,
op82_6,
op82_7
);
premuat_8 p83(
enable_81,
inverse,
ip83_0,
ip83_1,
ip83_2,
ip83_3,
ip83_4,
ip83_5,
ip83_6,
ip83_7,
op83_0,
op83_1,
op83_2,
op83_3,
op83_4,
op83_5,
op83_6,
op83_7
);
premuat_16 p160(
enable_160,
inverse,
ip160_0,
ip160_1,
ip160_2,
ip160_3,
ip160_4,
ip160_5,
ip160_6,
ip160_7,
ip160_8 ,
ip160_9 ,
ip160_10,
ip160_11,
ip160_12,
ip160_13,
ip160_14,
ip160_15,
op160_0,
op160_1,
op160_2,
op160_3,
op160_4,
op160_5,
op160_6,
op160_7,
op160_8,
op160_9,
op160_10,
op160_11,
op160_12,
op160_13,
op160_14,
op160_15
);
premuat_16 p161(
enable_161,
inverse,
ip161_0,
ip161_1,
ip161_2,
ip161_3,
ip161_4,
ip161_5,
ip161_6,
ip161_7,
ip161_8 ,
ip161_9 ,
ip161_10,
ip161_11,
ip161_12,
ip161_13,
ip161_14,
ip161_15,
op161_0,
op161_1,
op161_2,
op161_3,
op161_4,
op161_5,
op161_6,
op161_7,
op161_8 ,
op161_9 ,
op161_10,
op161_11,
op161_12,
op161_13,
op161_14,
op161_15
);
premuat_32 p320(
enable_320,
inverse,
ip320_0 ,
ip320_1 ,
ip320_2 ,
ip320_3 ,
ip320_4 ,
ip320_5 ,
ip320_6 ,
ip320_7 ,
ip320_8 ,
ip320_9 ,
ip320_10,
ip320_11,
ip320_12,
ip320_13,
ip320_14,
ip320_15,
ip320_16,
ip320_17,
ip320_18,
ip320_19,
ip320_20,
ip320_21,
ip320_22,
ip320_23,
ip320_24,
ip320_25,
ip320_26,
ip320_27,
ip320_28,
ip320_29,
ip320_30,
ip320_31,
op320_0 ,
op320_1 ,
op320_2 ,
op320_3 ,
op320_4 ,
op320_5 ,
op320_6 ,
op320_7 ,
op320_8 ,
op320_9 ,
op320_10,
op320_11,
op320_12,
op320_13,
op320_14,
op320_15,
op320_16,
op320_17,
op320_18,
op320_19,
op320_20,
op320_21,
op320_22,
op320_23,
op320_24,
op320_25,
op320_26,
op320_27,
op320_28,
op320_29,
op320_30,
op320_31
);
endmodule
|
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 25100 $
// $Date: 2011-09-01 18:44:19 +0000 (Thu, 01 Sep 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Single-Ported BRAM with byte enables
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
initial
begin : init_block
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
`else
always @(WE or DI or DATAwr) begin : combo1
integer j;
// DATA = 0; // While this line is better coding sytle, it leads to incorrect synthsis for some tools
for(j = 0; j < WE_WIDTH; j = j + 1) begin
if (WE[j]) DATA[j*CHUNKSIZE +: CHUNKSIZE] = DI[j*CHUNKSIZE +: CHUNKSIZE];
else DATA[j*CHUNKSIZE +: CHUNKSIZE] = DATAwr[j*CHUNKSIZE +: CHUNKSIZE];
end
end
`endif // !`ifdef __ICARUS__
always @(posedge CLK) begin
if (EN) begin
if (|WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
DO_R <= `BSV_ASSIGNMENT_DELAY DATA;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end
// Output driver
assign DO = (PIPELINED) ? DO_R2 : DO_R;
endmodule // BRAM1BE
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:07:26 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n1789, Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554,
n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609,
n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664,
n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686,
n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708,
n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719,
n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785,
n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796,
n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818,
n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829,
n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840,
n841, n842, n843, n844, n845, n846, n847, n848, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n947, n948, n949, n950, n951, n952,
DP_OP_15J9_123_2691_n8, DP_OP_15J9_123_2691_n7,
DP_OP_15J9_123_2691_n6, DP_OP_15J9_123_2691_n5,
DP_OP_15J9_123_2691_n4, intadd_3_B_9_, intadd_3_B_8_, intadd_3_B_7_,
intadd_3_B_6_, intadd_3_B_5_, intadd_3_B_4_, intadd_3_B_3_,
intadd_3_B_2_, intadd_3_B_1_, intadd_3_B_0_, intadd_3_CI,
intadd_3_SUM_9_, intadd_3_SUM_8_, intadd_3_SUM_7_, intadd_3_SUM_6_,
intadd_3_SUM_5_, intadd_3_SUM_4_, intadd_3_SUM_3_, intadd_3_SUM_2_,
intadd_3_SUM_1_, intadd_3_SUM_0_, intadd_3_n10, intadd_3_n9,
intadd_3_n8, intadd_3_n7, intadd_3_n6, intadd_3_n5, intadd_3_n4,
intadd_3_n3, intadd_3_n2, intadd_3_n1, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1629, n1630, n1631, n1632, n1633,
n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1642, n1643, n1644,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1788;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:2] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n947), .CK(clk), .RN(n1784), .QN(
n960) );
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n1753), .Q(
Shift_reg_FLAGS_7[1]), .QN(n959) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n1776), .Q(
intAS) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n854), .CK(clk), .RN(n1759), .Q(
Data_array_SWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n846), .CK(clk), .RN(n1755),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n845), .CK(clk), .RN(n1769),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n844), .CK(clk), .RN(n1756),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n843), .CK(clk), .RN(n1784),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n834), .CK(clk), .RN(n1778), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n833), .CK(clk), .RN(n1757), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n832), .CK(clk), .RN(n1761), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n831), .CK(clk), .RN(n1777), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n830), .CK(clk), .RN(n1783), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n829), .CK(clk), .RN(n1771), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n828), .CK(clk), .RN(n1761), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n827), .CK(clk), .RN(n1776), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n826), .CK(clk), .RN(n1760), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n825), .CK(clk), .RN(n1768), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n824), .CK(clk), .RN(n1770), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n823), .CK(clk), .RN(n1772), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n822), .CK(clk), .RN(n1761), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n821), .CK(clk), .RN(n1774), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n820), .CK(clk), .RN(n1777), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n819), .CK(clk), .RN(n1776), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n818), .CK(clk), .RN(n1784), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n817), .CK(clk), .RN(n1775), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n816), .CK(clk), .RN(n1782), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n815), .CK(clk), .RN(n1768), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n814), .CK(clk), .RN(n1770), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n813), .CK(clk), .RN(n1763), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n812), .CK(clk), .RN(n1064), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n807), .CK(clk), .RN(n989), .QN(n977)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n806), .CK(clk), .RN(n1764), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n805), .CK(clk), .RN(n1762), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n804), .CK(clk), .RN(n1767), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n803), .CK(clk), .RN(n1766), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n802), .CK(clk), .RN(n1765), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n801), .CK(clk), .RN(n1764), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n800), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n799), .CK(clk), .RN(n1767), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n797), .CK(clk), .RN(n1766), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n796), .CK(clk), .RN(n1765), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n794), .CK(clk), .RN(n1763), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n1764), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n791), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n790), .CK(clk), .RN(n1767), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n788), .CK(clk), .RN(n1763), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n787), .CK(clk), .RN(n989), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n785), .CK(clk), .RN(n1764), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n784), .CK(clk), .RN(n1762), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n782), .CK(clk), .RN(n1767), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n781), .CK(clk), .RN(n1766), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n779), .CK(clk), .RN(n1765), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1763), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n776), .CK(clk), .RN(n1766), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n775), .CK(clk), .RN(n1765), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n773), .CK(clk), .RN(n1763), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n772), .CK(clk), .RN(n1764), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n770), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n769), .CK(clk), .RN(n1767), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n767), .CK(clk), .RN(n1766), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n766), .CK(clk), .RN(n1765), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n764), .CK(clk), .RN(n1763), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n763), .CK(clk), .RN(n1764), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n761), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n760), .CK(clk), .RN(n1767), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n759), .CK(clk), .RN(n989), .Q(
DMP_SFG[13]), .QN(n1697) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n758), .CK(clk), .RN(n1766), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n757), .CK(clk), .RN(n1765), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n756), .CK(clk), .RN(n1764), .Q(
DMP_SFG[14]), .QN(n1700) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n755), .CK(clk), .RN(n1763), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n754), .CK(clk), .RN(n1064), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n753), .CK(clk), .RN(n1762), .Q(
DMP_SFG[15]), .QN(n1719) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n752), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n751), .CK(clk), .RN(n1767), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n750), .CK(clk), .RN(n1767), .Q(
DMP_SFG[16]), .QN(n1718) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n749), .CK(clk), .RN(n1766), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n748), .CK(clk), .RN(n1765), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n747), .CK(clk), .RN(n1766), .Q(
DMP_SFG[17]), .QN(n1733) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n746), .CK(clk), .RN(n1763), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n745), .CK(clk), .RN(n1064), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n744), .CK(clk), .RN(n1765), .Q(
DMP_SFG[18]), .QN(n1732) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n743), .CK(clk), .RN(n989), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n742), .CK(clk), .RN(n1764), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n1774), .Q(
DMP_SFG[19]), .QN(n1740) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n740), .CK(clk), .RN(n1768), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n739), .CK(clk), .RN(n1770), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n738), .CK(clk), .RN(n1784), .Q(
DMP_SFG[20]), .QN(n1739) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n737), .CK(clk), .RN(n1772), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n736), .CK(clk), .RN(n1761), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n735), .CK(clk), .RN(n1777), .Q(
DMP_SFG[21]), .QN(n1750) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n734), .CK(clk), .RN(n1756), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n733), .CK(clk), .RN(n1774), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n732), .CK(clk), .RN(n1775), .Q(
DMP_SFG[22]), .QN(n1749) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n731), .CK(clk), .RN(n1777), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1776), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n729), .CK(clk), .RN(n1779), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n728), .CK(clk), .RN(n1758), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n726), .CK(clk), .RN(n1757), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n725), .CK(clk), .RN(n1781), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n724), .CK(clk), .RN(n1783), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n723), .CK(clk), .RN(n1769), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n721), .CK(clk), .RN(n1771), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n720), .CK(clk), .RN(n1773), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1780), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n1760), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n716), .CK(clk), .RN(n1778), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n715), .CK(clk), .RN(n1779), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n714), .CK(clk), .RN(n1782), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n713), .CK(clk), .RN(n1756), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n711), .CK(clk), .RN(n1768), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n710), .CK(clk), .RN(n1770), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n1772), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n708), .CK(clk), .RN(n1761), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n706), .CK(clk), .RN(n1774), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n705), .CK(clk), .RN(n1777), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n704), .CK(clk), .RN(n1776), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1784), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n701), .CK(clk), .RN(n1775), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n700), .CK(clk), .RN(n1782), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n699), .CK(clk), .RN(n1783), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n698), .CK(clk), .RN(n1769), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n696), .CK(clk), .RN(n1771), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n695), .CK(clk), .RN(n1773), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n694), .CK(clk), .RN(n1757), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n693), .CK(clk), .RN(n1780), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n691), .CK(clk), .RN(n1760), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n690), .CK(clk), .RN(n1778), .QN(
n968) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n1779), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n688), .CK(clk), .RN(n1760), .QN(
n969) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n687), .CK(clk), .RN(n1778), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n685), .CK(clk), .RN(n1772), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n684), .CK(clk), .RN(n1761), .QN(
n975) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n683), .CK(clk), .RN(n1756), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n682), .CK(clk), .RN(n1774), .QN(
n962) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n681), .CK(clk), .RN(n1777), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n680), .CK(clk), .RN(n1776), .QN(
n970) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n679), .CK(clk), .RN(n1774), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n1777), .QN(
n961) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n677), .CK(clk), .RN(n1776), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n676), .CK(clk), .RN(n1784), .QN(
n976) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n675), .CK(clk), .RN(n1775), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n673), .CK(clk), .RN(n1769), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n672), .CK(clk), .RN(n1771), .QN(
n972) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n671), .CK(clk), .RN(n1773), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n669), .CK(clk), .RN(n1780), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n668), .CK(clk), .RN(n1760),
.QN(n973) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n667), .CK(clk), .RN(n1778), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n665), .CK(clk), .RN(n1779), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n664), .CK(clk), .RN(n1758),
.QN(n974) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n663), .CK(clk), .RN(n1781), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n661), .CK(clk), .RN(n1773), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n659), .CK(clk), .RN(n1770), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n657), .CK(clk), .RN(n1774), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n655), .CK(clk), .RN(n1781), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n653), .CK(clk), .RN(n1757), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n651), .CK(clk), .RN(n1772), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n649), .CK(clk), .RN(n1777), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n648), .CK(clk), .RN(n1758),
.QN(n971) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n647), .CK(clk), .RN(n1771), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n638), .CK(clk), .RN(n1758), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n637), .CK(clk), .RN(n1773), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n636), .CK(clk), .RN(n1775), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n635), .CK(clk), .RN(n1771), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n634), .CK(clk), .RN(n1760), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n632), .CK(clk), .RN(n1782), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n631), .CK(clk), .RN(n1782), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n630), .CK(clk), .RN(n1768), .QN(
n1656) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n629), .CK(clk), .RN(n1781), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n628), .CK(clk), .RN(n1779), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n1774), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n626), .CK(clk), .RN(n1776), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n625), .CK(clk), .RN(n1769), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n610), .CK(clk), .RN(n1761), .Q(
LZD_output_NRM2_EW[4]), .QN(n1701) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n609), .CK(clk), .RN(n1775), .Q(
DmP_mant_SFG_SWR[1]), .QN(n1027) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n607), .CK(clk), .RN(n1770), .Q(
LZD_output_NRM2_EW[2]), .QN(n1698) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n604), .CK(clk), .RN(n1756), .Q(
LZD_output_NRM2_EW[1]), .QN(n1689) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[0]), .QN(n1029) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n598), .CK(clk), .RN(n1772), .Q(
LZD_output_NRM2_EW[3]), .QN(n1702) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1776), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n592), .CK(clk), .RN(n1777), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1673) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n590), .CK(clk), .RN(n1769), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1670) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n586), .CK(clk), .RN(n1768), .Q(
DmP_mant_SFG_SWR[9]), .QN(n1033) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n580), .CK(clk), .RN(n1779), .Q(
DmP_mant_SFG_SWR[11]), .QN(n1017) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n578), .CK(clk), .RN(n1781), .Q(
DmP_mant_SFG_SWR[10]), .QN(n1018) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n549), .CK(clk), .RN(n1784), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1730) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n548), .CK(clk), .RN(n1775), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1731) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n545), .CK(clk), .RN(n1779), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1747) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n544), .CK(clk), .RN(n1781), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1676) );
CMPR32X2TS intadd_3_U11 ( .A(n1697), .B(intadd_3_B_0_), .C(intadd_3_CI),
.CO(intadd_3_n10), .S(intadd_3_SUM_0_) );
CMPR32X2TS intadd_3_U10 ( .A(n1700), .B(intadd_3_B_1_), .C(intadd_3_n10),
.CO(intadd_3_n9), .S(intadd_3_SUM_1_) );
CMPR32X2TS intadd_3_U9 ( .A(n1719), .B(intadd_3_B_2_), .C(intadd_3_n9), .CO(
intadd_3_n8), .S(intadd_3_SUM_2_) );
CMPR32X2TS intadd_3_U8 ( .A(n1718), .B(intadd_3_B_3_), .C(intadd_3_n8), .CO(
intadd_3_n7), .S(intadd_3_SUM_3_) );
CMPR32X2TS intadd_3_U7 ( .A(n1733), .B(intadd_3_B_4_), .C(intadd_3_n7), .CO(
intadd_3_n6), .S(intadd_3_SUM_4_) );
CMPR32X2TS intadd_3_U6 ( .A(n1732), .B(intadd_3_B_5_), .C(intadd_3_n6), .CO(
intadd_3_n5), .S(intadd_3_SUM_5_) );
CMPR32X2TS intadd_3_U5 ( .A(n1740), .B(intadd_3_B_6_), .C(intadd_3_n5), .CO(
intadd_3_n4), .S(intadd_3_SUM_6_) );
CMPR32X2TS intadd_3_U4 ( .A(n1739), .B(intadd_3_B_7_), .C(intadd_3_n4), .CO(
intadd_3_n3), .S(intadd_3_SUM_7_) );
CMPR32X2TS intadd_3_U3 ( .A(n1750), .B(intadd_3_B_8_), .C(intadd_3_n3), .CO(
intadd_3_n2), .S(intadd_3_SUM_8_) );
CMPR32X2TS intadd_3_U2 ( .A(n1749), .B(intadd_3_B_9_), .C(intadd_3_n2), .CO(
intadd_3_n1), .S(intadd_3_SUM_9_) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1755),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n640), .CK(clk), .RN(n1770), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n633), .CK(clk), .RN(n1780), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n577), .CK(clk), .RN(n1783), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n576), .CK(clk), .RN(n1769), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n574), .CK(clk), .RN(n1771), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n573), .CK(clk), .RN(n1773), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n571), .CK(clk), .RN(n1757), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n570), .CK(clk), .RN(n1783), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n569), .CK(clk), .RN(n1769), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n568), .CK(clk), .RN(n1771), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n567), .CK(clk), .RN(n1773), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n566), .CK(clk), .RN(n1757), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n565), .CK(clk), .RN(n1780), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n564), .CK(clk), .RN(n1760), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n563), .CK(clk), .RN(n1778), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n1779), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n559), .CK(clk), .RN(n1758), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n558), .CK(clk), .RN(n1756), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n555), .CK(clk), .RN(n1774), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n639), .CK(clk), .RN(n1773), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n583), .CK(clk), .RN(n1783), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n572), .CK(clk), .RN(n1780), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n561), .CK(clk), .RN(n1781), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n560), .CK(clk), .RN(n1783), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n557), .CK(clk), .RN(n1777), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n556), .CK(clk), .RN(n1776), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1768), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n841), .CK(clk), .RN(n1757), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n840), .CK(clk), .RN(n1780), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n839), .CK(clk), .RN(n1760), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n838), .CK(clk), .RN(n1778), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n837), .CK(clk), .RN(n1779), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n836), .CK(clk), .RN(n1760), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n835), .CK(clk), .RN(n1778), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n624), .CK(clk), .RN(n1758), .Q(
final_result_ieee[31]) );
DFFSX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1023), .CK(clk), .SN(n1066), .Q(
n1786), .QN(n1785) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1753), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1661) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n599), .CK(clk), .RN(n1770), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1728) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1679) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n594), .CK(clk), .RN(n1777), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1690) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n611), .CK(clk), .RN(n1761), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1678) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n622), .CK(clk), .RN(n1756), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1737) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n906), .CK(clk), .RN(n1754), .Q(
intDY_EWSW[3]), .QN(n1703) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n887), .CK(clk), .RN(n1777),
.Q(intDY_EWSW[22]), .QN(n1664) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n888), .CK(clk), .RN(n1754),
.Q(intDY_EWSW[21]), .QN(n1707) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n883), .CK(clk), .RN(n988), .Q(
intDY_EWSW[26]), .QN(n1720) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n884), .CK(clk), .RN(n1753),
.Q(intDY_EWSW[25]), .QN(n1721) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n891), .CK(clk), .RN(n1755),
.Q(intDY_EWSW[18]), .QN(n1727) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n892), .CK(clk), .RN(n1759),
.Q(intDY_EWSW[17]), .QN(n1723) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n894), .CK(clk), .RN(n1753),
.Q(intDY_EWSW[15]), .QN(n1722) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n895), .CK(clk), .RN(n1753),
.Q(intDY_EWSW[14]), .QN(n1663) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n896), .CK(clk), .RN(n1776),
.Q(intDY_EWSW[13]), .QN(n1706) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n897), .CK(clk), .RN(n1773),
.Q(intDY_EWSW[12]), .QN(n1710) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n901), .CK(clk), .RN(n1754), .Q(
intDY_EWSW[8]), .QN(n1724) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n915), .CK(clk), .RN(n1776),
.Q(intDX_EWSW[28]), .QN(n1726) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n917), .CK(clk), .RN(n1780),
.Q(intDX_EWSW[26]), .QN(n1675) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n918), .CK(clk), .RN(n1774),
.Q(intDX_EWSW[25]), .QN(n1674) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n919), .CK(clk), .RN(n1757),
.Q(intDX_EWSW[24]), .QN(n1743) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n927), .CK(clk), .RN(n988), .Q(
intDX_EWSW[16]), .QN(n1692) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n936), .CK(clk), .RN(n1778), .Q(
intDX_EWSW[7]), .QN(n1658) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n937), .CK(clk), .RN(n1754), .Q(
intDX_EWSW[6]), .QN(n1684) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n938), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[5]), .QN(n1683) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n939), .CK(clk), .RN(n1755), .Q(
intDX_EWSW[4]), .QN(n1657) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n848), .CK(clk), .RN(n1759), .Q(
shift_value_SHT2_EWR[4]), .QN(n1681) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n1754), .Q(
Data_array_SWR[12]), .QN(n1742) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n874), .CK(clk), .RN(n1755), .Q(
Data_array_SWR[22]), .QN(n1653) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n866), .CK(clk), .RN(n1755), .Q(
Data_array_SWR[14]), .QN(n1671) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n875), .CK(clk), .RN(n1760), .Q(
Data_array_SWR[23]), .QN(n1667) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n692), .CK(clk), .RN(n1066), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1738) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n697), .CK(clk), .RN(n1065), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1716) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1775), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1717) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n727), .CK(clk), .RN(n1784), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1688) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n600), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1686) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n951), .CK(clk), .RN(
n1781), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1699) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n596), .CK(clk), .RN(n1761), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1659) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n579), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1680) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n587), .CK(clk), .RN(n1784), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1691) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n589), .CK(clk), .RN(n1783), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1682) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n879), .CK(clk), .RN(n1756),
.Q(intDY_EWSW[30]), .QN(n1695) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n904), .CK(clk), .RN(n1758), .Q(
intDY_EWSW[5]), .QN(n1662) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n905), .CK(clk), .RN(n1760), .Q(
intDY_EWSW[4]), .QN(n1709) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n882), .CK(clk), .RN(n1779),
.Q(intDY_EWSW[27]), .QN(n1713) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n885), .CK(clk), .RN(n1755),
.Q(intDY_EWSW[24]), .QN(n1652) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n886), .CK(clk), .RN(n1759),
.Q(intDY_EWSW[23]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n890), .CK(clk), .RN(n1756),
.Q(intDY_EWSW[19]), .QN(n1666) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n893), .CK(clk), .RN(n1778),
.Q(intDY_EWSW[16]), .QN(n1711) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n900), .CK(clk), .RN(n1759), .Q(
intDY_EWSW[9]), .QN(n1705) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n903), .CK(clk), .RN(n1754), .Q(
intDY_EWSW[6]), .QN(n1704) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n621), .CK(clk), .RN(n1772), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1693) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n907), .CK(clk), .RN(n1759), .Q(
intDY_EWSW[2]), .QN(n1708) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n902), .CK(clk), .RN(n1759), .Q(
intDY_EWSW[7]), .QN(n1714) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n880), .CK(clk), .RN(n988), .Q(
intDY_EWSW[29]), .QN(n1660) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n617), .CK(clk), .RN(n1774), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1685) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n616), .CK(clk), .RN(n1769), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1655) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n1780), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1650) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n614), .CK(clk), .RN(n1772), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1651) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n808), .CK(clk), .RN(n989), .Q(
DMP_EXP_EWSW[26]), .QN(n1744) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n809), .CK(clk), .RN(n1764), .Q(
DMP_EXP_EWSW[25]), .QN(n1736) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n810), .CK(clk), .RN(n1762), .Q(
DMP_EXP_EWSW[24]), .QN(n1669) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n613), .CK(clk), .RN(n1777), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1677) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n642), .CK(clk), .RN(n1770), .Q(
DmP_EXP_EWSW[26]), .QN(n1741) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n643), .CK(clk), .RN(n1776), .Q(
DmP_EXP_EWSW[25]), .QN(n1745) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1758), .Q(
DmP_EXP_EWSW[24]), .QN(n1668) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n862), .CK(clk), .RN(n1754), .Q(
Data_array_SWR[10]), .QN(n1734) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n872), .CK(clk), .RN(n1774), .Q(
Data_array_SWR[20]), .QN(n1746) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n870), .CK(clk), .RN(n1754), .Q(
Data_array_SWR[18]), .QN(n1725) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n867), .CK(clk), .RN(n1771), .Q(
Data_array_SWR[15]), .QN(n1672) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n871), .CK(clk), .RN(n1779), .Q(
Data_array_SWR[19]), .QN(n1729) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n863), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[11]), .QN(n1735) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n949), .CK(clk), .RN(n1754), .Q(
n1654), .QN(n1748) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n940), .CK(clk), .RN(n1765), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n920), .CK(clk), .RN(n1754),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n930), .CK(clk), .RN(n1753),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n928), .CK(clk), .RN(n1759),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n922), .CK(clk), .RN(n1755),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n876), .CK(clk), .RN(n1783), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n935), .CK(clk), .RN(n989), .Q(
intDX_EWSW[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n1774), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n926), .CK(clk), .RN(n1759),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n877), .CK(clk), .RN(n1782), .Q(
Data_array_SWR[25]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n932), .CK(clk), .RN(n1754),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n934), .CK(clk), .RN(n1759), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n916), .CK(clk), .RN(n989), .Q(
intDX_EWSW[27]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n581), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n591), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n865), .CK(clk), .RN(n1759), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n943), .CK(clk), .RN(n1784), .Q(
intDX_EWSW[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n605), .CK(clk), .RN(n1781), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n623), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n925), .CK(clk), .RN(n1753),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1771), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n952), .CK(clk), .RN(
n1760), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n860), .CK(clk), .RN(n1772), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n868), .CK(clk), .RN(n1755), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n620), .CK(clk), .RN(n1768), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n856), .CK(clk), .RN(n1770), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1756), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n762), .CK(clk), .RN(n1763), .Q(
DMP_SFG[12]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n858), .CK(clk), .RN(n1781), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n859), .CK(clk), .RN(n1768), .Q(
Data_array_SWR[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n792), .CK(clk), .RN(n1064), .Q(
DMP_SFG[2]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n912), .CK(clk), .RN(n1755),
.Q(intDX_EWSW[31]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n850), .CK(clk), .RN(n1753), .Q(
shift_value_SHT2_EWR[3]), .QN(n1694) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n1762), .Q(
DMP_SFG[8]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n913), .CK(clk), .RN(n1757),
.Q(intDX_EWSW[30]), .QN(n1665) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n914), .CK(clk), .RN(n1766),
.Q(intDX_EWSW[29]), .QN(n1715) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n899), .CK(clk), .RN(n1755),
.Q(intDY_EWSW[10]), .QN(n964) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n795), .CK(clk), .RN(n989), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n909), .CK(clk), .RN(n1782), .Q(
intDY_EWSW[0]), .QN(n967) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n777), .CK(clk), .RN(n1767), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n786), .CK(clk), .RN(n1766), .Q(
DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n789), .CK(clk), .RN(n1765), .Q(
DMP_SFG[3]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n765), .CK(clk), .RN(n1064), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n546), .CK(clk), .RN(n1771), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n547), .CK(clk), .RN(n1768), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n582), .CK(clk), .RN(n1779), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n584), .CK(clk), .RN(n1769), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n597), .CK(clk), .RN(n1775), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n601), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n847), .CK(clk), .RN(n1759),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n771), .CK(clk), .RN(n1766), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n768), .CK(clk), .RN(n1765), .Q(
DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n780), .CK(clk), .RN(n1763), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n798), .CK(clk), .RN(n1764), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n783), .CK(clk), .RN(n1064), .Q(
DMP_SFG[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n811), .CK(clk), .RN(n1767), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n712), .CK(clk), .RN(n1777), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n717), .CK(clk), .RN(n1774), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1776), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n855), .CK(clk), .RN(n1755), .Q(
Data_array_SWR[3]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n898), .CK(clk), .RN(n1775),
.Q(intDY_EWSW[11]), .QN(n1696) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n878), .CK(clk), .RN(n1753),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n931), .CK(clk), .RN(n1755),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n923), .CK(clk), .RN(n989), .Q(
intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n929), .CK(clk), .RN(n1754),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n921), .CK(clk), .RN(n1759),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n942), .CK(clk), .RN(n989), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n941), .CK(clk), .RN(n1753), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n933), .CK(clk), .RN(n1753),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n881), .CK(clk), .RN(n1775),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n924), .CK(clk), .RN(n1755),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n861), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n869), .CK(clk), .RN(n1769), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n873), .CK(clk), .RN(n1783), .Q(
Data_array_SWR[21]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[0]) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .RN(n1754), .Q(
n1789), .QN(n1788) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n908), .CK(clk), .RN(n1754), .Q(
intDY_EWSW[1]), .QN(n1752) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n585), .CK(clk), .RN(n1761), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1032) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n674), .CK(clk), .RN(n1784), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n670), .CK(clk), .RN(n1760), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n666), .CK(clk), .RN(n1779), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n654), .CK(clk), .RN(n1757), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n652), .CK(clk), .RN(n1781), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n662), .CK(clk), .RN(n1758), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n686), .CK(clk), .RN(n1757), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n646), .CK(clk), .RN(n1773), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n660), .CK(clk), .RN(n1782), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n650), .CK(clk), .RN(n1777), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n658), .CK(clk), .RN(n1783), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n656), .CK(clk), .RN(n1773), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n889), .CK(clk), .RN(n1753),
.Q(intDY_EWSW[20]), .QN(n1712) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n851), .CK(clk), .RN(n988), .Q(
shift_value_SHT2_EWR[2]), .QN(n1687) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n645), .CK(clk), .RN(n1772), .Q(
DmP_EXP_EWSW[23]), .QN(n1025) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1782), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n852), .CK(clk), .RN(n1755), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n853), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n1776), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n588), .CK(clk), .RN(n1774), .Q(
DmP_mant_SFG_SWR[7]), .QN(n1031) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n554), .CK(clk), .RN(n1782), .Q(
DmP_mant_SFG_SWR[15]), .QN(n1019) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n553), .CK(clk), .RN(n1768), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1020) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n552), .CK(clk), .RN(n1770), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1021) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n551), .CK(clk), .RN(n1772), .Q(
DmP_mant_SFG_SWR[18]), .QN(n1022) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n550), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[19]), .QN(n1024) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n606), .CK(clk), .RN(n1779), .Q(
DmP_mant_SFG_SWR[8]), .QN(n1028) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n595), .CK(clk), .RN(n1778), .Q(
DmP_mant_SFG_SWR[6]), .QN(n1030) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n612), .CK(clk), .RN(n1756), .Q(
DmP_mant_SFG_SWR[14]), .QN(n1026) );
ADDFX1TS DP_OP_15J9_123_2691_U8 ( .A(n1689), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J9_123_2691_n8), .CO(DP_OP_15J9_123_2691_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J9_123_2691_U7 ( .A(n1698), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J9_123_2691_n7), .CO(DP_OP_15J9_123_2691_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J9_123_2691_U6 ( .A(n1702), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J9_123_2691_n6), .CO(DP_OP_15J9_123_2691_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J9_123_2691_U5 ( .A(n1701), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J9_123_2691_n5), .CO(DP_OP_15J9_123_2691_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n910), .CK(clk), .RN(n1778), .Q(
left_right_SHT2), .QN(n966) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n944), .CK(clk), .RN(n1759), .Q(
Shift_reg_FLAGS_7[0]), .QN(n953) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n950), .CK(clk), .RN(n1754), .Q(
Shift_reg_FLAGS_7_6), .QN(n1034) );
AOI211X1TS U964 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n956), .B0(n1409), .C0(
n1398), .Y(n1403) );
NAND2X4TS U965 ( .A(n1005), .B(n953), .Y(n1444) );
AOI211X1TS U966 ( .A0(n1487), .A1(Data_array_SWR[2]), .B0(n1091), .C0(n1090),
.Y(n1624) );
CMPR32X2TS U967 ( .A(DMP_SFG[1]), .B(n1497), .C(n1502), .CO(n1515), .S(n1067) );
NOR2XLTS U968 ( .A(n1350), .B(n1081), .Y(n1085) );
OAI211XLTS U969 ( .A0(n1315), .A1(n1013), .B0(n1314), .C0(n1313), .Y(n861)
);
OAI211XLTS U970 ( .A0(n1323), .A1(n1013), .B0(n1322), .C0(n1321), .Y(n857)
);
OAI211XLTS U971 ( .A0(n1319), .A1(n1012), .B0(n1318), .C0(n1317), .Y(n863)
);
OAI211X1TS U972 ( .A0(n1328), .A1(n1013), .B0(n1327), .C0(n1326), .Y(n871)
);
OAI211X1TS U973 ( .A0(n1308), .A1(n1013), .B0(n1307), .C0(n1306), .Y(n867)
);
NOR2X4TS U974 ( .A(n955), .B(n1276), .Y(n1330) );
OAI21XLTS U975 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1038), .Y(n1039) );
BUFX3TS U976 ( .A(n1160), .Y(n954) );
NAND3BXLTS U977 ( .AN(n1140), .B(n1138), .C(n1137), .Y(n1157) );
INVX4TS U978 ( .A(n1421), .Y(n955) );
INVX3TS U979 ( .A(n982), .Y(n958) );
INVX4TS U980 ( .A(n983), .Y(n956) );
INVX1TS U981 ( .A(LZD_output_NRM2_EW[0]), .Y(n1354) );
NAND2BXLTS U982 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1096) );
CLKBUFX2TS U983 ( .A(n1712), .Y(n996) );
CLKBUFX2TS U984 ( .A(n1752), .Y(n1011) );
OAI211X1TS U985 ( .A0(n1333), .A1(n1013), .B0(n1332), .C0(n1331), .Y(n856)
);
OAI21X1TS U986 ( .A0(n1408), .A1(n1013), .B0(n1349), .Y(n868) );
OAI211X1TS U987 ( .A0(n1312), .A1(n1013), .B0(n1311), .C0(n1310), .Y(n853)
);
AOI222X1TS U988 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1397), .B0(n985), .B1(n1004), .C0(n1340), .C1(DmP_mant_SHT1_SW[22]), .Y(n1334) );
AOI222X1TS U989 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1413), .B0(n985), .B1(
n1003), .C0(n1340), .C1(n997), .Y(n1296) );
INVX3TS U990 ( .A(n1330), .Y(n991) );
AOI222X1TS U991 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1397), .B0(n985), .B1(
n1000), .C0(n1409), .C1(DmP_mant_SHT1_SW[14]), .Y(n1308) );
INVX3TS U992 ( .A(n1401), .Y(n1397) );
INVX3TS U993 ( .A(n1346), .Y(n1324) );
INVX3TS U994 ( .A(n1401), .Y(n1413) );
AND2X2TS U995 ( .A(n1276), .B(n1421), .Y(n1277) );
OAI211X2TS U996 ( .A0(n1690), .A1(n1265), .B0(n1057), .C0(n1056), .Y(n1280)
);
AOI31X1TS U997 ( .A0(n1055), .A1(Raw_mant_NRM_SWR[8]), .A2(n1691), .B0(n1371), .Y(n1056) );
INVX3TS U998 ( .A(n954), .Y(n1453) );
INVX3TS U999 ( .A(n954), .Y(n1255) );
INVX3TS U1000 ( .A(n1199), .Y(n1190) );
INVX3TS U1001 ( .A(n1199), .Y(n1451) );
NOR2X4TS U1002 ( .A(n1159), .B(n1034), .Y(n1160) );
NOR3X1TS U1003 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .C(n1266),
.Y(n1038) );
AO21X1TS U1004 ( .A0(n1050), .A1(Raw_mant_NRM_SWR[18]), .B0(n1364), .Y(n1051) );
XOR2XLTS U1005 ( .A(DMP_SFG[12]), .B(n994), .Y(n1467) );
AO22XLTS U1006 ( .A0(n1386), .A1(add_subt), .B0(n992), .B1(intAS), .Y(n911)
);
BUFX3TS U1007 ( .A(n1444), .Y(n1642) );
INVX3TS U1008 ( .A(n1059), .Y(n985) );
OAI211X1TS U1009 ( .A0(n1099), .A1(n1154), .B0(n1098), .C0(n1097), .Y(n1104)
);
OAI211X2TS U1010 ( .A0(intDX_EWSW[20]), .A1(n996), .B0(n1150), .C0(n1136),
.Y(n1145) );
INVX3TS U1011 ( .A(n1492), .Y(n1491) );
BUFX3TS U1012 ( .A(n1386), .Y(n957) );
CLKINVX3TS U1013 ( .A(n1579), .Y(n1461) );
NOR2X6TS U1014 ( .A(shift_value_SHT2_EWR[4]), .B(n1089), .Y(n1086) );
OR2X1TS U1015 ( .A(n978), .B(Shift_amount_SHT1_EWR[0]), .Y(n1059) );
CLKINVX3TS U1016 ( .A(n1578), .Y(n1469) );
OAI211X2TS U1017 ( .A0(intDX_EWSW[12]), .A1(n1710), .B0(n1131), .C0(n1117),
.Y(n1133) );
INVX3TS U1018 ( .A(n1789), .Y(n1446) );
INVX4TS U1019 ( .A(rst), .Y(n989) );
NAND2X1TS U1020 ( .A(n1053), .B(n1679), .Y(n1037) );
AOI31XLTS U1021 ( .A0(n1050), .A1(Raw_mant_NRM_SWR[16]), .A2(n1693), .B0(
n1049), .Y(n1057) );
NAND2X1TS U1022 ( .A(n1357), .B(n1678), .Y(n1036) );
CLKAND2X2TS U1023 ( .A(n1358), .B(n1359), .Y(n1357) );
NAND2X1TS U1024 ( .A(n1038), .B(n1682), .Y(n1265) );
NOR2XLTS U1025 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1040)
);
NAND2X1TS U1026 ( .A(n1055), .B(n1680), .Y(n1266) );
AOI222X1TS U1027 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1397), .B0(n985), .B1(
n997), .C0(n1340), .C1(DmP_mant_SHT1_SW[8]), .Y(n1315) );
AOI222X1TS U1028 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1397), .B0(n985), .B1(
n998), .C0(n1340), .C1(n999), .Y(n1323) );
AOI222X1TS U1029 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1397), .B0(n985), .B1(
n1002), .C0(n1340), .C1(DmP_mant_SHT1_SW[10]), .Y(n1319) );
AOI222X1TS U1030 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1397), .B0(n985), .B1(
n1001), .C0(n1340), .C1(DmP_mant_SHT1_SW[12]), .Y(n1316) );
AOI222X1TS U1031 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1397), .B0(n985), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1340), .C1(DmP_mant_SHT1_SW[18]), .Y(n1328) );
OAI21XLTS U1032 ( .A0(n1678), .A1(n1411), .B0(n1294), .Y(n1295) );
OAI21XLTS U1033 ( .A0(n1691), .A1(n1401), .B0(n1344), .Y(n1345) );
AOI222X1TS U1034 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1413), .B0(n985), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1340), .C1(n998), .Y(n1333) );
OAI2BB2XLTS U1035 ( .B0(intDY_EWSW[0]), .B1(n1107), .A0N(intDX_EWSW[1]),
.A1N(n1011), .Y(n1109) );
NAND2BXLTS U1036 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1108) );
AOI2BB2XLTS U1037 ( .B0(intDX_EWSW[3]), .B1(n1703), .A0N(intDY_EWSW[2]),
.A1N(n1110), .Y(n1111) );
NAND2BXLTS U1038 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1123) );
NAND3XLTS U1039 ( .A(n1724), .B(n1121), .C(intDX_EWSW[8]), .Y(n1122) );
NAND2BXLTS U1040 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1142) );
NOR2XLTS U1041 ( .A(n1153), .B(intDY_EWSW[24]), .Y(n1095) );
NAND2BXLTS U1042 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1121) );
NAND2BXLTS U1043 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1117) );
NAND2BXLTS U1044 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1136) );
NOR2XLTS U1045 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1041) );
AOI221X1TS U1046 ( .A0(n1011), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1723), .C0(n1208), .Y(n1215) );
OAI2BB2XLTS U1047 ( .B0(intDY_EWSW[22]), .B1(n1146), .A0N(intDX_EWSW[23]),
.A1N(n1010), .Y(n1147) );
NAND2BXLTS U1048 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1097) );
NAND3XLTS U1049 ( .A(n1720), .B(n1096), .C(intDX_EWSW[26]), .Y(n1098) );
NAND2BXLTS U1050 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1151) );
AO22XLTS U1051 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1544), .B0(n1496), .B1(n1673), .Y(n965) );
AOI222X4TS U1052 ( .A0(Data_array_SWR[21]), .A1(n1461), .B0(
Data_array_SWR[17]), .B1(n1086), .C0(Data_array_SWR[25]), .C1(n1469),
.Y(n1555) );
NAND2BXLTS U1053 ( .AN(n1080), .B(n1376), .Y(n1081) );
NAND3XLTS U1054 ( .A(n1375), .B(exp_rslt_NRM2_EW1[4]), .C(n1079), .Y(n1080)
);
NAND2BXLTS U1055 ( .AN(n1376), .B(n1073), .Y(n1076) );
NAND4BXLTS U1056 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1071), .C(n1070), .D(n1069), .Y(n1072) );
AOI31XLTS U1057 ( .A0(n1680), .A1(Raw_mant_NRM_SWR[11]), .A2(n1053), .B0(
n1051), .Y(n1046) );
NOR2XLTS U1058 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1044) );
OAI21XLTS U1059 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1686), .B0(n1659), .Y(n1052) );
AOI222X4TS U1060 ( .A0(Data_array_SWR[21]), .A1(n1512), .B0(
Data_array_SWR[17]), .B1(n1511), .C0(Data_array_SWR[25]), .C1(n1486),
.Y(n1477) );
NAND2BXLTS U1061 ( .AN(n1265), .B(Raw_mant_NRM_SWR[5]), .Y(n1369) );
AOI221X1TS U1062 ( .A0(n1664), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1010), .C0(n1211), .Y(n1212) );
AOI221X1TS U1063 ( .A0(n996), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]), .B1(
n1707), .C0(n1210), .Y(n1213) );
AOI222X1TS U1064 ( .A0(DMP_SFG[12]), .A1(n994), .B0(DMP_SFG[12]), .B1(n1353),
.C0(n994), .C1(n1353), .Y(intadd_3_B_0_) );
OAI21XLTS U1065 ( .A0(n1524), .A1(n1503), .B0(n1522), .Y(n1481) );
AOI2BB2XLTS U1066 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n1492), .A0N(n1496),
.A1N(DmP_mant_SFG_SWR[23]), .Y(intadd_3_B_8_) );
AOI2BB2XLTS U1067 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1492), .A0N(n1543),
.A1N(DmP_mant_SFG_SWR[22]), .Y(intadd_3_B_7_) );
CLKAND2X2TS U1068 ( .A(DMP_SFG[5]), .B(n1480), .Y(n1530) );
NAND2X1TS U1069 ( .A(n1534), .B(DMP_SFG[7]), .Y(n1586) );
OAI21XLTS U1070 ( .A0(n1589), .A1(n1586), .B0(n1569), .Y(n1570) );
NAND3XLTS U1071 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1661), .C(
n1699), .Y(n1379) );
OAI21XLTS U1072 ( .A0(n1728), .A1(n1401), .B0(n1400), .Y(n1402) );
AO22XLTS U1073 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1397), .B0(
Raw_mant_NRM_SWR[0]), .B1(n1399), .Y(n1398) );
OAI21XLTS U1074 ( .A0(n1680), .A1(n1411), .B0(n1410), .Y(n1412) );
AOI31X1TS U1075 ( .A0(n995), .A1(DMP_SFG[2]), .A2(n1504), .B0(n1514), .Y(
n1523) );
CLKAND2X2TS U1076 ( .A(DMP_SFG[9]), .B(n1557), .Y(n1593) );
CLKAND2X2TS U1077 ( .A(n1738), .B(n1083), .Y(n1084) );
AOI222X1TS U1078 ( .A0(n1604), .A1(n958), .B0(n1646), .B1(Data_array_SWR[9]),
.C0(n1603), .C1(n1542), .Y(n1602) );
NAND4XLTS U1079 ( .A(n1362), .B(n1365), .C(n1361), .D(n1360), .Y(n1363) );
OAI21XLTS U1080 ( .A0(n1267), .A1(n1266), .B0(n1369), .Y(n1268) );
BUFX4TS U1081 ( .A(n1161), .Y(n1261) );
AO22XLTS U1082 ( .A0(n1391), .A1(intDY_EWSW[20]), .B0(n957), .B1(Data_Y[20]),
.Y(n889) );
AO22XLTS U1083 ( .A0(n1016), .A1(DmP_EXP_EWSW[17]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[17]), .Y(n656) );
AO22XLTS U1084 ( .A0(n1016), .A1(DmP_EXP_EWSW[16]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[16]), .Y(n658) );
AO22XLTS U1085 ( .A0(n1016), .A1(DmP_EXP_EWSW[20]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[20]), .Y(n650) );
AO22XLTS U1086 ( .A0(n1016), .A1(DmP_EXP_EWSW[15]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[15]), .Y(n660) );
AO22XLTS U1087 ( .A0(n1016), .A1(DmP_EXP_EWSW[22]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[22]), .Y(n646) );
AO22XLTS U1088 ( .A0(n1654), .A1(DmP_EXP_EWSW[2]), .B0(n1449), .B1(
DmP_mant_SHT1_SW[2]), .Y(n686) );
AO22XLTS U1089 ( .A0(n1654), .A1(DmP_EXP_EWSW[14]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[14]), .Y(n662) );
AO22XLTS U1090 ( .A0(n1016), .A1(DmP_EXP_EWSW[19]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[19]), .Y(n652) );
AO22XLTS U1091 ( .A0(n1016), .A1(DmP_EXP_EWSW[18]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[18]), .Y(n654) );
AO22XLTS U1092 ( .A0(n1654), .A1(DmP_EXP_EWSW[12]), .B0(n1450), .B1(
DmP_mant_SHT1_SW[12]), .Y(n666) );
AO22XLTS U1093 ( .A0(n1654), .A1(DmP_EXP_EWSW[10]), .B0(n1449), .B1(
DmP_mant_SHT1_SW[10]), .Y(n670) );
AO22XLTS U1094 ( .A0(n1654), .A1(DmP_EXP_EWSW[8]), .B0(n1449), .B1(
DmP_mant_SHT1_SW[8]), .Y(n674) );
NOR2XLTS U1095 ( .A(n1591), .B(n1589), .Y(n1549) );
OAI21XLTS U1096 ( .A0(n1588), .A1(n1547), .B0(n1586), .Y(n1548) );
AO22XLTS U1097 ( .A0(n1391), .A1(intDY_EWSW[1]), .B0(n1387), .B1(Data_Y[1]),
.Y(n908) );
AOI2BB2XLTS U1098 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1336), .A0N(n1334), .A1N(
n990), .Y(n1301) );
AOI2BB2XLTS U1099 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1336), .A0N(n1328), .A1N(
n990), .Y(n1303) );
AOI2BB2XLTS U1100 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1336), .A0N(n1319),
.A1N(n990), .Y(n1313) );
AO22XLTS U1101 ( .A0(n1386), .A1(Data_X[19]), .B0(n1389), .B1(intDX_EWSW[19]), .Y(n924) );
AO22XLTS U1102 ( .A0(n993), .A1(Data_Y[28]), .B0(n1388), .B1(intDY_EWSW[28]),
.Y(n881) );
AO22XLTS U1103 ( .A0(n1387), .A1(Data_X[10]), .B0(n1392), .B1(intDX_EWSW[10]), .Y(n933) );
AO22XLTS U1104 ( .A0(n1395), .A1(Data_X[2]), .B0(n1392), .B1(intDX_EWSW[2]),
.Y(n941) );
AO22XLTS U1105 ( .A0(n1395), .A1(Data_X[1]), .B0(n1388), .B1(intDX_EWSW[1]),
.Y(n942) );
AO22XLTS U1106 ( .A0(n957), .A1(Data_X[22]), .B0(n1388), .B1(intDX_EWSW[22]),
.Y(n921) );
AO22XLTS U1107 ( .A0(n1395), .A1(Data_X[14]), .B0(n1393), .B1(intDX_EWSW[14]), .Y(n929) );
AO22XLTS U1108 ( .A0(n957), .A1(Data_X[20]), .B0(n992), .B1(intDX_EWSW[20]),
.Y(n923) );
AO22XLTS U1109 ( .A0(n1387), .A1(Data_X[12]), .B0(n1389), .B1(intDX_EWSW[12]), .Y(n931) );
AO22XLTS U1110 ( .A0(n1387), .A1(Data_Y[31]), .B0(n1389), .B1(intDY_EWSW[31]), .Y(n878) );
AO22XLTS U1111 ( .A0(n1394), .A1(intDY_EWSW[11]), .B0(n993), .B1(Data_Y[11]),
.Y(n898) );
OAI21XLTS U1112 ( .A0(n1010), .A1(n1255), .B0(n1200), .Y(n811) );
AO22XLTS U1113 ( .A0(n1448), .A1(DMP_SHT2_EWSW[5]), .B0(n1642), .B1(
DMP_SFG[5]), .Y(n783) );
AO22XLTS U1114 ( .A0(n1640), .A1(DMP_SHT2_EWSW[0]), .B0(n1642), .B1(
DMP_SFG[0]), .Y(n798) );
AO22XLTS U1115 ( .A0(n1640), .A1(DMP_SHT2_EWSW[6]), .B0(n1642), .B1(
DMP_SFG[6]), .Y(n780) );
AO22XLTS U1116 ( .A0(n1448), .A1(DMP_SHT2_EWSW[10]), .B0(n1444), .B1(
DMP_SFG[10]), .Y(n768) );
AO22XLTS U1117 ( .A0(n1448), .A1(DMP_SHT2_EWSW[9]), .B0(n1642), .B1(
DMP_SFG[9]), .Y(n771) );
AO22XLTS U1118 ( .A0(n1640), .A1(n1494), .B0(n1556), .B1(DmP_mant_SFG_SWR[2]), .Y(n601) );
AO22XLTS U1119 ( .A0(n1448), .A1(n1495), .B0(n1556), .B1(DmP_mant_SFG_SWR[3]), .Y(n597) );
AO22XLTS U1120 ( .A0(n1640), .A1(n1552), .B0(n1556), .B1(
DmP_mant_SFG_SWR[12]), .Y(n584) );
AO22XLTS U1121 ( .A0(n1448), .A1(n1601), .B0(n1556), .B1(
DmP_mant_SFG_SWR[13]), .Y(n582) );
AO22XLTS U1122 ( .A0(n1640), .A1(DMP_SHT2_EWSW[11]), .B0(n1444), .B1(
DMP_SFG[11]), .Y(n765) );
AO22XLTS U1123 ( .A0(n1388), .A1(intDY_EWSW[0]), .B0(n1395), .B1(Data_Y[0]),
.Y(n909) );
AO22XLTS U1124 ( .A0(n1640), .A1(DMP_SHT2_EWSW[1]), .B0(n1642), .B1(
DMP_SFG[1]), .Y(n795) );
AO22XLTS U1125 ( .A0(n1389), .A1(intDY_EWSW[10]), .B0(n993), .B1(Data_Y[10]),
.Y(n899) );
AO22XLTS U1126 ( .A0(n992), .A1(intDX_EWSW[29]), .B0(n1395), .B1(Data_X[29]),
.Y(n914) );
AO22XLTS U1127 ( .A0(n1394), .A1(intDX_EWSW[30]), .B0(n1387), .B1(Data_X[30]), .Y(n913) );
AO22XLTS U1128 ( .A0(n1640), .A1(DMP_SHT2_EWSW[8]), .B0(n1556), .B1(
DMP_SFG[8]), .Y(n774) );
AO22XLTS U1129 ( .A0(n957), .A1(Data_X[31]), .B0(n1388), .B1(intDX_EWSW[31]),
.Y(n912) );
AO22XLTS U1130 ( .A0(n1448), .A1(DMP_SHT2_EWSW[2]), .B0(n1642), .B1(
DMP_SFG[2]), .Y(n792) );
OAI211XLTS U1131 ( .A0(n1315), .A1(n991), .B0(n1286), .C0(n1285), .Y(n859)
);
OAI211XLTS U1132 ( .A0(n1296), .A1(n991), .B0(n1290), .C0(n1289), .Y(n858)
);
AOI2BB2XLTS U1133 ( .B0(n1563), .B1(intadd_3_SUM_3_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1785), .Y(n620) );
OAI21XLTS U1134 ( .A0(n1415), .A1(n991), .B0(n1298), .Y(n860) );
AO22XLTS U1135 ( .A0(n1395), .A1(Data_X[18]), .B0(n1392), .B1(intDX_EWSW[18]), .Y(n925) );
AOI2BB2XLTS U1136 ( .B0(n1565), .B1(intadd_3_SUM_0_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1785), .Y(n623) );
AOI2BB2XLTS U1137 ( .B0(n1563), .B1(intadd_3_SUM_4_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1785), .Y(n619) );
AOI2BB2XLTS U1138 ( .B0(n1598), .B1(n1485), .A0N(Raw_mant_NRM_SWR[8]), .A1N(
n1563), .Y(n605) );
AO22XLTS U1139 ( .A0(n1386), .A1(Data_X[0]), .B0(n1394), .B1(intDX_EWSW[0]),
.Y(n943) );
AOI2BB2XLTS U1140 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1336), .A0N(n1308),
.A1N(n990), .Y(n1299) );
AOI2BB2XLTS U1141 ( .B0(n1563), .B1(n1518), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n1598), .Y(n591) );
NOR2XLTS U1142 ( .A(n1514), .B(n1513), .Y(n1517) );
AOI2BB2XLTS U1143 ( .B0(n1598), .B1(n1564), .A0N(Raw_mant_NRM_SWR[13]),
.A1N(n1563), .Y(n581) );
NAND2BXLTS U1144 ( .AN(n1560), .B(n1559), .Y(n1561) );
AOI31XLTS U1145 ( .A0(n1591), .A1(n1571), .A2(n1592), .B0(n1558), .Y(n1562)
);
AO22XLTS U1146 ( .A0(n1386), .A1(Data_X[27]), .B0(n1394), .B1(intDX_EWSW[27]), .Y(n916) );
AO22XLTS U1147 ( .A0(n1390), .A1(Data_X[9]), .B0(n1392), .B1(intDX_EWSW[9]),
.Y(n934) );
AO22XLTS U1148 ( .A0(n957), .A1(Data_X[11]), .B0(n1389), .B1(intDX_EWSW[11]),
.Y(n932) );
AO22XLTS U1149 ( .A0(n1395), .A1(Data_X[17]), .B0(n1392), .B1(intDX_EWSW[17]), .Y(n926) );
AOI2BB2XLTS U1150 ( .B0(n1598), .B1(intadd_3_SUM_5_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1598), .Y(n618) );
AO22XLTS U1151 ( .A0(n957), .A1(Data_X[8]), .B0(n1388), .B1(intDX_EWSW[8]),
.Y(n935) );
AO22XLTS U1152 ( .A0(n993), .A1(Data_X[21]), .B0(n1393), .B1(intDX_EWSW[21]),
.Y(n922) );
AO22XLTS U1153 ( .A0(n1387), .A1(Data_X[15]), .B0(n992), .B1(intDX_EWSW[15]),
.Y(n928) );
AO22XLTS U1154 ( .A0(n1387), .A1(Data_X[13]), .B0(n992), .B1(intDX_EWSW[13]),
.Y(n930) );
AO22XLTS U1155 ( .A0(n1390), .A1(Data_X[23]), .B0(n1394), .B1(intDX_EWSW[23]), .Y(n920) );
AO22XLTS U1156 ( .A0(n1395), .A1(Data_X[3]), .B0(n1389), .B1(intDX_EWSW[3]),
.Y(n940) );
AOI2BB2XLTS U1157 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1336), .A0N(n1316),
.A1N(n990), .Y(n1317) );
AOI2BB2XLTS U1158 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1336), .A0N(n1325), .A1N(
n990), .Y(n1326) );
AOI2BB2XLTS U1159 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1336), .A0N(n1305), .A1N(
n990), .Y(n1306) );
OAI21XLTS U1160 ( .A0(n1404), .A1(n991), .B0(n1343), .Y(n870) );
AO22XLTS U1161 ( .A0(n957), .A1(Data_Y[29]), .B0(n992), .B1(intDY_EWSW[29]),
.Y(n880) );
AO22XLTS U1162 ( .A0(n1389), .A1(intDY_EWSW[7]), .B0(n993), .B1(Data_Y[7]),
.Y(n902) );
AO22XLTS U1163 ( .A0(n1392), .A1(intDY_EWSW[2]), .B0(n1387), .B1(Data_Y[2]),
.Y(n907) );
AO22XLTS U1164 ( .A0(n992), .A1(intDY_EWSW[6]), .B0(n1387), .B1(Data_Y[6]),
.Y(n903) );
AO22XLTS U1165 ( .A0(n1392), .A1(intDY_EWSW[9]), .B0(n1395), .B1(Data_Y[9]),
.Y(n900) );
AO22XLTS U1166 ( .A0(n1391), .A1(intDY_EWSW[16]), .B0(n993), .B1(Data_Y[16]),
.Y(n893) );
AO22XLTS U1167 ( .A0(n1394), .A1(intDY_EWSW[19]), .B0(n993), .B1(Data_Y[19]),
.Y(n890) );
AO22XLTS U1168 ( .A0(n1391), .A1(intDY_EWSW[23]), .B0(n957), .B1(Data_Y[23]),
.Y(n886) );
AO22XLTS U1169 ( .A0(n1391), .A1(intDY_EWSW[24]), .B0(n957), .B1(Data_Y[24]),
.Y(n885) );
AO22XLTS U1170 ( .A0(n1393), .A1(intDY_EWSW[27]), .B0(n1390), .B1(Data_Y[27]), .Y(n882) );
AO22XLTS U1171 ( .A0(n1393), .A1(intDY_EWSW[4]), .B0(n1395), .B1(Data_Y[4]),
.Y(n905) );
AO22XLTS U1172 ( .A0(n1388), .A1(intDY_EWSW[5]), .B0(n957), .B1(Data_Y[5]),
.Y(n904) );
AO22XLTS U1173 ( .A0(n1390), .A1(Data_Y[30]), .B0(n1394), .B1(intDY_EWSW[30]), .Y(n879) );
OAI21XLTS U1174 ( .A0(n1524), .A1(n1523), .B0(n1522), .Y(n1525) );
AOI31XLTS U1175 ( .A0(n1533), .A1(n1532), .A2(n1531), .B0(n1546), .Y(n1536)
);
AO22XLTS U1176 ( .A0(n1786), .A1(Raw_mant_NRM_SWR[4]), .B0(n1785), .B1(n1498), .Y(n596) );
OAI21XLTS U1177 ( .A0(n1381), .A1(n1094), .B0(n1379), .Y(n951) );
OAI21XLTS U1178 ( .A0(n1396), .A1(n991), .B0(n1337), .Y(n875) );
OAI21XLTS U1179 ( .A0(n1421), .A1(n1681), .B0(n1274), .Y(n848) );
AO22XLTS U1180 ( .A0(n1387), .A1(Data_X[4]), .B0(n992), .B1(intDX_EWSW[4]),
.Y(n939) );
AO22XLTS U1181 ( .A0(n957), .A1(Data_X[5]), .B0(n1393), .B1(intDX_EWSW[5]),
.Y(n938) );
AO22XLTS U1182 ( .A0(n993), .A1(Data_X[6]), .B0(n1393), .B1(intDX_EWSW[6]),
.Y(n937) );
AO22XLTS U1183 ( .A0(n993), .A1(Data_X[7]), .B0(n1393), .B1(intDX_EWSW[7]),
.Y(n936) );
AO22XLTS U1184 ( .A0(n957), .A1(Data_X[16]), .B0(n1394), .B1(intDX_EWSW[16]),
.Y(n927) );
AO22XLTS U1185 ( .A0(n992), .A1(intDX_EWSW[24]), .B0(n1387), .B1(Data_X[24]),
.Y(n919) );
AO22XLTS U1186 ( .A0(n1388), .A1(intDX_EWSW[25]), .B0(n1395), .B1(Data_X[25]), .Y(n918) );
AO22XLTS U1187 ( .A0(n1392), .A1(intDX_EWSW[26]), .B0(n1387), .B1(Data_X[26]), .Y(n917) );
AO22XLTS U1188 ( .A0(n1393), .A1(intDX_EWSW[28]), .B0(n1387), .B1(Data_X[28]), .Y(n915) );
AO22XLTS U1189 ( .A0(n1393), .A1(intDY_EWSW[8]), .B0(n1395), .B1(Data_Y[8]),
.Y(n901) );
AO22XLTS U1190 ( .A0(n1392), .A1(intDY_EWSW[12]), .B0(n993), .B1(Data_Y[12]),
.Y(n897) );
AO22XLTS U1191 ( .A0(n1388), .A1(intDY_EWSW[13]), .B0(n993), .B1(Data_Y[13]),
.Y(n896) );
AO22XLTS U1192 ( .A0(n992), .A1(intDY_EWSW[14]), .B0(n993), .B1(Data_Y[14]),
.Y(n895) );
AO22XLTS U1193 ( .A0(n1388), .A1(intDY_EWSW[15]), .B0(n993), .B1(Data_Y[15]),
.Y(n894) );
AO22XLTS U1194 ( .A0(n1393), .A1(intDY_EWSW[17]), .B0(n993), .B1(Data_Y[17]),
.Y(n892) );
AO22XLTS U1195 ( .A0(n1392), .A1(intDY_EWSW[18]), .B0(n993), .B1(Data_Y[18]),
.Y(n891) );
AO22XLTS U1196 ( .A0(n1389), .A1(intDY_EWSW[25]), .B0(n1387), .B1(Data_Y[25]), .Y(n884) );
AO22XLTS U1197 ( .A0(n1394), .A1(intDY_EWSW[26]), .B0(n1395), .B1(Data_Y[26]), .Y(n883) );
AO22XLTS U1198 ( .A0(n1389), .A1(intDY_EWSW[21]), .B0(n1395), .B1(Data_Y[21]), .Y(n888) );
AO22XLTS U1199 ( .A0(n1389), .A1(intDY_EWSW[22]), .B0(n957), .B1(Data_Y[22]),
.Y(n887) );
AO22XLTS U1200 ( .A0(n1394), .A1(intDY_EWSW[3]), .B0(n957), .B1(Data_Y[3]),
.Y(n906) );
OAI21XLTS U1201 ( .A0(n1465), .A1(n1560), .B0(n1559), .Y(n1466) );
NOR2XLTS U1202 ( .A(n1533), .B(n1524), .Y(n1507) );
OAI21XLTS U1203 ( .A0(n1513), .A1(n1505), .B0(n1523), .Y(n1506) );
NAND2BXLTS U1204 ( .AN(n1593), .B(n1592), .Y(n1594) );
NOR2XLTS U1205 ( .A(n1591), .B(n1590), .Y(n1595) );
NOR2XLTS U1206 ( .A(n1454), .B(SIGN_FLAG_SHT1SHT2), .Y(n1351) );
AO22XLTS U1207 ( .A0(n1626), .A1(n1639), .B0(final_result_ieee[21]), .B1(
n1625), .Y(n556) );
AO22XLTS U1208 ( .A0(n1626), .A1(n1638), .B0(final_result_ieee[20]), .B1(
n1625), .Y(n557) );
AO22XLTS U1209 ( .A0(n1626), .A1(n1494), .B0(final_result_ieee[0]), .B1(
n1625), .Y(n560) );
AO22XLTS U1210 ( .A0(n1626), .A1(n1495), .B0(final_result_ieee[1]), .B1(
n1625), .Y(n561) );
AO22XLTS U1211 ( .A0(n1626), .A1(n1601), .B0(final_result_ieee[11]), .B1(
n1625), .Y(n572) );
AO22XLTS U1212 ( .A0(n1626), .A1(n1552), .B0(final_result_ieee[10]), .B1(
n1625), .Y(n583) );
AO21XLTS U1213 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1420), .B0(n1373), .Y(n604) );
AO21XLTS U1214 ( .A0(LZD_output_NRM2_EW[4]), .A1(n956), .B0(n1356), .Y(n610)
);
OAI21XLTS U1215 ( .A0(n1664), .A1(n1451), .B0(n1164), .Y(n647) );
AO22XLTS U1216 ( .A0(n1016), .A1(DmP_EXP_EWSW[21]), .B0(n1450), .B1(n1004),
.Y(n648) );
OAI21XLTS U1217 ( .A0(n1707), .A1(n1451), .B0(n1171), .Y(n649) );
OAI21XLTS U1218 ( .A0(n996), .A1(n1451), .B0(n1172), .Y(n651) );
OAI21XLTS U1219 ( .A0(n1666), .A1(n1451), .B0(n1165), .Y(n653) );
OAI21XLTS U1220 ( .A0(n1727), .A1(n1451), .B0(n1177), .Y(n655) );
OAI21XLTS U1221 ( .A0(n1723), .A1(n1451), .B0(n1169), .Y(n657) );
OAI21XLTS U1222 ( .A0(n1711), .A1(n1190), .B0(n1168), .Y(n659) );
OAI21XLTS U1223 ( .A0(n1722), .A1(n1190), .B0(n1189), .Y(n661) );
OAI21XLTS U1224 ( .A0(n1663), .A1(n1190), .B0(n1162), .Y(n663) );
AO22XLTS U1225 ( .A0(n1654), .A1(DmP_EXP_EWSW[13]), .B0(n1450), .B1(n1000),
.Y(n664) );
OAI21XLTS U1226 ( .A0(n1706), .A1(n1190), .B0(n1170), .Y(n665) );
OAI21XLTS U1227 ( .A0(n1710), .A1(n1190), .B0(n1180), .Y(n667) );
AO22XLTS U1228 ( .A0(n1654), .A1(DmP_EXP_EWSW[11]), .B0(n1449), .B1(n1001),
.Y(n668) );
OAI21XLTS U1229 ( .A0(n1251), .A1(n1190), .B0(n1185), .Y(n669) );
OAI21XLTS U1230 ( .A0(n964), .A1(n1190), .B0(n1182), .Y(n671) );
AO22XLTS U1231 ( .A0(n1654), .A1(DmP_EXP_EWSW[9]), .B0(n1449), .B1(n1002),
.Y(n672) );
OAI21XLTS U1232 ( .A0(n1705), .A1(n1190), .B0(n1183), .Y(n673) );
OAI21XLTS U1233 ( .A0(n1724), .A1(n1190), .B0(n1181), .Y(n675) );
AO22XLTS U1234 ( .A0(n1654), .A1(DmP_EXP_EWSW[7]), .B0(n1449), .B1(n997),
.Y(n676) );
OAI21XLTS U1235 ( .A0(n1714), .A1(n1190), .B0(n1173), .Y(n677) );
AO22XLTS U1236 ( .A0(n1654), .A1(DmP_EXP_EWSW[6]), .B0(n1449), .B1(n1003),
.Y(n678) );
OAI21XLTS U1237 ( .A0(n1704), .A1(n1190), .B0(n1174), .Y(n679) );
AO22XLTS U1238 ( .A0(n1654), .A1(DmP_EXP_EWSW[5]), .B0(n1449), .B1(n1006),
.Y(n680) );
OAI21XLTS U1239 ( .A0(n1662), .A1(n1190), .B0(n1175), .Y(n681) );
AO22XLTS U1240 ( .A0(n1654), .A1(DmP_EXP_EWSW[4]), .B0(n1449), .B1(n999),
.Y(n682) );
OAI21XLTS U1241 ( .A0(n1709), .A1(n1236), .B0(n1176), .Y(n683) );
AO22XLTS U1242 ( .A0(n1654), .A1(DmP_EXP_EWSW[3]), .B0(n1449), .B1(n998),
.Y(n684) );
OAI21XLTS U1243 ( .A0(n1703), .A1(n1236), .B0(n1186), .Y(n685) );
OAI21XLTS U1244 ( .A0(n1708), .A1(n1236), .B0(n1184), .Y(n687) );
AO22XLTS U1245 ( .A0(n1654), .A1(DmP_EXP_EWSW[1]), .B0(n1449), .B1(n1007),
.Y(n688) );
OAI21XLTS U1246 ( .A0(n1011), .A1(n1236), .B0(n1178), .Y(n689) );
AO22XLTS U1247 ( .A0(n1016), .A1(DmP_EXP_EWSW[0]), .B0(n1457), .B1(n1008),
.Y(n690) );
OAI21XLTS U1248 ( .A0(n967), .A1(n1236), .B0(n1179), .Y(n691) );
OAI21XLTS U1249 ( .A0(n1240), .A1(n1161), .B0(n1236), .Y(n1238) );
AO22XLTS U1250 ( .A0(n1443), .A1(n1442), .B0(ZERO_FLAG_EXP), .B1(n1161), .Y(
n802) );
OAI21XLTS U1251 ( .A0(n1665), .A1(n1236), .B0(n1166), .Y(n804) );
OAI21XLTS U1252 ( .A0(n1715), .A1(n1236), .B0(n1167), .Y(n805) );
OAI21XLTS U1253 ( .A0(n1726), .A1(n1451), .B0(n1163), .Y(n806) );
OAI21XLTS U1254 ( .A0(n1713), .A1(n1453), .B0(n1196), .Y(n807) );
OAI21XLTS U1255 ( .A0(n1664), .A1(n1453), .B0(n1245), .Y(n812) );
OAI21XLTS U1256 ( .A0(n1707), .A1(n1453), .B0(n1192), .Y(n813) );
OAI21XLTS U1257 ( .A0(n996), .A1(n1453), .B0(n1198), .Y(n814) );
OAI21XLTS U1258 ( .A0(n1666), .A1(n1453), .B0(n1241), .Y(n815) );
OAI21XLTS U1259 ( .A0(n1727), .A1(n1255), .B0(n1242), .Y(n816) );
OAI21XLTS U1260 ( .A0(n1723), .A1(n1255), .B0(n1247), .Y(n817) );
OAI21XLTS U1261 ( .A0(n1711), .A1(n1255), .B0(n1195), .Y(n818) );
OAI21XLTS U1262 ( .A0(n1722), .A1(n1255), .B0(n1254), .Y(n819) );
OAI21XLTS U1263 ( .A0(n1663), .A1(n1255), .B0(n1246), .Y(n820) );
OAI21XLTS U1264 ( .A0(n1706), .A1(n1255), .B0(n1252), .Y(n821) );
OAI21XLTS U1265 ( .A0(n1710), .A1(n1255), .B0(n1248), .Y(n822) );
OAI21XLTS U1266 ( .A0(n1251), .A1(n1255), .B0(n1250), .Y(n823) );
OAI21XLTS U1267 ( .A0(n964), .A1(n1255), .B0(n1243), .Y(n824) );
OAI21XLTS U1268 ( .A0(n1705), .A1(n1255), .B0(n1194), .Y(n825) );
OAI21XLTS U1269 ( .A0(n1714), .A1(n1255), .B0(n1193), .Y(n827) );
OAI21XLTS U1270 ( .A0(n1704), .A1(n1264), .B0(n1259), .Y(n828) );
OAI21XLTS U1271 ( .A0(n1662), .A1(n1264), .B0(n1263), .Y(n829) );
OAI21XLTS U1272 ( .A0(n1709), .A1(n1264), .B0(n1260), .Y(n830) );
OAI21XLTS U1273 ( .A0(n1703), .A1(n1264), .B0(n1257), .Y(n831) );
OAI21XLTS U1274 ( .A0(n1708), .A1(n1264), .B0(n1258), .Y(n832) );
OAI21XLTS U1275 ( .A0(n1011), .A1(n1264), .B0(n1256), .Y(n833) );
OAI21XLTS U1276 ( .A0(n967), .A1(n1453), .B0(n1197), .Y(n834) );
AO22XLTS U1277 ( .A0(n1384), .A1(busy), .B0(n1383), .B1(n1005), .Y(n947) );
INVX2TS U1278 ( .A(n978), .Y(n1420) );
OA22X1TS U1279 ( .A0(n1492), .A1(DmP_mant_SFG_SWR[14]), .B0(n1026), .B1(
n1491), .Y(n963) );
BUFX3TS U1280 ( .A(n955), .Y(n1419) );
INVX2TS U1281 ( .A(left_right_SHT2), .Y(n981) );
INVX2TS U1282 ( .A(n1014), .Y(n1015) );
INVX2TS U1283 ( .A(n959), .Y(n978) );
INVX2TS U1284 ( .A(n1390), .Y(n1391) );
INVX2TS U1285 ( .A(n1626), .Y(n979) );
INVX2TS U1286 ( .A(n1626), .Y(n980) );
INVX2TS U1287 ( .A(n981), .Y(n982) );
INVX2TS U1288 ( .A(n1420), .Y(n983) );
CLKINVX3TS U1289 ( .A(n1059), .Y(n984) );
INVX2TS U1290 ( .A(n1015), .Y(n986) );
INVX2TS U1291 ( .A(n986), .Y(n987) );
OAI21XLTS U1292 ( .A0(n1713), .A1(n1190), .B0(n1188), .Y(n641) );
AOI222X1TS U1293 ( .A0(n1621), .A1(n958), .B0(n1646), .B1(Data_array_SWR[8]),
.C0(n1619), .C1(n1542), .Y(n1617) );
CLKINVX3TS U1294 ( .A(n1623), .Y(n1646) );
AOI222X1TS U1295 ( .A0(n1621), .A1(left_right_SHT2), .B0(Data_array_SWR[8]),
.B1(n1620), .C0(n1619), .C1(n1618), .Y(n1631) );
CLKINVX3TS U1296 ( .A(n1582), .Y(n1620) );
BUFX4TS U1297 ( .A(n1642), .Y(n1633) );
NOR2X4TS U1298 ( .A(shift_value_SHT2_EWR[4]), .B(left_right_SHT2), .Y(n1618)
);
NOR2X4TS U1299 ( .A(shift_value_SHT2_EWR[4]), .B(n958), .Y(n1542) );
INVX2TS U1300 ( .A(rst), .Y(n988) );
INVX2TS U1301 ( .A(n1330), .Y(n990) );
INVX2TS U1302 ( .A(n1390), .Y(n992) );
INVX4TS U1303 ( .A(n1391), .Y(n993) );
NOR2X2TS U1304 ( .A(shift_value_SHT2_EWR[2]), .B(n1694), .Y(n1486) );
OAI22X2TS U1305 ( .A0(n1667), .A1(n1089), .B0(n1729), .B1(n1474), .Y(n1615)
);
OAI22X2TS U1306 ( .A0(n1653), .A1(n1089), .B0(n1725), .B1(n1474), .Y(n1606)
);
INVX2TS U1307 ( .A(n963), .Y(n994) );
INVX2TS U1308 ( .A(n965), .Y(n995) );
NOR2X4TS U1309 ( .A(n1474), .B(shift_value_SHT2_EWR[4]), .Y(n1487) );
BUFX4TS U1310 ( .A(n1764), .Y(n1754) );
BUFX4TS U1311 ( .A(n1762), .Y(n1759) );
BUFX4TS U1312 ( .A(n1767), .Y(n1755) );
BUFX4TS U1313 ( .A(n1763), .Y(n1753) );
BUFX3TS U1314 ( .A(n988), .Y(n1065) );
AOI222X1TS U1315 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1397), .B0(n984), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1340), .C1(DmP_mant_SHT1_SW[16]), .Y(n1305) );
INVX2TS U1316 ( .A(n976), .Y(n997) );
INVX2TS U1317 ( .A(n975), .Y(n998) );
INVX2TS U1318 ( .A(n962), .Y(n999) );
AOI222X1TS U1319 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1397), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1340), .C0(n984), .C1(DmP_mant_SHT1_SW[19]), .Y(n1325) );
INVX2TS U1320 ( .A(n974), .Y(n1000) );
INVX2TS U1321 ( .A(n973), .Y(n1001) );
INVX2TS U1322 ( .A(n972), .Y(n1002) );
INVX2TS U1323 ( .A(n961), .Y(n1003) );
INVX2TS U1324 ( .A(n971), .Y(n1004) );
INVX2TS U1325 ( .A(n960), .Y(n1005) );
INVX2TS U1326 ( .A(n970), .Y(n1006) );
INVX2TS U1327 ( .A(n969), .Y(n1007) );
INVX2TS U1328 ( .A(n968), .Y(n1008) );
INVX2TS U1329 ( .A(n977), .Y(n1009) );
OAI21XLTS U1330 ( .A0(n1032), .A1(n1411), .B0(n1406), .Y(n1407) );
INVX2TS U1331 ( .A(intDY_EWSW[23]), .Y(n1010) );
BUFX4TS U1332 ( .A(n954), .Y(n1187) );
INVX2TS U1333 ( .A(n1277), .Y(n1012) );
INVX4TS U1334 ( .A(n1277), .Y(n1013) );
INVX4TS U1335 ( .A(n1444), .Y(n1640) );
INVX4TS U1336 ( .A(n1444), .Y(n1448) );
INVX4TS U1337 ( .A(n1642), .Y(n1649) );
INVX4TS U1338 ( .A(n1642), .Y(n1637) );
INVX2TS U1339 ( .A(n1788), .Y(n1014) );
OAI211XLTS U1340 ( .A0(n1325), .A1(n1012), .B0(n1302), .C0(n1301), .Y(n873)
);
OAI211XLTS U1341 ( .A0(n1305), .A1(n1012), .B0(n1304), .C0(n1303), .Y(n869)
);
AOI222X1TS U1342 ( .A0(n1604), .A1(n982), .B0(Data_array_SWR[9]), .B1(n1620),
.C0(n1603), .C1(n1618), .Y(n1630) );
AOI32X1TS U1343 ( .A0(n1727), .A1(n1142), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1666), .Y(n1143) );
AOI221X1TS U1344 ( .A0(n1727), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1666), .C0(n1209), .Y(n1214) );
AOI221X1TS U1345 ( .A0(n1713), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1726), .C0(n1202), .Y(n1206) );
AOI221X1TS U1346 ( .A0(n964), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1251), .C0(n1217), .Y(n1222) );
AOI221X1TS U1347 ( .A0(n1708), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1703), .C0(n1225), .Y(n1230) );
AOI221X1TS U1348 ( .A0(n1663), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1722), .C0(n1219), .Y(n1220) );
AOI221X1TS U1349 ( .A0(n1710), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1706), .C0(n1218), .Y(n1221) );
AOI222X4TS U1350 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1397), .B0(n985), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1340), .C1(DmP_mant_SHT1_SW[17]), .Y(n1347) );
OAI211XLTS U1351 ( .A0(n1323), .A1(n990), .B0(n1282), .C0(n1281), .Y(n855)
);
OAI31XLTS U1352 ( .A0(n1443), .A1(n1240), .A2(n1453), .B0(n1239), .Y(n801)
);
NOR2X2TS U1353 ( .A(n1058), .B(n956), .Y(n1373) );
NOR4BBX2TS U1354 ( .AN(n1048), .BN(n1046), .C(n1269), .D(n1045), .Y(n1058)
);
NOR2X2TS U1355 ( .A(n1025), .B(DMP_EXP_EWSW[23]), .Y(n1428) );
XNOR2X2TS U1356 ( .A(DMP_exp_NRM2_EW[0]), .B(n1354), .Y(n1374) );
XNOR2X2TS U1357 ( .A(DMP_exp_NRM2_EW[6]), .B(n1074), .Y(n1376) );
XNOR2X2TS U1358 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J9_123_2691_n4), .Y(
n1375) );
BUFX4TS U1359 ( .A(n1066), .Y(n1774) );
BUFX4TS U1360 ( .A(n1065), .Y(n1760) );
BUFX4TS U1361 ( .A(n1066), .Y(n1777) );
BUFX4TS U1362 ( .A(n1065), .Y(n1778) );
BUFX4TS U1363 ( .A(n1066), .Y(n1776) );
BUFX4TS U1364 ( .A(n1065), .Y(n1779) );
BUFX3TS U1365 ( .A(n988), .Y(n1066) );
NOR2X2TS U1366 ( .A(n1352), .B(DMP_SFG[11]), .Y(n1560) );
NOR2X2TS U1367 ( .A(n1501), .B(DMP_SFG[3]), .Y(n1513) );
NOR2X2TS U1368 ( .A(n1478), .B(DMP_SFG[4]), .Y(n1524) );
NOR2X2TS U1369 ( .A(n1534), .B(DMP_SFG[7]), .Y(n1588) );
OAI211XLTS U1370 ( .A0(n995), .A1(DMP_SFG[2]), .B0(n1502), .C0(DMP_SFG[1]),
.Y(n1505) );
NOR2XLTS U1371 ( .A(n1119), .B(intDY_EWSW[10]), .Y(n1120) );
AOI221X1TS U1372 ( .A0(intDX_EWSW[30]), .A1(n1695), .B0(intDX_EWSW[29]),
.B1(n1660), .C0(n1101), .Y(n1103) );
NOR2X4TS U1373 ( .A(n1454), .B(n1378), .Y(n1626) );
OAI2BB1X2TS U1374 ( .A0N(n1085), .A1N(n1084), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1378) );
NAND3X2TS U1375 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1681), .Y(n1578) );
NAND2X4TS U1376 ( .A(n956), .B(n987), .Y(n1421) );
AOI222X1TS U1377 ( .A0(n1607), .A1(n981), .B0(n1646), .B1(Data_array_SWR[7]),
.C0(n1606), .C1(n1542), .Y(n1605) );
AOI222X1TS U1378 ( .A0(n1607), .A1(left_right_SHT2), .B0(Data_array_SWR[7]),
.B1(n1620), .C0(n1606), .C1(n1618), .Y(n1632) );
AOI222X1TS U1379 ( .A0(n1616), .A1(n958), .B0(n1646), .B1(Data_array_SWR[6]),
.C0(n1615), .C1(n1542), .Y(n1614) );
AOI222X1TS U1380 ( .A0(n1616), .A1(n982), .B0(Data_array_SWR[6]), .B1(n1620),
.C0(n1615), .C1(n1618), .Y(n1634) );
AOI222X1TS U1381 ( .A0(n1610), .A1(n981), .B0(n1646), .B1(Data_array_SWR[5]),
.C0(n1609), .C1(n1542), .Y(n1608) );
AOI222X1TS U1382 ( .A0(n1610), .A1(left_right_SHT2), .B0(Data_array_SWR[5]),
.B1(n1620), .C0(n1609), .C1(n1618), .Y(n1635) );
AOI222X1TS U1383 ( .A0(n1613), .A1(n958), .B0(n1646), .B1(Data_array_SWR[4]),
.C0(n1612), .C1(n1542), .Y(n1611) );
AOI222X1TS U1384 ( .A0(n1613), .A1(n982), .B0(Data_array_SWR[4]), .B1(n1620),
.C0(n1612), .C1(n1618), .Y(n1636) );
INVX4TS U1385 ( .A(n1575), .Y(n1598) );
NOR2BX1TS U1386 ( .AN(n1050), .B(Raw_mant_NRM_SWR[18]), .Y(n1358) );
AOI222X4TS U1387 ( .A0(Data_array_SWR[20]), .A1(n1461), .B0(
Data_array_SWR[24]), .B1(n1469), .C0(Data_array_SWR[16]), .C1(n1086),
.Y(n1554) );
AOI222X4TS U1388 ( .A0(Data_array_SWR[20]), .A1(n1512), .B0(
Data_array_SWR[24]), .B1(n1486), .C0(Data_array_SWR[16]), .C1(n1511),
.Y(n1541) );
NOR2X2TS U1389 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1699), .Y(n1381) );
OAI21X2TS U1390 ( .A0(intDX_EWSW[18]), .A1(n1727), .B0(n1142), .Y(n1209) );
AOI32X1TS U1391 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1042), .A2(n1041), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1042), .Y(n1043) );
NOR3X1TS U1392 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1367) );
NOR2XLTS U1393 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n1267)
);
OAI21XLTS U1394 ( .A0(intDX_EWSW[1]), .A1(n1011), .B0(intDX_EWSW[0]), .Y(
n1107) );
OAI211XLTS U1395 ( .A0(n1316), .A1(n1012), .B0(n1300), .C0(n1299), .Y(n865)
);
OAI211XLTS U1396 ( .A0(intDX_EWSW[8]), .A1(n1724), .B0(n1121), .C0(n1124),
.Y(n1135) );
OAI21XLTS U1397 ( .A0(intDX_EWSW[21]), .A1(n1707), .B0(intDX_EWSW[20]), .Y(
n1139) );
OAI21XLTS U1398 ( .A0(intDX_EWSW[13]), .A1(n1706), .B0(intDX_EWSW[12]), .Y(
n1118) );
OAI21XLTS U1399 ( .A0(intDX_EWSW[23]), .A1(n1010), .B0(intDX_EWSW[22]), .Y(
n1146) );
OAI21XLTS U1400 ( .A0(intDX_EWSW[3]), .A1(n1703), .B0(intDX_EWSW[2]), .Y(
n1110) );
OAI211XLTS U1401 ( .A0(n1703), .A1(intDX_EWSW[3]), .B0(n1109), .C0(n1108),
.Y(n1112) );
INVX2TS U1402 ( .A(n1748), .Y(n1016) );
AOI22X1TS U1403 ( .A0(n1383), .A1(n1598), .B0(n1384), .B1(n1005), .Y(n1023)
);
NOR2XLTS U1404 ( .A(n1696), .B(intDX_EWSW[11]), .Y(n1119) );
OAI21XLTS U1405 ( .A0(intDX_EWSW[15]), .A1(n1722), .B0(intDX_EWSW[14]), .Y(
n1127) );
NOR2XLTS U1406 ( .A(n1140), .B(intDY_EWSW[16]), .Y(n1141) );
NOR2XLTS U1407 ( .A(n1374), .B(exp_rslt_NRM2_EW1[1]), .Y(n1071) );
NOR2XLTS U1408 ( .A(n1072), .B(n1375), .Y(n1073) );
NOR2X1TS U1409 ( .A(Raw_mant_NRM_SWR[10]), .B(n1037), .Y(n1055) );
NAND2X1TS U1410 ( .A(n1270), .B(n1659), .Y(n1368) );
OAI21XLTS U1411 ( .A0(n1659), .A1(n1411), .B0(n1338), .Y(n1339) );
OR2X1TS U1412 ( .A(n1076), .B(n1078), .Y(n1077) );
OAI21XLTS U1413 ( .A0(DmP_EXP_EWSW[25]), .A1(n1736), .B0(n1432), .Y(n1429)
);
AOI31XLTS U1414 ( .A0(n1789), .A1(Shift_amount_SHT1_EWR[4]), .A2(n956), .B0(
n1356), .Y(n1274) );
OAI21XLTS U1415 ( .A0(n1724), .A1(n1255), .B0(n1191), .Y(n826) );
OAI211XLTS U1416 ( .A0(n1333), .A1(n990), .B0(n1293), .C0(n1292), .Y(n854)
);
NOR2XLTS U1417 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1035) );
AOI32X4TS U1418 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1035), .B1(n1699), .Y(n1384)
);
INVX2TS U1419 ( .A(n1384), .Y(n1383) );
BUFX3TS U1420 ( .A(n1786), .Y(n1575) );
INVX2TS U1421 ( .A(n1575), .Y(n1563) );
NAND4X1TS U1422 ( .A(n1677), .B(n1651), .C(n1650), .D(n1655), .Y(n1366) );
NOR2BX2TS U1423 ( .AN(n1367), .B(n1366), .Y(n1050) );
NOR3X1TS U1424 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1359) );
NAND2X1TS U1425 ( .A(Raw_mant_NRM_SWR[14]), .B(n1357), .Y(n1048) );
NOR2X2TS U1426 ( .A(Raw_mant_NRM_SWR[13]), .B(n1036), .Y(n1053) );
NOR3X1TS U1427 ( .A(Raw_mant_NRM_SWR[12]), .B(n1032), .C(n1037), .Y(n1364)
);
NOR3X2TS U1428 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1265),
.Y(n1270) );
OAI21X1TS U1429 ( .A0(n1040), .A1(n1368), .B0(n1039), .Y(n1269) );
NOR2X1TS U1430 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1042) );
AOI211X1TS U1431 ( .A0(n1044), .A1(n1043), .B0(Raw_mant_NRM_SWR[24]), .C0(
Raw_mant_NRM_SWR[25]), .Y(n1045) );
AOI32X1TS U1432 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1650), .A2(n1685), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1650), .Y(n1047) );
AOI32X1TS U1433 ( .A0(n1651), .A1(n1048), .A2(n1047), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1048), .Y(n1049) );
NOR3X1TS U1434 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .C(n1368),
.Y(n1271) );
NAND2X1TS U1435 ( .A(n1271), .B(Raw_mant_NRM_SWR[0]), .Y(n1272) );
AOI21X1TS U1436 ( .A0(n1270), .A1(n1052), .B0(n1051), .Y(n1054) );
NAND2X1TS U1437 ( .A(Raw_mant_NRM_SWR[12]), .B(n1053), .Y(n1362) );
OAI211X1TS U1438 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1272), .B0(n1054), .C0(
n1362), .Y(n1371) );
NAND2X2TS U1439 ( .A(n1280), .B(n978), .Y(n1411) );
INVX2TS U1440 ( .A(n1411), .Y(n1399) );
NAND2X1TS U1441 ( .A(n1058), .B(n1399), .Y(n1341) );
INVX4TS U1442 ( .A(n1341), .Y(n1336) );
AOI22X1TS U1443 ( .A0(n955), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1336), .Y(n1063) );
OR2X2TS U1444 ( .A(n956), .B(n1280), .Y(n1401) );
AOI21X1TS U1445 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n956), .B0(n1373), .Y(
n1276) );
NOR2BX1TS U1446 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1275) );
BUFX3TS U1447 ( .A(n1275), .Y(n1409) );
AOI22X1TS U1448 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1399), .B0(n1409), .B1(
n1007), .Y(n1061) );
AOI22X1TS U1449 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1413), .B0(n984), .B1(
n1008), .Y(n1060) );
NAND2X1TS U1450 ( .A(n1061), .B(n1060), .Y(n1291) );
AOI22X1TS U1451 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1413), .B0(n1330), .B1(
n1291), .Y(n1062) );
NAND2X1TS U1452 ( .A(n1063), .B(n1062), .Y(n852) );
CLKBUFX2TS U1453 ( .A(n989), .Y(n1064) );
BUFX3TS U1454 ( .A(n1066), .Y(n1768) );
BUFX3TS U1455 ( .A(n1065), .Y(n1769) );
BUFX3TS U1456 ( .A(n1066), .Y(n1770) );
BUFX3TS U1457 ( .A(n1065), .Y(n1771) );
BUFX3TS U1458 ( .A(n1066), .Y(n1772) );
BUFX3TS U1459 ( .A(n1065), .Y(n1773) );
BUFX3TS U1460 ( .A(n1066), .Y(n1761) );
BUFX3TS U1461 ( .A(n988), .Y(n1763) );
BUFX3TS U1462 ( .A(n988), .Y(n1765) );
BUFX3TS U1463 ( .A(n988), .Y(n1766) );
BUFX3TS U1464 ( .A(n989), .Y(n1767) );
BUFX3TS U1465 ( .A(n1065), .Y(n1781) );
BUFX3TS U1466 ( .A(n989), .Y(n1762) );
BUFX3TS U1467 ( .A(n1066), .Y(n1756) );
BUFX3TS U1468 ( .A(n1065), .Y(n1757) );
BUFX3TS U1469 ( .A(n1066), .Y(n1775) );
BUFX3TS U1470 ( .A(n1066), .Y(n1784) );
BUFX3TS U1471 ( .A(n989), .Y(n1764) );
BUFX3TS U1472 ( .A(n1065), .Y(n1780) );
BUFX3TS U1473 ( .A(n1065), .Y(n1758) );
BUFX3TS U1474 ( .A(n1066), .Y(n1782) );
BUFX3TS U1475 ( .A(n1065), .Y(n1783) );
AO22XLTS U1476 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n1420),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n625) );
AO22XLTS U1477 ( .A0(n978), .A1(ZERO_FLAG_NRM), .B0(n956), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n634) );
INVX4TS U1478 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1625) );
AO22XLTS U1479 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1625), .B1(zero_flag), .Y(n633) );
BUFX3TS U1480 ( .A(n1575), .Y(n1596) );
CLKBUFX2TS U1481 ( .A(n1656), .Y(n1543) );
BUFX3TS U1482 ( .A(n1543), .Y(n1492) );
AOI2BB2X1TS U1483 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n1491), .A0N(n1491), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n1092) );
CLKAND2X2TS U1484 ( .A(n1092), .B(DMP_SFG[0]), .Y(n1497) );
AOI2BB2X1TS U1485 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n1491), .A0N(n1491), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1502) );
AO22XLTS U1486 ( .A0(n1596), .A1(Raw_mant_NRM_SWR[3]), .B0(n1785), .B1(n1067), .Y(n599) );
INVX2TS U1487 ( .A(DP_OP_15J9_123_2691_n4), .Y(n1068) );
NAND2X1TS U1488 ( .A(n1717), .B(n1068), .Y(n1074) );
INVX2TS U1489 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1070) );
INVX2TS U1490 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1069) );
INVX2TS U1491 ( .A(n1074), .Y(n1075) );
NAND2X1TS U1492 ( .A(n1716), .B(n1075), .Y(n1082) );
XNOR2X1TS U1493 ( .A(DMP_exp_NRM2_EW[7]), .B(n1082), .Y(n1078) );
NAND2X2TS U1494 ( .A(n1077), .B(Shift_reg_FLAGS_7[0]), .Y(n1377) );
OA22X1TS U1495 ( .A0(n1377), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n839) );
OA22X1TS U1496 ( .A0(n1377), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n838) );
OA22X1TS U1497 ( .A0(n1377), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n840) );
OA22X1TS U1498 ( .A0(n1377), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n841) );
INVX4TS U1499 ( .A(n1446), .Y(busy) );
INVX2TS U1500 ( .A(n1077), .Y(n1454) );
INVX2TS U1501 ( .A(n1078), .Y(n1350) );
AND4X1TS U1502 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1374), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1079) );
INVX2TS U1503 ( .A(n1082), .Y(n1083) );
NOR2X2TS U1504 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1511) );
INVX2TS U1505 ( .A(n1511), .Y(n1474) );
NAND2X2TS U1506 ( .A(n1681), .B(n1486), .Y(n1579) );
OAI22X1TS U1507 ( .A0(n1672), .A1(n1578), .B0(n1735), .B1(n1579), .Y(n1088)
);
NOR2X2TS U1508 ( .A(shift_value_SHT2_EWR[3]), .B(n1687), .Y(n1512) );
INVX2TS U1509 ( .A(n1512), .Y(n1089) );
AO22XLTS U1510 ( .A0(n1615), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[7]), .B1(n1086), .Y(n1087) );
AOI211X1TS U1511 ( .A0(Data_array_SWR[3]), .A1(n1487), .B0(n1088), .C0(n1087), .Y(n1622) );
NAND2X2TS U1512 ( .A(n982), .B(n1487), .Y(n1582) );
OAI22X1TS U1513 ( .A0(n982), .A1(n1622), .B0(n1653), .B1(n1582), .Y(n1495)
);
OAI22X1TS U1514 ( .A0(n1671), .A1(n1578), .B0(n1734), .B1(n1579), .Y(n1091)
);
AO22XLTS U1515 ( .A0(n1606), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[6]), .B1(n1086), .Y(n1090) );
OAI22X1TS U1516 ( .A0(left_right_SHT2), .A1(n1624), .B0(n1667), .B1(n1582),
.Y(n1494) );
OAI21XLTS U1517 ( .A0(n1014), .A1(n981), .B0(n956), .Y(n910) );
NOR2XLTS U1518 ( .A(n1092), .B(DMP_SFG[0]), .Y(n1093) );
OAI32X1TS U1519 ( .A0(n1575), .A1(n1497), .A2(n1093), .B0(n1598), .B1(n1686),
.Y(n600) );
AOI2BB2XLTS U1520 ( .B0(beg_OP), .B1(n1661), .A0N(n1661), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1094) );
NOR2X1TS U1521 ( .A(n1721), .B(intDX_EWSW[25]), .Y(n1153) );
AOI22X1TS U1522 ( .A0(intDX_EWSW[25]), .A1(n1721), .B0(intDX_EWSW[24]), .B1(
n1095), .Y(n1099) );
OAI21X1TS U1523 ( .A0(intDX_EWSW[26]), .A1(n1720), .B0(n1096), .Y(n1154) );
NOR2X1TS U1524 ( .A(n1695), .B(intDX_EWSW[30]), .Y(n1102) );
NOR2X1TS U1525 ( .A(n1660), .B(intDX_EWSW[29]), .Y(n1100) );
AOI211X1TS U1526 ( .A0(intDY_EWSW[28]), .A1(n1726), .B0(n1102), .C0(n1100),
.Y(n1152) );
NOR3X1TS U1527 ( .A(n1726), .B(n1100), .C(intDY_EWSW[28]), .Y(n1101) );
AOI2BB2X1TS U1528 ( .B0(n1104), .B1(n1152), .A0N(n1103), .A1N(n1102), .Y(
n1158) );
NOR2X1TS U1529 ( .A(n1723), .B(intDX_EWSW[17]), .Y(n1140) );
INVX2TS U1530 ( .A(intDY_EWSW[11]), .Y(n1251) );
OAI22X1TS U1531 ( .A0(n964), .A1(intDX_EWSW[10]), .B0(n1251), .B1(
intDX_EWSW[11]), .Y(n1217) );
INVX2TS U1532 ( .A(n1217), .Y(n1124) );
OAI2BB1X1TS U1533 ( .A0N(n1683), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1105) );
OAI22X1TS U1534 ( .A0(intDY_EWSW[4]), .A1(n1105), .B0(n1683), .B1(
intDY_EWSW[5]), .Y(n1116) );
OAI2BB1X1TS U1535 ( .A0N(n1658), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1106) );
OAI22X1TS U1536 ( .A0(intDY_EWSW[6]), .A1(n1106), .B0(n1658), .B1(
intDY_EWSW[7]), .Y(n1115) );
AOI222X1TS U1537 ( .A0(intDY_EWSW[4]), .A1(n1657), .B0(n1112), .B1(n1111),
.C0(intDY_EWSW[5]), .C1(n1683), .Y(n1114) );
AOI22X1TS U1538 ( .A0(intDY_EWSW[7]), .A1(n1658), .B0(intDY_EWSW[6]), .B1(
n1684), .Y(n1113) );
OAI32X1TS U1539 ( .A0(n1116), .A1(n1115), .A2(n1114), .B0(n1113), .B1(n1115),
.Y(n1134) );
OA22X1TS U1540 ( .A0(n1663), .A1(intDX_EWSW[14]), .B0(n1722), .B1(
intDX_EWSW[15]), .Y(n1131) );
OAI2BB2XLTS U1541 ( .B0(intDY_EWSW[12]), .B1(n1118), .A0N(intDX_EWSW[13]),
.A1N(n1706), .Y(n1130) );
AOI22X1TS U1542 ( .A0(intDX_EWSW[11]), .A1(n1696), .B0(intDX_EWSW[10]), .B1(
n1120), .Y(n1126) );
AOI21X1TS U1543 ( .A0(n1123), .A1(n1122), .B0(n1133), .Y(n1125) );
OAI2BB2XLTS U1544 ( .B0(n1126), .B1(n1133), .A0N(n1125), .A1N(n1124), .Y(
n1129) );
OAI2BB2XLTS U1545 ( .B0(intDY_EWSW[14]), .B1(n1127), .A0N(intDX_EWSW[15]),
.A1N(n1722), .Y(n1128) );
AOI211X1TS U1546 ( .A0(n1131), .A1(n1130), .B0(n1129), .C0(n1128), .Y(n1132)
);
OAI31X1TS U1547 ( .A0(n1135), .A1(n1134), .A2(n1133), .B0(n1132), .Y(n1138)
);
OA22X1TS U1548 ( .A0(n1664), .A1(intDX_EWSW[22]), .B0(n1010), .B1(
intDX_EWSW[23]), .Y(n1150) );
AOI211X1TS U1549 ( .A0(intDY_EWSW[16]), .A1(n1692), .B0(n1145), .C0(n1209),
.Y(n1137) );
OAI2BB2XLTS U1550 ( .B0(intDY_EWSW[20]), .B1(n1139), .A0N(intDX_EWSW[21]),
.A1N(n1707), .Y(n1149) );
AOI22X1TS U1551 ( .A0(intDX_EWSW[17]), .A1(n1723), .B0(intDX_EWSW[16]), .B1(
n1141), .Y(n1144) );
OAI32X1TS U1552 ( .A0(n1209), .A1(n1145), .A2(n1144), .B0(n1143), .B1(n1145),
.Y(n1148) );
AOI211X1TS U1553 ( .A0(n1150), .A1(n1149), .B0(n1148), .C0(n1147), .Y(n1156)
);
NAND4BBX1TS U1554 ( .AN(n1154), .BN(n1153), .C(n1152), .D(n1151), .Y(n1155)
);
AOI32X1TS U1555 ( .A0(n1158), .A1(n1157), .A2(n1156), .B0(n1155), .B1(n1158),
.Y(n1159) );
AND2X2TS U1556 ( .A(Shift_reg_FLAGS_7_6), .B(n1159), .Y(n1199) );
INVX2TS U1557 ( .A(Shift_reg_FLAGS_7_6), .Y(n1161) );
BUFX3TS U1558 ( .A(n1261), .Y(n1237) );
AOI22X1TS U1559 ( .A0(intDX_EWSW[14]), .A1(n1160), .B0(DmP_EXP_EWSW[14]),
.B1(n1237), .Y(n1162) );
BUFX3TS U1560 ( .A(n1161), .Y(n1249) );
AOI22X1TS U1561 ( .A0(intDY_EWSW[28]), .A1(n1160), .B0(DMP_EXP_EWSW[28]),
.B1(n1249), .Y(n1163) );
BUFX3TS U1562 ( .A(n1261), .Y(n1382) );
AOI22X1TS U1563 ( .A0(intDX_EWSW[22]), .A1(n1160), .B0(DmP_EXP_EWSW[22]),
.B1(n1382), .Y(n1164) );
AOI22X1TS U1564 ( .A0(intDX_EWSW[19]), .A1(n1160), .B0(DmP_EXP_EWSW[19]),
.B1(n1382), .Y(n1165) );
INVX2TS U1565 ( .A(n1199), .Y(n1236) );
AOI22X1TS U1566 ( .A0(intDY_EWSW[30]), .A1(n954), .B0(DMP_EXP_EWSW[30]),
.B1(n1249), .Y(n1166) );
AOI22X1TS U1567 ( .A0(intDY_EWSW[29]), .A1(n954), .B0(DMP_EXP_EWSW[29]),
.B1(n1249), .Y(n1167) );
AOI22X1TS U1568 ( .A0(intDX_EWSW[16]), .A1(n954), .B0(DmP_EXP_EWSW[16]),
.B1(n1382), .Y(n1168) );
AOI22X1TS U1569 ( .A0(intDX_EWSW[17]), .A1(n954), .B0(DmP_EXP_EWSW[17]),
.B1(n1382), .Y(n1169) );
AOI22X1TS U1570 ( .A0(intDX_EWSW[13]), .A1(n954), .B0(DmP_EXP_EWSW[13]),
.B1(n1382), .Y(n1170) );
AOI22X1TS U1571 ( .A0(intDX_EWSW[21]), .A1(n954), .B0(DmP_EXP_EWSW[21]),
.B1(n1382), .Y(n1171) );
AOI22X1TS U1572 ( .A0(intDX_EWSW[20]), .A1(n954), .B0(DmP_EXP_EWSW[20]),
.B1(n1382), .Y(n1172) );
AOI22X1TS U1573 ( .A0(intDX_EWSW[7]), .A1(n1187), .B0(DmP_EXP_EWSW[7]), .B1(
n1237), .Y(n1173) );
AOI22X1TS U1574 ( .A0(intDX_EWSW[6]), .A1(n1187), .B0(DmP_EXP_EWSW[6]), .B1(
n1237), .Y(n1174) );
AOI22X1TS U1575 ( .A0(intDX_EWSW[5]), .A1(n1187), .B0(DmP_EXP_EWSW[5]), .B1(
n1237), .Y(n1175) );
AOI22X1TS U1576 ( .A0(intDX_EWSW[4]), .A1(n1187), .B0(DmP_EXP_EWSW[4]), .B1(
n1237), .Y(n1176) );
AOI22X1TS U1577 ( .A0(intDX_EWSW[18]), .A1(n1187), .B0(DmP_EXP_EWSW[18]),
.B1(n1382), .Y(n1177) );
AOI22X1TS U1578 ( .A0(intDX_EWSW[1]), .A1(n1187), .B0(DmP_EXP_EWSW[1]), .B1(
n1237), .Y(n1178) );
AOI22X1TS U1579 ( .A0(intDX_EWSW[0]), .A1(n1187), .B0(DmP_EXP_EWSW[0]), .B1(
n1249), .Y(n1179) );
AOI22X1TS U1580 ( .A0(intDX_EWSW[12]), .A1(n1187), .B0(DmP_EXP_EWSW[12]),
.B1(n1237), .Y(n1180) );
AOI22X1TS U1581 ( .A0(intDX_EWSW[8]), .A1(n1187), .B0(DmP_EXP_EWSW[8]), .B1(
n1237), .Y(n1181) );
AOI22X1TS U1582 ( .A0(intDX_EWSW[10]), .A1(n1187), .B0(DmP_EXP_EWSW[10]),
.B1(n1249), .Y(n1182) );
AOI22X1TS U1583 ( .A0(intDX_EWSW[9]), .A1(n1187), .B0(DmP_EXP_EWSW[9]), .B1(
n1237), .Y(n1183) );
AOI22X1TS U1584 ( .A0(intDX_EWSW[2]), .A1(n1187), .B0(DmP_EXP_EWSW[2]), .B1(
n1237), .Y(n1184) );
AOI22X1TS U1585 ( .A0(intDX_EWSW[11]), .A1(n1187), .B0(DmP_EXP_EWSW[11]),
.B1(n1237), .Y(n1185) );
AOI22X1TS U1586 ( .A0(intDX_EWSW[3]), .A1(n1187), .B0(DmP_EXP_EWSW[3]), .B1(
n1237), .Y(n1186) );
AOI22X1TS U1587 ( .A0(DmP_EXP_EWSW[27]), .A1(n1382), .B0(intDX_EWSW[27]),
.B1(n1187), .Y(n1188) );
AOI22X1TS U1588 ( .A0(intDX_EWSW[15]), .A1(n1160), .B0(DmP_EXP_EWSW[15]),
.B1(n1382), .Y(n1189) );
BUFX3TS U1589 ( .A(n1199), .Y(n1262) );
AOI22X1TS U1590 ( .A0(intDX_EWSW[8]), .A1(n1262), .B0(DMP_EXP_EWSW[8]), .B1(
n1261), .Y(n1191) );
AOI22X1TS U1591 ( .A0(intDX_EWSW[21]), .A1(n1262), .B0(DMP_EXP_EWSW[21]),
.B1(n1249), .Y(n1192) );
AOI22X1TS U1592 ( .A0(intDX_EWSW[7]), .A1(n1262), .B0(DMP_EXP_EWSW[7]), .B1(
n1261), .Y(n1193) );
AOI22X1TS U1593 ( .A0(intDX_EWSW[9]), .A1(n1262), .B0(DMP_EXP_EWSW[9]), .B1(
n1261), .Y(n1194) );
BUFX3TS U1594 ( .A(n1262), .Y(n1253) );
AOI22X1TS U1595 ( .A0(intDX_EWSW[16]), .A1(n1253), .B0(DMP_EXP_EWSW[16]),
.B1(n1249), .Y(n1195) );
AOI22X1TS U1596 ( .A0(n1009), .A1(n1382), .B0(intDX_EWSW[27]), .B1(n1199),
.Y(n1196) );
AOI22X1TS U1597 ( .A0(intDX_EWSW[0]), .A1(n1262), .B0(DMP_EXP_EWSW[0]), .B1(
n1161), .Y(n1197) );
AOI22X1TS U1598 ( .A0(intDX_EWSW[20]), .A1(n1199), .B0(DMP_EXP_EWSW[20]),
.B1(n1249), .Y(n1198) );
AOI22X1TS U1599 ( .A0(DMP_EXP_EWSW[23]), .A1(n1382), .B0(intDX_EWSW[23]),
.B1(n1199), .Y(n1200) );
OAI22X1TS U1600 ( .A0(n1721), .A1(intDX_EWSW[25]), .B0(n1720), .B1(
intDX_EWSW[26]), .Y(n1201) );
AOI221X1TS U1601 ( .A0(n1721), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1720), .C0(n1201), .Y(n1207) );
OAI22X1TS U1602 ( .A0(n1713), .A1(intDX_EWSW[27]), .B0(n1726), .B1(
intDY_EWSW[28]), .Y(n1202) );
OAI22X1TS U1603 ( .A0(n1715), .A1(intDY_EWSW[29]), .B0(n1665), .B1(
intDY_EWSW[30]), .Y(n1203) );
AOI221X1TS U1604 ( .A0(n1715), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1665), .C0(n1203), .Y(n1205) );
AOI2BB2XLTS U1605 ( .B0(intDX_EWSW[7]), .B1(n1714), .A0N(n1714), .A1N(
intDX_EWSW[7]), .Y(n1204) );
NAND4XLTS U1606 ( .A(n1207), .B(n1206), .C(n1205), .D(n1204), .Y(n1235) );
OAI22X1TS U1607 ( .A0(n1011), .A1(intDX_EWSW[1]), .B0(n1723), .B1(
intDX_EWSW[17]), .Y(n1208) );
OAI22X1TS U1608 ( .A0(n996), .A1(intDX_EWSW[20]), .B0(n1707), .B1(
intDX_EWSW[21]), .Y(n1210) );
OAI22X1TS U1609 ( .A0(n1664), .A1(intDX_EWSW[22]), .B0(n1010), .B1(
intDX_EWSW[23]), .Y(n1211) );
NAND4XLTS U1610 ( .A(n1215), .B(n1214), .C(n1213), .D(n1212), .Y(n1234) );
OAI22X1TS U1611 ( .A0(n1652), .A1(intDX_EWSW[24]), .B0(n1705), .B1(
intDX_EWSW[9]), .Y(n1216) );
AOI221X1TS U1612 ( .A0(n1652), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1705), .C0(n1216), .Y(n1223) );
OAI22X1TS U1613 ( .A0(n1710), .A1(intDX_EWSW[12]), .B0(n1706), .B1(
intDX_EWSW[13]), .Y(n1218) );
OAI22X1TS U1614 ( .A0(n1663), .A1(intDX_EWSW[14]), .B0(n1722), .B1(
intDX_EWSW[15]), .Y(n1219) );
NAND4XLTS U1615 ( .A(n1223), .B(n1222), .C(n1221), .D(n1220), .Y(n1233) );
OAI22X1TS U1616 ( .A0(n1711), .A1(intDX_EWSW[16]), .B0(n967), .B1(
intDX_EWSW[0]), .Y(n1224) );
AOI221X1TS U1617 ( .A0(n1711), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n967), .C0(n1224), .Y(n1231) );
OAI22X1TS U1618 ( .A0(n1708), .A1(intDX_EWSW[2]), .B0(n1703), .B1(
intDX_EWSW[3]), .Y(n1225) );
OAI22X1TS U1619 ( .A0(n1709), .A1(intDX_EWSW[4]), .B0(n1662), .B1(
intDX_EWSW[5]), .Y(n1226) );
AOI221X1TS U1620 ( .A0(n1709), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1662), .C0(n1226), .Y(n1229) );
OAI22X1TS U1621 ( .A0(n1724), .A1(intDX_EWSW[8]), .B0(n1704), .B1(
intDX_EWSW[6]), .Y(n1227) );
AOI221X1TS U1622 ( .A0(n1724), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1704), .C0(n1227), .Y(n1228) );
NAND4XLTS U1623 ( .A(n1231), .B(n1230), .C(n1229), .D(n1228), .Y(n1232) );
NOR4X1TS U1624 ( .A(n1235), .B(n1234), .C(n1233), .D(n1232), .Y(n1443) );
CLKXOR2X2TS U1625 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1441) );
INVX2TS U1626 ( .A(n1441), .Y(n1240) );
AOI22X1TS U1627 ( .A0(intDX_EWSW[31]), .A1(n1238), .B0(SIGN_FLAG_EXP), .B1(
n1237), .Y(n1239) );
AOI22X1TS U1628 ( .A0(intDX_EWSW[19]), .A1(n1253), .B0(DMP_EXP_EWSW[19]),
.B1(n1249), .Y(n1241) );
AOI22X1TS U1629 ( .A0(intDX_EWSW[18]), .A1(n1253), .B0(DMP_EXP_EWSW[18]),
.B1(n1249), .Y(n1242) );
AOI22X1TS U1630 ( .A0(intDX_EWSW[10]), .A1(n1253), .B0(DMP_EXP_EWSW[10]),
.B1(n1261), .Y(n1243) );
AOI222X1TS U1631 ( .A0(n954), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1161), .C0(intDY_EWSW[23]), .C1(n1253), .Y(n1244) );
INVX2TS U1632 ( .A(n1244), .Y(n645) );
AOI22X1TS U1633 ( .A0(intDX_EWSW[22]), .A1(n1253), .B0(DMP_EXP_EWSW[22]),
.B1(n1249), .Y(n1245) );
AOI22X1TS U1634 ( .A0(intDX_EWSW[14]), .A1(n1253), .B0(DMP_EXP_EWSW[14]),
.B1(n1261), .Y(n1246) );
AOI22X1TS U1635 ( .A0(intDX_EWSW[17]), .A1(n1253), .B0(DMP_EXP_EWSW[17]),
.B1(n1249), .Y(n1247) );
AOI22X1TS U1636 ( .A0(intDX_EWSW[12]), .A1(n1253), .B0(DMP_EXP_EWSW[12]),
.B1(n1261), .Y(n1248) );
AOI22X1TS U1637 ( .A0(intDX_EWSW[11]), .A1(n1253), .B0(DMP_EXP_EWSW[11]),
.B1(n1249), .Y(n1250) );
AOI22X1TS U1638 ( .A0(intDX_EWSW[13]), .A1(n1253), .B0(DMP_EXP_EWSW[13]),
.B1(n1261), .Y(n1252) );
AOI22X1TS U1639 ( .A0(intDX_EWSW[15]), .A1(n1253), .B0(DMP_EXP_EWSW[15]),
.B1(n1261), .Y(n1254) );
INVX2TS U1640 ( .A(n954), .Y(n1264) );
AOI22X1TS U1641 ( .A0(intDX_EWSW[1]), .A1(n1262), .B0(DMP_EXP_EWSW[1]), .B1(
n1161), .Y(n1256) );
AOI22X1TS U1642 ( .A0(intDX_EWSW[3]), .A1(n1262), .B0(DMP_EXP_EWSW[3]), .B1(
n1261), .Y(n1257) );
AOI22X1TS U1643 ( .A0(intDX_EWSW[2]), .A1(n1262), .B0(DMP_EXP_EWSW[2]), .B1(
n1261), .Y(n1258) );
AOI22X1TS U1644 ( .A0(intDX_EWSW[6]), .A1(n1262), .B0(DMP_EXP_EWSW[6]), .B1(
n1261), .Y(n1259) );
AOI22X1TS U1645 ( .A0(intDX_EWSW[4]), .A1(n1262), .B0(DMP_EXP_EWSW[4]), .B1(
n1261), .Y(n1260) );
AOI22X1TS U1646 ( .A0(intDX_EWSW[5]), .A1(n1262), .B0(DMP_EXP_EWSW[5]), .B1(
n1261), .Y(n1263) );
AOI211X1TS U1647 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1270), .B0(n1269), .C0(
n1268), .Y(n1273) );
NAND2X1TS U1648 ( .A(Raw_mant_NRM_SWR[1]), .B(n1271), .Y(n1361) );
AOI31X1TS U1649 ( .A0(n1273), .A1(n1272), .A2(n1361), .B0(n956), .Y(n1356)
);
BUFX3TS U1650 ( .A(n1275), .Y(n1340) );
AOI22X1TS U1651 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1399), .B0(n1409), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1279) );
AOI22X1TS U1652 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1413), .B0(n984), .B1(
n1007), .Y(n1278) );
NAND2X1TS U1653 ( .A(n1279), .B(n1278), .Y(n1309) );
AOI22X1TS U1654 ( .A0(n1419), .A1(Data_array_SWR[3]), .B0(n1277), .B1(n1309),
.Y(n1282) );
NAND2X1TS U1655 ( .A(n1373), .B(n1280), .Y(n1346) );
NAND2X1TS U1656 ( .A(Raw_mant_NRM_SWR[19]), .B(n1324), .Y(n1281) );
AOI22X1TS U1657 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1399), .B0(n1409), .B1(
n1003), .Y(n1284) );
AOI22X1TS U1658 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1413), .B0(n984), .B1(
n1006), .Y(n1283) );
NAND2X1TS U1659 ( .A(n1284), .B(n1283), .Y(n1320) );
AOI22X1TS U1660 ( .A0(n955), .A1(Data_array_SWR[7]), .B0(n1277), .B1(n1320),
.Y(n1286) );
NAND2X1TS U1661 ( .A(Raw_mant_NRM_SWR[15]), .B(n1324), .Y(n1285) );
AOI22X1TS U1662 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1399), .B0(n1409), .B1(
n1006), .Y(n1288) );
AOI22X1TS U1663 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1413), .B0(n984), .B1(n999), .Y(n1287) );
NAND2X1TS U1664 ( .A(n1288), .B(n1287), .Y(n1329) );
AOI22X1TS U1665 ( .A0(n1419), .A1(Data_array_SWR[6]), .B0(n1277), .B1(n1329),
.Y(n1290) );
NAND2X1TS U1666 ( .A(Raw_mant_NRM_SWR[16]), .B(n1324), .Y(n1289) );
AOI22X1TS U1667 ( .A0(n1419), .A1(Data_array_SWR[2]), .B0(n1277), .B1(n1291),
.Y(n1293) );
NAND2X1TS U1668 ( .A(Raw_mant_NRM_SWR[20]), .B(n1324), .Y(n1292) );
AOI22X1TS U1669 ( .A0(n984), .A1(DmP_mant_SHT1_SW[8]), .B0(n1409), .B1(n1002), .Y(n1294) );
AOI21X1TS U1670 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1413), .B0(n1295), .Y(
n1415) );
OAI22X1TS U1671 ( .A0(n1296), .A1(n1012), .B0(n1737), .B1(n1341), .Y(n1297)
);
AOI21X1TS U1672 ( .A0(n1419), .A1(Data_array_SWR[8]), .B0(n1297), .Y(n1298)
);
AOI22X1TS U1673 ( .A0(n955), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1324), .Y(n1300) );
AOI22X1TS U1674 ( .A0(n1419), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1324), .Y(n1302) );
AOI22X1TS U1675 ( .A0(n955), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1324), .Y(n1304) );
AOI22X1TS U1676 ( .A0(n955), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1324), .Y(n1307) );
AOI22X1TS U1677 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1413), .B0(n1409), .B1(
n1008), .Y(n1312) );
AOI22X1TS U1678 ( .A0(n955), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1336), .Y(n1311) );
NAND2X1TS U1679 ( .A(n1330), .B(n1309), .Y(n1310) );
AOI22X1TS U1680 ( .A0(n955), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1324), .Y(n1314) );
AOI22X1TS U1681 ( .A0(n1419), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1324), .Y(n1318) );
AOI22X1TS U1682 ( .A0(n955), .A1(Data_array_SWR[5]), .B0(n1330), .B1(n1320),
.Y(n1322) );
NAND2X1TS U1683 ( .A(Raw_mant_NRM_SWR[19]), .B(n1336), .Y(n1321) );
AOI22X1TS U1684 ( .A0(n1419), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1324), .Y(n1327) );
AOI22X1TS U1685 ( .A0(n1419), .A1(Data_array_SWR[4]), .B0(n1330), .B1(n1329),
.Y(n1332) );
NAND2X1TS U1686 ( .A(Raw_mant_NRM_SWR[20]), .B(n1336), .Y(n1331) );
AOI21X1TS U1687 ( .A0(n1413), .A1(Raw_mant_NRM_SWR[0]), .B0(n985), .Y(n1396)
);
OAI22X1TS U1688 ( .A0(n1334), .A1(n1012), .B0(n1421), .B1(n1667), .Y(n1335)
);
AOI21X1TS U1689 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1336), .B0(n1335), .Y(n1337) );
AOI22X1TS U1690 ( .A0(n984), .A1(DmP_mant_SHT1_SW[18]), .B0(n1409), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1338) );
AOI21X1TS U1691 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1413), .B0(n1339), .Y(n1404) );
OAI22X1TS U1692 ( .A0(n1347), .A1(n1012), .B0(n1690), .B1(n1341), .Y(n1342)
);
AOI21X1TS U1693 ( .A0(n955), .A1(Data_array_SWR[18]), .B0(n1342), .Y(n1343)
);
AOI22X1TS U1694 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1399), .B0(n1409), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1344) );
AOI21X1TS U1695 ( .A0(n985), .A1(DmP_mant_SHT1_SW[14]), .B0(n1345), .Y(n1408) );
OAI22X1TS U1696 ( .A0(n1347), .A1(n990), .B0(n1690), .B1(n1346), .Y(n1348)
);
AOI21X1TS U1697 ( .A0(n1419), .A1(Data_array_SWR[16]), .B0(n1348), .Y(n1349)
);
OAI2BB2XLTS U1698 ( .B0(n1378), .B1(n1350), .A0N(n953), .A1N(
final_result_ieee[30]), .Y(n835) );
OAI2BB2XLTS U1699 ( .B0(n1351), .B1(n1378), .A0N(n953), .A1N(
final_result_ieee[31]), .Y(n624) );
AOI2BB2X1TS U1700 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1491), .A0N(n1491),
.A1N(DmP_mant_SFG_SWR[13]), .Y(n1352) );
AOI2BB2X1TS U1701 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1492), .A0N(n1543),
.A1N(DmP_mant_SFG_SWR[12]), .Y(n1464) );
NAND2BX1TS U1702 ( .AN(n1464), .B(DMP_SFG[10]), .Y(n1572) );
NAND2X1TS U1703 ( .A(n1352), .B(DMP_SFG[11]), .Y(n1559) );
OAI21X1TS U1704 ( .A0(n1560), .A1(n1572), .B0(n1559), .Y(n1353) );
INVX2TS U1705 ( .A(n1354), .Y(n1355) );
NAND2X1TS U1706 ( .A(n1688), .B(n1355), .Y(DP_OP_15J9_123_2691_n8) );
MX2X1TS U1707 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n978),
.Y(n692) );
MX2X1TS U1708 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n983),
.Y(n697) );
MX2X1TS U1709 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n978),
.Y(n702) );
MX2X1TS U1710 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n983),
.Y(n707) );
MX2X1TS U1711 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n978),
.Y(n712) );
MX2X1TS U1712 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n983),
.Y(n717) );
MX2X1TS U1713 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n978),
.Y(n722) );
MX2X1TS U1714 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n983),
.Y(n727) );
OAI211X1TS U1715 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1357), .C0(n1678), .Y(n1365) );
OAI2BB1X1TS U1716 ( .A0N(n1359), .A1N(n1678), .B0(n1358), .Y(n1360) );
OAI21X1TS U1717 ( .A0(n1364), .A1(n1363), .B0(n978), .Y(n1422) );
OAI2BB1X1TS U1718 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n956), .B0(n1422), .Y(
n598) );
OAI21XLTS U1719 ( .A0(n1367), .A1(n1366), .B0(n1365), .Y(n1372) );
OAI22X1TS U1720 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1369), .B0(n1368), .B1(
n1728), .Y(n1370) );
OAI31X1TS U1721 ( .A0(n1372), .A1(n1371), .A2(n1370), .B0(n983), .Y(n1417)
);
OAI2BB1X1TS U1722 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1420), .B0(n1417),
.Y(n607) );
OAI2BB1X1TS U1723 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1420), .B0(n1411),
.Y(n593) );
OA22X1TS U1724 ( .A0(n1377), .A1(n1374), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n842) );
OA22X1TS U1725 ( .A0(n1377), .A1(n1375), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n837) );
OA22X1TS U1726 ( .A0(n1377), .A1(n1376), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n836) );
OA21XLTS U1727 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1378),
.Y(n639) );
INVX2TS U1728 ( .A(n1381), .Y(n1380) );
AOI22X1TS U1729 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1380), .B1(n1661), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1730 ( .A(n1380), .B(n1379), .Y(n952) );
AOI22X1TS U1731 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1381), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1661), .Y(n1385) );
AO22XLTS U1732 ( .A0(n1383), .A1(Shift_reg_FLAGS_7_6), .B0(n1384), .B1(n1385), .Y(n950) );
AOI22X1TS U1733 ( .A0(n1384), .A1(n1382), .B0(n1748), .B1(n1383), .Y(n949)
);
AOI22X1TS U1734 ( .A0(n1384), .A1(n1748), .B0(n987), .B1(n1383), .Y(n948) );
AOI22X1TS U1735 ( .A0(n1384), .A1(n1575), .B0(n956), .B1(n1383), .Y(n945) );
AOI22X1TS U1736 ( .A0(n1384), .A1(n1420), .B0(n953), .B1(n1383), .Y(n944) );
AND2X2TS U1737 ( .A(beg_OP), .B(n1385), .Y(n1386) );
INVX2TS U1738 ( .A(n1390), .Y(n1393) );
INVX2TS U1739 ( .A(n1390), .Y(n1392) );
BUFX3TS U1740 ( .A(n1386), .Y(n1390) );
BUFX3TS U1741 ( .A(n1386), .Y(n1395) );
BUFX3TS U1742 ( .A(n1386), .Y(n1387) );
INVX2TS U1743 ( .A(n1390), .Y(n1394) );
INVX2TS U1744 ( .A(n1390), .Y(n1388) );
INVX2TS U1745 ( .A(n1390), .Y(n1389) );
OAI2BB2XLTS U1746 ( .B0(n1396), .B1(n1013), .A0N(n1419), .A1N(
Data_array_SWR[25]), .Y(n877) );
OAI2BB2XLTS U1747 ( .B0(n1403), .B1(n1013), .A0N(n955), .A1N(
Data_array_SWR[24]), .Y(n876) );
AOI22X1TS U1748 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1399), .B0(n1004), .B1(
n1409), .Y(n1400) );
AOI21X1TS U1749 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n985), .B0(n1402), .Y(n1405) );
OAI222X1TS U1750 ( .A0(n1421), .A1(n1653), .B0(n991), .B1(n1403), .C0(n1013),
.C1(n1405), .Y(n874) );
OAI222X1TS U1751 ( .A0(n1746), .A1(n1421), .B0(n991), .B1(n1405), .C0(n1013),
.C1(n1404), .Y(n872) );
AOI22X1TS U1752 ( .A0(n984), .A1(DmP_mant_SHT1_SW[12]), .B0(n1409), .B1(
n1000), .Y(n1406) );
AOI21X1TS U1753 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1413), .B0(n1407), .Y(
n1414) );
OAI222X1TS U1754 ( .A0(n1671), .A1(n1421), .B0(n991), .B1(n1408), .C0(n1013),
.C1(n1414), .Y(n866) );
AOI22X1TS U1755 ( .A0(n984), .A1(DmP_mant_SHT1_SW[10]), .B0(n1409), .B1(
n1001), .Y(n1410) );
AOI21X1TS U1756 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n1413), .B0(n1412), .Y(
n1416) );
OAI222X1TS U1757 ( .A0(n1742), .A1(n1421), .B0(n991), .B1(n1414), .C0(n1013),
.C1(n1416), .Y(n864) );
OAI222X1TS U1758 ( .A0(n1734), .A1(n1421), .B0(n991), .B1(n1416), .C0(n1013),
.C1(n1415), .Y(n862) );
AOI32X1TS U1759 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1421), .A2(n1420),
.B0(shift_value_SHT2_EWR[2]), .B1(n1419), .Y(n1418) );
NAND2X1TS U1760 ( .A(n1418), .B(n1417), .Y(n851) );
AOI32X1TS U1761 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1421), .A2(n956), .B0(
shift_value_SHT2_EWR[3]), .B1(n955), .Y(n1423) );
NAND2X1TS U1762 ( .A(n1423), .B(n1422), .Y(n850) );
INVX2TS U1763 ( .A(n1748), .Y(n1445) );
AOI21X1TS U1764 ( .A0(DMP_EXP_EWSW[23]), .A1(n1025), .B0(n1428), .Y(n1424)
);
AOI2BB2XLTS U1765 ( .B0(n1445), .B1(n1424), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1445), .Y(n847) );
NOR2X1TS U1766 ( .A(n1668), .B(DMP_EXP_EWSW[24]), .Y(n1427) );
AOI21X1TS U1767 ( .A0(DMP_EXP_EWSW[24]), .A1(n1668), .B0(n1427), .Y(n1425)
);
XNOR2X1TS U1768 ( .A(n1428), .B(n1425), .Y(n1426) );
AO22XLTS U1769 ( .A0(n1445), .A1(n1426), .B0(n1748), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n846) );
OAI22X1TS U1770 ( .A0(n1428), .A1(n1427), .B0(DmP_EXP_EWSW[24]), .B1(n1669),
.Y(n1431) );
NAND2X1TS U1771 ( .A(DmP_EXP_EWSW[25]), .B(n1736), .Y(n1432) );
XNOR2X1TS U1772 ( .A(n1431), .B(n1429), .Y(n1430) );
AO22XLTS U1773 ( .A0(n1445), .A1(n1430), .B0(n1457), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n845) );
AOI22X1TS U1774 ( .A0(DMP_EXP_EWSW[25]), .A1(n1745), .B0(n1432), .B1(n1431),
.Y(n1435) );
NOR2X1TS U1775 ( .A(n1741), .B(DMP_EXP_EWSW[26]), .Y(n1436) );
AOI21X1TS U1776 ( .A0(DMP_EXP_EWSW[26]), .A1(n1741), .B0(n1436), .Y(n1433)
);
XNOR2X1TS U1777 ( .A(n1435), .B(n1433), .Y(n1434) );
AO22XLTS U1778 ( .A0(n1445), .A1(n1434), .B0(n1447), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n844) );
OAI22X1TS U1779 ( .A0(n1436), .A1(n1435), .B0(DmP_EXP_EWSW[26]), .B1(n1744),
.Y(n1438) );
XNOR2X1TS U1780 ( .A(DmP_EXP_EWSW[27]), .B(n1009), .Y(n1437) );
XOR2XLTS U1781 ( .A(n1438), .B(n1437), .Y(n1439) );
AO22XLTS U1782 ( .A0(n1445), .A1(n1439), .B0(n1449), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n843) );
OAI222X1TS U1783 ( .A0(n1451), .A1(n1743), .B0(n1669), .B1(
Shift_reg_FLAGS_7_6), .C0(n1652), .C1(n1453), .Y(n810) );
OAI222X1TS U1784 ( .A0(n1451), .A1(n1674), .B0(n1736), .B1(
Shift_reg_FLAGS_7_6), .C0(n1721), .C1(n1453), .Y(n809) );
OAI222X1TS U1785 ( .A0(n1451), .A1(n1675), .B0(n1744), .B1(
Shift_reg_FLAGS_7_6), .C0(n1720), .C1(n1453), .Y(n808) );
OAI21XLTS U1786 ( .A0(n1441), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1440) );
AOI21X1TS U1787 ( .A0(n1441), .A1(intDX_EWSW[31]), .B0(n1440), .Y(n1442) );
AO21XLTS U1788 ( .A0(OP_FLAG_EXP), .A1(n1161), .B0(n1442), .Y(n803) );
AO22XLTS U1789 ( .A0(n1445), .A1(DMP_EXP_EWSW[0]), .B0(n1450), .B1(
DMP_SHT1_EWSW[0]), .Y(n800) );
AO22XLTS U1790 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1446), .B1(
DMP_SHT2_EWSW[0]), .Y(n799) );
AO22XLTS U1791 ( .A0(n1445), .A1(DMP_EXP_EWSW[1]), .B0(n1457), .B1(
DMP_SHT1_EWSW[1]), .Y(n797) );
AO22XLTS U1792 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n987), .B1(
DMP_SHT2_EWSW[1]), .Y(n796) );
AO22XLTS U1793 ( .A0(n1445), .A1(DMP_EXP_EWSW[2]), .B0(n1447), .B1(
DMP_SHT1_EWSW[2]), .Y(n794) );
AO22XLTS U1794 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n987), .B1(
DMP_SHT2_EWSW[2]), .Y(n793) );
INVX4TS U1795 ( .A(n1748), .Y(n1456) );
AO22XLTS U1796 ( .A0(n1456), .A1(DMP_EXP_EWSW[3]), .B0(n1449), .B1(
DMP_SHT1_EWSW[3]), .Y(n791) );
AO22XLTS U1797 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1015), .B1(
DMP_SHT2_EWSW[3]), .Y(n790) );
AO22XLTS U1798 ( .A0(n1640), .A1(DMP_SHT2_EWSW[3]), .B0(n1633), .B1(
DMP_SFG[3]), .Y(n789) );
AO22XLTS U1799 ( .A0(n1456), .A1(DMP_EXP_EWSW[4]), .B0(n1450), .B1(
DMP_SHT1_EWSW[4]), .Y(n788) );
AO22XLTS U1800 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1788), .B1(
DMP_SHT2_EWSW[4]), .Y(n787) );
AO22XLTS U1801 ( .A0(n1448), .A1(DMP_SHT2_EWSW[4]), .B0(n1633), .B1(
DMP_SFG[4]), .Y(n786) );
AO22XLTS U1802 ( .A0(n1456), .A1(DMP_EXP_EWSW[5]), .B0(n1457), .B1(
DMP_SHT1_EWSW[5]), .Y(n785) );
AO22XLTS U1803 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1015), .B1(
DMP_SHT2_EWSW[5]), .Y(n784) );
AO22XLTS U1804 ( .A0(n1456), .A1(DMP_EXP_EWSW[6]), .B0(n1447), .B1(
DMP_SHT1_EWSW[6]), .Y(n782) );
AO22XLTS U1805 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1788), .B1(
DMP_SHT2_EWSW[6]), .Y(n781) );
AO22XLTS U1806 ( .A0(n1456), .A1(DMP_EXP_EWSW[7]), .B0(n1449), .B1(
DMP_SHT1_EWSW[7]), .Y(n779) );
AO22XLTS U1807 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1015), .B1(
DMP_SHT2_EWSW[7]), .Y(n778) );
AO22XLTS U1808 ( .A0(n1649), .A1(DMP_SHT2_EWSW[7]), .B0(n1633), .B1(
DMP_SFG[7]), .Y(n777) );
AO22XLTS U1809 ( .A0(n1456), .A1(DMP_EXP_EWSW[8]), .B0(n1450), .B1(
DMP_SHT1_EWSW[8]), .Y(n776) );
AO22XLTS U1810 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1788), .B1(
DMP_SHT2_EWSW[8]), .Y(n775) );
AO22XLTS U1811 ( .A0(n1456), .A1(DMP_EXP_EWSW[9]), .B0(n1748), .B1(
DMP_SHT1_EWSW[9]), .Y(n773) );
AO22XLTS U1812 ( .A0(n986), .A1(DMP_SHT1_EWSW[9]), .B0(n1446), .B1(
DMP_SHT2_EWSW[9]), .Y(n772) );
AO22XLTS U1813 ( .A0(n1456), .A1(DMP_EXP_EWSW[10]), .B0(n1748), .B1(
DMP_SHT1_EWSW[10]), .Y(n770) );
AO22XLTS U1814 ( .A0(n986), .A1(DMP_SHT1_EWSW[10]), .B0(n1446), .B1(
DMP_SHT2_EWSW[10]), .Y(n769) );
BUFX3TS U1815 ( .A(n1748), .Y(n1447) );
AO22XLTS U1816 ( .A0(n1456), .A1(DMP_EXP_EWSW[11]), .B0(n1447), .B1(
DMP_SHT1_EWSW[11]), .Y(n767) );
AO22XLTS U1817 ( .A0(busy), .A1(DMP_SHT1_EWSW[11]), .B0(n1446), .B1(
DMP_SHT2_EWSW[11]), .Y(n766) );
AO22XLTS U1818 ( .A0(n1456), .A1(DMP_EXP_EWSW[12]), .B0(n1447), .B1(
DMP_SHT1_EWSW[12]), .Y(n764) );
AO22XLTS U1819 ( .A0(busy), .A1(DMP_SHT1_EWSW[12]), .B0(n1788), .B1(
DMP_SHT2_EWSW[12]), .Y(n763) );
AO22XLTS U1820 ( .A0(n1448), .A1(DMP_SHT2_EWSW[12]), .B0(n1633), .B1(
DMP_SFG[12]), .Y(n762) );
AO22XLTS U1821 ( .A0(n1456), .A1(DMP_EXP_EWSW[13]), .B0(n1447), .B1(
DMP_SHT1_EWSW[13]), .Y(n761) );
AO22XLTS U1822 ( .A0(busy), .A1(DMP_SHT1_EWSW[13]), .B0(n1446), .B1(
DMP_SHT2_EWSW[13]), .Y(n760) );
BUFX3TS U1823 ( .A(n1444), .Y(n1647) );
AO22XLTS U1824 ( .A0(n1647), .A1(DMP_SFG[13]), .B0(n1448), .B1(
DMP_SHT2_EWSW[13]), .Y(n759) );
AO22XLTS U1825 ( .A0(n1456), .A1(DMP_EXP_EWSW[14]), .B0(n1447), .B1(
DMP_SHT1_EWSW[14]), .Y(n758) );
AO22XLTS U1826 ( .A0(busy), .A1(DMP_SHT1_EWSW[14]), .B0(n1446), .B1(
DMP_SHT2_EWSW[14]), .Y(n757) );
AO22XLTS U1827 ( .A0(n1647), .A1(DMP_SFG[14]), .B0(n1637), .B1(
DMP_SHT2_EWSW[14]), .Y(n756) );
AO22XLTS U1828 ( .A0(n1456), .A1(DMP_EXP_EWSW[15]), .B0(n1447), .B1(
DMP_SHT1_EWSW[15]), .Y(n755) );
AO22XLTS U1829 ( .A0(busy), .A1(DMP_SHT1_EWSW[15]), .B0(n1446), .B1(
DMP_SHT2_EWSW[15]), .Y(n754) );
AO22XLTS U1830 ( .A0(n1647), .A1(DMP_SFG[15]), .B0(n1637), .B1(
DMP_SHT2_EWSW[15]), .Y(n753) );
AO22XLTS U1831 ( .A0(n1456), .A1(DMP_EXP_EWSW[16]), .B0(n1447), .B1(
DMP_SHT1_EWSW[16]), .Y(n752) );
AO22XLTS U1832 ( .A0(n1789), .A1(DMP_SHT1_EWSW[16]), .B0(n1446), .B1(
DMP_SHT2_EWSW[16]), .Y(n751) );
AO22XLTS U1833 ( .A0(n1647), .A1(DMP_SFG[16]), .B0(n1448), .B1(
DMP_SHT2_EWSW[16]), .Y(n750) );
INVX4TS U1834 ( .A(n1748), .Y(n1458) );
AO22XLTS U1835 ( .A0(n1458), .A1(DMP_EXP_EWSW[17]), .B0(n1447), .B1(
DMP_SHT1_EWSW[17]), .Y(n749) );
AO22XLTS U1836 ( .A0(n1789), .A1(DMP_SHT1_EWSW[17]), .B0(n1446), .B1(
DMP_SHT2_EWSW[17]), .Y(n748) );
AO22XLTS U1837 ( .A0(n1647), .A1(DMP_SFG[17]), .B0(n1640), .B1(
DMP_SHT2_EWSW[17]), .Y(n747) );
AO22XLTS U1838 ( .A0(n1458), .A1(DMP_EXP_EWSW[18]), .B0(n1447), .B1(
DMP_SHT1_EWSW[18]), .Y(n746) );
AO22XLTS U1839 ( .A0(n1789), .A1(DMP_SHT1_EWSW[18]), .B0(n1446), .B1(
DMP_SHT2_EWSW[18]), .Y(n745) );
AO22XLTS U1840 ( .A0(n1647), .A1(DMP_SFG[18]), .B0(n1448), .B1(
DMP_SHT2_EWSW[18]), .Y(n744) );
AO22XLTS U1841 ( .A0(n1458), .A1(DMP_EXP_EWSW[19]), .B0(n1447), .B1(
DMP_SHT1_EWSW[19]), .Y(n743) );
AO22XLTS U1842 ( .A0(n1789), .A1(DMP_SHT1_EWSW[19]), .B0(n1446), .B1(
DMP_SHT2_EWSW[19]), .Y(n742) );
AO22XLTS U1843 ( .A0(n1444), .A1(DMP_SFG[19]), .B0(n1640), .B1(
DMP_SHT2_EWSW[19]), .Y(n741) );
AO22XLTS U1844 ( .A0(n1458), .A1(DMP_EXP_EWSW[20]), .B0(n1447), .B1(
DMP_SHT1_EWSW[20]), .Y(n740) );
AO22XLTS U1845 ( .A0(n1789), .A1(DMP_SHT1_EWSW[20]), .B0(n1446), .B1(
DMP_SHT2_EWSW[20]), .Y(n739) );
AO22XLTS U1846 ( .A0(n1647), .A1(DMP_SFG[20]), .B0(n1649), .B1(
DMP_SHT2_EWSW[20]), .Y(n738) );
AO22XLTS U1847 ( .A0(n1458), .A1(DMP_EXP_EWSW[21]), .B0(n1447), .B1(
DMP_SHT1_EWSW[21]), .Y(n737) );
AO22XLTS U1848 ( .A0(n1789), .A1(DMP_SHT1_EWSW[21]), .B0(n1788), .B1(
DMP_SHT2_EWSW[21]), .Y(n736) );
AO22XLTS U1849 ( .A0(n1444), .A1(DMP_SFG[21]), .B0(n1448), .B1(
DMP_SHT2_EWSW[21]), .Y(n735) );
BUFX3TS U1850 ( .A(n1748), .Y(n1457) );
AO22XLTS U1851 ( .A0(n1458), .A1(DMP_EXP_EWSW[22]), .B0(n1457), .B1(
DMP_SHT1_EWSW[22]), .Y(n734) );
AO22XLTS U1852 ( .A0(n1014), .A1(DMP_SHT1_EWSW[22]), .B0(n1015), .B1(
DMP_SHT2_EWSW[22]), .Y(n733) );
AO22XLTS U1853 ( .A0(n1647), .A1(DMP_SFG[22]), .B0(n1640), .B1(
DMP_SHT2_EWSW[22]), .Y(n732) );
AO22XLTS U1854 ( .A0(n1458), .A1(DMP_EXP_EWSW[23]), .B0(n1457), .B1(
DMP_SHT1_EWSW[23]), .Y(n731) );
AO22XLTS U1855 ( .A0(n1014), .A1(DMP_SHT1_EWSW[23]), .B0(n1788), .B1(
DMP_SHT2_EWSW[23]), .Y(n730) );
BUFX3TS U1856 ( .A(n1444), .Y(n1556) );
AO22XLTS U1857 ( .A0(n1649), .A1(DMP_SHT2_EWSW[23]), .B0(n1556), .B1(
DMP_SFG[23]), .Y(n729) );
AO22XLTS U1858 ( .A0(n1785), .A1(DMP_SFG[23]), .B0(n1596), .B1(
DMP_exp_NRM_EW[0]), .Y(n728) );
AO22XLTS U1859 ( .A0(n1458), .A1(DMP_EXP_EWSW[24]), .B0(n1457), .B1(
DMP_SHT1_EWSW[24]), .Y(n726) );
AO22XLTS U1860 ( .A0(n986), .A1(DMP_SHT1_EWSW[24]), .B0(n1446), .B1(
DMP_SHT2_EWSW[24]), .Y(n725) );
AO22XLTS U1861 ( .A0(n1448), .A1(DMP_SHT2_EWSW[24]), .B0(n1647), .B1(
DMP_SFG[24]), .Y(n724) );
AO22XLTS U1862 ( .A0(n1785), .A1(DMP_SFG[24]), .B0(n1786), .B1(
DMP_exp_NRM_EW[1]), .Y(n723) );
AO22XLTS U1863 ( .A0(n1458), .A1(DMP_EXP_EWSW[25]), .B0(n1457), .B1(
DMP_SHT1_EWSW[25]), .Y(n721) );
AO22XLTS U1864 ( .A0(n1014), .A1(DMP_SHT1_EWSW[25]), .B0(n1788), .B1(
DMP_SHT2_EWSW[25]), .Y(n720) );
AO22XLTS U1865 ( .A0(n1649), .A1(DMP_SHT2_EWSW[25]), .B0(n1647), .B1(
DMP_SFG[25]), .Y(n719) );
AO22XLTS U1866 ( .A0(n1785), .A1(DMP_SFG[25]), .B0(n1786), .B1(
DMP_exp_NRM_EW[2]), .Y(n718) );
AO22XLTS U1867 ( .A0(n1458), .A1(DMP_EXP_EWSW[26]), .B0(n1457), .B1(
DMP_SHT1_EWSW[26]), .Y(n716) );
AO22XLTS U1868 ( .A0(n1789), .A1(DMP_SHT1_EWSW[26]), .B0(n1015), .B1(
DMP_SHT2_EWSW[26]), .Y(n715) );
AO22XLTS U1869 ( .A0(n1640), .A1(DMP_SHT2_EWSW[26]), .B0(n1556), .B1(
DMP_SFG[26]), .Y(n714) );
AO22XLTS U1870 ( .A0(n1785), .A1(DMP_SFG[26]), .B0(n1786), .B1(
DMP_exp_NRM_EW[3]), .Y(n713) );
AO22XLTS U1871 ( .A0(n1458), .A1(n1009), .B0(n1457), .B1(DMP_SHT1_EWSW[27]),
.Y(n711) );
AO22XLTS U1872 ( .A0(n1014), .A1(DMP_SHT1_EWSW[27]), .B0(n1788), .B1(
DMP_SHT2_EWSW[27]), .Y(n710) );
AO22XLTS U1873 ( .A0(n1649), .A1(DMP_SHT2_EWSW[27]), .B0(n1556), .B1(
DMP_SFG[27]), .Y(n709) );
AO22XLTS U1874 ( .A0(n1785), .A1(DMP_SFG[27]), .B0(n1786), .B1(
DMP_exp_NRM_EW[4]), .Y(n708) );
AO22XLTS U1875 ( .A0(n1458), .A1(DMP_EXP_EWSW[28]), .B0(n1457), .B1(
DMP_SHT1_EWSW[28]), .Y(n706) );
AO22XLTS U1876 ( .A0(n1014), .A1(DMP_SHT1_EWSW[28]), .B0(n1015), .B1(
DMP_SHT2_EWSW[28]), .Y(n705) );
AO22XLTS U1877 ( .A0(n1448), .A1(DMP_SHT2_EWSW[28]), .B0(n1647), .B1(
DMP_SFG[28]), .Y(n704) );
AO22XLTS U1878 ( .A0(n1785), .A1(DMP_SFG[28]), .B0(n1786), .B1(
DMP_exp_NRM_EW[5]), .Y(n703) );
AO22XLTS U1879 ( .A0(n1458), .A1(DMP_EXP_EWSW[29]), .B0(n1457), .B1(
DMP_SHT1_EWSW[29]), .Y(n701) );
AO22XLTS U1880 ( .A0(n986), .A1(DMP_SHT1_EWSW[29]), .B0(n1788), .B1(
DMP_SHT2_EWSW[29]), .Y(n700) );
AO22XLTS U1881 ( .A0(n1448), .A1(DMP_SHT2_EWSW[29]), .B0(n1556), .B1(
DMP_SFG[29]), .Y(n699) );
AO22XLTS U1882 ( .A0(n1785), .A1(DMP_SFG[29]), .B0(n1786), .B1(
DMP_exp_NRM_EW[6]), .Y(n698) );
AO22XLTS U1883 ( .A0(n1654), .A1(DMP_EXP_EWSW[30]), .B0(n1457), .B1(
DMP_SHT1_EWSW[30]), .Y(n696) );
AO22XLTS U1884 ( .A0(n1014), .A1(DMP_SHT1_EWSW[30]), .B0(n1015), .B1(
DMP_SHT2_EWSW[30]), .Y(n695) );
AO22XLTS U1885 ( .A0(n1649), .A1(DMP_SHT2_EWSW[30]), .B0(n1556), .B1(
DMP_SFG[30]), .Y(n694) );
INVX2TS U1886 ( .A(n1575), .Y(n1565) );
AO22XLTS U1887 ( .A0(n1565), .A1(DMP_SFG[30]), .B0(n1596), .B1(
DMP_exp_NRM_EW[7]), .Y(n693) );
BUFX3TS U1888 ( .A(n1748), .Y(n1449) );
BUFX3TS U1889 ( .A(n1748), .Y(n1450) );
OAI222X1TS U1890 ( .A0(n1453), .A1(n1743), .B0(n1668), .B1(
Shift_reg_FLAGS_7_6), .C0(n1652), .C1(n1451), .Y(n644) );
OAI222X1TS U1891 ( .A0(n1453), .A1(n1674), .B0(n1745), .B1(
Shift_reg_FLAGS_7_6), .C0(n1721), .C1(n1451), .Y(n643) );
OAI222X1TS U1892 ( .A0(n1453), .A1(n1675), .B0(n1741), .B1(
Shift_reg_FLAGS_7_6), .C0(n1720), .C1(n1451), .Y(n642) );
NAND2X1TS U1893 ( .A(n1454), .B(Shift_reg_FLAGS_7[0]), .Y(n1455) );
OAI2BB1X1TS U1894 ( .A0N(underflow_flag), .A1N(n1625), .B0(n1455), .Y(n640)
);
AO22XLTS U1895 ( .A0(n1458), .A1(ZERO_FLAG_EXP), .B0(n1748), .B1(
ZERO_FLAG_SHT1), .Y(n638) );
AO22XLTS U1896 ( .A0(n1014), .A1(ZERO_FLAG_SHT1), .B0(n1015), .B1(
ZERO_FLAG_SHT2), .Y(n637) );
AO22XLTS U1897 ( .A0(n1649), .A1(ZERO_FLAG_SHT2), .B0(n1556), .B1(
ZERO_FLAG_SFG), .Y(n636) );
AO22XLTS U1898 ( .A0(n1785), .A1(ZERO_FLAG_SFG), .B0(n1786), .B1(
ZERO_FLAG_NRM), .Y(n635) );
AO22XLTS U1899 ( .A0(n1456), .A1(OP_FLAG_EXP), .B0(n1748), .B1(OP_FLAG_SHT1),
.Y(n632) );
AO22XLTS U1900 ( .A0(n1014), .A1(OP_FLAG_SHT1), .B0(n1015), .B1(OP_FLAG_SHT2), .Y(n631) );
BUFX3TS U1901 ( .A(n1492), .Y(n1496) );
INVX4TS U1902 ( .A(n1496), .Y(n1544) );
AO22XLTS U1903 ( .A0(n1444), .A1(n1544), .B0(n1649), .B1(OP_FLAG_SHT2), .Y(
n630) );
AO22XLTS U1904 ( .A0(n1458), .A1(SIGN_FLAG_EXP), .B0(n1457), .B1(
SIGN_FLAG_SHT1), .Y(n629) );
AO22XLTS U1905 ( .A0(n986), .A1(SIGN_FLAG_SHT1), .B0(n987), .B1(
SIGN_FLAG_SHT2), .Y(n628) );
AO22XLTS U1906 ( .A0(n1640), .A1(SIGN_FLAG_SHT2), .B0(n1556), .B1(
SIGN_FLAG_SFG), .Y(n627) );
AO22XLTS U1907 ( .A0(n1565), .A1(SIGN_FLAG_SFG), .B0(n1596), .B1(
SIGN_FLAG_NRM), .Y(n626) );
AOI22X1TS U1908 ( .A0(n1544), .A1(n1019), .B0(DmP_mant_SFG_SWR[15]), .B1(
n1496), .Y(intadd_3_CI) );
AOI22X1TS U1909 ( .A0(n1544), .A1(n1020), .B0(DmP_mant_SFG_SWR[16]), .B1(
n1496), .Y(intadd_3_B_1_) );
AOI22X1TS U1910 ( .A0(n1598), .A1(intadd_3_SUM_1_), .B0(n1737), .B1(n1596),
.Y(n622) );
AOI22X1TS U1911 ( .A0(n1544), .A1(n1021), .B0(DmP_mant_SFG_SWR[17]), .B1(
n1496), .Y(intadd_3_B_2_) );
AOI22X1TS U1912 ( .A0(n1563), .A1(intadd_3_SUM_2_), .B0(n1693), .B1(n1596),
.Y(n621) );
AOI22X1TS U1913 ( .A0(n1544), .A1(n1022), .B0(DmP_mant_SFG_SWR[18]), .B1(
n1496), .Y(intadd_3_B_3_) );
AOI22X1TS U1914 ( .A0(n1544), .A1(n1024), .B0(DmP_mant_SFG_SWR[19]), .B1(
n1496), .Y(intadd_3_B_4_) );
AOI22X1TS U1915 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1492), .B0(n1491), .B1(
n1730), .Y(intadd_3_B_5_) );
AOI22X1TS U1916 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1492), .B0(n1491), .B1(
n1731), .Y(intadd_3_B_6_) );
AOI22X1TS U1917 ( .A0(n1565), .A1(intadd_3_SUM_6_), .B0(n1685), .B1(n1596),
.Y(n617) );
AOI22X1TS U1918 ( .A0(n1565), .A1(intadd_3_SUM_7_), .B0(n1655), .B1(n1596),
.Y(n616) );
AOI22X1TS U1919 ( .A0(n1598), .A1(intadd_3_SUM_8_), .B0(n1650), .B1(n1596),
.Y(n615) );
AOI22X1TS U1920 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1492), .B0(n1491), .B1(
n1747), .Y(intadd_3_B_9_) );
AOI22X1TS U1921 ( .A0(n1598), .A1(intadd_3_SUM_9_), .B0(n1651), .B1(n1596),
.Y(n614) );
AOI22X1TS U1922 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1544), .B0(n1496), .B1(
n1676), .Y(n1459) );
XNOR2X1TS U1923 ( .A(intadd_3_n1), .B(n1459), .Y(n1460) );
AOI22X1TS U1924 ( .A0(n1563), .A1(n1460), .B0(n1677), .B1(n1596), .Y(n613)
);
AOI22X1TS U1925 ( .A0(Data_array_SWR[19]), .A1(n1461), .B0(
Data_array_SWR[15]), .B1(n1086), .Y(n1462) );
OAI21X1TS U1926 ( .A0(n1667), .A1(n1578), .B0(n1462), .Y(n1567) );
INVX2TS U1927 ( .A(n1086), .Y(n1577) );
OAI22X1TS U1928 ( .A0(n1653), .A1(n1579), .B0(n1725), .B1(n1577), .Y(n1568)
);
NAND2X2TS U1929 ( .A(n958), .B(n1487), .Y(n1623) );
OAI22X1TS U1930 ( .A0(n1671), .A1(n1623), .B0(n1735), .B1(n1582), .Y(n1463)
);
AOI221X1TS U1931 ( .A0(left_right_SHT2), .A1(n1567), .B0(n958), .B1(n1568),
.C0(n1463), .Y(n1600) );
AOI22X1TS U1932 ( .A0(n1637), .A1(n1600), .B0(n1026), .B1(n1444), .Y(n612)
);
AOI22X1TS U1933 ( .A0(n1544), .A1(DmP_mant_SFG_SWR[11]), .B0(n1496), .B1(
n1017), .Y(n1557) );
NAND2BX1TS U1934 ( .AN(DMP_SFG[10]), .B(n1464), .Y(n1571) );
OAI2BB1X1TS U1935 ( .A0N(n1593), .A1N(n1571), .B0(n1572), .Y(n1558) );
INVX2TS U1936 ( .A(n1558), .Y(n1465) );
XNOR2X1TS U1937 ( .A(n1467), .B(n1466), .Y(n1468) );
AOI22X1TS U1938 ( .A0(n1563), .A1(n1468), .B0(n1678), .B1(n1596), .Y(n611)
);
AOI22X1TS U1939 ( .A0(Data_array_SWR[13]), .A1(n1469), .B0(Data_array_SWR[9]), .B1(n1461), .Y(n1471) );
AOI22X1TS U1940 ( .A0(Data_array_SWR[5]), .A1(n1086), .B0(Data_array_SWR[1]),
.B1(n1487), .Y(n1470) );
OAI211X1TS U1941 ( .A0(n1477), .A1(n1681), .B0(n1471), .C0(n1470), .Y(n1627)
);
AOI22X1TS U1942 ( .A0(Data_array_SWR[24]), .A1(n1620), .B0(n958), .B1(n1627),
.Y(n1472) );
AOI22X1TS U1943 ( .A0(n1637), .A1(n1472), .B0(n1556), .B1(n1027), .Y(n609)
);
AOI22X1TS U1944 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1492), .B0(n1491), .B1(
n1027), .Y(n1473) );
AOI2BB2XLTS U1945 ( .B0(n1565), .B1(n1473), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1565), .Y(n608) );
AOI22X1TS U1946 ( .A0(Data_array_SWR[12]), .A1(n1086), .B0(
Data_array_SWR[16]), .B1(n1461), .Y(n1476) );
NOR2X2TS U1947 ( .A(n1681), .B(n1474), .Y(n1538) );
AOI22X1TS U1948 ( .A0(Data_array_SWR[20]), .A1(n1469), .B0(
Data_array_SWR[24]), .B1(n1538), .Y(n1475) );
NAND2X1TS U1949 ( .A(n1476), .B(n1475), .Y(n1621) );
INVX2TS U1950 ( .A(n1477), .Y(n1619) );
AOI22X1TS U1951 ( .A0(n1637), .A1(n1617), .B0(n1028), .B1(n1556), .Y(n606)
);
AOI22X1TS U1952 ( .A0(n1544), .A1(n1031), .B0(DmP_mant_SFG_SWR[7]), .B1(
n1543), .Y(n1479) );
NAND2BX1TS U1953 ( .AN(DMP_SFG[5]), .B(n1479), .Y(n1532) );
AOI22X1TS U1954 ( .A0(n1544), .A1(DmP_mant_SFG_SWR[6]), .B0(n1496), .B1(
n1030), .Y(n1478) );
AOI22X1TS U1955 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1544), .B0(n1496), .B1(
n1670), .Y(n1501) );
NAND2X1TS U1956 ( .A(n1501), .B(DMP_SFG[3]), .Y(n1503) );
NAND2X1TS U1957 ( .A(n1478), .B(DMP_SFG[4]), .Y(n1522) );
INVX2TS U1958 ( .A(n1479), .Y(n1480) );
AOI21X1TS U1959 ( .A0(n1532), .A1(n1481), .B0(n1530), .Y(n1484) );
OAI22X1TS U1960 ( .A0(n1492), .A1(n1028), .B0(DmP_mant_SFG_SWR[8]), .B1(
n1491), .Y(n1482) );
NAND2BX1TS U1961 ( .AN(n1482), .B(DMP_SFG[6]), .Y(n1587) );
NAND2BX1TS U1962 ( .AN(DMP_SFG[6]), .B(n1482), .Y(n1531) );
NAND2X1TS U1963 ( .A(n1587), .B(n1531), .Y(n1483) );
XNOR2X1TS U1964 ( .A(n1484), .B(n1483), .Y(n1485) );
AOI22X1TS U1965 ( .A0(Data_array_SWR[12]), .A1(n1469), .B0(Data_array_SWR[8]), .B1(n1461), .Y(n1489) );
AOI22X1TS U1966 ( .A0(Data_array_SWR[4]), .A1(n1086), .B0(Data_array_SWR[0]),
.B1(n1487), .Y(n1488) );
OAI211X1TS U1967 ( .A0(n1541), .A1(n1681), .B0(n1489), .C0(n1488), .Y(n1644)
);
AOI22X1TS U1968 ( .A0(Data_array_SWR[25]), .A1(n1620), .B0(n958), .B1(n1644),
.Y(n1490) );
AOI22X1TS U1969 ( .A0(n1649), .A1(n1490), .B0(n1633), .B1(n1029), .Y(n603)
);
AOI22X1TS U1970 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1492), .B0(n1491), .B1(
n1029), .Y(n1493) );
AOI2BB2XLTS U1971 ( .B0(n1565), .B1(n1493), .A0N(Raw_mant_NRM_SWR[0]), .A1N(
n1785), .Y(n602) );
AOI22X1TS U1972 ( .A0(Data_array_SWR[14]), .A1(n1461), .B0(
Data_array_SWR[10]), .B1(n1086), .Y(n1500) );
AOI22X1TS U1973 ( .A0(Data_array_SWR[22]), .A1(n1538), .B0(
Data_array_SWR[18]), .B1(n1469), .Y(n1499) );
NAND2X1TS U1974 ( .A(n1500), .B(n1499), .Y(n1616) );
AOI22X1TS U1975 ( .A0(n1637), .A1(n1614), .B0(n1030), .B1(n1444), .Y(n595)
);
INVX2TS U1976 ( .A(n1522), .Y(n1533) );
INVX2TS U1977 ( .A(n1513), .Y(n1504) );
INVX2TS U1978 ( .A(n1503), .Y(n1514) );
XNOR2X1TS U1979 ( .A(n1507), .B(n1506), .Y(n1508) );
AOI22X1TS U1980 ( .A0(n1598), .A1(n1508), .B0(n1690), .B1(n1575), .Y(n594)
);
AOI22X1TS U1981 ( .A0(Data_array_SWR[20]), .A1(n1511), .B0(
Data_array_SWR[24]), .B1(n1512), .Y(n1521) );
AOI22X1TS U1982 ( .A0(Data_array_SWR[12]), .A1(n1461), .B0(Data_array_SWR[8]), .B1(n1086), .Y(n1510) );
NAND2X1TS U1983 ( .A(Data_array_SWR[16]), .B(n1469), .Y(n1509) );
OAI211X1TS U1984 ( .A0(n1521), .A1(n1681), .B0(n1510), .C0(n1509), .Y(n1613)
);
AO22X1TS U1985 ( .A0(Data_array_SWR[25]), .A1(n1512), .B0(Data_array_SWR[21]), .B1(n1511), .Y(n1612) );
AOI22X1TS U1986 ( .A0(n1637), .A1(n1611), .B0(n1647), .B1(n1673), .Y(n592)
);
CMPR32X2TS U1987 ( .A(DMP_SFG[2]), .B(n995), .C(n1515), .CO(n1516), .S(n1498) );
XNOR2X1TS U1988 ( .A(n1517), .B(n1516), .Y(n1518) );
AOI22X1TS U1989 ( .A0(Data_array_SWR[13]), .A1(n1461), .B0(Data_array_SWR[9]), .B1(n1086), .Y(n1520) );
AOI22X1TS U1990 ( .A0(Data_array_SWR[17]), .A1(n1469), .B0(
shift_value_SHT2_EWR[4]), .B1(n1612), .Y(n1519) );
NAND2X1TS U1991 ( .A(n1520), .B(n1519), .Y(n1610) );
INVX2TS U1992 ( .A(n1521), .Y(n1609) );
AOI22X1TS U1993 ( .A0(n1649), .A1(n1608), .B0(n1633), .B1(n1670), .Y(n590)
);
NOR2BX1TS U1994 ( .AN(n1532), .B(n1530), .Y(n1526) );
XNOR2X1TS U1995 ( .A(n1526), .B(n1525), .Y(n1527) );
AOI22X1TS U1996 ( .A0(n1598), .A1(n1527), .B0(n1682), .B1(n1575), .Y(n589)
);
AOI22X1TS U1997 ( .A0(Data_array_SWR[15]), .A1(n1461), .B0(
Data_array_SWR[11]), .B1(n1086), .Y(n1529) );
AOI22X1TS U1998 ( .A0(Data_array_SWR[23]), .A1(n1538), .B0(
Data_array_SWR[19]), .B1(n1469), .Y(n1528) );
NAND2X1TS U1999 ( .A(n1529), .B(n1528), .Y(n1607) );
AOI22X1TS U2000 ( .A0(n1637), .A1(n1605), .B0(n1031), .B1(n1633), .Y(n588)
);
OAI2BB1X1TS U2001 ( .A0N(n1530), .A1N(n1531), .B0(n1587), .Y(n1546) );
AOI22X1TS U2002 ( .A0(n1544), .A1(DmP_mant_SFG_SWR[9]), .B0(n1543), .B1(
n1033), .Y(n1534) );
NOR2BX1TS U2003 ( .AN(n1586), .B(n1588), .Y(n1535) );
XOR2X1TS U2004 ( .A(n1536), .B(n1535), .Y(n1537) );
AOI22X1TS U2005 ( .A0(n1598), .A1(n1537), .B0(n1691), .B1(n1575), .Y(n587)
);
AOI22X1TS U2006 ( .A0(Data_array_SWR[17]), .A1(n1461), .B0(
Data_array_SWR[13]), .B1(n1086), .Y(n1540) );
AOI22X1TS U2007 ( .A0(Data_array_SWR[21]), .A1(n1469), .B0(
Data_array_SWR[25]), .B1(n1538), .Y(n1539) );
NAND2X1TS U2008 ( .A(n1540), .B(n1539), .Y(n1604) );
INVX2TS U2009 ( .A(n1541), .Y(n1603) );
AOI22X1TS U2010 ( .A0(n1649), .A1(n1602), .B0(n1633), .B1(n1033), .Y(n586)
);
AOI22X1TS U2011 ( .A0(n1544), .A1(DmP_mant_SFG_SWR[10]), .B0(n1543), .B1(
n1018), .Y(n1545) );
NAND2X1TS U2012 ( .A(n1545), .B(DMP_SFG[8]), .Y(n1569) );
INVX2TS U2013 ( .A(n1569), .Y(n1591) );
NOR2X2TS U2014 ( .A(n1545), .B(DMP_SFG[8]), .Y(n1589) );
INVX2TS U2015 ( .A(n1546), .Y(n1547) );
XNOR2X1TS U2016 ( .A(n1549), .B(n1548), .Y(n1550) );
AOI22X1TS U2017 ( .A0(n1598), .A1(n1550), .B0(n1032), .B1(n1575), .Y(n585)
);
AOI22X1TS U2018 ( .A0(Data_array_SWR[12]), .A1(n1646), .B0(
Data_array_SWR[13]), .B1(n1620), .Y(n1551) );
OAI221X1TS U2019 ( .A0(n982), .A1(n1554), .B0(n958), .B1(n1555), .C0(n1551),
.Y(n1552) );
AOI22X1TS U2020 ( .A0(Data_array_SWR[12]), .A1(n1620), .B0(
Data_array_SWR[13]), .B1(n1646), .Y(n1553) );
OAI221X1TS U2021 ( .A0(left_right_SHT2), .A1(n1555), .B0(n958), .B1(n1554),
.C0(n1553), .Y(n1601) );
OR2X1TS U2022 ( .A(DMP_SFG[9]), .B(n1557), .Y(n1592) );
XNOR2X1TS U2023 ( .A(n1562), .B(n1561), .Y(n1564) );
OAI22X1TS U2024 ( .A0(n1671), .A1(n1582), .B0(n1735), .B1(n1623), .Y(n1566)
);
AOI221X1TS U2025 ( .A0(left_right_SHT2), .A1(n1568), .B0(n981), .B1(n1567),
.C0(n1566), .Y(n1599) );
AOI22X1TS U2026 ( .A0(n1649), .A1(n1599), .B0(n1633), .B1(n1017), .Y(n580)
);
AOI21X1TS U2027 ( .A0(n1592), .A1(n1570), .B0(n1593), .Y(n1574) );
NAND2X1TS U2028 ( .A(n1572), .B(n1571), .Y(n1573) );
XNOR2X1TS U2029 ( .A(n1574), .B(n1573), .Y(n1576) );
AOI22X1TS U2030 ( .A0(n1563), .A1(n1576), .B0(n1680), .B1(n1575), .Y(n579)
);
OAI22X1TS U2031 ( .A0(n1667), .A1(n1579), .B0(n1729), .B1(n1577), .Y(n1584)
);
OAI222X1TS U2032 ( .A0(n1579), .A1(n1725), .B0(n1578), .B1(n1653), .C0(n1577), .C1(n1671), .Y(n1585) );
OAI22X1TS U2033 ( .A0(n1734), .A1(n1623), .B0(n1672), .B1(n1582), .Y(n1580)
);
AOI221X1TS U2034 ( .A0(left_right_SHT2), .A1(n1584), .B0(n966), .B1(n1585),
.C0(n1580), .Y(n1581) );
AOI22X1TS U2035 ( .A0(n1649), .A1(n1581), .B0(n1633), .B1(n1018), .Y(n578)
);
OAI2BB2XLTS U2036 ( .B0(n1581), .B1(n979), .A0N(final_result_ieee[8]), .A1N(
n1625), .Y(n577) );
OAI22X1TS U2037 ( .A0(n1734), .A1(n1582), .B0(n1672), .B1(n1623), .Y(n1583)
);
AOI221X1TS U2038 ( .A0(left_right_SHT2), .A1(n1585), .B0(n958), .B1(n1584),
.C0(n1583), .Y(n1629) );
OAI2BB2XLTS U2039 ( .B0(n1629), .B1(n979), .A0N(final_result_ieee[13]),
.A1N(n1625), .Y(n576) );
OAI32X1TS U2040 ( .A0(n1589), .A1(n1588), .A2(n1587), .B0(n1586), .B1(n1589),
.Y(n1590) );
XNOR2X1TS U2041 ( .A(n1595), .B(n1594), .Y(n1597) );
AOI22X1TS U2042 ( .A0(n1598), .A1(n1597), .B0(n1679), .B1(n1596), .Y(n575)
);
OAI2BB2XLTS U2043 ( .B0(n1599), .B1(n979), .A0N(final_result_ieee[9]), .A1N(
n1625), .Y(n574) );
OAI2BB2XLTS U2044 ( .B0(n1600), .B1(n979), .A0N(final_result_ieee[12]),
.A1N(n1625), .Y(n573) );
OAI2BB2XLTS U2045 ( .B0(n1602), .B1(n980), .A0N(final_result_ieee[7]), .A1N(
n1625), .Y(n571) );
OAI2BB2XLTS U2046 ( .B0(n1630), .B1(n980), .A0N(final_result_ieee[14]),
.A1N(n1625), .Y(n570) );
OAI2BB2XLTS U2047 ( .B0(n1605), .B1(n979), .A0N(final_result_ieee[5]), .A1N(
n953), .Y(n569) );
OAI2BB2XLTS U2048 ( .B0(n1632), .B1(n980), .A0N(final_result_ieee[16]),
.A1N(n953), .Y(n568) );
OAI2BB2XLTS U2049 ( .B0(n1608), .B1(n980), .A0N(final_result_ieee[3]), .A1N(
n953), .Y(n567) );
OAI2BB2XLTS U2050 ( .B0(n1635), .B1(n980), .A0N(final_result_ieee[18]),
.A1N(n953), .Y(n566) );
OAI2BB2XLTS U2051 ( .B0(n1611), .B1(n980), .A0N(final_result_ieee[2]), .A1N(
n953), .Y(n565) );
OAI2BB2XLTS U2052 ( .B0(n1636), .B1(n980), .A0N(final_result_ieee[19]),
.A1N(n953), .Y(n564) );
OAI2BB2XLTS U2053 ( .B0(n1614), .B1(n980), .A0N(final_result_ieee[4]), .A1N(
n953), .Y(n563) );
OAI2BB2XLTS U2054 ( .B0(n1634), .B1(n980), .A0N(final_result_ieee[17]),
.A1N(n953), .Y(n562) );
OAI2BB2XLTS U2055 ( .B0(n1617), .B1(n979), .A0N(final_result_ieee[6]), .A1N(
n953), .Y(n559) );
OAI2BB2XLTS U2056 ( .B0(n1631), .B1(n979), .A0N(final_result_ieee[15]),
.A1N(n1625), .Y(n558) );
OAI22X1TS U2057 ( .A0(n1622), .A1(n981), .B0(n1653), .B1(n1623), .Y(n1638)
);
OAI22X1TS U2058 ( .A0(n1624), .A1(n981), .B0(n1667), .B1(n1623), .Y(n1639)
);
AOI22X1TS U2059 ( .A0(Data_array_SWR[24]), .A1(n1646), .B0(left_right_SHT2),
.B1(n1627), .Y(n1643) );
OAI2BB2XLTS U2060 ( .B0(n1643), .B1(n979), .A0N(final_result_ieee[22]),
.A1N(n953), .Y(n555) );
AOI22X1TS U2061 ( .A0(n1649), .A1(n1629), .B0(n1019), .B1(n1633), .Y(n554)
);
AOI22X1TS U2062 ( .A0(n1649), .A1(n1630), .B0(n1020), .B1(n1633), .Y(n553)
);
AOI22X1TS U2063 ( .A0(n1637), .A1(n1631), .B0(n1021), .B1(n1642), .Y(n552)
);
AOI22X1TS U2064 ( .A0(n1637), .A1(n1632), .B0(n1022), .B1(n1633), .Y(n551)
);
AOI22X1TS U2065 ( .A0(n1637), .A1(n1634), .B0(n1024), .B1(n1633), .Y(n550)
);
AOI22X1TS U2066 ( .A0(n1637), .A1(n1635), .B0(n1642), .B1(n1730), .Y(n549)
);
AOI22X1TS U2067 ( .A0(n1637), .A1(n1636), .B0(n1642), .B1(n1731), .Y(n548)
);
AO22XLTS U2068 ( .A0(n1444), .A1(DmP_mant_SFG_SWR[22]), .B0(n1640), .B1(
n1638), .Y(n547) );
AO22XLTS U2069 ( .A0(n1444), .A1(DmP_mant_SFG_SWR[23]), .B0(n1640), .B1(
n1639), .Y(n546) );
AOI22X1TS U2070 ( .A0(n1637), .A1(n1643), .B0(n1642), .B1(n1747), .Y(n545)
);
AOI22X1TS U2071 ( .A0(Data_array_SWR[25]), .A1(n1646), .B0(n982), .B1(n1644),
.Y(n1648) );
AOI22X1TS U2072 ( .A0(n1637), .A1(n1648), .B0(n1647), .B1(n1676), .Y(n544)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk20.tcl_ACAIN16Q4_syn.sdf");
endmodule
|
// lpddr2_cntrlr_s0_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_s0_mm_interconnect_1 (
input wire avl_clk_out_clk_clk, // avl_clk_out_clk.clk
input wire trk_mm_bridge_reset_reset_bridge_in_reset_reset, // trk_mm_bridge_reset_reset_bridge_in_reset.reset
input wire [15:0] trk_mm_bridge_m0_address, // trk_mm_bridge_m0.address
output wire trk_mm_bridge_m0_waitrequest, // .waitrequest
input wire [0:0] trk_mm_bridge_m0_burstcount, // .burstcount
input wire [3:0] trk_mm_bridge_m0_byteenable, // .byteenable
input wire trk_mm_bridge_m0_read, // .read
output wire [31:0] trk_mm_bridge_m0_readdata, // .readdata
output wire trk_mm_bridge_m0_readdatavalid, // .readdatavalid
input wire trk_mm_bridge_m0_write, // .write
input wire [31:0] trk_mm_bridge_m0_writedata, // .writedata
input wire trk_mm_bridge_m0_debugaccess, // .debugaccess
output wire [3:0] sequencer_reg_file_inst_avl_address, // sequencer_reg_file_inst_avl.address
output wire sequencer_reg_file_inst_avl_write, // .write
output wire sequencer_reg_file_inst_avl_read, // .read
input wire [31:0] sequencer_reg_file_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_reg_file_inst_avl_writedata, // .writedata
output wire [3:0] sequencer_reg_file_inst_avl_byteenable, // .byteenable
input wire sequencer_reg_file_inst_avl_waitrequest, // .waitrequest
output wire [12:0] sequencer_scc_mgr_inst_avl_address, // sequencer_scc_mgr_inst_avl.address
output wire sequencer_scc_mgr_inst_avl_write, // .write
output wire sequencer_scc_mgr_inst_avl_read, // .read
input wire [31:0] sequencer_scc_mgr_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_scc_mgr_inst_avl_writedata, // .writedata
input wire sequencer_scc_mgr_inst_avl_waitrequest // .waitrequest
);
wire trk_mm_bridge_m0_translator_avalon_universal_master_0_waitrequest; // trk_mm_bridge_m0_agent:av_waitrequest -> trk_mm_bridge_m0_translator:uav_waitrequest
wire [31:0] trk_mm_bridge_m0_translator_avalon_universal_master_0_readdata; // trk_mm_bridge_m0_agent:av_readdata -> trk_mm_bridge_m0_translator:uav_readdata
wire trk_mm_bridge_m0_translator_avalon_universal_master_0_debugaccess; // trk_mm_bridge_m0_translator:uav_debugaccess -> trk_mm_bridge_m0_agent:av_debugaccess
wire [17:0] trk_mm_bridge_m0_translator_avalon_universal_master_0_address; // trk_mm_bridge_m0_translator:uav_address -> trk_mm_bridge_m0_agent:av_address
wire trk_mm_bridge_m0_translator_avalon_universal_master_0_read; // trk_mm_bridge_m0_translator:uav_read -> trk_mm_bridge_m0_agent:av_read
wire [3:0] trk_mm_bridge_m0_translator_avalon_universal_master_0_byteenable; // trk_mm_bridge_m0_translator:uav_byteenable -> trk_mm_bridge_m0_agent:av_byteenable
wire trk_mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // trk_mm_bridge_m0_agent:av_readdatavalid -> trk_mm_bridge_m0_translator:uav_readdatavalid
wire trk_mm_bridge_m0_translator_avalon_universal_master_0_lock; // trk_mm_bridge_m0_translator:uav_lock -> trk_mm_bridge_m0_agent:av_lock
wire trk_mm_bridge_m0_translator_avalon_universal_master_0_write; // trk_mm_bridge_m0_translator:uav_write -> trk_mm_bridge_m0_agent:av_write
wire [31:0] trk_mm_bridge_m0_translator_avalon_universal_master_0_writedata; // trk_mm_bridge_m0_translator:uav_writedata -> trk_mm_bridge_m0_agent:av_writedata
wire [2:0] trk_mm_bridge_m0_translator_avalon_universal_master_0_burstcount; // trk_mm_bridge_m0_translator:uav_burstcount -> trk_mm_bridge_m0_agent:av_burstcount
wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_readdata; // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_agent:m0_readdata
wire sequencer_scc_mgr_inst_avl_agent_m0_waitrequest; // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_agent:m0_waitrequest
wire sequencer_scc_mgr_inst_avl_agent_m0_debugaccess; // sequencer_scc_mgr_inst_avl_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
wire [17:0] sequencer_scc_mgr_inst_avl_agent_m0_address; // sequencer_scc_mgr_inst_avl_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
wire [3:0] sequencer_scc_mgr_inst_avl_agent_m0_byteenable; // sequencer_scc_mgr_inst_avl_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
wire sequencer_scc_mgr_inst_avl_agent_m0_read; // sequencer_scc_mgr_inst_avl_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
wire sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid; // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_agent:m0_readdatavalid
wire sequencer_scc_mgr_inst_avl_agent_m0_lock; // sequencer_scc_mgr_inst_avl_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_writedata; // sequencer_scc_mgr_inst_avl_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
wire sequencer_scc_mgr_inst_avl_agent_m0_write; // sequencer_scc_mgr_inst_avl_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
wire [2:0] sequencer_scc_mgr_inst_avl_agent_m0_burstcount; // sequencer_scc_mgr_inst_avl_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
wire sequencer_scc_mgr_inst_avl_agent_rf_source_valid; // sequencer_scc_mgr_inst_avl_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_valid
wire [88:0] sequencer_scc_mgr_inst_avl_agent_rf_source_data; // sequencer_scc_mgr_inst_avl_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_data
wire sequencer_scc_mgr_inst_avl_agent_rf_source_ready; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_agent:rf_source_ready
wire sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket; // sequencer_scc_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket; // sequencer_scc_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_agent:rf_sink_valid
wire [88:0] sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_agent:rf_sink_data
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready; // sequencer_scc_mgr_inst_avl_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_agent:rf_sink_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> sequencer_scc_mgr_inst_avl_agent:cp_valid
wire [87:0] cmd_mux_src_data; // cmd_mux:src_data -> sequencer_scc_mgr_inst_avl_agent:cp_data
wire cmd_mux_src_ready; // sequencer_scc_mgr_inst_avl_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> sequencer_scc_mgr_inst_avl_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> sequencer_scc_mgr_inst_avl_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> sequencer_scc_mgr_inst_avl_agent:cp_endofpacket
wire [31:0] sequencer_reg_file_inst_avl_agent_m0_readdata; // sequencer_reg_file_inst_avl_translator:uav_readdata -> sequencer_reg_file_inst_avl_agent:m0_readdata
wire sequencer_reg_file_inst_avl_agent_m0_waitrequest; // sequencer_reg_file_inst_avl_translator:uav_waitrequest -> sequencer_reg_file_inst_avl_agent:m0_waitrequest
wire sequencer_reg_file_inst_avl_agent_m0_debugaccess; // sequencer_reg_file_inst_avl_agent:m0_debugaccess -> sequencer_reg_file_inst_avl_translator:uav_debugaccess
wire [17:0] sequencer_reg_file_inst_avl_agent_m0_address; // sequencer_reg_file_inst_avl_agent:m0_address -> sequencer_reg_file_inst_avl_translator:uav_address
wire [3:0] sequencer_reg_file_inst_avl_agent_m0_byteenable; // sequencer_reg_file_inst_avl_agent:m0_byteenable -> sequencer_reg_file_inst_avl_translator:uav_byteenable
wire sequencer_reg_file_inst_avl_agent_m0_read; // sequencer_reg_file_inst_avl_agent:m0_read -> sequencer_reg_file_inst_avl_translator:uav_read
wire sequencer_reg_file_inst_avl_agent_m0_readdatavalid; // sequencer_reg_file_inst_avl_translator:uav_readdatavalid -> sequencer_reg_file_inst_avl_agent:m0_readdatavalid
wire sequencer_reg_file_inst_avl_agent_m0_lock; // sequencer_reg_file_inst_avl_agent:m0_lock -> sequencer_reg_file_inst_avl_translator:uav_lock
wire [31:0] sequencer_reg_file_inst_avl_agent_m0_writedata; // sequencer_reg_file_inst_avl_agent:m0_writedata -> sequencer_reg_file_inst_avl_translator:uav_writedata
wire sequencer_reg_file_inst_avl_agent_m0_write; // sequencer_reg_file_inst_avl_agent:m0_write -> sequencer_reg_file_inst_avl_translator:uav_write
wire [2:0] sequencer_reg_file_inst_avl_agent_m0_burstcount; // sequencer_reg_file_inst_avl_agent:m0_burstcount -> sequencer_reg_file_inst_avl_translator:uav_burstcount
wire sequencer_reg_file_inst_avl_agent_rf_source_valid; // sequencer_reg_file_inst_avl_agent:rf_source_valid -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_valid
wire [88:0] sequencer_reg_file_inst_avl_agent_rf_source_data; // sequencer_reg_file_inst_avl_agent:rf_source_data -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_data
wire sequencer_reg_file_inst_avl_agent_rf_source_ready; // sequencer_reg_file_inst_avl_agent_rsp_fifo:in_ready -> sequencer_reg_file_inst_avl_agent:rf_source_ready
wire sequencer_reg_file_inst_avl_agent_rf_source_startofpacket; // sequencer_reg_file_inst_avl_agent:rf_source_startofpacket -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_reg_file_inst_avl_agent_rf_source_endofpacket; // sequencer_reg_file_inst_avl_agent:rf_source_endofpacket -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_valid -> sequencer_reg_file_inst_avl_agent:rf_sink_valid
wire [88:0] sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_data -> sequencer_reg_file_inst_avl_agent:rf_sink_data
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready; // sequencer_reg_file_inst_avl_agent:rf_sink_ready -> sequencer_reg_file_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_reg_file_inst_avl_agent:rf_sink_startofpacket
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_reg_file_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> sequencer_reg_file_inst_avl_agent:cp_valid
wire [87:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> sequencer_reg_file_inst_avl_agent:cp_data
wire cmd_mux_001_src_ready; // sequencer_reg_file_inst_avl_agent:cp_ready -> cmd_mux_001:src_ready
wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> sequencer_reg_file_inst_avl_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> sequencer_reg_file_inst_avl_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> sequencer_reg_file_inst_avl_agent:cp_endofpacket
wire trk_mm_bridge_m0_agent_cp_valid; // trk_mm_bridge_m0_agent:cp_valid -> router:sink_valid
wire [87:0] trk_mm_bridge_m0_agent_cp_data; // trk_mm_bridge_m0_agent:cp_data -> router:sink_data
wire trk_mm_bridge_m0_agent_cp_ready; // router:sink_ready -> trk_mm_bridge_m0_agent:cp_ready
wire trk_mm_bridge_m0_agent_cp_startofpacket; // trk_mm_bridge_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire trk_mm_bridge_m0_agent_cp_endofpacket; // trk_mm_bridge_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire sequencer_scc_mgr_inst_avl_agent_rp_valid; // sequencer_scc_mgr_inst_avl_agent:rp_valid -> router_001:sink_valid
wire [87:0] sequencer_scc_mgr_inst_avl_agent_rp_data; // sequencer_scc_mgr_inst_avl_agent:rp_data -> router_001:sink_data
wire sequencer_scc_mgr_inst_avl_agent_rp_ready; // router_001:sink_ready -> sequencer_scc_mgr_inst_avl_agent:rp_ready
wire sequencer_scc_mgr_inst_avl_agent_rp_startofpacket; // sequencer_scc_mgr_inst_avl_agent:rp_startofpacket -> router_001:sink_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rp_endofpacket; // sequencer_scc_mgr_inst_avl_agent:rp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire [87:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire sequencer_reg_file_inst_avl_agent_rp_valid; // sequencer_reg_file_inst_avl_agent:rp_valid -> router_002:sink_valid
wire [87:0] sequencer_reg_file_inst_avl_agent_rp_data; // sequencer_reg_file_inst_avl_agent:rp_data -> router_002:sink_data
wire sequencer_reg_file_inst_avl_agent_rp_ready; // router_002:sink_ready -> sequencer_reg_file_inst_avl_agent:rp_ready
wire sequencer_reg_file_inst_avl_agent_rp_startofpacket; // sequencer_reg_file_inst_avl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire sequencer_reg_file_inst_avl_agent_rp_endofpacket; // sequencer_reg_file_inst_avl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux_001:sink_valid
wire [87:0] router_002_src_data; // router_002:src_data -> rsp_demux_001:sink_data
wire router_002_src_ready; // rsp_demux_001:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux_001:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_src_valid; // router:src_valid -> trk_mm_bridge_m0_limiter:cmd_sink_valid
wire [87:0] router_src_data; // router:src_data -> trk_mm_bridge_m0_limiter:cmd_sink_data
wire router_src_ready; // trk_mm_bridge_m0_limiter:cmd_sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> trk_mm_bridge_m0_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> trk_mm_bridge_m0_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> trk_mm_bridge_m0_limiter:cmd_sink_endofpacket
wire [87:0] trk_mm_bridge_m0_limiter_cmd_src_data; // trk_mm_bridge_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire trk_mm_bridge_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> trk_mm_bridge_m0_limiter:cmd_src_ready
wire [1:0] trk_mm_bridge_m0_limiter_cmd_src_channel; // trk_mm_bridge_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire trk_mm_bridge_m0_limiter_cmd_src_startofpacket; // trk_mm_bridge_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire trk_mm_bridge_m0_limiter_cmd_src_endofpacket; // trk_mm_bridge_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> trk_mm_bridge_m0_limiter:rsp_sink_valid
wire [87:0] rsp_mux_src_data; // rsp_mux:src_data -> trk_mm_bridge_m0_limiter:rsp_sink_data
wire rsp_mux_src_ready; // trk_mm_bridge_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> trk_mm_bridge_m0_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> trk_mm_bridge_m0_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> trk_mm_bridge_m0_limiter:rsp_sink_endofpacket
wire trk_mm_bridge_m0_limiter_rsp_src_valid; // trk_mm_bridge_m0_limiter:rsp_src_valid -> trk_mm_bridge_m0_agent:rp_valid
wire [87:0] trk_mm_bridge_m0_limiter_rsp_src_data; // trk_mm_bridge_m0_limiter:rsp_src_data -> trk_mm_bridge_m0_agent:rp_data
wire trk_mm_bridge_m0_limiter_rsp_src_ready; // trk_mm_bridge_m0_agent:rp_ready -> trk_mm_bridge_m0_limiter:rsp_src_ready
wire [1:0] trk_mm_bridge_m0_limiter_rsp_src_channel; // trk_mm_bridge_m0_limiter:rsp_src_channel -> trk_mm_bridge_m0_agent:rp_channel
wire trk_mm_bridge_m0_limiter_rsp_src_startofpacket; // trk_mm_bridge_m0_limiter:rsp_src_startofpacket -> trk_mm_bridge_m0_agent:rp_startofpacket
wire trk_mm_bridge_m0_limiter_rsp_src_endofpacket; // trk_mm_bridge_m0_limiter:rsp_src_endofpacket -> trk_mm_bridge_m0_agent:rp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [87:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [87:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [87:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [87:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire [1:0] trk_mm_bridge_m0_limiter_cmd_valid_data; // trk_mm_bridge_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_error
wire sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid; // sequencer_reg_file_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data; // sequencer_reg_file_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> sequencer_reg_file_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) trk_mm_bridge_m0_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (trk_mm_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (trk_mm_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (trk_mm_bridge_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (trk_mm_bridge_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (trk_mm_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (trk_mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (trk_mm_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (trk_mm_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (trk_mm_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (trk_mm_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (trk_mm_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (trk_mm_bridge_m0_address), // avalon_anti_master_0.address
.av_waitrequest (trk_mm_bridge_m0_waitrequest), // .waitrequest
.av_burstcount (trk_mm_bridge_m0_burstcount), // .burstcount
.av_byteenable (trk_mm_bridge_m0_byteenable), // .byteenable
.av_read (trk_mm_bridge_m0_read), // .read
.av_readdata (trk_mm_bridge_m0_readdata), // .readdata
.av_readdatavalid (trk_mm_bridge_m0_readdatavalid), // .readdatavalid
.av_write (trk_mm_bridge_m0_write), // .write
.av_writedata (trk_mm_bridge_m0_writedata), // .writedata
.av_debugaccess (trk_mm_bridge_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_scc_mgr_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_scc_mgr_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_scc_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_scc_mgr_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_scc_mgr_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_scc_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_scc_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_scc_mgr_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_scc_mgr_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_scc_mgr_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_scc_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_scc_mgr_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_scc_mgr_inst_avl_write), // .write
.av_read (sequencer_scc_mgr_inst_avl_read), // .read
.av_readdata (sequencer_scc_mgr_inst_avl_readdata), // .readdata
.av_writedata (sequencer_scc_mgr_inst_avl_writedata), // .writedata
.av_waitrequest (sequencer_scc_mgr_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (18),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_reg_file_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_reg_file_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_reg_file_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_reg_file_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_reg_file_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_reg_file_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_reg_file_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_reg_file_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_reg_file_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_reg_file_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_reg_file_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_reg_file_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_reg_file_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_reg_file_inst_avl_write), // .write
.av_read (sequencer_reg_file_inst_avl_read), // .read
.av_readdata (sequencer_reg_file_inst_avl_readdata), // .readdata
.av_writedata (sequencer_reg_file_inst_avl_writedata), // .writedata
.av_byteenable (sequencer_reg_file_inst_avl_byteenable), // .byteenable
.av_waitrequest (sequencer_reg_file_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (87),
.PKT_ORI_BURST_SIZE_L (85),
.PKT_RESPONSE_STATUS_H (84),
.PKT_RESPONSE_STATUS_L (83),
.PKT_QOS_H (72),
.PKT_QOS_L (72),
.PKT_DATA_SIDEBAND_H (70),
.PKT_DATA_SIDEBAND_L (70),
.PKT_ADDR_SIDEBAND_H (69),
.PKT_ADDR_SIDEBAND_L (69),
.PKT_BURST_TYPE_H (68),
.PKT_BURST_TYPE_L (67),
.PKT_CACHE_H (82),
.PKT_CACHE_L (79),
.PKT_THREAD_ID_H (75),
.PKT_THREAD_ID_L (75),
.PKT_BURST_SIZE_H (66),
.PKT_BURST_SIZE_L (64),
.PKT_TRANS_EXCLUSIVE (59),
.PKT_TRANS_LOCK (58),
.PKT_BEGIN_BURST (71),
.PKT_PROTECTION_H (78),
.PKT_PROTECTION_L (76),
.PKT_BURSTWRAP_H (63),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (73),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (74),
.ST_DATA_W (88),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) trk_mm_bridge_m0_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (trk_mm_bridge_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (trk_mm_bridge_m0_translator_avalon_universal_master_0_write), // .write
.av_read (trk_mm_bridge_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (trk_mm_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (trk_mm_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (trk_mm_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (trk_mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (trk_mm_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (trk_mm_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (trk_mm_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (trk_mm_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (trk_mm_bridge_m0_agent_cp_valid), // cp.valid
.cp_data (trk_mm_bridge_m0_agent_cp_data), // .data
.cp_startofpacket (trk_mm_bridge_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (trk_mm_bridge_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (trk_mm_bridge_m0_agent_cp_ready), // .ready
.rp_valid (trk_mm_bridge_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (trk_mm_bridge_m0_limiter_rsp_src_data), // .data
.rp_channel (trk_mm_bridge_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (trk_mm_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (trk_mm_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (trk_mm_bridge_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (87),
.PKT_ORI_BURST_SIZE_L (85),
.PKT_RESPONSE_STATUS_H (84),
.PKT_RESPONSE_STATUS_L (83),
.PKT_BURST_SIZE_H (66),
.PKT_BURST_SIZE_L (64),
.PKT_TRANS_LOCK (58),
.PKT_BEGIN_BURST (71),
.PKT_PROTECTION_H (78),
.PKT_PROTECTION_L (76),
.PKT_BURSTWRAP_H (63),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (73),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (88),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_scc_mgr_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_scc_mgr_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_scc_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_scc_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_scc_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_scc_mgr_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_scc_mgr_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_scc_mgr_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_scc_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_scc_mgr_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_scc_mgr_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_scc_mgr_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_scc_mgr_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_scc_mgr_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_scc_mgr_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_scc_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_scc_mgr_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_scc_mgr_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_scc_mgr_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (89),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_scc_mgr_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_scc_mgr_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_scc_mgr_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_scc_mgr_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (87),
.PKT_ORI_BURST_SIZE_L (85),
.PKT_RESPONSE_STATUS_H (84),
.PKT_RESPONSE_STATUS_L (83),
.PKT_BURST_SIZE_H (66),
.PKT_BURST_SIZE_L (64),
.PKT_TRANS_LOCK (58),
.PKT_BEGIN_BURST (71),
.PKT_PROTECTION_H (78),
.PKT_PROTECTION_L (76),
.PKT_BURSTWRAP_H (63),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_ADDR_H (53),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (54),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.PKT_TRANS_READ (57),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (73),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (88),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_reg_file_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_reg_file_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_reg_file_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_reg_file_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_reg_file_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_reg_file_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_reg_file_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_reg_file_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_reg_file_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_reg_file_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_reg_file_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_reg_file_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_reg_file_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_reg_file_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_reg_file_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_reg_file_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_reg_file_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_reg_file_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_reg_file_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_reg_file_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_reg_file_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_reg_file_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (89),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_reg_file_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_reg_file_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_reg_file_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_reg_file_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_reg_file_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_reg_file_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
lpddr2_cntrlr_s0_mm_interconnect_1_router router (
.sink_ready (trk_mm_bridge_m0_agent_cp_ready), // sink.ready
.sink_valid (trk_mm_bridge_m0_agent_cp_valid), // .valid
.sink_data (trk_mm_bridge_m0_agent_cp_data), // .data
.sink_startofpacket (trk_mm_bridge_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (trk_mm_bridge_m0_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_1_router_001 router_001 (
.sink_ready (sequencer_scc_mgr_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_scc_mgr_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_scc_mgr_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_scc_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_scc_mgr_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_1_router_001 router_002 (
.sink_ready (sequencer_reg_file_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_reg_file_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_reg_file_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_reg_file_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_reg_file_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (74),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (73),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (55),
.PKT_TRANS_WRITE (56),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (88),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) trk_mm_bridge_m0_limiter (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (trk_mm_bridge_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (trk_mm_bridge_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (trk_mm_bridge_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (trk_mm_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (trk_mm_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (trk_mm_bridge_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (trk_mm_bridge_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (trk_mm_bridge_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (trk_mm_bridge_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (trk_mm_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (trk_mm_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (trk_mm_bridge_m0_limiter_cmd_valid_data) // cmd_valid.data
);
lpddr2_cntrlr_s0_mm_interconnect_1_cmd_demux cmd_demux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (trk_mm_bridge_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (trk_mm_bridge_m0_limiter_cmd_src_channel), // .channel
.sink_data (trk_mm_bridge_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (trk_mm_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (trk_mm_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (trk_mm_bridge_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_1_cmd_mux cmd_mux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_1_rsp_demux rsp_demux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_1_rsp_mux rsp_mux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
lpddr2_cntrlr_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (trk_mm_bridge_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_TB_V
`define SKY130_FD_SC_HVL__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hvl__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 29 20:15:21 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_buffer_register_0_0 -prefix
// system_buffer_register_0_0_ system_buffer_register_0_0_stub.v
// Design : system_buffer_register_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "buffer_register,Vivado 2016.4" *)
module system_buffer_register_0_0(clk, val_in, val_out)
/* synthesis syn_black_box black_box_pad_pin="clk,val_in[31:0],val_out[31:0]" */;
input clk;
input [31:0]val_in;
output [31:0]val_out;
endmodule
|
`timescale 10ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:38:47 03/06/2016
// Design Name: DPWM
// Module Name: C:/Users/Jafet/Documents/Proyectos Dis.Sist.Digitales/I_Proyecto_Laboratorio_Sistemas_Digitales/DPWM_TestBench.v
// Project Name: I_Proyecto_Laboratorio_Sistemas_Digitales
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DPWM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DPWM_TestBench;
// Inputs
reg CLK_FPGA_BOARD;
reg boton_aumentar;
reg boton_disminuir;
reg seleccion_funcion;
reg seleccion_salida;
reg reinicio;
// Outputs
wire BUCK_Gate;
wire Full_Bridge;
wire [3:0] anodos_7seg;
wire [7:0] catodos_7seg;
// Instantiate the Unit Under Test (UUT)
DPWM uut (
.CLK_FPGA_BOARD(CLK_FPGA_BOARD),
.boton_aumentar(boton_aumentar),
.boton_disminuir(boton_disminuir),
.seleccion_funcion(seleccion_funcion),
.seleccion_salida(seleccion_salida),
.reinicio(reinicio),
.BUCK_Gate(BUCK_Gate),
.Full_Bridge(Full_Bridge),
.anodos_7seg(anodos_7seg),
.catodos_7seg(catodos_7seg)
);
initial
begin
// Initialize Inputs
CLK_FPGA_BOARD = 0;
boton_aumentar = 0;
boton_disminuir = 0;
seleccion_funcion = 0;
seleccion_salida = 0;
reinicio = 0;
end
// Wait 100 ns for global reset to finish
//#100;
//this process block sets up the free running clock
initial
begin
CLK_FPGA_BOARD = 0;
forever #5 CLK_FPGA_BOARD = ~CLK_FPGA_BOARD;
end
// Add stimulus here
initial
begin
reinicio = 1;
boton_aumentar = 0;
boton_disminuir = 0;
seleccion_funcion = 0;
seleccion_salida = 0;
#10
reinicio = 0;
#10
reinicio = 0;
boton_aumentar = 1;
#50
boton_aumentar = 0;
#20
boton_aumentar = 1;
#20
boton_aumentar = 0;
boton_disminuir = 0;
/*
seleccion_funcion = 0;
seleccion_salida = 0;
#200
*/
//#1000000$stop;
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
reg r_change;
reg [width-1:0] r_test_expr;
reg r_state;
parameter WIN_CHANGE_START = 1'b0;
parameter WIN_CHANGE_CHECK = 1'b1;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
wire valid_end_event;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
assign valid_end_event = ~(end_event^end_event);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=WIN_CHANGE_START;
r_change=1'b0;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
case (r_state)
WIN_CHANGE_START: begin
if (start_event == 1'b1) begin
r_change <= 1'b0;
r_state <= WIN_CHANGE_CHECK;
r_test_expr <= test_expr;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_start_event == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
WIN_CHANGE_CHECK: begin
if (r_test_expr != test_expr) begin
r_change <= 1'b1;
end
// go to start state on last check
if (end_event == 1'b1) begin
r_state <= WIN_CHANGE_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window covered");
end
end
`endif // OVL_COVER_ON
// Check that the property is true
`ifdef OVL_ASSERT_ON
if ((r_change != 1'b1) && (r_test_expr == test_expr)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression has not changed value before window is closed");
end
`endif // OVL_ASSERT_ON
end
r_test_expr <= test_expr;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (valid_end_event == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"end_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
endcase
end
else begin
r_state<=WIN_CHANGE_START;
r_change<=1'b0;
r_test_expr <= {width{1'b0}};
end
end // always
`endif // OVL_SHARED_CODE
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/*
* File : MIPS_Parameters.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ([email protected])
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 26-May-2012 GEA Release version.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Provides a language abstraction for the MIPS32-specific op-codes and
* the processor-specific datapath, hazard, and exception bits which
* control the processor. These definitions are used extensively
* throughout the processor HDL modules.
*/
/*** Exception Vector Locations ***
When the CPU powers up or is reset, it will begin execution at 'EXC_Vector_Base_Reset'.
All other exceptions are the sum of a base address and offset:
- The base address is either a bootstrap or normal value. It is controlled by
the 'BEV' bit in the CP0 'Status' register. Both base addresses can be mapped to
the same location.
- The offset address is either a standard offset (which is always used for
non-interrupt general exceptions in this processor because it lacks TLB Refill
and Cache errors), or a special interrupt-only offset for interrupts, which is
enabled with the 'IV' bit in the CP0 'Cause' register.
Current Setup:
General exceptions go to 0x0. Interrupts go to 0x8. Booting starts at 0x10.
*/
`define EXC_Vector_Base_Reset 32'h0000_0010 // MIPS Standard is 0xBFC0_0000
`define EXC_Vector_Base_Other_NoBoot 32'h0000_0000 // MIPS Standard is 0x8000_0000
`define EXC_Vector_Base_Other_Boot 32'h0000_0000 // MIPS Standard is 0xBFC0_0200
`define EXC_Vector_Offset_General 32'h0000_0000 // MIPS Standard is 0x0000_0180
`define EXC_Vector_Offset_Special 32'h0000_0008 // MIPS Standard is 0x0000_0200
/*** Kernel/User Memory Areas ***
Kernel memory starts at address 0x0. User memory starts at 'UMem_Lower' and extends to
the end of the address space.
A distinction is made to protect against accesses to kernel memory while the processor
is in user mode. Lacking MMU hardware, these addresses are physical, not virtual.
This simple two-part division of the address space can be extended almost arbitrarily
in the Data Memory Controller. Note that there is currently no user/kernel space check
for the Instruction Memory, because it is assumed that instructions are in the kernel space.
*/
`define UMem_Lower 32'h08000000
/*** Processor Endianness ***
The MIPS Configuration Register (CP0 Register 16 Select 0) specifies the processor's
endianness. A processor in user mode may switch to reverse endianness, which will be
the opposite of this `define.
*/
`define Big_Endian 1'b1
/*** Encodings for MIPS32 Release 1 Architecture ***/
/* Op Code Categories */
`define Op_Type_R 6'b00_0000 // Standard R-Type instructions
`define Op_Type_R2 6'b01_1100 // Extended R-Like instructions
`define Op_Type_BI 6'b00_0001 // Branch/Trap extended instructions
`define Op_Type_CP0 6'b01_0000 // Coprocessor 0 instructions
`define Op_Type_CP1 6'b01_0001 // Coprocessor 1 instructions (not implemented)
`define Op_Type_CP2 6'b01_0010 // Coprocessor 2 instructions (not implemented)
`define Op_Type_CP3 6'b01_0011 // Coprocessor 3 instructions (not implemented)
// --------------------------------------
`define Op_Add `Op_Type_R
`define Op_Addi 6'b00_1000
`define Op_Addiu 6'b00_1001
`define Op_Addu `Op_Type_R
`define Op_And `Op_Type_R
`define Op_Andi 6'b00_1100
`define Op_Beq 6'b00_0100
`define Op_Bgez `Op_Type_BI
`define Op_Bgezal `Op_Type_BI
`define Op_Bgtz 6'b00_0111
`define Op_Blez 6'b00_0110
`define Op_Bltz `Op_Type_BI
`define Op_Bltzal `Op_Type_BI
`define Op_Bne 6'b00_0101
`define Op_Break `Op_Type_R
`define Op_Clo `Op_Type_R2
`define Op_Clz `Op_Type_R2
`define Op_Div `Op_Type_R
`define Op_Divu `Op_Type_R
`define Op_Eret `Op_Type_CP0
`define Op_J 6'b00_0010
`define Op_Jal 6'b00_0011
`define Op_Jalr `Op_Type_R
`define Op_Jr `Op_Type_R
`define Op_Lb 6'b10_0000
`define Op_Lbu 6'b10_0100
`define Op_Lh 6'b10_0001
`define Op_Lhu 6'b10_0101
`define Op_Ll 6'b11_0000
`define Op_Lui 6'b00_1111
`define Op_Lw 6'b10_0011
`define Op_Lwl 6'b10_0010
`define Op_Lwr 6'b10_0110
`define Op_Madd `Op_Type_R2
`define Op_Maddu `Op_Type_R2
`define Op_Mfc0 `Op_Type_CP0
`define Op_Mfhi `Op_Type_R
`define Op_Mflo `Op_Type_R
`define Op_Movn `Op_Type_R
`define Op_Movz `Op_Type_R
`define Op_Msub `Op_Type_R2
`define Op_Msubu `Op_Type_R2
`define Op_Mtc0 `Op_Type_CP0
`define Op_Mthi `Op_Type_R
`define Op_Mtlo `Op_Type_R
`define Op_Mul `Op_Type_R2
`define Op_Mult `Op_Type_R
`define Op_Multu `Op_Type_R
`define Op_Nor `Op_Type_R
`define Op_Or `Op_Type_R
`define Op_Ori 6'b00_1101
`define Op_Pref 6'b11_0011 // Prefetch does nothing in this implementation.
`define Op_Sb 6'b10_1000
`define Op_Sc 6'b11_1000
`define Op_Sh 6'b10_1001
`define Op_Sll `Op_Type_R
`define Op_Sllv `Op_Type_R
`define Op_Slt `Op_Type_R
`define Op_Slti 6'b00_1010
`define Op_Sltiu 6'b00_1011
`define Op_Sltu `Op_Type_R
`define Op_Sra `Op_Type_R
`define Op_Srav `Op_Type_R
`define Op_Srl `Op_Type_R
`define Op_Srlv `Op_Type_R
`define Op_Sub `Op_Type_R
`define Op_Subu `Op_Type_R
`define Op_Sw 6'b10_1011
`define Op_Swl 6'b10_1010
`define Op_Swr 6'b10_1110
`define Op_Syscall `Op_Type_R
`define Op_Teq `Op_Type_R
`define Op_Teqi `Op_Type_BI
`define Op_Tge `Op_Type_R
`define Op_Tgei `Op_Type_BI
`define Op_Tgeiu `Op_Type_BI
`define Op_Tgeu `Op_Type_R
`define Op_Tlt `Op_Type_R
`define Op_Tlti `Op_Type_BI
`define Op_Tltiu `Op_Type_BI
`define Op_Tltu `Op_Type_R
`define Op_Tne `Op_Type_R
`define Op_Tnei `Op_Type_BI
`define Op_Xor `Op_Type_R
`define Op_Xori 6'b00_1110
/* Op Code Rt fields for Branches & Traps */
`define OpRt_Bgez 5'b00001
`define OpRt_Bgezal 5'b10001
`define OpRt_Bltz 5'b00000
`define OpRt_Bltzal 5'b10000
`define OpRt_Teqi 5'b01100
`define OpRt_Tgei 5'b01000
`define OpRt_Tgeiu 5'b01001
`define OpRt_Tlti 5'b01010
`define OpRt_Tltiu 5'b01011
`define OpRt_Tnei 5'b01110
/* Op Code Rs fields for Coprocessors */
`define OpRs_MF 5'b00000
`define OpRs_MT 5'b00100
/* Special handling for ERET */
`define OpRs_ERET 5'b10000
`define Funct_ERET 6'b011000
/* Function Codes for R-Type Op Codes */
`define Funct_Add 6'b10_0000
`define Funct_Addu 6'b10_0001
`define Funct_And 6'b10_0100
`define Funct_Break 6'b00_1101
`define Funct_Clo 6'b10_0001 // same as Addu
`define Funct_Clz 6'b10_0000 // same as Add
`define Funct_Div 6'b01_1010
`define Funct_Divu 6'b01_1011
`define Funct_Jr 6'b00_1000
`define Funct_Jalr 6'b00_1001
`define Funct_Madd 6'b00_0000
`define Funct_Maddu 6'b00_0001
`define Funct_Mfhi 6'b01_0000
`define Funct_Mflo 6'b01_0010
`define Funct_Movn 6'b00_1011
`define Funct_Movz 6'b00_1010
`define Funct_Msub 6'b00_0100 // same as Sllv
`define Funct_Msubu 6'b00_0101
`define Funct_Mthi 6'b01_0001
`define Funct_Mtlo 6'b01_0011
`define Funct_Mul 6'b00_0010 // same as Srl
`define Funct_Mult 6'b01_1000
`define Funct_Multu 6'b01_1001
`define Funct_Nor 6'b10_0111
`define Funct_Or 6'b10_0101
`define Funct_Sll 6'b00_0000
`define Funct_Sllv 6'b00_0100
`define Funct_Slt 6'b10_1010
`define Funct_Sltu 6'b10_1011
`define Funct_Sra 6'b00_0011
`define Funct_Srav 6'b00_0111
`define Funct_Srl 6'b00_0010
`define Funct_Srlv 6'b00_0110
`define Funct_Sub 6'b10_0010
`define Funct_Subu 6'b10_0011
`define Funct_Syscall 6'b00_1100
`define Funct_Teq 6'b11_0100
`define Funct_Tge 6'b11_0000
`define Funct_Tgeu 6'b11_0001
`define Funct_Tlt 6'b11_0010
`define Funct_Tltu 6'b11_0011
`define Funct_Tne 6'b11_0110
`define Funct_Xor 6'b10_0110
/* ALU Operations (Implementation) */
`define AluOp_Add 5'd1
`define AluOp_Addu 5'd0
`define AluOp_And 5'd2
`define AluOp_Clo 5'd3
`define AluOp_Clz 5'd4
`define AluOp_Div 5'd5
`define AluOp_Divu 5'd6
`define AluOp_Madd 5'd7
`define AluOp_Maddu 5'd8
`define AluOp_Mfhi 5'd9
`define AluOp_Mflo 5'd10
`define AluOp_Msub 5'd13
`define AluOp_Msubu 5'd14
`define AluOp_Mthi 5'd11
`define AluOp_Mtlo 5'd12
`define AluOp_Mul 5'd15
`define AluOp_Mult 5'd16
`define AluOp_Multu 5'd17
`define AluOp_Nor 5'd18
`define AluOp_Or 5'd19
`define AluOp_Sll 5'd20
`define AluOp_Sllc 5'd21 // Move this if another AluOp is needed
`define AluOp_Sllv 5'd22
`define AluOp_Slt 5'd23
`define AluOp_Sltu 5'd24
`define AluOp_Sra 5'd25
`define AluOp_Srav 5'd26
`define AluOp_Srl 5'd27
`define AluOp_Srlv 5'd28
`define AluOp_Sub 5'd29
`define AluOp_Subu 5'd30
`define AluOp_Xor 5'd31
// Movc:10->11, Trap:9->10, TrapCond:8->9, RegDst:7->8
/*** Datapath ***
All Signals are Active High. Branching and Jump signals (determined by "PCSrc"),
as well as ALU operation signals ("ALUOp") are handled by the controller and are not found here.
Bit Name Description
------------------------------
15: PCSrc (Instruction Type)
14: 11: Instruction is Jump to Register
10: Instruction is Branch
01: Instruction is Jump to Immediate
00: Instruction does not branch nor jump
13: Link (Link on Branch/Jump)
------------------------------
12: ALUSrc (ALU Source) [0=ALU input B is 2nd register file output; 1=Immediate value]
11: Movc (Conditional Move)
10: Trap (Trap Instruction)
9 : TrapCond (Trap Condition) [0=ALU result is 0; 1=ALU result is not 0]
8 : RegDst (Register File Target) [0=Rt field; 1=Rd field]
------------------------------
7 : LLSC (Load Linked or Store Conditional)
6 : MemRead (Data Memory Read)
5 : MemWrite (Data Memory Write)
4 : MemHalf (Half Word Memory Access)
3 : MemByte (Byte size Memory Access)
2 : MemSignExtend (Sign Extend Read Memory) [0=Zero Extend; 1=Sign Extend]
------------------------------
1 : RegWrite (Register File Write)
0 : MemtoReg (Memory to Register) [0=Register File write data is ALU output; 1=Is Data Memory]
------------------------------
*/
`define DP_None 16'b000_00000_000000_00 // Instructions which require nothing of the main datapath.
`define DP_RType 16'b000_00001_000000_10 // Standard R-Type
`define DP_IType 16'b000_10000_000000_10 // Standard I-Type
`define DP_Branch 16'b100_00000_000000_00 // Standard Branch
`define DP_BranchLink 16'b101_00000_000000_10 // Branch and Link
`define DP_HiLoWr 16'b000_00000_000000_00 // Write to Hi/Lo ALU register (Div,Divu,Mult,Multu,Mthi,Mtlo). Currently 'DP_None'.
`define DP_Jump 16'b010_00000_000000_00 // Standard Jump
`define DP_JumpLink 16'b011_00000_000000_10 // Jump and Link
`define DP_JumpLinkReg 16'b111_00000_000000_10 // Jump and Link Register
`define DP_JumpReg 16'b110_00000_000000_00 // Jump Register
`define DP_LoadByteS 16'b000_10000_010011_11 // Load Byte Signed
`define DP_LoadByteU 16'b000_10000_010010_11 // Load Byte Unsigned
`define DP_LoadHalfS 16'b000_10000_010101_11 // Load Half Signed
`define DP_LoadHalfU 16'b000_10000_010100_11 // Load Half Unsigned
`define DP_LoadWord 16'b000_10000_010000_11 // Load Word
`define DP_ExtWrRt 16'b000_00000_000000_10 // A DP-external write to Rt
`define DP_ExtWrRd 16'b000_00001_000000_10 // A DP-external write to Rd
`define DP_Movc 16'b000_01001_000000_10 // Conditional Move
`define DP_LoadLinked 16'b000_10000_110000_11 // Load Linked
`define DP_StoreCond 16'b000_10000_101000_11 // Store Conditional
`define DP_StoreByte 16'b000_10000_001010_00 // Store Byte
`define DP_StoreHalf 16'b000_10000_001100_00 // Store Half
`define DP_StoreWord 16'b000_10000_001000_00 // Store Word
`define DP_TrapRegCNZ 16'b000_00110_000000_00 // Trap using Rs and Rt, non-zero ALU (Tlt, Tltu, Tne)
`define DP_TrapRegCZ 16'b000_00100_000000_00 // Trap using RS and Rt, zero ALU (Teq, Tge, Tgeu)
`define DP_TrapImmCNZ 16'b000_10110_000000_00 // Trap using Rs and Imm, non-zero ALU (Tlti, Tltiu, Tnei)
`define DP_TrapImmCZ 16'b000_10100_000000_00 // Trap using Rs and Imm, zero ALU (Teqi, Tgei, Tgeiu)
//--------------------------------------------------------
`define DP_Add `DP_RType
`define DP_Addi `DP_IType
`define DP_Addiu `DP_IType
`define DP_Addu `DP_RType
`define DP_And `DP_RType
`define DP_Andi `DP_IType
`define DP_Beq `DP_Branch
`define DP_Bgez `DP_Branch
`define DP_Bgezal `DP_BranchLink
`define DP_Bgtz `DP_Branch
`define DP_Blez `DP_Branch
`define DP_Bltz `DP_Branch
`define DP_Bltzal `DP_BranchLink
`define DP_Bne `DP_Branch
`define DP_Break `DP_None
`define DP_Clo `DP_RType
`define DP_Clz `DP_RType
`define DP_Div `DP_HiLoWr
`define DP_Divu `DP_HiLoWr
`define DP_Eret `DP_None
`define DP_J `DP_Jump
`define DP_Jal `DP_JumpLink
`define DP_Jalr `DP_JumpLinkReg
`define DP_Jr `DP_JumpReg
`define DP_Lb `DP_LoadByteS
`define DP_Lbu `DP_LoadByteU
`define DP_Lh `DP_LoadHalfS
`define DP_Lhu `DP_LoadHalfU
`define DP_Ll `DP_LoadLinked
`define DP_Lui `DP_IType
`define DP_Lw `DP_LoadWord
`define DP_Lwl `DP_LoadWord
`define DP_Lwr `DP_LoadWord
`define DP_Madd `DP_HiLoWr
`define DP_Maddu `DP_HiLoWr
`define DP_Mfc0 `DP_ExtWrRt
`define DP_Mfhi `DP_ExtWrRd
`define DP_Mflo `DP_ExtWrRd
`define DP_Movn `DP_Movc
`define DP_Movz `DP_Movc
`define DP_Msub `DP_HiLoWr
`define DP_Msubu `DP_HiLoWr
`define DP_Mtc0 `DP_None
`define DP_Mthi `DP_HiLoWr
`define DP_Mtlo `DP_HiLoWr
`define DP_Mul `DP_RType
`define DP_Mult `DP_HiLoWr
`define DP_Multu `DP_HiLoWr
`define DP_Nor `DP_RType
`define DP_Or `DP_RType
`define DP_Ori `DP_IType
`define DP_Pref `DP_None // Not Implemented
`define DP_Sb `DP_StoreByte
`define DP_Sc `DP_StoreCond
`define DP_Sh `DP_StoreHalf
`define DP_Sll `DP_RType
`define DP_Sllv `DP_RType
`define DP_Slt `DP_RType
`define DP_Slti `DP_IType
`define DP_Sltiu `DP_IType
`define DP_Sltu `DP_RType
`define DP_Sra `DP_RType
`define DP_Srav `DP_RType
`define DP_Srl `DP_RType
`define DP_Srlv `DP_RType
`define DP_Sub `DP_RType
`define DP_Subu `DP_RType
`define DP_Sw `DP_StoreWord
`define DP_Swl `DP_StoreWord
`define DP_Swr `DP_StoreWord
`define DP_Syscall `DP_None
`define DP_Teq `DP_TrapRegCZ
`define DP_Teqi `DP_TrapImmCZ
`define DP_Tge `DP_TrapRegCZ
`define DP_Tgei `DP_TrapImmCZ
`define DP_Tgeiu `DP_TrapImmCZ
`define DP_Tgeu `DP_TrapRegCZ
`define DP_Tlt `DP_TrapRegCNZ
`define DP_Tlti `DP_TrapImmCNZ
`define DP_Tltiu `DP_TrapImmCNZ
`define DP_Tltu `DP_TrapRegCNZ
`define DP_Tne `DP_TrapRegCNZ
`define DP_Tnei `DP_TrapImmCNZ
`define DP_Xor `DP_RType
`define DP_Xori `DP_IType
/*** Exception Information ***
All signals are Active High.
Bit Meaning
------------
2: Instruction can cause exceptions in ID
1: Instruction can cause exceptions in EX
0: Instruction can cause exceptions in MEM
*/
`define EXC_None 3'b000
`define EXC_ID 3'b100
`define EXC_EX 3'b010
`define EXC_MEM 3'b001
//--------------------------------
`define EXC_Add `EXC_EX
`define EXC_Addi `EXC_EX
`define EXC_Addiu `EXC_None
`define EXC_Addu `EXC_None
`define EXC_And `EXC_None
`define EXC_Andi `EXC_None
`define EXC_Beq `EXC_None
`define EXC_Bgez `EXC_None
`define EXC_Bgezal `EXC_None
`define EXC_Bgtz `EXC_None
`define EXC_Blez `EXC_None
`define EXC_Bltz `EXC_None
`define EXC_Bltzal `EXC_None
`define EXC_Bne `EXC_None
`define EXC_Break `EXC_ID
`define EXC_Clo `EXC_None
`define EXC_Clz `EXC_None
`define EXC_Div `EXC_None
`define EXC_Divu `EXC_None
`define EXC_Eret `EXC_ID
`define EXC_J `EXC_None
`define EXC_Jal `EXC_None
`define EXC_Jalr `EXC_None
`define EXC_Jr `EXC_None
`define EXC_Lb `EXC_MEM
`define EXC_Lbu `EXC_MEM
`define EXC_Lh `EXC_MEM
`define EXC_Lhu `EXC_MEM
`define EXC_Ll `EXC_MEM
`define EXC_Lui `EXC_None
`define EXC_Lw `EXC_MEM
`define EXC_Lwl `EXC_MEM
`define EXC_Lwr `EXC_MEM
`define EXC_Madd `EXC_None
`define EXC_Maddu `EXC_None
`define EXC_Mfc0 `EXC_ID
`define EXC_Mfhi `EXC_None
`define EXC_Mflo `EXC_None
`define EXC_Movn `EXC_None
`define EXC_Movz `EXC_None
`define EXC_Msub `EXC_None
`define EXC_Msubu `EXC_None
`define EXC_Mtc0 `EXC_ID
`define EXC_Mthi `EXC_None
`define EXC_Mtlo `EXC_None
`define EXC_Mul `EXC_None
`define EXC_Mult `EXC_None
`define EXC_Multu `EXC_None
`define EXC_Nor `EXC_None
`define EXC_Or `EXC_None
`define EXC_Ori `EXC_None
`define EXC_Pref `EXC_None // XXX
`define EXC_Sb `EXC_MEM
`define EXC_Sc `EXC_MEM
`define EXC_Sh `EXC_MEM
`define EXC_Sll `EXC_None
`define EXC_Sllv `EXC_None
`define EXC_Slt `EXC_None
`define EXC_Slti `EXC_None
`define EXC_Sltiu `EXC_None
`define EXC_Sltu `EXC_None
`define EXC_Sra `EXC_None
`define EXC_Srav `EXC_None
`define EXC_Srl `EXC_None
`define EXC_Srlv `EXC_None
`define EXC_Sub `EXC_EX
`define EXC_Subu `EXC_None
`define EXC_Sw `EXC_MEM
`define EXC_Swl `EXC_MEM
`define EXC_Swr `EXC_MEM
`define EXC_Syscall `EXC_ID
`define EXC_Teq `EXC_MEM
`define EXC_Teqi `EXC_MEM
`define EXC_Tge `EXC_MEM
`define EXC_Tgei `EXC_MEM
`define EXC_Tgeiu `EXC_MEM
`define EXC_Tgeu `EXC_MEM
`define EXC_Tlt `EXC_MEM
`define EXC_Tlti `EXC_MEM
`define EXC_Tltiu `EXC_MEM
`define EXC_Tltu `EXC_MEM
`define EXC_Tne `EXC_MEM
`define EXC_Tnei `EXC_MEM
`define EXC_Xor `EXC_None
`define EXC_Xori `EXC_None
/*** Hazard & Forwarding Datapath ***
All signals are Active High.
Bit Meaning
------------
7: Wants Rs by ID
6: Needs Rs by ID
5: Wants Rt by ID
4: Needs Rt by ID
3: Wants Rs by EX
2: Needs Rs by EX
1: Wants Rt by EX
0: Needs Rt by EX
*/
`define HAZ_Nothing 8'b00000000 // Jumps, Lui, Mfhi/lo, special, etc.
`define HAZ_IDRsIDRt 8'b11110000 // Beq, Bne, Traps
`define HAZ_IDRs 8'b11000000 // Most branches, Jumps to registers
`define HAZ_IDRt 8'b00110000 // Mtc0
`define HAZ_IDRtEXRs 8'b10111100 // Movn, Movz
`define HAZ_EXRsEXRt 8'b10101111 // Many R-Type ops
`define HAZ_EXRs 8'b10001100 // Immediates: Loads, Clo/z, Mthi/lo, etc.
`define HAZ_EXRsWRt 8'b10101110 // Stores
`define HAZ_EXRt 8'b00100011 // Shifts using Shamt field
//-----------------------------------------
`define HAZ_Add `HAZ_EXRsEXRt
`define HAZ_Addi `HAZ_EXRs
`define HAZ_Addiu `HAZ_EXRs
`define HAZ_Addu `HAZ_EXRsEXRt
`define HAZ_And `HAZ_EXRsEXRt
`define HAZ_Andi `HAZ_EXRs
`define HAZ_Beq `HAZ_IDRsIDRt
`define HAZ_Bgez `HAZ_IDRs
`define HAZ_Bgezal `HAZ_IDRs
`define HAZ_Bgtz `HAZ_IDRs
`define HAZ_Blez `HAZ_IDRs
`define HAZ_Bltz `HAZ_IDRs
`define HAZ_Bltzal `HAZ_IDRs
`define HAZ_Bne `HAZ_IDRsIDRt
`define HAZ_Break `HAZ_Nothing
`define HAZ_Clo `HAZ_EXRs
`define HAZ_Clz `HAZ_EXRs
`define HAZ_Div `HAZ_EXRsEXRt
`define HAZ_Divu `HAZ_EXRsEXRt
`define HAZ_Eret `HAZ_Nothing
`define HAZ_J `HAZ_Nothing
`define HAZ_Jal `HAZ_Nothing
`define HAZ_Jalr `HAZ_IDRs
`define HAZ_Jr `HAZ_IDRs
`define HAZ_Lb `HAZ_EXRs
`define HAZ_Lbu `HAZ_EXRs
`define HAZ_Lh `HAZ_EXRs
`define HAZ_Lhu `HAZ_EXRs
`define HAZ_Ll `HAZ_EXRs
`define HAZ_Lui `HAZ_Nothing
`define HAZ_Lw `HAZ_EXRs
`define HAZ_Lwl `HAZ_EXRsEXRt
`define HAZ_Lwr `HAZ_EXRsEXRt
`define HAZ_Madd `HAZ_EXRsEXRt
`define HAZ_Maddu `HAZ_EXRsEXRt
`define HAZ_Mfc0 `HAZ_Nothing
`define HAZ_Mfhi `HAZ_Nothing
`define HAZ_Mflo `HAZ_Nothing
`define HAZ_Movn `HAZ_IDRtEXRs
`define HAZ_Movz `HAZ_IDRtEXRs
`define HAZ_Msub `HAZ_EXRsEXRt
`define HAZ_Msubu `HAZ_EXRsEXRt
`define HAZ_Mtc0 `HAZ_IDRt
`define HAZ_Mthi `HAZ_EXRs
`define HAZ_Mtlo `HAZ_EXRs
`define HAZ_Mul `HAZ_EXRsEXRt
`define HAZ_Mult `HAZ_EXRsEXRt
`define HAZ_Multu `HAZ_EXRsEXRt
`define HAZ_Nor `HAZ_EXRsEXRt
`define HAZ_Or `HAZ_EXRsEXRt
`define HAZ_Ori `HAZ_EXRs
`define HAZ_Pref `HAZ_Nothing // XXX
`define HAZ_Sb `HAZ_EXRsWRt
`define HAZ_Sc `HAZ_EXRsWRt
`define HAZ_Sh `HAZ_EXRsWRt
`define HAZ_Sll `HAZ_EXRt
`define HAZ_Sllv `HAZ_EXRsEXRt
`define HAZ_Slt `HAZ_EXRsEXRt
`define HAZ_Slti `HAZ_EXRs
`define HAZ_Sltiu `HAZ_EXRs
`define HAZ_Sltu `HAZ_EXRsEXRt
`define HAZ_Sra `HAZ_EXRt
`define HAZ_Srav `HAZ_EXRsEXRt
`define HAZ_Srl `HAZ_EXRt
`define HAZ_Srlv `HAZ_EXRsEXRt
`define HAZ_Sub `HAZ_EXRsEXRt
`define HAZ_Subu `HAZ_EXRsEXRt
`define HAZ_Sw `HAZ_EXRsWRt
`define HAZ_Swl `HAZ_EXRsWRt
`define HAZ_Swr `HAZ_EXRsWRt
`define HAZ_Syscall `HAZ_Nothing
`define HAZ_Teq `HAZ_EXRsEXRt
`define HAZ_Teqi `HAZ_EXRs
`define HAZ_Tge `HAZ_EXRsEXRt
`define HAZ_Tgei `HAZ_EXRs
`define HAZ_Tgeiu `HAZ_EXRs
`define HAZ_Tgeu `HAZ_EXRsEXRt
`define HAZ_Tlt `HAZ_EXRsEXRt
`define HAZ_Tlti `HAZ_EXRs
`define HAZ_Tltiu `HAZ_EXRs
`define HAZ_Tltu `HAZ_EXRsEXRt
`define HAZ_Tne `HAZ_EXRsEXRt
`define HAZ_Tnei `HAZ_EXRs
`define HAZ_Xor `HAZ_EXRsEXRt
`define HAZ_Xori `HAZ_EXRs
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_BLACKBOX_V
`define SKY130_FD_SC_LS__O32A_BLACKBOX_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_BLACKBOX_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_faddsub(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input sub,
input valid_i,
output [31:0] r,
output reg valid_o
);
wire a_sign = a[31];
wire [7:0] a_expn = a[30:23];
wire [22:0] a_mant = a[22:0];
wire b_sign = b[31] ^ sub;
wire [7:0] b_expn = b[30:23];
wire [22:0] b_mant = b[22:0];
/* Stage 1 */
reg s1_iszero; /* one or both of the operands is zero */
reg s1_sign; /* sign of the result */
reg s1_issub; /* shall we do a subtraction or an addition */
reg [7:0] s1_expn_max; /* exponent of the bigger number (abs value) */
reg [7:0] s1_expn_diff; /* difference with the exponent of the smaller number (abs value) */
reg [22:0] s1_mant_max; /* mantissa of the bigger number (abs value) */
reg [22:0] s1_mant_min; /* mantissa of the smaller number (abs value) */
reg s1_valid;
/* local signals ; explicitly share the comparators */
wire expn_compare = a_expn > b_expn;
wire expn_equal = a_expn == b_expn;
wire mant_compare = a_mant > b_mant;
always @(posedge sys_clk) begin
if(alu_rst)
s1_valid <= 1'b0;
else
s1_valid <= valid_i;
s1_issub <= a_sign ^ b_sign;
if(expn_compare)
/* |b| <= |a| */
s1_sign <= a_sign;
else begin
if(expn_equal) begin
if(mant_compare)
/* |b| <= |a| */
s1_sign <= a_sign;
else
/* |b| > |a| */
s1_sign <= b_sign;
end else
/* |b| > |a| */
s1_sign <= b_sign;
end
if(expn_compare) begin
s1_expn_max <= a_expn;
s1_expn_diff <= a_expn - b_expn;
end else begin
s1_expn_max <= b_expn;
s1_expn_diff <= b_expn - a_expn;
end
if(expn_equal) begin
if(mant_compare) begin
s1_mant_max <= a_mant;
s1_mant_min <= b_mant;
end else begin
s1_mant_max <= b_mant;
s1_mant_min <= a_mant;
end
end else begin
if(expn_compare) begin
s1_mant_max <= a_mant;
s1_mant_min <= b_mant;
end else begin
s1_mant_max <= b_mant;
s1_mant_min <= a_mant;
end
end
s1_iszero <= (a_expn == 8'd0)|(b_expn == 8'd0);
end
/* Stage 2 */
reg s2_sign;
reg [7:0] s2_expn;
reg [25:0] s2_mant;
reg s2_valid;
/* local signals */
wire [24:0] max_expanded = {1'b1, s1_mant_max, 1'b0}; /* 1 guard digit */
wire [24:0] min_expanded = {1'b1, s1_mant_min, 1'b0} >> s1_expn_diff;
always @(posedge sys_clk) begin
if(alu_rst)
s2_valid <= 1'b0;
else
s2_valid <= s1_valid;
s2_sign <= s1_sign;
s2_expn <= s1_expn_max;
if(s1_iszero)
s2_mant <= {2'b01, s1_mant_max, 1'b0};
else begin
if(s1_issub)
s2_mant <= max_expanded - min_expanded;
else
s2_mant <= max_expanded + min_expanded;
end
end
/* Stage 3 */
reg s3_sign;
reg [7:0] s3_expn;
reg [25:0] s3_mant;
wire [4:0] clz;
pfpu_clz32 clz32(
.d({s2_mant, 6'bx}),
.clz(clz)
);
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= s2_valid;
s3_sign <= s2_sign;
s3_mant <= s2_mant << clz;
s3_expn <= s2_expn - clz + 8'd1;
end
assign r = {s3_sign, s3_expn, s3_mant[24:2]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_TB_V
`define SKY130_FD_SC_MS__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ms__tap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_TB_V
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module gpu(
input wire clr,
input wire clka,
input wire clkb,
input wire ena,
input wire wea,
input wire [12:0] addra,
input wire [15:0] dina,
output wire [15:0] douta,
output wire [2:0] vgaRed,
output wire [2:0] vgaGreen,
output wire [2:1] vgaBlue,
output wire Hsync,
output wire Vsync
);
reg [23:0] BlinkCount;
wire cBlink;
assign cBlink = BlinkCount[23];
/* vgabase_1024x768 SyncGen*/
wire pl0_xsync, pl0_ysync, pl0_vidon;
wire [11:0] pl0_xpos, pl0_ypos;
vgabase Pipeline0(.clk(clkb), .clr(clr),
.hsync(pl0_xsync), .vsync(pl0_ysync),
.hc(pl0_xpos), .vc(pl0_ypos), .vidon(pl0_vidon)
);
/* vgamem_128x48 CharMemoryAccess */
wire [7:0] fontcolor;
wire [7:0] backcolor;
wire [6:0] char;
wire Blink;
wire pl1_xsync, pl1_ysync, pl1_vidon;
wire [11:0] pl1_xpos, pl1_ypos;
vgamem Pipeline1( .clr(clr), .clka(clka), .clkb(clkb),
.ena(ena), .wea(wea), .addra(addra), .dina(dina), .douta(douta),
.char(char), .fontcolor(fontcolor), .backcolor(backcolor), .Blink(Blink),
.xsync(pl0_xsync), .ysync(pl0_ysync),
.xpos(pl0_xpos), .ypos(pl0_ypos), .valid(pl0_vidon),
.hsync(pl1_xsync), .vsync(pl1_ysync),
.hc(pl1_xpos), .vc(pl1_ypos), .vidon(pl1_vidon)
);
/* vgachar_128x48 CharFontGen*/
vgachar Pipeline2(.clk(clkb), .clr(clr), .cBlink(cBlink),
.char(char), .fontcolor(fontcolor), .backcolor(backcolor), .Blink(Blink),
.xsync(pl1_xsync), .ysync(pl1_ysync),
.xpos(pl1_xpos), .ypos(pl1_ypos), .valid(pl1_vidon),
.hsync(Hsync), .vsync(Vsync),
.vgaRed(vgaRed), .vgaGreen(vgaGreen), .vgaBlue(vgaBlue)
);
always @(posedge clkb or posedge clr) begin
if(clr == 1)
BlinkCount <= 0;
else
BlinkCount <= BlinkCount + 1'b1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__BUFBUF_BEHAVIORAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFBUF_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_TB_V
`define SKY130_FD_SC_HD__O21BA_TB_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ba.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__o21ba dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_TB_V
|
module KeyboardReader (
input wire rst,
input wire clk,
inout wire ps2CLK,
inout wire ps2DATA,
output reg[8:0] pressedKey,
output reg pressed
);
wire[7:0] readData;
wire update;
reg update_prev;
always @ (posedge clk)
update_prev <= update;
wire update_posedge = !update_prev && update;
PS2_Controller ps2 (
.reset (rst),
.CLOCK_50 (clk),
.PS2_CLK(ps2CLK),
.PS2_DAT(ps2DATA),
.received_data(readData),
.received_data_en(update)
);
reg breakSig = 0;
reg extended = 0;
always @ (posedge clk) begin
if (pressed)
pressed <= 0;
if (rst) begin
breakSig <= 0;
extended <= 0;
pressed <= 0;
pressedKey <= 9'b0;
end else if (update_posedge) begin
if (readData == 8'hF0) breakSig <= 1;
else if (readData == 8'hE0) extended <= 1;
else if (breakSig) begin
breakSig <= 0;
extended <= 0;
end else begin
pressedKey <= {extended, readData};
pressed <= 1;
breakSig <= 0;
extended <= 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_TB_V
`define SKY130_FD_SC_HDLL__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hdll__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_TB_V
|
/*
Text Mode Memory
Screen Memory is 16kB, and is organized into 128-bit cells.
Also has a 2kB fixed font.
*/
module ModTxtMemW(clock, reset,
pixCellIx, cellData,
fontGlyph, fontData,
busAddr, busData, busOE, busWR, busOK);
/* verilator lint_off UNUSED */
input clock;
input reset;
input[13:0] pixCellIx;
output[127:0] cellData;
input[15:0] fontGlyph;
output[63:0] fontData;
input[31:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output[1:0] busOK;
reg[1:0] tBusOK; //Read OK State
reg[31:0] tBusData; //Output Data
wire tBusCSel; //Bus Chip-Select (Addr Matches)
assign busOK = (busOE && tBusCSel) ? tBusOK : 2'bZ;
assign busData = (busOE && tBusCSel) ? tBusData : 32'hZZZZ_ZZZZ;
assign tBusCSel = (busAddr[31:16]==16'h0080);
reg[13:0] tPixCellIx; //base cell index
reg[13:0] nxtPixCellIx; //base cell index
(* ram_style="block" *) reg[31:0] scrCell1A[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1B[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1C[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1D[0:1023];
reg[63:0] fontMem[255:0];
reg[63:0] fontGfx1Mem[127:0];
reg[63:0] fontGfx2Mem[127:0];
reg[31:0] scrRegCtrl[7:0]; //Control Registers
reg[127:0] tCell1;
reg[127:0] tNextCell1;
reg[15:0] tFontGlyph;
reg[63:0] tFontData1;
reg[63:0] tFontData2;
reg[63:0] tFontDataAsc1;
reg[63:0] tFontDataGfx1;
reg[63:0] tFontDataGfx2;
assign cellData = tCell1;
assign fontData = tFontData1;
initial begin
$readmemh("fontmem.txt", fontMem);
$readmemh("gfxfont0.txt", fontGfx1Mem);
$readmemh("gfxfont1.txt", fontGfx2Mem);
$readmemh("scrmem_1a.txt", scrCell1A);
$readmemh("scrmem_1b.txt", scrCell1B);
$readmemh("scrmem_1c.txt", scrCell1C);
$readmemh("scrmem_1d.txt", scrCell1D);
end
always @ (clock)
begin
nxtPixCellIx = pixCellIx;
tBusOK = 0;
tBusData = 0;
if(busOE && tBusCSel)
begin
nxtPixCellIx = busAddr[15:2];
if(busAddr[15:8]==255)
begin
tBusOK=1;
case(busAddr[6:2])
0: tBusData = scrRegCtrl[0];
1: tBusData = scrRegCtrl[1];
2: tBusData = scrRegCtrl[2];
3: tBusData = scrRegCtrl[3];
8: tBusData = {18'h0, pixCellIx};
endcase
end
else
begin
// tBusOK = tPixCellIx == busAddr[15:2];
// tBusData = tCell1;
tBusOK = (tPixCellIx[11:0] == busAddr[15:4]) ? 1: 0;
case(busAddr[3:2])
2'b00: tBusData = tCell1[ 31: 0];
2'b01: tBusData = tCell1[ 63:32];
2'b10: tBusData = tCell1[ 95:64];
2'b11: tBusData = tCell1[127:96];
endcase
end
end
tFontDataAsc1 = fontMem[tFontGlyph[7:0]];
tFontDataGfx1 = fontGfx1Mem[tFontGlyph[6:0]];
tFontDataGfx2 = fontGfx2Mem[tFontGlyph[6:0]];
case(tFontGlyph[9:7])
3'b000: tFontData2 = tFontDataAsc1;
3'b001: tFontData2 = tFontDataAsc1;
3'b010: tFontData2 = tFontDataGfx2;
3'b011: tFontData2 = tFontDataGfx1;
// 3'b100: tFontData2 = tFontDataAsc1;
// 3'b101: tFontData2 = tFontDataGfx2;
default: tFontData2 = tFontDataAsc1;
endcase
end
always @ (posedge clock)
begin
// tCell1 <= tNextCell1;
// tPixCellIx <= pixCellIx;
tPixCellIx <= nxtPixCellIx;
tCell1[ 31: 0] <= scrCell1A[tPixCellIx[9:0]];
tCell1[ 63:32] <= scrCell1B[tPixCellIx[9:0]];
tCell1[ 95:64] <= scrCell1C[tPixCellIx[9:0]];
tCell1[127:96] <= scrCell1D[tPixCellIx[9:0]];
tFontGlyph <= fontGlyph;
tFontData1 <= tFontData2;
if(tBusCSel && busOE)
tPixCellIx <= busAddr[15:2];
else
tPixCellIx <= pixCellIx;
if(tBusCSel && busWR && !busOE)
begin
if(busAddr[15:8]==255)
begin
scrRegCtrl[busAddr[4:2]] <= busData;
end
else
begin
// scrCell1[busAddr[11:2]] <= busData;
case(busAddr[3:2])
2'b00: scrCell1A[busAddr[13:4]] <= busData;
2'b01: scrCell1B[busAddr[13:4]] <= busData;
2'b10: scrCell1C[busAddr[13:4]] <= busData;
2'b11: scrCell1D[busAddr[13:4]] <= busData;
endcase
end
end
end
endmodule
|
`timescale 1ns / 1ps
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 05/19/2017 12:40:27 PM
// Design Name: CRC Generator - Master
// Module Name: crcGenMaster
// Project Name: SD2017
// Target Devices: Basys3
// Revision: 1.02
// Revision 1.02 - General CRC generator and size
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// CRC-7 Generator
module crcGenMaster # (
parameter bitLength = 40,
parameter crcLength = 7
)(
clk, // Clock
useModule, // sync. CRC Slave will start on posedge and keeps crc until negedge
instream, // input bit stream. length defined by parameter 'bitLength'. Should not change while useModule.
generator, // crc generator polynomial
crc, // crc value
finish, // sync. 1 = isFinished
state // {_start, _running, _waiting}, used for debugging
);
// 'public' variables
input clk;
input useModule;
input [bitLength - 1:0] instream;
input [crcLength:0] generator;
output wire [crcLength - 1:0] crc;
output reg finish = 0;
output [2:0] state;
// 'private' variables
wire [crcLength - 1:0] _crc;
reg _enable = 0, _clear = 1, _sync_enable;
reg _start = 0, _running = 0, _waiting = 0;
reg [9:0] _i = 0; // loop index
wire _datain;
assign _datain = _enable ? instream[_i] : 1'b0;
reg _sync_useModule;
reg [1:0] _edge_useModule;
assign crc = (_sync_useModule || _running ? _crc : {crcLength{1'bZ}});
reg [1:0] _error = 0;
// 'Private' Slave CRC Generator
crcGenerator c0 (_datain, clk, _clear, _sync_enable, generator, _crc);
always @ (posedge clk) begin
if (_edge_useModule == 2'b01 && ~_start && ~_running && ~_waiting) begin
// start condition
finish <= 0;
_clear <= 0;
_enable <= 1;
_start <= 1; // state start & not running & not waiting
end else if (_edge_useModule == 2'b11 && _start && _waiting) begin
// end condition
_start <= 0; // state not start & not running & waiting
_enable <= 0;
end else if (_edge_useModule == 2'b11 && ~_start && _waiting) begin
finish <= 1;
end else if (_edge_useModule == 2'b10) begin
// unuse module
finish <= 0;
_clear <= 1;
_enable <= 0;
end else begin
// => should not enter this always loop : rw/s, r/w/s, r/ws
_error[0] = 1;
end
end
// 'for loop'
always @ (posedge clk) begin
if (_start && ~_running && ~_waiting) begin
// start loop with index i > 0 (doesn't handle i = 0)
_running <= 1;
_i = bitLength - 2; // first bit is always 0 (sent in this if-block)
if (_i == 0) begin
// end loop condition
_running <= 0;
_waiting <= 1;
end
end else if (_start && _running & ~_waiting) begin
// looping
_i = _i - 1;
if (_i == 1) begin // signal delay to control block (this::line 60) compensation
// end loop condition
_running <= 0;
_waiting <= 1;
end
end else if (_start && _waiting) begin
// do nothing if waiting
end else begin
// iff not started
_running = 0;
_waiting = 0;
end
end
assign state = {_start, _running, _waiting};
always @ (posedge clk) begin
_sync_enable <= _enable;
end
always @ (posedge clk) begin
_edge_useModule[1] <= _edge_useModule[0];
_edge_useModule[0] <= useModule;
end
always @ (posedge clk) begin
_sync_useModule <= useModule;
end
endmodule
|
module TestBench_Lab2 (
output reg clk,
output reg [8:0] key_input
);
initial
begin
clk = 0;
key_input = 9'b0;
end
always
begin
#5 clk = ~clk;
end
// For the test case assigned below, the LED output should be 5'b00001
// There is an initial delay of 500 ns because the slow clock (in pwm_controller.v file) needs to be set up
// This slow clock is at 1 MHz while system clock is at 100 MHz
initial begin
# 500
#10000000
key_input <= {2'b00, 7'b0000001};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b00, 7'b0000001};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b01, 7'b0000010};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b01, 7'b0000100};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b10, 7'b0001000};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b10, 7'b0010000};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b00, 7'b0100000};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b11, 7'b1000000};
$display("key_input = %b ", key_input);
#10000000 $finish;
end
endmodule
|
module tb_fpga();
parameter wire_width = 7;
parameter lb_cfg_size = 18;
parameter fpga_width = 5;
parameter fpga_height = 5;
// Test ports
reg A, B;
reg carryin;
wire out;
wire carryout;
// Configuration ports
reg [fpga_height*fpga_width*wire_width*12-1:0] brbselect;
reg [(fpga_height-1)*(fpga_width-1)*(wire_width*wire_width*12)-1:0] bsbselect;
reg [fpga_width*fpga_height*lb_cfg_size-1:0] lbselect;
reg [2*wire_width*fpga_height-1:0] leftioselect;
reg [2*wire_width*fpga_height-1:0] rightioselect;
reg [2*wire_width*fpga_height-1:0] topioselect;
reg [2*wire_width*fpga_height-1:0] bottomioselect;
wire [4:0] left, right, top, bottom;
assign bottom[0] = A;
// assign bottom[2] = B;
// assign bottom[4] = carryin;
// // assign out = top[0];
assign out = left[0];
// assign carryout = top[4];
fpga_top #(
.wire_width(wire_width),
.lb_cfg_size(lb_cfg_size),
.fpga_width(fpga_width),
.fpga_height(fpga_width)
) f1(
clk,
brbselect, bsbselect, lbselect,
leftioselect, rightioselect, topioselect, bottomioselect,
left, right, top, bottom
);
reg k;
initial begin
brbselect = 900'b0;
bsbselect = 1728'b0;
lbselect = 80'b0;
leftioselect = 30'b0;
rightioselect = 30'b0;
topioselect = 30'b0;
bottomioselect = 30'b0;
$display("initialized memory");
set_bottom_io_cfg(0, 0, 1); // Bottom left in
// // bottomioselect[1] = 1'b1;
// set_top_io_cfg(0, 0, 1); // Top left out
set_left_io_cfg(0, 0, 2);
// // leftioselect[0] = 1'b1;
set_brb_cfg(0, 0, 0, 2, 1);
// brbselect[4] = 1'b0;
// brbselect[5] = 1'b1;
// // set_brb_cfg(0, 0, 0, 3, 1);
// set_brb_cfg(1, 0, 0, 3, 1);
// set_brb_cfg(2, 0, 0, 3, 1);
// set_brb_cfg(3, 0, 0, 3, 1);
// set_brb_cfg(4, 0, 0, 3, 1);
$display("finished setting bits.");
A = 1'b0; B = 1'b0; carryin = 1'b0;
$monitor("A = %b, B = %b, carryin = %b, out = %b, carryout = %b",
A, B, carryin, out, carryout);
#10 A = 1'b0; B = 1'b0; carryin = 1'b0;
#10 A = 1'b1; B = 1'b0; carryin = 1'b0;
#10 A = 1'b0; B = 1'b1; carryin = 1'b0;
#10 A = 1'b1; B = 1'b1; carryin = 1'b0;
#10 A = 1'b0; B = 1'b0; carryin = 1'b1;
#10 A = 1'b1; B = 1'b0; carryin = 1'b1;
#10 A = 1'b0; B = 1'b1; carryin = 1'b1;
#10 A = 1'b1; B = 1'b1; carryin = 1'b1;
end
task set_top_io_cfg;
input integer io_index, io_line, io_dir;
begin
if (io_dir == 0) begin // Off
topioselect[io_index*6+io_line*2+0] = 1'b0;
topioselect[io_index*6+io_line*2+1] = 1'b0;
end else if (io_dir == 1) begin // Out
$display("set bit %d in top", io_index*6+io_line*2+1);
topioselect[io_index*6+io_line*2+0] = 1'b0;
topioselect[io_index*6+io_line*2+1] = 1'b1;
end else if (io_dir == 2) begin // In
$display("set bit %d in top", io_index*6+io_line*2+0);
topioselect[io_index*6+io_line*2+0] = 1'b1;
topioselect[io_index*6+io_line*2+1] = 1'b0;
end
end
endtask
task set_bottom_io_cfg;
input integer io_index, io_line, io_dir;
begin
if (io_dir == 0) begin // Off
bottomioselect[io_index*6+io_line*2+0] = 1'b0;
bottomioselect[io_index*6+io_line*2+1] = 1'b0;
end else if (io_dir == 1) begin // Out
$display("set bit %d in bottom", io_index*6+io_line*2+1);
bottomioselect[io_index*6+io_line*2+0] = 1'b0;
bottomioselect[io_index*6+io_line*2+1] = 1'b1;
end else if (io_dir == 2) begin // In
$display("set bit %d in bottom", io_index*6+io_line*2+0);
bottomioselect[io_index*6+io_line*2+0] = 1'b1;
bottomioselect[io_index*6+io_line*2+1] = 1'b0;
end
end
endtask
task set_left_io_cfg;
input integer io_index, io_line, io_dir;
begin
if (io_dir == 0) begin // Off
leftioselect[io_index*6+io_line*2+0] = 1'b0;
leftioselect[io_index*6+io_line*2+1] = 1'b0;
end else if (io_dir == 1) begin // Out
$display("set bit %d in left", io_index*6+io_line*2+1);
leftioselect[io_index*6+io_line*2+0] = 1'b0;
leftioselect[io_index*6+io_line*2+1] = 1'b1;
end else if (io_dir == 2) begin // In
$display("set bit %d in left", io_index*6+io_line*2+0);
leftioselect[io_index*6+io_line*2+0] = 1'b1;
leftioselect[io_index*6+io_line*2+1] = 1'b0;
end
end
endtask
task set_right_io_cfg;
input integer io_index, io_line, io_dir;
begin
if (io_dir == 0) begin // Off
rightioselect[io_index*6+io_line*2+0] = 1'b0;
rightioselect[io_index*6+io_line*2+1] = 1'b0;
end else if (io_dir == 1) begin // Out
$display("set bit %d in right", io_index*6+io_line*2+1);
rightioselect[io_index*6+io_line*2+0] = 1'b0;
rightioselect[io_index*6+io_line*2+1] = 1'b1;
end else if (io_dir == 2) begin // In
$display("set bit %d in right", io_index*6+io_line*2+0);
rightioselect[io_index*6+io_line*2+0] = 1'b1;
rightioselect[io_index*6+io_line*2+1] = 1'b0;
end
end
endtask
task set_brb_cfg;
input integer row, col;
// which switch element, which internal switch
input integer s_index, s_sel;
input integer dir;
begin
if (dir == 0) begin // Off
brbselect[col*36 + row*180 + s_index*12 + s_sel*2] = 1'b0;
brbselect[col*36 + row*180 + s_index*12 + s_sel*2 + 1] = 1'b0;
end else if (dir == 1) begin // In
brbselect[col*36 + row*180 + s_index*12 + s_sel*2] = 1'b0;
brbselect[col*36 + row*180 + s_index*12 + s_sel*2 + 1] = 1'b1;
end else if (dir == 2) begin // Out
brbselect[col*36 + row*180 + s_index*12 + s_sel*2] = 1'b1;
brbselect[col*36 + row*180 + s_index*12 + s_sel*2 + 1] = 1'b0;
end
end
endtask
task set_bsb_cfg;
input integer row, col;
// which switch element, which internal switch
input integer s_row, s_col, s_sel;
input integer dir;
begin
if (dir == 0) begin // Off
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2] = 1'b0;
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2 + 1] = 1'b0;
end else if (dir == 1) begin // In
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2] = 1'b0;
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2 + 1] = 1'b1;
end else if (dir == 2) begin // Out
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2] = 1'b1;
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2 + 1] = 1'b0;
end
end
endtask
task set_lb_cfg;
input integer row, col;
input [3:0] truth_tbl;
input sync;
begin
lbselect[col*5 + row * 20] = truth_tbl[0];
lbselect[col*5 + row * 20 + 1] = truth_tbl[1];
lbselect[col*5 + row * 20 + 2] = truth_tbl[2];
lbselect[col*5 + row * 20 + 3] = truth_tbl[3];
lbselect[col*5 + row * 20 + 4] = sync;
end
endtask
endmodule
|
`timescale 1ns/1ps
module rgb_generator #(
parameter CLOCK_RATE = 100000000,
parameter FPS = 60,
//Should be at the center of the screen
parameter FRAME_WIDTH = 480,
parameter FRAME_HEIGHT = 272,
parameter X_OFFSET = 112,
parameter Y_OFFSET = 6,
parameter BG_COLOR = 8'h00,
parameter HBLANK = 100,
parameter VBLANK = 10
)(
input clk, // 100MHz system clock signal
input rst, // reset signal
//X, Y, Y Next, pixel clock and a vblank
output [9:0] o_nes_x_out, // nes x coordinate
output [9:0] o_nes_y_out, // nes y coordinate
output [9:0] o_nes_y_next_out, // next line's nes y coordinate
output reg o_pix_pulse_out, // 1 clk pulse prior to o_nes_x update
//output o_pix_pulse_out, // 1 clk pulse prior to o_nes_x update
output o_vblank, // indicates a vblank is occuring (no PPU vram access)
//From the below control signal, the PPU returns this value
input [5:0] i_sys_palette_idx_in, // system palette index (selects output color)
//Generated Signals to Drive Display
output reg o_video_hsync = 0, // Video horizontal sync
output reg o_sof_stb = 0, // Start of frame
output [2:0] o_r_out, // vga red signal
output [2:0] o_g_out, // vga green signal
output [1:0] o_b_out // vga blue signal
);
//local parameters
localparam IMAGE_WIDTH = 256;
localparam IMAGE_HEIGHT = 240;
localparam VBLANK_TIMEOUT = ((((FRAME_WIDTH + HBLANK) * FRAME_HEIGHT) + VBLANK) > (CLOCK_RATE / FPS)) ?
10 :
(CLOCK_RATE / FPS) - (((FRAME_WIDTH + HBLANK) * FRAME_HEIGHT) + VBLANK);
//localparam VBLANK_TIMEOUT = 500;
//localparam VBLANK_TIMEOUT = 148064;
//localparam VBLANK_TIMEOUT = 150000;
localparam IDLE = 0;
localparam VID = 1;
//Registers/Wires
reg [9:0] r_x_pos;
reg [9:0] r_y_pos;
reg [7:0] r_rgb;
wire [8:0] w_x_pos;
wire [8:0] w_y_pos;
reg [23:0] r_clk_div_count;
wire [23:0] w_vblank_debug = VBLANK_TIMEOUT;
reg [3:0] state;
wire [7:0] w_bg_color;
wire w_valid;
reg r_valid;
wire [31:0] w_vblank_timeout = VBLANK_TIMEOUT;
reg r_start_stb;
//synchronous logic
//Generate a pulse when we are about to start capturing video
always @ (posedge clk) begin
r_start_stb <= 0;
if (rst) begin
r_clk_div_count <= 0;
end
else begin
if (r_clk_div_count < VBLANK_TIMEOUT) begin
r_clk_div_count <= r_clk_div_count + 1;
end
else begin
r_clk_div_count <= 0;
r_start_stb <= 1;
end
end
end
//Color lookup table
always @ (*) begin
if (!r_valid) begin
r_rgb = 0;
end
else begin
// Lookup RGB values based on sys_palette_idx. Table is an approximation of the NES
// system palette. Taken from http://nesdev.parodius.com/NESTechFAQ.htm#nessnescompat.
case (i_sys_palette_idx_in)
6'h00: r_rgb = { 3'h3, 3'h3, 2'h1 };
6'h01: r_rgb = { 3'h1, 3'h0, 2'h2 };
6'h02: r_rgb = { 3'h0, 3'h0, 2'h2 };
6'h03: r_rgb = { 3'h2, 3'h0, 2'h2 };
6'h04: r_rgb = { 3'h4, 3'h0, 2'h1 };
6'h05: r_rgb = { 3'h5, 3'h0, 2'h0 };
6'h06: r_rgb = { 3'h5, 3'h0, 2'h0 };
6'h07: r_rgb = { 3'h3, 3'h0, 2'h0 };
6'h08: r_rgb = { 3'h2, 3'h1, 2'h0 };
6'h09: r_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0a: r_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0b: r_rgb = { 3'h0, 3'h1, 2'h0 };
6'h0c: r_rgb = { 3'h0, 3'h1, 2'h1 };
6'h0d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h10: r_rgb = { 3'h5, 3'h5, 2'h2 };
6'h11: r_rgb = { 3'h0, 3'h3, 2'h3 };
6'h12: r_rgb = { 3'h1, 3'h1, 2'h3 };
6'h13: r_rgb = { 3'h4, 3'h0, 2'h3 };
6'h14: r_rgb = { 3'h5, 3'h0, 2'h2 };
6'h15: r_rgb = { 3'h7, 3'h0, 2'h1 };
6'h16: r_rgb = { 3'h6, 3'h1, 2'h0 };
6'h17: r_rgb = { 3'h6, 3'h2, 2'h0 };
6'h18: r_rgb = { 3'h4, 3'h3, 2'h0 };
6'h19: r_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1a: r_rgb = { 3'h0, 3'h5, 2'h0 };
6'h1b: r_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1c: r_rgb = { 3'h0, 3'h4, 2'h2 };
6'h1d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h20: r_rgb = { 3'h7, 3'h7, 2'h3 };
6'h21: r_rgb = { 3'h1, 3'h5, 2'h3 };
6'h22: r_rgb = { 3'h2, 3'h4, 2'h3 };
6'h23: r_rgb = { 3'h5, 3'h4, 2'h3 };
6'h24: r_rgb = { 3'h7, 3'h3, 2'h3 };
6'h25: r_rgb = { 3'h7, 3'h3, 2'h2 };
6'h26: r_rgb = { 3'h7, 3'h3, 2'h1 };
6'h27: r_rgb = { 3'h7, 3'h4, 2'h0 };
6'h28: r_rgb = { 3'h7, 3'h5, 2'h0 };
6'h29: r_rgb = { 3'h4, 3'h6, 2'h0 };
6'h2a: r_rgb = { 3'h2, 3'h6, 2'h1 };
6'h2b: r_rgb = { 3'h2, 3'h7, 2'h2 };
6'h2c: r_rgb = { 3'h0, 3'h7, 2'h3 };
6'h2d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h30: r_rgb = { 3'h7, 3'h7, 2'h3 };
6'h31: r_rgb = { 3'h5, 3'h7, 2'h3 };
6'h32: r_rgb = { 3'h6, 3'h6, 2'h3 };
6'h33: r_rgb = { 3'h6, 3'h6, 2'h3 };
6'h34: r_rgb = { 3'h7, 3'h6, 2'h3 };
6'h35: r_rgb = { 3'h7, 3'h6, 2'h3 };
6'h36: r_rgb = { 3'h7, 3'h5, 2'h2 };
6'h37: r_rgb = { 3'h7, 3'h6, 2'h2 };
6'h38: r_rgb = { 3'h7, 3'h7, 2'h2 };
6'h39: r_rgb = { 3'h7, 3'h7, 2'h2 };
6'h3a: r_rgb = { 3'h5, 3'h7, 2'h2 };
6'h3b: r_rgb = { 3'h5, 3'h7, 2'h3 };
6'h3c: r_rgb = { 3'h4, 3'h7, 2'h3 };
6'h3d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3f: r_rgb = { 3'h0, 3'h0, 2'h0 };
default: r_rgb = {3'h0, 3'h0, 2'h0 };
endcase
end
end
assign o_vblank = state == VID;
//assign o_pix_pulse_out = w_valid;
assign w_valid = (r_x_pos >= X_OFFSET) && (r_x_pos < (X_OFFSET + IMAGE_WIDTH)) &&
(r_y_pos >= Y_OFFSET) && (r_y_pos < (Y_OFFSET + IMAGE_HEIGHT));
assign w_x_pos = w_valid ? r_x_pos - X_OFFSET: 0;
assign w_y_pos = w_valid ? r_y_pos - Y_OFFSET: 0;
assign o_nes_x_out = {1'b0, w_x_pos};
assign o_nes_y_out = {1'b0, w_y_pos};
assign o_nes_y_next_out = w_valid ? o_nes_y_out + 1: 1;
assign o_r_out = r_valid ? r_rgb[7:5]: w_bg_color[7:5];
assign o_g_out = r_valid ? r_rgb[4:2]: w_bg_color[4:2];
assign o_b_out = r_valid ? r_rgb[1:0]: w_bg_color[1:0];
assign w_bg_color = BG_COLOR;
//Positional data
always @ (posedge clk) begin
o_sof_stb <= 0;
r_valid <= w_valid;
o_pix_pulse_out <= 0;
if (rst) begin
r_x_pos <= 0;
r_y_pos <= 0;
o_video_hsync <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
if (r_start_stb) begin
state <= VID;
r_y_pos <= 0;
r_x_pos <= 0;
end
end
VID: begin
//if ((r_y_pos == Y_OFFSET) && (r_x_pos == X_OFFSET)) begin
if ((r_y_pos == 0) && (r_x_pos == 0)) begin
o_sof_stb <= 1;
end
if ((r_x_pos == 0) && (r_y_pos < FRAME_HEIGHT)) begin
o_video_hsync <= 1;
end
if (r_y_pos < (FRAME_HEIGHT + VBLANK)) begin
if (r_x_pos < (FRAME_WIDTH + HBLANK)) begin
if (r_x_pos < FRAME_WIDTH) begin
if (((r_y_pos >= (Y_OFFSET - 1)) && (r_y_pos < (Y_OFFSET + IMAGE_HEIGHT))) &&
((r_x_pos >= (X_OFFSET - 1)) && (r_x_pos < (X_OFFSET + IMAGE_WIDTH )))) begin
o_pix_pulse_out <= 1;
end
end
else begin
o_video_hsync <= 0;
end
r_x_pos <= r_x_pos + 1;
end
else begin
//$display("Next Line!");
r_x_pos <= 0;
r_y_pos <= r_y_pos + 1;
end
end
else begin
state <= IDLE;
end
end
default: begin
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:30:37 11/03/2014
// Design Name:
// Module Name:
// Project Name:
// Target Devices:
// Tool versions:
// Description: HEX to Seven segment display
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module hex_to_sseg(
input wire[3:0] hex,
output reg[7:0] sseg, // led order: dp, a, b, c, d, e, f, g
input dp
);
always @*
begin
case(hex)
4'h0: sseg[6:0] = 7'b0000001;
4'h1: sseg[6:0] = 7'b1001111;
4'h2: sseg[6:0] = 7'b0010010;
4'h3: sseg[6:0] = 7'b0000110;
4'h4: sseg[6:0] = 7'b1001100;
4'h5: sseg[6:0] = 7'b0100100;
4'h6: sseg[6:0] = 7'b0100000;
4'h7: sseg[6:0] = 7'b0001111;
4'h8: sseg[6:0] = 7'b0000000;
4'h9: sseg[6:0] = 7'b0000100;
4'ha: sseg[6:0] = 7'b0000010;
4'hb: sseg[6:0] = 7'b1100000;
4'hc: sseg[6:0] = 7'b0110001;
4'hd: sseg[6:0] = 7'b1000010;
4'he: sseg[6:0] = 7'b0010000;
4'hf: sseg[6:0] = 7'b0111000;
default: sseg[6:0] = 7'b111111;
endcase
sseg[7] = dp;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 11:11:04 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
n167, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178,
n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266,
n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n310, n311,
n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322,
n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333,
n334, n335, n336, n337, n338, n339, n340, n341, n342, n343, n344,
n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355,
n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366,
n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, n377,
n378, n379, n380, mult_x_59_n37, mult_x_59_n36, mult_x_59_n30,
mult_x_59_n29, mult_x_59_n23, mult_x_59_n22, mult_x_59_n18,
mult_x_59_n17, mult_x_59_n15, mult_x_59_n14, mult_x_58_n37,
mult_x_58_n36, mult_x_58_n30, mult_x_58_n29, mult_x_58_n23,
mult_x_58_n22, mult_x_58_n18, mult_x_58_n17, mult_x_58_n15,
mult_x_58_n14, mult_x_57_n37, mult_x_57_n36, mult_x_57_n30,
mult_x_57_n29, mult_x_57_n23, mult_x_57_n22, mult_x_57_n18,
mult_x_57_n17, mult_x_57_n15, mult_x_57_n14, mult_x_56_n37,
mult_x_56_n36, mult_x_56_n30, mult_x_56_n29, mult_x_56_n23,
mult_x_56_n22, mult_x_56_n18, mult_x_56_n17, mult_x_56_n15,
mult_x_56_n14, DP_OP_36J23_129_4699_n22, DP_OP_36J23_129_4699_n21,
DP_OP_36J23_129_4699_n20, DP_OP_36J23_129_4699_n19,
DP_OP_36J23_129_4699_n18, DP_OP_36J23_129_4699_n17,
DP_OP_36J23_129_4699_n16, DP_OP_36J23_129_4699_n15,
DP_OP_36J23_129_4699_n9, DP_OP_36J23_129_4699_n8,
DP_OP_36J23_129_4699_n7, DP_OP_36J23_129_4699_n6,
DP_OP_36J23_129_4699_n5, DP_OP_36J23_129_4699_n4,
DP_OP_36J23_129_4699_n3, DP_OP_36J23_129_4699_n2,
DP_OP_36J23_129_4699_n1, intadd_54_A_8_, intadd_54_A_0_,
intadd_54_B_8_, intadd_54_B_7_, intadd_54_B_2_, intadd_54_B_1_,
intadd_54_B_0_, intadd_54_CI, intadd_54_n9, intadd_54_n8,
intadd_54_n7, intadd_54_n6, intadd_54_n5, intadd_54_n4, intadd_54_n3,
intadd_54_n2, intadd_54_n1, intadd_55_A_8_, intadd_55_A_1_,
intadd_55_A_0_, intadd_55_B_8_, intadd_55_B_7_, intadd_55_B_2_,
intadd_55_B_1_, intadd_55_B_0_, intadd_55_CI, intadd_55_n9,
intadd_55_n8, intadd_55_n7, intadd_55_n6, intadd_55_n5, intadd_55_n4,
intadd_55_n3, intadd_55_n2, intadd_55_n1, intadd_56_A_8_,
intadd_56_A_0_, intadd_56_B_8_, intadd_56_B_7_, intadd_56_B_2_,
intadd_56_B_1_, intadd_56_B_0_, intadd_56_CI, intadd_56_n9,
intadd_56_n8, intadd_56_n7, intadd_56_n6, intadd_56_n5, intadd_56_n4,
intadd_56_n3, intadd_56_n2, intadd_56_n1, intadd_57_A_0_,
intadd_57_B_7_, intadd_57_B_2_, intadd_57_B_1_, intadd_57_B_0_,
intadd_57_n8, intadd_57_n7, intadd_57_n6, intadd_57_n5, intadd_57_n4,
intadd_57_n3, intadd_57_n2, intadd_57_n1, DP_OP_157J23_126_5719_n188,
DP_OP_157J23_126_5719_n187, DP_OP_157J23_126_5719_n186,
DP_OP_157J23_126_5719_n185, DP_OP_157J23_126_5719_n181,
DP_OP_157J23_126_5719_n180, DP_OP_157J23_126_5719_n179,
DP_OP_157J23_126_5719_n178, DP_OP_157J23_126_5719_n174,
DP_OP_157J23_126_5719_n172, DP_OP_157J23_126_5719_n171,
DP_OP_157J23_126_5719_n170, DP_OP_157J23_126_5719_n165,
DP_OP_157J23_126_5719_n164, DP_OP_157J23_126_5719_n162,
DP_OP_157J23_126_5719_n161, DP_OP_157J23_126_5719_n158,
DP_OP_157J23_126_5719_n157, DP_OP_157J23_126_5719_n155,
DP_OP_157J23_126_5719_n154, DP_OP_157J23_126_5719_n151,
DP_OP_157J23_126_5719_n150, DP_OP_157J23_126_5719_n147,
DP_OP_157J23_126_5719_n141, DP_OP_157J23_126_5719_n138,
DP_OP_157J23_126_5719_n137, DP_OP_157J23_126_5719_n136,
DP_OP_157J23_126_5719_n135, DP_OP_157J23_126_5719_n134,
DP_OP_157J23_126_5719_n132, DP_OP_157J23_126_5719_n131,
DP_OP_157J23_126_5719_n130, DP_OP_157J23_126_5719_n129,
DP_OP_157J23_126_5719_n128, DP_OP_157J23_126_5719_n127,
DP_OP_157J23_126_5719_n126, DP_OP_157J23_126_5719_n125,
DP_OP_157J23_126_5719_n124, DP_OP_157J23_126_5719_n123,
DP_OP_157J23_126_5719_n122, DP_OP_157J23_126_5719_n121,
DP_OP_157J23_126_5719_n120, DP_OP_157J23_126_5719_n119,
DP_OP_157J23_126_5719_n118, DP_OP_157J23_126_5719_n117,
DP_OP_157J23_126_5719_n116, DP_OP_157J23_126_5719_n115,
DP_OP_157J23_126_5719_n112, DP_OP_157J23_126_5719_n111,
DP_OP_157J23_126_5719_n110, DP_OP_157J23_126_5719_n109,
DP_OP_157J23_126_5719_n108, DP_OP_157J23_126_5719_n107,
DP_OP_157J23_126_5719_n106, DP_OP_157J23_126_5719_n105,
DP_OP_157J23_126_5719_n104, DP_OP_157J23_126_5719_n103,
DP_OP_157J23_126_5719_n102, DP_OP_157J23_126_5719_n101,
DP_OP_157J23_126_5719_n100, DP_OP_159J23_128_5719_n188,
DP_OP_159J23_128_5719_n187, DP_OP_159J23_128_5719_n186,
DP_OP_159J23_128_5719_n185, DP_OP_159J23_128_5719_n181,
DP_OP_159J23_128_5719_n180, DP_OP_159J23_128_5719_n179,
DP_OP_159J23_128_5719_n178, DP_OP_159J23_128_5719_n174,
DP_OP_159J23_128_5719_n172, DP_OP_159J23_128_5719_n171,
DP_OP_159J23_128_5719_n170, DP_OP_159J23_128_5719_n165,
DP_OP_159J23_128_5719_n164, DP_OP_159J23_128_5719_n162,
DP_OP_159J23_128_5719_n161, DP_OP_159J23_128_5719_n158,
DP_OP_159J23_128_5719_n157, DP_OP_159J23_128_5719_n155,
DP_OP_159J23_128_5719_n154, DP_OP_159J23_128_5719_n151,
DP_OP_159J23_128_5719_n150, DP_OP_159J23_128_5719_n147,
DP_OP_159J23_128_5719_n141, DP_OP_159J23_128_5719_n138,
DP_OP_159J23_128_5719_n137, DP_OP_159J23_128_5719_n136,
DP_OP_159J23_128_5719_n135, DP_OP_159J23_128_5719_n134,
DP_OP_159J23_128_5719_n132, DP_OP_159J23_128_5719_n131,
DP_OP_159J23_128_5719_n130, DP_OP_159J23_128_5719_n129,
DP_OP_159J23_128_5719_n128, DP_OP_159J23_128_5719_n127,
DP_OP_159J23_128_5719_n126, DP_OP_159J23_128_5719_n125,
DP_OP_159J23_128_5719_n124, DP_OP_159J23_128_5719_n123,
DP_OP_159J23_128_5719_n122, DP_OP_159J23_128_5719_n121,
DP_OP_159J23_128_5719_n120, DP_OP_159J23_128_5719_n119,
DP_OP_159J23_128_5719_n118, DP_OP_159J23_128_5719_n117,
DP_OP_159J23_128_5719_n116, DP_OP_159J23_128_5719_n115,
DP_OP_159J23_128_5719_n112, DP_OP_159J23_128_5719_n111,
DP_OP_159J23_128_5719_n110, DP_OP_159J23_128_5719_n109,
DP_OP_159J23_128_5719_n108, DP_OP_159J23_128_5719_n107,
DP_OP_159J23_128_5719_n106, DP_OP_159J23_128_5719_n105,
DP_OP_159J23_128_5719_n104, DP_OP_159J23_128_5719_n103,
DP_OP_159J23_128_5719_n102, DP_OP_159J23_128_5719_n101,
DP_OP_159J23_128_5719_n100, DP_OP_156J23_125_3370_n304,
DP_OP_156J23_125_3370_n303, DP_OP_156J23_125_3370_n302,
DP_OP_156J23_125_3370_n301, DP_OP_156J23_125_3370_n300,
DP_OP_156J23_125_3370_n297, DP_OP_156J23_125_3370_n295,
DP_OP_156J23_125_3370_n294, DP_OP_156J23_125_3370_n293,
DP_OP_156J23_125_3370_n292, DP_OP_156J23_125_3370_n290,
DP_OP_156J23_125_3370_n281, DP_OP_156J23_125_3370_n280,
DP_OP_156J23_125_3370_n279, DP_OP_156J23_125_3370_n278,
DP_OP_156J23_125_3370_n277, DP_OP_156J23_125_3370_n276,
DP_OP_156J23_125_3370_n275, DP_OP_156J23_125_3370_n274,
DP_OP_156J23_125_3370_n273, DP_OP_156J23_125_3370_n270,
DP_OP_156J23_125_3370_n268, DP_OP_156J23_125_3370_n267,
DP_OP_156J23_125_3370_n266, DP_OP_156J23_125_3370_n252,
DP_OP_156J23_125_3370_n250, DP_OP_156J23_125_3370_n249,
DP_OP_156J23_125_3370_n248, DP_OP_156J23_125_3370_n247,
DP_OP_156J23_125_3370_n246, DP_OP_156J23_125_3370_n245,
DP_OP_156J23_125_3370_n244, DP_OP_156J23_125_3370_n243,
DP_OP_156J23_125_3370_n242, DP_OP_156J23_125_3370_n241,
DP_OP_156J23_125_3370_n240, DP_OP_156J23_125_3370_n239,
DP_OP_156J23_125_3370_n238, DP_OP_156J23_125_3370_n237,
DP_OP_156J23_125_3370_n236, DP_OP_156J23_125_3370_n235,
DP_OP_156J23_125_3370_n234, DP_OP_156J23_125_3370_n233,
DP_OP_156J23_125_3370_n232, DP_OP_156J23_125_3370_n231,
DP_OP_156J23_125_3370_n230, DP_OP_156J23_125_3370_n229,
DP_OP_156J23_125_3370_n228, DP_OP_156J23_125_3370_n227,
DP_OP_156J23_125_3370_n226, DP_OP_156J23_125_3370_n225,
DP_OP_156J23_125_3370_n224, DP_OP_156J23_125_3370_n223,
DP_OP_156J23_125_3370_n222, DP_OP_156J23_125_3370_n221,
DP_OP_156J23_125_3370_n220, DP_OP_156J23_125_3370_n219,
DP_OP_156J23_125_3370_n218, DP_OP_156J23_125_3370_n217,
DP_OP_156J23_125_3370_n216, DP_OP_156J23_125_3370_n215,
DP_OP_156J23_125_3370_n214, DP_OP_156J23_125_3370_n213,
DP_OP_156J23_125_3370_n212, DP_OP_156J23_125_3370_n211,
DP_OP_156J23_125_3370_n210, DP_OP_156J23_125_3370_n209,
DP_OP_156J23_125_3370_n208, DP_OP_156J23_125_3370_n207,
DP_OP_156J23_125_3370_n206, DP_OP_156J23_125_3370_n205,
DP_OP_156J23_125_3370_n204, DP_OP_156J23_125_3370_n203,
DP_OP_156J23_125_3370_n202, DP_OP_153J23_122_3500_n147,
DP_OP_154J23_123_2814_n140, DP_OP_158J23_127_356_n529,
DP_OP_158J23_127_356_n525, DP_OP_158J23_127_356_n524,
DP_OP_158J23_127_356_n523, DP_OP_158J23_127_356_n519,
DP_OP_158J23_127_356_n518, DP_OP_158J23_127_356_n517,
DP_OP_158J23_127_356_n513, DP_OP_158J23_127_356_n511,
DP_OP_158J23_127_356_n508, DP_OP_158J23_127_356_n505,
DP_OP_158J23_127_356_n502, DP_OP_158J23_127_356_n499,
DP_OP_158J23_127_356_n497, DP_OP_158J23_127_356_n496,
DP_OP_158J23_127_356_n490, DP_OP_158J23_127_356_n487,
DP_OP_158J23_127_356_n486, DP_OP_158J23_127_356_n485,
DP_OP_158J23_127_356_n484, DP_OP_158J23_127_356_n483,
DP_OP_158J23_127_356_n481, DP_OP_158J23_127_356_n480,
DP_OP_158J23_127_356_n479, DP_OP_158J23_127_356_n478,
DP_OP_158J23_127_356_n477, DP_OP_158J23_127_356_n476,
DP_OP_158J23_127_356_n475, DP_OP_158J23_127_356_n474,
DP_OP_158J23_127_356_n473, DP_OP_158J23_127_356_n472,
DP_OP_158J23_127_356_n471, DP_OP_158J23_127_356_n470,
DP_OP_158J23_127_356_n469, DP_OP_158J23_127_356_n468,
DP_OP_158J23_127_356_n467, DP_OP_158J23_127_356_n466,
DP_OP_158J23_127_356_n465, DP_OP_158J23_127_356_n464,
DP_OP_158J23_127_356_n463, DP_OP_158J23_127_356_n462,
DP_OP_158J23_127_356_n461, DP_OP_158J23_127_356_n460,
DP_OP_158J23_127_356_n459, DP_OP_158J23_127_356_n458,
DP_OP_158J23_127_356_n457, DP_OP_158J23_127_356_n456,
DP_OP_158J23_127_356_n455, DP_OP_158J23_127_356_n263,
DP_OP_158J23_127_356_n262, DP_OP_158J23_127_356_n261,
DP_OP_158J23_127_356_n260, DP_OP_158J23_127_356_n259,
DP_OP_158J23_127_356_n254, DP_OP_158J23_127_356_n253,
DP_OP_158J23_127_356_n252, DP_OP_158J23_127_356_n251,
DP_OP_158J23_127_356_n250, DP_OP_158J23_127_356_n247,
DP_OP_158J23_127_356_n246, DP_OP_158J23_127_356_n245,
DP_OP_158J23_127_356_n244, DP_OP_158J23_127_356_n243,
DP_OP_158J23_127_356_n242, DP_OP_158J23_127_356_n241,
DP_OP_158J23_127_356_n237, DP_OP_158J23_127_356_n236,
DP_OP_158J23_127_356_n235, DP_OP_158J23_127_356_n234,
DP_OP_158J23_127_356_n233, DP_OP_158J23_127_356_n232,
DP_OP_158J23_127_356_n229, DP_OP_158J23_127_356_n228,
DP_OP_158J23_127_356_n227, DP_OP_158J23_127_356_n225,
DP_OP_158J23_127_356_n224, DP_OP_158J23_127_356_n219,
DP_OP_158J23_127_356_n216, DP_OP_158J23_127_356_n214,
DP_OP_158J23_127_356_n211, DP_OP_158J23_127_356_n208,
DP_OP_158J23_127_356_n207, DP_OP_158J23_127_356_n206,
DP_OP_158J23_127_356_n203, DP_OP_158J23_127_356_n200,
DP_OP_158J23_127_356_n198, DP_OP_158J23_127_356_n193,
DP_OP_158J23_127_356_n191, DP_OP_158J23_127_356_n190,
DP_OP_158J23_127_356_n188, DP_OP_158J23_127_356_n187,
DP_OP_158J23_127_356_n186, DP_OP_158J23_127_356_n184,
DP_OP_158J23_127_356_n183, DP_OP_158J23_127_356_n182,
DP_OP_158J23_127_356_n181, DP_OP_158J23_127_356_n180,
DP_OP_158J23_127_356_n179, DP_OP_158J23_127_356_n178,
DP_OP_158J23_127_356_n176, DP_OP_158J23_127_356_n175,
DP_OP_158J23_127_356_n174, DP_OP_158J23_127_356_n173,
DP_OP_158J23_127_356_n172, DP_OP_158J23_127_356_n171,
DP_OP_158J23_127_356_n169, DP_OP_158J23_127_356_n168,
DP_OP_158J23_127_356_n167, DP_OP_158J23_127_356_n166,
DP_OP_158J23_127_356_n165, DP_OP_158J23_127_356_n164,
DP_OP_158J23_127_356_n163, DP_OP_158J23_127_356_n162,
DP_OP_158J23_127_356_n161, DP_OP_158J23_127_356_n160,
DP_OP_158J23_127_356_n159, DP_OP_158J23_127_356_n158,
DP_OP_158J23_127_356_n157, DP_OP_158J23_127_356_n156,
DP_OP_158J23_127_356_n155, DP_OP_158J23_127_356_n154,
DP_OP_158J23_127_356_n153, DP_OP_158J23_127_356_n152,
DP_OP_158J23_127_356_n151, DP_OP_158J23_127_356_n150,
DP_OP_158J23_127_356_n149, DP_OP_158J23_127_356_n148,
DP_OP_158J23_127_356_n147, DP_OP_158J23_127_356_n146,
DP_OP_158J23_127_356_n145, DP_OP_158J23_127_356_n144,
DP_OP_158J23_127_356_n143, DP_OP_158J23_127_356_n142,
DP_OP_158J23_127_356_n141, DP_OP_158J23_127_356_n140,
DP_OP_158J23_127_356_n139, DP_OP_158J23_127_356_n138,
DP_OP_158J23_127_356_n137, DP_OP_158J23_127_356_n136,
DP_OP_158J23_127_356_n135, DP_OP_158J23_127_356_n134,
DP_OP_158J23_127_356_n133, DP_OP_158J23_127_356_n132,
DP_OP_158J23_127_356_n131, DP_OP_158J23_127_356_n130,
DP_OP_158J23_127_356_n129, DP_OP_158J23_127_356_n128,
DP_OP_158J23_127_356_n127, DP_OP_158J23_127_356_n126,
DP_OP_158J23_127_356_n125, DP_OP_158J23_127_356_n124,
DP_OP_158J23_127_356_n123, DP_OP_158J23_127_356_n122,
DP_OP_158J23_127_356_n121, DP_OP_158J23_127_356_n120, n390, n391,
n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402,
n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n562, n563, n564, n565, n566, n567, n568, n569, n570,
n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581,
n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592,
n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614,
n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636,
n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647,
n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658,
n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669,
n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680,
n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702,
n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724,
n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746,
n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768,
n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779,
n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790,
n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801,
n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812,
n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823,
n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834,
n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845,
n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878,
n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349,
n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499,
n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509,
n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519,
n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579,
n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599,
n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839,
n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889,
n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909,
n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919,
n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929,
n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949,
n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959,
n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969,
n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979,
n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989,
n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999,
n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009,
n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159,
n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169,
n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269,
n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279,
n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369,
n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379,
n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429,
n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109,
n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119,
n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129,
n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139,
n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149,
n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159,
n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169,
n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179,
n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259,
n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269,
n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279,
n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289,
n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299,
n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309,
n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319,
n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329,
n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339,
n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349,
n3350, n3351, n3352, n3353, n3355, n3356, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3378, n3379, n3380, n3381, n3382,
n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392,
n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402,
n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412,
n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422,
n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432,
n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442,
n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452,
n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462,
n3463;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [5:0] Sgf_operation_Result;
wire [1:0] Sgf_operation_EVEN1_Q_left;
wire [13:0] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle;
wire [11:2] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right;
wire [11:0] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [15:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle;
wire [13:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [10:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [13:0] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle;
wire [11:6] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right;
wire [11:0] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n310), .CK(clk), .RN(
n3440), .Q(Op_MY[31]) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n378), .CK(clk), .RN(n3437), .Q(
FS_Module_state_reg[0]), .QN(n3422) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n3441), .Q(Op_MX[19]), .QN(n585) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n3442), .Q(n419), .QN(n584) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n3442), .Q(Op_MX[11]), .QN(n574) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n3442), .Q(Op_MX[10]), .QN(n3414) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(
n3443), .Q(Op_MX[1]), .QN(n582) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n3443), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n306), .CK(clk), .RN(n3445),
.Q(Add_result[0]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n3447), .Q(Op_MY[20]), .QN(n438) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n3447), .Q(Op_MY[15]), .QN(n550) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n3448), .Q(Op_MY[5]), .QN(n568) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n255), .CK(clk), .RN(
n3439), .Q(P_Sgf[40]), .QN(n531) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n238), .CK(clk), .RN(
n3437), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n237), .CK(clk), .RN(
n3435), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n229), .CK(clk), .RN(
n3436), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n227), .CK(clk), .RN(
n3436), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n225), .CK(clk), .RN(
n3436), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n224), .CK(clk), .RN(
n3436), .Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n217), .CK(clk), .RN(
n3435), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n215), .CK(clk), .RN(
n3435), .Q(P_Sgf[0]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n307), .CK(clk),
.RN(n2405), .Q(Sgf_normalized_result[23]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n3461), .CK(clk), .Q(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_15_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_Result[1]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_55_n1), .CK(clk), .Q(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(Sgf_operation_EVEN1_Q_left[1]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]) );
CMPR32X2TS DP_OP_36J23_129_4699_U8 ( .A(DP_OP_36J23_129_4699_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J23_129_4699_n8), .CO(
DP_OP_36J23_129_4699_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J23_129_4699_U7 ( .A(DP_OP_36J23_129_4699_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J23_129_4699_n7), .CO(
DP_OP_36J23_129_4699_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J23_129_4699_U6 ( .A(DP_OP_36J23_129_4699_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J23_129_4699_n6), .CO(
DP_OP_36J23_129_4699_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J23_129_4699_U5 ( .A(DP_OP_36J23_129_4699_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J23_129_4699_n5), .CO(
DP_OP_36J23_129_4699_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J23_129_4699_U4 ( .A(DP_OP_36J23_129_4699_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J23_129_4699_n4), .CO(
DP_OP_36J23_129_4699_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J23_129_4699_U3 ( .A(DP_OP_36J23_129_4699_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J23_129_4699_n3), .CO(
DP_OP_36J23_129_4699_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS intadd_54_U10 ( .A(intadd_54_A_0_), .B(intadd_54_B_0_), .C(
intadd_54_CI), .CO(intadd_54_n9), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2)
);
CMPR32X2TS intadd_54_U8 ( .A(mult_x_59_n37), .B(intadd_54_B_2_), .C(
intadd_54_n8), .CO(intadd_54_n7), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4)
);
CMPR32X2TS intadd_54_U7 ( .A(mult_x_59_n36), .B(mult_x_59_n30), .C(
intadd_54_n7), .CO(intadd_54_n6), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5)
);
CMPR32X2TS intadd_54_U6 ( .A(mult_x_59_n29), .B(mult_x_59_n23), .C(
intadd_54_n6), .CO(intadd_54_n5), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6)
);
CMPR32X2TS intadd_54_U4 ( .A(mult_x_59_n17), .B(mult_x_59_n15), .C(
intadd_54_n4), .CO(intadd_54_n3), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8)
);
CMPR32X2TS intadd_54_U2 ( .A(intadd_54_A_8_), .B(intadd_54_B_8_), .C(
intadd_54_n2), .CO(intadd_54_n1), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10)
);
CMPR32X2TS intadd_55_U10 ( .A(intadd_55_A_0_), .B(intadd_55_B_0_), .C(
intadd_55_CI), .CO(intadd_55_n9), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2)
);
CMPR32X2TS intadd_55_U9 ( .A(intadd_55_A_1_), .B(intadd_55_B_1_), .C(
intadd_55_n9), .CO(intadd_55_n8), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3)
);
CMPR32X2TS intadd_55_U8 ( .A(mult_x_58_n37), .B(intadd_55_B_2_), .C(
intadd_55_n8), .CO(intadd_55_n7), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4)
);
CMPR32X2TS intadd_55_U7 ( .A(mult_x_58_n36), .B(mult_x_58_n30), .C(
intadd_55_n7), .CO(intadd_55_n6), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5)
);
CMPR32X2TS intadd_55_U6 ( .A(mult_x_58_n29), .B(mult_x_58_n23), .C(
intadd_55_n6), .CO(intadd_55_n5), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6)
);
CMPR32X2TS intadd_55_U5 ( .A(mult_x_58_n22), .B(mult_x_58_n18), .C(
intadd_55_n5), .CO(intadd_55_n4), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7)
);
CMPR32X2TS intadd_55_U4 ( .A(mult_x_58_n17), .B(mult_x_58_n15), .C(
intadd_55_n4), .CO(intadd_55_n3), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8)
);
CMPR32X2TS intadd_55_U2 ( .A(intadd_55_A_8_), .B(intadd_55_B_8_), .C(
intadd_55_n2), .CO(intadd_55_n1), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10)
);
CMPR32X2TS intadd_56_U10 ( .A(intadd_56_A_0_), .B(intadd_56_B_0_), .C(
intadd_56_CI), .CO(intadd_56_n9), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2)
);
CMPR32X2TS intadd_56_U8 ( .A(mult_x_57_n37), .B(intadd_56_B_2_), .C(
intadd_56_n8), .CO(intadd_56_n7), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4)
);
CMPR32X2TS intadd_56_U7 ( .A(mult_x_57_n36), .B(mult_x_57_n30), .C(
intadd_56_n7), .CO(intadd_56_n6), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5)
);
CMPR32X2TS intadd_56_U6 ( .A(mult_x_57_n29), .B(mult_x_57_n23), .C(
intadd_56_n6), .CO(intadd_56_n5), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6)
);
CMPR32X2TS intadd_56_U4 ( .A(mult_x_57_n17), .B(mult_x_57_n15), .C(
intadd_56_n4), .CO(intadd_56_n3), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8)
);
CMPR32X2TS intadd_56_U2 ( .A(intadd_56_A_8_), .B(intadd_56_B_8_), .C(
intadd_56_n2), .CO(intadd_56_n1), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10)
);
CMPR32X2TS intadd_57_U9 ( .A(intadd_57_A_0_), .B(intadd_57_B_0_), .C(n3417),
.CO(intadd_57_n8), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
CMPR32X2TS intadd_57_U7 ( .A(mult_x_56_n37), .B(intadd_57_B_2_), .C(
intadd_57_n7), .CO(intadd_57_n6), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_57_U6 ( .A(mult_x_56_n36), .B(mult_x_56_n30), .C(
intadd_57_n6), .CO(intadd_57_n5), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_57_U5 ( .A(mult_x_56_n29), .B(mult_x_56_n23), .C(
intadd_57_n5), .CO(intadd_57_n4), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_57_U4 ( .A(mult_x_56_n22), .B(mult_x_56_n18), .C(
intadd_57_n4), .CO(intadd_57_n3), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_57_U3 ( .A(mult_x_56_n17), .B(mult_x_56_n15), .C(
intadd_57_n3), .CO(intadd_57_n2), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR42X1TS DP_OP_157J23_126_5719_U122 ( .A(DP_OP_157J23_126_5719_n137), .B(
DP_OP_157J23_126_5719_n180), .C(DP_OP_157J23_126_5719_n187), .D(
DP_OP_157J23_126_5719_n134), .ICI(DP_OP_157J23_126_5719_n131), .S(
DP_OP_157J23_126_5719_n129), .ICO(DP_OP_157J23_126_5719_n127), .CO(
DP_OP_157J23_126_5719_n128) );
CMPR42X2TS DP_OP_157J23_126_5719_U119 ( .A(DP_OP_157J23_126_5719_n150), .B(
DP_OP_157J23_126_5719_n157), .C(DP_OP_157J23_126_5719_n185), .D(
DP_OP_157J23_126_5719_n164), .ICI(DP_OP_157J23_126_5719_n124), .S(
DP_OP_157J23_126_5719_n120), .ICO(DP_OP_157J23_126_5719_n118), .CO(
DP_OP_157J23_126_5719_n119) );
CMPR42X2TS DP_OP_157J23_126_5719_U115 ( .A(DP_OP_157J23_126_5719_n170), .B(
DP_OP_157J23_126_5719_n118), .C(DP_OP_157J23_126_5719_n112), .D(
DP_OP_157J23_126_5719_n119), .ICI(DP_OP_157J23_126_5719_n115), .S(
DP_OP_157J23_126_5719_n110), .ICO(DP_OP_157J23_126_5719_n108), .CO(
DP_OP_157J23_126_5719_n109) );
CMPR42X1TS DP_OP_159J23_128_5719_U125 ( .A(DP_OP_159J23_128_5719_n174), .B(
DP_OP_159J23_128_5719_n138), .C(DP_OP_159J23_128_5719_n141), .D(
DP_OP_159J23_128_5719_n181), .ICI(DP_OP_159J23_128_5719_n188), .S(
DP_OP_159J23_128_5719_n136), .ICO(DP_OP_159J23_128_5719_n134), .CO(
DP_OP_159J23_128_5719_n135) );
CMPR42X1TS DP_OP_159J23_128_5719_U122 ( .A(DP_OP_159J23_128_5719_n137), .B(
DP_OP_159J23_128_5719_n180), .C(DP_OP_159J23_128_5719_n187), .D(
DP_OP_159J23_128_5719_n134), .ICI(DP_OP_159J23_128_5719_n131), .S(
DP_OP_159J23_128_5719_n129), .ICO(DP_OP_159J23_128_5719_n127), .CO(
DP_OP_159J23_128_5719_n128) );
CMPR42X1TS DP_OP_159J23_128_5719_U121 ( .A(DP_OP_159J23_128_5719_n151), .B(
DP_OP_159J23_128_5719_n158), .C(DP_OP_159J23_128_5719_n132), .D(
DP_OP_159J23_128_5719_n165), .ICI(DP_OP_159J23_128_5719_n130), .S(
DP_OP_159J23_128_5719_n126), .ICO(DP_OP_159J23_128_5719_n124), .CO(
DP_OP_159J23_128_5719_n125) );
CMPR42X2TS DP_OP_159J23_128_5719_U119 ( .A(DP_OP_159J23_128_5719_n150), .B(
DP_OP_159J23_128_5719_n157), .C(DP_OP_159J23_128_5719_n185), .D(
DP_OP_159J23_128_5719_n164), .ICI(DP_OP_159J23_128_5719_n124), .S(
DP_OP_159J23_128_5719_n120), .ICO(DP_OP_159J23_128_5719_n118), .CO(
DP_OP_159J23_128_5719_n119) );
CMPR42X2TS DP_OP_159J23_128_5719_U115 ( .A(DP_OP_159J23_128_5719_n170), .B(
DP_OP_159J23_128_5719_n118), .C(DP_OP_159J23_128_5719_n112), .D(
DP_OP_159J23_128_5719_n119), .ICI(DP_OP_159J23_128_5719_n115), .S(
DP_OP_159J23_128_5719_n110), .ICO(DP_OP_159J23_128_5719_n108), .CO(
DP_OP_159J23_128_5719_n109) );
CMPR42X2TS DP_OP_159J23_128_5719_U113 ( .A(DP_OP_159J23_128_5719_n162), .B(
DP_OP_159J23_128_5719_n155), .C(DP_OP_159J23_128_5719_n107), .D(
DP_OP_159J23_128_5719_n111), .ICI(DP_OP_159J23_128_5719_n108), .S(
DP_OP_159J23_128_5719_n105), .ICO(DP_OP_159J23_128_5719_n103), .CO(
DP_OP_159J23_128_5719_n104) );
CMPR42X2TS DP_OP_159J23_128_5719_U112 ( .A(DP_OP_159J23_128_5719_n161), .B(
DP_OP_159J23_128_5719_n154), .C(DP_OP_159J23_128_5719_n147), .D(
DP_OP_159J23_128_5719_n106), .ICI(DP_OP_159J23_128_5719_n103), .S(
DP_OP_159J23_128_5719_n102), .ICO(DP_OP_159J23_128_5719_n100), .CO(
DP_OP_159J23_128_5719_n101) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[4]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n254), .CK(clk), .RN(
n3439), .Q(P_Sgf[39]), .QN(n541) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n258), .CK(clk), .RN(
n3439), .Q(P_Sgf[43]), .QN(n542) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n260), .CK(clk), .RN(
n3439), .Q(P_Sgf[45]), .QN(n543) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n257), .CK(clk), .RN(
n3439), .Q(P_Sgf[42]), .QN(n545) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n253), .CK(clk), .RN(
n3439), .Q(P_Sgf[38]), .QN(n546) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n259), .CK(clk), .RN(
n3439), .Q(P_Sgf[44]), .QN(n547) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[5]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[3]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_Result[4]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_Result[5]) );
DFFHQX8TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n3459), .CK(clk), .Q(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_Result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n198), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[7]), .QN(n3431) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n201), .CK(clk),
.RN(n3450), .Q(Sgf_normalized_result[10]), .QN(n3430) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n197), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[6]), .QN(n3427) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n195), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[4]), .QN(n3426) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n196), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[5]), .QN(n3418) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n200), .CK(clk),
.RN(n3451), .Q(Sgf_normalized_result[9]), .QN(n3416) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n194), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[3]), .QN(n3415) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n3440), .Q(FSM_selector_A),
.QN(n3428) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n199), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[8]), .QN(n3408) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n3449), .Q(
FSM_selector_B[1]), .QN(n3406) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n190),
.CK(clk), .RN(n3453), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n189),
.CK(clk), .RN(n3454), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n188),
.CK(clk), .RN(n3454), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n187),
.CK(clk), .RN(n3454), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n186),
.CK(clk), .RN(n3454), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n185),
.CK(clk), .RN(n3454), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n184),
.CK(clk), .RN(n3454), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n183),
.CK(clk), .RN(n3454), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n182),
.CK(clk), .RN(n3454), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n181),
.CK(clk), .RN(n3454), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n180),
.CK(clk), .RN(n3454), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n179),
.CK(clk), .RN(n3455), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n178),
.CK(clk), .RN(n3455), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n177),
.CK(clk), .RN(n3455), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n176),
.CK(clk), .RN(n3455), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n175),
.CK(clk), .RN(n3455), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n174),
.CK(clk), .RN(n3455), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n173),
.CK(clk), .RN(n3455), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n172),
.CK(clk), .RN(n3455), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n171),
.CK(clk), .RN(n3455), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n170),
.CK(clk), .RN(n3455), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n169),
.CK(clk), .RN(n3456), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n167),
.CK(clk), .RN(n3456), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n270),
.CK(clk), .RN(n3453), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n269),
.CK(clk), .RN(n3453), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n268),
.CK(clk), .RN(n3453), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n267),
.CK(clk), .RN(n3453), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n266),
.CK(clk), .RN(n3453), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n265),
.CK(clk), .RN(n3453), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n264),
.CK(clk), .RN(n3453), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n263),
.CK(clk), .RN(n3453), .Q(final_result_ieee[30]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n271), .CK(clk), .RN(n3450), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n272), .CK(clk), .RN(n3452),
.Q(underflow_flag), .QN(n3434) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n281), .CK(clk), .RN(n3449),
.Q(exp_oper_result[8]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]) );
CMPR32X2TS intadd_57_U8 ( .A(n3419), .B(intadd_57_B_1_), .C(intadd_57_n8),
.CO(intadd_57_n7), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_54_U9 ( .A(n3421), .B(intadd_54_B_1_), .C(intadd_54_n9),
.CO(intadd_54_n8), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3)
);
CMPR32X2TS intadd_54_U5 ( .A(mult_x_59_n22), .B(mult_x_59_n18), .C(
intadd_54_n5), .CO(intadd_54_n4), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7)
);
CMPR32X2TS intadd_56_U9 ( .A(n3420), .B(intadd_56_B_1_), .C(intadd_56_n9),
.CO(intadd_56_n8), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3)
);
CMPR32X2TS intadd_56_U5 ( .A(mult_x_57_n22), .B(mult_x_57_n18), .C(
intadd_56_n5), .CO(intadd_56_n4), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7)
);
CMPR32X2TS intadd_56_U3 ( .A(mult_x_57_n14), .B(intadd_56_B_7_), .C(
intadd_56_n3), .CO(intadd_56_n2), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9)
);
CMPR32X2TS intadd_55_U3 ( .A(mult_x_58_n14), .B(intadd_55_B_7_), .C(
intadd_55_n3), .CO(intadd_55_n2), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9)
);
CMPR32X2TS intadd_54_U3 ( .A(mult_x_59_n14), .B(intadd_54_B_7_), .C(
intadd_54_n3), .CO(intadd_54_n2), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9)
);
CMPR42X2TS DP_OP_156J23_125_3370_U241 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_156J23_125_3370_n247), .D(DP_OP_156J23_125_3370_n280), .ICI(
DP_OP_156J23_125_3370_n304), .S(DP_OP_156J23_125_3370_n246), .ICO(
DP_OP_156J23_125_3370_n244), .CO(DP_OP_156J23_125_3370_n245) );
CMPR42X2TS DP_OP_156J23_125_3370_U240 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_156J23_125_3370_n244), .D(DP_OP_156J23_125_3370_n279), .ICI(
DP_OP_156J23_125_3370_n303), .S(DP_OP_156J23_125_3370_n243), .ICO(
DP_OP_156J23_125_3370_n241), .CO(DP_OP_156J23_125_3370_n242) );
CMPR42X2TS DP_OP_156J23_125_3370_U239 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_156J23_125_3370_n241), .D(DP_OP_156J23_125_3370_n278), .ICI(
DP_OP_156J23_125_3370_n302), .S(DP_OP_156J23_125_3370_n240), .ICO(
DP_OP_156J23_125_3370_n238), .CO(DP_OP_156J23_125_3370_n239) );
CMPR42X2TS DP_OP_156J23_125_3370_U238 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_156J23_125_3370_n238), .D(DP_OP_156J23_125_3370_n277), .ICI(
DP_OP_156J23_125_3370_n301), .S(DP_OP_156J23_125_3370_n237), .ICO(
DP_OP_156J23_125_3370_n235), .CO(DP_OP_156J23_125_3370_n236) );
CMPR42X2TS DP_OP_156J23_125_3370_U237 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_156J23_125_3370_n235), .D(DP_OP_156J23_125_3370_n276), .ICI(
DP_OP_156J23_125_3370_n300), .S(DP_OP_156J23_125_3370_n234), .ICO(
DP_OP_156J23_125_3370_n232), .CO(DP_OP_156J23_125_3370_n233) );
CMPR42X2TS DP_OP_156J23_125_3370_U235 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_156J23_125_3370_n229), .D(DP_OP_156J23_125_3370_n274), .ICI(
n1442), .S(DP_OP_156J23_125_3370_n228), .ICO(
DP_OP_156J23_125_3370_n226), .CO(DP_OP_156J23_125_3370_n227) );
CMPR42X2TS DP_OP_156J23_125_3370_U234 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_156J23_125_3370_n273), .D(DP_OP_156J23_125_3370_n297), .ICI(
DP_OP_156J23_125_3370_n226), .S(DP_OP_156J23_125_3370_n225), .ICO(
DP_OP_156J23_125_3370_n223), .CO(DP_OP_156J23_125_3370_n224) );
CMPR42X2TS DP_OP_156J23_125_3370_U233 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(n576), .D(n2377), .ICI(DP_OP_156J23_125_3370_n223), .S(DP_OP_156J23_125_3370_n222), .ICO(
DP_OP_156J23_125_3370_n220), .CO(DP_OP_156J23_125_3370_n221) );
CMPR42X2TS DP_OP_156J23_125_3370_U232 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(n552), .D(
DP_OP_156J23_125_3370_n295), .ICI(DP_OP_156J23_125_3370_n220), .S(
DP_OP_156J23_125_3370_n219), .ICO(DP_OP_156J23_125_3370_n217), .CO(
DP_OP_156J23_125_3370_n218) );
CMPR42X2TS DP_OP_156J23_125_3370_U231 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_156J23_125_3370_n270), .D(DP_OP_156J23_125_3370_n294), .ICI(
DP_OP_156J23_125_3370_n217), .S(DP_OP_156J23_125_3370_n216), .ICO(
DP_OP_156J23_125_3370_n214), .CO(DP_OP_156J23_125_3370_n215) );
CMPR42X2TS DP_OP_156J23_125_3370_U230 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(n428), .D(
DP_OP_156J23_125_3370_n293), .ICI(DP_OP_156J23_125_3370_n214), .S(
DP_OP_156J23_125_3370_n213), .ICO(DP_OP_156J23_125_3370_n211), .CO(
DP_OP_156J23_125_3370_n212) );
CMPR42X2TS DP_OP_156J23_125_3370_U229 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
DP_OP_156J23_125_3370_n268), .D(DP_OP_156J23_125_3370_n292), .ICI(
DP_OP_156J23_125_3370_n211), .S(DP_OP_156J23_125_3370_n210), .ICO(
DP_OP_156J23_125_3370_n208), .CO(DP_OP_156J23_125_3370_n209) );
CMPR42X2TS DP_OP_156J23_125_3370_U228 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(
DP_OP_156J23_125_3370_n267), .D(n399), .ICI(DP_OP_156J23_125_3370_n208), .S(DP_OP_156J23_125_3370_n207), .ICO(DP_OP_156J23_125_3370_n205), .CO(
DP_OP_156J23_125_3370_n206) );
CMPR42X2TS DP_OP_156J23_125_3370_U227 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_156J23_125_3370_n266), .D(DP_OP_156J23_125_3370_n290), .ICI(
DP_OP_156J23_125_3370_n205), .S(DP_OP_156J23_125_3370_n204), .ICO(
DP_OP_156J23_125_3370_n202), .CO(DP_OP_156J23_125_3370_n203) );
CMPR42X2TS DP_OP_158J23_127_356_U445 ( .A(DP_OP_158J23_127_356_n513), .B(
DP_OP_158J23_127_356_n519), .C(DP_OP_158J23_127_356_n525), .D(
DP_OP_158J23_127_356_n487), .ICI(DP_OP_158J23_127_356_n490), .S(
DP_OP_158J23_127_356_n485), .ICO(DP_OP_158J23_127_356_n483), .CO(
DP_OP_158J23_127_356_n484) );
CMPR42X2TS DP_OP_158J23_127_356_U440 ( .A(DP_OP_158J23_127_356_n511), .B(
DP_OP_158J23_127_356_n505), .C(DP_OP_158J23_127_356_n479), .D(
DP_OP_158J23_127_356_n476), .ICI(DP_OP_158J23_127_356_n475), .S(
DP_OP_158J23_127_356_n472), .ICO(DP_OP_158J23_127_356_n470), .CO(
DP_OP_158J23_127_356_n471) );
CMPR42X2TS DP_OP_158J23_127_356_U437 ( .A(DP_OP_158J23_127_356_n469), .B(
DP_OP_158J23_127_356_n473), .C(DP_OP_158J23_127_356_n467), .D(
DP_OP_158J23_127_356_n470), .ICI(DP_OP_158J23_127_356_n474), .S(
DP_OP_158J23_127_356_n465), .ICO(DP_OP_158J23_127_356_n463), .CO(
DP_OP_158J23_127_356_n464) );
CMPR42X2TS DP_OP_158J23_127_356_U156 ( .A(DP_OP_158J23_127_356_n262), .B(
DP_OP_158J23_127_356_n186), .C(DP_OP_158J23_127_356_n246), .D(
DP_OP_158J23_127_356_n254), .ICI(DP_OP_158J23_127_356_n183), .S(
DP_OP_158J23_127_356_n181), .ICO(DP_OP_158J23_127_356_n179), .CO(
DP_OP_158J23_127_356_n180) );
CMPR42X2TS DP_OP_158J23_127_356_U154 ( .A(DP_OP_158J23_127_356_n229), .B(
DP_OP_158J23_127_356_n184), .C(DP_OP_158J23_127_356_n178), .D(
DP_OP_158J23_127_356_n237), .ICI(DP_OP_158J23_127_356_n253), .S(
DP_OP_158J23_127_356_n176), .ICO(DP_OP_158J23_127_356_n174), .CO(
DP_OP_158J23_127_356_n175) );
CMPR42X2TS DP_OP_158J23_127_356_U150 ( .A(DP_OP_158J23_127_356_n228), .B(
DP_OP_158J23_127_356_n174), .C(DP_OP_158J23_127_356_n244), .D(
DP_OP_158J23_127_356_n168), .ICI(DP_OP_158J23_127_356_n175), .S(
DP_OP_158J23_127_356_n166), .ICO(DP_OP_158J23_127_356_n164), .CO(
DP_OP_158J23_127_356_n165) );
CMPR42X2TS DP_OP_158J23_127_356_U149 ( .A(DP_OP_158J23_127_356_n236), .B(
DP_OP_158J23_127_356_n171), .C(DP_OP_158J23_127_356_n260), .D(
DP_OP_158J23_127_356_n252), .ICI(DP_OP_158J23_127_356_n166), .S(
DP_OP_158J23_127_356_n163), .ICO(DP_OP_158J23_127_356_n161), .CO(
DP_OP_158J23_127_356_n162) );
CMPR42X2TS DP_OP_158J23_127_356_U148 ( .A(DP_OP_158J23_127_356_n203), .B(
DP_OP_158J23_127_356_n211), .C(DP_OP_158J23_127_356_n169), .D(
DP_OP_158J23_127_356_n219), .ICI(DP_OP_158J23_127_356_n227), .S(
DP_OP_158J23_127_356_n160), .ICO(DP_OP_158J23_127_356_n158), .CO(
DP_OP_158J23_127_356_n159) );
CMPR42X2TS DP_OP_158J23_127_356_U147 ( .A(DP_OP_158J23_127_356_n235), .B(
DP_OP_158J23_127_356_n167), .C(DP_OP_158J23_127_356_n259), .D(
DP_OP_158J23_127_356_n164), .ICI(DP_OP_158J23_127_356_n243), .S(
DP_OP_158J23_127_356_n157), .ICO(DP_OP_158J23_127_356_n155), .CO(
DP_OP_158J23_127_356_n156) );
CMPR42X2TS DP_OP_158J23_127_356_U143 ( .A(DP_OP_158J23_127_356_n151), .B(
DP_OP_158J23_127_356_n250), .C(DP_OP_158J23_127_356_n149), .D(
DP_OP_158J23_127_356_n234), .ICI(DP_OP_158J23_127_356_n159), .S(
DP_OP_158J23_127_356_n147), .ICO(DP_OP_158J23_127_356_n145), .CO(
DP_OP_158J23_127_356_n146) );
CMPR42X2TS DP_OP_158J23_127_356_U142 ( .A(DP_OP_158J23_127_356_n242), .B(
DP_OP_158J23_127_356_n155), .C(DP_OP_158J23_127_356_n156), .D(
DP_OP_158J23_127_356_n152), .ICI(DP_OP_158J23_127_356_n147), .S(
DP_OP_158J23_127_356_n144), .ICO(DP_OP_158J23_127_356_n142), .CO(
DP_OP_158J23_127_356_n143) );
CMPR42X2TS DP_OP_158J23_127_356_U140 ( .A(DP_OP_158J23_127_356_n150), .B(
DP_OP_158J23_127_356_n241), .C(DP_OP_158J23_127_356_n141), .D(
DP_OP_158J23_127_356_n148), .ICI(DP_OP_158J23_127_356_n145), .S(
DP_OP_158J23_127_356_n139), .ICO(DP_OP_158J23_127_356_n137), .CO(
DP_OP_158J23_127_356_n138) );
CMPR42X2TS DP_OP_158J23_127_356_U139 ( .A(DP_OP_158J23_127_356_n233), .B(
DP_OP_158J23_127_356_n225), .C(DP_OP_158J23_127_356_n146), .D(
DP_OP_158J23_127_356_n139), .ICI(DP_OP_158J23_127_356_n142), .S(
DP_OP_158J23_127_356_n136), .ICO(DP_OP_158J23_127_356_n134), .CO(
DP_OP_158J23_127_356_n135) );
CMPR42X2TS DP_OP_158J23_127_356_U138 ( .A(DP_OP_158J23_127_356_n200), .B(
DP_OP_158J23_127_356_n208), .C(DP_OP_158J23_127_356_n232), .D(
DP_OP_158J23_127_356_n140), .ICI(DP_OP_158J23_127_356_n216), .S(
DP_OP_158J23_127_356_n133), .ICO(DP_OP_158J23_127_356_n131), .CO(
DP_OP_158J23_127_356_n132) );
CMPR42X2TS DP_OP_158J23_127_356_U137 ( .A(DP_OP_158J23_127_356_n224), .B(
DP_OP_158J23_127_356_n137), .C(DP_OP_158J23_127_356_n138), .D(
DP_OP_158J23_127_356_n133), .ICI(DP_OP_158J23_127_356_n134), .S(
DP_OP_158J23_127_356_n130), .ICO(DP_OP_158J23_127_356_n128), .CO(
DP_OP_158J23_127_356_n129) );
CMPR42X2TS DP_OP_158J23_127_356_U134 ( .A(DP_OP_158J23_127_356_n214), .B(
DP_OP_158J23_127_356_n198), .C(DP_OP_158J23_127_356_n206), .D(
DP_OP_158J23_127_356_n126), .ICI(DP_OP_158J23_127_356_n123), .S(
DP_OP_158J23_127_356_n122), .ICO(DP_OP_158J23_127_356_n120), .CO(
DP_OP_158J23_127_356_n121) );
DFFHQX8TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]) );
CMPR42X2TS DP_OP_157J23_126_5719_U118 ( .A(DP_OP_157J23_126_5719_n178), .B(
DP_OP_157J23_126_5719_n171), .C(DP_OP_157J23_126_5719_n121), .D(
DP_OP_157J23_126_5719_n125), .ICI(DP_OP_157J23_126_5719_n120), .S(
DP_OP_157J23_126_5719_n117), .ICO(DP_OP_157J23_126_5719_n115), .CO(
DP_OP_157J23_126_5719_n116) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n3448), .Q(n3412), .QN(n577) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(
n3443), .Q(Op_MX[2]), .QN(n3403) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n3443), .Q(Op_MX[3]), .QN(n417) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(
n3443), .Q(Op_MX[0]), .QN(n549) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n3447), .Q(Op_MY[12]), .QN(n435) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n3441), .Q(Op_MX[15]), .QN(n583) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n3448), .Q(Op_MY[3]), .QN(n393) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n3447), .Q(Op_MY[14]), .QN(n580) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n3441), .Q(Op_MX[18]), .QN(n573) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n3441), .Q(Op_MX[17]), .QN(n566) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n3442), .Q(Op_MX[6]), .QN(n562) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n3448), .Q(Op_MY[4]), .QN(n557) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n3447), .Q(Op_MY[17]), .QN(n548) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n191), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n193), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n202), .CK(clk),
.RN(n3450), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n204), .CK(clk),
.RN(n3451), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n206), .CK(clk),
.RN(n3450), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n208), .CK(clk),
.RN(n3451), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n210), .CK(clk),
.RN(n3451), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n212), .CK(clk),
.RN(n2405), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n203), .CK(clk),
.RN(n3450), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n205), .CK(clk),
.RN(n2441), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n207), .CK(clk),
.RN(n2441), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n209), .CK(clk),
.RN(n2441), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n211), .CK(clk),
.RN(n3450), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n213), .CK(clk),
.RN(n3451), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n380), .CK(clk), .RN(
n3437), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n3440), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n3440), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n3446), .Q(Op_MY[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n3446), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n3441), .Q(Op_MX[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n3446), .Q(Op_MY[28]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n274), .CK(clk), .RN(n2405),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n276), .CK(clk), .RN(n3449),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n277), .CK(clk), .RN(n3449),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n278), .CK(clk), .RN(n3449),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n279), .CK(clk), .RN(n3449),
.Q(exp_oper_result[1]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n216), .CK(clk), .RN(
n3436), .Q(P_Sgf[1]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n228), .CK(clk), .RN(
n3437), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n235), .CK(clk), .RN(
n3435), .Q(P_Sgf[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n192), .CK(clk),
.RN(n3452), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n3440), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n3440), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n3440), .Q(Op_MX[29]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n3440), .Q(Op_MX[25]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n284), .CK(clk), .RN(n3443),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n285), .CK(clk), .RN(n3443),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n286), .CK(clk), .RN(n3443),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n287), .CK(clk), .RN(n3443),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n288), .CK(clk), .RN(n3443),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n289), .CK(clk), .RN(n3444),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n290), .CK(clk), .RN(n3444),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n291), .CK(clk), .RN(n3444),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n292), .CK(clk), .RN(n3444),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n293), .CK(clk), .RN(n3444),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n294), .CK(clk), .RN(n3444),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n295), .CK(clk), .RN(n3444),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n296), .CK(clk), .RN(n3444),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n297), .CK(clk), .RN(n3444),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n298), .CK(clk), .RN(n3444),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n299), .CK(clk), .RN(n3445),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n300), .CK(clk), .RN(n3445),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n301), .CK(clk), .RN(n3445),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n302), .CK(clk), .RN(n3445),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n303), .CK(clk), .RN(n3445),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n304), .CK(clk), .RN(n3445),
.Q(Add_result[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n305), .CK(clk), .RN(n3445),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n283), .CK(clk), .RN(n3445),
.Q(Add_result[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n3446), .Q(Op_MY[26]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n280), .CK(clk), .RN(n3449),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n275), .CK(clk), .RN(n3450),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n273), .CK(clk), .RN(n3451),
.Q(exp_oper_result[7]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n3446), .Q(Op_MY[27]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n3446), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n3446), .Q(Op_MY[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n3446), .Q(Op_MY[24]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n252), .CK(clk), .RN(
n3439), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n251), .CK(clk), .RN(
n3439), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n250), .CK(clk), .RN(
n3438), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n249), .CK(clk), .RN(
n3438), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n248), .CK(clk), .RN(
n3438), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n247), .CK(clk), .RN(
n3438), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n246), .CK(clk), .RN(
n3438), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n256), .CK(clk), .RN(
n3439), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n245), .CK(clk), .RN(
n3438), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n244), .CK(clk), .RN(
n3438), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n243), .CK(clk), .RN(
n3438), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n242), .CK(clk), .RN(
n3438), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n241), .CK(clk), .RN(
n3438), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n240), .CK(clk), .RN(
n3437), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n239), .CK(clk), .RN(
n3437), .Q(P_Sgf[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n3447), .Q(Op_MY[11]), .QN(n575) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n233), .CK(clk), .RN(
n3435), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n230), .CK(clk), .RN(
n3437), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n218), .CK(clk), .RN(
n3436), .Q(P_Sgf[3]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n236), .CK(clk), .RN(
n3435), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n232), .CK(clk), .RN(
n3437), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n220), .CK(clk), .RN(
n3436), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n234), .CK(clk), .RN(
n3435), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n231), .CK(clk), .RN(
n3436), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n219), .CK(clk), .RN(
n3436), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n223), .CK(clk), .RN(
n3436), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n222), .CK(clk), .RN(
n3435), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n221), .CK(clk), .RN(
n3435), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n226), .CK(clk), .RN(
n3435), .Q(P_Sgf[11]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n3441), .Q(Op_MX[16]), .QN(n424) );
DFFX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11),
.CK(clk), .QN(DP_OP_153J23_122_3500_n147) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n3448), .Q(Op_MY[2]), .QN(n446) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n3441), .Q(Op_MX[21]), .QN(n397) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[2]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n3442), .Q(n414), .QN(n3402) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(
n3442), .Q(Op_MX[13]), .QN(n431) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n3448), .Q(n423), .QN(n429) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n3448), .Q(n420), .QN(n426) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n3442), .Q(Op_MX[8]), .QN(n425) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n3441), .Q(n3411) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n3448), .Q(Op_MY[9]), .QN(n415) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n3447), .Q(n412), .QN(n3405) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n3448), .Q(n411), .QN(n596) );
DFFRX1TS FS_Module_state_reg_reg_1_ ( .D(n377), .CK(clk), .RN(n3437), .Q(
FS_Module_state_reg[1]), .QN(n3410) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n3441), .Q(Op_MX[20]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n3425), .CK(clk), .Q(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]) );
DFFHQX1TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]) );
DFFHQX1TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]) );
DFFHQX1TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]) );
DFFHQX1TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]) );
DFFHQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n556), .CK(clk), .Q(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]) );
DFFHQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]) );
DFFHQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]) );
DFFHQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]) );
DFFHQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n1856), .CK(clk), .Q(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
DFFHQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
DFFHQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n3458), .CK(clk), .Q(Sgf_operation_Result[0]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_56_n1), .CK(clk), .Q(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]) );
DFFQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]) );
DFFHQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]) );
DFFHQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n3424), .CK(clk), .Q(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3]) );
DFFHQX1TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]) );
DFFHQX1TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]) );
DFFHQX1TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]) );
DFFHQX1TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]) );
DFFHQX1TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n261), .CK(clk), .RN(
n3463), .Q(P_Sgf[46]), .QN(n3401) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n214), .CK(clk), .RN(n2441), .Q(FSM_selector_C),
.QN(n3423) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2),
.CK(clk), .Q(Sgf_operation_Result[2]) );
DFFRX1TS FS_Module_state_reg_reg_3_ ( .D(n379), .CK(clk), .RN(n3463), .Q(
FS_Module_state_reg[3]), .QN(n3462) );
DFFSX1TS Sel_B_Q_reg_0_ ( .D(n3457), .CK(clk), .SN(n3449), .Q(n3413), .QN(
FSM_selector_B[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n3448), .Q(Op_MY[6]), .QN(n3409) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n262),
.CK(clk), .RN(n3453), .Q(final_result_ieee[31]), .QN(n3433) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n3449), .Q(zero_flag), .QN(n3432) );
DFFRXLTS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n282), .CK(clk), .RN(
n3445), .Q(FSM_add_overflow_flag), .QN(n3429) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n3440), .Q(Op_MX[24]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n376), .CK(clk), .RN(n3437), .Q(
FS_Module_state_reg[2]), .QN(n3407) );
DFFX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n3460), .CK(clk), .Q(Sgf_operation_EVEN1_Q_left[0]), .QN(
DP_OP_154J23_123_2814_n140) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n3446), .Q(n395), .QN(n430) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n3442), .Q(Op_MX[7]), .QN(n457) );
DFFQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n565), .CK(clk), .Q(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n3442), .Q(Op_MX[5]), .QN(n454) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n3442), .Q(n394), .QN(n567) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]) );
DFFHQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]) );
DFFHQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX4TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]) );
DFFHQX2TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]) );
DFFHQX2TS Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]) );
DFFHQX1TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
DFFHQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
DFFQX4TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_54_n1), .CK(clk), .Q(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]) );
DFFQX1TS Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11),
.CK(clk), .Q(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]) );
DFFQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
DFFQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
DFFQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
DFFQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
DFFQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
DFFHQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
DFFHQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
DFFQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]) );
DFFQX4TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
DFFQX2TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6),
.CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(
n3441), .Q(n391) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(clk), .RN(
n3449), .Q(Op_MY[0]), .QN(n571) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n3447), .Q(Op_MY[16]), .QN(n551) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(clk), .RN(
n3447), .Q(n413), .QN(n432) );
DFFQX1TS Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_14_ (
.D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14), .CK(clk), .Q(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n3446), .Q(n390), .QN(n416) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(clk), .RN(
n3447), .Q(n3404), .QN(n398) );
CMPR32X2TS DP_OP_36J23_129_4699_U10 ( .A(S_Oper_A_exp[0]), .B(n2422), .C(
DP_OP_36J23_129_4699_n22), .CO(DP_OP_36J23_129_4699_n9), .S(
Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J23_129_4699_U9 ( .A(DP_OP_36J23_129_4699_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J23_129_4699_n9), .CO(
DP_OP_36J23_129_4699_n8), .S(Exp_module_Data_S[1]) );
CMPR42X1TS DP_OP_157J23_126_5719_U113 ( .A(DP_OP_157J23_126_5719_n162), .B(
DP_OP_157J23_126_5719_n155), .C(DP_OP_157J23_126_5719_n107), .D(
DP_OP_157J23_126_5719_n111), .ICI(DP_OP_157J23_126_5719_n108), .S(
DP_OP_157J23_126_5719_n105), .ICO(DP_OP_157J23_126_5719_n103), .CO(
DP_OP_157J23_126_5719_n104) );
CMPR32X2TS intadd_57_U2 ( .A(mult_x_56_n14), .B(intadd_57_B_7_), .C(
intadd_57_n2), .CO(intadd_57_n1), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS DP_OP_36J23_129_4699_U2 ( .A(n506), .B(S_Oper_A_exp[8]), .C(
DP_OP_36J23_129_4699_n2), .CO(DP_OP_36J23_129_4699_n1), .S(
Exp_module_Data_S[8]) );
MX2X2TS U405 ( .A(P_Sgf[41]), .B(n2379), .S0(n2665), .Y(n256) );
INVX2TS U406 ( .A(n3136), .Y(n3130) );
INVX2TS U407 ( .A(n3396), .Y(n3398) );
INVX2TS U408 ( .A(n3396), .Y(n3395) );
INVX2TS U409 ( .A(n3393), .Y(n3397) );
NAND2X1TS U410 ( .A(n405), .B(n1608), .Y(n1609) );
OR2X2TS U411 ( .A(intadd_57_n1), .B(n2322), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11)
);
BUFX3TS U412 ( .A(n2665), .Y(n3224) );
BUFX3TS U413 ( .A(n2665), .Y(n520) );
BUFX3TS U414 ( .A(n2665), .Y(n3304) );
BUFX3TS U415 ( .A(n2665), .Y(n3345) );
INVX2TS U416 ( .A(n1600), .Y(n1601) );
AO21X2TS U417 ( .A0(n1591), .A1(n1588), .B0(n1587), .Y(n558) );
NAND2X2TS U418 ( .A(n1599), .B(n1578), .Y(n1580) );
NAND2X1TS U419 ( .A(n1980), .B(n1979), .Y(n1990) );
NAND2X1TS U420 ( .A(n2587), .B(n2586), .Y(n2671) );
NAND2X1TS U421 ( .A(n2616), .B(n2615), .Y(n2746) );
INVX2TS U422 ( .A(n1478), .Y(n1479) );
INVX2TS U423 ( .A(n2374), .Y(n1434) );
NOR2X4TS U424 ( .A(n1611), .B(n1607), .Y(n1599) );
CLKINVX3TS U425 ( .A(n1470), .Y(n1471) );
CLKINVX3TS U426 ( .A(n1486), .Y(n1487) );
INVX4TS U427 ( .A(n2341), .Y(n2365) );
NAND2X1TS U428 ( .A(n2825), .B(n2445), .Y(n3389) );
NOR2X2TS U429 ( .A(n2393), .B(n399), .Y(n2395) );
NOR2X2TS U430 ( .A(n1478), .B(n448), .Y(n1440) );
OR3X1TS U431 ( .A(underflow_flag), .B(overflow_flag), .C(n3399), .Y(n3396)
);
OAI21X2TS U432 ( .A0(n2363), .A1(n2362), .B0(n2361), .Y(n2364) );
OAI21X2TS U433 ( .A0(n2781), .A1(n2778), .B0(n2779), .Y(n2767) );
AND2X2TS U434 ( .A(n3266), .B(n2444), .Y(n3136) );
NAND2X4TS U435 ( .A(n1428), .B(n2421), .Y(n2665) );
NAND2X1TS U436 ( .A(DP_OP_159J23_128_5719_n117), .B(
DP_OP_159J23_128_5719_n122), .Y(n2699) );
NAND2X1TS U437 ( .A(DP_OP_157J23_126_5719_n110), .B(
DP_OP_157J23_126_5719_n116), .Y(n2769) );
NAND2X1TS U438 ( .A(DP_OP_158J23_127_356_n465), .B(DP_OP_158J23_127_356_n471), .Y(n1782) );
NAND2X1TS U439 ( .A(DP_OP_159J23_128_5719_n123), .B(
DP_OP_159J23_128_5719_n128), .Y(n2704) );
NAND2X1TS U440 ( .A(DP_OP_158J23_127_356_n472), .B(DP_OP_158J23_127_356_n477), .Y(n1787) );
NAND2X1TS U441 ( .A(DP_OP_158J23_127_356_n478), .B(DP_OP_158J23_127_356_n484), .Y(n1792) );
NAND2X1TS U442 ( .A(DP_OP_158J23_127_356_n121), .B(n1576), .Y(n1595) );
INVX2TS U443 ( .A(n485), .Y(n486) );
CMPR32X2TS U444 ( .A(n1984), .B(n1983), .C(n1982), .CO(n1986), .S(n1979) );
NAND2X1TS U445 ( .A(DP_OP_157J23_126_5719_n123), .B(
DP_OP_157J23_126_5719_n128), .Y(n2779) );
INVX2TS U446 ( .A(n485), .Y(n487) );
NOR2X4TS U447 ( .A(DP_OP_158J23_127_356_n130), .B(DP_OP_158J23_127_356_n135),
.Y(n1611) );
NOR2X2TS U448 ( .A(DP_OP_159J23_128_5719_n110), .B(
DP_OP_159J23_128_5719_n116), .Y(n2693) );
NOR2X2TS U449 ( .A(DP_OP_158J23_127_356_n464), .B(DP_OP_158J23_127_356_n460),
.Y(n1772) );
NAND2X2TS U450 ( .A(DP_OP_158J23_127_356_n124), .B(DP_OP_158J23_127_356_n122), .Y(n1603) );
NOR2X2TS U451 ( .A(DP_OP_158J23_127_356_n124), .B(DP_OP_158J23_127_356_n122),
.Y(n1585) );
NAND2X1TS U452 ( .A(DP_OP_157J23_126_5719_n117), .B(
DP_OP_157J23_126_5719_n122), .Y(n2774) );
NOR2X2TS U453 ( .A(n3422), .B(n2453), .Y(n3266) );
OAI21X2TS U454 ( .A0(n1617), .A1(n1623), .B0(n1618), .Y(n1539) );
INVX2TS U455 ( .A(n3393), .Y(n3399) );
NAND2X2TS U456 ( .A(n2389), .B(n1462), .Y(n1485) );
AOI21X2TS U457 ( .A0(n570), .A1(n537), .B0(n1736), .Y(n1794) );
OAI21X1TS U458 ( .A0(n2022), .A1(n2028), .B0(n2023), .Y(n1916) );
NOR2X2TS U459 ( .A(n2012), .B(n2010), .Y(n2004) );
NAND2X1TS U460 ( .A(n2408), .B(n2453), .Y(n1428) );
CMPR32X2TS U461 ( .A(n1582), .B(n1581), .C(DP_OP_158J23_127_356_n120), .CO(
n1583), .S(n1576) );
NAND2X1TS U462 ( .A(n1911), .B(n1910), .Y(n2033) );
NOR2X1TS U463 ( .A(n2390), .B(n1418), .Y(n1419) );
NAND2X2TS U464 ( .A(DP_OP_158J23_127_356_n154), .B(DP_OP_158J23_127_356_n162), .Y(n1628) );
NOR2X2TS U465 ( .A(n1959), .B(n1958), .Y(n2010) );
NAND2X2TS U466 ( .A(n1963), .B(n1962), .Y(n2006) );
INVX2TS U467 ( .A(n2411), .Y(n3171) );
AO21X2TS U468 ( .A0(n569), .A1(n1799), .B0(n1734), .Y(n537) );
NOR2X2TS U469 ( .A(n1458), .B(n1431), .Y(n1433) );
CLKBUFX2TS U470 ( .A(n3391), .Y(n3393) );
NAND2X1TS U471 ( .A(DP_OP_159J23_128_5719_n102), .B(
DP_OP_159J23_128_5719_n104), .Y(n2684) );
CMPR32X2TS U472 ( .A(n1951), .B(n1950), .C(n1949), .CO(n1965), .S(n1962) );
CMPR32X2TS U473 ( .A(n1933), .B(n1932), .C(n1931), .CO(n1960), .S(n1959) );
CMPR32X2TS U474 ( .A(n1936), .B(n1935), .C(n1934), .CO(n1958), .S(n1915) );
NAND2X1TS U475 ( .A(DP_OP_159J23_128_5719_n101), .B(n2582), .Y(n2679) );
CMPR32X2TS U476 ( .A(n1972), .B(n1971), .C(n1970), .CO(n1980), .S(n1964) );
CMPR32X2TS U477 ( .A(n1906), .B(n1905), .C(n1904), .CO(n1912), .S(n1911) );
NAND2X1TS U478 ( .A(DP_OP_158J23_127_356_n456), .B(n1747), .Y(n1769) );
NAND2X1TS U479 ( .A(DP_OP_157J23_126_5719_n101), .B(n2611), .Y(n2754) );
NOR2XLTS U480 ( .A(n491), .B(n1687), .Y(n1581) );
NOR2XLTS U481 ( .A(n491), .B(n1689), .Y(n1582) );
OR2X2TS U482 ( .A(DP_OP_158J23_127_356_n163), .B(DP_OP_158J23_127_356_n172),
.Y(n579) );
NOR2X2TS U483 ( .A(n1415), .B(n2226), .Y(n2380) );
NAND2BX1TS U484 ( .AN(n2390), .B(n1460), .Y(n1461) );
AND2X2TS U485 ( .A(n2444), .B(n2445), .Y(n3391) );
AND2X2TS U486 ( .A(n2406), .B(n2453), .Y(n2411) );
NOR2X2TS U487 ( .A(n1458), .B(n1457), .Y(n1462) );
ADDFX2TS U488 ( .A(n1939), .B(n1938), .CI(n1937), .CO(n1963), .S(n1961) );
CMPR32X2TS U489 ( .A(n1876), .B(n1875), .C(n1874), .CO(n1914), .S(n1913) );
CMPR32X2TS U490 ( .A(n1873), .B(n1872), .C(n1871), .CO(n1935), .S(n1874) );
CMPR32X2TS U491 ( .A(n1948), .B(n1947), .C(n1946), .CO(n1949), .S(n1937) );
CMPR32X2TS U492 ( .A(n1831), .B(n1830), .C(n1829), .CO(
DP_OP_158J23_127_356_n479), .S(DP_OP_158J23_127_356_n480) );
CMPR32X2TS U493 ( .A(n1928), .B(n1927), .C(n1926), .CO(n1932), .S(n1934) );
CMPR32X2TS U494 ( .A(n1754), .B(n1753), .C(DP_OP_158J23_127_356_n455), .CO(
n1756), .S(n1747) );
NOR2X1TS U495 ( .A(n3410), .B(n3422), .Y(n2445) );
NOR2X1TS U496 ( .A(n491), .B(n1690), .Y(DP_OP_158J23_127_356_n214) );
NAND2X1TS U497 ( .A(n1731), .B(n1730), .Y(n1802) );
NAND2X1TS U498 ( .A(n1895), .B(n1894), .Y(n2041) );
NAND2X4TS U499 ( .A(n1415), .B(n2226), .Y(n2399) );
NOR2X6TS U500 ( .A(n1416), .B(n2223), .Y(n2382) );
NAND2XLTS U501 ( .A(n2620), .B(n3264), .Y(n2406) );
NOR2X2TS U502 ( .A(DP_OP_158J23_127_356_n173), .B(DP_OP_158J23_127_356_n180),
.Y(n1635) );
NAND2X1TS U503 ( .A(n1854), .B(n1853), .Y(n1855) );
OAI21X2TS U504 ( .A0(n2408), .A1(n2407), .B0(n2453), .Y(n3101) );
CMPR32X2TS U505 ( .A(n1930), .B(n1929), .C(n1946), .CO(n1938), .S(n1931) );
AOI21X1TS U506 ( .A0(n581), .A1(n2046), .B0(n1888), .Y(n2044) );
CMPR32X2TS U507 ( .A(n2286), .B(n2284), .C(n2285), .CO(
DP_OP_157J23_126_5719_n130), .S(DP_OP_157J23_126_5719_n131) );
CMPR32X2TS U508 ( .A(n2267), .B(n2266), .C(n2265), .CO(
DP_OP_159J23_128_5719_n130), .S(DP_OP_159J23_128_5719_n131) );
CMPR32X2TS U509 ( .A(n2596), .B(n2595), .C(n2594), .CO(n2605), .S(n2604) );
CMPR32X2TS U510 ( .A(n1898), .B(n1897), .C(n1896), .CO(n1905), .S(n1902) );
CMPR32X2TS U511 ( .A(n1727), .B(n1726), .C(n1725), .CO(n1735), .S(n1733) );
NOR2X1TS U512 ( .A(n491), .B(n1692), .Y(n1657) );
NOR2X4TS U513 ( .A(n1310), .B(n1309), .Y(n2352) );
NOR2BX1TS U514 ( .AN(n2049), .B(n1977), .Y(n1872) );
OAI22X1TS U515 ( .A0(n1975), .A1(n1919), .B0(n1918), .B1(n525), .Y(n1929) );
NAND2X2TS U516 ( .A(n540), .B(n539), .Y(n1280) );
NOR2X2TS U517 ( .A(n2620), .B(n3429), .Y(n2408) );
OAI22X1TS U518 ( .A0(n502), .A1(n1849), .B0(n470), .B1(n1847), .Y(n1730) );
CMPR32X2TS U519 ( .A(n1826), .B(n1825), .C(n1824), .CO(
DP_OP_158J23_127_356_n466), .S(DP_OP_158J23_127_356_n467) );
ADDHXLTS U520 ( .A(n2258), .B(n2257), .CO(DP_OP_159J23_128_5719_n132), .S(
n2266) );
ADDHXLTS U521 ( .A(n2593), .B(n2592), .CO(DP_OP_157J23_126_5719_n141), .S(
n2594) );
NAND2X1TS U522 ( .A(DP_OP_158J23_127_356_n188), .B(n1536), .Y(n1644) );
CMPR32X2TS U523 ( .A(n2435), .B(n2434), .C(n2433), .CO(
DP_OP_159J23_128_5719_n111), .S(DP_OP_159J23_128_5719_n112) );
CMPR32X2TS U524 ( .A(n2440), .B(n2439), .C(n2438), .CO(
DP_OP_157J23_126_5719_n111), .S(DP_OP_157J23_126_5719_n112) );
NAND2X1TS U525 ( .A(n1322), .B(n1330), .Y(n1323) );
NAND2X1TS U526 ( .A(n2214), .B(n1481), .Y(n1431) );
NAND2X1TS U527 ( .A(n1359), .B(n1358), .Y(n1360) );
NOR2X2TS U528 ( .A(DP_OP_158J23_127_356_n188), .B(n1536), .Y(n1643) );
NOR2X1TS U529 ( .A(n1841), .B(n2833), .Y(n1833) );
NAND2X1TS U530 ( .A(n477), .B(n513), .Y(n2862) );
NOR2X2TS U531 ( .A(n490), .B(n1696), .Y(DP_OP_158J23_127_356_n241) );
INVX2TS U532 ( .A(n2298), .Y(n3200) );
XNOR2X1TS U533 ( .A(n530), .B(n1944), .Y(n1918) );
XNOR2X1TS U534 ( .A(n530), .B(n1922), .Y(n1919) );
NOR2X2TS U535 ( .A(n3232), .B(n3243), .Y(n1273) );
XNOR2X1TS U536 ( .A(n1976), .B(n530), .Y(n1954) );
NAND2X2TS U537 ( .A(n2444), .B(n3422), .Y(n2620) );
XNOR2X1TS U538 ( .A(n1976), .B(n1884), .Y(n1870) );
XNOR2X1TS U539 ( .A(n1976), .B(n472), .Y(n1924) );
INVX2TS U540 ( .A(n1655), .Y(n519) );
INVX2TS U541 ( .A(n434), .Y(n476) );
NAND2X1TS U542 ( .A(n1296), .B(n1295), .Y(n1297) );
NAND2X1TS U543 ( .A(n1083), .B(n1086), .Y(n1084) );
NAND2X1TS U544 ( .A(n1319), .B(n1332), .Y(n1107) );
NAND2X1TS U545 ( .A(n1104), .B(n1097), .Y(n1098) );
CLKBUFX2TS U546 ( .A(n2810), .Y(n511) );
INVX2TS U547 ( .A(n448), .Y(n1481) );
NAND2X1TS U548 ( .A(n1245), .B(n595), .Y(n1259) );
INVX4TS U549 ( .A(n1655), .Y(n1701) );
OAI22X1TS U550 ( .A0(n518), .A1(n1697), .B0(n1702), .B1(n1696), .Y(
DP_OP_158J23_127_356_n244) );
NOR2X2TS U551 ( .A(n1270), .B(Sgf_operation_EVEN1_Q_left[0]), .Y(n3243) );
XOR2X1TS U552 ( .A(n506), .B(n2821), .Y(DP_OP_36J23_129_4699_n21) );
NAND2X2TS U553 ( .A(n1275), .B(n1274), .Y(n3221) );
NAND2X1TS U554 ( .A(DP_OP_156J23_125_3370_n203), .B(n1338), .Y(n1351) );
INVX2TS U555 ( .A(n440), .Y(n483) );
BUFX3TS U556 ( .A(n2741), .Y(n484) );
CLKINVX6TS U557 ( .A(n1746), .Y(n1846) );
CLKINVX6TS U558 ( .A(n471), .Y(n472) );
INVX2TS U559 ( .A(n566), .Y(n498) );
INVX2TS U560 ( .A(n1712), .Y(n1841) );
INVX2TS U561 ( .A(n1721), .Y(n1848) );
NOR2X1TS U562 ( .A(n473), .B(n2735), .Y(n2423) );
OR2X2TS U563 ( .A(n1256), .B(n1255), .Y(n1245) );
INVX4TS U564 ( .A(n1820), .Y(n1850) );
INVX2TS U565 ( .A(n1708), .Y(n1844) );
ADDHX1TS U566 ( .A(n1672), .B(n1671), .CO(n1667), .S(
DP_OP_158J23_127_356_n178) );
NAND2X2TS U567 ( .A(n1884), .B(n2048), .Y(n1908) );
XNOR2X1TS U568 ( .A(n1920), .B(n1884), .Y(n1893) );
CLKXOR2X2TS U569 ( .A(n1654), .B(n1653), .Y(n1655) );
XOR2X2TS U570 ( .A(n1126), .B(n1125), .Y(n1275) );
ADDHXLTS U571 ( .A(n3379), .B(n3411), .CO(n2268), .S(n2231) );
ADDHXLTS U572 ( .A(n420), .B(n404), .CO(n1713), .S(n1709) );
ADDHXLTS U573 ( .A(n513), .B(Op_MY[9]), .CO(n1805), .S(n1724) );
INVX2TS U574 ( .A(n2335), .Y(n2741) );
INVX2TS U575 ( .A(n1511), .Y(n2049) );
INVX2TS U576 ( .A(n2247), .Y(n2733) );
ADDHXLTS U577 ( .A(n3378), .B(n477), .CO(n2240), .S(n2238) );
NAND2X1TS U578 ( .A(n1234), .B(n1233), .Y(n3331) );
ADDHXLTS U579 ( .A(n3351), .B(n3353), .CO(n1742), .S(n1806) );
INVX4TS U580 ( .A(n494), .Y(n495) );
NOR2X1TS U581 ( .A(n1511), .B(n497), .Y(n1858) );
INVX2TS U582 ( .A(n421), .Y(n2048) );
NOR2X2TS U583 ( .A(n1654), .B(n1653), .Y(n442) );
OAI21X1TS U584 ( .A0(n2427), .A1(n2426), .B0(n2425), .Y(n2432) );
NOR2X2TS U585 ( .A(n1234), .B(n1233), .Y(n3332) );
CLKXOR2X2TS U586 ( .A(n1819), .B(n1818), .Y(n1820) );
CLKXOR2X2TS U587 ( .A(n1707), .B(n1706), .Y(n1708) );
INVX6TS U588 ( .A(n1090), .Y(n1293) );
ADDHXLTS U589 ( .A(n391), .B(n3380), .CO(n2283), .S(n2282) );
ADDHXLTS U590 ( .A(Op_MX[2]), .B(n3372), .CO(n2264), .S(n2263) );
NOR2X1TS U591 ( .A(n1695), .B(n497), .Y(n1686) );
INVX2TS U592 ( .A(n1281), .Y(n1289) );
CLKBUFX2TS U593 ( .A(n2197), .Y(n1255) );
ADDHXLTS U594 ( .A(n3370), .B(n3367), .CO(n2336), .S(n2244) );
INVX4TS U595 ( .A(n1660), .Y(n1688) );
ADDHXLTS U596 ( .A(n2832), .B(n2828), .CO(n2316), .S(n2591) );
INVX4TS U597 ( .A(n1562), .Y(n1689) );
XOR2X1TS U598 ( .A(n2276), .B(n2271), .Y(n437) );
NAND2X2TS U599 ( .A(n3462), .B(n1427), .Y(n2421) );
OAI21X1TS U600 ( .A0(n2259), .A1(n2323), .B0(n2325), .Y(n2262) );
OAI21X1TS U601 ( .A0(n2276), .A1(n2275), .B0(n2274), .Y(n2281) );
NOR2X1TS U602 ( .A(n1691), .B(n497), .Y(n1679) );
OAI21X1TS U603 ( .A0(n3314), .A1(n3311), .B0(n3315), .Y(n3320) );
AOI21X1TS U604 ( .A0(n418), .A1(n1710), .B0(n1704), .Y(n1707) );
CLKXOR2X2TS U605 ( .A(n2236), .B(n2235), .Y(n2237) );
NOR2X1TS U606 ( .A(n3407), .B(FS_Module_state_reg[0]), .Y(n1427) );
INVX2TS U607 ( .A(n1508), .Y(n1698) );
NAND2X6TS U608 ( .A(DP_OP_156J23_125_3370_n225), .B(
DP_OP_156J23_125_3370_n227), .Y(n1288) );
NAND2X1TS U609 ( .A(n1209), .B(n1208), .Y(n3311) );
OA21XLTS U610 ( .A0(n2428), .A1(n2425), .B0(n2429), .Y(n2331) );
NOR2X1TS U611 ( .A(n3167), .B(n3098), .Y(n3161) );
INVX4TS U612 ( .A(n1508), .Y(n515) );
INVX4TS U613 ( .A(n1504), .Y(n1699) );
INVX4TS U614 ( .A(n679), .Y(n1693) );
INVX2TS U615 ( .A(n1528), .Y(n1695) );
NOR2X4TS U616 ( .A(n1281), .B(n1283), .Y(n1292) );
INVX2TS U617 ( .A(n639), .Y(n1703) );
XNOR2X2TS U618 ( .A(n1556), .B(n1555), .Y(n1866) );
INVX2TS U619 ( .A(n1216), .Y(n1248) );
NAND2X1TS U620 ( .A(n3352), .B(Op_MY[5]), .Y(n2429) );
INVX4TS U621 ( .A(n2396), .Y(DP_OP_156J23_125_3370_n290) );
INVX2TS U622 ( .A(n1519), .Y(n1697) );
NAND2X1TS U623 ( .A(n1554), .B(n1553), .Y(n1555) );
INVX2TS U624 ( .A(n443), .Y(n497) );
NAND2X1TS U625 ( .A(n3351), .B(n3355), .Y(n2425) );
NOR2X4TS U626 ( .A(DP_OP_156J23_125_3370_n225), .B(
DP_OP_156J23_125_3370_n227), .Y(n1281) );
NAND2X1TS U627 ( .A(n3353), .B(n2837), .Y(n2312) );
NAND2X1TS U628 ( .A(Op_MY[6]), .B(Op_MY[0]), .Y(n2252) );
NAND2X1TS U629 ( .A(n3404), .B(n462), .Y(n2233) );
NAND2X1TS U630 ( .A(n3412), .B(n465), .Y(n2251) );
NAND2X1TS U631 ( .A(Op_MY[9]), .B(n469), .Y(n2324) );
NAND2X1TS U632 ( .A(n578), .B(n1505), .Y(n1506) );
NAND2XLTS U633 ( .A(n1572), .B(n1571), .Y(n1573) );
NOR2X4TS U634 ( .A(n654), .B(n1864), .Y(n1542) );
NAND2X1TS U635 ( .A(Op_MX[7]), .B(Op_MX[19]), .Y(n1716) );
NOR2X1TS U636 ( .A(Op_MX[7]), .B(Op_MX[19]), .Y(n1714) );
INVX2TS U637 ( .A(n2213), .Y(DP_OP_156J23_125_3370_n270) );
NAND2X1TS U638 ( .A(n3411), .B(Op_MX[10]), .Y(n1816) );
NAND2X1TS U639 ( .A(n1525), .B(n1524), .Y(n1526) );
NAND2X1TS U640 ( .A(n675), .B(n674), .Y(n676) );
NAND2X1TS U641 ( .A(n1500), .B(n1565), .Y(n642) );
NAND2X1TS U642 ( .A(n3380), .B(n3372), .Y(n1715) );
NOR2X2TS U643 ( .A(Op_MX[21]), .B(n414), .Y(n1811) );
INVX2TS U644 ( .A(n2330), .Y(n3352) );
CLKXOR2X4TS U645 ( .A(n1551), .B(n653), .Y(n1864) );
INVX2TS U646 ( .A(n429), .Y(n3351) );
INVX2TS U647 ( .A(n2202), .Y(DP_OP_156J23_125_3370_n274) );
NAND2X1TS U648 ( .A(n652), .B(n661), .Y(n653) );
INVX2TS U649 ( .A(n3402), .Y(n461) );
NAND2X1TS U650 ( .A(n2175), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .Y(n2177) );
AO21XLTS U651 ( .A0(n1503), .A1(n1502), .B0(n1501), .Y(n447) );
INVX4TS U652 ( .A(n2824), .Y(n3367) );
INVX4TS U653 ( .A(n430), .Y(n3353) );
INVX4TS U654 ( .A(n646), .Y(n644) );
CMPR32X2TS U655 ( .A(n1723), .B(n3356), .C(n404), .CO(n1522), .S(n1529) );
OR2X2TS U656 ( .A(DP_OP_156J23_125_3370_n246), .B(DP_OP_156J23_125_3370_n248), .Y(n1247) );
NAND2X1TS U657 ( .A(n1391), .B(n1390), .Y(n1392) );
NAND2X1TS U658 ( .A(n1410), .B(n1409), .Y(n1411) );
NAND2X1TS U659 ( .A(n1380), .B(n1379), .Y(n1381) );
CLKXOR2X4TS U660 ( .A(n1155), .B(n1154), .Y(n2202) );
NAND2X1TS U661 ( .A(n606), .B(n622), .Y(n1512) );
INVX2TS U662 ( .A(n2220), .Y(DP_OP_156J23_125_3370_n277) );
NAND2X1TS U663 ( .A(n439), .B(n663), .Y(n664) );
BUFX6TS U664 ( .A(n606), .Y(n1884) );
NAND2X1TS U665 ( .A(n1153), .B(n1164), .Y(n1154) );
NAND2X1TS U666 ( .A(n1171), .B(n1170), .Y(n1172) );
CLKINVX6TS U667 ( .A(n2835), .Y(n404) );
INVX8TS U668 ( .A(n1397), .Y(n1377) );
NAND2X1TS U669 ( .A(Op_MY[5]), .B(n600), .Y(n1564) );
NAND2X2TS U670 ( .A(DP_OP_156J23_125_3370_n249), .B(n1067), .Y(n1224) );
INVX4TS U671 ( .A(n1012), .Y(n1184) );
NOR2X2TS U672 ( .A(Op_MY[5]), .B(n600), .Y(n1566) );
CMPR32X2TS U673 ( .A(n414), .B(Op_MX[21]), .C(n635), .CO(n650), .S(n628) );
BUFX3TS U674 ( .A(Op_MY[17]), .Y(n600) );
NAND2X1TS U675 ( .A(n611), .B(n632), .Y(n633) );
INVX2TS U676 ( .A(Op_MY[20]), .Y(n2835) );
NOR2X1TS U677 ( .A(n1162), .B(n1166), .Y(n1168) );
NAND2X6TS U678 ( .A(n994), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n1182) );
NAND2X2TS U679 ( .A(n838), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n1379) );
INVX2TS U680 ( .A(n651), .Y(n1551) );
INVX8TS U681 ( .A(n812), .Y(n1397) );
INVX4TS U682 ( .A(n557), .Y(n3355) );
NOR2X2TS U683 ( .A(n465), .B(n412), .Y(n1514) );
NAND2X4TS U684 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]),
.B(n1018), .Y(n1228) );
NAND2X4TS U685 ( .A(Op_MY[0]), .B(n3362), .Y(n1517) );
NAND2X2TS U686 ( .A(n421), .B(n620), .Y(n1520) );
NAND2X2TS U687 ( .A(n468), .B(Op_MY[15]), .Y(n674) );
CLKXOR2X4TS U688 ( .A(n1344), .B(n1327), .Y(n2226) );
INVX2TS U689 ( .A(n446), .Y(n467) );
INVX2TS U690 ( .A(n393), .Y(n468) );
INVX2TS U691 ( .A(n3405), .Y(n462) );
NAND2X1TS U692 ( .A(n1326), .B(n1342), .Y(n1327) );
NAND2X1TS U693 ( .A(n1347), .B(n1346), .Y(n1348) );
NAND2X1TS U694 ( .A(n1138), .B(n1137), .Y(n1139) );
OAI21X2TS U695 ( .A0(n1344), .A1(n1343), .B0(n1342), .Y(n1349) );
NAND2X1TS U696 ( .A(n1133), .B(n1132), .Y(n1134) );
NAND2X2TS U697 ( .A(n2114), .B(n2117), .Y(n2128) );
NAND2X2TS U698 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]),
.B(n976), .Y(n1164) );
INVX2TS U699 ( .A(n661), .Y(n616) );
INVX4TS U700 ( .A(n2097), .Y(n2156) );
NAND2X4TS U701 ( .A(n809), .B(n1399), .Y(n811) );
INVX4TS U702 ( .A(n562), .Y(n3371) );
NOR2X2TS U703 ( .A(n2207), .B(n1136), .Y(n919) );
XNOR2X1TS U704 ( .A(n2219), .B(n2218), .Y(n3302) );
CMPR32X2TS U705 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]),
.B(n880), .C(n1044), .CO(n1054), .S(n1043) );
NAND2X1TS U706 ( .A(n1113), .B(n1112), .Y(n1114) );
INVX2TS U707 ( .A(Op_MX[20]), .Y(n2648) );
AOI21X2TS U708 ( .A0(n832), .A1(n814), .B0(n813), .Y(n821) );
OAI21X2TS U709 ( .A0(n2164), .A1(n2163), .B0(n2162), .Y(n2169) );
OR2X2TS U710 ( .A(n391), .B(Op_MX[2]), .Y(n610) );
OR2X4TS U711 ( .A(n3368), .B(n3378), .Y(n611) );
NOR2X1TS U712 ( .A(n824), .B(n822), .Y(n814) );
INVX4TS U713 ( .A(n454), .Y(n3370) );
NOR2X6TS U714 ( .A(n799), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n1343) );
NAND2X1TS U715 ( .A(n391), .B(Op_MX[2]), .Y(n625) );
NAND2X1TS U716 ( .A(n962), .B(n955), .Y(n950) );
NAND2X1TS U717 ( .A(n963), .B(n965), .Y(n960) );
NOR2X4TS U718 ( .A(n2065), .B(n2064), .Y(n2165) );
NOR2X1TS U719 ( .A(n1028), .B(n1027), .Y(n1127) );
NOR2X2TS U720 ( .A(n834), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(n840) );
NAND2X2TS U721 ( .A(n972), .B(n999), .Y(n973) );
NOR2X2TS U722 ( .A(n823), .B(n824), .Y(n831) );
INVX6TS U723 ( .A(n751), .Y(n832) );
NOR2X4TS U724 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]),
.B(n913), .Y(n914) );
OR2X2TS U725 ( .A(n779), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n1023) );
CLKINVX1TS U726 ( .A(n937), .Y(n929) );
CLKAND2X2TS U727 ( .A(n748), .B(n747), .Y(n749) );
NAND2X2TS U728 ( .A(n2058), .B(n2057), .Y(n2183) );
NOR2X2TS U729 ( .A(n1002), .B(n997), .Y(n1005) );
NAND2X2TS U730 ( .A(n2056), .B(n2053), .Y(n1052) );
OR2X6TS U731 ( .A(n996), .B(n1000), .Y(n1002) );
NAND2X4TS U732 ( .A(n1045), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n1058) );
INVX6TS U733 ( .A(n984), .Y(n1003) );
NAND2X2TS U734 ( .A(n895), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n1056) );
NAND2X4TS U735 ( .A(n753), .B(n731), .Y(n824) );
OR2X6TS U736 ( .A(n725), .B(n726), .Y(n731) );
INVX2TS U737 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(
n2061) );
INVX2TS U738 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .Y(
n2060) );
NAND2X1TS U739 ( .A(n791), .B(n790), .Y(n792) );
INVX2TS U740 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(
n2057) );
NOR2X6TS U741 ( .A(n736), .B(n735), .Y(n822) );
OAI21X2TS U742 ( .A0(n937), .A1(n936), .B0(n935), .Y(n938) );
NAND2X2TS U743 ( .A(n872), .B(n871), .Y(n877) );
NOR2X4TS U744 ( .A(n741), .B(n746), .Y(n716) );
INVX2TS U745 ( .A(n766), .Y(n788) );
NAND2X2TS U746 ( .A(n897), .B(n904), .Y(n898) );
NAND2X2TS U747 ( .A(n714), .B(n713), .Y(n747) );
OR2X4TS U748 ( .A(n699), .B(n705), .Y(n782) );
INVX2TS U749 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(
n734) );
NAND2X4TS U750 ( .A(n692), .B(n691), .Y(n786) );
NOR2X4TS U751 ( .A(n688), .B(n1027), .Y(n769) );
CLKINVX2TS U752 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]),
.Y(n702) );
INVX2TS U753 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(
n719) );
CLKINVX2TS U754 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]),
.Y(n969) );
INVX3TS U755 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(
n926) );
OR2X2TS U756 ( .A(n685), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(n691) );
INVX2TS U757 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[4]), .Y(
n706) );
INVX6TS U758 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(
n707) );
INVX3TS U759 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(
n701) );
INVX3TS U760 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(
n947) );
OR2X4TS U761 ( .A(n855), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(n858) );
INVX6TS U762 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(
n857) );
CLKINVX6TS U763 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]),
.Y(n865) );
INVX4TS U764 ( .A(Sgf_operation_Result[2]), .Y(n856) );
INVX3TS U765 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(
n686) );
INVX4TS U766 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(
n852) );
INVX4TS U767 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(
n685) );
OR2X2TS U768 ( .A(n2111), .B(n2110), .Y(n2117) );
NAND2X2TS U769 ( .A(n1860), .B(n636), .Y(n645) );
INVX4TS U770 ( .A(n767), .Y(n785) );
XNOR2X2TS U771 ( .A(n1052), .B(n2055), .Y(n1493) );
INVX2TS U772 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[5]), .Y(
n1044) );
NAND2X2TS U773 ( .A(n785), .B(n786), .Y(n768) );
INVX4TS U774 ( .A(n740), .Y(n784) );
INVX2TS U775 ( .A(n1545), .Y(n668) );
CLKINVX3TS U776 ( .A(n662), .Y(n652) );
NOR2X6TS U777 ( .A(n1229), .B(n1231), .Y(n1020) );
AOI21X1TS U778 ( .A0(n418), .A1(n1807), .B0(n1809), .Y(n1720) );
NAND2X1TS U779 ( .A(n411), .B(n462), .Y(n1515) );
ADDHXLTS U780 ( .A(n3368), .B(n414), .CO(n2256), .S(n2255) );
NAND2X2TS U781 ( .A(n610), .B(n611), .Y(n614) );
AOI21X2TS U782 ( .A0(n1569), .A1(n1568), .B0(n1567), .Y(n1574) );
OR2X1TS U783 ( .A(n1039), .B(n1038), .Y(n1175) );
NAND2X1TS U784 ( .A(n413), .B(Op_MY[6]), .Y(n1571) );
INVX4TS U785 ( .A(n659), .Y(n1691) );
OR2X1TS U786 ( .A(n1031), .B(n1030), .Y(n1148) );
NAND2X1TS U787 ( .A(n1516), .B(n1515), .Y(n1518) );
NOR2XLTS U788 ( .A(n475), .B(n2805), .Y(n2319) );
NAND2X2TS U789 ( .A(n888), .B(n887), .Y(n890) );
NAND2X1TS U790 ( .A(n1119), .B(n1118), .Y(n1120) );
NAND2X2TS U791 ( .A(n1047), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n1063) );
NOR2X2TS U792 ( .A(n1458), .B(n1448), .Y(n1450) );
OAI21X1TS U793 ( .A0(n2427), .A1(n2332), .B0(n2331), .Y(n433) );
BUFX4TS U794 ( .A(n1974), .Y(n525) );
OAI22X1TS U795 ( .A0(n1850), .A1(n1839), .B0(n1848), .B1(n1838), .Y(n1825)
);
INVX4TS U796 ( .A(n657), .Y(n1702) );
NOR2XLTS U797 ( .A(Op_MX[19]), .B(n3404), .Y(n2841) );
AOI21X1TS U798 ( .A0(n1142), .A1(DP_OP_154J23_123_2814_n140), .B0(n1026),
.Y(n1130) );
CLKXOR2X2TS U799 ( .A(n1518), .B(n1517), .Y(n1882) );
ADDHXLTS U800 ( .A(Op_MX[1]), .B(Op_MX[7]), .CO(n2337), .S(n2562) );
CMPR42X1TS U801 ( .A(DP_OP_157J23_126_5719_n151), .B(
DP_OP_157J23_126_5719_n158), .C(DP_OP_157J23_126_5719_n132), .D(
DP_OP_157J23_126_5719_n165), .ICI(DP_OP_157J23_126_5719_n130), .S(
DP_OP_157J23_126_5719_n126), .ICO(DP_OP_157J23_126_5719_n124), .CO(
DP_OP_157J23_126_5719_n125) );
XNOR2X2TS U802 ( .A(n1269), .B(n1268), .Y(n1270) );
NOR2XLTS U803 ( .A(n3095), .B(n3186), .Y(n3096) );
NOR2XLTS U804 ( .A(n3055), .B(n3056), .Y(n2627) );
INVX2TS U805 ( .A(n433), .Y(n474) );
NOR2XLTS U806 ( .A(n2975), .B(n2974), .Y(n2517) );
ADDHX1TS U807 ( .A(n3412), .B(n3404), .CO(n1723), .S(n1722) );
NOR2XLTS U808 ( .A(n476), .B(n2801), .Y(n2610) );
NOR2XLTS U809 ( .A(n2845), .B(n2844), .Y(n2846) );
NAND2X2TS U810 ( .A(Op_MX[0]), .B(n419), .Y(n619) );
INVX2TS U811 ( .A(n2237), .Y(n2806) );
NAND2X1TS U812 ( .A(n1271), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n3233) );
NAND2X4TS U813 ( .A(n1311), .B(n2199), .Y(n2361) );
NAND2X1TS U814 ( .A(n2411), .B(n3101), .Y(n2409) );
CMPR42X1TS U815 ( .A(DP_OP_158J23_127_356_n497), .B(
DP_OP_158J23_127_356_n468), .C(DP_OP_158J23_127_356_n462), .D(
DP_OP_158J23_127_356_n466), .ICI(DP_OP_158J23_127_356_n463), .S(
DP_OP_158J23_127_356_n460), .ICO(DP_OP_158J23_127_356_n458), .CO(
DP_OP_158J23_127_356_n459) );
OR2X1TS U816 ( .A(n1144), .B(n2221), .Y(n594) );
NAND2X1TS U817 ( .A(DP_OP_159J23_128_5719_n110), .B(
DP_OP_159J23_128_5719_n116), .Y(n2694) );
ADDHXLTS U818 ( .A(n3371), .B(n3369), .CO(n2561), .S(n2443) );
OR2X1TS U819 ( .A(n1887), .B(n1886), .Y(n581) );
NAND2X1TS U820 ( .A(n1756), .B(n1755), .Y(n1760) );
CLKINVX6TS U821 ( .A(n1510), .Y(n1700) );
OR2X1TS U822 ( .A(n1045), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n1046) );
OAI21XLTS U823 ( .A0(n3247), .A1(n3243), .B0(n3244), .Y(n3236) );
INVX2TS U824 ( .A(n3264), .Y(n2446) );
NOR2XLTS U825 ( .A(n2940), .B(n2932), .Y(n2938) );
OR2X1TS U826 ( .A(n2572), .B(n2571), .Y(n2722) );
NOR2X1TS U827 ( .A(n1895), .B(n1894), .Y(n2040) );
NOR2X1TS U828 ( .A(n1731), .B(n1730), .Y(n1801) );
INVX2TS U829 ( .A(n1599), .Y(n1602) );
AOI21X2TS U830 ( .A0(n594), .A1(n3271), .B0(n1145), .Y(n3296) );
OAI21XLTS U831 ( .A0(n2701), .A1(n2698), .B0(n2699), .Y(n2697) );
INVX2TS U832 ( .A(n1994), .Y(n2020) );
NOR2XLTS U833 ( .A(n454), .B(n568), .Y(intadd_56_A_8_) );
OAI21X1TS U834 ( .A0(n1625), .A1(n1622), .B0(n1623), .Y(n1621) );
NAND2X1TS U835 ( .A(n1858), .B(n1857), .Y(n1859) );
BUFX3TS U836 ( .A(n2665), .Y(n3342) );
NAND2X1TS U837 ( .A(Op_MY[6]), .B(n458), .Y(n3019) );
INVX2TS U838 ( .A(n549), .Y(n3369) );
OAI21XLTS U839 ( .A0(n2988), .A1(n2987), .B0(n2491), .Y(mult_x_58_n36) );
OAI21XLTS U840 ( .A0(n3054), .A1(n3065), .B0(n2455), .Y(intadd_56_B_2_) );
OR2X1TS U841 ( .A(n520), .B(n547), .Y(n1475) );
NAND2X1TS U842 ( .A(Op_MX[13]), .B(n3362), .Y(n2971) );
NAND2X1TS U843 ( .A(Op_MX[1]), .B(Op_MY[0]), .Y(n3092) );
NAND2X1TS U844 ( .A(n1604), .B(n1603), .Y(n1605) );
OAI21XLTS U845 ( .A0(n2879), .A1(n2880), .B0(n2560), .Y(mult_x_56_n14) );
OR2X1TS U846 ( .A(n3345), .B(n531), .Y(n1437) );
CLKINVX3TS U847 ( .A(n2827), .Y(n2826) );
BUFX3TS U848 ( .A(FS_Module_state_reg[1]), .Y(n2453) );
OAI21XLTS U849 ( .A0(Sgf_normalized_result[0]), .A1(n3241), .B0(n2447), .Y(
n306) );
XNOR2X2TS U850 ( .A(n2259), .B(n409), .Y(n392) );
OR2X4TS U851 ( .A(n686), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .Y(n396) );
CLKINVX3TS U852 ( .A(n397), .Y(n477) );
XNOR2X4TS U853 ( .A(n1424), .B(n1423), .Y(n399) );
INVX2TS U854 ( .A(n2224), .Y(DP_OP_156J23_125_3370_n292) );
OR2X1TS U855 ( .A(n2213), .B(n1212), .Y(n400) );
CLKXOR2X4TS U856 ( .A(n1513), .B(n553), .Y(n401) );
OR2X2TS U857 ( .A(DP_OP_158J23_127_356_n457), .B(DP_OP_158J23_127_356_n459),
.Y(n402) );
NOR2X4TS U858 ( .A(n1271), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n3232) );
INVX4TS U859 ( .A(n1607), .Y(n405) );
INVX2TS U860 ( .A(n1594), .Y(n1596) );
NAND2X6TS U861 ( .A(DP_OP_158J23_127_356_n130), .B(DP_OP_158J23_127_356_n135), .Y(n1612) );
INVX6TS U862 ( .A(n2225), .Y(DP_OP_156J23_125_3370_n295) );
MX2X1TS U863 ( .A(P_Sgf[12]), .B(n3301), .S0(n3304), .Y(n227) );
XOR2X1TS U864 ( .A(n2766), .B(n2765), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9)
);
OAI21X1TS U865 ( .A0(n2766), .A1(n2758), .B0(n2763), .Y(n2762) );
OAI21X1TS U866 ( .A0(n2766), .A1(n2753), .B0(n2752), .Y(n2757) );
MX2X1TS U867 ( .A(P_Sgf[11]), .B(n3306), .S0(n3345), .Y(n226) );
NAND2X2TS U868 ( .A(DP_OP_158J23_127_356_n457), .B(DP_OP_158J23_127_356_n459), .Y(n1773) );
NOR2X4TS U869 ( .A(n1371), .B(n1372), .Y(n849) );
INVX2TS U870 ( .A(n2201), .Y(DP_OP_156J23_125_3370_n303) );
MX2X1TS U871 ( .A(P_Sgf[10]), .B(n2666), .S0(n520), .Y(n225) );
INVX8TS U872 ( .A(n494), .Y(n403) );
INVX6TS U873 ( .A(n1362), .Y(n1407) );
ADDHX1TS U874 ( .A(n1833), .B(n1832), .CO(DP_OP_158J23_127_356_n481), .S(
n1829) );
MX2X1TS U875 ( .A(P_Sgf[8]), .B(n3302), .S0(n520), .Y(n223) );
NOR2X2TS U876 ( .A(n1688), .B(n497), .Y(n1671) );
INVX6TS U877 ( .A(n1101), .Y(n1109) );
MX2X1TS U878 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n3343),
.Y(n279) );
CLKMX2X2TS U879 ( .A(P_Sgf[6]), .B(n3303), .S0(n3304), .Y(n221) );
MX2X1TS U880 ( .A(P_Sgf[4]), .B(Sgf_operation_Result[4]), .S0(n3345), .Y(
n219) );
MX2X1TS U881 ( .A(P_Sgf[5]), .B(Sgf_operation_Result[5]), .S0(n3304), .Y(
n220) );
OR2X2TS U882 ( .A(n3345), .B(n541), .Y(n1444) );
MX2X1TS U883 ( .A(P_Sgf[1]), .B(Sgf_operation_Result[1]), .S0(n520), .Y(n216) );
INVX4TS U884 ( .A(n1530), .Y(n1696) );
ADDHX1TS U885 ( .A(n1529), .B(n1882), .CO(n1530), .S(n1519) );
BUFX3TS U886 ( .A(n3396), .Y(n3392) );
OR2X2TS U887 ( .A(n1047), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n559) );
INVX2TS U888 ( .A(n2525), .Y(n2522) );
MX2X1TS U889 ( .A(Data_MX[22]), .B(n488), .S0(n2826), .Y(n366) );
MX2X1TS U890 ( .A(Data_MY[19]), .B(n3404), .S0(n493), .Y(n331) );
MX2X1TS U891 ( .A(Data_MX[7]), .B(n458), .S0(n3341), .Y(n351) );
MX2X1TS U892 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n3340), .Y(n341) );
MX2X1TS U893 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n3390), .Y(n338) );
MX2X1TS U894 ( .A(n3242), .B(Add_result[1]), .S0(n3130), .Y(n305) );
MX2X1TS U895 ( .A(n3230), .B(Add_result[2]), .S0(n3130), .Y(n304) );
MX2X1TS U896 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n3340), .Y(n371) );
MX2X1TS U897 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n3340), .Y(n340) );
MX2X1TS U898 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n3340), .Y(n372) );
NAND2X1TS U899 ( .A(n1718), .B(n1810), .Y(n1719) );
OAI21XLTS U900 ( .A0(n2648), .A1(n398), .B0(n2647), .Y(n2649) );
INVX2TS U901 ( .A(n729), .Y(n730) );
INVX2TS U902 ( .A(n1811), .Y(n1718) );
OAI21XLTS U903 ( .A0(n596), .A1(n3403), .B0(n2651), .Y(n2652) );
NAND2XLTS U904 ( .A(n394), .B(Op_MY[0]), .Y(n3051) );
NAND2XLTS U905 ( .A(n3379), .B(n3362), .Y(n2930) );
INVX1TS U906 ( .A(n2620), .Y(n2623) );
AND2X4TS U907 ( .A(n3266), .B(n2825), .Y(n2827) );
NAND2X2TS U908 ( .A(n834), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(n839) );
NOR2X1TS U909 ( .A(n3380), .B(n404), .Y(n2554) );
NAND2XLTS U910 ( .A(n3371), .B(Op_MY[9]), .Y(n3015) );
INVX2TS U911 ( .A(n663), .Y(n615) );
NAND2X2TS U912 ( .A(FS_Module_state_reg[2]), .B(n3462), .Y(n3264) );
CLKMX2X2TS U913 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
OAI21X2TS U914 ( .A0(n1615), .A1(n1590), .B0(n1589), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15) );
XOR2X2TS U915 ( .A(n1615), .B(n1614), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10) );
INVX12TS U916 ( .A(n1541), .Y(n1615) );
NAND2X2TS U917 ( .A(n1599), .B(n533), .Y(n1590) );
INVX2TS U918 ( .A(n410), .Y(n1080) );
INVX2TS U919 ( .A(n1603), .Y(n1591) );
XOR2X1TS U920 ( .A(n1989), .B(n1988), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13)
);
CLKMX2X2TS U921 ( .A(P_Sgf[14]), .B(n3297), .S0(n520), .Y(n229) );
NOR2X6TS U922 ( .A(DP_OP_158J23_127_356_n129), .B(DP_OP_158J23_127_356_n125),
.Y(n1607) );
INVX4TS U923 ( .A(n1612), .Y(n1575) );
INVX2TS U924 ( .A(n1632), .Y(n1538) );
CLKMX2X2TS U925 ( .A(P_Sgf[13]), .B(n3273), .S0(n3224), .Y(n228) );
INVX2TS U926 ( .A(n552), .Y(n1211) );
NAND2X2TS U927 ( .A(DP_OP_158J23_127_356_n173), .B(DP_OP_158J23_127_356_n180), .Y(n1636) );
OAI21X1TS U928 ( .A0(n2691), .A1(n2590), .B0(n2589), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
INVX2TS U929 ( .A(n1122), .Y(n1124) );
OAI21X1TS U930 ( .A0(n2691), .A1(n2683), .B0(n2688), .Y(n2687) );
OAI21X1TS U931 ( .A0(n2691), .A1(n2678), .B0(n2677), .Y(n2682) );
NOR2X4TS U932 ( .A(n1772), .B(n1750), .Y(n1759) );
NAND2X4TS U933 ( .A(DP_OP_156J23_125_3370_n231), .B(
DP_OP_156J23_125_3370_n233), .Y(n1123) );
XOR2X1TS U934 ( .A(n2691), .B(n2690), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9)
);
NAND2X4TS U935 ( .A(n1959), .B(n1958), .Y(n2017) );
NOR2X4TS U936 ( .A(n1963), .B(n1962), .Y(n2005) );
OAI21X2TS U937 ( .A0(n1781), .A1(n1787), .B0(n1782), .Y(n1737) );
NOR2X2TS U938 ( .A(n491), .B(n1700), .Y(DP_OP_158J23_127_356_n250) );
NAND2X2TS U939 ( .A(n1913), .B(n1912), .Y(n2028) );
OR2X4TS U940 ( .A(DP_OP_156J23_125_3370_n243), .B(DP_OP_156J23_125_3370_n245), .Y(n1249) );
NOR2X2TS U941 ( .A(n491), .B(n1694), .Y(DP_OP_158J23_127_356_n232) );
INVX2TS U942 ( .A(n2223), .Y(DP_OP_156J23_125_3370_n301) );
NOR2X4TS U943 ( .A(n1915), .B(n1914), .Y(n2022) );
OAI21X2TS U944 ( .A0(n2693), .A1(n2699), .B0(n2694), .Y(n2578) );
XNOR2X2TS U945 ( .A(n1227), .B(n1226), .Y(n1234) );
INVX3TS U946 ( .A(n2666), .Y(DP_OP_156J23_125_3370_n279) );
NOR2X4TS U947 ( .A(n1228), .B(n1231), .Y(n1019) );
ADDFHX2TS U948 ( .A(n1677), .B(n1676), .CI(n1675), .CO(
DP_OP_158J23_127_356_n182), .S(DP_OP_158J23_127_356_n183) );
NAND2X2TS U949 ( .A(n2209), .B(n2208), .Y(n2210) );
INVX6TS U950 ( .A(n657), .Y(n516) );
INVX2TS U951 ( .A(n1136), .Y(n1138) );
ADDHX2TS U952 ( .A(n1686), .B(n1685), .CO(DP_OP_158J23_127_356_n193), .S(
n1533) );
ADDFHX1TS U953 ( .A(n1823), .B(n1822), .CI(n1821), .CO(
DP_OP_158J23_127_356_n461), .S(DP_OP_158J23_127_356_n462) );
AND2X2TS U954 ( .A(n452), .B(n1855), .Y(n1856) );
ADDHX1TS U955 ( .A(n1828), .B(n1827), .CO(DP_OP_158J23_127_356_n468), .S(
DP_OP_158J23_127_356_n469) );
INVX2TS U956 ( .A(n3302), .Y(DP_OP_156J23_125_3370_n281) );
NOR2X2TS U957 ( .A(n497), .B(n1699), .Y(n1857) );
INVX8TS U958 ( .A(n528), .Y(n530) );
INVX2TS U959 ( .A(n3305), .Y(n2227) );
INVX4TS U960 ( .A(n649), .Y(n1507) );
OR2X2TS U961 ( .A(n1049), .B(n1048), .Y(n535) );
NAND2X2TS U962 ( .A(n1940), .B(n667), .Y(n1543) );
INVX6TS U963 ( .A(n1976), .Y(n1687) );
CLKMX2X2TS U964 ( .A(n3152), .B(Add_result[13]), .S0(n3130), .Y(n293) );
AOI21X2TS U965 ( .A0(n418), .A1(n586), .B0(n1744), .Y(n1745) );
ADDHX2TS U966 ( .A(n1944), .B(n658), .CO(n643), .S(n659) );
INVX12TS U967 ( .A(n942), .Y(n924) );
ADDHX2TS U968 ( .A(n1659), .B(n1952), .CO(n1562), .S(n1660) );
CLKMX2X2TS U969 ( .A(n3188), .B(Add_result[7]), .S0(n3241), .Y(n299) );
CLKMX2X2TS U970 ( .A(n3157), .B(Add_result[12]), .S0(n3262), .Y(n294) );
CLKMX2X2TS U971 ( .A(n3170), .B(Add_result[10]), .S0(n3130), .Y(n296) );
CLKMX2X2TS U972 ( .A(n3176), .B(Add_result[9]), .S0(n3262), .Y(n297) );
INVX1TS U973 ( .A(n2867), .Y(n2543) );
NOR2X4TS U974 ( .A(n895), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n1055) );
CLKMX2X2TS U975 ( .A(n3162), .B(Add_result[11]), .S0(n3262), .Y(n295) );
CLKMX2X2TS U976 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n3340), .Y(n367) );
MX2X1TS U977 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n3390), .Y(n342) );
INVX1TS U978 ( .A(n3060), .Y(n3053) );
MX2X1TS U979 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n3390), .Y(n374) );
CLKMX2X2TS U980 ( .A(Data_MY[22]), .B(n395), .S0(n2831), .Y(n334) );
MX2X1TS U981 ( .A(Data_MX[4]), .B(n394), .S0(n3390), .Y(n348) );
NAND2X2TS U982 ( .A(n444), .B(n1520), .Y(n1521) );
CLKMX2X2TS U983 ( .A(Data_MY[10]), .B(n423), .S0(n492), .Y(n322) );
NAND2X4TS U984 ( .A(n439), .B(n652), .Y(n1550) );
CLKMX2X2TS U985 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n2831), .Y(n359) );
CLKMX2X2TS U986 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n3340), .Y(n347) );
INVX1TS U987 ( .A(n2939), .Y(n2932) );
CLKMX2X2TS U988 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n3340), .Y(n337) );
CLKMX2X2TS U989 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n2831), .Y(n316) );
OAI31X1TS U990 ( .A0(n3136), .A1(n3349), .A2(n3406), .B0(n2448), .Y(n308) );
INVX2TS U991 ( .A(n2558), .Y(n2555) );
OR2X4TS U992 ( .A(n421), .B(n620), .Y(n444) );
INVX4TS U993 ( .A(n3136), .Y(n3262) );
INVX2TS U994 ( .A(n1523), .Y(n1525) );
NAND2X6TS U995 ( .A(n3379), .B(n394), .Y(n661) );
INVX2TS U996 ( .A(n632), .Y(n612) );
NAND2X2TS U997 ( .A(n3380), .B(n489), .Y(n2558) );
INVX2TS U998 ( .A(n2421), .Y(n2407) );
NAND2X4TS U999 ( .A(n466), .B(n467), .Y(n1524) );
OR2X2TS U1000 ( .A(n1029), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n1030) );
AND2X2TS U1001 ( .A(n391), .B(n466), .Y(n2934) );
INVX6TS U1002 ( .A(n2830), .Y(n3379) );
NOR2X1TS U1003 ( .A(n422), .B(n450), .Y(n2303) );
INVX2TS U1004 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]),
.Y(n925) );
INVX2TS U1005 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]),
.Y(n833) );
INVX2TS U1006 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]),
.Y(n815) );
INVX6TS U1007 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(
n870) );
CLKMX2X2TS U1008 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[3]) );
CLKMX2X2TS U1009 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[4]) );
AND2X2TS U1010 ( .A(Op_MX[2]), .B(Op_MY[2]), .Y(n3055) );
INVX2TS U1011 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(
n2071) );
INVX2TS U1012 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(
n2069) );
CLKMX2X2TS U1013 ( .A(P_Sgf[35]), .B(n2403), .S0(n3224), .Y(n250) );
MX2X2TS U1014 ( .A(P_Sgf[32]), .B(n2357), .S0(n3304), .Y(n247) );
MX2X2TS U1015 ( .A(P_Sgf[33]), .B(n2348), .S0(n520), .Y(n248) );
CLKMX2X2TS U1016 ( .A(P_Sgf[31]), .B(n2344), .S0(n3304), .Y(n246) );
CLKMX2X2TS U1017 ( .A(P_Sgf[29]), .B(n2302), .S0(n3342), .Y(n244) );
CLKMX2X2TS U1018 ( .A(P_Sgf[30]), .B(n2295), .S0(n3342), .Y(n245) );
CLKMX2X2TS U1019 ( .A(P_Sgf[28]), .B(n3203), .S0(n3342), .Y(n243) );
NOR2X4TS U1020 ( .A(n1469), .B(DP_OP_156J23_125_3370_n293), .Y(n1453) );
CLKMX2X2TS U1021 ( .A(P_Sgf[27]), .B(n3214), .S0(n3342), .Y(n242) );
INVX4TS U1022 ( .A(n2287), .Y(n3202) );
CLKMX2X2TS U1023 ( .A(P_Sgf[26]), .B(n3225), .S0(n3342), .Y(n241) );
CLKMX2X2TS U1024 ( .A(P_Sgf[25]), .B(n3237), .S0(n3345), .Y(n240) );
CLKMX2X2TS U1025 ( .A(P_Sgf[24]), .B(n3248), .S0(n3224), .Y(n239) );
CLKMX2X2TS U1026 ( .A(P_Sgf[23]), .B(n3260), .S0(n3345), .Y(n238) );
CLKMX2X2TS U1027 ( .A(P_Sgf[22]), .B(n3310), .S0(n520), .Y(n237) );
CLKMX2X2TS U1028 ( .A(P_Sgf[21]), .B(n3339), .S0(n3345), .Y(n236) );
INVX3TS U1029 ( .A(n3199), .Y(n1302) );
CLKMX2X2TS U1030 ( .A(P_Sgf[20]), .B(n3330), .S0(n3304), .Y(n235) );
OAI21X1TS U1031 ( .A0(n3333), .A1(n3332), .B0(n3331), .Y(n3338) );
CLKMX2X2TS U1032 ( .A(P_Sgf[18]), .B(n3319), .S0(n3304), .Y(n233) );
CLKMX2X2TS U1033 ( .A(P_Sgf[19]), .B(n3326), .S0(n520), .Y(n234) );
OAI21X2TS U1034 ( .A0(n3232), .A1(n3244), .B0(n3233), .Y(n1272) );
OR2X2TS U1035 ( .A(n1357), .B(DP_OP_153J23_122_3500_n147), .Y(n1359) );
CLKMX2X2TS U1036 ( .A(P_Sgf[16]), .B(n3290), .S0(n3345), .Y(n231) );
INVX2TS U1037 ( .A(n1095), .Y(n406) );
CLKMX2X2TS U1038 ( .A(P_Sgf[17]), .B(n3277), .S0(n3345), .Y(n232) );
NOR2X1TS U1039 ( .A(n1383), .B(n1446), .Y(n1414) );
CLKMX2X2TS U1040 ( .A(P_Sgf[15]), .B(n3281), .S0(n3224), .Y(n230) );
NOR2X6TS U1041 ( .A(DP_OP_156J23_125_3370_n207), .B(
DP_OP_156J23_125_3370_n209), .Y(n1328) );
NOR2X6TS U1042 ( .A(n1294), .B(n1087), .Y(n1089) );
OAI21X1TS U1043 ( .A0(n3284), .A1(n3283), .B0(n3282), .Y(n3289) );
NOR2X6TS U1044 ( .A(DP_OP_158J23_127_356_n144), .B(DP_OP_158J23_127_356_n153), .Y(n1622) );
NOR2X1TS U1045 ( .A(n1595), .B(n1586), .Y(n1587) );
OR2X2TS U1046 ( .A(n1254), .B(n1253), .Y(n595) );
AOI21X2TS U1047 ( .A0(n1992), .A1(n588), .B0(n1981), .Y(n1989) );
OAI21X1TS U1048 ( .A0(n1790), .A1(n1786), .B0(n1787), .Y(n1785) );
OAI21X1TS U1049 ( .A0(n1779), .A1(n1764), .B0(n1763), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11)
);
NOR2X1TS U1050 ( .A(n1993), .B(n2005), .Y(n1997) );
OAI21X1TS U1051 ( .A0(n1779), .A1(n1768), .B0(n1767), .Y(n1771) );
OAI21X1TS U1052 ( .A0(n1779), .A1(n1772), .B0(n1776), .Y(n1775) );
OAI21X1TS U1053 ( .A0(n1779), .A1(n1752), .B0(n1751), .Y(n1758) );
INVX2TS U1054 ( .A(n2003), .Y(n1995) );
OAI21X1TS U1055 ( .A0(n1998), .A1(n2006), .B0(n1999), .Y(n1966) );
XOR2X1TS U1056 ( .A(n2702), .B(n2701), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7)
);
CLKMX2X2TS U1057 ( .A(n3263), .B(FSM_add_overflow_flag), .S0(n3130), .Y(n282) );
NAND2X2TS U1058 ( .A(DP_OP_156J23_125_3370_n240), .B(
DP_OP_156J23_125_3370_n242), .Y(n1238) );
CLKMX2X2TS U1059 ( .A(n3099), .B(Add_result[23]), .S0(n3241), .Y(n283) );
NAND2X2TS U1060 ( .A(n1961), .B(n1960), .Y(n2013) );
XOR2X1TS U1061 ( .A(n2777), .B(n2776), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7)
);
CLKMX2X2TS U1062 ( .A(n3104), .B(Add_result[22]), .S0(n3262), .Y(n284) );
ADDFHX2TS U1063 ( .A(n1663), .B(n1662), .CI(n1661), .CO(
DP_OP_158J23_127_356_n140), .S(DP_OP_158J23_127_356_n141) );
OAI21X1TS U1064 ( .A0(n2776), .A1(n2773), .B0(n2774), .Y(n2772) );
NAND2X4TS U1065 ( .A(n402), .B(n591), .Y(n1750) );
XOR2X1TS U1066 ( .A(n2707), .B(n2706), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6)
);
CLKMX2X2TS U1067 ( .A(n3109), .B(Add_result[21]), .S0(n3130), .Y(n285) );
OR2X2TS U1068 ( .A(n1980), .B(n1979), .Y(n588) );
NAND2X2TS U1069 ( .A(n1915), .B(n1914), .Y(n2023) );
NOR2X2TS U1070 ( .A(n490), .B(n1511), .Y(DP_OP_158J23_127_356_n259) );
OR2X2TS U1071 ( .A(n1534), .B(n1533), .Y(n572) );
OR2X2TS U1072 ( .A(n1986), .B(n589), .Y(n544) );
CLKMX2X2TS U1073 ( .A(n3115), .B(Add_result[20]), .S0(n3262), .Y(n286) );
XOR2X1TS U1074 ( .A(n2782), .B(n2781), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6)
);
XOR2X1TS U1075 ( .A(n2715), .B(n2714), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4)
);
OR2X2TS U1076 ( .A(n1733), .B(n1732), .Y(n569) );
OAI22X1TS U1077 ( .A0(Exp_module_Data_S[8]), .A1(n3350), .B0(n3349), .B1(
n3434), .Y(n272) );
CLKMX2X2TS U1078 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(
n3343), .Y(n281) );
XNOR2X2TS U1079 ( .A(DP_OP_36J23_129_4699_n1), .B(n3344), .Y(n3346) );
XOR2X1TS U1080 ( .A(n2790), .B(n2789), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4)
);
CLKMX2X2TS U1081 ( .A(n3120), .B(Add_result[19]), .S0(n3130), .Y(n287) );
OR2X2TS U1082 ( .A(n1756), .B(n1755), .Y(n592) );
OR2X2TS U1083 ( .A(DP_OP_158J23_127_356_n485), .B(n1735), .Y(n570) );
XOR2X1TS U1084 ( .A(n2720), .B(n2719), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3)
);
AND2X2TS U1085 ( .A(n555), .B(n1859), .Y(n556) );
AO21X1TS U1086 ( .A0(n1975), .A1(n525), .B0(n1973), .Y(n1983) );
AND2X2TS U1087 ( .A(n953), .B(n975), .Y(n532) );
CLKMX2X2TS U1088 ( .A(n3125), .B(Add_result[18]), .S0(n3262), .Y(n288) );
CLKMX2X2TS U1089 ( .A(P_Sgf[9]), .B(n3291), .S0(n3224), .Y(n224) );
NOR2X4TS U1090 ( .A(n1365), .B(n1368), .Y(n846) );
CLKMX2X2TS U1091 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(
n3343), .Y(n273) );
NAND3BX1TS U1092 ( .AN(Exp_module_Data_S[7]), .B(n3349), .C(n3348), .Y(n3350) );
NAND2X2TS U1093 ( .A(n1395), .B(n1394), .Y(n1396) );
OR2X2TS U1094 ( .A(n1985), .B(n1687), .Y(n589) );
OR2X2TS U1095 ( .A(n2587), .B(n2586), .Y(n2672) );
NAND4BX1TS U1096 ( .AN(n3347), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n3348) );
OR2X2TS U1097 ( .A(n1858), .B(n1857), .Y(n555) );
ADDHX1TS U1098 ( .A(n1729), .B(n1728), .CO(n1732), .S(n1731) );
XOR2X2TS U1099 ( .A(n638), .B(n637), .Y(n639) );
OR2X2TS U1100 ( .A(n1902), .B(n1901), .Y(n563) );
OR2X2TS U1101 ( .A(DP_OP_159J23_128_5719_n129), .B(
DP_OP_159J23_128_5719_n135), .Y(n590) );
CLKMX2X2TS U1102 ( .A(n3131), .B(Add_result[17]), .S0(n3262), .Y(n289) );
NAND2X2TS U1103 ( .A(n1497), .B(n1496), .Y(n1498) );
CLKMX2X2TS U1104 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(
n3343), .Y(n274) );
OR2X2TS U1105 ( .A(DP_OP_157J23_126_5719_n129), .B(
DP_OP_157J23_126_5719_n135), .Y(n554) );
OR2X2TS U1106 ( .A(n2616), .B(n2615), .Y(n2747) );
CLKMX2X2TS U1107 ( .A(n3137), .B(Add_result[16]), .S0(n3130), .Y(n290) );
INVX6TS U1108 ( .A(n914), .Y(n1497) );
NOR2X6TS U1109 ( .A(n952), .B(n951), .Y(n979) );
NOR2X4TS U1110 ( .A(n837), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n1375) );
CLKMX2X2TS U1111 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(
n3343), .Y(n275) );
NAND2BX1TS U1112 ( .AN(n2049), .B(n530), .Y(n1869) );
NAND2X2TS U1113 ( .A(n655), .B(n1544), .Y(n656) );
NOR2X1TS U1114 ( .A(n527), .B(n2330), .Y(n1755) );
CLKMX2X2TS U1115 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(
n3343), .Y(n276) );
CLKMX2X2TS U1116 ( .A(P_Sgf[7]), .B(n3305), .S0(n3224), .Y(n222) );
CLKMX2X2TS U1117 ( .A(n3142), .B(Add_result[15]), .S0(n3262), .Y(n291) );
INVX3TS U1118 ( .A(n1112), .Y(n796) );
OAI22X1TS U1119 ( .A0(n1924), .A1(n1943), .B0(n526), .B1(n471), .Y(n1947) );
CLKMX2X2TS U1120 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(
n3343), .Y(n280) );
OAI21X1TS U1121 ( .A0(n2519), .A1(n3003), .B0(n3005), .Y(n2520) );
OAI21X1TS U1122 ( .A0(n2466), .A1(n3076), .B0(n3078), .Y(n2467) );
NAND2BX1TS U1123 ( .AN(n2049), .B(n472), .Y(n1889) );
CLKMX2X2TS U1124 ( .A(n3147), .B(Add_result[14]), .S0(n3262), .Y(n292) );
OR2X2TS U1125 ( .A(n2601), .B(n2600), .Y(n2797) );
OAI21X1TS U1126 ( .A0(n2480), .A1(n2955), .B0(n2957), .Y(n2481) );
NAND2X2TS U1127 ( .A(n644), .B(n645), .Y(n637) );
CLKMX2X2TS U1128 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(
n3343), .Y(n277) );
XOR2X2TS U1129 ( .A(n2161), .B(n2160), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
CLKMX2X2TS U1130 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(
n3343), .Y(n278) );
OAI211X1TS U1131 ( .A0(n3432), .A1(n3344), .B0(n3171), .C0(n2454), .Y(n379)
);
XNOR2X2TS U1132 ( .A(n2169), .B(n2168), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
OAI21X1TS U1133 ( .A0(n2453), .A1(n3264), .B0(n2452), .Y(n376) );
NAND2X2TS U1134 ( .A(n1057), .B(n1056), .Y(n1059) );
AO21X1TS U1135 ( .A0(n3000), .A1(n2999), .B0(n3001), .Y(n2537) );
OR2X2TS U1136 ( .A(n520), .B(n542), .Y(n1467) );
AO21X1TS U1137 ( .A0(n2880), .A1(n2879), .B0(n2883), .Y(n2560) );
OR2X2TS U1138 ( .A(n3304), .B(n545), .Y(n1490) );
AO22X1TS U1139 ( .A0(Sgf_normalized_result[5]), .A1(n3395), .B0(
final_result_ieee[5]), .B1(n3394), .Y(n185) );
OR2X2TS U1140 ( .A(n3224), .B(n546), .Y(n1483) );
OAI21X1TS U1141 ( .A0(n2868), .A1(n2543), .B0(n2869), .Y(n2544) );
AO22X1TS U1142 ( .A0(Sgf_normalized_result[4]), .A1(n3395), .B0(
final_result_ieee[4]), .B1(n3394), .Y(n186) );
OR2X2TS U1143 ( .A(n3342), .B(n3401), .Y(n1429) );
AO21X1TS U1144 ( .A0(Sgf_normalized_result[23]), .A1(n3171), .B0(n3102), .Y(
n307) );
OR2X2TS U1145 ( .A(n3304), .B(n543), .Y(n1455) );
OAI21X1TS U1146 ( .A0(n3407), .A1(n3267), .B0(FS_Module_state_reg[3]), .Y(
n2454) );
AO21X1TS U1147 ( .A0(n3011), .A1(n3012), .B0(n3013), .Y(n2501) );
OAI31XLTS U1148 ( .A0(FS_Module_state_reg[0]), .A1(FS_Module_state_reg[2]),
.A2(n3410), .B0(n2624), .Y(n377) );
NOR2X4TS U1149 ( .A(n3342), .B(n3349), .Y(n3343) );
AO22X1TS U1150 ( .A0(Sgf_normalized_result[6]), .A1(n3395), .B0(
final_result_ieee[6]), .B1(n3394), .Y(n184) );
ADDHX2TS U1151 ( .A(n1673), .B(n1920), .CO(n1674), .S(n1528) );
CLKMX2X2TS U1152 ( .A(P_Sgf[3]), .B(Sgf_operation_Result[3]), .S0(n3224),
.Y(n218) );
AO22X1TS U1153 ( .A0(Sgf_normalized_result[7]), .A1(n3395), .B0(
final_result_ieee[7]), .B1(n3394), .Y(n183) );
AO22X1TS U1154 ( .A0(Sgf_normalized_result[8]), .A1(n3395), .B0(
final_result_ieee[8]), .B1(n3394), .Y(n182) );
CLKMX2X2TS U1155 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n2826), .Y(n349) );
NOR2X1TS U1156 ( .A(n2896), .B(n2898), .Y(intadd_57_B_2_) );
NOR2X1TS U1157 ( .A(n2599), .B(n2813), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0)
);
CLKMX2X2TS U1158 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n2826), .Y(n370) );
NOR2X1TS U1159 ( .A(n2570), .B(n2740), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0)
);
NOR2X1TS U1160 ( .A(n3061), .B(n3053), .Y(n3059) );
OR2X2TS U1161 ( .A(FSM_selector_C), .B(n2409), .Y(n449) );
NOR2X1TS U1162 ( .A(n3085), .B(n3084), .Y(n2635) );
CLKMX2X2TS U1163 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n2826), .Y(n335) );
NOR2X1TS U1164 ( .A(n2800), .B(Op_MX[17]), .Y(n2273) );
AO22X1TS U1165 ( .A0(n2827), .A1(Data_MY[31]), .B0(n3390), .B1(Op_MY[31]),
.Y(n310) );
CLKMX2X2TS U1166 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n2826), .Y(n368) );
NOR2X1TS U1167 ( .A(n2993), .B(n2994), .Y(n2998) );
NOR2X1TS U1168 ( .A(n2964), .B(n2963), .Y(n2646) );
NOR2X1TS U1169 ( .A(n3417), .B(n2442), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1) );
XNOR2X2TS U1170 ( .A(n1557), .B(n3352), .Y(n658) );
CLKMX2X2TS U1171 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n2826), .Y(n339) );
NOR2X1TS U1172 ( .A(n2726), .B(n2731), .Y(n2564) );
NOR2X1TS U1173 ( .A(n2485), .B(n2484), .Y(intadd_55_A_1_) );
NAND2BX1TS U1174 ( .AN(n2049), .B(n1884), .Y(n1885) );
AO22X1TS U1175 ( .A0(n2827), .A1(Data_MX[31]), .B0(n3390), .B1(Op_MX[31]),
.Y(n343) );
NOR2X1TS U1176 ( .A(n1808), .B(n1811), .Y(n1814) );
NOR2X1TS U1177 ( .A(n3067), .B(n3066), .Y(n3071) );
CLKMX2X2TS U1178 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n2826), .Y(n336) );
NOR2X1TS U1179 ( .A(n2945), .B(n2946), .Y(n2950) );
NAND2X2TS U1180 ( .A(n902), .B(n901), .Y(n903) );
INVX2TS U1181 ( .A(n1884), .Y(n1930) );
MXI2X1TS U1182 ( .A(n2877), .B(n2878), .S0(n2876), .Y(n2883) );
AND2X2TS U1183 ( .A(n2842), .B(n3461), .Y(n3417) );
OR2X2TS U1184 ( .A(n1884), .B(n622), .Y(n436) );
NOR2X4TS U1185 ( .A(n3101), .B(n3423), .Y(n3110) );
OR2X2TS U1186 ( .A(n3101), .B(FSM_selector_C), .Y(n3251) );
INVX2TS U1187 ( .A(n2827), .Y(n3390) );
OAI21X1TS U1188 ( .A0(n3050), .A1(n3046), .B0(n3045), .Y(n3047) );
AO21X1TS U1189 ( .A0(n2987), .A1(n2988), .B0(n2990), .Y(n2491) );
OAI21X1TS U1190 ( .A0(n2929), .A1(n2925), .B0(n2924), .Y(n2926) );
AOI211X1TS U1191 ( .A0(FSM_selector_B[0]), .A1(n2448), .B0(n3136), .C0(n3349), .Y(n3457) );
ADDFHX2TS U1192 ( .A(n513), .B(n2834), .CI(n1522), .CO(n678), .S(n1673) );
AND2X2TS U1193 ( .A(n2254), .B(n2325), .Y(n409) );
NOR2X1TS U1194 ( .A(n2530), .B(n2529), .Y(n2531) );
AO21X1TS U1195 ( .A0(n2534), .A1(n2535), .B0(n2533), .Y(n2419) );
AND2X2TS U1196 ( .A(n2243), .B(n2252), .Y(n2249) );
OR2X4TS U1197 ( .A(n822), .B(n827), .Y(n823) );
AND2X2TS U1198 ( .A(n2230), .B(n2235), .Y(n2239) );
AO21X1TS U1199 ( .A0(n2912), .A1(n2911), .B0(n2910), .Y(n2417) );
BUFX4TS U1200 ( .A(n2422), .Y(n506) );
NAND3X1TS U1201 ( .A(n2308), .B(n2307), .C(n2306), .Y(n2310) );
NOR2X1TS U1202 ( .A(n2902), .B(n2901), .Y(n2903) );
NOR2X1TS U1203 ( .A(n3023), .B(n3022), .Y(n3024) );
OAI21X1TS U1204 ( .A0(n1564), .A1(n1570), .B0(n1571), .Y(n1501) );
AO21X1TS U1205 ( .A0(n3033), .A1(n3032), .B0(n3031), .Y(n2415) );
NAND2X4TS U1206 ( .A(n538), .B(n1517), .Y(n1511) );
OR2X2TS U1207 ( .A(n2426), .B(n2428), .Y(n2332) );
NOR2X1TS U1208 ( .A(n2494), .B(n2495), .Y(n2499) );
AND2X2TS U1209 ( .A(n2312), .B(n548), .Y(n603) );
OR2X2TS U1210 ( .A(Op_MY[0]), .B(n3362), .Y(n538) );
INVX2TS U1211 ( .A(n1514), .Y(n1516) );
OAI21X1TS U1212 ( .A0(n3409), .A1(n3414), .B0(n2488), .Y(n2489) );
AND2X2TS U1213 ( .A(n3371), .B(n3351), .Y(n2495) );
NAND2X2TS U1214 ( .A(n2825), .B(n2404), .Y(n2441) );
NAND2X2TS U1215 ( .A(n2829), .B(n3371), .Y(n1553) );
NOR2X1TS U1216 ( .A(n3218), .B(Sgf_normalized_result[2]), .Y(n3219) );
NOR2X4TS U1217 ( .A(n818), .B(n817), .Y(n827) );
OR2X2TS U1218 ( .A(Op_MY[6]), .B(Op_MY[0]), .Y(n2243) );
NOR2X1TS U1219 ( .A(n488), .B(n395), .Y(n2321) );
NAND2X4TS U1220 ( .A(n949), .B(n948), .Y(n955) );
OR2X2TS U1221 ( .A(n3362), .B(n413), .Y(n2230) );
NAND3X1TS U1222 ( .A(n3266), .B(P_Sgf[47]), .C(n2446), .Y(n2448) );
OR2X2TS U1223 ( .A(n2140), .B(n2139), .Y(n2172) );
NOR2X1TS U1224 ( .A(n2934), .B(n2935), .Y(n2638) );
AND2X2TS U1225 ( .A(n3369), .B(n3355), .Y(n3056) );
OR2X2TS U1226 ( .A(n2138), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .Y(n2139) );
ADDFHX2TS U1227 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]),
.B(n850), .CI(n833), .CO(n834), .S(n818) );
OR2X2TS U1228 ( .A(n2174), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .Y(n2175) );
NOR2X1TS U1229 ( .A(n3095), .B(n3418), .Y(n3097) );
AND2X2TS U1230 ( .A(n461), .B(Op_MY[9]), .Y(n2975) );
AND2X2TS U1231 ( .A(n3372), .B(n3351), .Y(n2974) );
AND2X2TS U1232 ( .A(n3372), .B(n420), .Y(n2494) );
CLKMX2X2TS U1233 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[5]) );
CLKMX2X2TS U1234 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[6]) );
CLKMX2X2TS U1235 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[7]) );
AND2X2TS U1236 ( .A(n419), .B(Op_MY[16]), .Y(n2935) );
BUFX3TS U1237 ( .A(n3411), .Y(n488) );
NOR2X1TS U1238 ( .A(n574), .B(n575), .Y(intadd_55_A_8_) );
INVX4TS U1239 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]),
.Y(n1008) );
INVX3TS U1240 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(
n816) );
NOR3XLTS U1241 ( .A(n419), .B(Op_MX[24]), .C(Op_MX[23]), .Y(n451) );
MX2X1TS U1242 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
OR2X2TS U1243 ( .A(FSM_selector_B[1]), .B(n3413), .Y(n2815) );
NOR2X1TS U1244 ( .A(n548), .B(n566), .Y(intadd_54_A_8_) );
NAND2X4TS U1245 ( .A(Op_MX[1]), .B(Op_MX[13]), .Y(n607) );
OR2X2TS U1246 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
INVX4TS U1247 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[3]), .Y(
n698) );
INVX4TS U1248 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(
n697) );
INVX6TS U1249 ( .A(Sgf_operation_Result[5]), .Y(n880) );
NAND2X4TS U1250 ( .A(DP_OP_156J23_125_3370_n213), .B(
DP_OP_156J23_125_3370_n215), .Y(n1105) );
CLKINVX6TS U1251 ( .A(n710), .Y(n757) );
NAND2X2TS U1252 ( .A(n668), .B(n1543), .Y(n669) );
INVX4TS U1253 ( .A(Sgf_operation_Result[4]), .Y(n1041) );
CLKINVX6TS U1254 ( .A(n1185), .Y(n407) );
INVX8TS U1255 ( .A(n407), .Y(n408) );
ADDFX2TS U1256 ( .A(n969), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]), .CI(n968),
.CO(n970), .S(n959) );
NAND2X4TS U1257 ( .A(n962), .B(n963), .Y(n997) );
NOR2X8TS U1258 ( .A(n691), .B(n684), .Y(n767) );
ADDFHX2TS U1259 ( .A(n1658), .B(n1657), .CI(n1656), .CO(
DP_OP_158J23_127_356_n126), .S(DP_OP_158J23_127_356_n127) );
INVX4TS U1260 ( .A(n1585), .Y(n1604) );
AOI21X2TS U1261 ( .A0(n1407), .A1(n1388), .B0(n1387), .Y(n1393) );
AOI21X1TS U1262 ( .A0(n1407), .A1(n1399), .B0(n1398), .Y(n1403) );
NOR2X6TS U1263 ( .A(n1366), .B(n1368), .Y(n848) );
NOR2X8TS U1264 ( .A(n843), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n1366) );
OAI21X4TS U1265 ( .A0(n829), .A1(n823), .B0(n828), .Y(n830) );
NOR2X4TS U1266 ( .A(n868), .B(n867), .Y(n876) );
NAND2X4TS U1267 ( .A(n868), .B(n867), .Y(n901) );
XOR2X2TS U1268 ( .A(n2186), .B(n2185), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
OAI21X1TS U1269 ( .A0(n1003), .A1(n996), .B0(n999), .Y(n985) );
OAI21X2TS U1270 ( .A0(n1003), .A1(n1002), .B0(n1001), .Y(n1004) );
NOR2X4TS U1271 ( .A(n917), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(n2207) );
AOI21X4TS U1272 ( .A0(n760), .A1(n716), .B0(n715), .Y(n717) );
NOR2X6TS U1273 ( .A(n712), .B(n711), .Y(n741) );
NOR2X8TS U1274 ( .A(n714), .B(n713), .Y(n746) );
NAND2X4TS U1275 ( .A(DP_OP_158J23_127_356_n143), .B(
DP_OP_158J23_127_356_n136), .Y(n1618) );
AOI21X4TS U1276 ( .A0(n924), .A1(n941), .B0(n939), .Y(n885) );
NAND2X6TS U1277 ( .A(n1977), .B(n1866), .Y(n1985) );
OAI21X1TS U1278 ( .A0(n1995), .A1(n2005), .B0(n2006), .Y(n1996) );
INVX4TS U1279 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(
n689) );
OAI21X2TS U1280 ( .A0(n788), .A1(n787), .B0(n786), .Y(n793) );
NAND2X4TS U1281 ( .A(n794), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n1101) );
NOR2X4TS U1282 ( .A(n1343), .B(n1345), .Y(n802) );
XNOR2X4TS U1283 ( .A(n2181), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
OAI21X4TS U1284 ( .A0(n2180), .A1(n2176), .B0(n2177), .Y(n2181) );
OAI21X4TS U1285 ( .A0(n2145), .A1(n2142), .B0(n2146), .Y(n2118) );
AOI21X4TS U1286 ( .A0(n1006), .A1(n962), .B0(n964), .Y(n961) );
OAI21X4TS U1287 ( .A0(n921), .A1(n934), .B0(n936), .Y(n922) );
XNOR2X1TS U1288 ( .A(n1029), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n1028) );
CMPR42X2TS U1289 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]),
.B(DP_OP_156J23_125_3370_n252), .C(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .D(
DP_OP_156J23_125_3370_n250), .ICI(DP_OP_156J23_125_3370_n281), .S(
DP_OP_156J23_125_3370_n249), .ICO(DP_OP_156J23_125_3370_n247), .CO(
DP_OP_156J23_125_3370_n248) );
NAND2X2TS U1290 ( .A(DP_OP_158J23_127_356_n163), .B(
DP_OP_158J23_127_356_n172), .Y(n1632) );
OAI22X4TS U1291 ( .A0(n517), .A1(n1693), .B0(n1702), .B1(n1692), .Y(n682) );
NAND2X4TS U1292 ( .A(DP_OP_156J23_125_3370_n207), .B(
DP_OP_156J23_125_3370_n209), .Y(n1332) );
OAI21X4TS U1293 ( .A0(n841), .A1(n840), .B0(n839), .Y(n842) );
NAND2X4TS U1294 ( .A(n805), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n1400) );
NOR2X4TS U1295 ( .A(n767), .B(n789), .Y(n696) );
NAND2X4TS U1296 ( .A(n807), .B(n806), .Y(n1390) );
NOR2X8TS U1297 ( .A(n807), .B(n806), .Y(n1389) );
XOR2X2TS U1298 ( .A(n2180), .B(n2179), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
NAND2X4TS U1299 ( .A(DP_OP_156J23_125_3370_n234), .B(
DP_OP_156J23_125_3370_n236), .Y(n1263) );
AOI21X2TS U1300 ( .A0(n924), .A1(n923), .B0(n922), .Y(n931) );
INVX4TS U1301 ( .A(n941), .Y(n920) );
INVX6TS U1302 ( .A(n1494), .Y(n2206) );
NOR2X8TS U1303 ( .A(n1166), .B(n1169), .Y(n981) );
NOR2X6TS U1304 ( .A(n977), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n1169) );
INVX4TS U1305 ( .A(n891), .Y(n853) );
NAND2X4TS U1306 ( .A(n1289), .B(n1288), .Y(n1290) );
AOI21X2TS U1307 ( .A0(n1192), .A1(n535), .B0(n1050), .Y(n1206) );
NOR2X8TS U1308 ( .A(DP_OP_156J23_125_3370_n222), .B(
DP_OP_156J23_125_3370_n224), .Y(n1283) );
INVX6TS U1309 ( .A(n2215), .Y(DP_OP_156J23_125_3370_n297) );
OAI21X2TS U1310 ( .A0(n1230), .A1(n1229), .B0(n1228), .Y(n1232) );
OR2X4TS U1311 ( .A(n949), .B(n948), .Y(n962) );
INVX4TS U1312 ( .A(n939), .Y(n921) );
NOR2X8TS U1313 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]),
.B(n976), .Y(n1166) );
ADDFHX4TS U1314 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]),
.B(n947), .CI(n946), .CO(n948), .S(n928) );
AOI21X4TS U1315 ( .A0(n981), .A1(n1163), .B0(n978), .Y(n983) );
OAI21X4TS U1316 ( .A0(n1169), .A1(n1164), .B0(n1170), .Y(n978) );
NOR2X4TS U1317 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]),
.B(n932), .Y(n980) );
NAND2X6TS U1318 ( .A(n932), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(n1132) );
NAND2X4TS U1319 ( .A(n441), .B(n1152), .Y(n982) );
NAND2X4TS U1320 ( .A(n3370), .B(Op_MX[17]), .Y(n663) );
XNOR2X2TS U1321 ( .A(n2749), .B(n2748), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12)
);
OAI21X4TS U1322 ( .A0(n2766), .A1(n2745), .B0(n2744), .Y(n2749) );
AOI21X2TS U1323 ( .A0(n2750), .A1(n2755), .B0(n2612), .Y(n2613) );
NOR2X4TS U1324 ( .A(n3379), .B(n394), .Y(n662) );
OAI21X1TS U1325 ( .A0(n1551), .A1(n662), .B0(n661), .Y(n665) );
NOR2X4TS U1326 ( .A(n994), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n1012) );
AOI21X2TS U1327 ( .A0(n1006), .A1(n986), .B0(n985), .Y(n993) );
INVX6TS U1328 ( .A(n2212), .Y(DP_OP_156J23_125_3370_n273) );
CMPR42X2TS U1329 ( .A(DP_OP_158J23_127_356_n247), .B(
DP_OP_158J23_127_356_n190), .C(DP_OP_158J23_127_356_n193), .D(
DP_OP_158J23_127_356_n263), .ICI(DP_OP_158J23_127_356_n191), .S(
DP_OP_158J23_127_356_n188), .ICO(DP_OP_158J23_127_356_n186), .CO(
DP_OP_158J23_127_356_n187) );
OAI21X1TS U1330 ( .A0(n2766), .A1(n2619), .B0(n2618), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13)
);
NOR2X6TS U1331 ( .A(n838), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n1378) );
XOR2X4TS U1332 ( .A(n841), .B(n836), .Y(n838) );
INVX4TS U1333 ( .A(Sgf_operation_Result[0]), .Y(n893) );
XNOR2X4TS U1334 ( .A(n1248), .B(n1218), .Y(n1235) );
OAI21X2TS U1335 ( .A0(n3334), .A1(n3331), .B0(n3335), .Y(n1236) );
NAND2X4TS U1336 ( .A(DP_OP_158J23_127_356_n144), .B(
DP_OP_158J23_127_356_n153), .Y(n1623) );
CMPR22X2TS U1337 ( .A(n1679), .B(n1678), .CO(DP_OP_158J23_127_356_n184), .S(
n1676) );
OR2X8TS U1338 ( .A(DP_OP_156J23_125_3370_n234), .B(
DP_OP_156J23_125_3370_n236), .Y(n1262) );
XNOR2X4TS U1339 ( .A(n2059), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .Y(n2058) );
AOI21X4TS U1340 ( .A0(n1377), .A1(n845), .B0(n847), .Y(n1367) );
NOR2X4TS U1341 ( .A(n1375), .B(n1378), .Y(n845) );
OAI21X2TS U1342 ( .A0(n2786), .A1(n2789), .B0(n2787), .Y(n2784) );
OAI21X4TS U1343 ( .A0(n1332), .A1(n1331), .B0(n1330), .Y(n1333) );
NOR2X2TS U1344 ( .A(n1846), .B(n1851), .Y(n1832) );
INVX2TS U1345 ( .A(n2207), .Y(n2209) );
AOI21X2TS U1346 ( .A0(n2039), .A1(n563), .B0(n1903), .Y(n2035) );
OAI21X1TS U1347 ( .A0(n2031), .A1(n2027), .B0(n2028), .Y(n2026) );
ADDFHX2TS U1348 ( .A(n957), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]), .CI(n956),
.CO(n958), .S(n949) );
NOR2X4TS U1349 ( .A(n1485), .B(DP_OP_156J23_125_3370_n295), .Y(n1465) );
NOR2X8TS U1350 ( .A(n1417), .B(n2198), .Y(n1458) );
ADDFHX4TS U1351 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]),
.B(n690), .CI(n689), .CO(n693), .S(n692) );
XOR2X4TS U1352 ( .A(n739), .B(n738), .Y(n807) );
XNOR2X4TS U1353 ( .A(n2206), .B(n2205), .Y(n3291) );
XNOR2X4TS U1354 ( .A(n911), .B(n910), .Y(n912) );
OAI21X4TS U1355 ( .A0(n906), .A1(n905), .B0(n904), .Y(n911) );
OAI22X2TS U1356 ( .A0(n403), .A1(n1690), .B0(n1702), .B1(n1691), .Y(n683) );
XNOR2X4TS U1357 ( .A(n666), .B(n3367), .Y(n654) );
AOI21X4TS U1358 ( .A0(n1488), .A1(n460), .B0(n1487), .Y(n1489) );
NOR2X6TS U1359 ( .A(n1220), .B(n1222), .Y(n1021) );
NOR2X8TS U1360 ( .A(n1018), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n1229) );
AOI21X4TS U1361 ( .A0(n1453), .A1(n460), .B0(n1452), .Y(n1454) );
OAI21X4TS U1362 ( .A0(n1378), .A1(n1394), .B0(n1379), .Y(n847) );
AOI21X4TS U1363 ( .A0(n1465), .A1(n460), .B0(n1464), .Y(n1466) );
OAI21X4TS U1364 ( .A0(n1015), .A1(n1014), .B0(n1013), .Y(n1016) );
INVX6TS U1365 ( .A(n2197), .Y(DP_OP_156J23_125_3370_n266) );
NOR2X4TS U1366 ( .A(DP_OP_158J23_127_356_n154), .B(DP_OP_158J23_127_356_n162), .Y(n1627) );
NAND2X4TS U1367 ( .A(n644), .B(n578), .Y(n648) );
CMPR42X2TS U1368 ( .A(DP_OP_158J23_127_356_n251), .B(
DP_OP_158J23_127_356_n161), .C(DP_OP_158J23_127_356_n160), .D(
DP_OP_158J23_127_356_n165), .ICI(DP_OP_158J23_127_356_n157), .S(
DP_OP_158J23_127_356_n154), .ICO(DP_OP_158J23_127_356_n152), .CO(
DP_OP_158J23_127_356_n153) );
AOI21X4TS U1369 ( .A0(n1023), .A1(n1024), .B0(n780), .Y(n1100) );
XOR2X4TS U1370 ( .A(n788), .B(n768), .Y(n779) );
AOI21X4TS U1371 ( .A0(n1472), .A1(n460), .B0(n1471), .Y(n1474) );
NAND2X4TS U1372 ( .A(DP_OP_156J23_125_3370_n204), .B(
DP_OP_156J23_125_3370_n206), .Y(n1330) );
XNOR2X4TS U1373 ( .A(n1243), .B(n1242), .Y(DP_OP_156J23_125_3370_n267) );
AOI21X4TS U1374 ( .A0(n1225), .A1(n1226), .B0(n1068), .Y(n1216) );
OAI21X2TS U1375 ( .A0(n1206), .A1(n1203), .B0(n1204), .Y(n1226) );
XNOR2X4TS U1376 ( .A(n776), .B(DP_OP_154J23_123_2814_n140), .Y(n1047) );
AOI21X4TS U1377 ( .A0(n2218), .A1(n2217), .B0(n900), .Y(n1494) );
OAI21X4TS U1378 ( .A0(n1055), .A1(n1058), .B0(n1056), .Y(n2218) );
XOR2X4TS U1379 ( .A(n906), .B(n898), .Y(n899) );
OAI21X2TS U1380 ( .A0(n1283), .A1(n1288), .B0(n1284), .Y(n1291) );
XOR2X4TS U1381 ( .A(n765), .B(n764), .Y(n800) );
AO21X4TS U1382 ( .A0(n784), .A1(n761), .B0(n760), .Y(n765) );
NAND2X6TS U1383 ( .A(n1199), .B(n1020), .Y(n1220) );
NOR2X8TS U1384 ( .A(DP_OP_156J23_125_3370_n204), .B(
DP_OP_156J23_125_3370_n206), .Y(n1331) );
NAND2X4TS U1385 ( .A(n2358), .B(n1314), .Y(n1316) );
INVX4TS U1386 ( .A(n2200), .Y(DP_OP_156J23_125_3370_n268) );
NAND2X4TS U1387 ( .A(n2389), .B(n2391), .Y(n1477) );
AOI21X4TS U1388 ( .A0(n1548), .A1(n1547), .B0(n1546), .Y(n1654) );
XNOR2X4TS U1389 ( .A(n665), .B(n664), .Y(n1940) );
OAI21X1TS U1390 ( .A0(n1812), .A1(n1811), .B0(n1810), .Y(n1813) );
XNOR2X2TS U1391 ( .A(n1864), .B(n1860), .Y(n1974) );
OAI21X2TS U1392 ( .A0(n1080), .A1(n1294), .B0(n1295), .Y(n1081) );
INVX2TS U1393 ( .A(n2360), .Y(n2363) );
NOR2X8TS U1394 ( .A(n934), .B(n937), .Y(n940) );
NOR2X8TS U1395 ( .A(n927), .B(n928), .Y(n937) );
INVX2TS U1396 ( .A(n1161), .Y(n1162) );
XOR2X4TS U1397 ( .A(n885), .B(n884), .Y(n918) );
NAND2X6TS U1398 ( .A(n1417), .B(n2198), .Y(n2390) );
XOR2X4TS U1399 ( .A(n1232), .B(n1231), .Y(n428) );
INVX16TS U1400 ( .A(n2402), .Y(n460) );
INVX8TS U1401 ( .A(n1317), .Y(n2402) );
OA21X4TS U1402 ( .A0(n824), .A1(n751), .B0(n829), .Y(n739) );
XOR2X4TS U1403 ( .A(n1397), .B(n1396), .Y(n2376) );
XOR2X4TS U1404 ( .A(n875), .B(n874), .Y(n917) );
AOI21X4TS U1405 ( .A0(n924), .A1(n902), .B0(n869), .Y(n875) );
NOR2X4TS U1406 ( .A(n1458), .B(n1418), .Y(n1420) );
OAI21X4TS U1407 ( .A0(n2367), .A1(n2361), .B0(n2368), .Y(n1313) );
NAND2X4TS U1408 ( .A(DP_OP_156J23_125_3370_n228), .B(
DP_OP_156J23_125_3370_n230), .Y(n1118) );
NAND2X4TS U1409 ( .A(n1300), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[5]), .Y(n2299) );
OR2X8TS U1410 ( .A(n1300), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[5]), .Y(n560) );
XOR2X4TS U1411 ( .A(n759), .B(n758), .Y(n799) );
AO21X4TS U1412 ( .A0(n784), .A1(n782), .B0(n781), .Y(n759) );
XOR2X4TS U1413 ( .A(n1403), .B(n1402), .Y(n2214) );
NOR2X8TS U1414 ( .A(n1312), .B(n2201), .Y(n2367) );
XOR2X4TS U1415 ( .A(n974), .B(n973), .Y(n977) );
AOI21X4TS U1416 ( .A0(n1006), .A1(n967), .B0(n984), .Y(n974) );
CMPR42X2TS U1417 ( .A(DP_OP_158J23_127_356_n245), .B(
DP_OP_158J23_127_356_n182), .C(DP_OP_158J23_127_356_n261), .D(
DP_OP_158J23_127_356_n179), .ICI(DP_OP_158J23_127_356_n176), .S(
DP_OP_158J23_127_356_n173), .ICO(DP_OP_158J23_127_356_n171), .CO(
DP_OP_158J23_127_356_n172) );
XOR2X4TS U1418 ( .A(n1527), .B(n1526), .Y(n1920) );
OAI21X4TS U1419 ( .A0(n1638), .A1(n1635), .B0(n1636), .Y(n1633) );
AOI21X4TS U1420 ( .A0(n1641), .A1(n427), .B0(n1537), .Y(n1638) );
OAI21X4TS U1421 ( .A0(n1087), .A1(n1295), .B0(n1086), .Y(n1088) );
NAND2X4TS U1422 ( .A(DP_OP_156J23_125_3370_n216), .B(
DP_OP_156J23_125_3370_n218), .Y(n1086) );
NOR2X8TS U1423 ( .A(DP_OP_156J23_125_3370_n216), .B(
DP_OP_156J23_125_3370_n218), .Y(n1087) );
AOI21X2TS U1424 ( .A0(n1329), .A1(n1356), .B0(n1334), .Y(n1108) );
NOR2X6TS U1425 ( .A(n2362), .B(n2367), .Y(n1314) );
INVX4TS U1426 ( .A(n955), .Y(n964) );
OAI21X4TS U1427 ( .A0(n3274), .A1(n1215), .B0(n1214), .Y(n3327) );
NAND2X2TS U1428 ( .A(n3321), .B(n400), .Y(n1215) );
AOI21X2TS U1429 ( .A0(n3320), .A1(n400), .B0(n1213), .Y(n1214) );
XNOR2X4TS U1430 ( .A(n1189), .B(n1188), .Y(n552) );
NAND2X4TS U1431 ( .A(n1308), .B(n1307), .Y(n2349) );
OAI21X4TS U1432 ( .A0(n1216), .A1(n1071), .B0(n1070), .Y(n1240) );
NAND2X2TS U1433 ( .A(n1310), .B(n1309), .Y(n2353) );
XOR2X4TS U1434 ( .A(n890), .B(n889), .Y(n895) );
OAI21X4TS U1435 ( .A0(n1994), .A1(n1969), .B0(n1968), .Y(n1992) );
INVX6TS U1436 ( .A(n1940), .Y(n528) );
XOR2X4TS U1437 ( .A(n1252), .B(n1251), .Y(n1254) );
XNOR2X4TS U1438 ( .A(n894), .B(n893), .Y(n1045) );
NAND2X4TS U1439 ( .A(n892), .B(n891), .Y(n894) );
NOR2X6TS U1440 ( .A(DP_OP_156J23_125_3370_n210), .B(
DP_OP_156J23_125_3370_n212), .Y(n1106) );
AOI21X4TS U1441 ( .A0(n1433), .A1(n2388), .B0(n1432), .Y(n2374) );
NAND2X4TS U1442 ( .A(DP_OP_156J23_125_3370_n237), .B(
DP_OP_156J23_125_3370_n239), .Y(n1266) );
INVX4TS U1443 ( .A(n1116), .Y(n1126) );
XNOR2X4TS U1444 ( .A(n793), .B(n792), .Y(n794) );
XNOR2X2TS U1445 ( .A(n1241), .B(n1240), .Y(n1256) );
NOR2X4TS U1446 ( .A(n1308), .B(n1307), .Y(n2342) );
XOR2X4TS U1447 ( .A(n821), .B(n820), .Y(n837) );
XOR2X4TS U1448 ( .A(n1265), .B(n1264), .Y(n1271) );
AOI21X4TS U1449 ( .A0(n1268), .A1(n1267), .B0(n1261), .Y(n1265) );
AOI21X4TS U1450 ( .A0(n1240), .A1(n1239), .B0(n1072), .Y(n1260) );
AOI21X4TS U1451 ( .A0(n460), .A1(n1480), .B0(n1479), .Y(n1482) );
AOI21X4TS U1452 ( .A0(n1177), .A1(n1175), .B0(n1040), .Y(n1197) );
OAI21X2TS U1453 ( .A0(n1127), .A1(n1130), .B0(n1128), .Y(n1150) );
AOI21X4TS U1454 ( .A0(n460), .A1(n1435), .B0(n1434), .Y(n1436) );
INVX4TS U1455 ( .A(n1260), .Y(n1268) );
OA21X4TS U1456 ( .A0(n646), .A1(n1505), .B0(n645), .Y(n647) );
OAI22X2TS U1457 ( .A0(n517), .A1(n1691), .B0(n1702), .B1(n1690), .Y(n1661)
);
INVX4TS U1458 ( .A(n671), .Y(n517) );
NOR2X4TS U1459 ( .A(n1860), .B(n636), .Y(n646) );
XOR2X4TS U1460 ( .A(n634), .B(n633), .Y(n1860) );
CMPR42X2TS U1461 ( .A(DP_OP_158J23_127_356_n207), .B(
DP_OP_158J23_127_356_n131), .C(DP_OP_158J23_127_356_n127), .D(
DP_OP_158J23_127_356_n132), .ICI(DP_OP_158J23_127_356_n128), .S(
DP_OP_158J23_127_356_n125), .ICO(DP_OP_158J23_127_356_n123), .CO(
DP_OP_158J23_127_356_n124) );
OAI21X4TS U1462 ( .A0(n1630), .A1(n1627), .B0(n1628), .Y(n1616) );
AOI21X4TS U1463 ( .A0(n1633), .A1(n579), .B0(n1538), .Y(n1630) );
XNOR2X4TS U1464 ( .A(n605), .B(n609), .Y(n606) );
NAND2X2TS U1465 ( .A(n534), .B(n607), .Y(n605) );
OAI21X4TS U1466 ( .A0(n1643), .A1(n1646), .B0(n1644), .Y(n1641) );
AOI21X2TS U1467 ( .A0(n572), .A1(n1649), .B0(n1535), .Y(n1646) );
OR2X2TS U1468 ( .A(n1557), .B(n3352), .Y(n1659) );
NAND2X1TS U1469 ( .A(n1743), .B(n2824), .Y(n1741) );
INVX2TS U1470 ( .A(n673), .Y(n675) );
NAND2X1TS U1471 ( .A(n610), .B(n625), .Y(n626) );
ADDFHX2TS U1472 ( .A(n1668), .B(n1667), .CI(n1666), .CO(
DP_OP_158J23_127_356_n167), .S(DP_OP_158J23_127_356_n168) );
INVX2TS U1473 ( .A(n1552), .Y(n1554) );
INVX2TS U1474 ( .A(n1570), .Y(n1572) );
INVX2TS U1475 ( .A(n1742), .Y(n1838) );
INVX4TS U1476 ( .A(n1558), .Y(n1569) );
NOR2X4TS U1477 ( .A(n1550), .B(n1552), .Y(n618) );
OAI21X2TS U1478 ( .A0(n1794), .A1(n1791), .B0(n1792), .Y(n1780) );
NOR2X2TS U1479 ( .A(n2187), .B(n2091), .Y(n2093) );
INVX2TS U1480 ( .A(n1512), .Y(n623) );
OAI21X2TS U1481 ( .A0(n2182), .A1(n2185), .B0(n2183), .Y(n2150) );
INVX6TS U1482 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(
n879) );
INVX2TS U1483 ( .A(n1956), .Y(n1946) );
INVX2TS U1484 ( .A(n619), .Y(n609) );
NOR2X2TS U1485 ( .A(n495), .B(n1687), .Y(n1663) );
NOR2X1TS U1486 ( .A(n1687), .B(n497), .Y(n1670) );
NOR2X1TS U1487 ( .A(n475), .B(n2808), .Y(n2436) );
NOR2X4TS U1488 ( .A(n803), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n1363) );
OAI22X1TS U1489 ( .A0(n1870), .A1(n1908), .B0(n1930), .B1(n2048), .Y(n1927)
);
OAI22X1TS U1490 ( .A0(n1846), .A1(n1840), .B0(n1852), .B1(n1842), .Y(n1822)
);
ADDHX1TS U1491 ( .A(n1835), .B(n1834), .CO(DP_OP_158J23_127_356_n486), .S(
DP_OP_158J23_127_356_n487) );
NOR2X1TS U1492 ( .A(n1841), .B(n1839), .Y(n1835) );
NOR2X1TS U1493 ( .A(n1841), .B(n1842), .Y(n1837) );
NOR2X1TS U1494 ( .A(n1693), .B(n496), .Y(n1681) );
INVX2TS U1495 ( .A(Op_MY[11]), .Y(n2330) );
OAI21X1TS U1496 ( .A0(n3229), .A1(n3415), .B0(n3094), .Y(n3185) );
INVX6TS U1497 ( .A(n583), .Y(n3378) );
INVX6TS U1498 ( .A(n417), .Y(n3368) );
NOR2X1TS U1499 ( .A(n1841), .B(n1845), .Y(n1729) );
ADDFHX2TS U1500 ( .A(n1684), .B(n1683), .CI(n1682), .CO(
DP_OP_158J23_127_356_n191), .S(n1534) );
NOR2X1TS U1501 ( .A(n1781), .B(n1786), .Y(n1738) );
NOR2X2TS U1502 ( .A(n2122), .B(n2121), .Y(n2130) );
ADDFHX2TS U1503 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]),
.B(n707), .CI(n706), .CO(n708), .S(n699) );
OAI21X2TS U1504 ( .A0(n2165), .A1(n2162), .B0(n2166), .Y(n2066) );
NAND2X4TS U1505 ( .A(n964), .B(n963), .Y(n966) );
NAND2X1TS U1506 ( .A(n991), .B(n998), .Y(n992) );
BUFX12TS U1507 ( .A(n864), .Y(n942) );
CLKBUFX2TS U1508 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]),
.Y(n951) );
ADDFHX2TS U1509 ( .A(n2229), .B(n2228), .CI(n2227), .CO(
DP_OP_156J23_125_3370_n250), .S(n1066) );
NAND2X1TS U1510 ( .A(n1817), .B(n1816), .Y(n1818) );
INVX2TS U1511 ( .A(n1815), .Y(n1817) );
NAND2X1TS U1512 ( .A(n1705), .B(n1715), .Y(n1706) );
INVX2TS U1513 ( .A(n1717), .Y(n1705) );
NOR2X2TS U1514 ( .A(n489), .B(Op_MY[14]), .Y(n2275) );
INVX4TS U1515 ( .A(n896), .Y(n906) );
INVX2TS U1516 ( .A(n1132), .Y(n933) );
CLKINVX6TS U1517 ( .A(n1079), .Y(n1284) );
OAI21X1TS U1518 ( .A0(n1558), .A1(n1563), .B0(n1565), .Y(n1561) );
INVX2TS U1519 ( .A(n2835), .Y(n489) );
NAND2X1TS U1520 ( .A(n731), .B(n729), .Y(n727) );
ADDFHX2TS U1521 ( .A(n1957), .B(n1956), .CI(n1955), .CO(n1970), .S(n1950) );
XNOR2X1TS U1522 ( .A(n1952), .B(n1940), .Y(n1941) );
XNOR2X1TS U1523 ( .A(n1952), .B(n606), .Y(n1909) );
XNOR2X1TS U1524 ( .A(n1944), .B(n1884), .Y(n1907) );
XNOR2X1TS U1525 ( .A(n1884), .B(n1922), .Y(n1892) );
INVX2TS U1526 ( .A(n1806), .Y(n1839) );
INVX2TS U1527 ( .A(n1805), .Y(n1840) );
INVX2TS U1528 ( .A(n1713), .Y(n1843) );
INVX2TS U1529 ( .A(n1709), .Y(n1845) );
INVX2TS U1530 ( .A(n1723), .Y(n1847) );
NAND2X1TS U1531 ( .A(n1710), .B(n1716), .Y(n1711) );
INVX4TS U1532 ( .A(n442), .Y(n490) );
NAND2X1TS U1533 ( .A(n1406), .B(n1404), .Y(n1364) );
AOI21X1TS U1534 ( .A0(n3097), .A1(n3185), .B0(n3096), .Y(n3167) );
INVX2TS U1535 ( .A(n1952), .Y(n1978) );
NOR2X1TS U1536 ( .A(n2022), .B(n2027), .Y(n1917) );
OAI22X1TS U1537 ( .A0(n1908), .A1(n1893), .B0(n1892), .B1(n2048), .Y(n1894)
);
XNOR2X1TS U1538 ( .A(n1884), .B(n1882), .Y(n1883) );
OAI22X1TS U1539 ( .A0(n505), .A1(n2330), .B0(n527), .B1(n2833), .Y(n1753) );
NOR2X1TS U1540 ( .A(n1566), .B(n1570), .Y(n1503) );
NAND2X1TS U1541 ( .A(n436), .B(n1512), .Y(n1513) );
OAI21X2TS U1542 ( .A0(n1750), .A1(n1776), .B0(n1749), .Y(n1762) );
NOR2X1TS U1543 ( .A(n2390), .B(n1431), .Y(n1432) );
INVX2TS U1544 ( .A(n3185), .Y(n3207) );
INVX2TS U1545 ( .A(n3167), .Y(n3180) );
NAND4XLTS U1546 ( .A(n3383), .B(n3382), .C(n3381), .D(n451), .Y(n3384) );
NAND4XLTS U1547 ( .A(n3376), .B(n3375), .C(n3374), .D(n3373), .Y(n3385) );
MX2X1TS U1548 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
OAI21XLTS U1549 ( .A0(n3405), .A1(n2655), .B0(n2654), .Y(n2656) );
NOR2X4TS U1550 ( .A(n1961), .B(n1960), .Y(n2012) );
INVX2TS U1551 ( .A(n2052), .Y(n2046) );
OAI22X1TS U1552 ( .A0(n1908), .A1(n2049), .B0(n1883), .B1(n2048), .Y(n2051)
);
NAND2X1TS U1553 ( .A(n2051), .B(n2050), .Y(n2052) );
INVX2TS U1554 ( .A(n1762), .Y(n1751) );
NAND2X2TS U1555 ( .A(DP_OP_158J23_127_356_n464), .B(
DP_OP_158J23_127_356_n460), .Y(n1776) );
INVX2TS U1556 ( .A(n1796), .Y(n1736) );
NOR2X1TS U1557 ( .A(n1841), .B(n1851), .Y(n1854) );
NOR2X1TS U1558 ( .A(n1841), .B(n1849), .Y(n1853) );
AOI21X2TS U1559 ( .A0(n2784), .A1(n554), .B0(n2606), .Y(n2781) );
INVX2TS U1560 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(
n2059) );
INVX2TS U1561 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(
n1051) );
OR2X1TS U1562 ( .A(n2059), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .Y(n2062) );
INVX2TS U1563 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]),
.Y(n988) );
NOR2X4TS U1564 ( .A(n990), .B(n989), .Y(n1000) );
NOR2X1TS U1565 ( .A(n997), .B(n996), .Y(n986) );
INVX2TS U1566 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]),
.Y(n956) );
INVX2TS U1567 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
n957) );
NAND2X2TS U1568 ( .A(n941), .B(n940), .Y(n943) );
INVX2TS U1569 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(
n2077) );
INVX2TS U1570 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(
n2099) );
NOR2X2TS U1571 ( .A(n2083), .B(n2082), .Y(n2091) );
INVX2TS U1572 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(
n2109) );
NOR2X1TS U1573 ( .A(n2137), .B(n2136), .Y(n2192) );
INVX2TS U1574 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]),
.Y(n946) );
OR2X2TS U1575 ( .A(n666), .B(n3367), .Y(n667) );
NOR2X2TS U1576 ( .A(n2058), .B(n2057), .Y(n2182) );
OR2X2TS U1577 ( .A(n1051), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(n2056) );
NAND2X2TS U1578 ( .A(n1051), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(n2053) );
INVX2TS U1579 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]),
.Y(n2055) );
NAND2X1TS U1580 ( .A(n1009), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(n1013) );
NOR2X1TS U1581 ( .A(n1009), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(n1014) );
AND2X2TS U1582 ( .A(n981), .B(n1161), .Y(n441) );
AOI21X1TS U1583 ( .A0(n2156), .A1(n2155), .B0(n2154), .Y(n2161) );
NAND2X1TS U1584 ( .A(n2159), .B(n2158), .Y(n2160) );
NOR2X2TS U1585 ( .A(n2079), .B(n2078), .Y(n2187) );
NAND2X1TS U1586 ( .A(n2083), .B(n2082), .Y(n2090) );
NAND2X2TS U1587 ( .A(n688), .B(n1027), .Y(n770) );
INVX2TS U1588 ( .A(n775), .Y(n687) );
NAND2X1TS U1589 ( .A(n2137), .B(n2136), .Y(n2193) );
NOR2X1TS U1590 ( .A(n2128), .B(n2130), .Y(n2133) );
OAI21X2TS U1591 ( .A0(n2131), .A1(n2130), .B0(n2129), .Y(n2132) );
NAND2X1TS U1592 ( .A(n2140), .B(n2139), .Y(n2170) );
NOR2X1TS U1593 ( .A(n920), .B(n934), .Y(n923) );
OAI21X2TS U1594 ( .A0(n743), .A1(n741), .B0(n762), .Y(n744) );
NOR2X2TS U1595 ( .A(n742), .B(n741), .Y(n745) );
INVX2TS U1596 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(
n723) );
INVX2TS U1597 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(
n724) );
INVX2TS U1598 ( .A(n672), .Y(n1527) );
INVX2TS U1599 ( .A(n624), .Y(n631) );
NOR2X1TS U1600 ( .A(n1811), .B(n1815), .Y(n1740) );
INVX2TS U1601 ( .A(n1809), .Y(n1812) );
OAI21X2TS U1602 ( .A0(n1717), .A1(n1716), .B0(n1715), .Y(n1809) );
NOR2X2TS U1603 ( .A(n1717), .B(n1714), .Y(n1807) );
NAND2X2TS U1604 ( .A(n477), .B(n461), .Y(n1810) );
NOR2X2TS U1605 ( .A(n3380), .B(n3372), .Y(n1717) );
INVX2TS U1606 ( .A(n1716), .Y(n1704) );
ADDFX2TS U1607 ( .A(n3351), .B(n3353), .CI(n678), .CO(n1557), .S(n680) );
NOR2X2TS U1608 ( .A(n1545), .B(n1542), .Y(n1548) );
OAI21X2TS U1609 ( .A0(n1545), .A1(n1544), .B0(n1543), .Y(n1546) );
INVX2TS U1610 ( .A(n1866), .Y(n1653) );
NAND2X2TS U1611 ( .A(n654), .B(n1864), .Y(n1544) );
INVX2TS U1612 ( .A(n1505), .Y(n629) );
NAND2X2TS U1613 ( .A(n1861), .B(n628), .Y(n1505) );
AOI21X2TS U1614 ( .A0(n534), .A1(n609), .B0(n608), .Y(n624) );
INVX2TS U1615 ( .A(n607), .Y(n608) );
NAND2X2TS U1616 ( .A(n3368), .B(n3378), .Y(n632) );
INVX2TS U1617 ( .A(n625), .Y(n630) );
INVX2TS U1618 ( .A(Sgf_operation_Result[1]), .Y(n1029) );
NAND2X1TS U1619 ( .A(n2167), .B(n2166), .Y(n2168) );
OAI21X2TS U1620 ( .A0(n746), .A1(n762), .B0(n747), .Y(n715) );
ADDFX2TS U1621 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]),
.B(n1054), .CI(n1053), .CO(n2228), .S(n1049) );
INVX2TS U1622 ( .A(n2198), .Y(DP_OP_156J23_125_3370_n300) );
INVX2TS U1623 ( .A(n2221), .Y(DP_OP_156J23_125_3370_n276) );
XNOR2X1TS U1624 ( .A(n2149), .B(n2148), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
NAND2X4TS U1625 ( .A(n686), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .Y(n775) );
NAND2X1TS U1626 ( .A(n819), .B(n825), .Y(n820) );
NAND2X1TS U1627 ( .A(n782), .B(n755), .Y(n783) );
INVX2TS U1628 ( .A(n1022), .Y(n780) );
AND2X2TS U1629 ( .A(n757), .B(n756), .Y(n758) );
CLKAND2X2TS U1630 ( .A(n763), .B(n762), .Y(n764) );
OAI21X1TS U1631 ( .A0(n1566), .A1(n1565), .B0(n1564), .Y(n1567) );
NOR2X1TS U1632 ( .A(n1563), .B(n1566), .Y(n1568) );
NAND2X1TS U1633 ( .A(n835), .B(n839), .Y(n836) );
NAND2X1TS U1634 ( .A(n753), .B(n752), .Y(n754) );
INVX2TS U1635 ( .A(n1920), .Y(n1923) );
INVX2TS U1636 ( .A(n1922), .Y(n1945) );
INVX2TS U1637 ( .A(n1882), .Y(n1921) );
XNOR2X1TS U1638 ( .A(n530), .B(n1920), .Y(n1867) );
AOI21X2TS U1639 ( .A0(n1740), .A1(n1809), .B0(n1739), .Y(n1743) );
OAI21X1TS U1640 ( .A0(n1815), .A1(n1810), .B0(n1816), .Y(n1739) );
NOR2X2TS U1641 ( .A(Op_MY[16]), .B(n3355), .Y(n1563) );
AOI21X2TS U1642 ( .A0(n641), .A1(n672), .B0(n640), .Y(n1558) );
NOR2X1TS U1643 ( .A(n1523), .B(n673), .Y(n641) );
NAND2X2TS U1644 ( .A(Op_MY[16]), .B(n3355), .Y(n1565) );
INVX2TS U1645 ( .A(n1714), .Y(n1710) );
ADDHX1TS U1646 ( .A(n1922), .B(n680), .CO(n681), .S(n679) );
ADDHX1TS U1647 ( .A(n1665), .B(n1664), .CO(DP_OP_158J23_127_356_n150), .S(
DP_OP_158J23_127_356_n151) );
ADDHX1TS U1648 ( .A(Op_MX[19]), .B(Op_MX[7]), .CO(n627), .S(n620) );
ADDFHX2TS U1649 ( .A(Op_MX[8]), .B(n627), .CI(n3380), .CO(n635), .S(n622) );
AOI21X2TS U1650 ( .A0(n2269), .A1(n599), .B0(n598), .Y(n2315) );
INVX2TS U1651 ( .A(n876), .Y(n902) );
INVX2TS U1652 ( .A(n901), .Y(n869) );
INVX2TS U1653 ( .A(n3291), .Y(DP_OP_156J23_125_3370_n280) );
INVX2TS U1654 ( .A(n2199), .Y(DP_OP_156J23_125_3370_n304) );
INVX2TS U1655 ( .A(n3306), .Y(DP_OP_156J23_125_3370_n278) );
NAND2X4TS U1656 ( .A(n852), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .Y(n891) );
INVX2TS U1657 ( .A(n886), .Y(n888) );
INVX2TS U1658 ( .A(n905), .Y(n897) );
OAI21X1TS U1659 ( .A0(n1166), .A1(n1165), .B0(n1164), .Y(n1167) );
NAND2X2TS U1660 ( .A(n977), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n1170) );
NAND2X1TS U1661 ( .A(n1184), .B(n1182), .Y(n995) );
NOR2X4TS U1662 ( .A(n980), .B(n979), .Y(n1161) );
NOR2X1TS U1663 ( .A(n1035), .B(n1034), .Y(n1156) );
AOI21X2TS U1664 ( .A0(n1200), .A1(n1184), .B0(n1183), .Y(n1189) );
OAI21X2TS U1665 ( .A0(n1197), .A1(n1193), .B0(n1194), .Y(n1192) );
NAND2X1TS U1666 ( .A(n396), .B(n775), .Y(n776) );
NAND2X4TS U1667 ( .A(n837), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n1394) );
NOR2X4TS U1668 ( .A(n778), .B(n777), .Y(n1060) );
NAND2X2TS U1669 ( .A(n779), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n1022) );
OAI21X2TS U1670 ( .A0(n1060), .A1(n1063), .B0(n1061), .Y(n1024) );
OR2X4TS U1671 ( .A(n794), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n1110) );
INVX2TS U1672 ( .A(n1100), .Y(n1111) );
NOR2X2TS U1673 ( .A(DP_OP_156J23_125_3370_n203), .B(n1338), .Y(n1352) );
INVX2TS U1674 ( .A(n1353), .Y(n1336) );
NOR2X6TS U1675 ( .A(n800), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n1345) );
NAND2X4TS U1676 ( .A(n799), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n1342) );
INVX2TS U1677 ( .A(n1325), .Y(n1344) );
NAND2X2TS U1678 ( .A(n800), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n1346) );
OR2X2TS U1679 ( .A(DP_OP_156J23_125_3370_n249), .B(n1067), .Y(n1225) );
INVX2TS U1680 ( .A(n1375), .Y(n1395) );
NAND2X4TS U1681 ( .A(n845), .B(n848), .Y(n1371) );
NAND2X1TS U1682 ( .A(n2260), .B(n2324), .Y(n2261) );
INVX2TS U1683 ( .A(n392), .Y(n479) );
INVX2TS U1684 ( .A(n392), .Y(n478) );
XNOR2X1TS U1685 ( .A(n529), .B(n1882), .Y(n1877) );
INVX2TS U1686 ( .A(n426), .Y(n3356) );
CMPR42X1TS U1687 ( .A(DP_OP_158J23_127_356_n529), .B(
DP_OP_158J23_127_356_n499), .C(DP_OP_158J23_127_356_n523), .D(
DP_OP_158J23_127_356_n517), .ICI(DP_OP_158J23_127_356_n481), .S(
DP_OP_158J23_127_356_n475), .ICO(DP_OP_158J23_127_356_n473), .CO(
DP_OP_158J23_127_356_n474) );
INVX2TS U1688 ( .A(n1724), .Y(n1842) );
INVX2TS U1689 ( .A(n1563), .Y(n1500) );
NOR2X2TS U1690 ( .A(n413), .B(Op_MY[6]), .Y(n1570) );
INVX2TS U1691 ( .A(n1565), .Y(n1502) );
INVX4TS U1692 ( .A(n442), .Y(n491) );
INVX4TS U1693 ( .A(n643), .Y(n1690) );
INVX2TS U1694 ( .A(n681), .Y(n1692) );
INVX2TS U1695 ( .A(n1674), .Y(n1694) );
INVX2TS U1696 ( .A(n1520), .Y(n621) );
NAND2X1TS U1697 ( .A(n2279), .B(n2278), .Y(n2280) );
INVX2TS U1698 ( .A(n437), .Y(n480) );
NAND2X1TS U1699 ( .A(n2234), .B(n2233), .Y(n2236) );
INVX2TS U1700 ( .A(n2216), .Y(n900) );
NAND2X1TS U1701 ( .A(n909), .B(n908), .Y(n910) );
NAND2X1TS U1702 ( .A(n873), .B(n877), .Y(n874) );
INVX2TS U1703 ( .A(n878), .Y(n873) );
NAND2X1TS U1704 ( .A(n883), .B(n936), .Y(n884) );
NAND2X1TS U1705 ( .A(n1031), .B(n1030), .Y(n1147) );
OR2X2TS U1706 ( .A(DP_OP_156J23_125_3370_n240), .B(
DP_OP_156J23_125_3370_n242), .Y(n1239) );
NAND2X1TS U1707 ( .A(n737), .B(n826), .Y(n738) );
CLKBUFX2TS U1708 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]),
.Y(n806) );
NAND2X2TS U1709 ( .A(n899), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n2216) );
OR2X4TS U1710 ( .A(n899), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n2217) );
NAND2X1TS U1711 ( .A(n2245), .B(n2251), .Y(n2246) );
INVX2TS U1712 ( .A(n1984), .Y(n1971) );
OAI22X1TS U1713 ( .A0(n1909), .A1(n1908), .B0(n1870), .B1(n2048), .Y(n1875)
);
OAI21X2TS U1714 ( .A0(n2035), .A1(n2032), .B0(n2033), .Y(n2021) );
OAI22X1TS U1715 ( .A0(n1909), .A1(n2048), .B0(n1908), .B1(n1907), .Y(n1910)
);
OAI22X1TS U1716 ( .A0(n1908), .A1(n1892), .B0(n1907), .B1(n2048), .Y(n1896)
);
OAI22X1TS U1717 ( .A0(n1943), .A1(n1890), .B0(n1879), .B1(n1942), .Y(n1897)
);
OAI22X1TS U1718 ( .A0(n1908), .A1(n1883), .B0(n1893), .B1(n2048), .Y(n1887)
);
CMPR42X1TS U1719 ( .A(DP_OP_158J23_127_356_n508), .B(
DP_OP_158J23_127_356_n502), .C(DP_OP_158J23_127_356_n496), .D(
DP_OP_158J23_127_356_n461), .ICI(DP_OP_158J23_127_356_n458), .S(
DP_OP_158J23_127_356_n457), .ICO(DP_OP_158J23_127_356_n455), .CO(
DP_OP_158J23_127_356_n456) );
CMPR42X1TS U1720 ( .A(DP_OP_158J23_127_356_n524), .B(
DP_OP_158J23_127_356_n518), .C(DP_OP_158J23_127_356_n486), .D(
DP_OP_158J23_127_356_n483), .ICI(DP_OP_158J23_127_356_n480), .S(
DP_OP_158J23_127_356_n478), .ICO(DP_OP_158J23_127_356_n476), .CO(
DP_OP_158J23_127_356_n477) );
OAI22X1TS U1721 ( .A0(n1848), .A1(n1849), .B0(n1844), .B1(n1847), .Y(n1726)
);
INVX2TS U1722 ( .A(n1722), .Y(n1849) );
NOR2X1TS U1723 ( .A(n495), .B(n1511), .Y(DP_OP_158J23_127_356_n263) );
ADDHX1TS U1724 ( .A(n1722), .B(n1509), .CO(n1510), .S(n1504) );
NAND2X4TS U1725 ( .A(n912), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n2203) );
OR2X4TS U1726 ( .A(n912), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n2204) );
NAND2X1TS U1727 ( .A(n893), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .Y(n1141) );
OR2X1TS U1728 ( .A(n893), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .Y(n1142) );
NOR2X4TS U1729 ( .A(n918), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n1136) );
NAND2X4TS U1730 ( .A(n917), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(n2208) );
INVX2TS U1731 ( .A(n1135), .Y(n2211) );
NAND2X2TS U1732 ( .A(n918), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n1137) );
INVX2TS U1733 ( .A(n1583), .Y(n1586) );
OAI21X1TS U1734 ( .A0(n1603), .A1(n1594), .B0(n1595), .Y(n1577) );
NOR2X2TS U1735 ( .A(n1585), .B(n1594), .Y(n1578) );
AND2X2TS U1736 ( .A(n1046), .B(n1058), .Y(n3303) );
NAND2X1TS U1737 ( .A(n2217), .B(n2216), .Y(n2219) );
NOR2X4TS U1738 ( .A(n2342), .B(n2352), .Y(n2358) );
NAND2X2TS U1739 ( .A(n2389), .B(n1420), .Y(n2393) );
NAND2X2TS U1740 ( .A(DP_OP_158J23_127_356_n129), .B(
DP_OP_158J23_127_356_n125), .Y(n1608) );
INVX2TS U1741 ( .A(n2827), .Y(n3340) );
NAND2X2TS U1742 ( .A(n1599), .B(n1604), .Y(n1593) );
INVX2TS U1743 ( .A(n1990), .Y(n1981) );
NAND2X1TS U1744 ( .A(n2004), .B(n1967), .Y(n1969) );
AOI21X1TS U1745 ( .A0(n2003), .A1(n1967), .B0(n1966), .Y(n1968) );
NOR2X1TS U1746 ( .A(n2005), .B(n1998), .Y(n1967) );
NAND2X1TS U1747 ( .A(n1401), .B(n1400), .Y(n1402) );
NOR2X1TS U1748 ( .A(n1477), .B(n448), .Y(n1441) );
NOR2X2TS U1749 ( .A(n1965), .B(n1964), .Y(n1998) );
INVX2TS U1750 ( .A(n2004), .Y(n1993) );
NAND2X1TS U1751 ( .A(n1965), .B(n1964), .Y(n1999) );
INVX2TS U1752 ( .A(n2017), .Y(n2011) );
NOR2X2TS U1753 ( .A(n1913), .B(n1912), .Y(n2027) );
INVX2TS U1754 ( .A(n2021), .Y(n2031) );
NOR2X1TS U1755 ( .A(n1911), .B(n1910), .Y(n2032) );
INVX2TS U1756 ( .A(n2037), .Y(n1903) );
NAND2X1TS U1757 ( .A(n1902), .B(n1901), .Y(n2037) );
OAI21X1TS U1758 ( .A0(n2044), .A1(n2040), .B0(n2041), .Y(n2039) );
NAND2X1TS U1759 ( .A(n1887), .B(n1886), .Y(n2045) );
INVX2TS U1760 ( .A(n1773), .Y(n1765) );
INVX2TS U1761 ( .A(n1776), .Y(n1766) );
NAND2X1TS U1762 ( .A(n1777), .B(n402), .Y(n1768) );
INVX2TS U1763 ( .A(n1772), .Y(n1777) );
NOR2X2TS U1764 ( .A(DP_OP_158J23_127_356_n465), .B(DP_OP_158J23_127_356_n471), .Y(n1781) );
NOR2X2TS U1765 ( .A(DP_OP_158J23_127_356_n472), .B(DP_OP_158J23_127_356_n477), .Y(n1786) );
INVX2TS U1766 ( .A(n1780), .Y(n1790) );
NOR2X1TS U1767 ( .A(DP_OP_158J23_127_356_n478), .B(DP_OP_158J23_127_356_n484), .Y(n1791) );
NAND2X1TS U1768 ( .A(DP_OP_158J23_127_356_n485), .B(n1735), .Y(n1796) );
INVX2TS U1769 ( .A(n1798), .Y(n1734) );
NAND2X1TS U1770 ( .A(n1733), .B(n1732), .Y(n1798) );
OAI21X1TS U1771 ( .A0(n1801), .A1(n1855), .B0(n1802), .Y(n1799) );
NOR2X1TS U1772 ( .A(n1594), .B(n1586), .Y(n1588) );
INVX2TS U1773 ( .A(n1616), .Y(n1625) );
INVX2TS U1774 ( .A(n1640), .Y(n1537) );
NAND2X1TS U1775 ( .A(DP_OP_158J23_127_356_n181), .B(
DP_OP_158J23_127_356_n187), .Y(n1640) );
INVX2TS U1776 ( .A(n1648), .Y(n1535) );
NAND2X1TS U1777 ( .A(n1534), .B(n1533), .Y(n1648) );
INVX2TS U1778 ( .A(n443), .Y(n496) );
ADDHX1TS U1779 ( .A(n1532), .B(n1531), .CO(n1682), .S(n1651) );
NOR2X1TS U1780 ( .A(n1697), .B(n497), .Y(n1532) );
OA21XLTS U1781 ( .A0(n2320), .A1(n2876), .B0(n2862), .Y(n2873) );
NAND2X2TS U1782 ( .A(n2204), .B(n2203), .Y(n2205) );
INVX2TS U1783 ( .A(n2827), .Y(n3341) );
MX2X1TS U1784 ( .A(Data_MY[1]), .B(n411), .S0(n2831), .Y(n313) );
MX2X1TS U1785 ( .A(Data_MY[13]), .B(n412), .S0(n3341), .Y(n325) );
MX2X1TS U1786 ( .A(Data_MY[9]), .B(n2834), .S0(n492), .Y(n321) );
MX2X1TS U1787 ( .A(Data_MY[21]), .B(n513), .S0(n492), .Y(n333) );
MX2X1TS U1788 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n3341), .Y(n352) );
MX2X1TS U1789 ( .A(Data_MY[8]), .B(n420), .S0(n2831), .Y(n320) );
MX2X1TS U1790 ( .A(Data_MX[13]), .B(n2832), .S0(n2836), .Y(n357) );
MX2X1TS U1791 ( .A(Data_MY[18]), .B(n413), .S0(n493), .Y(n330) );
MX2X1TS U1792 ( .A(Data_MX[9]), .B(n461), .S0(n3341), .Y(n353) );
MX2X1TS U1793 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n2836), .Y(n365) );
MX2X1TS U1794 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n493), .Y(n314) );
NAND2X1TS U1795 ( .A(n1759), .B(n592), .Y(n1764) );
MX2X1TS U1796 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n2836), .Y(n360) );
MX2X1TS U1797 ( .A(Data_MY[11]), .B(n2833), .S0(n2831), .Y(n323) );
XNOR2X1TS U1798 ( .A(n2294), .B(n2293), .Y(n2295) );
CLKMX2X2TS U1799 ( .A(P_Sgf[34]), .B(n2372), .S0(n3345), .Y(n249) );
XOR2X2TS U1800 ( .A(n2371), .B(n2370), .Y(n2372) );
CLKMX2X2TS U1801 ( .A(P_Sgf[36]), .B(n2387), .S0(n2665), .Y(n251) );
AND2X2TS U1802 ( .A(n2391), .B(n2390), .Y(n456) );
MX2X1TS U1803 ( .A(n3220), .B(Add_result[3]), .S0(n3241), .Y(n303) );
INVX2TS U1804 ( .A(n3229), .Y(n3218) );
MX2X1TS U1805 ( .A(n3208), .B(Add_result[4]), .S0(n3241), .Y(n302) );
MX2X1TS U1806 ( .A(n3198), .B(Add_result[5]), .S0(n3241), .Y(n301) );
MX2X1TS U1807 ( .A(n3193), .B(Add_result[6]), .S0(n3241), .Y(n300) );
MX2X1TS U1808 ( .A(n3181), .B(Add_result[8]), .S0(n3262), .Y(n298) );
MX2X1TS U1809 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n3390), .Y(n369) );
MX2X1TS U1810 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n3390), .Y(n373) );
MX2X1TS U1811 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n2826), .Y(n329) );
MX2X1TS U1812 ( .A(Data_MX[14]), .B(n391), .S0(n492), .Y(n358) );
MX2X1TS U1813 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n2826), .Y(n350) );
MX2X1TS U1814 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n2831), .Y(n361) );
MX2X1TS U1815 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n492), .Y(n312) );
MX2X1TS U1816 ( .A(Data_MX[18]), .B(n2829), .S0(n492), .Y(n362) );
MX2X1TS U1817 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n3390), .Y(n326) );
MX2X1TS U1818 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n492), .Y(n315) );
MX2X1TS U1819 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n3340), .Y(n324) );
MX2X1TS U1820 ( .A(Data_MX[0]), .B(n3369), .S0(n2831), .Y(n344) );
NAND4XLTS U1821 ( .A(n3366), .B(n3365), .C(n3364), .D(n3363), .Y(n3386) );
NAND4XLTS U1822 ( .A(n3361), .B(n3360), .C(n3359), .D(n3358), .Y(n3387) );
MX2X1TS U1823 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n3341), .Y(n346) );
NOR2XLTS U1824 ( .A(n2449), .B(underflow_flag), .Y(n2450) );
MX2X1TS U1825 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n493), .Y(n318) );
MX2X1TS U1826 ( .A(Data_MY[7]), .B(n3412), .S0(n493), .Y(n319) );
CLKAND2X2TS U1827 ( .A(n2867), .B(n2649), .Y(n3419) );
XNOR2X1TS U1828 ( .A(n1992), .B(n1991), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12)
);
NAND2X1TS U1829 ( .A(n588), .B(n1990), .Y(n1991) );
NAND2X1TS U1830 ( .A(n544), .B(n1987), .Y(n1988) );
NAND2X1TS U1831 ( .A(n1986), .B(n589), .Y(n1987) );
NAND4XLTS U1832 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n3347) );
CLKAND2X2TS U1833 ( .A(n3060), .B(n2652), .Y(n3420) );
CLKAND2X2TS U1834 ( .A(n2939), .B(n2656), .Y(n3421) );
CLKAND2X2TS U1835 ( .A(n2660), .B(n2659), .Y(n3424) );
OR2X1TS U1836 ( .A(n2658), .B(n2657), .Y(n2660) );
XOR2X1TS U1837 ( .A(n2002), .B(n2001), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11)
);
NAND2X1TS U1838 ( .A(n2000), .B(n1999), .Y(n2001) );
AOI21X1TS U1839 ( .A0(n1997), .A1(n2020), .B0(n1996), .Y(n2002) );
INVX2TS U1840 ( .A(n1998), .Y(n2000) );
XOR2X1TS U1841 ( .A(n2009), .B(n2008), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10)
);
AOI21X1TS U1842 ( .A0(n2020), .A1(n2004), .B0(n2003), .Y(n2009) );
INVX2TS U1843 ( .A(n2005), .Y(n2007) );
XOR2X1TS U1844 ( .A(n2016), .B(n2015), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9)
);
NAND2X1TS U1845 ( .A(n2014), .B(n2013), .Y(n2015) );
AOI21X1TS U1846 ( .A0(n2020), .A1(n2018), .B0(n2011), .Y(n2016) );
INVX2TS U1847 ( .A(n2012), .Y(n2014) );
XNOR2X1TS U1848 ( .A(n2020), .B(n2019), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8)
);
NAND2X1TS U1849 ( .A(n2018), .B(n2017), .Y(n2019) );
XNOR2X1TS U1850 ( .A(n2026), .B(n2025), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7)
);
NAND2X1TS U1851 ( .A(n2024), .B(n2023), .Y(n2025) );
INVX2TS U1852 ( .A(n2022), .Y(n2024) );
XOR2X1TS U1853 ( .A(n2031), .B(n2030), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6)
);
NAND2X1TS U1854 ( .A(n2029), .B(n2028), .Y(n2030) );
INVX2TS U1855 ( .A(n2027), .Y(n2029) );
XOR2X1TS U1856 ( .A(n2036), .B(n2035), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5)
);
NAND2X1TS U1857 ( .A(n2034), .B(n2033), .Y(n2036) );
INVX2TS U1858 ( .A(n2032), .Y(n2034) );
XNOR2X1TS U1859 ( .A(n2039), .B(n2038), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4)
);
NAND2X1TS U1860 ( .A(n563), .B(n2037), .Y(n2038) );
XOR2X1TS U1861 ( .A(n2044), .B(n2043), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3)
);
NAND2X1TS U1862 ( .A(n2042), .B(n2041), .Y(n2043) );
XNOR2X1TS U1863 ( .A(n2047), .B(n2046), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2)
);
NAND2X1TS U1864 ( .A(n581), .B(n2045), .Y(n2047) );
CLKAND2X2TS U1865 ( .A(n564), .B(n2052), .Y(n565) );
NOR2BX1TS U1866 ( .AN(n2049), .B(n2048), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0)
);
NAND2X1TS U1867 ( .A(n592), .B(n1760), .Y(n1757) );
INVX2TS U1868 ( .A(n1759), .Y(n1752) );
XNOR2X1TS U1869 ( .A(n1771), .B(n1770), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9)
);
NAND2X1TS U1870 ( .A(n591), .B(n1769), .Y(n1770) );
AOI21X1TS U1871 ( .A0(n1766), .A1(n402), .B0(n1765), .Y(n1767) );
XNOR2X1TS U1872 ( .A(n1775), .B(n1774), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8)
);
NAND2X1TS U1873 ( .A(n402), .B(n1773), .Y(n1774) );
XOR2X1TS U1874 ( .A(n1779), .B(n1778), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7)
);
NAND2X1TS U1875 ( .A(n1777), .B(n1776), .Y(n1778) );
XNOR2X1TS U1876 ( .A(n1785), .B(n1784), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6)
);
NAND2X1TS U1877 ( .A(n1783), .B(n1782), .Y(n1784) );
INVX2TS U1878 ( .A(n1781), .Y(n1783) );
XOR2X1TS U1879 ( .A(n1790), .B(n1789), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5)
);
NAND2X1TS U1880 ( .A(n1788), .B(n1787), .Y(n1789) );
INVX2TS U1881 ( .A(n1786), .Y(n1788) );
XOR2X1TS U1882 ( .A(n1795), .B(n1794), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4)
);
NAND2X1TS U1883 ( .A(n1793), .B(n1792), .Y(n1795) );
INVX2TS U1884 ( .A(n1791), .Y(n1793) );
XNOR2X1TS U1885 ( .A(n1797), .B(n537), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3)
);
NAND2X1TS U1886 ( .A(n570), .B(n1796), .Y(n1797) );
XNOR2X1TS U1887 ( .A(n1800), .B(n1799), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2)
);
NAND2X1TS U1888 ( .A(n569), .B(n1798), .Y(n1800) );
XOR2X1TS U1889 ( .A(n1804), .B(n1855), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1)
);
NAND2X1TS U1890 ( .A(n1803), .B(n1802), .Y(n1804) );
NAND2X1TS U1891 ( .A(n1613), .B(n1612), .Y(n1614) );
INVX2TS U1892 ( .A(n1611), .Y(n1613) );
XNOR2X1TS U1893 ( .A(n1621), .B(n1620), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9)
);
NAND2X1TS U1894 ( .A(n1619), .B(n1618), .Y(n1620) );
INVX2TS U1895 ( .A(n1617), .Y(n1619) );
XOR2X1TS U1896 ( .A(n1626), .B(n1625), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8)
);
NAND2X1TS U1897 ( .A(n1624), .B(n1623), .Y(n1626) );
INVX2TS U1898 ( .A(n1622), .Y(n1624) );
XOR2X1TS U1899 ( .A(n1631), .B(n1630), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7)
);
NAND2X1TS U1900 ( .A(n1629), .B(n1628), .Y(n1631) );
INVX2TS U1901 ( .A(n1627), .Y(n1629) );
XNOR2X1TS U1902 ( .A(n1634), .B(n1633), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6)
);
NAND2X1TS U1903 ( .A(n579), .B(n1632), .Y(n1634) );
XOR2X1TS U1904 ( .A(n1639), .B(n1638), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5)
);
NAND2X1TS U1905 ( .A(n1637), .B(n1636), .Y(n1639) );
INVX2TS U1906 ( .A(n1635), .Y(n1637) );
XNOR2X1TS U1907 ( .A(n1642), .B(n1641), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4)
);
NAND2X1TS U1908 ( .A(n427), .B(n1640), .Y(n1642) );
XOR2X1TS U1909 ( .A(n1647), .B(n1646), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3)
);
NAND2X1TS U1910 ( .A(n1645), .B(n1644), .Y(n1647) );
INVX2TS U1911 ( .A(n1643), .Y(n1645) );
XNOR2X1TS U1912 ( .A(n1650), .B(n1649), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2)
);
NAND2X1TS U1913 ( .A(n572), .B(n1648), .Y(n1650) );
CLKAND2X2TS U1914 ( .A(n2664), .B(n2663), .Y(n3425) );
OR2X1TS U1915 ( .A(n2662), .B(n2661), .Y(n2664) );
MX2X1TS U1916 ( .A(P_Sgf[0]), .B(Sgf_operation_Result[0]), .S0(n3224), .Y(
n215) );
MX2X1TS U1917 ( .A(P_Sgf[2]), .B(Sgf_operation_Result[2]), .S0(n3304), .Y(
n217) );
CLKAND2X2TS U1918 ( .A(n3300), .B(n3299), .Y(n3301) );
MX2X1TS U1919 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n493), .Y(n317) );
MX2X1TS U1920 ( .A(Data_MY[15]), .B(n2838), .S0(n3341), .Y(n327) );
MX2X1TS U1921 ( .A(Data_MY[16]), .B(n2837), .S0(n3341), .Y(n328) );
MX2X1TS U1922 ( .A(Data_MY[20]), .B(n404), .S0(n493), .Y(n332) );
MX2X1TS U1923 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n2836), .Y(n345) );
MX2X1TS U1924 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n3341), .Y(n354) );
MX2X1TS U1925 ( .A(Data_MX[11]), .B(n3367), .S0(n2826), .Y(n355) );
MX2X1TS U1926 ( .A(Data_MX[12]), .B(n419), .S0(n2836), .Y(n356) );
MX2X1TS U1927 ( .A(Data_MX[19]), .B(n2828), .S0(n2836), .Y(n363) );
MX2X1TS U1928 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n2836), .Y(n364) );
NAND2BXLTS U1929 ( .AN(zero_flag), .B(n506), .Y(n3268) );
NOR2X8TS U1930 ( .A(DP_OP_156J23_125_3370_n219), .B(
DP_OP_156J23_125_3370_n221), .Y(n1294) );
XOR2X4TS U1931 ( .A(n1298), .B(n1297), .Y(n1304) );
CLKINVX1TS U1932 ( .A(DP_OP_156J23_125_3370_n293), .Y(n1473) );
AOI21X1TS U1933 ( .A0(n418), .A1(n1814), .B0(n1813), .Y(n1819) );
NOR2X4TS U1934 ( .A(n468), .B(Op_MY[15]), .Y(n673) );
OAI21X2TS U1935 ( .A0(n2768), .A1(n2774), .B0(n2769), .Y(n2607) );
OAI21X4TS U1936 ( .A0(n1283), .A1(n1288), .B0(n1284), .Y(n410) );
NOR2X6TS U1937 ( .A(n1311), .B(n2199), .Y(n2362) );
OR2X4TS U1938 ( .A(n1277), .B(n1276), .Y(n540) );
NAND2X8TS U1939 ( .A(n983), .B(n982), .Y(n1200) );
INVX8TS U1940 ( .A(n2222), .Y(DP_OP_156J23_125_3370_n293) );
NOR2X6TS U1941 ( .A(DP_OP_156J23_125_3370_n231), .B(
DP_OP_156J23_125_3370_n233), .Y(n1122) );
OR2X6TS U1942 ( .A(n1091), .B(n1090), .Y(n1092) );
NOR2X4TS U1943 ( .A(n854), .B(n1029), .Y(n886) );
NOR2X4TS U1944 ( .A(n1617), .B(n1622), .Y(n1540) );
CLKXOR2X4TS U1945 ( .A(n1574), .B(n1573), .Y(n1976) );
INVX4TS U1946 ( .A(n580), .Y(n466) );
OAI21X4TS U1947 ( .A0(n2706), .A1(n2703), .B0(n2704), .Y(n2692) );
AOI21X2TS U1948 ( .A0(n2709), .A1(n590), .B0(n2577), .Y(n2706) );
OAI21X2TS U1949 ( .A0(n2711), .A1(n2714), .B0(n2712), .Y(n2709) );
OAI21X2TS U1950 ( .A0(n1126), .A1(n1122), .B0(n1123), .Y(n1121) );
CMPR42X2TS U1951 ( .A(DP_OP_159J23_128_5719_n178), .B(
DP_OP_159J23_128_5719_n171), .C(DP_OP_159J23_128_5719_n121), .D(
DP_OP_159J23_128_5719_n125), .ICI(DP_OP_159J23_128_5719_n120), .S(
DP_OP_159J23_128_5719_n117), .ICO(DP_OP_159J23_128_5719_n115), .CO(
DP_OP_159J23_128_5719_n116) );
CMPR42X2TS U1952 ( .A(DP_OP_159J23_128_5719_n172), .B(
DP_OP_159J23_128_5719_n186), .C(DP_OP_159J23_128_5719_n179), .D(
DP_OP_159J23_128_5719_n127), .ICI(DP_OP_159J23_128_5719_n126), .S(
DP_OP_159J23_128_5719_n123), .ICO(DP_OP_159J23_128_5719_n121), .CO(
DP_OP_159J23_128_5719_n122) );
ADDFHX4TS U1953 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]),
.B(n703), .CI(n702), .CO(n713), .S(n712) );
OAI21X1TS U1954 ( .A0(n1551), .A1(n1550), .B0(n1549), .Y(n1556) );
AO21X4TS U1955 ( .A0(n618), .A1(n651), .B0(n617), .Y(n418) );
XNOR2X2TS U1956 ( .A(n418), .B(n1711), .Y(n1712) );
AND2X4TS U1957 ( .A(n445), .B(n619), .Y(n421) );
CLKINVX6TS U1958 ( .A(n2402), .Y(n459) );
OR2X1TS U1959 ( .A(P_Sgf[9]), .B(P_Sgf[10]), .Y(n422) );
OR2X2TS U1960 ( .A(DP_OP_158J23_127_356_n181), .B(DP_OP_158J23_127_356_n187),
.Y(n427) );
OAI21X1TS U1961 ( .A0(n2315), .A1(n2311), .B0(n603), .Y(n434) );
INVX4TS U1962 ( .A(n597), .Y(n3362) );
OR2X4TS U1963 ( .A(n3370), .B(Op_MX[17]), .Y(n439) );
XOR2X1TS U1964 ( .A(n2315), .B(n2314), .Y(n440) );
CLKINVX6TS U1965 ( .A(n1703), .Y(n494) );
XNOR2X2TS U1966 ( .A(n418), .B(n1521), .Y(n443) );
OR2X4TS U1967 ( .A(n3369), .B(n419), .Y(n445) );
XNOR2X4TS U1968 ( .A(n1412), .B(n1411), .Y(n448) );
OR2X1TS U1969 ( .A(P_Sgf[14]), .B(P_Sgf[12]), .Y(n450) );
INVX2TS U1970 ( .A(n2376), .Y(n2377) );
OR2X1TS U1971 ( .A(n1854), .B(n1853), .Y(n452) );
NOR4X1TS U1972 ( .A(P_Sgf[8]), .B(P_Sgf[6]), .C(P_Sgf[7]), .D(P_Sgf[11]),
.Y(n453) );
INVX2TS U1973 ( .A(n2827), .Y(n2836) );
XOR2X4TS U1974 ( .A(n455), .B(n456), .Y(n2392) );
AO21X4TS U1975 ( .A0(n459), .A1(n2389), .B0(n2388), .Y(n455) );
AOI21X2TS U1976 ( .A0(n2094), .A1(n2093), .B0(n2092), .Y(n2095) );
XNOR2X2TS U1977 ( .A(n2113), .B(n2112), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
AOI2BB2X4TS U1978 ( .B0(n2395), .B1(n459), .A0N(n2394), .A1N(n399), .Y(n2397) );
AOI21X4TS U1979 ( .A0(n460), .A1(n2400), .B0(n2381), .Y(n2386) );
INVX2TS U1980 ( .A(n457), .Y(n458) );
NOR2X4TS U1981 ( .A(n2063), .B(n2062), .Y(n2163) );
NOR2X2TS U1982 ( .A(n2163), .B(n2165), .Y(n2067) );
ADDFX2TS U1983 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]),
.B(n2061), .CI(n2060), .CO(n2064), .S(n2063) );
AOI21X2TS U1984 ( .A0(n1152), .A1(n1133), .B0(n933), .Y(n954) );
NAND2X6TS U1985 ( .A(n803), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n1404) );
OAI21X2TS U1986 ( .A0(n660), .A1(n1542), .B0(n1544), .Y(n670) );
INVX4TS U1987 ( .A(n1547), .Y(n660) );
AOI21X2TS U1988 ( .A0(n1600), .A1(n533), .B0(n558), .Y(n1589) );
OAI22X2TS U1989 ( .A0(n1698), .A1(n1691), .B0(n401), .B1(n1690), .Y(n1669)
);
INVX2TS U1990 ( .A(n596), .Y(n465) );
INVX4TS U1991 ( .A(n425), .Y(n3372) );
INVX2TS U1992 ( .A(n393), .Y(n469) );
INVX2TS U1993 ( .A(n415), .Y(n2834) );
INVX2TS U1994 ( .A(n1712), .Y(n470) );
INVX2TS U1995 ( .A(n1860), .Y(n471) );
INVX2TS U1996 ( .A(n433), .Y(n473) );
INVX2TS U1997 ( .A(n434), .Y(n475) );
INVX2TS U1998 ( .A(n437), .Y(n481) );
INVX2TS U1999 ( .A(n440), .Y(n482) );
INVX2TS U2000 ( .A(n3110), .Y(n485) );
XNOR2X2TS U2001 ( .A(n459), .B(n2401), .Y(n2403) );
AOI21X2TS U2002 ( .A0(n1422), .A1(n460), .B0(n1421), .Y(n1426) );
INVX2TS U2003 ( .A(n2827), .Y(n492) );
INVX2TS U2004 ( .A(n2827), .Y(n493) );
INVX2TS U2005 ( .A(n2330), .Y(n2833) );
ADDHX1TS U2006 ( .A(n2297), .B(n2296), .CO(DP_OP_159J23_128_5719_n137), .S(
DP_OP_159J23_128_5719_n138) );
ADDHX1TS U2007 ( .A(n1881), .B(n1880), .CO(n1876), .S(n1904) );
ADDHX1TS U2008 ( .A(n1900), .B(n1899), .CO(n1901), .S(n1895) );
CLKXOR2X2TS U2009 ( .A(n2866), .B(n2865), .Y(n2890) );
OAI21X1TS U2010 ( .A0(n3000), .A1(n2999), .B0(n2537), .Y(mult_x_58_n14) );
NOR2X2TS U2011 ( .A(n2532), .B(n2531), .Y(n2999) );
NAND2X2TS U2012 ( .A(n3367), .B(n3356), .Y(n2530) );
NAND2X2TS U2013 ( .A(n488), .B(n3404), .Y(n2845) );
NOR2X2TS U2014 ( .A(n2904), .B(n2903), .Y(n2951) );
NOR2X2TS U2015 ( .A(n3025), .B(n3024), .Y(n3072) );
OAI21X1TS U2016 ( .A0(n2893), .A1(n2892), .B0(n2553), .Y(mult_x_56_n29) );
OAI21X2TS U2017 ( .A0(Op_MX[18]), .A1(n413), .B0(n2547), .Y(n2892) );
CMPR42X1TS U2018 ( .A(DP_OP_157J23_126_5719_n174), .B(
DP_OP_157J23_126_5719_n138), .C(DP_OP_157J23_126_5719_n141), .D(
DP_OP_157J23_126_5719_n181), .ICI(DP_OP_157J23_126_5719_n188), .S(
DP_OP_157J23_126_5719_n136), .ICO(DP_OP_157J23_126_5719_n134), .CO(
DP_OP_157J23_126_5719_n135) );
ADDHX1TS U2019 ( .A(n2242), .B(n2241), .CO(DP_OP_157J23_126_5719_n137), .S(
DP_OP_157J23_126_5719_n138) );
NOR2X2TS U2020 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]), .Y(
n2825) );
AOI21X2TS U2021 ( .A0(n2634), .A1(n2633), .B0(n3037), .Y(n3084) );
AOI21X2TS U2022 ( .A0(n2645), .A1(n2644), .B0(n2916), .Y(n2963) );
NOR2X2TS U2023 ( .A(n575), .B(n3414), .Y(n2994) );
AOI21X2TS U2024 ( .A0(n2458), .A1(n2457), .B0(n2456), .Y(n3039) );
AOI21X2TS U2025 ( .A0(n2472), .A1(n2471), .B0(n2470), .Y(n2918) );
INVX2TS U2026 ( .A(n449), .Y(n499) );
INVX2TS U2027 ( .A(n449), .Y(n500) );
INVX2TS U2028 ( .A(n449), .Y(n501) );
OAI22X1TS U2029 ( .A0(n1978), .A1(n1985), .B0(n1977), .B1(n1687), .Y(n1982)
);
OAI22X1TS U2030 ( .A0(n1978), .A1(n1977), .B0(n1985), .B1(n1953), .Y(n1972)
);
OAI22X1TS U2031 ( .A0(n1985), .A1(n1945), .B0(n1977), .B1(n1953), .Y(n1955)
);
OAI22X1TS U2032 ( .A0(n1985), .A1(n1923), .B0(n1977), .B1(n1945), .Y(n1948)
);
OAI22X1TS U2033 ( .A0(n1985), .A1(n1511), .B0(n1977), .B1(n1921), .Y(n1928)
);
OAI21X2TS U2034 ( .A0(n1438), .A1(n1491), .B0(n1437), .Y(n255) );
OAI21X2TS U2035 ( .A0(n1484), .A1(n1491), .B0(n1483), .Y(n253) );
INVX4TS U2036 ( .A(n2665), .Y(n1491) );
XNOR2X1TS U2037 ( .A(n1952), .B(n472), .Y(n1925) );
XNOR2X1TS U2038 ( .A(n1944), .B(n472), .Y(n1863) );
XNOR2X1TS U2039 ( .A(n1922), .B(n472), .Y(n1868) );
XNOR2X1TS U2040 ( .A(n2049), .B(n472), .Y(n1891) );
XNOR2X2TS U2041 ( .A(n1882), .B(n472), .Y(n1890) );
XNOR2X2TS U2042 ( .A(n1920), .B(n472), .Y(n1879) );
XOR2X1TS U2043 ( .A(n1861), .B(n1860), .Y(n1862) );
NOR2X2TS U2044 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n3229) );
INVX2TS U2045 ( .A(n1708), .Y(n502) );
OAI22X1TS U2046 ( .A0(n1844), .A1(n1839), .B0(n470), .B1(n1838), .Y(n1831)
);
OAI22X1TS U2047 ( .A0(n1844), .A1(n1842), .B0(n470), .B1(n1840), .Y(
DP_OP_158J23_127_356_n513) );
OAI22X1TS U2048 ( .A0(n1844), .A1(n1845), .B0(n470), .B1(n1843), .Y(n1727)
);
OAI22X1TS U2049 ( .A0(n1844), .A1(n2833), .B0(n470), .B1(n575), .Y(
DP_OP_158J23_127_356_n499) );
INVX2TS U2050 ( .A(n1721), .Y(n503) );
OAI22X1TS U2051 ( .A0(n503), .A1(n1839), .B0(n502), .B1(n1838), .Y(
DP_OP_158J23_127_356_n505) );
OAI22X2TS U2052 ( .A0(n1848), .A1(n1842), .B0(n502), .B1(n1840), .Y(n1830)
);
OAI22X1TS U2053 ( .A0(n1848), .A1(n1845), .B0(n1844), .B1(n1843), .Y(
DP_OP_158J23_127_356_n519) );
OAI22X1TS U2054 ( .A0(n1848), .A1(n3352), .B0(n1844), .B1(n575), .Y(n1826)
);
CLKXOR2X2TS U2055 ( .A(n1720), .B(n1719), .Y(n1721) );
INVX2TS U2056 ( .A(n1820), .Y(n504) );
OAI22X1TS U2057 ( .A0(n504), .A1(n1845), .B0(n503), .B1(n1843), .Y(
DP_OP_158J23_127_356_n518) );
OAI22X1TS U2058 ( .A0(n504), .A1(n1842), .B0(n503), .B1(n1840), .Y(
DP_OP_158J23_127_356_n511) );
OAI22X1TS U2059 ( .A0(n1850), .A1(n1849), .B0(n1848), .B1(n1847), .Y(
DP_OP_158J23_127_356_n525) );
OAI22X1TS U2060 ( .A0(n1850), .A1(n3352), .B0(n1848), .B1(n2330), .Y(
DP_OP_158J23_127_356_n497) );
INVX2TS U2061 ( .A(n1746), .Y(n505) );
OAI22X1TS U2062 ( .A0(n505), .A1(n1849), .B0(n504), .B1(n1847), .Y(
DP_OP_158J23_127_356_n524) );
OAI22X1TS U2063 ( .A0(n505), .A1(n1845), .B0(n1850), .B1(n1843), .Y(
DP_OP_158J23_127_356_n517) );
OAI22X1TS U2064 ( .A0(n1846), .A1(n2833), .B0(n1850), .B1(n2330), .Y(
DP_OP_158J23_127_356_n496) );
OAI22X1TS U2065 ( .A0(n1846), .A1(n1842), .B0(n1850), .B1(n1840), .Y(n1824)
);
OAI22X1TS U2066 ( .A0(n1846), .A1(n1839), .B0(n1850), .B1(n1838), .Y(n1821)
);
CLKXOR2X2TS U2067 ( .A(n1745), .B(n3367), .Y(n1746) );
INVX2TS U2068 ( .A(n2237), .Y(n507) );
CLKBUFX2TS U2069 ( .A(n2733), .Y(n508) );
XOR2X1TS U2070 ( .A(n2246), .B(n2252), .Y(n2247) );
CLKBUFX2TS U2071 ( .A(n2812), .Y(n509) );
CLKBUFX2TS U2072 ( .A(n2739), .Y(n510) );
OAI21X1TS U2073 ( .A0(n2315), .A1(n2311), .B0(n2312), .Y(n601) );
CLKBUFX2TS U2074 ( .A(n2737), .Y(n512) );
INVX2TS U2075 ( .A(n416), .Y(n513) );
NOR2XLTS U2076 ( .A(n477), .B(n390), .Y(n2320) );
NOR2X2TS U2077 ( .A(n390), .B(n2838), .Y(n2277) );
BUFX3TS U2078 ( .A(n401), .Y(n514) );
OAI22X1TS U2079 ( .A0(n514), .A1(n1699), .B0(n496), .B1(n1700), .Y(n1652) );
NOR2X1TS U2080 ( .A(n514), .B(n1687), .Y(DP_OP_158J23_127_356_n203) );
NOR2X1TS U2081 ( .A(n514), .B(n1511), .Y(n1531) );
OAI22X1TS U2082 ( .A0(n1689), .A1(n496), .B0(n1688), .B1(n401), .Y(n1668) );
OAI22X1TS U2083 ( .A0(n401), .A1(n1697), .B0(n1696), .B1(n496), .Y(n1685) );
OAI22X2TS U2084 ( .A0(n401), .A1(n1691), .B0(n1690), .B1(n496), .Y(n1672) );
OAI22X1TS U2085 ( .A0(n401), .A1(n1695), .B0(n1694), .B1(n496), .Y(n1680) );
OAI22X2TS U2086 ( .A0(n403), .A1(n1699), .B0(n515), .B1(n1700), .Y(n1536) );
NOR2X1TS U2087 ( .A(n515), .B(n1687), .Y(n1665) );
OAI22X1TS U2088 ( .A0(n495), .A1(n1697), .B0(n515), .B1(n1696), .Y(
DP_OP_158J23_127_356_n246) );
OAI22X1TS U2089 ( .A0(n495), .A1(n1691), .B0(n515), .B1(n1690), .Y(
DP_OP_158J23_127_356_n219) );
OAI22X1TS U2090 ( .A0(n403), .A1(n1695), .B0(n515), .B1(n1694), .Y(
DP_OP_158J23_127_356_n237) );
OAI22X1TS U2091 ( .A0(n403), .A1(n1688), .B0(n1689), .B1(n515), .Y(n1664) );
OAI22X1TS U2092 ( .A0(n403), .A1(n1693), .B0(n515), .B1(n1692), .Y(
DP_OP_158J23_127_356_n228) );
NOR2X1TS U2093 ( .A(n515), .B(n1511), .Y(n1684) );
OAI22X2TS U2094 ( .A0(n515), .A1(n1699), .B0(n514), .B1(n1700), .Y(n1683) );
OAI22X1TS U2095 ( .A0(n1689), .A1(n514), .B0(n1688), .B1(n515), .Y(
DP_OP_158J23_127_356_n211) );
OAI22X1TS U2096 ( .A0(n1698), .A1(n1695), .B0(n401), .B1(n1694), .Y(n1677)
);
OAI22X1TS U2097 ( .A0(n1698), .A1(n1697), .B0(n401), .B1(n1696), .Y(
DP_OP_158J23_127_356_n247) );
OAI22X1TS U2098 ( .A0(n1698), .A1(n1693), .B0(n401), .B1(n1692), .Y(
DP_OP_158J23_127_356_n229) );
OAI22X1TS U2099 ( .A0(n495), .A1(n1692), .B0(n516), .B1(n1693), .Y(
DP_OP_158J23_127_356_n227) );
OAI22X1TS U2100 ( .A0(n403), .A1(n1694), .B0(n516), .B1(n1695), .Y(
DP_OP_158J23_127_356_n236) );
NOR2X1TS U2101 ( .A(n1702), .B(n1687), .Y(DP_OP_158J23_127_356_n200) );
OAI22X1TS U2102 ( .A0(n495), .A1(n1700), .B0(n516), .B1(n1699), .Y(
DP_OP_158J23_127_356_n254) );
OAI22X1TS U2103 ( .A0(n403), .A1(n1696), .B0(n1702), .B1(n1697), .Y(
DP_OP_158J23_127_356_n245) );
NOR2X1TS U2104 ( .A(n516), .B(n1511), .Y(DP_OP_158J23_127_356_n262) );
INVX6TS U2105 ( .A(n671), .Y(n518) );
NOR2X1TS U2106 ( .A(n518), .B(n1687), .Y(n1658) );
OAI22X1TS U2107 ( .A0(n518), .A1(n1699), .B0(n1702), .B1(n1700), .Y(
DP_OP_158J23_127_356_n253) );
NOR2X1TS U2108 ( .A(n518), .B(n1511), .Y(DP_OP_158J23_127_356_n261) );
OAI22X1TS U2109 ( .A0(n517), .A1(n1695), .B0(n516), .B1(n1694), .Y(
DP_OP_158J23_127_356_n235) );
OAI22X1TS U2110 ( .A0(n518), .A1(n1688), .B0(n516), .B1(n1689), .Y(
DP_OP_158J23_127_356_n208) );
OAI22X1TS U2111 ( .A0(n519), .A1(n1693), .B0(n517), .B1(n1692), .Y(
DP_OP_158J23_127_356_n225) );
OAI22X1TS U2112 ( .A0(n1701), .A1(n1694), .B0(n490), .B1(n1695), .Y(
DP_OP_158J23_127_356_n233) );
OAI22X1TS U2113 ( .A0(n519), .A1(n1692), .B0(n490), .B1(n1693), .Y(
DP_OP_158J23_127_356_n224) );
OAI22X1TS U2114 ( .A0(n1701), .A1(n1688), .B0(n518), .B1(n1689), .Y(
DP_OP_158J23_127_356_n207) );
OAI22X1TS U2115 ( .A0(n519), .A1(n1696), .B0(n490), .B1(n1697), .Y(
DP_OP_158J23_127_356_n242) );
NOR2X1TS U2116 ( .A(n519), .B(n1687), .Y(DP_OP_158J23_127_356_n198) );
OAI22X1TS U2117 ( .A0(n1701), .A1(n1689), .B0(n490), .B1(n1688), .Y(
DP_OP_158J23_127_356_n206) );
OAI22X1TS U2118 ( .A0(n519), .A1(n1691), .B0(n518), .B1(n1690), .Y(
DP_OP_158J23_127_356_n216) );
OAI22X1TS U2119 ( .A0(n1701), .A1(n1697), .B0(n518), .B1(n1696), .Y(
DP_OP_158J23_127_356_n243) );
OAI22X1TS U2120 ( .A0(n1701), .A1(n1690), .B0(n490), .B1(n1691), .Y(n1656)
);
OAI22X1TS U2121 ( .A0(n1701), .A1(n1695), .B0(n518), .B1(n1694), .Y(
DP_OP_158J23_127_356_n234) );
OAI22X1TS U2122 ( .A0(n519), .A1(n1699), .B0(n517), .B1(n1700), .Y(
DP_OP_158J23_127_356_n252) );
NOR2X1TS U2123 ( .A(n1701), .B(n1511), .Y(DP_OP_158J23_127_356_n260) );
NAND2X2TS U2124 ( .A(n488), .B(n3353), .Y(n2876) );
NAND2X2TS U2125 ( .A(n466), .B(n498), .Y(n2902) );
NAND2X2TS U2126 ( .A(n3370), .B(Op_MY[2]), .Y(n3023) );
INVX2TS U2127 ( .A(n399), .Y(n1425) );
NOR2X2TS U2128 ( .A(n2840), .B(n2839), .Y(n2884) );
NOR2X2TS U2129 ( .A(n2559), .B(n2555), .Y(n2879) );
OAI21X2TS U2130 ( .A0(n2508), .A1(n2493), .B0(n2981), .Y(n3011) );
AOI22X2TS U2131 ( .A0(n2527), .A1(n2526), .B0(n2525), .B1(n2524), .Y(n3000)
);
NOR2X2TS U2132 ( .A(n3089), .B(n3093), .Y(n3090) );
NOR2X2TS U2133 ( .A(n3020), .B(n3016), .Y(n3017) );
NOR2X2TS U2134 ( .A(n424), .B(n548), .Y(n2946) );
NOR2X2TS U2135 ( .A(n582), .B(n557), .Y(n3046) );
NOR2X2TS U2136 ( .A(n431), .B(n551), .Y(n2925) );
NOR2X4TS U2137 ( .A(n2373), .B(DP_OP_156J23_125_3370_n297), .Y(n2375) );
NOR2X2TS U2138 ( .A(n567), .B(n568), .Y(n3067) );
OAI2BB2X2TS U2139 ( .B0(n2848), .B1(n2865), .A0N(n2864), .A1N(n3461), .Y(
n2885) );
NOR2X4TS U2140 ( .A(n573), .B(n432), .Y(n3461) );
AOI21X2TS U2141 ( .A0(n2507), .A1(n2506), .B0(n2505), .Y(n2983) );
OAI21X2TS U2142 ( .A0(n2980), .A1(n2979), .B0(n2978), .Y(n3008) );
AOI21X2TS U2143 ( .A0(n2540), .A1(n2539), .B0(n2858), .Y(n2868) );
AOI21X2TS U2144 ( .A0(n2931), .A1(n2930), .B0(n2929), .Y(n2940) );
AOI21X2TS U2145 ( .A0(n3052), .A1(n3051), .B0(n3050), .Y(n3061) );
OAI21X2TS U2146 ( .A0(n3032), .A1(n3033), .B0(n2415), .Y(n3066) );
OAI22X2TS U2147 ( .A0(ack_FSM), .A1(n2451), .B0(beg_FSM), .B1(n3440), .Y(
n3267) );
OAI21X1TS U2148 ( .A0(n3077), .A1(n2468), .B0(n2467), .Y(mult_x_57_n17) );
AOI22X2TS U2149 ( .A0(n3037), .A1(n2462), .B0(n2461), .B1(n3038), .Y(n3077)
);
OAI21X2TS U2150 ( .A0(n2534), .A1(n2535), .B0(n2419), .Y(n2993) );
OAI21X2TS U2151 ( .A0(n2911), .A1(n2912), .B0(n2417), .Y(n2945) );
AOI22X2TS U2152 ( .A0(n2916), .A1(n2476), .B0(n2475), .B1(n2917), .Y(n2956)
);
OAI22X2TS U2153 ( .A0(n3030), .A1(n3029), .B0(n3028), .B1(n3027), .Y(n3073)
);
OAI22X2TS U2154 ( .A0(n2909), .A1(n2908), .B0(n2907), .B1(n2906), .Y(n2952)
);
NOR2XLTS U2155 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n2822) );
NOR2XLTS U2156 ( .A(P_Sgf[47]), .B(n3264), .Y(n3265) );
ADDFX2TS U2157 ( .A(Op_MX[10]), .B(n3411), .CI(n650), .CO(n666), .S(n636) );
NOR2X2TS U2158 ( .A(n3411), .B(Op_MX[10]), .Y(n1815) );
NOR2X1TS U2159 ( .A(n1844), .B(n1851), .Y(n1728) );
NOR2X1TS U2160 ( .A(n1850), .B(n1851), .Y(n1834) );
NOR2X1TS U2161 ( .A(n1848), .B(n1851), .Y(n1836) );
INVX2TS U2162 ( .A(n1851), .Y(n1509) );
BUFX3TS U2163 ( .A(n2410), .Y(n521) );
BUFX3TS U2164 ( .A(n2410), .Y(n3253) );
NOR2X2TS U2165 ( .A(n3423), .B(n2409), .Y(n2410) );
INVX2TS U2166 ( .A(n3251), .Y(n522) );
INVX2TS U2167 ( .A(n3251), .Y(n523) );
INVX2TS U2168 ( .A(n3251), .Y(n524) );
OAI22X1TS U2169 ( .A0(n1941), .A1(n1975), .B0(n1954), .B1(n525), .Y(n1951)
);
OAI22X1TS U2170 ( .A0(n1941), .A1(n525), .B0(n1975), .B1(n1918), .Y(n1939)
);
OAI22X1TS U2171 ( .A0(n1975), .A1(n1878), .B0(n1877), .B1(n525), .Y(n1906)
);
OAI22X1TS U2172 ( .A0(n1975), .A1(n1973), .B0(n1869), .B1(n525), .Y(n1880)
);
OAI22X1TS U2173 ( .A0(n1975), .A1(n1877), .B0(n1867), .B1(n525), .Y(n1871)
);
OAI22X1TS U2174 ( .A0(n1975), .A1(n1867), .B0(n1919), .B1(n525), .Y(n1926)
);
OAI22X2TS U2175 ( .A0(n1975), .A1(n1954), .B0(n1973), .B1(n525), .Y(n1984)
);
NOR2BX1TS U2176 ( .AN(n2049), .B(n1974), .Y(n1898) );
NAND2X4TS U2177 ( .A(n1865), .B(n525), .Y(n1975) );
CLKBUFX2TS U2178 ( .A(n1942), .Y(n526) );
OAI22X1TS U2179 ( .A0(n1925), .A1(n526), .B0(n1863), .B1(n1943), .Y(n1936)
);
OAI22X1TS U2180 ( .A0(n1925), .A1(n1943), .B0(n1924), .B1(n526), .Y(n1933)
);
OAI22X1TS U2181 ( .A0(n1943), .A1(n1879), .B0(n1942), .B1(n1868), .Y(n1881)
);
OAI22X1TS U2182 ( .A0(n1863), .A1(n1942), .B0(n1943), .B1(n1868), .Y(n1873)
);
AO21X1TS U2183 ( .A0(n1943), .A1(n1942), .B0(n471), .Y(n1957) );
OAI22X1TS U2184 ( .A0(n1943), .A1(n1891), .B0(n1942), .B1(n1890), .Y(n1899)
);
OAI22X1TS U2185 ( .A0(n1943), .A1(n471), .B0(n1942), .B1(n1889), .Y(n1900)
);
NOR2BX1TS U2186 ( .AN(n2049), .B(n1942), .Y(n1886) );
NAND2X4TS U2187 ( .A(n1942), .B(n1862), .Y(n1943) );
NAND2X1TS U2188 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n3094) );
CLKBUFX2TS U2189 ( .A(n1852), .Y(n527) );
NOR2X1TS U2190 ( .A(n1852), .B(n1838), .Y(n1754) );
NOR2X1TS U2191 ( .A(n1852), .B(n1851), .Y(DP_OP_158J23_127_356_n529) );
OAI22X1TS U2192 ( .A0(n1846), .A1(n1838), .B0(n1852), .B1(n1839), .Y(
DP_OP_158J23_127_356_n502) );
OAI22X1TS U2193 ( .A0(n1846), .A1(n1847), .B0(n1852), .B1(n1849), .Y(
DP_OP_158J23_127_356_n523) );
NOR2X1TS U2194 ( .A(n1852), .B(n1847), .Y(n1828) );
NOR2X1TS U2195 ( .A(n1852), .B(n1843), .Y(n1823) );
OAI22X1TS U2196 ( .A0(n1846), .A1(n1843), .B0(n1852), .B1(n1845), .Y(n1827)
);
NOR2X1TS U2197 ( .A(n1852), .B(n1840), .Y(DP_OP_158J23_127_356_n508) );
INVX2TS U2198 ( .A(n528), .Y(n529) );
INVX2TS U2199 ( .A(n529), .Y(n1973) );
XOR2X1TS U2200 ( .A(n530), .B(n1864), .Y(n1865) );
NOR2X4TS U2201 ( .A(n529), .B(n667), .Y(n1545) );
AND2X2TS U2202 ( .A(n1604), .B(n1588), .Y(n533) );
OR2X4TS U2203 ( .A(Op_MX[1]), .B(Op_MX[13]), .Y(n534) );
AND2X2TS U2204 ( .A(n844), .B(n1365), .Y(n536) );
OR2X2TS U2205 ( .A(n1275), .B(n1274), .Y(n539) );
AO21X4TS U2206 ( .A0(n418), .A1(n444), .B0(n621), .Y(n553) );
OR2X1TS U2207 ( .A(n2051), .B(n2050), .Y(n564) );
INVX2TS U2208 ( .A(DP_OP_156J23_125_3370_n294), .Y(n1374) );
CLKBUFX2TS U2209 ( .A(n2225), .Y(n1459) );
NAND2X2TS U2210 ( .A(n959), .B(n958), .Y(n965) );
XNOR2X4TS U2211 ( .A(n1221), .B(n995), .Y(n576) );
OR2X2TS U2212 ( .A(n1861), .B(n628), .Y(n578) );
INVX2TS U2213 ( .A(n755), .Y(n781) );
INVX2TS U2214 ( .A(DP_OP_156J23_125_3370_n275), .Y(n1146) );
INVX2TS U2215 ( .A(n2214), .Y(n1442) );
AND2X2TS U2216 ( .A(n1740), .B(n1807), .Y(n586) );
AND2X2TS U2217 ( .A(n1503), .B(n1500), .Y(n587) );
OR2X2TS U2218 ( .A(DP_OP_158J23_127_356_n456), .B(n1747), .Y(n591) );
OA21X4TS U2219 ( .A0(n1136), .A1(n2208), .B0(n1137), .Y(n593) );
INVX2TS U2220 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(
n2081) );
NAND2X6TS U2221 ( .A(n966), .B(n965), .Y(n984) );
OAI21X2TS U2222 ( .A0(n2157), .A1(n2153), .B0(n2158), .Y(n2094) );
NAND2X1TS U2223 ( .A(n2111), .B(n2110), .Y(n2115) );
INVX2TS U2224 ( .A(n1807), .Y(n1808) );
INVX2TS U2225 ( .A(n979), .Y(n953) );
INVX2TS U2226 ( .A(n1743), .Y(n1744) );
INVX2TS U2227 ( .A(n1542), .Y(n655) );
NAND2X1TS U2228 ( .A(n929), .B(n935), .Y(n930) );
INVX2TS U2229 ( .A(n3303), .Y(n1053) );
INVX2TS U2230 ( .A(n2226), .Y(DP_OP_156J23_125_3370_n302) );
NOR2X6TS U2231 ( .A(n804), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n1408) );
INVX2TS U2232 ( .A(n1566), .Y(n1559) );
NOR2X4TS U2233 ( .A(n466), .B(n467), .Y(n1523) );
NOR2X4TS U2234 ( .A(Op_MX[18]), .B(n3371), .Y(n1552) );
NAND2X1TS U2235 ( .A(n1187), .B(n1186), .Y(n1188) );
AND2X4TS U2236 ( .A(DP_OP_156J23_125_3370_n222), .B(
DP_OP_156J23_125_3370_n224), .Y(n1079) );
NOR2X4TS U2237 ( .A(n1363), .B(n1408), .Y(n1399) );
NAND2X1TS U2238 ( .A(n1559), .B(n1564), .Y(n1560) );
OAI21X1TS U2239 ( .A0(n673), .A1(n1524), .B0(n674), .Y(n640) );
OAI22X2TS U2240 ( .A0(n495), .A1(n1689), .B0(n516), .B1(n1688), .Y(n1662) );
OAI22X1TS U2241 ( .A0(n401), .A1(n1693), .B0(n1692), .B1(n496), .Y(n1678) );
NAND2X1TS U2242 ( .A(n390), .B(n2838), .Y(n2278) );
INVX2TS U2243 ( .A(n980), .Y(n1133) );
NAND2X1TS U2244 ( .A(n1201), .B(n1228), .Y(n1202) );
INVX2TS U2245 ( .A(n1363), .Y(n1406) );
CLKXOR2X4TS U2246 ( .A(n2432), .B(n2431), .Y(n2737) );
INVX2TS U2247 ( .A(n1944), .Y(n1953) );
XNOR2X1TS U2248 ( .A(n530), .B(n2049), .Y(n1878) );
ADDHX1TS U2249 ( .A(n1670), .B(n1669), .CO(DP_OP_158J23_127_356_n169), .S(
n1666) );
NAND2X1TS U2250 ( .A(n1110), .B(n1101), .Y(n1102) );
INVX2TS U2251 ( .A(n1769), .Y(n1748) );
NAND2X1TS U2252 ( .A(n2829), .B(n3353), .Y(n2549) );
ADDHX1TS U2253 ( .A(n1837), .B(n1836), .CO(DP_OP_158J23_127_356_n490), .S(
n1725) );
OAI22X1TS U2254 ( .A0(n519), .A1(n1700), .B0(n490), .B1(n1699), .Y(
DP_OP_158J23_127_356_n251) );
ADDHX1TS U2255 ( .A(n1681), .B(n1680), .CO(n1675), .S(
DP_OP_158J23_127_356_n190) );
OAI22X1TS U2256 ( .A0(n2810), .A1(n2811), .B0(n476), .B1(n2813), .Y(
DP_OP_157J23_126_5719_n186) );
INVX2TS U2257 ( .A(DP_OP_156J23_125_3370_n267), .Y(n1253) );
AOI21X1TS U2258 ( .A0(n1765), .A1(n591), .B0(n1748), .Y(n1749) );
NOR2X4TS U2259 ( .A(DP_OP_158J23_127_356_n121), .B(n1576), .Y(n1594) );
INVX2TS U2260 ( .A(n2394), .Y(n1421) );
NOR2X1TS U2261 ( .A(DP_OP_159J23_128_5719_n123), .B(
DP_OP_159J23_128_5719_n128), .Y(n2703) );
CMPR42X1TS U2262 ( .A(DP_OP_157J23_126_5719_n161), .B(
DP_OP_157J23_126_5719_n154), .C(DP_OP_157J23_126_5719_n147), .D(
DP_OP_157J23_126_5719_n106), .ICI(DP_OP_157J23_126_5719_n103), .S(
DP_OP_157J23_126_5719_n102), .ICO(DP_OP_157J23_126_5719_n100), .CO(
DP_OP_157J23_126_5719_n101) );
INVX2TS U2263 ( .A(n1760), .Y(n1761) );
INVX2TS U2264 ( .A(n2010), .Y(n2018) );
INVX2TS U2265 ( .A(n2040), .Y(n2042) );
INVX2TS U2266 ( .A(Op_MX[16]), .Y(n2830) );
AOI21X1TS U2267 ( .A0(n1762), .A1(n592), .B0(n1761), .Y(n1763) );
NAND2X1TS U2268 ( .A(n1596), .B(n1595), .Y(n1597) );
NAND2X1TS U2269 ( .A(n2007), .B(n2006), .Y(n2008) );
INVX2TS U2270 ( .A(n551), .Y(n2837) );
XNOR2X1TS U2271 ( .A(n1758), .B(n1757), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10)
);
NOR2X2TS U2272 ( .A(n3404), .B(n462), .Y(n2232) );
INVX2TS U2273 ( .A(Op_MY[12]), .Y(n597) );
NAND2X2TS U2274 ( .A(n3362), .B(n413), .Y(n2235) );
OAI21X4TS U2275 ( .A0(n2232), .A1(n2235), .B0(n2233), .Y(n2269) );
NOR2X2TS U2276 ( .A(n2275), .B(n2277), .Y(n599) );
NAND2X2TS U2277 ( .A(n489), .B(n466), .Y(n2274) );
OAI21X2TS U2278 ( .A0(n2277), .A1(n2274), .B0(n2278), .Y(n598) );
NOR2X2TS U2279 ( .A(n3353), .B(Op_MY[16]), .Y(n2311) );
CLKXOR2X4TS U2280 ( .A(n601), .B(n600), .Y(n2810) );
INVX2TS U2281 ( .A(n602), .Y(n2811) );
ADDHXLTS U2282 ( .A(Op_MX[18]), .B(n419), .CO(n602), .S(n604) );
INVX2TS U2283 ( .A(n604), .Y(n2813) );
INVX8TS U2284 ( .A(n2648), .Y(n3380) );
AOI21X4TS U2285 ( .A0(n611), .A1(n630), .B0(n612), .Y(n613) );
OAI21X4TS U2286 ( .A0(n624), .A1(n614), .B0(n613), .Y(n651) );
AOI21X4TS U2287 ( .A0(n439), .A1(n616), .B0(n615), .Y(n1549) );
OAI21X4TS U2288 ( .A0(n1549), .A1(n1552), .B0(n1553), .Y(n617) );
AOI21X4TS U2289 ( .A0(n436), .A1(n553), .B0(n623), .Y(n649) );
XNOR2X4TS U2290 ( .A(n631), .B(n626), .Y(n1861) );
AOI21X4TS U2291 ( .A0(n1507), .A1(n578), .B0(n629), .Y(n638) );
AOI21X4TS U2292 ( .A0(n631), .A1(n610), .B0(n630), .Y(n634) );
OAI21X4TS U2293 ( .A0(n1514), .A1(n1517), .B0(n1515), .Y(n672) );
XNOR2X4TS U2294 ( .A(n1569), .B(n642), .Y(n1944) );
OAI21X4TS U2295 ( .A0(n649), .A1(n648), .B0(n647), .Y(n1547) );
INVX2TS U2296 ( .A(Op_MX[11]), .Y(n2824) );
XOR2X4TS U2297 ( .A(n660), .B(n656), .Y(n657) );
XNOR2X4TS U2298 ( .A(n670), .B(n669), .Y(n671) );
OAI21X4TS U2299 ( .A0(n1527), .A1(n1523), .B0(n1524), .Y(n677) );
XNOR2X4TS U2300 ( .A(n677), .B(n676), .Y(n1922) );
ADDFHX2TS U2301 ( .A(n683), .B(n682), .CI(DP_OP_158J23_127_356_n158), .CO(
DP_OP_158J23_127_356_n148), .S(DP_OP_158J23_127_356_n149) );
ADDFHX2TS U2302 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]),
.B(n689), .CI(n690), .S(n684) );
INVX4TS U2303 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[2]), .Y(
n690) );
NOR2X8TS U2304 ( .A(n694), .B(n693), .Y(n789) );
XNOR2X4TS U2305 ( .A(n685), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(n688) );
AOI21X4TS U2306 ( .A0(n396), .A1(DP_OP_154J23_123_2814_n140), .B0(n687), .Y(
n772) );
OAI21X4TS U2307 ( .A0(n769), .A1(n772), .B0(n770), .Y(n766) );
NAND2X4TS U2308 ( .A(n694), .B(n693), .Y(n790) );
OAI21X4TS U2309 ( .A0(n789), .A1(n786), .B0(n790), .Y(n695) );
AOI21X4TS U2310 ( .A0(n696), .A1(n766), .B0(n695), .Y(n740) );
ADDFHX2TS U2311 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]),
.B(n698), .CI(n697), .CO(n705), .S(n694) );
NOR2X8TS U2312 ( .A(n709), .B(n700), .Y(n710) );
AND2X8TS U2313 ( .A(n782), .B(n757), .Y(n761) );
INVX4TS U2314 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(
n703) );
ADDFHX4TS U2315 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]),
.B(n701), .CI(n1044), .CO(n711), .S(n709) );
NAND2X4TS U2316 ( .A(n761), .B(n716), .Y(n718) );
ADDFHX2TS U2317 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]),
.B(n707), .CI(n706), .CO(n700), .S(n704) );
NAND2X4TS U2318 ( .A(n705), .B(n704), .Y(n755) );
NAND2X4TS U2319 ( .A(n709), .B(n708), .Y(n756) );
OAI21X4TS U2320 ( .A0(n755), .A1(n710), .B0(n756), .Y(n760) );
NAND2X4TS U2321 ( .A(n712), .B(n711), .Y(n762) );
OA21X4TS U2322 ( .A0(n740), .A1(n718), .B0(n717), .Y(n751) );
ADDFHX4TS U2323 ( .A(n719), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]), .CI(n774), .CO(
n720), .S(n714) );
OR2X4TS U2324 ( .A(n721), .B(n720), .Y(n753) );
INVX2TS U2325 ( .A(n753), .Y(n722) );
NAND2X4TS U2326 ( .A(n721), .B(n720), .Y(n752) );
INVX6TS U2327 ( .A(n752), .Y(n732) );
AOI2BB1X4TS U2328 ( .A0N(n751), .A1N(n722), .B0(n732), .Y(n728) );
INVX2TS U2329 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(
n733) );
CMPR32X2TS U2330 ( .A(n724), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]), .C(n723), .CO(
n726), .S(n721) );
NAND2X4TS U2331 ( .A(n726), .B(n725), .Y(n729) );
XOR2X4TS U2332 ( .A(n728), .B(n727), .Y(n805) );
NOR2X8TS U2333 ( .A(n805), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n1384) );
AOI21X4TS U2334 ( .A0(n732), .A1(n731), .B0(n730), .Y(n829) );
CMPR32X2TS U2335 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]),
.B(n734), .C(n733), .CO(n735), .S(n725) );
INVX2TS U2336 ( .A(n822), .Y(n737) );
NAND2X2TS U2337 ( .A(n736), .B(n735), .Y(n826) );
NOR2X8TS U2338 ( .A(n1384), .B(n1389), .Y(n809) );
INVX2TS U2339 ( .A(n761), .Y(n742) );
INVX2TS U2340 ( .A(n741), .Y(n763) );
INVX2TS U2341 ( .A(n760), .Y(n743) );
AOI21X4TS U2342 ( .A0(n784), .A1(n745), .B0(n744), .Y(n750) );
INVX2TS U2343 ( .A(n746), .Y(n748) );
XNOR2X4TS U2344 ( .A(n750), .B(n749), .Y(n803) );
XNOR2X4TS U2345 ( .A(n832), .B(n754), .Y(n804) );
INVX2TS U2346 ( .A(n769), .Y(n771) );
NAND2X2TS U2347 ( .A(n771), .B(n770), .Y(n773) );
XOR2X4TS U2348 ( .A(n773), .B(n772), .Y(n778) );
INVX2TS U2349 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(
n774) );
INVX2TS U2350 ( .A(n774), .Y(n777) );
NAND2X2TS U2351 ( .A(n778), .B(n777), .Y(n1061) );
XNOR2X4TS U2352 ( .A(n784), .B(n783), .Y(n795) );
OR2X8TS U2353 ( .A(n795), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n1113) );
INVX2TS U2354 ( .A(n785), .Y(n787) );
INVX2TS U2355 ( .A(n789), .Y(n791) );
NAND2X4TS U2356 ( .A(n1113), .B(n1110), .Y(n798) );
NAND2X4TS U2357 ( .A(n795), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n1112) );
AOI21X4TS U2358 ( .A0(n1113), .A1(n1109), .B0(n796), .Y(n797) );
OAI21X4TS U2359 ( .A0(n1100), .A1(n798), .B0(n797), .Y(n1325) );
OAI21X4TS U2360 ( .A0(n1345), .A1(n1342), .B0(n1346), .Y(n801) );
AOI21X4TS U2361 ( .A0(n802), .A1(n1325), .B0(n801), .Y(n1362) );
NAND2X4TS U2362 ( .A(n804), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n1409) );
OAI21X4TS U2363 ( .A0(n1408), .A1(n1404), .B0(n1409), .Y(n1398) );
OAI21X4TS U2364 ( .A0(n1389), .A1(n1400), .B0(n1390), .Y(n808) );
AOI21X4TS U2365 ( .A0(n1398), .A1(n809), .B0(n808), .Y(n810) );
OAI21X4TS U2366 ( .A0(n811), .A1(n1362), .B0(n810), .Y(n812) );
OAI21X2TS U2367 ( .A0(n829), .A1(n822), .B0(n826), .Y(n813) );
ADDFX2TS U2368 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]),
.B(n816), .CI(n815), .CO(n817), .S(n736) );
INVX2TS U2369 ( .A(n827), .Y(n819) );
NAND2X2TS U2370 ( .A(n818), .B(n817), .Y(n825) );
OA21X4TS U2371 ( .A0(n827), .A1(n826), .B0(n825), .Y(n828) );
AOI21X4TS U2372 ( .A0(n832), .A1(n831), .B0(n830), .Y(n841) );
INVX2TS U2373 ( .A(n840), .Y(n835) );
XNOR2X4TS U2374 ( .A(n842), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .Y(n843) );
INVX2TS U2375 ( .A(n1366), .Y(n844) );
NAND2X4TS U2376 ( .A(n843), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n1365) );
XOR2X4TS U2377 ( .A(n1367), .B(n536), .Y(DP_OP_156J23_125_3370_n294) );
INVX2TS U2378 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(
n1368) );
INVX2TS U2379 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(
n1372) );
AOI21X4TS U2380 ( .A0(n848), .A1(n847), .B0(n846), .Y(n1370) );
AOI2BB2X4TS U2381 ( .B0(n1377), .B1(n849), .A0N(n1370), .A1N(n1372), .Y(
n1424) );
INVX2TS U2382 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(
n1423) );
NOR2X4TS U2383 ( .A(n1424), .B(n1423), .Y(n851) );
INVX2TS U2384 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(
n850) );
XNOR2X4TS U2385 ( .A(n851), .B(n850), .Y(n2396) );
XOR2X4TS U2386 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]),
.B(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(n854) );
OR2X8TS U2387 ( .A(n852), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .Y(n892) );
AOI21X4TS U2388 ( .A0(n892), .A1(n893), .B0(n853), .Y(n889) );
NAND2X4TS U2389 ( .A(n854), .B(n1029), .Y(n887) );
OAI21X4TS U2390 ( .A0(n886), .A1(n889), .B0(n887), .Y(n896) );
INVX2TS U2391 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(
n855) );
NOR2X8TS U2392 ( .A(n858), .B(n859), .Y(n905) );
INVX8TS U2393 ( .A(Sgf_operation_Result[3]), .Y(n866) );
ADDFHX4TS U2394 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]),
.B(n857), .CI(n856), .CO(n860), .S(n859) );
NOR2X8TS U2395 ( .A(n861), .B(n860), .Y(n907) );
NOR2X4TS U2396 ( .A(n905), .B(n907), .Y(n863) );
NAND2X6TS U2397 ( .A(n859), .B(n858), .Y(n904) );
NAND2X4TS U2398 ( .A(n861), .B(n860), .Y(n908) );
OAI21X4TS U2399 ( .A0(n907), .A1(n904), .B0(n908), .Y(n862) );
AOI21X4TS U2400 ( .A0(n896), .A1(n863), .B0(n862), .Y(n864) );
ADDFHX4TS U2401 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3]),
.B(n866), .CI(n865), .CO(n867), .S(n861) );
ADDFHX4TS U2402 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]),
.B(n870), .CI(n1041), .CO(n871), .S(n868) );
NOR2X8TS U2403 ( .A(n872), .B(n871), .Y(n878) );
NOR2X8TS U2404 ( .A(n876), .B(n878), .Y(n941) );
OAI21X4TS U2405 ( .A0(n878), .A1(n901), .B0(n877), .Y(n939) );
ADDFHX4TS U2406 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]),
.B(n880), .CI(n879), .CO(n881), .S(n872) );
NOR2X8TS U2407 ( .A(n882), .B(n881), .Y(n934) );
INVX2TS U2408 ( .A(n934), .Y(n883) );
NAND2X4TS U2409 ( .A(n882), .B(n881), .Y(n936) );
XNOR2X4TS U2410 ( .A(n924), .B(n903), .Y(n913) );
INVX2TS U2411 ( .A(n907), .Y(n909) );
NAND2X4TS U2412 ( .A(n1497), .B(n2204), .Y(n916) );
NAND2X4TS U2413 ( .A(n913), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(n1496) );
OA21X4TS U2414 ( .A0(n914), .A1(n2203), .B0(n1496), .Y(n915) );
OAI21X4TS U2415 ( .A0(n1494), .A1(n916), .B0(n915), .Y(n1135) );
OAI2BB1X4TS U2416 ( .A0N(n919), .A1N(n1135), .B0(n593), .Y(n1152) );
ADDFHX4TS U2417 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]),
.B(n926), .CI(n925), .CO(n927), .S(n882) );
NAND2X2TS U2418 ( .A(n928), .B(n927), .Y(n935) );
XOR2X4TS U2419 ( .A(n931), .B(n930), .Y(n932) );
AOI21X4TS U2420 ( .A0(n939), .A1(n940), .B0(n938), .Y(n945) );
OR2X8TS U2421 ( .A(n943), .B(n942), .Y(n944) );
NAND2X8TS U2422 ( .A(n945), .B(n944), .Y(n1006) );
XNOR2X4TS U2423 ( .A(n1006), .B(n950), .Y(n952) );
NAND2X4TS U2424 ( .A(n952), .B(n951), .Y(n975) );
XOR2X4TS U2425 ( .A(n954), .B(n532), .Y(DP_OP_156J23_125_3370_n275) );
INVX2TS U2426 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]),
.Y(n968) );
OR2X4TS U2427 ( .A(n959), .B(n958), .Y(n963) );
XOR2X4TS U2428 ( .A(n961), .B(n960), .Y(n976) );
INVX2TS U2429 ( .A(n997), .Y(n967) );
INVX2TS U2430 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]),
.Y(n987) );
NOR2X6TS U2431 ( .A(n971), .B(n970), .Y(n996) );
INVX2TS U2432 ( .A(n996), .Y(n972) );
NAND2X4TS U2433 ( .A(n971), .B(n970), .Y(n999) );
OAI21X4TS U2434 ( .A0(n1132), .A1(n979), .B0(n975), .Y(n1163) );
INVX4TS U2435 ( .A(n1200), .Y(n1221) );
INVX2TS U2436 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]),
.Y(n1007) );
CMPR32X2TS U2437 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]), .B(n988), .C(n987), .CO(n989), .S(n971) );
INVX2TS U2438 ( .A(n1000), .Y(n991) );
NAND2X2TS U2439 ( .A(n990), .B(n989), .Y(n998) );
XOR2X4TS U2440 ( .A(n993), .B(n992), .Y(n994) );
OA21X4TS U2441 ( .A0(n1000), .A1(n999), .B0(n998), .Y(n1001) );
AOI21X4TS U2442 ( .A0(n1006), .A1(n1005), .B0(n1004), .Y(n1015) );
CMPR32X2TS U2443 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]), .B(n1008), .C(n1007), .CO(n1009), .S(n990) );
INVX2TS U2444 ( .A(n1014), .Y(n1010) );
NAND2X2TS U2445 ( .A(n1010), .B(n1013), .Y(n1011) );
XOR2X4TS U2446 ( .A(n1015), .B(n1011), .Y(n1017) );
NOR2X8TS U2447 ( .A(n1017), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n1185) );
NOR2X8TS U2448 ( .A(n1012), .B(n408), .Y(n1199) );
XNOR2X4TS U2449 ( .A(n1016), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]), .Y(n1018) );
INVX2TS U2450 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
n1231) );
INVX2TS U2451 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
n1222) );
NAND2X4TS U2452 ( .A(n1017), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n1186) );
OAI21X4TS U2453 ( .A0(n1185), .A1(n1182), .B0(n1186), .Y(n1198) );
AOI21X4TS U2454 ( .A0(n1020), .A1(n1198), .B0(n1019), .Y(n1219) );
AOI2BB2X4TS U2455 ( .B0(n1021), .B1(n1200), .A0N(n1219), .A1N(n1222), .Y(
n1243) );
INVX2TS U2456 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]),
.Y(n1242) );
NOR2X8TS U2457 ( .A(DP_OP_156J23_125_3370_n228), .B(
DP_OP_156J23_125_3370_n230), .Y(n1117) );
NOR2X4TS U2458 ( .A(n1117), .B(n1122), .Y(n1077) );
OR2X4TS U2459 ( .A(DP_OP_156J23_125_3370_n237), .B(
DP_OP_156J23_125_3370_n239), .Y(n1267) );
NAND2X2TS U2460 ( .A(n1262), .B(n1267), .Y(n1075) );
NAND2X1TS U2461 ( .A(n1023), .B(n1022), .Y(n1025) );
XNOR2X2TS U2462 ( .A(n1025), .B(n1024), .Y(n1309) );
INVX2TS U2463 ( .A(n1309), .Y(n1067) );
INVX2TS U2464 ( .A(Sgf_operation_EVEN1_Q_left[1]), .Y(n1027) );
INVX2TS U2465 ( .A(n1141), .Y(n1026) );
NAND2X1TS U2466 ( .A(n1028), .B(n1027), .Y(n1128) );
INVX2TS U2467 ( .A(Sgf_operation_Result[2]), .Y(n1033) );
INVX2TS U2468 ( .A(n690), .Y(n1274) );
INVX2TS U2469 ( .A(n1147), .Y(n1032) );
AOI21X4TS U2470 ( .A0(n1150), .A1(n1148), .B0(n1032), .Y(n1160) );
CLKBUFX2TS U2471 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[3]),
.Y(n1276) );
INVX2TS U2472 ( .A(n1276), .Y(n1037) );
CMPR32X2TS U2473 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]),
.B(n1033), .C(n690), .CO(n1034), .S(n1031) );
NAND2X1TS U2474 ( .A(n1035), .B(n1034), .Y(n1157) );
OAI21X4TS U2475 ( .A0(n1160), .A1(n1156), .B0(n1157), .Y(n1177) );
INVX2TS U2476 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[4]), .Y(
n1036) );
CMPR32X2TS U2477 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]),
.B(n866), .C(n1037), .CO(n1038), .S(n1035) );
NAND2X1TS U2478 ( .A(n1039), .B(n1038), .Y(n1174) );
INVX2TS U2479 ( .A(n1174), .Y(n1040) );
CMPR32X2TS U2480 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]),
.B(n1041), .C(n1036), .CO(n1042), .S(n1039) );
NOR2X1TS U2481 ( .A(n1043), .B(n1042), .Y(n1193) );
NAND2X1TS U2482 ( .A(n1043), .B(n1042), .Y(n1194) );
AND2X2TS U2483 ( .A(n559), .B(n1063), .Y(n1303) );
INVX2TS U2484 ( .A(n1303), .Y(n1048) );
NAND2X1TS U2485 ( .A(n1049), .B(n1048), .Y(n1190) );
INVX2TS U2486 ( .A(n1190), .Y(n1050) );
INVX2TS U2487 ( .A(n1055), .Y(n1057) );
XOR2X4TS U2488 ( .A(n1059), .B(n1058), .Y(n3305) );
INVX2TS U2489 ( .A(n1060), .Y(n1062) );
NAND2X1TS U2490 ( .A(n1062), .B(n1061), .Y(n1064) );
CLKXOR2X2TS U2491 ( .A(n1064), .B(n1063), .Y(n1307) );
INVX2TS U2492 ( .A(n1307), .Y(n1065) );
NOR2X2TS U2493 ( .A(n1066), .B(n1065), .Y(n1203) );
NAND2X1TS U2494 ( .A(n1066), .B(n1065), .Y(n1204) );
INVX2TS U2495 ( .A(n1224), .Y(n1068) );
NAND2X2TS U2496 ( .A(n1249), .B(n1247), .Y(n1071) );
NAND2X2TS U2497 ( .A(DP_OP_156J23_125_3370_n246), .B(
DP_OP_156J23_125_3370_n248), .Y(n1217) );
INVX2TS U2498 ( .A(n1217), .Y(n1246) );
NAND2X2TS U2499 ( .A(DP_OP_156J23_125_3370_n243), .B(
DP_OP_156J23_125_3370_n245), .Y(n1250) );
INVX2TS U2500 ( .A(n1250), .Y(n1069) );
AOI21X4TS U2501 ( .A0(n1249), .A1(n1246), .B0(n1069), .Y(n1070) );
INVX2TS U2502 ( .A(n1238), .Y(n1072) );
INVX2TS U2503 ( .A(n1266), .Y(n1261) );
INVX2TS U2504 ( .A(n1263), .Y(n1073) );
AOI21X4TS U2505 ( .A0(n1262), .A1(n1261), .B0(n1073), .Y(n1074) );
OAI21X4TS U2506 ( .A0(n1075), .A1(n1260), .B0(n1074), .Y(n1116) );
OAI21X4TS U2507 ( .A0(n1117), .A1(n1123), .B0(n1118), .Y(n1076) );
AOI21X4TS U2508 ( .A0(n1077), .A1(n1116), .B0(n1076), .Y(n1090) );
INVX2TS U2509 ( .A(n1292), .Y(n1078) );
NOR2X1TS U2510 ( .A(n1078), .B(n1294), .Y(n1082) );
NAND2X4TS U2511 ( .A(DP_OP_156J23_125_3370_n219), .B(
DP_OP_156J23_125_3370_n221), .Y(n1295) );
AOI21X2TS U2512 ( .A0(n1293), .A1(n1082), .B0(n1081), .Y(n1085) );
INVX2TS U2513 ( .A(n1087), .Y(n1083) );
XOR2X4TS U2514 ( .A(n1085), .B(n1084), .Y(n1308) );
AOI21X4TS U2515 ( .A0(n1089), .A1(n1291), .B0(n1088), .Y(n1093) );
NAND2X4TS U2516 ( .A(n1089), .B(n1292), .Y(n1091) );
NAND2X8TS U2517 ( .A(n1093), .B(n1092), .Y(n1356) );
NOR2X4TS U2518 ( .A(DP_OP_156J23_125_3370_n213), .B(
DP_OP_156J23_125_3370_n215), .Y(n1103) );
INVX2TS U2519 ( .A(n1103), .Y(n1096) );
NAND2X2TS U2520 ( .A(n406), .B(n1096), .Y(n1094) );
XNOR2X4TS U2521 ( .A(n1356), .B(n1094), .Y(n1310) );
INVX2TS U2522 ( .A(n1105), .Y(n1095) );
AOI21X4TS U2523 ( .A0(n1356), .A1(n1096), .B0(n1095), .Y(n1099) );
NAND2X2TS U2524 ( .A(DP_OP_156J23_125_3370_n210), .B(
DP_OP_156J23_125_3370_n212), .Y(n1104) );
INVX2TS U2525 ( .A(n1106), .Y(n1097) );
XOR2X4TS U2526 ( .A(n1099), .B(n1098), .Y(n1311) );
XNOR2X4TS U2527 ( .A(n1111), .B(n1102), .Y(n2199) );
NOR2X4TS U2528 ( .A(n1103), .B(n1106), .Y(n1329) );
OAI21X4TS U2529 ( .A0(n1106), .A1(n1105), .B0(n1104), .Y(n1334) );
INVX2TS U2530 ( .A(n1328), .Y(n1319) );
XOR2X4TS U2531 ( .A(n1108), .B(n1107), .Y(n1312) );
AOI21X4TS U2532 ( .A0(n1111), .A1(n1110), .B0(n1109), .Y(n1115) );
XOR2X4TS U2533 ( .A(n1115), .B(n1114), .Y(n2201) );
INVX2TS U2534 ( .A(n1117), .Y(n1119) );
XNOR2X2TS U2535 ( .A(n1121), .B(n1120), .Y(n1277) );
NAND2X1TS U2536 ( .A(n1124), .B(n1123), .Y(n1125) );
INVX2TS U2537 ( .A(n1127), .Y(n1129) );
NAND2X1TS U2538 ( .A(n1129), .B(n1128), .Y(n1131) );
XOR2X1TS U2539 ( .A(n1131), .B(n1130), .Y(n1144) );
XNOR2X4TS U2540 ( .A(n1152), .B(n1134), .Y(n2221) );
OAI21X4TS U2541 ( .A0(n2211), .A1(n2207), .B0(n2208), .Y(n1140) );
XNOR2X4TS U2542 ( .A(n1140), .B(n1139), .Y(n2220) );
NAND2X1TS U2543 ( .A(n1142), .B(n1141), .Y(n1143) );
XNOR2X1TS U2544 ( .A(n1143), .B(DP_OP_154J23_123_2814_n140), .Y(n3298) );
NAND2X1TS U2545 ( .A(n2220), .B(n3298), .Y(n3299) );
INVX2TS U2546 ( .A(n3299), .Y(n3271) );
NAND2X1TS U2547 ( .A(n2221), .B(n1144), .Y(n3270) );
INVX2TS U2548 ( .A(n3270), .Y(n1145) );
NAND2X1TS U2549 ( .A(n1148), .B(n1147), .Y(n1149) );
XNOR2X1TS U2550 ( .A(n1150), .B(n1149), .Y(n1151) );
NOR2X1TS U2551 ( .A(n1146), .B(n1151), .Y(n3292) );
NAND2X1TS U2552 ( .A(n1146), .B(n1151), .Y(n3293) );
OAI21X1TS U2553 ( .A0(n3296), .A1(n3292), .B0(n3293), .Y(n3278) );
AOI21X2TS U2554 ( .A0(n1161), .A1(n1152), .B0(n1163), .Y(n1155) );
INVX2TS U2555 ( .A(n1166), .Y(n1153) );
INVX2TS U2556 ( .A(n1156), .Y(n1158) );
NAND2X1TS U2557 ( .A(n1158), .B(n1157), .Y(n1159) );
XOR2X1TS U2558 ( .A(n1160), .B(n1159), .Y(n1178) );
NOR2X2TS U2559 ( .A(n2202), .B(n1178), .Y(n3283) );
INVX2TS U2560 ( .A(n1163), .Y(n1165) );
AOI21X2TS U2561 ( .A0(n1152), .A1(n1168), .B0(n1167), .Y(n1173) );
INVX2TS U2562 ( .A(n1169), .Y(n1171) );
XOR2X4TS U2563 ( .A(n1173), .B(n1172), .Y(n2212) );
NAND2X1TS U2564 ( .A(n1175), .B(n1174), .Y(n1176) );
XNOR2X1TS U2565 ( .A(n1177), .B(n1176), .Y(n1179) );
NOR2X2TS U2566 ( .A(n2212), .B(n1179), .Y(n3285) );
NOR2X1TS U2567 ( .A(n3283), .B(n3285), .Y(n1181) );
NAND2X1TS U2568 ( .A(n2202), .B(n1178), .Y(n3282) );
NAND2X1TS U2569 ( .A(n2212), .B(n1179), .Y(n3286) );
OAI21X1TS U2570 ( .A0(n3285), .A1(n3282), .B0(n3286), .Y(n1180) );
AOI21X2TS U2571 ( .A0(n3278), .A1(n1181), .B0(n1180), .Y(n3274) );
INVX2TS U2572 ( .A(n1182), .Y(n1183) );
INVX2TS U2573 ( .A(n408), .Y(n1187) );
NAND2X1TS U2574 ( .A(n535), .B(n1190), .Y(n1191) );
XNOR2X1TS U2575 ( .A(n1192), .B(n1191), .Y(n1210) );
NOR2X2TS U2576 ( .A(n1211), .B(n1210), .Y(n3314) );
INVX2TS U2577 ( .A(n576), .Y(n1209) );
INVX2TS U2578 ( .A(n1193), .Y(n1195) );
NAND2X1TS U2579 ( .A(n1195), .B(n1194), .Y(n1196) );
XOR2X1TS U2580 ( .A(n1197), .B(n1196), .Y(n1208) );
NOR2X1TS U2581 ( .A(n1209), .B(n1208), .Y(n3275) );
NOR2X1TS U2582 ( .A(n3314), .B(n3275), .Y(n3321) );
AOI21X4TS U2583 ( .A0(n1200), .A1(n1199), .B0(n1198), .Y(n1230) );
INVX2TS U2584 ( .A(n1229), .Y(n1201) );
XOR2X4TS U2585 ( .A(n1230), .B(n1202), .Y(n2213) );
INVX2TS U2586 ( .A(n1203), .Y(n1205) );
NAND2X1TS U2587 ( .A(n1205), .B(n1204), .Y(n1207) );
XOR2X1TS U2588 ( .A(n1207), .B(n1206), .Y(n1212) );
NAND2X1TS U2589 ( .A(n1211), .B(n1210), .Y(n3315) );
NAND2X1TS U2590 ( .A(n2213), .B(n1212), .Y(n3323) );
INVX2TS U2591 ( .A(n3323), .Y(n1213) );
NAND2X1TS U2592 ( .A(n1247), .B(n1217), .Y(n1218) );
OAI21X4TS U2593 ( .A0(n1221), .A1(n1220), .B0(n1219), .Y(n1223) );
XNOR2X4TS U2594 ( .A(n1223), .B(n1222), .Y(n2200) );
NOR2X2TS U2595 ( .A(n1235), .B(n2200), .Y(n3334) );
NAND2X1TS U2596 ( .A(n1225), .B(n1224), .Y(n1227) );
INVX2TS U2597 ( .A(n428), .Y(n1233) );
NOR2X1TS U2598 ( .A(n3334), .B(n3332), .Y(n1237) );
NAND2X1TS U2599 ( .A(n1235), .B(n2200), .Y(n3335) );
AOI21X4TS U2600 ( .A0(n3327), .A1(n1237), .B0(n1236), .Y(n3255) );
NAND2X1TS U2601 ( .A(n1239), .B(n1238), .Y(n1241) );
NOR2X4TS U2602 ( .A(n1243), .B(n1242), .Y(n1244) );
XNOR2X4TS U2603 ( .A(n1244), .B(n1008), .Y(n2197) );
AOI21X4TS U2604 ( .A0(n1248), .A1(n1247), .B0(n1246), .Y(n1252) );
NAND2X1TS U2605 ( .A(n1250), .B(n1249), .Y(n1251) );
NAND2X1TS U2606 ( .A(n1254), .B(n1253), .Y(n3307) );
INVX2TS U2607 ( .A(n3307), .Y(n3256) );
NAND2X1TS U2608 ( .A(n1256), .B(n1255), .Y(n3257) );
INVX2TS U2609 ( .A(n3257), .Y(n1257) );
AOI21X4TS U2610 ( .A0(n1245), .A1(n3256), .B0(n1257), .Y(n1258) );
OAI21X4TS U2611 ( .A0(n3255), .A1(n1259), .B0(n1258), .Y(n3231) );
NAND2X1TS U2612 ( .A(n1263), .B(n1262), .Y(n1264) );
NAND2X1TS U2613 ( .A(n1267), .B(n1266), .Y(n1269) );
NAND2X2TS U2614 ( .A(n1270), .B(Sgf_operation_EVEN1_Q_left[0]), .Y(n3244) );
AOI21X4TS U2615 ( .A0(n3231), .A1(n1273), .B0(n1272), .Y(n3209) );
INVX2TS U2616 ( .A(n3221), .Y(n3210) );
NAND2X2TS U2617 ( .A(n1277), .B(n1276), .Y(n3211) );
INVX2TS U2618 ( .A(n3211), .Y(n1278) );
AOI21X4TS U2619 ( .A0(n540), .A1(n3210), .B0(n1278), .Y(n1279) );
OAI21X4TS U2620 ( .A0(n1280), .A1(n3209), .B0(n1279), .Y(n2287) );
INVX2TS U2621 ( .A(n1288), .Y(n1282) );
AOI21X4TS U2622 ( .A0(n1293), .A1(n1289), .B0(n1282), .Y(n1287) );
INVX2TS U2623 ( .A(n1283), .Y(n1285) );
NAND2X1TS U2624 ( .A(n1285), .B(n1284), .Y(n1286) );
XOR2X4TS U2625 ( .A(n1287), .B(n1286), .Y(n1300) );
XNOR2X4TS U2626 ( .A(n1293), .B(n1290), .Y(n1299) );
NOR2X2TS U2627 ( .A(n1299), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[4]), .Y(n2298) );
NAND2X6TS U2628 ( .A(n560), .B(n3200), .Y(n2289) );
AOI21X2TS U2629 ( .A0(n1293), .A1(n1292), .B0(n410), .Y(n1298) );
INVX2TS U2630 ( .A(n1294), .Y(n1296) );
NOR2X4TS U2631 ( .A(n1304), .B(n1303), .Y(n2290) );
NOR2X2TS U2632 ( .A(n2289), .B(n2290), .Y(n1306) );
NAND2X2TS U2633 ( .A(n1299), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[4]), .Y(n3199) );
INVX4TS U2634 ( .A(n2299), .Y(n1301) );
AOI21X4TS U2635 ( .A0(n560), .A1(n1302), .B0(n1301), .Y(n2288) );
NAND2X2TS U2636 ( .A(n1304), .B(n1303), .Y(n2291) );
OAI21X4TS U2637 ( .A0(n2288), .A1(n2290), .B0(n2291), .Y(n1305) );
AOI21X4TS U2638 ( .A0(n2287), .A1(n1306), .B0(n1305), .Y(n2341) );
OAI21X4TS U2639 ( .A0(n2352), .A1(n2349), .B0(n2353), .Y(n2360) );
NAND2X2TS U2640 ( .A(n1312), .B(n2201), .Y(n2368) );
AOI21X4TS U2641 ( .A0(n2360), .A1(n1314), .B0(n1313), .Y(n1315) );
OAI21X4TS U2642 ( .A0(n1316), .A1(n2341), .B0(n1315), .Y(n1317) );
INVX2TS U2643 ( .A(n1329), .Y(n1318) );
NOR2X2TS U2644 ( .A(n1318), .B(n1328), .Y(n1321) );
OAI2BB1X2TS U2645 ( .A0N(n1334), .A1N(n1319), .B0(n1332), .Y(n1320) );
AOI21X4TS U2646 ( .A0(n1356), .A1(n1321), .B0(n1320), .Y(n1324) );
INVX2TS U2647 ( .A(n1331), .Y(n1322) );
XOR2X4TS U2648 ( .A(n1324), .B(n1323), .Y(n1415) );
INVX2TS U2649 ( .A(n1343), .Y(n1326) );
NOR2X4TS U2650 ( .A(n1328), .B(n1331), .Y(n1335) );
NAND2X2TS U2651 ( .A(n1335), .B(n1329), .Y(n1350) );
INVX2TS U2652 ( .A(n1350), .Y(n1337) );
AOI21X4TS U2653 ( .A0(n1335), .A1(n1334), .B0(n1333), .Y(n1353) );
AOI21X4TS U2654 ( .A0(n1337), .A1(n1356), .B0(n1336), .Y(n1341) );
INVX2TS U2655 ( .A(n1352), .Y(n1339) );
NAND2X2TS U2656 ( .A(n1339), .B(n1351), .Y(n1340) );
XOR2X4TS U2657 ( .A(n1341), .B(n1340), .Y(n1416) );
INVX2TS U2658 ( .A(n1345), .Y(n1347) );
XNOR2X4TS U2659 ( .A(n1349), .B(n1348), .Y(n2223) );
NOR2X8TS U2660 ( .A(n2380), .B(n2382), .Y(n2389) );
NOR2X2TS U2661 ( .A(n1350), .B(n1352), .Y(n1355) );
OAI21X2TS U2662 ( .A0(n1353), .A1(n1352), .B0(n1351), .Y(n1354) );
AOI21X4TS U2663 ( .A0(n1356), .A1(n1355), .B0(n1354), .Y(n1361) );
ADDHX1TS U2664 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]),
.B(DP_OP_156J23_125_3370_n202), .CO(n1357), .S(n1338) );
NAND2X1TS U2665 ( .A(n1357), .B(DP_OP_153J23_122_3500_n147), .Y(n1358) );
XOR2X4TS U2666 ( .A(n1361), .B(n1360), .Y(n1417) );
XNOR2X4TS U2667 ( .A(n1407), .B(n1364), .Y(n2198) );
OAI21X4TS U2668 ( .A0(n1367), .A1(n1366), .B0(n1365), .Y(n1369) );
XNOR2X4TS U2669 ( .A(n1369), .B(n1368), .Y(n2222) );
OAI21X4TS U2670 ( .A0(n1371), .A1(n1397), .B0(n1370), .Y(n1373) );
XNOR2X4TS U2671 ( .A(n1373), .B(n1372), .Y(n2224) );
NAND2X1TS U2672 ( .A(n1473), .B(n2224), .Y(n1383) );
INVX2TS U2673 ( .A(n1394), .Y(n1376) );
AOI21X4TS U2674 ( .A0(n1377), .A1(n1395), .B0(n1376), .Y(n1382) );
INVX2TS U2675 ( .A(n1378), .Y(n1380) );
XOR2X4TS U2676 ( .A(n1382), .B(n1381), .Y(n2225) );
NAND2X1TS U2677 ( .A(n1374), .B(n1459), .Y(n1446) );
INVX2TS U2678 ( .A(n1399), .Y(n1385) );
NOR2X2TS U2679 ( .A(n1385), .B(n1384), .Y(n1388) );
INVX2TS U2680 ( .A(n1398), .Y(n1386) );
OAI21X2TS U2681 ( .A0(n1384), .A1(n1386), .B0(n1400), .Y(n1387) );
INVX2TS U2682 ( .A(n1389), .Y(n1391) );
XOR2X4TS U2683 ( .A(n1393), .B(n1392), .Y(n2215) );
NAND2X1TS U2684 ( .A(n2215), .B(n2376), .Y(n1413) );
INVX2TS U2685 ( .A(n1384), .Y(n1401) );
INVX2TS U2686 ( .A(n1404), .Y(n1405) );
AOI21X4TS U2687 ( .A0(n1407), .A1(n1406), .B0(n1405), .Y(n1412) );
INVX2TS U2688 ( .A(n1408), .Y(n1410) );
NOR2X2TS U2689 ( .A(n1413), .B(n1431), .Y(n1460) );
NAND2X1TS U2690 ( .A(n1414), .B(n1460), .Y(n1418) );
INVX2TS U2691 ( .A(n2393), .Y(n1422) );
NAND2X2TS U2692 ( .A(n1416), .B(n2223), .Y(n2383) );
OAI21X4TS U2693 ( .A0(n2382), .A1(n2399), .B0(n2383), .Y(n2388) );
AOI21X4TS U2694 ( .A0(n2388), .A1(n1420), .B0(n1419), .Y(n2394) );
XOR2X4TS U2695 ( .A(n1426), .B(n1425), .Y(n1430) );
NOR2X2TS U2696 ( .A(n3462), .B(FS_Module_state_reg[2]), .Y(n2444) );
OAI21X4TS U2697 ( .A0(n1430), .A1(n1491), .B0(n1429), .Y(n261) );
NAND2X4TS U2698 ( .A(n2389), .B(n1433), .Y(n2373) );
INVX2TS U2699 ( .A(n2373), .Y(n1435) );
XOR2X4TS U2700 ( .A(n1436), .B(n2215), .Y(n1438) );
INVX4TS U2701 ( .A(n1458), .Y(n2391) );
INVX2TS U2702 ( .A(n2390), .Y(n1439) );
AOI21X4TS U2703 ( .A0(n2388), .A1(n2391), .B0(n1439), .Y(n1478) );
AOI21X2TS U2704 ( .A0(n1441), .A1(n460), .B0(n1440), .Y(n1443) );
XOR2X4TS U2705 ( .A(n1443), .B(n2214), .Y(n1445) );
OAI21X4TS U2706 ( .A0(n1445), .A1(n1491), .B0(n1444), .Y(n254) );
INVX2TS U2707 ( .A(n1446), .Y(n1447) );
NAND2X1TS U2708 ( .A(n1460), .B(n1447), .Y(n1448) );
NAND2X2TS U2709 ( .A(n2389), .B(n1450), .Y(n1469) );
OR2X1TS U2710 ( .A(n2390), .B(n1448), .Y(n1449) );
OAI2BB1X4TS U2711 ( .A0N(n2388), .A1N(n1450), .B0(n1449), .Y(n1451) );
INVX6TS U2712 ( .A(n1451), .Y(n1470) );
NOR2X8TS U2713 ( .A(n1470), .B(DP_OP_156J23_125_3370_n293), .Y(n1452) );
XOR2X4TS U2714 ( .A(n1454), .B(n2224), .Y(n1456) );
OAI21X4TS U2715 ( .A0(n1456), .A1(n1491), .B0(n1455), .Y(n260) );
INVX2TS U2716 ( .A(n1460), .Y(n1457) );
OAI2BB1X4TS U2717 ( .A0N(n2388), .A1N(n1462), .B0(n1461), .Y(n1463) );
INVX6TS U2718 ( .A(n1463), .Y(n1486) );
NOR2X8TS U2719 ( .A(n1486), .B(DP_OP_156J23_125_3370_n295), .Y(n1464) );
XOR2X4TS U2720 ( .A(n1466), .B(n1374), .Y(n1468) );
OAI21X4TS U2721 ( .A0(n1468), .A1(n1491), .B0(n1467), .Y(n258) );
INVX2TS U2722 ( .A(n1469), .Y(n1472) );
XOR2X4TS U2723 ( .A(n1474), .B(n1473), .Y(n1476) );
OAI21X4TS U2724 ( .A0(n1476), .A1(n1491), .B0(n1475), .Y(n259) );
INVX2TS U2725 ( .A(n1477), .Y(n1480) );
XOR2X4TS U2726 ( .A(n1482), .B(n1481), .Y(n1484) );
INVX2TS U2727 ( .A(n1485), .Y(n1488) );
XOR2X4TS U2728 ( .A(n1489), .B(n1459), .Y(n1492) );
OAI21X4TS U2729 ( .A0(n1492), .A1(n1491), .B0(n1490), .Y(n257) );
ADDHX1TS U2730 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]),
.B(n1493), .CO(DP_OP_156J23_125_3370_n252), .S(n2229) );
INVX2TS U2731 ( .A(n2203), .Y(n1495) );
AOI21X4TS U2732 ( .A0(n2206), .A1(n2204), .B0(n1495), .Y(n1499) );
XOR2X4TS U2733 ( .A(n1499), .B(n1498), .Y(n2666) );
NOR2X8TS U2734 ( .A(DP_OP_158J23_127_356_n136), .B(DP_OP_158J23_127_356_n143), .Y(n1617) );
AOI21X4TS U2735 ( .A0(n1569), .A1(n587), .B0(n447), .Y(n1851) );
XNOR2X4TS U2736 ( .A(n1507), .B(n1506), .Y(n1508) );
AO21X4TS U2737 ( .A0(n1540), .A1(n1616), .B0(n1539), .Y(n1541) );
XNOR2X4TS U2738 ( .A(n1561), .B(n1560), .Y(n1952) );
OAI2BB1X4TS U2739 ( .A0N(n1575), .A1N(n405), .B0(n1608), .Y(n1600) );
AOI21X4TS U2740 ( .A0(n1600), .A1(n1578), .B0(n1577), .Y(n1579) );
OAI21X4TS U2741 ( .A0(n1615), .A1(n1580), .B0(n1579), .Y(n1584) );
XNOR2X4TS U2742 ( .A(n1584), .B(n1586), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14) );
AOI21X4TS U2743 ( .A0(n1600), .A1(n1604), .B0(n1591), .Y(n1592) );
OAI21X4TS U2744 ( .A0(n1615), .A1(n1593), .B0(n1592), .Y(n1598) );
XNOR2X4TS U2745 ( .A(n1598), .B(n1597), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13) );
OAI21X4TS U2746 ( .A0(n1615), .A1(n1602), .B0(n1601), .Y(n1606) );
XNOR2X4TS U2747 ( .A(n1606), .B(n1605), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12) );
OAI21X4TS U2748 ( .A0(n1615), .A1(n1611), .B0(n1612), .Y(n1610) );
XNOR2X4TS U2749 ( .A(n1610), .B(n1609), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11) );
AFHCINX2TS U2750 ( .CIN(n1859), .B(n1651), .A(n1652), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1),
.CO(n1649) );
AOI21X4TS U2751 ( .A0(n1738), .A1(n1780), .B0(n1737), .Y(n1779) );
AOI21X4TS U2752 ( .A0(n418), .A1(n586), .B0(n1741), .Y(n1852) );
INVX2TS U2753 ( .A(n1801), .Y(n1803) );
XNOR2X4TS U2754 ( .A(n1884), .B(n1861), .Y(n1942) );
XNOR2X4TS U2755 ( .A(n1866), .B(n530), .Y(n1977) );
NAND2X1TS U2756 ( .A(n1885), .B(n1908), .Y(n2050) );
INVX2TS U2757 ( .A(n2045), .Y(n1888) );
AOI21X4TS U2758 ( .A0(n1917), .A1(n2021), .B0(n1916), .Y(n1994) );
OAI22X4TS U2759 ( .A0(n1985), .A1(n1921), .B0(n1977), .B1(n1923), .Y(n1956)
);
OAI21X4TS U2760 ( .A0(n2012), .A1(n2017), .B0(n2013), .Y(n2003) );
INVX2TS U2761 ( .A(n2053), .Y(n2054) );
AOI21X2TS U2762 ( .A0(n2056), .A1(n2055), .B0(n2054), .Y(n2185) );
INVX2TS U2763 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]),
.Y(n2068) );
NAND2X4TS U2764 ( .A(n2063), .B(n2062), .Y(n2162) );
NAND2X2TS U2765 ( .A(n2065), .B(n2064), .Y(n2166) );
AOI21X4TS U2766 ( .A0(n2150), .A1(n2067), .B0(n2066), .Y(n2097) );
INVX2TS U2767 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]),
.Y(n2070) );
CMPR32X2TS U2768 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]),
.B(n2069), .C(n2068), .CO(n2072), .S(n2065) );
NOR2X4TS U2769 ( .A(n2073), .B(n2072), .Y(n2087) );
INVX2TS U2770 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]),
.Y(n2076) );
CMPR32X2TS U2771 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]),
.B(n2071), .C(n2070), .CO(n2074), .S(n2073) );
NOR2X4TS U2772 ( .A(n2075), .B(n2074), .Y(n2157) );
NOR2X2TS U2773 ( .A(n2087), .B(n2157), .Y(n2089) );
NAND2X4TS U2774 ( .A(n2073), .B(n2072), .Y(n2153) );
NAND2X2TS U2775 ( .A(n2075), .B(n2074), .Y(n2158) );
AOI21X4TS U2776 ( .A0(n2156), .A1(n2089), .B0(n2094), .Y(n2191) );
INVX2TS U2777 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]),
.Y(n2080) );
CMPR32X2TS U2778 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]),
.B(n2077), .C(n2076), .CO(n2078), .S(n2075) );
NAND2X2TS U2779 ( .A(n2079), .B(n2078), .Y(n2188) );
OAI21X1TS U2780 ( .A0(n2191), .A1(n2187), .B0(n2188), .Y(n2086) );
INVX2TS U2781 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]),
.Y(n2098) );
CMPR32X2TS U2782 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]),
.B(n2081), .C(n2080), .CO(n2082), .S(n2079) );
INVX2TS U2783 ( .A(n2091), .Y(n2084) );
NAND2X1TS U2784 ( .A(n2084), .B(n2090), .Y(n2085) );
XNOR2X1TS U2785 ( .A(n2086), .B(n2085), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
INVX2TS U2786 ( .A(n2087), .Y(n2155) );
NAND2X1TS U2787 ( .A(n2155), .B(n2153), .Y(n2088) );
XNOR2X1TS U2788 ( .A(n2156), .B(n2088), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
NAND2X2TS U2789 ( .A(n2089), .B(n2093), .Y(n2096) );
OAI21X1TS U2790 ( .A0(n2091), .A1(n2188), .B0(n2090), .Y(n2092) );
OAI21X4TS U2791 ( .A0(n2097), .A1(n2096), .B0(n2095), .Y(n2134) );
INVX4TS U2792 ( .A(n2134), .Y(n2144) );
INVX2TS U2793 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(
n2101) );
INVX2TS U2794 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]),
.Y(n2100) );
CMPR32X2TS U2795 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]),
.B(n2099), .C(n2098), .CO(n2102), .S(n2083) );
NOR2X4TS U2796 ( .A(n2103), .B(n2102), .Y(n2143) );
INVX2TS U2797 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]),
.Y(n2108) );
CMPR32X2TS U2798 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]),
.B(n2101), .C(n2100), .CO(n2104), .S(n2103) );
NOR2X4TS U2799 ( .A(n2105), .B(n2104), .Y(n2145) );
NOR2X4TS U2800 ( .A(n2143), .B(n2145), .Y(n2114) );
INVX2TS U2801 ( .A(n2114), .Y(n2107) );
NAND2X2TS U2802 ( .A(n2103), .B(n2102), .Y(n2142) );
NAND2X2TS U2803 ( .A(n2105), .B(n2104), .Y(n2146) );
INVX2TS U2804 ( .A(n2118), .Y(n2106) );
OAI21X1TS U2805 ( .A0(n2144), .A1(n2107), .B0(n2106), .Y(n2113) );
INVX2TS U2806 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]),
.Y(n2120) );
INVX2TS U2807 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]),
.Y(n2119) );
CMPR32X2TS U2808 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]),
.B(n2109), .C(n2108), .CO(n2110), .S(n2105) );
NAND2X1TS U2809 ( .A(n2117), .B(n2115), .Y(n2112) );
INVX2TS U2810 ( .A(n2115), .Y(n2116) );
AOI21X4TS U2811 ( .A0(n2118), .A1(n2117), .B0(n2116), .Y(n2131) );
OAI21X1TS U2812 ( .A0(n2144), .A1(n2128), .B0(n2131), .Y(n2125) );
INVX2TS U2813 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]),
.Y(n2135) );
CMPR32X2TS U2814 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]), .B(n2120), .C(n2119), .CO(n2121), .S(n2111) );
INVX2TS U2815 ( .A(n2130), .Y(n2123) );
NAND2X1TS U2816 ( .A(n2122), .B(n2121), .Y(n2129) );
NAND2X1TS U2817 ( .A(n2123), .B(n2129), .Y(n2124) );
XNOR2X1TS U2818 ( .A(n2125), .B(n2124), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
INVX2TS U2819 ( .A(n2143), .Y(n2126) );
NAND2X1TS U2820 ( .A(n2126), .B(n2142), .Y(n2127) );
XOR2X1TS U2821 ( .A(n2144), .B(n2127), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
AOI21X4TS U2822 ( .A0(n2134), .A1(n2133), .B0(n2132), .Y(n2196) );
INVX2TS U2823 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]),
.Y(n2138) );
XNOR2X1TS U2824 ( .A(n2138), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .Y(n2137) );
CMPR32X2TS U2825 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]), .B(DP_OP_153J23_122_3500_n147), .C(n2135), .CO(n2136), .S(n2122) );
OAI21X4TS U2826 ( .A0(n2196), .A1(n2192), .B0(n2193), .Y(n2173) );
INVX2TS U2827 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]),
.Y(n2174) );
XNOR2X1TS U2828 ( .A(n2174), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .Y(n2140) );
NAND2X1TS U2829 ( .A(n2172), .B(n2170), .Y(n2141) );
XNOR2X1TS U2830 ( .A(n2173), .B(n2141), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
OAI21X2TS U2831 ( .A0(n2144), .A1(n2143), .B0(n2142), .Y(n2149) );
INVX2TS U2832 ( .A(n2145), .Y(n2147) );
NAND2X1TS U2833 ( .A(n2147), .B(n2146), .Y(n2148) );
INVX4TS U2834 ( .A(n2150), .Y(n2164) );
INVX4TS U2835 ( .A(n2163), .Y(n2151) );
NAND2X4TS U2836 ( .A(n2151), .B(n2162), .Y(n2152) );
XOR2X4TS U2837 ( .A(n2164), .B(n2152), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
INVX2TS U2838 ( .A(n2153), .Y(n2154) );
INVX2TS U2839 ( .A(n2157), .Y(n2159) );
INVX2TS U2840 ( .A(n2165), .Y(n2167) );
INVX2TS U2841 ( .A(n2170), .Y(n2171) );
AOI21X4TS U2842 ( .A0(n2173), .A1(n2172), .B0(n2171), .Y(n2180) );
NOR2X1TS U2843 ( .A(n2175), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .Y(n2176) );
NOR2X2TS U2844 ( .A(n2181), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
INVX2TS U2845 ( .A(n2176), .Y(n2178) );
NAND2X1TS U2846 ( .A(n2178), .B(n2177), .Y(n2179) );
INVX2TS U2847 ( .A(n2182), .Y(n2184) );
NAND2X2TS U2848 ( .A(n2184), .B(n2183), .Y(n2186) );
INVX2TS U2849 ( .A(n2187), .Y(n2189) );
NAND2X1TS U2850 ( .A(n2189), .B(n2188), .Y(n2190) );
XOR2X1TS U2851 ( .A(n2191), .B(n2190), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
INVX2TS U2852 ( .A(n2192), .Y(n2194) );
NAND2X1TS U2853 ( .A(n2194), .B(n2193), .Y(n2195) );
XOR2X1TS U2854 ( .A(n2196), .B(n2195), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
XOR2X4TS U2855 ( .A(n2211), .B(n2210), .Y(n3306) );
INVX2TS U2856 ( .A(n2239), .Y(n2599) );
INVX2TS U2857 ( .A(n2231), .Y(n2802) );
NOR2X1TS U2858 ( .A(n2599), .B(n2802), .Y(n2242) );
INVX2TS U2859 ( .A(n2232), .Y(n2234) );
INVX2TS U2860 ( .A(n2238), .Y(n2804) );
INVX2TS U2861 ( .A(n2239), .Y(n2800) );
INVX2TS U2862 ( .A(n2240), .Y(n2803) );
OAI22X1TS U2863 ( .A0(n2806), .A1(n2804), .B0(n2800), .B1(n2803), .Y(n2241)
);
INVX2TS U2864 ( .A(n2249), .Y(n2726) );
INVX2TS U2865 ( .A(n2244), .Y(n2727) );
NOR2X1TS U2866 ( .A(n2726), .B(n2727), .Y(n2258) );
NOR2X2TS U2867 ( .A(n3412), .B(n465), .Y(n2253) );
INVX2TS U2868 ( .A(n2253), .Y(n2245) );
INVX2TS U2869 ( .A(n2248), .Y(n2729) );
INVX2TS U2870 ( .A(n2249), .Y(n2570) );
ADDHXLTS U2871 ( .A(n394), .B(Op_MX[10]), .CO(n2250), .S(n2248) );
INVX2TS U2872 ( .A(n2250), .Y(n2728) );
OAI22X1TS U2873 ( .A0(n2733), .A1(n2729), .B0(n2570), .B1(n2728), .Y(n2257)
);
OAI21X2TS U2874 ( .A0(n2253), .A1(n2252), .B0(n2251), .Y(n2328) );
INVX2TS U2875 ( .A(n2328), .Y(n2259) );
NOR2X2TS U2876 ( .A(n3356), .B(n467), .Y(n2323) );
INVX2TS U2877 ( .A(n2323), .Y(n2254) );
NAND2X2TS U2878 ( .A(n3356), .B(n467), .Y(n2325) );
INVX2TS U2879 ( .A(n2255), .Y(n2731) );
INVX2TS U2880 ( .A(n2256), .Y(n2730) );
OAI22X1TS U2881 ( .A0(n478), .A1(n2731), .B0(n508), .B1(n2730), .Y(n2267) );
NOR2X2TS U2882 ( .A(n2834), .B(n468), .Y(n2326) );
INVX2TS U2883 ( .A(n2326), .Y(n2260) );
CLKXOR2X4TS U2884 ( .A(n2262), .B(n2261), .Y(n2739) );
INVX2TS U2885 ( .A(n2263), .Y(n2734) );
INVX2TS U2886 ( .A(n2264), .Y(n2732) );
OAI22X1TS U2887 ( .A0(n2739), .A1(n2734), .B0(n479), .B1(n2732), .Y(n2265)
);
INVX2TS U2888 ( .A(n2268), .Y(n2801) );
OAI22X1TS U2889 ( .A0(n2806), .A1(n2802), .B0(n2599), .B1(n2801), .Y(n2272)
);
INVX2TS U2890 ( .A(n2269), .Y(n2276) );
INVX2TS U2891 ( .A(n2275), .Y(n2270) );
NAND2X1TS U2892 ( .A(n2270), .B(n2274), .Y(n2271) );
OAI22X1TS U2893 ( .A0(n481), .A1(n2804), .B0(n507), .B1(n2803), .Y(n2286) );
ADDHXLTS U2894 ( .A(n2273), .B(n2272), .CO(DP_OP_157J23_126_5719_n132), .S(
n2285) );
INVX2TS U2895 ( .A(n2277), .Y(n2279) );
CLKXOR2X4TS U2896 ( .A(n2281), .B(n2280), .Y(n2812) );
INVX2TS U2897 ( .A(n2282), .Y(n2807) );
INVX2TS U2898 ( .A(n2283), .Y(n2805) );
OAI22X1TS U2899 ( .A0(n2812), .A1(n2807), .B0(n481), .B1(n2805), .Y(n2284)
);
OAI21X1TS U2900 ( .A0(n3202), .A1(n2289), .B0(n2288), .Y(n2294) );
INVX2TS U2901 ( .A(n2290), .Y(n2292) );
NAND2X1TS U2902 ( .A(n2292), .B(n2291), .Y(n2293) );
NOR2X1TS U2903 ( .A(n2570), .B(n2729), .Y(n2297) );
OAI22X1TS U2904 ( .A0(n2733), .A1(n2731), .B0(n2726), .B1(n2730), .Y(n2296)
);
OAI21X1TS U2905 ( .A0(n3202), .A1(n2298), .B0(n3199), .Y(n2301) );
NAND2X1TS U2906 ( .A(n560), .B(n2299), .Y(n2300) );
XNOR2X1TS U2907 ( .A(n2301), .B(n2300), .Y(n2302) );
NOR4X1TS U2908 ( .A(P_Sgf[13]), .B(P_Sgf[17]), .C(P_Sgf[15]), .D(P_Sgf[16]),
.Y(n2308) );
NOR4X1TS U2909 ( .A(P_Sgf[20]), .B(P_Sgf[21]), .C(P_Sgf[18]), .D(P_Sgf[19]),
.Y(n2307) );
NOR4X1TS U2910 ( .A(P_Sgf[1]), .B(P_Sgf[5]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n2305) );
NOR3XLTS U2911 ( .A(P_Sgf[22]), .B(P_Sgf[0]), .C(P_Sgf[2]), .Y(n2304) );
AND4X1TS U2912 ( .A(n2305), .B(n2304), .C(n2303), .D(n453), .Y(n2306) );
XOR2X1TS U2913 ( .A(Op_MY[31]), .B(Op_MX[31]), .Y(n2449) );
MXI2X1TS U2914 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n2449), .Y(n2309)
);
OAI211X1TS U2915 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n2310), .C0(
n2309), .Y(n2622) );
OAI31X1TS U2916 ( .A0(n2453), .A1(n2620), .A2(n2622), .B0(n3423), .Y(n214)
);
INVX2TS U2917 ( .A(n2311), .Y(n2313) );
NAND2X1TS U2918 ( .A(n2313), .B(n2312), .Y(n2314) );
OAI22X1TS U2919 ( .A0(n482), .A1(n498), .B0(n2812), .B1(n566), .Y(n2318) );
OAI22X1TS U2920 ( .A0(n2812), .A1(Op_MX[17]), .B0(n480), .B1(n566), .Y(n2437) );
INVX2TS U2921 ( .A(n431), .Y(n2832) );
INVX2TS U2922 ( .A(n585), .Y(n2828) );
INVX2TS U2923 ( .A(n2316), .Y(n2808) );
CMPR32X2TS U2924 ( .A(n2319), .B(n2318), .C(n2317), .CO(
DP_OP_157J23_126_5719_n106), .S(DP_OP_157J23_126_5719_n107) );
NOR2X1TS U2925 ( .A(n3403), .B(n571), .Y(intadd_56_CI) );
NOR2X1TS U2926 ( .A(n425), .B(n3409), .Y(intadd_55_CI) );
OAI21X1TS U2927 ( .A0(n2873), .A1(n2321), .B0(n2876), .Y(n2322) );
OAI2BB1X1TS U2928 ( .A0N(intadd_57_n1), .A1N(n2322), .B0(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11),
.Y(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
NOR2X1TS U2929 ( .A(n2323), .B(n2326), .Y(n2329) );
OAI21X1TS U2930 ( .A0(n2326), .A1(n2325), .B0(n2324), .Y(n2327) );
AOI21X2TS U2931 ( .A0(n2329), .A1(n2328), .B0(n2327), .Y(n2427) );
NOR2X2TS U2932 ( .A(n3351), .B(n3355), .Y(n2426) );
NOR2X2TS U2933 ( .A(n3352), .B(Op_MY[5]), .Y(n2428) );
NOR2X1TS U2934 ( .A(n473), .B(n2732), .Y(n2340) );
INVX2TS U2935 ( .A(n2426), .Y(n2333) );
NAND2X1TS U2936 ( .A(n2333), .B(n2425), .Y(n2334) );
XOR2X1TS U2937 ( .A(n2427), .B(n2334), .Y(n2335) );
INVX2TS U2938 ( .A(n2336), .Y(n2725) );
OAI22X1TS U2939 ( .A0(n2741), .A1(n2727), .B0(n2739), .B1(n2725), .Y(n2339)
);
OAI22X1TS U2940 ( .A0(n2739), .A1(n2727), .B0(n478), .B1(n2725), .Y(n2424)
);
INVX2TS U2941 ( .A(n2337), .Y(n2735) );
CMPR32X2TS U2942 ( .A(n2340), .B(n2339), .C(n2338), .CO(
DP_OP_159J23_128_5719_n106), .S(DP_OP_159J23_128_5719_n107) );
INVX2TS U2943 ( .A(n2342), .Y(n2351) );
NAND2X1TS U2944 ( .A(n2351), .B(n2349), .Y(n2343) );
XNOR2X1TS U2945 ( .A(n2365), .B(n2343), .Y(n2344) );
AOI21X1TS U2946 ( .A0(n2365), .A1(n2358), .B0(n2360), .Y(n2347) );
INVX2TS U2947 ( .A(n2362), .Y(n2345) );
NAND2X1TS U2948 ( .A(n2345), .B(n2361), .Y(n2346) );
XOR2X4TS U2949 ( .A(n2347), .B(n2346), .Y(n2348) );
INVX2TS U2950 ( .A(n2349), .Y(n2350) );
AOI21X1TS U2951 ( .A0(n2365), .A1(n2351), .B0(n2350), .Y(n2356) );
INVX2TS U2952 ( .A(n2352), .Y(n2354) );
NAND2X1TS U2953 ( .A(n2354), .B(n2353), .Y(n2355) );
XOR2X4TS U2954 ( .A(n2356), .B(n2355), .Y(n2357) );
INVX2TS U2955 ( .A(n2358), .Y(n2359) );
NOR2X1TS U2956 ( .A(n2359), .B(n2362), .Y(n2366) );
AOI21X2TS U2957 ( .A0(n2366), .A1(n2365), .B0(n2364), .Y(n2371) );
INVX2TS U2958 ( .A(n2367), .Y(n2369) );
NAND2X1TS U2959 ( .A(n2369), .B(n2368), .Y(n2370) );
AOI2BB2X4TS U2960 ( .B0(n2375), .B1(n460), .A0N(n2374), .A1N(
DP_OP_156J23_125_3370_n297), .Y(n2378) );
XOR2X4TS U2961 ( .A(n2378), .B(n2377), .Y(n2379) );
INVX2TS U2962 ( .A(n2380), .Y(n2400) );
INVX2TS U2963 ( .A(n2399), .Y(n2381) );
INVX2TS U2964 ( .A(n2382), .Y(n2384) );
NAND2X1TS U2965 ( .A(n2384), .B(n2383), .Y(n2385) );
XOR2X4TS U2966 ( .A(n2386), .B(n2385), .Y(n2387) );
MX2X4TS U2967 ( .A(P_Sgf[37]), .B(n2392), .S0(n2665), .Y(n252) );
XOR2X4TS U2968 ( .A(n2397), .B(DP_OP_156J23_125_3370_n290), .Y(n2398) );
MX2X4TS U2969 ( .A(P_Sgf[47]), .B(n2398), .S0(n520), .Y(n380) );
INVX2TS U2970 ( .A(n391), .Y(n2655) );
NOR2X1TS U2971 ( .A(n2655), .B(n435), .Y(intadd_54_CI) );
NOR2X1TS U2972 ( .A(n432), .B(n2648), .Y(intadd_57_B_0_) );
NAND2X1TS U2973 ( .A(n2400), .B(n2399), .Y(n2401) );
NOR2XLTS U2974 ( .A(FS_Module_state_reg[0]), .B(n2453), .Y(n2404) );
CLKBUFX2TS U2975 ( .A(n2441), .Y(n2405) );
BUFX3TS U2976 ( .A(n3451), .Y(n3448) );
INVX2TS U2977 ( .A(rst), .Y(n3463) );
BUFX3TS U2978 ( .A(n3463), .Y(n3438) );
BUFX3TS U2979 ( .A(n3450), .Y(n3455) );
BUFX3TS U2980 ( .A(n3450), .Y(n3454) );
BUFX3TS U2981 ( .A(n2405), .Y(n3449) );
BUFX3TS U2982 ( .A(n3463), .Y(n3436) );
BUFX3TS U2983 ( .A(n3463), .Y(n3435) );
BUFX3TS U2984 ( .A(n3463), .Y(n3439) );
BUFX3TS U2985 ( .A(n3451), .Y(n3442) );
BUFX3TS U2986 ( .A(n3450), .Y(n3443) );
BUFX3TS U2987 ( .A(n2405), .Y(n3444) );
BUFX3TS U2988 ( .A(n2405), .Y(n3441) );
BUFX3TS U2989 ( .A(n3451), .Y(n3446) );
CLKBUFX2TS U2990 ( .A(n3451), .Y(n3456) );
BUFX3TS U2991 ( .A(n3463), .Y(n3437) );
BUFX3TS U2992 ( .A(n2441), .Y(n3440) );
BUFX3TS U2993 ( .A(n3171), .Y(n3163) );
AOI22X1TS U2994 ( .A0(n486), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n3163), .Y(n2412) );
OAI2BB1X1TS U2995 ( .A0N(n524), .A1N(P_Sgf[24]), .B0(n2412), .Y(n2413) );
AOI21X1TS U2996 ( .A0(n521), .A1(Add_result[0]), .B0(n2413), .Y(n2414) );
OAI2BB1X1TS U2997 ( .A0N(P_Sgf[23]), .A1N(n501), .B0(n2414), .Y(n191) );
INVX2TS U2998 ( .A(n3392), .Y(n3400) );
AO22X1TS U2999 ( .A0(Sgf_normalized_result[20]), .A1(n3400), .B0(
final_result_ieee[20]), .B1(n3399), .Y(n170) );
AO22X1TS U3000 ( .A0(Sgf_normalized_result[22]), .A1(n3400), .B0(
final_result_ieee[22]), .B1(n3397), .Y(n167) );
NOR2X1TS U3001 ( .A(n549), .B(n571), .Y(n3458) );
NAND2X1TS U3002 ( .A(Op_MX[1]), .B(n411), .Y(n3064) );
NOR2BX1TS U3003 ( .AN(n3458), .B(n3064), .Y(intadd_56_B_0_) );
NAND2X1TS U3004 ( .A(n3368), .B(Op_MY[5]), .Y(n3032) );
NAND2X1TS U3005 ( .A(n3370), .B(n469), .Y(n3033) );
NAND2X1TS U3006 ( .A(n394), .B(n3355), .Y(n3031) );
NAND2X1TS U3007 ( .A(n3355), .B(n3370), .Y(n3070) );
XNOR2X1TS U3008 ( .A(n3067), .B(n3070), .Y(n2416) );
XOR2X1TS U3009 ( .A(n3066), .B(n2416), .Y(intadd_56_B_7_) );
NOR2X1TS U3010 ( .A(n584), .B(n435), .Y(n3460) );
NAND2X1TS U3011 ( .A(n2832), .B(n412), .Y(n2943) );
NOR2BX1TS U3012 ( .AN(n3460), .B(n2943), .Y(intadd_54_B_0_) );
NAND2X1TS U3013 ( .A(Op_MY[15]), .B(n498), .Y(n2911) );
NAND2X1TS U3014 ( .A(n3378), .B(n600), .Y(n2912) );
NAND2X1TS U3015 ( .A(n3379), .B(Op_MY[16]), .Y(n2910) );
NAND2X1TS U3016 ( .A(Op_MY[16]), .B(n498), .Y(n2949) );
XNOR2X1TS U3017 ( .A(n2946), .B(n2949), .Y(n2418) );
XOR2X1TS U3018 ( .A(n2945), .B(n2418), .Y(intadd_54_B_7_) );
NOR2X1TS U3019 ( .A(n562), .B(n3409), .Y(n3459) );
NAND2X1TS U3020 ( .A(n458), .B(n3412), .Y(n2991) );
NOR2BX1TS U3021 ( .AN(n3459), .B(n2991), .Y(intadd_55_B_0_) );
NAND2X1TS U3022 ( .A(n2833), .B(n461), .Y(n2534) );
NAND2X1TS U3023 ( .A(n3367), .B(Op_MY[9]), .Y(n2535) );
NAND2X1TS U3024 ( .A(Op_MX[10]), .B(n3351), .Y(n2533) );
NAND2X1TS U3025 ( .A(n3367), .B(n423), .Y(n2997) );
XNOR2X1TS U3026 ( .A(n2994), .B(n2997), .Y(n2420) );
XOR2X1TS U3027 ( .A(n2993), .B(n2420), .Y(intadd_55_B_7_) );
NOR2X2TS U3028 ( .A(n2421), .B(n2453), .Y(n2422) );
OAI22X1TS U3029 ( .A0(n2741), .A1(n2729), .B0(n2739), .B1(n2728), .Y(n2435)
);
ADDHX1TS U3030 ( .A(n2424), .B(n2423), .CO(n2338), .S(n2434) );
INVX2TS U3031 ( .A(n2428), .Y(n2430) );
NAND2X1TS U3032 ( .A(n2430), .B(n2429), .Y(n2431) );
OAI22X1TS U3033 ( .A0(n2737), .A1(n2731), .B0(n484), .B1(n2730), .Y(n2433)
);
OAI22X1TS U3034 ( .A0(n482), .A1(n2802), .B0(n2812), .B1(n2801), .Y(n2440)
);
ADDHX1TS U3035 ( .A(n2437), .B(n2436), .CO(n2317), .S(n2439) );
OAI22X1TS U3036 ( .A0(n2810), .A1(n2804), .B0(n483), .B1(n2803), .Y(n2438)
);
BUFX3TS U3037 ( .A(n2441), .Y(n3450) );
BUFX3TS U3038 ( .A(n2441), .Y(n3451) );
BUFX3TS U3039 ( .A(n3456), .Y(n3452) );
BUFX3TS U3040 ( .A(n3456), .Y(n3445) );
BUFX3TS U3041 ( .A(n3456), .Y(n3453) );
BUFX3TS U3042 ( .A(n3456), .Y(n3447) );
NAND2X2TS U3043 ( .A(n2828), .B(n3404), .Y(n2872) );
INVX2TS U3044 ( .A(n2872), .Y(n2842) );
AOI22X1TS U3045 ( .A0(Op_MX[19]), .A1(n413), .B0(Op_MX[18]), .B1(n3404), .Y(
n2442) );
INVX2TS U3046 ( .A(n2443), .Y(n2740) );
INVX2TS U3047 ( .A(n3389), .Y(n3349) );
INVX2TS U3048 ( .A(n3136), .Y(n3241) );
NAND2X1TS U3049 ( .A(Add_result[0]), .B(n3241), .Y(n2447) );
OAI32X1TS U3050 ( .A0(n3399), .A1(n2450), .A2(overflow_flag), .B0(n3391),
.B1(n3433), .Y(n262) );
NAND2X1TS U3051 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n2621) );
NOR3X1TS U3052 ( .A(n2453), .B(FS_Module_state_reg[0]), .C(n2621), .Y(ready)
);
INVX2TS U3053 ( .A(ready), .Y(n2451) );
AOI32X1TS U3054 ( .A0(n2453), .A1(n3407), .A2(FS_Module_state_reg[0]), .B0(
FS_Module_state_reg[2]), .B1(n3267), .Y(n2452) );
INVX2TS U3055 ( .A(n506), .Y(n3344) );
NAND2X1TS U3056 ( .A(Op_MX[1]), .B(n469), .Y(n3054) );
NAND2X1TS U3057 ( .A(n3369), .B(n467), .Y(n3065) );
NAND2X1TS U3058 ( .A(Op_MX[1]), .B(Op_MY[2]), .Y(n3089) );
NAND2X1TS U3059 ( .A(n3369), .B(n411), .Y(n3093) );
INVX2TS U3060 ( .A(n3090), .Y(n2455) );
NAND2X2TS U3061 ( .A(n394), .B(n411), .Y(n2634) );
NAND2X1TS U3062 ( .A(n3370), .B(Op_MY[0]), .Y(n2633) );
NOR2X2TS U3063 ( .A(n2634), .B(n2633), .Y(n3037) );
NAND2X1TS U3064 ( .A(Op_MX[2]), .B(n468), .Y(n2631) );
INVX2TS U3065 ( .A(n2631), .Y(n2458) );
NAND2X1TS U3066 ( .A(n3368), .B(n467), .Y(n2630) );
INVX2TS U3067 ( .A(n2630), .Y(n2457) );
NAND2X1TS U3068 ( .A(n3369), .B(Op_MY[5]), .Y(n2629) );
AOI21X1TS U3069 ( .A0(n2630), .A1(n2631), .B0(n2629), .Y(n2456) );
INVX2TS U3070 ( .A(n3039), .Y(n2462) );
INVX2TS U3071 ( .A(n3037), .Y(n2459) );
NAND2X1TS U3072 ( .A(n3039), .B(n2459), .Y(n2461) );
NOR2X2TS U3073 ( .A(n2634), .B(n3023), .Y(n3026) );
AOI22X1TS U3074 ( .A0(n411), .A1(n3370), .B0(n394), .B1(n467), .Y(n2460) );
NOR2X1TS U3075 ( .A(n3026), .B(n2460), .Y(n3038) );
NAND2X1TS U3076 ( .A(n469), .B(n394), .Y(n3022) );
NAND2X1TS U3077 ( .A(Op_MY[5]), .B(Op_MX[2]), .Y(n3021) );
XNOR2X1TS U3078 ( .A(n3022), .B(n3021), .Y(n2463) );
CLKXOR2X2TS U3079 ( .A(n2463), .B(n3023), .Y(n3076) );
INVX2TS U3080 ( .A(n3076), .Y(n2468) );
INVX2TS U3081 ( .A(n3077), .Y(n2466) );
NAND2X1TS U3082 ( .A(Op_MX[2]), .B(n3355), .Y(n3043) );
NAND2X1TS U3083 ( .A(n3368), .B(n469), .Y(n3042) );
NAND2X1TS U3084 ( .A(Op_MX[1]), .B(Op_MY[5]), .Y(n3041) );
AOI21X1TS U3085 ( .A0(n3042), .A1(n3043), .B0(n3041), .Y(n2464) );
AOI2BB1X1TS U3086 ( .A0N(n3043), .A1N(n3042), .B0(n2464), .Y(n3030) );
NAND2X1TS U3087 ( .A(n3368), .B(n3355), .Y(n3028) );
XOR2X1TS U3088 ( .A(n3026), .B(n3028), .Y(n2465) );
XOR2X1TS U3089 ( .A(n3030), .B(n2465), .Y(n3078) );
NAND2X1TS U3090 ( .A(Op_MX[13]), .B(Op_MY[15]), .Y(n2933) );
NAND2X1TS U3091 ( .A(n419), .B(n466), .Y(n2944) );
NAND2X1TS U3092 ( .A(n2832), .B(Op_MY[14]), .Y(n2968) );
NAND2X1TS U3093 ( .A(n419), .B(n412), .Y(n2972) );
NOR2X2TS U3094 ( .A(n2968), .B(n2972), .Y(n2969) );
INVX2TS U3095 ( .A(n2969), .Y(n2469) );
OAI21X1TS U3096 ( .A0(n2933), .A1(n2944), .B0(n2469), .Y(intadd_54_B_2_) );
NAND2X2TS U3097 ( .A(n3379), .B(n412), .Y(n2645) );
NAND2X1TS U3098 ( .A(n3362), .B(Op_MX[17]), .Y(n2644) );
NOR2X2TS U3099 ( .A(n2645), .B(n2644), .Y(n2916) );
NAND2X1TS U3100 ( .A(n391), .B(Op_MY[15]), .Y(n2642) );
INVX2TS U3101 ( .A(n2642), .Y(n2472) );
NAND2X1TS U3102 ( .A(n3378), .B(n466), .Y(n2641) );
INVX2TS U3103 ( .A(n2641), .Y(n2471) );
NAND2X1TS U3104 ( .A(n419), .B(n600), .Y(n2640) );
AOI21X1TS U3105 ( .A0(n2641), .A1(n2642), .B0(n2640), .Y(n2470) );
INVX2TS U3106 ( .A(n2918), .Y(n2476) );
INVX2TS U3107 ( .A(n2916), .Y(n2473) );
NAND2X1TS U3108 ( .A(n2918), .B(n2473), .Y(n2475) );
NOR2X2TS U3109 ( .A(n2645), .B(n2902), .Y(n2905) );
AOI22X1TS U3110 ( .A0(n3379), .A1(n466), .B0(n412), .B1(Op_MX[17]), .Y(n2474) );
NOR2X1TS U3111 ( .A(n2905), .B(n2474), .Y(n2917) );
NAND2X1TS U3112 ( .A(Op_MY[15]), .B(n3379), .Y(n2901) );
NAND2X1TS U3113 ( .A(n600), .B(n391), .Y(n2900) );
XNOR2X1TS U3114 ( .A(n2901), .B(n2900), .Y(n2477) );
CLKXOR2X2TS U3115 ( .A(n2477), .B(n2902), .Y(n2955) );
INVX2TS U3116 ( .A(n2955), .Y(n2482) );
INVX2TS U3117 ( .A(n2956), .Y(n2480) );
NAND2X1TS U3118 ( .A(n391), .B(Op_MY[16]), .Y(n2922) );
NAND2X1TS U3119 ( .A(n3378), .B(Op_MY[15]), .Y(n2921) );
NAND2X1TS U3120 ( .A(Op_MX[13]), .B(n600), .Y(n2920) );
AOI21X1TS U3121 ( .A0(n2921), .A1(n2922), .B0(n2920), .Y(n2478) );
AOI2BB1X1TS U3122 ( .A0N(n2922), .A1N(n2921), .B0(n2478), .Y(n2909) );
NAND2X1TS U3123 ( .A(n3378), .B(Op_MY[16]), .Y(n2907) );
XOR2X1TS U3124 ( .A(n2905), .B(n2907), .Y(n2479) );
XOR2X1TS U3125 ( .A(n2909), .B(n2479), .Y(n2957) );
OAI21X1TS U3126 ( .A0(n2956), .A1(n2482), .B0(n2481), .Y(mult_x_59_n17) );
NAND2X1TS U3127 ( .A(n461), .B(n3412), .Y(n2488) );
INVX2TS U3128 ( .A(n2488), .Y(n2483) );
NAND2X1TS U3129 ( .A(intadd_55_CI), .B(n2483), .Y(n2987) );
INVX2TS U3130 ( .A(n2987), .Y(n2485) );
NOR2X1TS U3131 ( .A(n3409), .B(n3402), .Y(n2487) );
AOI21X1TS U3132 ( .A0(n3412), .A1(n3372), .B0(n2487), .Y(n2484) );
NAND2X1TS U3133 ( .A(n458), .B(Op_MY[9]), .Y(n2498) );
NAND2X1TS U3134 ( .A(n3371), .B(n420), .Y(n2992) );
NAND2X1TS U3135 ( .A(n3371), .B(n3412), .Y(n3020) );
NAND2X1TS U3136 ( .A(Op_MX[7]), .B(n420), .Y(n3016) );
INVX2TS U3137 ( .A(n3017), .Y(n2486) );
OAI21X1TS U3138 ( .A0(n2498), .A1(n2992), .B0(n2486), .Y(intadd_55_B_2_) );
NOR2X2TS U3139 ( .A(n577), .B(n3414), .Y(n2508) );
NAND2X1TS U3140 ( .A(n2508), .B(n2487), .Y(n2979) );
NAND2X1TS U3141 ( .A(n2979), .B(n2489), .Y(n2988) );
XOR2X1TS U3142 ( .A(n2494), .B(n2498), .Y(n2490) );
XOR2X1TS U3143 ( .A(n2490), .B(n2495), .Y(n2990) );
NAND2X1TS U3144 ( .A(n3372), .B(Op_MY[9]), .Y(n2503) );
NAND2X1TS U3145 ( .A(n3371), .B(n3352), .Y(n2502) );
XNOR2X1TS U3146 ( .A(n2503), .B(n2502), .Y(n2492) );
NAND2X1TS U3147 ( .A(n461), .B(n420), .Y(n2504) );
INVX2TS U3148 ( .A(n2504), .Y(n2506) );
CLKXOR2X2TS U3149 ( .A(n2492), .B(n2506), .Y(n3012) );
NOR2X1TS U3150 ( .A(n3409), .B(n574), .Y(n2493) );
NAND2X2TS U3151 ( .A(n2508), .B(n2493), .Y(n2981) );
NAND2X1TS U3152 ( .A(n458), .B(n3351), .Y(n2980) );
XOR2X1TS U3153 ( .A(n2980), .B(n2979), .Y(n2500) );
INVX2TS U3154 ( .A(n2494), .Y(n2497) );
INVX2TS U3155 ( .A(n2495), .Y(n2496) );
OAI22X1TS U3156 ( .A0(n2499), .A1(n2498), .B0(n2497), .B1(n2496), .Y(n2977)
);
XNOR2X1TS U3157 ( .A(n2500), .B(n2977), .Y(n3013) );
OAI21X1TS U3158 ( .A0(n3012), .A1(n3011), .B0(n2501), .Y(mult_x_58_n29) );
INVX2TS U3159 ( .A(n2503), .Y(n2507) );
AOI21X1TS U3160 ( .A0(n2504), .A1(n2503), .B0(n2502), .Y(n2505) );
NAND2X1TS U3161 ( .A(n2983), .B(n2981), .Y(n2513) );
INVX2TS U3162 ( .A(n2508), .Y(n2509) );
NOR2X2TS U3163 ( .A(n2509), .B(n2530), .Y(n2525) );
AOI22X1TS U3164 ( .A0(n3412), .A1(n3367), .B0(n420), .B1(Op_MX[10]), .Y(
n2510) );
NOR2X1TS U3165 ( .A(n2525), .B(n2510), .Y(n2982) );
INVX2TS U3166 ( .A(n2983), .Y(n2512) );
INVX2TS U3167 ( .A(n2981), .Y(n2511) );
AOI22X2TS U3168 ( .A0(n2513), .A1(n2982), .B0(n2512), .B1(n2511), .Y(n3004)
);
NAND2X1TS U3169 ( .A(Op_MX[10]), .B(Op_MY[9]), .Y(n2529) );
NAND2X1TS U3170 ( .A(n3352), .B(n3372), .Y(n2528) );
XNOR2X1TS U3171 ( .A(n2529), .B(n2528), .Y(n2514) );
CLKXOR2X2TS U3172 ( .A(n2514), .B(n2530), .Y(n3003) );
INVX2TS U3173 ( .A(n3003), .Y(n2521) );
INVX2TS U3174 ( .A(n3004), .Y(n2519) );
NAND2X1TS U3175 ( .A(n458), .B(n3352), .Y(n2973) );
INVX2TS U3176 ( .A(n2975), .Y(n2516) );
INVX2TS U3177 ( .A(n2974), .Y(n2515) );
OAI22X1TS U3178 ( .A0(n2517), .A1(n2973), .B0(n2516), .B1(n2515), .Y(n2527)
);
NAND2X1TS U3179 ( .A(n461), .B(n3351), .Y(n2523) );
XOR2X1TS U3180 ( .A(n2525), .B(n2523), .Y(n2518) );
XNOR2X1TS U3181 ( .A(n2527), .B(n2518), .Y(n3005) );
OAI21X1TS U3182 ( .A0(n3004), .A1(n2521), .B0(n2520), .Y(mult_x_58_n17) );
NAND2X1TS U3183 ( .A(n2522), .B(n2523), .Y(n2526) );
INVX2TS U3184 ( .A(n2523), .Y(n2524) );
AOI21X1TS U3185 ( .A0(n2530), .A1(n2529), .B0(n2528), .Y(n2532) );
XOR2X1TS U3186 ( .A(n2534), .B(n2533), .Y(n2536) );
XOR2X1TS U3187 ( .A(n2536), .B(n2535), .Y(n3001) );
NOR2X1TS U3188 ( .A(n476), .B(n2803), .Y(DP_OP_157J23_126_5719_n161) );
NOR2X1TS U3189 ( .A(n2872), .B(n438), .Y(n2538) );
OAI21X1TS U3190 ( .A0(n2538), .A1(n513), .B0(Op_MX[18]), .Y(n2896) );
NAND2X1TS U3191 ( .A(Op_MX[19]), .B(n404), .Y(n2898) );
NAND2X1TS U3192 ( .A(n477), .B(n3404), .Y(n2540) );
NAND2X1TS U3193 ( .A(n413), .B(n488), .Y(n2539) );
NAND2X1TS U3194 ( .A(n413), .B(n477), .Y(n2647) );
NOR2X2TS U3195 ( .A(n2845), .B(n2647), .Y(n2858) );
INVX2TS U3196 ( .A(n2868), .Y(n2545) );
INVX2TS U3197 ( .A(n2540), .Y(n2541) );
NAND2X1TS U3198 ( .A(intadd_57_B_0_), .B(n2541), .Y(n2867) );
NAND2X1TS U3199 ( .A(n513), .B(Op_MX[19]), .Y(n2548) );
XNOR2X1TS U3200 ( .A(n2549), .B(n2548), .Y(n2542) );
XOR2X1TS U3201 ( .A(n2542), .B(n2558), .Y(n2869) );
OAI21X1TS U3202 ( .A0(n2545), .A1(n2867), .B0(n2544), .Y(mult_x_56_n36) );
NAND2X1TS U3203 ( .A(n477), .B(n404), .Y(n2844) );
NAND2X1TS U3204 ( .A(n3353), .B(Op_MX[19]), .Y(n2843) );
XOR2X1TS U3205 ( .A(n2844), .B(n2843), .Y(n2546) );
CLKXOR2X2TS U3206 ( .A(n2546), .B(n2845), .Y(n2893) );
INVX2TS U3207 ( .A(n3461), .Y(n2547) );
INVX2TS U3208 ( .A(n2549), .Y(n2551) );
AOI21X1TS U3209 ( .A0(n2558), .A1(n2549), .B0(n2548), .Y(n2550) );
AOI21X1TS U3210 ( .A0(n2551), .A1(n2555), .B0(n2550), .Y(n2854) );
NAND2X1TS U3211 ( .A(n3380), .B(n513), .Y(n2855) );
XOR2X1TS U3212 ( .A(n2858), .B(n2855), .Y(n2552) );
XOR2X1TS U3213 ( .A(n2854), .B(n2552), .Y(n2894) );
OAI2BB1X1TS U3214 ( .A0N(n2892), .A1N(n2893), .B0(n2894), .Y(n2553) );
NAND2X1TS U3215 ( .A(n488), .B(n390), .Y(n2557) );
NOR2X1TS U3216 ( .A(n2557), .B(n2554), .Y(n2559) );
XNOR2X1TS U3217 ( .A(n3380), .B(n404), .Y(n2556) );
AOI22X1TS U3218 ( .A0(n2559), .A1(n2558), .B0(n2557), .B1(n2556), .Y(n2851)
);
NAND2X1TS U3219 ( .A(n3353), .B(n477), .Y(n2849) );
ACHCINX2TS U3220 ( .CIN(n2851), .A(n2849), .B(n2872), .CO(n2880) );
CLKXOR2X2TS U3221 ( .A(n513), .B(n477), .Y(n2878) );
INVX2TS U3222 ( .A(n2878), .Y(n2877) );
NOR2X1TS U3223 ( .A(n474), .B(n2730), .Y(DP_OP_159J23_128_5719_n161) );
NOR2X1TS U3224 ( .A(n475), .B(n2811), .Y(DP_OP_157J23_126_5719_n185) );
INVX2TS U3225 ( .A(n2561), .Y(n2738) );
NOR2X1TS U3226 ( .A(n473), .B(n2738), .Y(DP_OP_159J23_128_5719_n185) );
OAI22X1TS U3227 ( .A0(n2733), .A1(n2734), .B0(n2570), .B1(n2732), .Y(n2563)
);
NOR2X2TS U3228 ( .A(DP_OP_159J23_128_5719_n117), .B(
DP_OP_159J23_128_5719_n122), .Y(n2698) );
NOR2X1TS U3229 ( .A(n2693), .B(n2698), .Y(n2579) );
INVX2TS U3230 ( .A(n2562), .Y(n2736) );
OAI22X1TS U3231 ( .A0(n479), .A1(n2736), .B0(n508), .B1(n2735), .Y(n2567) );
NOR2X1TS U3232 ( .A(n2570), .B(n2734), .Y(n2569) );
OAI22X1TS U3233 ( .A0(n2733), .A1(n2736), .B0(n2726), .B1(n2735), .Y(n2568)
);
ADDHXLTS U3234 ( .A(n2564), .B(n2563), .CO(DP_OP_159J23_128_5719_n141), .S(
n2565) );
NOR2X1TS U3235 ( .A(DP_OP_159J23_128_5719_n136), .B(n2576), .Y(n2711) );
CMPR32X2TS U3236 ( .A(n2567), .B(n2566), .C(n2565), .CO(n2576), .S(n2575) );
OAI22X1TS U3237 ( .A0(n2739), .A1(n2740), .B0(n479), .B1(n2738), .Y(n2574)
);
NOR2X1TS U3238 ( .A(n2575), .B(n2574), .Y(n2716) );
ADDHX1TS U3239 ( .A(n2569), .B(n2568), .CO(n2566), .S(n2572) );
OAI22X1TS U3240 ( .A0(n478), .A1(n2740), .B0(n508), .B1(n2738), .Y(n2571) );
OAI22X1TS U3241 ( .A0(n2733), .A1(n2740), .B0(n2570), .B1(n2738), .Y(n2658)
);
NOR2X1TS U3242 ( .A(n2726), .B(n2736), .Y(n2657) );
NAND2X1TS U3243 ( .A(n2658), .B(n2657), .Y(n2659) );
INVX2TS U3244 ( .A(n2659), .Y(n2723) );
NAND2X1TS U3245 ( .A(n2572), .B(n2571), .Y(n2721) );
INVX2TS U3246 ( .A(n2721), .Y(n2573) );
AOI21X1TS U3247 ( .A0(n2722), .A1(n2723), .B0(n2573), .Y(n2719) );
NAND2X1TS U3248 ( .A(n2575), .B(n2574), .Y(n2717) );
OA21X2TS U3249 ( .A0(n2716), .A1(n2719), .B0(n2717), .Y(n2714) );
NAND2X1TS U3250 ( .A(DP_OP_159J23_128_5719_n136), .B(n2576), .Y(n2712) );
NAND2X1TS U3251 ( .A(DP_OP_159J23_128_5719_n129), .B(
DP_OP_159J23_128_5719_n135), .Y(n2708) );
INVX2TS U3252 ( .A(n2708), .Y(n2577) );
AOI21X4TS U3253 ( .A0(n2579), .A1(n2692), .B0(n2578), .Y(n2691) );
OR2X2TS U3254 ( .A(DP_OP_159J23_128_5719_n104), .B(
DP_OP_159J23_128_5719_n102), .Y(n2685) );
NOR2X1TS U3255 ( .A(n474), .B(n2728), .Y(n2581) );
OAI22X1TS U3256 ( .A0(n512), .A1(n2725), .B0(n474), .B1(n2727), .Y(n2580) );
OR2X2TS U3257 ( .A(DP_OP_159J23_128_5719_n101), .B(n2582), .Y(n2680) );
NAND2X1TS U3258 ( .A(n2685), .B(n2680), .Y(n2585) );
NOR2X2TS U3259 ( .A(DP_OP_159J23_128_5719_n109), .B(
DP_OP_159J23_128_5719_n105), .Y(n2683) );
NOR2X2TS U3260 ( .A(n2585), .B(n2683), .Y(n2667) );
CMPR32X2TS U3261 ( .A(n2581), .B(n2580), .C(DP_OP_159J23_128_5719_n100),
.CO(n2587), .S(n2582) );
NOR2X1TS U3262 ( .A(n474), .B(n2725), .Y(n2586) );
NAND2X1TS U3263 ( .A(n2667), .B(n2672), .Y(n2590) );
NAND2X2TS U3264 ( .A(DP_OP_159J23_128_5719_n109), .B(
DP_OP_159J23_128_5719_n105), .Y(n2688) );
INVX2TS U3265 ( .A(n2684), .Y(n2675) );
INVX2TS U3266 ( .A(n2679), .Y(n2583) );
AOI21X1TS U3267 ( .A0(n2675), .A1(n2680), .B0(n2583), .Y(n2584) );
OAI21X2TS U3268 ( .A0(n2585), .A1(n2688), .B0(n2584), .Y(n2668) );
INVX2TS U3269 ( .A(n2671), .Y(n2588) );
AOI21X1TS U3270 ( .A0(n2668), .A1(n2672), .B0(n2588), .Y(n2589) );
NOR2X1TS U3271 ( .A(n2800), .B(n2804), .Y(n2593) );
OAI22X1TS U3272 ( .A0(n2806), .A1(n2807), .B0(n2599), .B1(n2805), .Y(n2592)
);
NOR2X2TS U3273 ( .A(DP_OP_157J23_126_5719_n110), .B(
DP_OP_157J23_126_5719_n116), .Y(n2768) );
NOR2X2TS U3274 ( .A(DP_OP_157J23_126_5719_n117), .B(
DP_OP_157J23_126_5719_n122), .Y(n2773) );
NOR2X1TS U3275 ( .A(n2768), .B(n2773), .Y(n2608) );
INVX2TS U3276 ( .A(n2591), .Y(n2809) );
OAI22X1TS U3277 ( .A0(n481), .A1(n2809), .B0(n507), .B1(n2808), .Y(n2596) );
NOR2X1TS U3278 ( .A(n2599), .B(n2807), .Y(n2598) );
OAI22X1TS U3279 ( .A0(n2806), .A1(n2809), .B0(n2800), .B1(n2808), .Y(n2597)
);
NOR2X1TS U3280 ( .A(DP_OP_157J23_126_5719_n136), .B(n2605), .Y(n2786) );
OAI22X1TS U3281 ( .A0(n509), .A1(n2813), .B0(n481), .B1(n2811), .Y(n2603) );
NOR2X1TS U3282 ( .A(n2604), .B(n2603), .Y(n2791) );
ADDHX1TS U3283 ( .A(n2598), .B(n2597), .CO(n2595), .S(n2601) );
OAI22X1TS U3284 ( .A0(n481), .A1(n2813), .B0(n507), .B1(n2811), .Y(n2600) );
OAI22X1TS U3285 ( .A0(n2806), .A1(n2813), .B0(n2599), .B1(n2811), .Y(n2662)
);
NOR2X1TS U3286 ( .A(n2800), .B(n2809), .Y(n2661) );
NAND2X1TS U3287 ( .A(n2662), .B(n2661), .Y(n2663) );
INVX2TS U3288 ( .A(n2663), .Y(n2798) );
NAND2X1TS U3289 ( .A(n2601), .B(n2600), .Y(n2796) );
INVX2TS U3290 ( .A(n2796), .Y(n2602) );
AOI21X1TS U3291 ( .A0(n2797), .A1(n2798), .B0(n2602), .Y(n2794) );
NAND2X1TS U3292 ( .A(n2604), .B(n2603), .Y(n2792) );
OA21X4TS U3293 ( .A0(n2791), .A1(n2794), .B0(n2792), .Y(n2789) );
NAND2X1TS U3294 ( .A(DP_OP_157J23_126_5719_n136), .B(n2605), .Y(n2787) );
NAND2X1TS U3295 ( .A(DP_OP_157J23_126_5719_n129), .B(
DP_OP_157J23_126_5719_n135), .Y(n2783) );
INVX2TS U3296 ( .A(n2783), .Y(n2606) );
NOR2X2TS U3297 ( .A(DP_OP_157J23_126_5719_n123), .B(
DP_OP_157J23_126_5719_n128), .Y(n2778) );
AOI21X4TS U3298 ( .A0(n2608), .A1(n2767), .B0(n2607), .Y(n2766) );
OR2X2TS U3299 ( .A(DP_OP_157J23_126_5719_n102), .B(
DP_OP_157J23_126_5719_n104), .Y(n2760) );
OAI22X1TS U3300 ( .A0(n511), .A1(n566), .B0(n476), .B1(n498), .Y(n2609) );
OR2X2TS U3301 ( .A(DP_OP_157J23_126_5719_n101), .B(n2611), .Y(n2755) );
NAND2X4TS U3302 ( .A(n2760), .B(n2755), .Y(n2614) );
NOR2X2TS U3303 ( .A(DP_OP_157J23_126_5719_n109), .B(
DP_OP_157J23_126_5719_n105), .Y(n2758) );
NOR2X1TS U3304 ( .A(n2614), .B(n2758), .Y(n2742) );
CMPR32X2TS U3305 ( .A(n2610), .B(n2609), .C(DP_OP_157J23_126_5719_n100),
.CO(n2616), .S(n2611) );
NOR2X1TS U3306 ( .A(n476), .B(n566), .Y(n2615) );
NAND2X1TS U3307 ( .A(n2742), .B(n2747), .Y(n2619) );
NAND2X2TS U3308 ( .A(DP_OP_157J23_126_5719_n109), .B(
DP_OP_157J23_126_5719_n105), .Y(n2763) );
NAND2X1TS U3309 ( .A(DP_OP_157J23_126_5719_n102), .B(
DP_OP_157J23_126_5719_n104), .Y(n2759) );
INVX2TS U3310 ( .A(n2759), .Y(n2750) );
INVX2TS U3311 ( .A(n2754), .Y(n2612) );
OAI21X1TS U3312 ( .A0(n2614), .A1(n2763), .B0(n2613), .Y(n2743) );
INVX2TS U3313 ( .A(n2746), .Y(n2617) );
AOI21X1TS U3314 ( .A0(n2743), .A1(n2747), .B0(n2617), .Y(n2618) );
AOI22X1TS U3315 ( .A0(n2623), .A1(n2622), .B0(n3266), .B1(n2621), .Y(n2624)
);
INVX2TS U3316 ( .A(n3055), .Y(n2626) );
INVX2TS U3317 ( .A(n3056), .Y(n2625) );
OAI22X1TS U3318 ( .A0(n2627), .A1(n3054), .B0(n2626), .B1(n2625), .Y(n3045)
);
NAND2X1TS U3319 ( .A(n3368), .B(Op_MY[0]), .Y(n2651) );
NOR2X2TS U3320 ( .A(n2634), .B(n2651), .Y(n3050) );
XOR2X1TS U3321 ( .A(n3050), .B(n3046), .Y(n2628) );
XNOR2X1TS U3322 ( .A(n3045), .B(n2628), .Y(n3086) );
XNOR2X1TS U3323 ( .A(n2630), .B(n2629), .Y(n2632) );
CLKXOR2X2TS U3324 ( .A(n2632), .B(n2631), .Y(n3085) );
OAI2BB2XLTS U3325 ( .B0(n3086), .B1(n2635), .A0N(n3085), .A1N(n3084), .Y(
mult_x_57_n29) );
INVX2TS U3326 ( .A(n2934), .Y(n2637) );
INVX2TS U3327 ( .A(n2935), .Y(n2636) );
OAI22X1TS U3328 ( .A0(n2638), .A1(n2933), .B0(n2637), .B1(n2636), .Y(n2924)
);
NAND2X1TS U3329 ( .A(n3378), .B(n3362), .Y(n2654) );
NOR2X2TS U3330 ( .A(n2645), .B(n2654), .Y(n2929) );
XOR2X1TS U3331 ( .A(n2929), .B(n2925), .Y(n2639) );
XNOR2X1TS U3332 ( .A(n2924), .B(n2639), .Y(n2965) );
XNOR2X1TS U3333 ( .A(n2641), .B(n2640), .Y(n2643) );
CLKXOR2X2TS U3334 ( .A(n2643), .B(n2642), .Y(n2964) );
OAI2BB2XLTS U3335 ( .B0(n2965), .B1(n2646), .A0N(n2964), .A1N(n2963), .Y(
mult_x_59_n29) );
NAND2X1TS U3336 ( .A(n3368), .B(n411), .Y(n3052) );
INVX2TS U3337 ( .A(n3052), .Y(n2650) );
NAND2X1TS U3338 ( .A(intadd_56_CI), .B(n2650), .Y(n3060) );
NAND2X1TS U3339 ( .A(n3378), .B(n412), .Y(n2931) );
INVX2TS U3340 ( .A(n2931), .Y(n2653) );
NAND2X1TS U3341 ( .A(intadd_54_CI), .B(n2653), .Y(n2939) );
INVX2TS U3342 ( .A(n2667), .Y(n2670) );
INVX2TS U3343 ( .A(n2668), .Y(n2669) );
OAI21X1TS U3344 ( .A0(n2691), .A1(n2670), .B0(n2669), .Y(n2674) );
NAND2X1TS U3345 ( .A(n2672), .B(n2671), .Y(n2673) );
XNOR2X1TS U3346 ( .A(n2674), .B(n2673), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
INVX2TS U3347 ( .A(n2683), .Y(n2689) );
NAND2X1TS U3348 ( .A(n2689), .B(n2685), .Y(n2678) );
INVX2TS U3349 ( .A(n2688), .Y(n2676) );
AOI21X1TS U3350 ( .A0(n2676), .A1(n2685), .B0(n2675), .Y(n2677) );
NAND2X1TS U3351 ( .A(n2680), .B(n2679), .Y(n2681) );
XNOR2X1TS U3352 ( .A(n2682), .B(n2681), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
NAND2X1TS U3353 ( .A(n2685), .B(n2684), .Y(n2686) );
XNOR2X1TS U3354 ( .A(n2687), .B(n2686), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
NAND2X1TS U3355 ( .A(n2689), .B(n2688), .Y(n2690) );
INVX2TS U3356 ( .A(n2692), .Y(n2701) );
INVX2TS U3357 ( .A(n2693), .Y(n2695) );
NAND2X1TS U3358 ( .A(n2695), .B(n2694), .Y(n2696) );
XNOR2X1TS U3359 ( .A(n2697), .B(n2696), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8)
);
INVX2TS U3360 ( .A(n2698), .Y(n2700) );
NAND2X1TS U3361 ( .A(n2700), .B(n2699), .Y(n2702) );
INVX2TS U3362 ( .A(n2703), .Y(n2705) );
NAND2X1TS U3363 ( .A(n2705), .B(n2704), .Y(n2707) );
NAND2X1TS U3364 ( .A(n590), .B(n2708), .Y(n2710) );
XNOR2X1TS U3365 ( .A(n2710), .B(n2709), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5)
);
INVX2TS U3366 ( .A(n2711), .Y(n2713) );
NAND2X1TS U3367 ( .A(n2713), .B(n2712), .Y(n2715) );
INVX2TS U3368 ( .A(n2716), .Y(n2718) );
NAND2X1TS U3369 ( .A(n2718), .B(n2717), .Y(n2720) );
NAND2X1TS U3370 ( .A(n2722), .B(n2721), .Y(n2724) );
XNOR2X1TS U3371 ( .A(n2724), .B(n2723), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2)
);
OAI22X1TS U3372 ( .A0(n512), .A1(n2727), .B0(n484), .B1(n2725), .Y(
DP_OP_159J23_128_5719_n147) );
OAI22X1TS U3373 ( .A0(n479), .A1(n2727), .B0(n508), .B1(n2725), .Y(
DP_OP_159J23_128_5719_n150) );
OAI22X1TS U3374 ( .A0(n2733), .A1(n2727), .B0(n2726), .B1(n2725), .Y(
DP_OP_159J23_128_5719_n151) );
OAI22X1TS U3375 ( .A0(n2737), .A1(n2728), .B0(n474), .B1(n2729), .Y(
DP_OP_159J23_128_5719_n154) );
OAI22X1TS U3376 ( .A0(n2737), .A1(n2729), .B0(n484), .B1(n2728), .Y(
DP_OP_159J23_128_5719_n155) );
OAI22X1TS U3377 ( .A0(n2739), .A1(n2729), .B0(n479), .B1(n2728), .Y(
DP_OP_159J23_128_5719_n157) );
OAI22X1TS U3378 ( .A0(n478), .A1(n2729), .B0(n2733), .B1(n2728), .Y(
DP_OP_159J23_128_5719_n158) );
OAI22X1TS U3379 ( .A0(n2737), .A1(n2730), .B0(n474), .B1(n2731), .Y(
DP_OP_159J23_128_5719_n162) );
OAI22X1TS U3380 ( .A0(n484), .A1(n2731), .B0(n510), .B1(n2730), .Y(
DP_OP_159J23_128_5719_n164) );
OAI22X1TS U3381 ( .A0(n2739), .A1(n2731), .B0(n479), .B1(n2730), .Y(
DP_OP_159J23_128_5719_n165) );
OAI22X1TS U3382 ( .A0(n512), .A1(n2732), .B0(n474), .B1(n2734), .Y(
DP_OP_159J23_128_5719_n170) );
OAI22X1TS U3383 ( .A0(n2737), .A1(n2734), .B0(n484), .B1(n2732), .Y(
DP_OP_159J23_128_5719_n171) );
OAI22X1TS U3384 ( .A0(n484), .A1(n2734), .B0(n510), .B1(n2732), .Y(
DP_OP_159J23_128_5719_n172) );
OAI22X1TS U3385 ( .A0(n478), .A1(n2734), .B0(n2733), .B1(n2732), .Y(
DP_OP_159J23_128_5719_n174) );
OAI22X1TS U3386 ( .A0(n2737), .A1(n2735), .B0(n474), .B1(n2736), .Y(
DP_OP_159J23_128_5719_n178) );
OAI22X1TS U3387 ( .A0(n2737), .A1(n2736), .B0(n2741), .B1(n2735), .Y(
DP_OP_159J23_128_5719_n179) );
OAI22X1TS U3388 ( .A0(n2741), .A1(n2736), .B0(n2739), .B1(n2735), .Y(
DP_OP_159J23_128_5719_n180) );
OAI22X1TS U3389 ( .A0(n2739), .A1(n2736), .B0(n479), .B1(n2735), .Y(
DP_OP_159J23_128_5719_n181) );
OAI22X1TS U3390 ( .A0(n2737), .A1(n2738), .B0(n473), .B1(n2740), .Y(
DP_OP_159J23_128_5719_n186) );
OAI22X1TS U3391 ( .A0(n2737), .A1(n2740), .B0(n2741), .B1(n2738), .Y(
DP_OP_159J23_128_5719_n187) );
OAI22X1TS U3392 ( .A0(n484), .A1(n2740), .B0(n510), .B1(n2738), .Y(
DP_OP_159J23_128_5719_n188) );
INVX2TS U3393 ( .A(n2742), .Y(n2745) );
INVX2TS U3394 ( .A(n2743), .Y(n2744) );
NAND2X1TS U3395 ( .A(n2747), .B(n2746), .Y(n2748) );
INVX2TS U3396 ( .A(n2758), .Y(n2764) );
NAND2X1TS U3397 ( .A(n2764), .B(n2760), .Y(n2753) );
INVX2TS U3398 ( .A(n2763), .Y(n2751) );
AOI21X1TS U3399 ( .A0(n2751), .A1(n2760), .B0(n2750), .Y(n2752) );
NAND2X1TS U3400 ( .A(n2755), .B(n2754), .Y(n2756) );
XNOR2X1TS U3401 ( .A(n2757), .B(n2756), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11)
);
NAND2X1TS U3402 ( .A(n2760), .B(n2759), .Y(n2761) );
XNOR2X1TS U3403 ( .A(n2762), .B(n2761), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10)
);
NAND2X1TS U3404 ( .A(n2764), .B(n2763), .Y(n2765) );
INVX2TS U3405 ( .A(n2767), .Y(n2776) );
INVX2TS U3406 ( .A(n2768), .Y(n2770) );
NAND2X1TS U3407 ( .A(n2770), .B(n2769), .Y(n2771) );
XNOR2X1TS U3408 ( .A(n2772), .B(n2771), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8)
);
INVX2TS U3409 ( .A(n2773), .Y(n2775) );
NAND2X1TS U3410 ( .A(n2775), .B(n2774), .Y(n2777) );
INVX2TS U3411 ( .A(n2778), .Y(n2780) );
NAND2X1TS U3412 ( .A(n2780), .B(n2779), .Y(n2782) );
NAND2X1TS U3413 ( .A(n554), .B(n2783), .Y(n2785) );
XNOR2X1TS U3414 ( .A(n2785), .B(n2784), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5)
);
INVX2TS U3415 ( .A(n2786), .Y(n2788) );
NAND2X1TS U3416 ( .A(n2788), .B(n2787), .Y(n2790) );
INVX2TS U3417 ( .A(n2791), .Y(n2793) );
NAND2X1TS U3418 ( .A(n2793), .B(n2792), .Y(n2795) );
XOR2X1TS U3419 ( .A(n2795), .B(n2794), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3)
);
NAND2X1TS U3420 ( .A(n2797), .B(n2796), .Y(n2799) );
XNOR2X1TS U3421 ( .A(n2799), .B(n2798), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2)
);
OAI22X1TS U3422 ( .A0(n2810), .A1(n498), .B0(n483), .B1(n566), .Y(
DP_OP_157J23_126_5719_n147) );
OAI22X1TS U3423 ( .A0(n481), .A1(n498), .B0(n2806), .B1(n566), .Y(
DP_OP_157J23_126_5719_n150) );
OAI22X1TS U3424 ( .A0(n2806), .A1(n498), .B0(n2800), .B1(n566), .Y(
DP_OP_157J23_126_5719_n151) );
OAI22X1TS U3425 ( .A0(n2810), .A1(n2801), .B0(n475), .B1(n2802), .Y(
DP_OP_157J23_126_5719_n154) );
OAI22X1TS U3426 ( .A0(n2810), .A1(n2802), .B0(n483), .B1(n2801), .Y(
DP_OP_157J23_126_5719_n155) );
OAI22X1TS U3427 ( .A0(n2812), .A1(n2802), .B0(n480), .B1(n2801), .Y(
DP_OP_157J23_126_5719_n157) );
OAI22X1TS U3428 ( .A0(n480), .A1(n2802), .B0(n2806), .B1(n2801), .Y(
DP_OP_157J23_126_5719_n158) );
OAI22X1TS U3429 ( .A0(n2810), .A1(n2803), .B0(n476), .B1(n2804), .Y(
DP_OP_157J23_126_5719_n162) );
OAI22X1TS U3430 ( .A0(n483), .A1(n2804), .B0(n509), .B1(n2803), .Y(
DP_OP_157J23_126_5719_n164) );
OAI22X1TS U3431 ( .A0(n2812), .A1(n2804), .B0(n481), .B1(n2803), .Y(
DP_OP_157J23_126_5719_n165) );
OAI22X1TS U3432 ( .A0(n511), .A1(n2805), .B0(n476), .B1(n2807), .Y(
DP_OP_157J23_126_5719_n170) );
OAI22X1TS U3433 ( .A0(n511), .A1(n2807), .B0(n483), .B1(n2805), .Y(
DP_OP_157J23_126_5719_n171) );
OAI22X1TS U3434 ( .A0(n483), .A1(n2807), .B0(n2812), .B1(n2805), .Y(
DP_OP_157J23_126_5719_n172) );
OAI22X1TS U3435 ( .A0(n480), .A1(n2807), .B0(n2806), .B1(n2805), .Y(
DP_OP_157J23_126_5719_n174) );
OAI22X1TS U3436 ( .A0(n2810), .A1(n2808), .B0(n476), .B1(n2809), .Y(
DP_OP_157J23_126_5719_n178) );
OAI22X1TS U3437 ( .A0(n2810), .A1(n2809), .B0(n483), .B1(n2808), .Y(
DP_OP_157J23_126_5719_n179) );
OAI22X1TS U3438 ( .A0(n482), .A1(n2809), .B0(n2812), .B1(n2808), .Y(
DP_OP_157J23_126_5719_n180) );
OAI22X1TS U3439 ( .A0(n2812), .A1(n2809), .B0(n480), .B1(n2808), .Y(
DP_OP_157J23_126_5719_n181) );
OAI22X1TS U3440 ( .A0(n2810), .A1(n2813), .B0(n482), .B1(n2811), .Y(
DP_OP_157J23_126_5719_n187) );
OAI22X1TS U3441 ( .A0(n483), .A1(n2813), .B0(n509), .B1(n2811), .Y(
DP_OP_157J23_126_5719_n188) );
NOR3BX1TS U3442 ( .AN(Op_MY[30]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n2814) );
XOR2X1TS U3443 ( .A(n506), .B(n2814), .Y(DP_OP_36J23_129_4699_n15) );
OAI2BB1X1TS U3444 ( .A0N(Op_MY[29]), .A1N(n3406), .B0(n2815), .Y(n2816) );
XOR2X1TS U3445 ( .A(n506), .B(n2816), .Y(DP_OP_36J23_129_4699_n16) );
OAI2BB1X1TS U3446 ( .A0N(Op_MY[28]), .A1N(n3406), .B0(n2815), .Y(n2817) );
XOR2X1TS U3447 ( .A(n506), .B(n2817), .Y(DP_OP_36J23_129_4699_n17) );
OAI2BB1X1TS U3448 ( .A0N(Op_MY[27]), .A1N(n3406), .B0(n2815), .Y(n2818) );
XOR2X1TS U3449 ( .A(n506), .B(n2818), .Y(DP_OP_36J23_129_4699_n18) );
OAI2BB1X1TS U3450 ( .A0N(Op_MY[26]), .A1N(n3406), .B0(n2815), .Y(n2819) );
XOR2X1TS U3451 ( .A(n506), .B(n2819), .Y(DP_OP_36J23_129_4699_n19) );
OAI2BB1X1TS U3452 ( .A0N(Op_MY[25]), .A1N(n3406), .B0(n2815), .Y(n2820) );
XOR2X1TS U3453 ( .A(n506), .B(n2820), .Y(DP_OP_36J23_129_4699_n20) );
OAI2BB1X1TS U3454 ( .A0N(Op_MY[24]), .A1N(n3406), .B0(n2815), .Y(n2821) );
OAI21X1TS U3455 ( .A0(FSM_selector_B[0]), .A1(n2822), .B0(n2815), .Y(n2823)
);
XOR2X1TS U3456 ( .A(n2422), .B(n2823), .Y(DP_OP_36J23_129_4699_n22) );
INVX2TS U3457 ( .A(n2827), .Y(n2831) );
INVX2TS U3458 ( .A(n573), .Y(n2829) );
INVX2TS U3459 ( .A(n550), .Y(n2838) );
NAND2X1TS U3460 ( .A(n3380), .B(n3353), .Y(n2861) );
NAND2X1TS U3461 ( .A(n488), .B(n404), .Y(n2860) );
AOI21X1TS U3462 ( .A0(n2862), .A1(n2861), .B0(n2860), .Y(n2840) );
NOR2X1TS U3463 ( .A(n2862), .B(n2861), .Y(n2839) );
NOR2X2TS U3464 ( .A(n2842), .B(n2841), .Y(n2864) );
NOR2X1TS U3465 ( .A(n2864), .B(n3461), .Y(n2848) );
AOI21X1TS U3466 ( .A0(n2845), .A1(n2844), .B0(n2843), .Y(n2847) );
NOR2X1TS U3467 ( .A(n2847), .B(n2846), .Y(n2865) );
NOR2BX1TS U3468 ( .AN(n2884), .B(n2885), .Y(n2853) );
XNOR2X1TS U3469 ( .A(n2872), .B(n2849), .Y(n2850) );
XOR2X1TS U3470 ( .A(n2851), .B(n2850), .Y(n2886) );
INVX2TS U3471 ( .A(n2885), .Y(n2852) );
OAI22X1TS U3472 ( .A0(n2853), .A1(n2886), .B0(n2852), .B1(n2884), .Y(
mult_x_56_n17) );
INVX2TS U3473 ( .A(n2855), .Y(n2859) );
INVX2TS U3474 ( .A(n2858), .Y(n2856) );
AOI21X1TS U3475 ( .A0(n2856), .A1(n2855), .B0(n2854), .Y(n2857) );
AOI21X1TS U3476 ( .A0(n2859), .A1(n2858), .B0(n2857), .Y(n2889) );
XNOR2X1TS U3477 ( .A(n2861), .B(n2860), .Y(n2863) );
XOR2X1TS U3478 ( .A(n2863), .B(n2862), .Y(n2888) );
XNOR2X1TS U3479 ( .A(n2864), .B(n3461), .Y(n2866) );
ACHCINX2TS U3480 ( .CIN(n2889), .A(n2888), .B(n2890), .CO(mult_x_56_n22) );
XOR2X1TS U3481 ( .A(n2868), .B(n2867), .Y(n2870) );
XNOR2X1TS U3482 ( .A(n2870), .B(n2869), .Y(mult_x_56_n37) );
NAND2X1TS U3483 ( .A(n2829), .B(n404), .Y(n2871) );
NOR2X1TS U3484 ( .A(n2872), .B(n2871), .Y(n2897) );
AOI21X1TS U3485 ( .A0(n2872), .A1(n2871), .B0(n2897), .Y(intadd_57_A_0_) );
XNOR2X1TS U3486 ( .A(n488), .B(n3353), .Y(n2874) );
INVX2TS U3487 ( .A(n2874), .Y(n2875) );
MXI2X1TS U3488 ( .A(n2875), .B(n2874), .S0(n2873), .Y(intadd_57_B_7_) );
MXI2X1TS U3489 ( .A(n2878), .B(n2877), .S0(n2876), .Y(n2882) );
XOR2X1TS U3490 ( .A(n2880), .B(n2879), .Y(n2881) );
MXI2X1TS U3491 ( .A(n2883), .B(n2882), .S0(n2881), .Y(mult_x_56_n15) );
XNOR2X1TS U3492 ( .A(n2885), .B(n2884), .Y(n2887) );
XNOR2X1TS U3493 ( .A(n2887), .B(n2886), .Y(mult_x_56_n18) );
XOR2X1TS U3494 ( .A(n2889), .B(n2888), .Y(n2891) );
XNOR2X1TS U3495 ( .A(n2891), .B(n2890), .Y(mult_x_56_n23) );
XOR2X1TS U3496 ( .A(n2893), .B(n2892), .Y(n2895) );
XOR2X1TS U3497 ( .A(n2895), .B(n2894), .Y(mult_x_56_n30) );
AOI21X1TS U3498 ( .A0(n390), .A1(n2897), .B0(n2896), .Y(n2899) );
XNOR2X1TS U3499 ( .A(n2899), .B(n2898), .Y(intadd_57_B_1_) );
AOI21X1TS U3500 ( .A0(n2902), .A1(n2901), .B0(n2900), .Y(n2904) );
NOR2BX1TS U3501 ( .AN(n2907), .B(n2905), .Y(n2908) );
INVX2TS U3502 ( .A(n2905), .Y(n2906) );
NOR2BX1TS U3503 ( .AN(n2951), .B(n2952), .Y(n2915) );
XOR2X1TS U3504 ( .A(n2911), .B(n2910), .Y(n2913) );
XOR2X1TS U3505 ( .A(n2913), .B(n2912), .Y(n2953) );
INVX2TS U3506 ( .A(n2952), .Y(n2914) );
OAI22X1TS U3507 ( .A0(n2915), .A1(n2953), .B0(n2914), .B1(n2951), .Y(
mult_x_59_n14) );
XOR2X1TS U3508 ( .A(n2917), .B(n2916), .Y(n2919) );
XOR2X1TS U3509 ( .A(n2919), .B(n2918), .Y(n2961) );
XNOR2X1TS U3510 ( .A(n2921), .B(n2920), .Y(n2923) );
XOR2X1TS U3511 ( .A(n2923), .B(n2922), .Y(n2959) );
INVX2TS U3512 ( .A(n2925), .Y(n2928) );
INVX2TS U3513 ( .A(n2929), .Y(n2927) );
OAI21X1TS U3514 ( .A0(n2928), .A1(n2927), .B0(n2926), .Y(n2960) );
ACHCINX2TS U3515 ( .CIN(n2961), .A(n2959), .B(n2960), .CO(mult_x_59_n22) );
XOR2X1TS U3516 ( .A(n2934), .B(n2933), .Y(n2936) );
XOR2X1TS U3517 ( .A(n2936), .B(n2935), .Y(n2942) );
INVX2TS U3518 ( .A(n2940), .Y(n2937) );
OAI22X1TS U3519 ( .A0(n2938), .A1(n2942), .B0(n2937), .B1(n2939), .Y(
mult_x_59_n36) );
XOR2X1TS U3520 ( .A(n2940), .B(n2939), .Y(n2941) );
XOR2X1TS U3521 ( .A(n2942), .B(n2941), .Y(mult_x_59_n37) );
AOI21X1TS U3522 ( .A0(n2944), .A1(n2943), .B0(n2969), .Y(intadd_54_A_0_) );
INVX2TS U3523 ( .A(n2945), .Y(n2948) );
INVX2TS U3524 ( .A(n2946), .Y(n2947) );
OAI22X1TS U3525 ( .A0(n2950), .A1(n2949), .B0(n2948), .B1(n2947), .Y(
intadd_54_B_8_) );
XOR2X1TS U3526 ( .A(n2952), .B(n2951), .Y(n2954) );
XOR2X1TS U3527 ( .A(n2954), .B(n2953), .Y(mult_x_59_n15) );
XOR2X1TS U3528 ( .A(n2956), .B(n2955), .Y(n2958) );
XNOR2X1TS U3529 ( .A(n2958), .B(n2957), .Y(mult_x_59_n18) );
XNOR2X1TS U3530 ( .A(n2960), .B(n2959), .Y(n2962) );
XOR2X1TS U3531 ( .A(n2962), .B(n2961), .Y(mult_x_59_n23) );
XOR2X1TS U3532 ( .A(n2964), .B(n2963), .Y(n2966) );
XNOR2X1TS U3533 ( .A(n2966), .B(n2965), .Y(mult_x_59_n30) );
NAND2X1TS U3534 ( .A(n419), .B(Op_MY[15]), .Y(n2967) );
XOR2X1TS U3535 ( .A(n2968), .B(n2967), .Y(n2970) );
XOR2X1TS U3536 ( .A(n2970), .B(n2969), .Y(intadd_54_B_1_) );
AOI21X1TS U3537 ( .A0(n2972), .A1(n2971), .B0(intadd_54_B_0_), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1)
);
XOR2X1TS U3538 ( .A(n2974), .B(n2973), .Y(n2976) );
CLKXOR2X2TS U3539 ( .A(n2976), .B(n2975), .Y(n3007) );
OAI2BB1X1TS U3540 ( .A0N(n2979), .A1N(n2980), .B0(n2977), .Y(n2978) );
NOR2BX1TS U3541 ( .AN(n3007), .B(n3008), .Y(n2986) );
XNOR2X1TS U3542 ( .A(n2982), .B(n2981), .Y(n2984) );
XOR2X1TS U3543 ( .A(n2984), .B(n2983), .Y(n3009) );
INVX2TS U3544 ( .A(n3008), .Y(n2985) );
OAI22X1TS U3545 ( .A0(n2986), .A1(n3009), .B0(n2985), .B1(n3007), .Y(
mult_x_58_n22) );
XOR2X1TS U3546 ( .A(n2988), .B(n2987), .Y(n2989) );
XNOR2X1TS U3547 ( .A(n2990), .B(n2989), .Y(mult_x_58_n37) );
AOI21X1TS U3548 ( .A0(n2992), .A1(n2991), .B0(n3017), .Y(intadd_55_A_0_) );
INVX2TS U3549 ( .A(n2993), .Y(n2996) );
INVX2TS U3550 ( .A(n2994), .Y(n2995) );
OAI22X1TS U3551 ( .A0(n2998), .A1(n2997), .B0(n2996), .B1(n2995), .Y(
intadd_55_B_8_) );
XOR2X1TS U3552 ( .A(n3000), .B(n2999), .Y(n3002) );
XNOR2X1TS U3553 ( .A(n3002), .B(n3001), .Y(mult_x_58_n15) );
XOR2X1TS U3554 ( .A(n3004), .B(n3003), .Y(n3006) );
XNOR2X1TS U3555 ( .A(n3006), .B(n3005), .Y(mult_x_58_n18) );
XOR2X1TS U3556 ( .A(n3008), .B(n3007), .Y(n3010) );
XOR2X1TS U3557 ( .A(n3010), .B(n3009), .Y(mult_x_58_n23) );
XOR2X1TS U3558 ( .A(n3012), .B(n3011), .Y(n3014) );
XNOR2X1TS U3559 ( .A(n3014), .B(n3013), .Y(mult_x_58_n30) );
XOR2X1TS U3560 ( .A(n3016), .B(n3015), .Y(n3018) );
XOR2X1TS U3561 ( .A(n3018), .B(n3017), .Y(intadd_55_B_1_) );
AOI21X1TS U3562 ( .A0(n3020), .A1(n3019), .B0(intadd_55_B_0_), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1)
);
AOI21X1TS U3563 ( .A0(n3023), .A1(n3022), .B0(n3021), .Y(n3025) );
NOR2BX1TS U3564 ( .AN(n3028), .B(n3026), .Y(n3029) );
INVX2TS U3565 ( .A(n3026), .Y(n3027) );
NOR2BX1TS U3566 ( .AN(n3072), .B(n3073), .Y(n3036) );
XOR2X1TS U3567 ( .A(n3032), .B(n3031), .Y(n3034) );
XOR2X1TS U3568 ( .A(n3034), .B(n3033), .Y(n3074) );
INVX2TS U3569 ( .A(n3073), .Y(n3035) );
OAI22X1TS U3570 ( .A0(n3036), .A1(n3074), .B0(n3035), .B1(n3072), .Y(
mult_x_57_n14) );
XOR2X1TS U3571 ( .A(n3038), .B(n3037), .Y(n3040) );
XOR2X1TS U3572 ( .A(n3040), .B(n3039), .Y(n3082) );
XNOR2X1TS U3573 ( .A(n3042), .B(n3041), .Y(n3044) );
XOR2X1TS U3574 ( .A(n3044), .B(n3043), .Y(n3080) );
INVX2TS U3575 ( .A(n3046), .Y(n3049) );
INVX2TS U3576 ( .A(n3050), .Y(n3048) );
OAI21X1TS U3577 ( .A0(n3049), .A1(n3048), .B0(n3047), .Y(n3081) );
ACHCINX2TS U3578 ( .CIN(n3082), .A(n3080), .B(n3081), .CO(mult_x_57_n22) );
XOR2X1TS U3579 ( .A(n3055), .B(n3054), .Y(n3057) );
XOR2X1TS U3580 ( .A(n3057), .B(n3056), .Y(n3063) );
INVX2TS U3581 ( .A(n3061), .Y(n3058) );
OAI22X1TS U3582 ( .A0(n3059), .A1(n3063), .B0(n3058), .B1(n3060), .Y(
mult_x_57_n36) );
XOR2X1TS U3583 ( .A(n3061), .B(n3060), .Y(n3062) );
XOR2X1TS U3584 ( .A(n3063), .B(n3062), .Y(mult_x_57_n37) );
AOI21X1TS U3585 ( .A0(n3065), .A1(n3064), .B0(n3090), .Y(intadd_56_A_0_) );
INVX2TS U3586 ( .A(n3066), .Y(n3069) );
INVX2TS U3587 ( .A(n3067), .Y(n3068) );
OAI22X1TS U3588 ( .A0(n3071), .A1(n3070), .B0(n3069), .B1(n3068), .Y(
intadd_56_B_8_) );
XOR2X1TS U3589 ( .A(n3073), .B(n3072), .Y(n3075) );
XOR2X1TS U3590 ( .A(n3075), .B(n3074), .Y(mult_x_57_n15) );
XOR2X1TS U3591 ( .A(n3077), .B(n3076), .Y(n3079) );
XNOR2X1TS U3592 ( .A(n3079), .B(n3078), .Y(mult_x_57_n18) );
XNOR2X1TS U3593 ( .A(n3081), .B(n3080), .Y(n3083) );
XOR2X1TS U3594 ( .A(n3083), .B(n3082), .Y(mult_x_57_n23) );
XOR2X1TS U3595 ( .A(n3085), .B(n3084), .Y(n3087) );
XNOR2X1TS U3596 ( .A(n3087), .B(n3086), .Y(mult_x_57_n30) );
NAND2X1TS U3597 ( .A(n3369), .B(n468), .Y(n3088) );
XOR2X1TS U3598 ( .A(n3089), .B(n3088), .Y(n3091) );
XOR2X1TS U3599 ( .A(n3091), .B(n3090), .Y(intadd_56_B_1_) );
AOI21X1TS U3600 ( .A0(n3093), .A1(n3092), .B0(intadd_56_B_0_), .Y(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1)
);
NAND2X1TS U3601 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n3095) );
NAND2X1TS U3602 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[4]),
.Y(n3186) );
NOR2X1TS U3603 ( .A(n3408), .B(n3416), .Y(n3168) );
NAND2X1TS U3604 ( .A(n3168), .B(Sgf_normalized_result[10]), .Y(n3098) );
MXI2X1TS U3605 ( .A(P_Sgf[46]), .B(Add_result[23]), .S0(FSM_selector_C), .Y(
n3100) );
AOI21X1TS U3606 ( .A0(n3101), .A1(n3100), .B0(n3171), .Y(n3102) );
AHHCINX2TS U3607 ( .A(Sgf_normalized_result[22]), .CIN(n3103), .S(n3104),
.CO(n3261) );
AOI22X1TS U3608 ( .A0(n487), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n3171), .Y(n3105) );
OAI2BB1X1TS U3609 ( .A0N(P_Sgf[46]), .A1N(n523), .B0(n3105), .Y(n3106) );
AOI21X1TS U3610 ( .A0(n3253), .A1(Add_result[22]), .B0(n3106), .Y(n3107) );
OAI2BB1X1TS U3611 ( .A0N(n499), .A1N(P_Sgf[45]), .B0(n3107), .Y(n213) );
AHHCONX2TS U3612 ( .A(Sgf_normalized_result[21]), .CI(n3108), .CON(n3103),
.S(n3109) );
AOI22X1TS U3613 ( .A0(n3110), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n3171), .Y(n3111) );
OAI2BB1X1TS U3614 ( .A0N(P_Sgf[45]), .A1N(n522), .B0(n3111), .Y(n3112) );
AOI21X1TS U3615 ( .A0(n521), .A1(Add_result[21]), .B0(n3112), .Y(n3113) );
OAI2BB1X1TS U3616 ( .A0N(n499), .A1N(P_Sgf[44]), .B0(n3113), .Y(n212) );
AHHCINX2TS U3617 ( .A(Sgf_normalized_result[20]), .CIN(n3114), .S(n3115),
.CO(n3108) );
AOI22X1TS U3618 ( .A0(n487), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n3171), .Y(n3116) );
OAI2BB1X1TS U3619 ( .A0N(n523), .A1N(P_Sgf[44]), .B0(n3116), .Y(n3117) );
AOI21X1TS U3620 ( .A0(n2410), .A1(Add_result[20]), .B0(n3117), .Y(n3118) );
OAI2BB1X1TS U3621 ( .A0N(n499), .A1N(P_Sgf[43]), .B0(n3118), .Y(n211) );
AHHCONX2TS U3622 ( .A(Sgf_normalized_result[19]), .CI(n3119), .CON(n3114),
.S(n3120) );
AOI22X1TS U3623 ( .A0(n486), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n3163), .Y(n3121) );
OAI2BB1X1TS U3624 ( .A0N(n524), .A1N(P_Sgf[43]), .B0(n3121), .Y(n3122) );
AOI21X1TS U3625 ( .A0(n521), .A1(Add_result[19]), .B0(n3122), .Y(n3123) );
OAI2BB1X1TS U3626 ( .A0N(n499), .A1N(P_Sgf[42]), .B0(n3123), .Y(n210) );
AHHCINX2TS U3627 ( .A(Sgf_normalized_result[18]), .CIN(n3124), .S(n3125),
.CO(n3119) );
AOI22X1TS U3628 ( .A0(n487), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n3163), .Y(n3126) );
OAI2BB1X1TS U3629 ( .A0N(n524), .A1N(P_Sgf[42]), .B0(n3126), .Y(n3127) );
AOI21X1TS U3630 ( .A0(n2410), .A1(Add_result[18]), .B0(n3127), .Y(n3128) );
OAI2BB1X1TS U3631 ( .A0N(n499), .A1N(P_Sgf[41]), .B0(n3128), .Y(n209) );
AHHCONX2TS U3632 ( .A(Sgf_normalized_result[17]), .CI(n3129), .CON(n3124),
.S(n3131) );
AOI22X1TS U3633 ( .A0(n487), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n3163), .Y(n3132) );
OAI2BB1X1TS U3634 ( .A0N(n522), .A1N(P_Sgf[41]), .B0(n3132), .Y(n3133) );
AOI21X1TS U3635 ( .A0(n521), .A1(Add_result[17]), .B0(n3133), .Y(n3134) );
OAI2BB1X1TS U3636 ( .A0N(n499), .A1N(P_Sgf[40]), .B0(n3134), .Y(n208) );
AHHCINX2TS U3637 ( .A(Sgf_normalized_result[16]), .CIN(n3135), .S(n3137),
.CO(n3129) );
AOI22X1TS U3638 ( .A0(n486), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n3163), .Y(n3138) );
OAI2BB1X1TS U3639 ( .A0N(n522), .A1N(P_Sgf[40]), .B0(n3138), .Y(n3139) );
AOI21X1TS U3640 ( .A0(n521), .A1(Add_result[16]), .B0(n3139), .Y(n3140) );
OAI2BB1X1TS U3641 ( .A0N(n500), .A1N(P_Sgf[39]), .B0(n3140), .Y(n207) );
AHHCONX2TS U3642 ( .A(Sgf_normalized_result[15]), .CI(n3141), .CON(n3135),
.S(n3142) );
AOI22X1TS U3643 ( .A0(n3110), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n3163), .Y(n3143) );
OAI2BB1X1TS U3644 ( .A0N(n523), .A1N(P_Sgf[39]), .B0(n3143), .Y(n3144) );
AOI21X1TS U3645 ( .A0(n521), .A1(Add_result[15]), .B0(n3144), .Y(n3145) );
OAI2BB1X1TS U3646 ( .A0N(n501), .A1N(P_Sgf[38]), .B0(n3145), .Y(n206) );
AHHCINX2TS U3647 ( .A(Sgf_normalized_result[14]), .CIN(n3146), .S(n3147),
.CO(n3141) );
AOI22X1TS U3648 ( .A0(n486), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n3163), .Y(n3148) );
OAI2BB1X1TS U3649 ( .A0N(n523), .A1N(P_Sgf[38]), .B0(n3148), .Y(n3149) );
AOI21X1TS U3650 ( .A0(n2410), .A1(Add_result[14]), .B0(n3149), .Y(n3150) );
OAI2BB1X1TS U3651 ( .A0N(n500), .A1N(P_Sgf[37]), .B0(n3150), .Y(n205) );
AHHCONX2TS U3652 ( .A(Sgf_normalized_result[13]), .CI(n3151), .CON(n3146),
.S(n3152) );
AOI22X1TS U3653 ( .A0(n487), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n3163), .Y(n3153) );
OAI2BB1X1TS U3654 ( .A0N(n524), .A1N(P_Sgf[37]), .B0(n3153), .Y(n3154) );
AOI21X1TS U3655 ( .A0(n521), .A1(Add_result[13]), .B0(n3154), .Y(n3155) );
OAI2BB1X1TS U3656 ( .A0N(n501), .A1N(P_Sgf[36]), .B0(n3155), .Y(n204) );
AHHCINX2TS U3657 ( .A(Sgf_normalized_result[12]), .CIN(n3156), .S(n3157),
.CO(n3151) );
AOI22X1TS U3658 ( .A0(n487), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n3163), .Y(n3158) );
OAI2BB1X1TS U3659 ( .A0N(n524), .A1N(P_Sgf[36]), .B0(n3158), .Y(n3159) );
AOI21X1TS U3660 ( .A0(n521), .A1(Add_result[12]), .B0(n3159), .Y(n3160) );
OAI2BB1X1TS U3661 ( .A0N(n500), .A1N(P_Sgf[35]), .B0(n3160), .Y(n203) );
AHHCONX2TS U3662 ( .A(Sgf_normalized_result[11]), .CI(n3161), .CON(n3156),
.S(n3162) );
AOI22X1TS U3663 ( .A0(n486), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n3163), .Y(n3164) );
OAI2BB1X1TS U3664 ( .A0N(n522), .A1N(P_Sgf[35]), .B0(n3164), .Y(n3165) );
AOI21X1TS U3665 ( .A0(n521), .A1(Add_result[11]), .B0(n3165), .Y(n3166) );
OAI2BB1X1TS U3666 ( .A0N(n501), .A1N(P_Sgf[34]), .B0(n3166), .Y(n202) );
NAND2X1TS U3667 ( .A(n3180), .B(n3168), .Y(n3169) );
XOR2X1TS U3668 ( .A(n3169), .B(n3430), .Y(n3170) );
BUFX3TS U3669 ( .A(n3171), .Y(n3249) );
AOI22X1TS U3670 ( .A0(n486), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n3249), .Y(n3172) );
OAI2BB1X1TS U3671 ( .A0N(n522), .A1N(P_Sgf[34]), .B0(n3172), .Y(n3173) );
AOI21X1TS U3672 ( .A0(n3253), .A1(Add_result[10]), .B0(n3173), .Y(n3174) );
OAI2BB1X1TS U3673 ( .A0N(n500), .A1N(P_Sgf[33]), .B0(n3174), .Y(n201) );
NAND2X1TS U3674 ( .A(n3180), .B(Sgf_normalized_result[8]), .Y(n3175) );
XOR2X1TS U3675 ( .A(n3175), .B(n3416), .Y(n3176) );
AOI22X1TS U3676 ( .A0(n3110), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n3249), .Y(n3177) );
OAI2BB1X1TS U3677 ( .A0N(n523), .A1N(P_Sgf[33]), .B0(n3177), .Y(n3178) );
AOI21X1TS U3678 ( .A0(n3253), .A1(Add_result[9]), .B0(n3178), .Y(n3179) );
OAI2BB1X1TS U3679 ( .A0N(n501), .A1N(P_Sgf[32]), .B0(n3179), .Y(n200) );
XNOR2X1TS U3680 ( .A(n3180), .B(n3408), .Y(n3181) );
AOI22X1TS U3681 ( .A0(n487), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n3249), .Y(n3182) );
OAI2BB1X1TS U3682 ( .A0N(n524), .A1N(P_Sgf[32]), .B0(n3182), .Y(n3183) );
AOI21X1TS U3683 ( .A0(n3253), .A1(Add_result[8]), .B0(n3183), .Y(n3184) );
OAI2BB1X1TS U3684 ( .A0N(n500), .A1N(P_Sgf[31]), .B0(n3184), .Y(n199) );
OAI21X1TS U3685 ( .A0(n3207), .A1(n3418), .B0(n3186), .Y(n3192) );
NAND2X1TS U3686 ( .A(n3192), .B(Sgf_normalized_result[6]), .Y(n3187) );
XOR2X1TS U3687 ( .A(n3187), .B(n3431), .Y(n3188) );
AOI22X1TS U3688 ( .A0(n3110), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n3249), .Y(n3189) );
OAI2BB1X1TS U3689 ( .A0N(n522), .A1N(P_Sgf[31]), .B0(n3189), .Y(n3190) );
AOI21X1TS U3690 ( .A0(n3253), .A1(Add_result[7]), .B0(n3190), .Y(n3191) );
OAI2BB1X1TS U3691 ( .A0N(n501), .A1N(P_Sgf[30]), .B0(n3191), .Y(n198) );
XNOR2X1TS U3692 ( .A(n3192), .B(n3427), .Y(n3193) );
AOI22X1TS U3693 ( .A0(n486), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n3249), .Y(n3194) );
OAI2BB1X1TS U3694 ( .A0N(n523), .A1N(P_Sgf[30]), .B0(n3194), .Y(n3195) );
AOI21X1TS U3695 ( .A0(n3253), .A1(Add_result[6]), .B0(n3195), .Y(n3196) );
OAI2BB1X1TS U3696 ( .A0N(n500), .A1N(P_Sgf[29]), .B0(n3196), .Y(n197) );
NAND2X1TS U3697 ( .A(n3207), .B(n3426), .Y(n3197) );
XNOR2X1TS U3698 ( .A(n3197), .B(n3418), .Y(n3198) );
NAND2X1TS U3699 ( .A(n3200), .B(n3199), .Y(n3201) );
XOR2X1TS U3700 ( .A(n3202), .B(n3201), .Y(n3203) );
AOI22X1TS U3701 ( .A0(n486), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n3249), .Y(n3204) );
OAI2BB1X1TS U3702 ( .A0N(n524), .A1N(P_Sgf[29]), .B0(n3204), .Y(n3205) );
AOI21X1TS U3703 ( .A0(n3253), .A1(Add_result[5]), .B0(n3205), .Y(n3206) );
OAI2BB1X1TS U3704 ( .A0N(n501), .A1N(P_Sgf[28]), .B0(n3206), .Y(n196) );
XOR2X1TS U3705 ( .A(n3207), .B(Sgf_normalized_result[4]), .Y(n3208) );
INVX2TS U3706 ( .A(n3209), .Y(n3223) );
AOI21X1TS U3707 ( .A0(n3223), .A1(n539), .B0(n3210), .Y(n3213) );
NAND2X1TS U3708 ( .A(n540), .B(n3211), .Y(n3212) );
XOR2X1TS U3709 ( .A(n3213), .B(n3212), .Y(n3214) );
AOI22X1TS U3710 ( .A0(n487), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n3249), .Y(n3215) );
OAI2BB1X1TS U3711 ( .A0N(n522), .A1N(P_Sgf[28]), .B0(n3215), .Y(n3216) );
AOI21X1TS U3712 ( .A0(n3253), .A1(Add_result[4]), .B0(n3216), .Y(n3217) );
OAI2BB1X1TS U3713 ( .A0N(n500), .A1N(P_Sgf[27]), .B0(n3217), .Y(n195) );
XOR2X1TS U3714 ( .A(n3219), .B(n3415), .Y(n3220) );
NAND2X1TS U3715 ( .A(n539), .B(n3221), .Y(n3222) );
XNOR2X1TS U3716 ( .A(n3223), .B(n3222), .Y(n3225) );
AOI22X1TS U3717 ( .A0(n3110), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n3249), .Y(n3226) );
OAI2BB1X1TS U3718 ( .A0N(n523), .A1N(P_Sgf[27]), .B0(n3226), .Y(n3227) );
AOI21X1TS U3719 ( .A0(n3253), .A1(Add_result[3]), .B0(n3227), .Y(n3228) );
OAI2BB1X1TS U3720 ( .A0N(n501), .A1N(P_Sgf[26]), .B0(n3228), .Y(n194) );
XOR2X1TS U3721 ( .A(n3229), .B(Sgf_normalized_result[2]), .Y(n3230) );
INVX2TS U3722 ( .A(n3231), .Y(n3247) );
INVX2TS U3723 ( .A(n3232), .Y(n3234) );
NAND2X1TS U3724 ( .A(n3234), .B(n3233), .Y(n3235) );
XNOR2X1TS U3725 ( .A(n3236), .B(n3235), .Y(n3237) );
AOI22X1TS U3726 ( .A0(n486), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n3249), .Y(n3238) );
OAI2BB1X1TS U3727 ( .A0N(n522), .A1N(P_Sgf[26]), .B0(n3238), .Y(n3239) );
AOI21X1TS U3728 ( .A0(n3253), .A1(Add_result[2]), .B0(n3239), .Y(n3240) );
OAI2BB1X1TS U3729 ( .A0N(n499), .A1N(P_Sgf[25]), .B0(n3240), .Y(n193) );
XNOR2X1TS U3730 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n3242) );
INVX2TS U3731 ( .A(n3243), .Y(n3245) );
NAND2X1TS U3732 ( .A(n3245), .B(n3244), .Y(n3246) );
XOR2X1TS U3733 ( .A(n3247), .B(n3246), .Y(n3248) );
AOI22X1TS U3734 ( .A0(n3110), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n3249), .Y(n3250) );
OAI2BB1X1TS U3735 ( .A0N(n523), .A1N(P_Sgf[25]), .B0(n3250), .Y(n3252) );
AOI21X1TS U3736 ( .A0(n521), .A1(Add_result[1]), .B0(n3252), .Y(n3254) );
OAI2BB1X1TS U3737 ( .A0N(n500), .A1N(P_Sgf[24]), .B0(n3254), .Y(n192) );
INVX2TS U3738 ( .A(n3255), .Y(n3309) );
AOI21X1TS U3739 ( .A0(n3309), .A1(n595), .B0(n3256), .Y(n3259) );
NAND2X1TS U3740 ( .A(n1245), .B(n3257), .Y(n3258) );
XOR2X1TS U3741 ( .A(n3259), .B(n3258), .Y(n3260) );
ADDHXLTS U3742 ( .A(Sgf_normalized_result[23]), .B(n3261), .CO(n3263), .S(
n3099) );
AOI22X1TS U3743 ( .A0(n3266), .A1(n3265), .B0(n3422), .B1(n3407), .Y(n3269)
);
AOI21X1TS U3744 ( .A0(n3269), .A1(n3268), .B0(n3267), .Y(n378) );
NAND2X1TS U3745 ( .A(n594), .B(n3270), .Y(n3272) );
XNOR2X1TS U3746 ( .A(n3272), .B(n3271), .Y(n3273) );
INVX2TS U3747 ( .A(n3274), .Y(n3322) );
INVX2TS U3748 ( .A(n3275), .Y(n3313) );
NAND2X1TS U3749 ( .A(n3313), .B(n3311), .Y(n3276) );
XNOR2X1TS U3750 ( .A(n3322), .B(n3276), .Y(n3277) );
INVX2TS U3751 ( .A(n3278), .Y(n3284) );
INVX2TS U3752 ( .A(n3283), .Y(n3279) );
NAND2X1TS U3753 ( .A(n3279), .B(n3282), .Y(n3280) );
XOR2X1TS U3754 ( .A(n3284), .B(n3280), .Y(n3281) );
INVX2TS U3755 ( .A(n3285), .Y(n3287) );
NAND2X1TS U3756 ( .A(n3287), .B(n3286), .Y(n3288) );
XNOR2X1TS U3757 ( .A(n3289), .B(n3288), .Y(n3290) );
INVX2TS U3758 ( .A(n3292), .Y(n3294) );
NAND2X1TS U3759 ( .A(n3294), .B(n3293), .Y(n3295) );
XOR2X1TS U3760 ( .A(n3296), .B(n3295), .Y(n3297) );
OR2X1TS U3761 ( .A(n2220), .B(n3298), .Y(n3300) );
NAND2X1TS U3762 ( .A(n3307), .B(n595), .Y(n3308) );
XNOR2X1TS U3763 ( .A(n3309), .B(n3308), .Y(n3310) );
INVX2TS U3764 ( .A(n3311), .Y(n3312) );
AOI21X1TS U3765 ( .A0(n3322), .A1(n3313), .B0(n3312), .Y(n3318) );
INVX2TS U3766 ( .A(n3314), .Y(n3316) );
NAND2X1TS U3767 ( .A(n3316), .B(n3315), .Y(n3317) );
XOR2X1TS U3768 ( .A(n3318), .B(n3317), .Y(n3319) );
AOI21X1TS U3769 ( .A0(n3322), .A1(n3321), .B0(n3320), .Y(n3325) );
NAND2X1TS U3770 ( .A(n400), .B(n3323), .Y(n3324) );
XOR2X1TS U3771 ( .A(n3325), .B(n3324), .Y(n3326) );
INVX2TS U3772 ( .A(n3327), .Y(n3333) );
INVX2TS U3773 ( .A(n3332), .Y(n3328) );
NAND2X1TS U3774 ( .A(n3328), .B(n3331), .Y(n3329) );
XOR2X1TS U3775 ( .A(n3333), .B(n3329), .Y(n3330) );
INVX2TS U3776 ( .A(n3334), .Y(n3336) );
NAND2X1TS U3777 ( .A(n3336), .B(n3335), .Y(n3337) );
XNOR2X1TS U3778 ( .A(n3338), .B(n3337), .Y(n3339) );
NAND2X1TS U3779 ( .A(n3389), .B(n3428), .Y(n375) );
NOR2BX1TS U3780 ( .AN(exp_oper_result[8]), .B(n3428), .Y(S_Oper_A_exp[8]) );
CLKMX2X2TS U3781 ( .A(Exp_module_Overflow_flag_A), .B(n3346), .S0(n3224),
.Y(n271) );
AO22X1TS U3782 ( .A0(n3395), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n3399), .Y(n190) );
AO22X1TS U3783 ( .A0(n3395), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n3399), .Y(n189) );
AO22X1TS U3784 ( .A0(n3395), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n3399), .Y(n188) );
NOR4X1TS U3785 ( .A(n395), .B(n2833), .C(n3412), .D(n423), .Y(n3361) );
NOR4X1TS U3786 ( .A(Op_MY[6]), .B(n411), .C(Op_MY[0]), .D(n413), .Y(n3360)
);
NOR4X1TS U3787 ( .A(Op_MY[5]), .B(n3355), .C(n468), .D(n467), .Y(n3359) );
NOR4X1TS U3788 ( .A(n390), .B(Op_MY[9]), .C(n420), .D(n3404), .Y(n3358) );
NOR4X1TS U3789 ( .A(Op_MY[28]), .B(Op_MY[27]), .C(Op_MY[26]), .D(Op_MY[25]),
.Y(n3366) );
NOR4X1TS U3790 ( .A(Op_MY[16]), .B(Op_MY[15]), .C(n466), .D(n412), .Y(n3365)
);
NOR4X1TS U3791 ( .A(n404), .B(n3362), .C(Op_MY[30]), .D(Op_MY[29]), .Y(n3364) );
NOR3XLTS U3792 ( .A(n600), .B(Op_MY[23]), .C(Op_MY[24]), .Y(n3363) );
NOR4X1TS U3793 ( .A(n488), .B(n3367), .C(n458), .D(n461), .Y(n3376) );
NOR4X1TS U3794 ( .A(n3368), .B(Op_MX[2]), .C(Op_MX[1]), .D(Op_MX[18]), .Y(
n3375) );
NOR4X1TS U3795 ( .A(n3371), .B(n3370), .C(n3369), .D(n394), .Y(n3374) );
NOR4X1TS U3796 ( .A(n477), .B(Op_MX[10]), .C(n3372), .D(Op_MX[19]), .Y(n3373) );
NOR4X1TS U3797 ( .A(Op_MX[28]), .B(Op_MX[27]), .C(Op_MX[26]), .D(Op_MX[25]),
.Y(n3383) );
NOR4X1TS U3798 ( .A(n3379), .B(n3378), .C(n391), .D(Op_MX[13]), .Y(n3382) );
NOR4X1TS U3799 ( .A(n3380), .B(n498), .C(Op_MX[30]), .D(Op_MX[29]), .Y(n3381) );
OA22X1TS U3800 ( .A0(n3387), .A1(n3386), .B0(n3385), .B1(n3384), .Y(n3388)
);
OAI2BB2XLTS U3801 ( .B0(n3389), .B1(n3388), .A0N(n3389), .A1N(zero_flag),
.Y(n311) );
OA22X1TS U3802 ( .A0(n3393), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n3392), .Y(n270) );
OA22X1TS U3803 ( .A0(n3393), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n3392), .Y(n269) );
OA22X1TS U3804 ( .A0(n3391), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n3392), .Y(n268) );
OA22X1TS U3805 ( .A0(n3391), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n3392), .Y(n267) );
OA22X1TS U3806 ( .A0(n3391), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n3392), .Y(n266) );
OA22X1TS U3807 ( .A0(n3391), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n3392), .Y(n265) );
OA22X1TS U3808 ( .A0(n3391), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n3392), .Y(n264) );
OA22X1TS U3809 ( .A0(n3393), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n3392), .Y(n263) );
AO22X1TS U3810 ( .A0(Sgf_normalized_result[3]), .A1(n3395), .B0(
final_result_ieee[3]), .B1(n3399), .Y(n187) );
INVX2TS U3811 ( .A(n3393), .Y(n3394) );
AO22X1TS U3812 ( .A0(Sgf_normalized_result[9]), .A1(n3395), .B0(
final_result_ieee[9]), .B1(n3397), .Y(n181) );
AO22X1TS U3813 ( .A0(Sgf_normalized_result[10]), .A1(n3398), .B0(
final_result_ieee[10]), .B1(n3397), .Y(n180) );
AO22X1TS U3814 ( .A0(Sgf_normalized_result[11]), .A1(n3398), .B0(
final_result_ieee[11]), .B1(n3397), .Y(n179) );
AO22X1TS U3815 ( .A0(Sgf_normalized_result[12]), .A1(n3398), .B0(
final_result_ieee[12]), .B1(n3397), .Y(n178) );
AO22X1TS U3816 ( .A0(Sgf_normalized_result[13]), .A1(n3398), .B0(
final_result_ieee[13]), .B1(n3397), .Y(n177) );
AO22X1TS U3817 ( .A0(Sgf_normalized_result[14]), .A1(n3398), .B0(
final_result_ieee[14]), .B1(n3397), .Y(n176) );
AO22X1TS U3818 ( .A0(Sgf_normalized_result[15]), .A1(n3398), .B0(
final_result_ieee[15]), .B1(n3397), .Y(n175) );
AO22X1TS U3819 ( .A0(Sgf_normalized_result[16]), .A1(n3398), .B0(
final_result_ieee[16]), .B1(n3397), .Y(n174) );
AO22X1TS U3820 ( .A0(Sgf_normalized_result[17]), .A1(n3398), .B0(
final_result_ieee[17]), .B1(n3397), .Y(n173) );
AO22X1TS U3821 ( .A0(Sgf_normalized_result[18]), .A1(n3398), .B0(
final_result_ieee[18]), .B1(n3399), .Y(n172) );
AO22X1TS U3822 ( .A0(Sgf_normalized_result[19]), .A1(n3398), .B0(
final_result_ieee[19]), .B1(n3399), .Y(n171) );
AO22X1TS U3823 ( .A0(Sgf_normalized_result[21]), .A1(n3400), .B0(
final_result_ieee[21]), .B1(n3399), .Y(n169) );
CMPR42X2TS U3824 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]),
.B(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(
DP_OP_156J23_125_3370_n275), .D(n448), .ICI(DP_OP_156J23_125_3370_n232), .S(DP_OP_156J23_125_3370_n231), .ICO(DP_OP_156J23_125_3370_n229), .CO(
DP_OP_156J23_125_3370_n230) );
CMPR42X1TS U3825 ( .A(DP_OP_157J23_126_5719_n172), .B(
DP_OP_157J23_126_5719_n186), .C(DP_OP_157J23_126_5719_n179), .D(
DP_OP_157J23_126_5719_n127), .ICI(DP_OP_157J23_126_5719_n126), .S(
DP_OP_157J23_126_5719_n123), .ICO(DP_OP_157J23_126_5719_n121), .CO(
DP_OP_157J23_126_5719_n122) );
initial $sdf_annotate("FPU_Multiplication_Function_RKOA_2STAGE_syn.sdf");
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// lineControlUpdate.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
input fullSpeedPolarity;
input fullSpeedBitRate;
output [1:0] JBit;
output [1:0] KBit;
wire fullSpeedPolarity;
wire fullSpeedBitRate;
reg [1:0] JBit;
reg [1:0] KBit;
always @(fullSpeedPolarity)
begin
if (fullSpeedPolarity == 1'b1)
begin
JBit = `ONE_ZERO;
KBit = `ZERO_ONE;
end
else
begin
JBit = `ZERO_ONE;
KBit = `ONE_ZERO;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 48-bit Multi-Functional Arithmetic Block
// /___/ /\ Filename : DSP48E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 01/10/13 - 694456 - DIN_in/D_in connectivity issue
// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml
// 02/13/13 - PCIN_47A change from internal feedback to PCIN(47) pin
// 03/06/13 - 701316 - A_B_reg no clk when REG=0
// 04/03/13 - yaml update
// 04/08/13 - 710304 - AREG, BREG, ACASCREG and BCASCREG dynamic registers mis sized.
// 04/22/13 - 714213 - ACOUT, BCOUT wrong logic
// 04/22/13 - 713695 - Zero mult result on USE_SIMD
// 04/22/13 - 713617 - CARRYCASCOUT behaviour
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// 04/23/13 - 713706 - change P_PDBK connection
// 05/07/13 - 716896 - AREG, BREG, ACASCREG and BCASCREG localparams mis sized.
// 05/07/13 - 716896 - ALUMODE/OPMODE_INV_REG mis sized
// 05/07/13 - 716896 - INMODE_INV_REG mis sized
// 05/07/13 - x_mac_cascd missing for sensitivity list.
// 10/22/14 - 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP48E2 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer ACASCREG = 1,
parameter integer ADREG = 1,
parameter integer ALUMODEREG = 1,
parameter AMULTSEL = "A",
parameter integer AREG = 1,
parameter AUTORESET_PATDET = "NO_RESET",
parameter AUTORESET_PRIORITY = "RESET",
parameter A_INPUT = "DIRECT",
parameter integer BCASCREG = 1,
parameter BMULTSEL = "B",
parameter integer BREG = 1,
parameter B_INPUT = "DIRECT",
parameter integer CARRYINREG = 1,
parameter integer CARRYINSELREG = 1,
parameter integer CREG = 1,
parameter integer DREG = 1,
parameter integer INMODEREG = 1,
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000,
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [4:0] IS_INMODE_INVERTED = 5'b00000,
parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000,
parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0,
parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0,
parameter [0:0] IS_RSTA_INVERTED = 1'b0,
parameter [0:0] IS_RSTB_INVERTED = 1'b0,
parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0,
parameter [0:0] IS_RSTC_INVERTED = 1'b0,
parameter [0:0] IS_RSTD_INVERTED = 1'b0,
parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0,
parameter [0:0] IS_RSTM_INVERTED = 1'b0,
parameter [0:0] IS_RSTP_INVERTED = 1'b0,
parameter [47:0] MASK = 48'h3FFFFFFFFFFF,
parameter integer MREG = 1,
parameter integer OPMODEREG = 1,
parameter [47:0] PATTERN = 48'h000000000000,
parameter PREADDINSEL = "A",
parameter integer PREG = 1,
parameter [47:0] RND = 48'h000000000000,
parameter SEL_MASK = "MASK",
parameter SEL_PATTERN = "PATTERN",
parameter USE_MULT = "MULTIPLY",
parameter USE_PATTERN_DETECT = "NO_PATDET",
parameter USE_SIMD = "ONE48",
parameter USE_WIDEXOR = "FALSE",
parameter XORSIMD = "XOR24_48_96"
)(
output [29:0] ACOUT,
output [17:0] BCOUT,
output CARRYCASCOUT,
output [3:0] CARRYOUT,
output MULTSIGNOUT,
output OVERFLOW,
output [47:0] P,
output PATTERNBDETECT,
output PATTERNDETECT,
output [47:0] PCOUT,
output UNDERFLOW,
output [7:0] XOROUT,
input [29:0] A,
input [29:0] ACIN,
input [3:0] ALUMODE,
input [17:0] B,
input [17:0] BCIN,
input [47:0] C,
input CARRYCASCIN,
input CARRYIN,
input [2:0] CARRYINSEL,
input CEA1,
input CEA2,
input CEAD,
input CEALUMODE,
input CEB1,
input CEB2,
input CEC,
input CECARRYIN,
input CECTRL,
input CED,
input CEINMODE,
input CEM,
input CEP,
input CLK,
input [26:0] D,
input [4:0] INMODE,
input MULTSIGNIN,
input [8:0] OPMODE,
input [47:0] PCIN,
input RSTA,
input RSTALLCARRYIN,
input RSTALUMODE,
input RSTB,
input RSTC,
input RSTCTRL,
input RSTD,
input RSTINMODE,
input RSTM,
input RSTP
);
// define constants
localparam MODULE_NAME = "DSP48E2";
// Parameter encodings and registers
localparam AMULTSEL_A = 0;
localparam AMULTSEL_AD = 1;
localparam AUTORESET_PATDET_NO_RESET = 0;
localparam AUTORESET_PATDET_RESET_MATCH = 1;
localparam AUTORESET_PATDET_RESET_NOT_MATCH = 2;
localparam AUTORESET_PRIORITY_CEP = 1;
localparam AUTORESET_PRIORITY_RESET = 0;
localparam A_INPUT_CASCADE = 1;
localparam A_INPUT_DIRECT = 0;
localparam BMULTSEL_AD = 1;
localparam BMULTSEL_B = 0;
localparam B_INPUT_CASCADE = 1;
localparam B_INPUT_DIRECT = 0;
localparam PREADDINSEL_A = 0;
localparam PREADDINSEL_B = 1;
localparam SEL_MASK_C = 1;
localparam SEL_MASK_MASK = 0;
localparam SEL_MASK_ROUNDING_MODE1 = 2;
localparam SEL_MASK_ROUNDING_MODE2 = 3;
localparam SEL_PATTERN_C = 1;
localparam SEL_PATTERN_PATTERN = 0;
localparam USE_MULT_DYNAMIC = 1;
localparam USE_MULT_MULTIPLY = 0;
localparam USE_MULT_NONE = 2;
localparam USE_PATTERN_DETECT_NO_PATDET = 0;
localparam USE_PATTERN_DETECT_PATDET = 1;
localparam USE_SIMD_FOUR12 = 1;
localparam USE_SIMD_ONE48 = 0;
localparam USE_SIMD_TWO24 = 2;
localparam USE_WIDEXOR_FALSE = 0;
localparam USE_WIDEXOR_TRUE = 1;
localparam XORSIMD_XOR12 = 1;
localparam XORSIMD_XOR24_48_96 = 0;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP48E2_dr.v"
`else
reg [31:0] ACASCREG_REG = ACASCREG;
reg [31:0] ADREG_REG = ADREG;
reg [31:0] ALUMODEREG_REG = ALUMODEREG;
reg [16:1] AMULTSEL_REG = AMULTSEL;
reg [31:0] AREG_REG = AREG;
reg [120:1] AUTORESET_PATDET_REG = AUTORESET_PATDET;
reg [40:1] AUTORESET_PRIORITY_REG = AUTORESET_PRIORITY;
reg [56:1] A_INPUT_REG = A_INPUT;
reg [31:0] BCASCREG_REG = BCASCREG;
reg [16:1] BMULTSEL_REG = BMULTSEL;
reg [31:0] BREG_REG = BREG;
reg [56:1] B_INPUT_REG = B_INPUT;
reg [31:0] CARRYINREG_REG = CARRYINREG;
reg [31:0] CARRYINSELREG_REG = CARRYINSELREG;
reg [31:0] CREG_REG = CREG;
reg [31:0] DREG_REG = DREG;
reg [31:0] INMODEREG_REG = INMODEREG;
reg [3:0] IS_ALUMODE_INVERTED_REG = IS_ALUMODE_INVERTED;
reg [0:0] IS_CARRYIN_INVERTED_REG = IS_CARRYIN_INVERTED;
reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
reg [4:0] IS_INMODE_INVERTED_REG = IS_INMODE_INVERTED;
reg [8:0] IS_OPMODE_INVERTED_REG = IS_OPMODE_INVERTED;
reg [0:0] IS_RSTALLCARRYIN_INVERTED_REG = IS_RSTALLCARRYIN_INVERTED;
reg [0:0] IS_RSTALUMODE_INVERTED_REG = IS_RSTALUMODE_INVERTED;
reg [0:0] IS_RSTA_INVERTED_REG = IS_RSTA_INVERTED;
reg [0:0] IS_RSTB_INVERTED_REG = IS_RSTB_INVERTED;
reg [0:0] IS_RSTCTRL_INVERTED_REG = IS_RSTCTRL_INVERTED;
reg [0:0] IS_RSTC_INVERTED_REG = IS_RSTC_INVERTED;
reg [0:0] IS_RSTD_INVERTED_REG = IS_RSTD_INVERTED;
reg [0:0] IS_RSTINMODE_INVERTED_REG = IS_RSTINMODE_INVERTED;
reg [0:0] IS_RSTM_INVERTED_REG = IS_RSTM_INVERTED;
reg [0:0] IS_RSTP_INVERTED_REG = IS_RSTP_INVERTED;
reg [47:0] MASK_REG = MASK;
reg [31:0] MREG_REG = MREG;
reg [31:0] OPMODEREG_REG = OPMODEREG;
reg [47:0] PATTERN_REG = PATTERN;
reg [8:1] PREADDINSEL_REG = PREADDINSEL;
reg [31:0] PREG_REG = PREG;
reg [47:0] RND_REG = RND;
reg [112:1] SEL_MASK_REG = SEL_MASK;
reg [56:1] SEL_PATTERN_REG = SEL_PATTERN;
reg [64:1] USE_MULT_REG = USE_MULT;
reg [72:1] USE_PATTERN_DETECT_REG = USE_PATTERN_DETECT;
reg [48:1] USE_SIMD_REG = USE_SIMD;
reg [40:1] USE_WIDEXOR_REG = USE_WIDEXOR;
reg [88:1] XORSIMD_REG = XORSIMD;
`endif
`ifdef XIL_XECLIB
wire [1:0] ACASCREG_BIN;
wire ADREG_BIN;
wire ALUMODEREG_BIN;
wire AMULTSEL_BIN;
wire [1:0] AREG_BIN;
wire [1:0] AUTORESET_PATDET_BIN;
wire AUTORESET_PRIORITY_BIN;
wire A_INPUT_BIN;
wire [1:0] BCASCREG_BIN;
wire BMULTSEL_BIN;
wire [1:0] BREG_BIN;
wire B_INPUT_BIN;
wire CARRYINREG_BIN;
wire CARRYINSELREG_BIN;
wire CREG_BIN;
wire DREG_BIN;
wire INMODEREG_BIN;
wire MREG_BIN;
wire OPMODEREG_BIN;
wire PREADDINSEL_BIN;
wire PREG_BIN;
wire [1:0] SEL_MASK_BIN;
wire SEL_PATTERN_BIN;
wire [1:0] USE_MULT_BIN;
wire USE_PATTERN_DETECT_BIN;
wire [1:0] USE_SIMD_BIN;
wire USE_WIDEXOR_BIN;
wire XORSIMD_BIN;
`else
reg [1:0] ACASCREG_BIN;
reg ADREG_BIN;
reg ALUMODEREG_BIN;
reg AMULTSEL_BIN;
reg [1:0] AREG_BIN;
reg [1:0] AUTORESET_PATDET_BIN;
reg AUTORESET_PRIORITY_BIN;
reg A_INPUT_BIN;
reg [1:0] BCASCREG_BIN;
reg BMULTSEL_BIN;
reg [1:0] BREG_BIN;
reg B_INPUT_BIN;
reg CARRYINREG_BIN;
reg CARRYINSELREG_BIN;
reg CREG_BIN;
reg DREG_BIN;
reg INMODEREG_BIN;
reg MREG_BIN;
reg OPMODEREG_BIN;
reg PREADDINSEL_BIN;
reg PREG_BIN;
reg [1:0] SEL_MASK_BIN;
reg SEL_PATTERN_BIN;
reg [1:0] USE_MULT_BIN;
reg USE_PATTERN_DETECT_BIN;
reg [1:0] USE_SIMD_BIN;
reg USE_WIDEXOR_BIN;
reg XORSIMD_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CARRYCASCIN_in;
wire CARRYIN_in;
wire CEA1_in;
wire CEA2_in;
wire CEAD_in;
wire CEALUMODE_in;
wire CEB1_in;
wire CEB2_in;
wire CECARRYIN_in;
wire CECTRL_in;
wire CEC_in;
wire CED_in;
wire CEINMODE_in;
wire CEM_in;
wire CEP_in;
wire CLK_in;
wire MULTSIGNIN_in;
wire RSTALLCARRYIN_in;
wire RSTALUMODE_in;
wire RSTA_in;
wire RSTB_in;
wire RSTCTRL_in;
wire RSTC_in;
wire RSTD_in;
wire RSTINMODE_in;
wire RSTM_in;
wire RSTP_in;
wire [17:0] BCIN_in;
wire [17:0] B_in;
wire [26:0] D_in;
wire [29:0] ACIN_in;
wire [29:0] A_in;
wire [2:0] CARRYINSEL_in;
wire [3:0] ALUMODE_in;
wire [47:0] C_in;
wire [47:0] PCIN_in;
wire [4:0] INMODE_in;
wire [8:0] OPMODE_in;
assign ACIN_in = ACIN;
assign ALUMODE_in[0] = (ALUMODE[0] !== 1'bz) && (ALUMODE[0] ^ IS_ALUMODE_INVERTED_REG[0]); // rv 0
assign ALUMODE_in[1] = (ALUMODE[1] !== 1'bz) && (ALUMODE[1] ^ IS_ALUMODE_INVERTED_REG[1]); // rv 0
assign ALUMODE_in[2] = (ALUMODE[2] !== 1'bz) && (ALUMODE[2] ^ IS_ALUMODE_INVERTED_REG[2]); // rv 0
assign ALUMODE_in[3] = (ALUMODE[3] !== 1'bz) && (ALUMODE[3] ^ IS_ALUMODE_INVERTED_REG[3]); // rv 0
assign A_in[0] = (A[0] === 1'bz) || A[0]; // rv 1
assign A_in[10] = (A[10] === 1'bz) || A[10]; // rv 1
assign A_in[11] = (A[11] === 1'bz) || A[11]; // rv 1
assign A_in[12] = (A[12] === 1'bz) || A[12]; // rv 1
assign A_in[13] = (A[13] === 1'bz) || A[13]; // rv 1
assign A_in[14] = (A[14] === 1'bz) || A[14]; // rv 1
assign A_in[15] = (A[15] === 1'bz) || A[15]; // rv 1
assign A_in[16] = (A[16] === 1'bz) || A[16]; // rv 1
assign A_in[17] = (A[17] === 1'bz) || A[17]; // rv 1
assign A_in[18] = (A[18] === 1'bz) || A[18]; // rv 1
assign A_in[19] = (A[19] === 1'bz) || A[19]; // rv 1
assign A_in[1] = (A[1] === 1'bz) || A[1]; // rv 1
assign A_in[20] = (A[20] === 1'bz) || A[20]; // rv 1
assign A_in[21] = (A[21] === 1'bz) || A[21]; // rv 1
assign A_in[22] = (A[22] === 1'bz) || A[22]; // rv 1
assign A_in[23] = (A[23] === 1'bz) || A[23]; // rv 1
assign A_in[24] = (A[24] === 1'bz) || A[24]; // rv 1
assign A_in[25] = (A[25] === 1'bz) || A[25]; // rv 1
assign A_in[26] = (A[26] === 1'bz) || A[26]; // rv 1
assign A_in[27] = (A[27] === 1'bz) || A[27]; // rv 1
assign A_in[28] = (A[28] === 1'bz) || A[28]; // rv 1
assign A_in[29] = (A[29] === 1'bz) || A[29]; // rv 1
assign A_in[2] = (A[2] === 1'bz) || A[2]; // rv 1
assign A_in[3] = (A[3] === 1'bz) || A[3]; // rv 1
assign A_in[4] = (A[4] === 1'bz) || A[4]; // rv 1
assign A_in[5] = (A[5] === 1'bz) || A[5]; // rv 1
assign A_in[6] = (A[6] === 1'bz) || A[6]; // rv 1
assign A_in[7] = (A[7] === 1'bz) || A[7]; // rv 1
assign A_in[8] = (A[8] === 1'bz) || A[8]; // rv 1
assign A_in[9] = (A[9] === 1'bz) || A[9]; // rv 1
assign BCIN_in = BCIN;
assign B_in[0] = (B[0] === 1'bz) || B[0]; // rv 1
assign B_in[10] = (B[10] === 1'bz) || B[10]; // rv 1
assign B_in[11] = (B[11] === 1'bz) || B[11]; // rv 1
assign B_in[12] = (B[12] === 1'bz) || B[12]; // rv 1
assign B_in[13] = (B[13] === 1'bz) || B[13]; // rv 1
assign B_in[14] = (B[14] === 1'bz) || B[14]; // rv 1
assign B_in[15] = (B[15] === 1'bz) || B[15]; // rv 1
assign B_in[16] = (B[16] === 1'bz) || B[16]; // rv 1
assign B_in[17] = (B[17] === 1'bz) || B[17]; // rv 1
assign B_in[1] = (B[1] === 1'bz) || B[1]; // rv 1
assign B_in[2] = (B[2] === 1'bz) || B[2]; // rv 1
assign B_in[3] = (B[3] === 1'bz) || B[3]; // rv 1
assign B_in[4] = (B[4] === 1'bz) || B[4]; // rv 1
assign B_in[5] = (B[5] === 1'bz) || B[5]; // rv 1
assign B_in[6] = (B[6] === 1'bz) || B[6]; // rv 1
assign B_in[7] = (B[7] === 1'bz) || B[7]; // rv 1
assign B_in[8] = (B[8] === 1'bz) || B[8]; // rv 1
assign B_in[9] = (B[9] === 1'bz) || B[9]; // rv 1
assign CARRYCASCIN_in = CARRYCASCIN;
assign CARRYINSEL_in[0] = (CARRYINSEL[0] !== 1'bz) && CARRYINSEL[0]; // rv 0
assign CARRYINSEL_in[1] = (CARRYINSEL[1] !== 1'bz) && CARRYINSEL[1]; // rv 0
assign CARRYINSEL_in[2] = (CARRYINSEL[2] !== 1'bz) && CARRYINSEL[2]; // rv 0
assign CARRYIN_in = (CARRYIN !== 1'bz) && (CARRYIN ^ IS_CARRYIN_INVERTED_REG); // rv 0
assign CEA1_in = (CEA1 !== 1'bz) && CEA1; // rv 0
assign CEA2_in = (CEA2 !== 1'bz) && CEA2; // rv 0
assign CEAD_in = (CEAD !== 1'bz) && CEAD; // rv 0
assign CEALUMODE_in = (CEALUMODE !== 1'bz) && CEALUMODE; // rv 0
assign CEB1_in = (CEB1 !== 1'bz) && CEB1; // rv 0
assign CEB2_in = (CEB2 !== 1'bz) && CEB2; // rv 0
assign CECARRYIN_in = (CECARRYIN !== 1'bz) && CECARRYIN; // rv 0
assign CECTRL_in = (CECTRL !== 1'bz) && CECTRL; // rv 0
assign CEC_in = (CEC !== 1'bz) && CEC; // rv 0
assign CED_in = (CED !== 1'bz) && CED; // rv 0
assign CEINMODE_in = CEINMODE;
assign CEM_in = (CEM !== 1'bz) && CEM; // rv 0
assign CEP_in = (CEP !== 1'bz) && CEP; // rv 0
assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0
assign C_in[0] = (C[0] === 1'bz) || C[0]; // rv 1
assign C_in[10] = (C[10] === 1'bz) || C[10]; // rv 1
assign C_in[11] = (C[11] === 1'bz) || C[11]; // rv 1
assign C_in[12] = (C[12] === 1'bz) || C[12]; // rv 1
assign C_in[13] = (C[13] === 1'bz) || C[13]; // rv 1
assign C_in[14] = (C[14] === 1'bz) || C[14]; // rv 1
assign C_in[15] = (C[15] === 1'bz) || C[15]; // rv 1
assign C_in[16] = (C[16] === 1'bz) || C[16]; // rv 1
assign C_in[17] = (C[17] === 1'bz) || C[17]; // rv 1
assign C_in[18] = (C[18] === 1'bz) || C[18]; // rv 1
assign C_in[19] = (C[19] === 1'bz) || C[19]; // rv 1
assign C_in[1] = (C[1] === 1'bz) || C[1]; // rv 1
assign C_in[20] = (C[20] === 1'bz) || C[20]; // rv 1
assign C_in[21] = (C[21] === 1'bz) || C[21]; // rv 1
assign C_in[22] = (C[22] === 1'bz) || C[22]; // rv 1
assign C_in[23] = (C[23] === 1'bz) || C[23]; // rv 1
assign C_in[24] = (C[24] === 1'bz) || C[24]; // rv 1
assign C_in[25] = (C[25] === 1'bz) || C[25]; // rv 1
assign C_in[26] = (C[26] === 1'bz) || C[26]; // rv 1
assign C_in[27] = (C[27] === 1'bz) || C[27]; // rv 1
assign C_in[28] = (C[28] === 1'bz) || C[28]; // rv 1
assign C_in[29] = (C[29] === 1'bz) || C[29]; // rv 1
assign C_in[2] = (C[2] === 1'bz) || C[2]; // rv 1
assign C_in[30] = (C[30] === 1'bz) || C[30]; // rv 1
assign C_in[31] = (C[31] === 1'bz) || C[31]; // rv 1
assign C_in[32] = (C[32] === 1'bz) || C[32]; // rv 1
assign C_in[33] = (C[33] === 1'bz) || C[33]; // rv 1
assign C_in[34] = (C[34] === 1'bz) || C[34]; // rv 1
assign C_in[35] = (C[35] === 1'bz) || C[35]; // rv 1
assign C_in[36] = (C[36] === 1'bz) || C[36]; // rv 1
assign C_in[37] = (C[37] === 1'bz) || C[37]; // rv 1
assign C_in[38] = (C[38] === 1'bz) || C[38]; // rv 1
assign C_in[39] = (C[39] === 1'bz) || C[39]; // rv 1
assign C_in[3] = (C[3] === 1'bz) || C[3]; // rv 1
assign C_in[40] = (C[40] === 1'bz) || C[40]; // rv 1
assign C_in[41] = (C[41] === 1'bz) || C[41]; // rv 1
assign C_in[42] = (C[42] === 1'bz) || C[42]; // rv 1
assign C_in[43] = (C[43] === 1'bz) || C[43]; // rv 1
assign C_in[44] = (C[44] === 1'bz) || C[44]; // rv 1
assign C_in[45] = (C[45] === 1'bz) || C[45]; // rv 1
assign C_in[46] = (C[46] === 1'bz) || C[46]; // rv 1
assign C_in[47] = (C[47] === 1'bz) || C[47]; // rv 1
assign C_in[4] = (C[4] === 1'bz) || C[4]; // rv 1
assign C_in[5] = (C[5] === 1'bz) || C[5]; // rv 1
assign C_in[6] = (C[6] === 1'bz) || C[6]; // rv 1
assign C_in[7] = (C[7] === 1'bz) || C[7]; // rv 1
assign C_in[8] = (C[8] === 1'bz) || C[8]; // rv 1
assign C_in[9] = (C[9] === 1'bz) || C[9]; // rv 1
assign D_in[0] = (D[0] !== 1'bz) && D[0]; // rv 0
assign D_in[10] = (D[10] !== 1'bz) && D[10]; // rv 0
assign D_in[11] = (D[11] !== 1'bz) && D[11]; // rv 0
assign D_in[12] = (D[12] !== 1'bz) && D[12]; // rv 0
assign D_in[13] = (D[13] !== 1'bz) && D[13]; // rv 0
assign D_in[14] = (D[14] !== 1'bz) && D[14]; // rv 0
assign D_in[15] = (D[15] !== 1'bz) && D[15]; // rv 0
assign D_in[16] = (D[16] !== 1'bz) && D[16]; // rv 0
assign D_in[17] = (D[17] !== 1'bz) && D[17]; // rv 0
assign D_in[18] = (D[18] !== 1'bz) && D[18]; // rv 0
assign D_in[19] = (D[19] !== 1'bz) && D[19]; // rv 0
assign D_in[1] = (D[1] !== 1'bz) && D[1]; // rv 0
assign D_in[20] = (D[20] !== 1'bz) && D[20]; // rv 0
assign D_in[21] = (D[21] !== 1'bz) && D[21]; // rv 0
assign D_in[22] = (D[22] !== 1'bz) && D[22]; // rv 0
assign D_in[23] = (D[23] !== 1'bz) && D[23]; // rv 0
assign D_in[24] = (D[24] !== 1'bz) && D[24]; // rv 0
assign D_in[25] = (D[25] !== 1'bz) && D[25]; // rv 0
assign D_in[26] = (D[26] !== 1'bz) && D[26]; // rv 0
assign D_in[2] = (D[2] !== 1'bz) && D[2]; // rv 0
assign D_in[3] = (D[3] !== 1'bz) && D[3]; // rv 0
assign D_in[4] = (D[4] !== 1'bz) && D[4]; // rv 0
assign D_in[5] = (D[5] !== 1'bz) && D[5]; // rv 0
assign D_in[6] = (D[6] !== 1'bz) && D[6]; // rv 0
assign D_in[7] = (D[7] !== 1'bz) && D[7]; // rv 0
assign D_in[8] = (D[8] !== 1'bz) && D[8]; // rv 0
assign D_in[9] = (D[9] !== 1'bz) && D[9]; // rv 0
assign INMODE_in[0] = (INMODE[0] !== 1'bz) && (INMODE[0] ^ IS_INMODE_INVERTED_REG[0]); // rv 0
assign INMODE_in[1] = (INMODE[1] !== 1'bz) && (INMODE[1] ^ IS_INMODE_INVERTED_REG[1]); // rv 0
assign INMODE_in[2] = (INMODE[2] !== 1'bz) && (INMODE[2] ^ IS_INMODE_INVERTED_REG[2]); // rv 0
assign INMODE_in[3] = (INMODE[3] !== 1'bz) && (INMODE[3] ^ IS_INMODE_INVERTED_REG[3]); // rv 0
assign INMODE_in[4] = (INMODE[4] !== 1'bz) && (INMODE[4] ^ IS_INMODE_INVERTED_REG[4]); // rv 0
assign MULTSIGNIN_in = MULTSIGNIN;
assign OPMODE_in[0] = (OPMODE[0] !== 1'bz) && (OPMODE[0] ^ IS_OPMODE_INVERTED_REG[0]); // rv 0
assign OPMODE_in[1] = (OPMODE[1] !== 1'bz) && (OPMODE[1] ^ IS_OPMODE_INVERTED_REG[1]); // rv 0
assign OPMODE_in[2] = (OPMODE[2] !== 1'bz) && (OPMODE[2] ^ IS_OPMODE_INVERTED_REG[2]); // rv 0
assign OPMODE_in[3] = (OPMODE[3] !== 1'bz) && (OPMODE[3] ^ IS_OPMODE_INVERTED_REG[3]); // rv 0
assign OPMODE_in[4] = (OPMODE[4] !== 1'bz) && (OPMODE[4] ^ IS_OPMODE_INVERTED_REG[4]); // rv 0
assign OPMODE_in[5] = (OPMODE[5] !== 1'bz) && (OPMODE[5] ^ IS_OPMODE_INVERTED_REG[5]); // rv 0
assign OPMODE_in[6] = (OPMODE[6] !== 1'bz) && (OPMODE[6] ^ IS_OPMODE_INVERTED_REG[6]); // rv 0
assign OPMODE_in[7] = (OPMODE[7] !== 1'bz) && (OPMODE[7] ^ IS_OPMODE_INVERTED_REG[7]); // rv 0
assign OPMODE_in[8] = (OPMODE[8] !== 1'bz) && (OPMODE[8] ^ IS_OPMODE_INVERTED_REG[8]); // rv 0
assign PCIN_in = PCIN;
assign RSTALLCARRYIN_in = (RSTALLCARRYIN !== 1'bz) && (RSTALLCARRYIN ^ IS_RSTALLCARRYIN_INVERTED_REG); // rv 0
assign RSTALUMODE_in = (RSTALUMODE !== 1'bz) && (RSTALUMODE ^ IS_RSTALUMODE_INVERTED_REG); // rv 0
assign RSTA_in = (RSTA !== 1'bz) && (RSTA ^ IS_RSTA_INVERTED_REG); // rv 0
assign RSTB_in = (RSTB !== 1'bz) && (RSTB ^ IS_RSTB_INVERTED_REG); // rv 0
assign RSTCTRL_in = (RSTCTRL !== 1'bz) && (RSTCTRL ^ IS_RSTCTRL_INVERTED_REG); // rv 0
assign RSTC_in = (RSTC !== 1'bz) && (RSTC ^ IS_RSTC_INVERTED_REG); // rv 0
assign RSTD_in = (RSTD !== 1'bz) && (RSTD ^ IS_RSTD_INVERTED_REG); // rv 0
assign RSTINMODE_in = (RSTINMODE !== 1'bz) && (RSTINMODE ^ IS_RSTINMODE_INVERTED_REG); // rv 0
assign RSTM_in = (RSTM !== 1'bz) && (RSTM ^ IS_RSTM_INVERTED_REG); // rv 0
assign RSTP_in = (RSTP !== 1'bz) && (RSTP ^ IS_RSTP_INVERTED_REG); // rv 0
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign ACASCREG_BIN = ACASCREG_REG[1:0];
assign ADREG_BIN = ADREG_REG[0];
assign ALUMODEREG_BIN = ALUMODEREG_REG[0];
assign AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
assign AREG_BIN = AREG_REG[1:0];
assign AUTORESET_PATDET_BIN =
(AUTORESET_PATDET_REG == "NO_RESET") ? AUTORESET_PATDET_NO_RESET :
(AUTORESET_PATDET_REG == "RESET_MATCH") ? AUTORESET_PATDET_RESET_MATCH :
(AUTORESET_PATDET_REG == "RESET_NOT_MATCH") ? AUTORESET_PATDET_RESET_NOT_MATCH :
AUTORESET_PATDET_NO_RESET;
assign AUTORESET_PRIORITY_BIN =
(AUTORESET_PRIORITY_REG == "RESET") ? AUTORESET_PRIORITY_RESET :
(AUTORESET_PRIORITY_REG == "CEP") ? AUTORESET_PRIORITY_CEP :
AUTORESET_PRIORITY_RESET;
assign A_INPUT_BIN =
(A_INPUT_REG == "DIRECT") ? A_INPUT_DIRECT :
(A_INPUT_REG == "CASCADE") ? A_INPUT_CASCADE :
A_INPUT_DIRECT;
assign BCASCREG_BIN = BCASCREG_REG[1:0];
assign BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
assign BREG_BIN = BREG_REG[1:0];
assign B_INPUT_BIN =
(B_INPUT_REG == "DIRECT") ? B_INPUT_DIRECT :
(B_INPUT_REG == "CASCADE") ? B_INPUT_CASCADE :
B_INPUT_DIRECT;
assign CARRYINREG_BIN = CARRYINREG_REG[0];
assign CARRYINSELREG_BIN = CARRYINSELREG_REG[0];
assign CREG_BIN = CREG_REG[0];
assign DREG_BIN = DREG_REG[0];
assign INMODEREG_BIN = INMODEREG_REG[0];
assign MREG_BIN = MREG_REG[0];
assign OPMODEREG_BIN = OPMODEREG_REG[0];
assign PREADDINSEL_BIN =
(PREADDINSEL_REG == "A") ? PREADDINSEL_A :
(PREADDINSEL_REG == "B") ? PREADDINSEL_B :
PREADDINSEL_A;
assign PREG_BIN = PREG_REG[0];
assign SEL_MASK_BIN =
(SEL_MASK_REG == "MASK") ? SEL_MASK_MASK :
(SEL_MASK_REG == "C") ? SEL_MASK_C :
(SEL_MASK_REG == "ROUNDING_MODE1") ? SEL_MASK_ROUNDING_MODE1 :
(SEL_MASK_REG == "ROUNDING_MODE2") ? SEL_MASK_ROUNDING_MODE2 :
SEL_MASK_MASK;
assign SEL_PATTERN_BIN =
(SEL_PATTERN_REG == "PATTERN") ? SEL_PATTERN_PATTERN :
(SEL_PATTERN_REG == "C") ? SEL_PATTERN_C :
SEL_PATTERN_PATTERN;
assign USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
assign USE_PATTERN_DETECT_BIN =
(USE_PATTERN_DETECT_REG == "NO_PATDET") ? USE_PATTERN_DETECT_NO_PATDET :
(USE_PATTERN_DETECT_REG == "PATDET") ? USE_PATTERN_DETECT_PATDET :
USE_PATTERN_DETECT_NO_PATDET;
assign USE_SIMD_BIN =
(USE_SIMD_REG == "ONE48") ? USE_SIMD_ONE48 :
(USE_SIMD_REG == "FOUR12") ? USE_SIMD_FOUR12 :
(USE_SIMD_REG == "TWO24") ? USE_SIMD_TWO24 :
USE_SIMD_ONE48;
assign USE_WIDEXOR_BIN =
(USE_WIDEXOR_REG == "FALSE") ? USE_WIDEXOR_FALSE :
(USE_WIDEXOR_REG == "TRUE") ? USE_WIDEXOR_TRUE :
USE_WIDEXOR_FALSE;
assign XORSIMD_BIN =
(XORSIMD_REG == "XOR24_48_96") ? XORSIMD_XOR24_48_96 :
(XORSIMD_REG == "XOR12") ? XORSIMD_XOR12 :
XORSIMD_XOR24_48_96;
`else
always @(trig_attr) begin
#1;
ACASCREG_BIN = ACASCREG_REG[1:0];
ADREG_BIN = ADREG_REG[0];
ALUMODEREG_BIN = ALUMODEREG_REG[0];
AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
AREG_BIN = AREG_REG[1:0];
AUTORESET_PATDET_BIN =
(AUTORESET_PATDET_REG == "NO_RESET") ? AUTORESET_PATDET_NO_RESET :
(AUTORESET_PATDET_REG == "RESET_MATCH") ? AUTORESET_PATDET_RESET_MATCH :
(AUTORESET_PATDET_REG == "RESET_NOT_MATCH") ? AUTORESET_PATDET_RESET_NOT_MATCH :
AUTORESET_PATDET_NO_RESET;
AUTORESET_PRIORITY_BIN =
(AUTORESET_PRIORITY_REG == "RESET") ? AUTORESET_PRIORITY_RESET :
(AUTORESET_PRIORITY_REG == "CEP") ? AUTORESET_PRIORITY_CEP :
AUTORESET_PRIORITY_RESET;
A_INPUT_BIN =
(A_INPUT_REG == "DIRECT") ? A_INPUT_DIRECT :
(A_INPUT_REG == "CASCADE") ? A_INPUT_CASCADE :
A_INPUT_DIRECT;
BCASCREG_BIN = BCASCREG_REG[1:0];
BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
BREG_BIN = BREG_REG[1:0];
B_INPUT_BIN =
(B_INPUT_REG == "DIRECT") ? B_INPUT_DIRECT :
(B_INPUT_REG == "CASCADE") ? B_INPUT_CASCADE :
B_INPUT_DIRECT;
CARRYINREG_BIN = CARRYINREG_REG[0];
CARRYINSELREG_BIN = CARRYINSELREG_REG[0];
CREG_BIN = CREG_REG[0];
DREG_BIN = DREG_REG[0];
INMODEREG_BIN = INMODEREG_REG[0];
MREG_BIN = MREG_REG[0];
OPMODEREG_BIN = OPMODEREG_REG[0];
PREADDINSEL_BIN =
(PREADDINSEL_REG == "A") ? PREADDINSEL_A :
(PREADDINSEL_REG == "B") ? PREADDINSEL_B :
PREADDINSEL_A;
PREG_BIN = PREG_REG[0];
SEL_MASK_BIN =
(SEL_MASK_REG == "MASK") ? SEL_MASK_MASK :
(SEL_MASK_REG == "C") ? SEL_MASK_C :
(SEL_MASK_REG == "ROUNDING_MODE1") ? SEL_MASK_ROUNDING_MODE1 :
(SEL_MASK_REG == "ROUNDING_MODE2") ? SEL_MASK_ROUNDING_MODE2 :
SEL_MASK_MASK;
SEL_PATTERN_BIN =
(SEL_PATTERN_REG == "PATTERN") ? SEL_PATTERN_PATTERN :
(SEL_PATTERN_REG == "C") ? SEL_PATTERN_C :
SEL_PATTERN_PATTERN;
USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
USE_PATTERN_DETECT_BIN =
(USE_PATTERN_DETECT_REG == "NO_PATDET") ? USE_PATTERN_DETECT_NO_PATDET :
(USE_PATTERN_DETECT_REG == "PATDET") ? USE_PATTERN_DETECT_PATDET :
USE_PATTERN_DETECT_NO_PATDET;
USE_SIMD_BIN =
(USE_SIMD_REG == "ONE48") ? USE_SIMD_ONE48 :
(USE_SIMD_REG == "FOUR12") ? USE_SIMD_FOUR12 :
(USE_SIMD_REG == "TWO24") ? USE_SIMD_TWO24 :
USE_SIMD_ONE48;
USE_WIDEXOR_BIN =
(USE_WIDEXOR_REG == "FALSE") ? USE_WIDEXOR_FALSE :
(USE_WIDEXOR_REG == "TRUE") ? USE_WIDEXOR_TRUE :
USE_WIDEXOR_FALSE;
XORSIMD_BIN =
(XORSIMD_REG == "XOR24_48_96") ? XORSIMD_XOR24_48_96 :
(XORSIMD_REG == "XOR12") ? XORSIMD_XOR12 :
XORSIMD_XOR24_48_96;
end
`endif
`ifndef XIL_XECLIB
always @(trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((ACASCREG_REG != 1) &&
(ACASCREG_REG != 0) &&
(ACASCREG_REG != 2))) begin
$display("Error: [Unisim %s-101] ACASCREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, ACASCREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ADREG_REG != 1) &&
(ADREG_REG != 0))) begin
$display("Error: [Unisim %s-102] ADREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, ADREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALUMODEREG_REG != 1) &&
(ALUMODEREG_REG != 0))) begin
$display("Error: [Unisim %s-103] ALUMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, ALUMODEREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AMULTSEL_REG != "A") &&
(AMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-104] AMULTSEL attribute is set to %s. Legal values for this attribute are A or AD. Instance: %m", MODULE_NAME, AMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AREG_REG != 1) &&
(AREG_REG != 0) &&
(AREG_REG != 2))) begin
$display("Error: [Unisim %s-105] AREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, AREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AUTORESET_PATDET_REG != "NO_RESET") &&
(AUTORESET_PATDET_REG != "RESET_MATCH") &&
(AUTORESET_PATDET_REG != "RESET_NOT_MATCH"))) begin
$display("Error: [Unisim %s-106] AUTORESET_PATDET attribute is set to %s. Legal values for this attribute are NO_RESET, RESET_MATCH or RESET_NOT_MATCH. Instance: %m", MODULE_NAME, AUTORESET_PATDET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AUTORESET_PRIORITY_REG != "RESET") &&
(AUTORESET_PRIORITY_REG != "CEP"))) begin
$display("Error: [Unisim %s-107] AUTORESET_PRIORITY attribute is set to %s. Legal values for this attribute are RESET or CEP. Instance: %m", MODULE_NAME, AUTORESET_PRIORITY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_INPUT_REG != "DIRECT") &&
(A_INPUT_REG != "CASCADE"))) begin
$display("Error: [Unisim %s-108] A_INPUT attribute is set to %s. Legal values for this attribute are DIRECT or CASCADE. Instance: %m", MODULE_NAME, A_INPUT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BCASCREG_REG != 1) &&
(BCASCREG_REG != 0) &&
(BCASCREG_REG != 2))) begin
$display("Error: [Unisim %s-109] BCASCREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, BCASCREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BMULTSEL_REG != "B") &&
(BMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-110] BMULTSEL attribute is set to %s. Legal values for this attribute are B or AD. Instance: %m", MODULE_NAME, BMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BREG_REG != 1) &&
(BREG_REG != 0) &&
(BREG_REG != 2))) begin
$display("Error: [Unisim %s-111] BREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, BREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((B_INPUT_REG != "DIRECT") &&
(B_INPUT_REG != "CASCADE"))) begin
$display("Error: [Unisim %s-112] B_INPUT attribute is set to %s. Legal values for this attribute are DIRECT or CASCADE. Instance: %m", MODULE_NAME, B_INPUT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CARRYINREG_REG != 1) &&
(CARRYINREG_REG != 0))) begin
$display("Error: [Unisim %s-113] CARRYINREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CARRYINREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CARRYINSELREG_REG != 1) &&
(CARRYINSELREG_REG != 0))) begin
$display("Error: [Unisim %s-114] CARRYINSELREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CARRYINSELREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CREG_REG != 1) &&
(CREG_REG != 0))) begin
$display("Error: [Unisim %s-115] CREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DREG_REG != 1) &&
(DREG_REG != 0))) begin
$display("Error: [Unisim %s-116] DREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, DREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INMODEREG_REG != 1) &&
(INMODEREG_REG != 0))) begin
$display("Error: [Unisim %s-117] INMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, INMODEREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MREG_REG != 1) &&
(MREG_REG != 0))) begin
$display("Error: [Unisim %s-134] MREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, MREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OPMODEREG_REG != 1) &&
(OPMODEREG_REG != 0))) begin
$display("Error: [Unisim %s-135] OPMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, OPMODEREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PREADDINSEL_REG != "A") &&
(PREADDINSEL_REG != "B"))) begin
$display("Error: [Unisim %s-137] PREADDINSEL attribute is set to %s. Legal values for this attribute are A or B. Instance: %m", MODULE_NAME, PREADDINSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PREG_REG != 1) &&
(PREG_REG != 0))) begin
$display("Error: [Unisim %s-138] PREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, PREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SEL_MASK_REG != "MASK") &&
(SEL_MASK_REG != "C") &&
(SEL_MASK_REG != "ROUNDING_MODE1") &&
(SEL_MASK_REG != "ROUNDING_MODE2"))) begin
$display("Error: [Unisim %s-140] SEL_MASK attribute is set to %s. Legal values for this attribute are MASK, C, ROUNDING_MODE1 or ROUNDING_MODE2. Instance: %m", MODULE_NAME, SEL_MASK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SEL_PATTERN_REG != "PATTERN") &&
(SEL_PATTERN_REG != "C"))) begin
$display("Error: [Unisim %s-141] SEL_PATTERN attribute is set to %s. Legal values for this attribute are PATTERN or C. Instance: %m", MODULE_NAME, SEL_PATTERN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_MULT_REG != "MULTIPLY") &&
(USE_MULT_REG != "DYNAMIC") &&
(USE_MULT_REG != "NONE"))) begin
$display("Error: [Unisim %s-142] USE_MULT attribute is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE. Instance: %m", MODULE_NAME, USE_MULT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_PATTERN_DETECT_REG != "NO_PATDET") &&
(USE_PATTERN_DETECT_REG != "PATDET"))) begin
$display("Error: [Unisim %s-143] USE_PATTERN_DETECT attribute is set to %s. Legal values for this attribute are NO_PATDET or PATDET. Instance: %m", MODULE_NAME, USE_PATTERN_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_SIMD_REG != "ONE48") &&
(USE_SIMD_REG != "FOUR12") &&
(USE_SIMD_REG != "TWO24"))) begin
$display("Error: [Unisim %s-144] USE_SIMD attribute is set to %s. Legal values for this attribute are ONE48, FOUR12 or TWO24. Instance: %m", MODULE_NAME, USE_SIMD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_WIDEXOR_REG != "FALSE") &&
(USE_WIDEXOR_REG != "TRUE"))) begin
$display("Error: [Unisim %s-145] USE_WIDEXOR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_WIDEXOR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XORSIMD_REG != "XOR24_48_96") &&
(XORSIMD_REG != "XOR12"))) begin
$display("Error: [Unisim %s-146] XORSIMD attribute is set to %s. Legal values for this attribute are XOR24_48_96 or XOR12. Instance: %m", MODULE_NAME, XORSIMD_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
// begin behavioral model
always @(trig_attr) begin
#1;
case (AREG_REG)
0, 1 : if (AREG_REG != ACASCREG_REG) begin
$display("Error: [Unisim %s-2] AREG attribute is set to %0d and ACASCREG attribute is set to %0d. When AREG is 0 or 1, ACASCREG must be set to the same value. Instance: %m", MODULE_NAME, AREG_REG, ACASCREG_REG);
attr_err = 1'b1;
end
2 : if (ACASCREG_REG == 0) begin
$display("Error: [Unisim %s-3] AREG attribute is set to %0d and ACASCREG attribute is set to %0d. When AREG is 2, ACASCREG must be set to 1 or 2. Instance: %m", MODULE_NAME, AREG_REG, ACASCREG_REG);
attr_err = 1'b1;
end
endcase
case (BREG_REG)
0, 1 : if (BREG_REG != BCASCREG_REG) begin
$display("Error: [Unisim %s-4] BREG attribute is set to %0d and BCASCREG attribute is set to %0d. When BREG is 0 or 1, BCASCREG must be set to the same value. Instance: %m", MODULE_NAME, BREG_REG, BCASCREG_REG);
attr_err = 1'b1;
end
2 : if (BCASCREG_REG == 0) begin
$display("Error: [Unisim %s-5] BREG attribute is set to %0d and BCASCREG attribute is set to %0d. When BREG is 2, BCASCREG must be set to 1 or 2. Instance: %m", MODULE_NAME, BREG_REG, BCASCREG_REG);
attr_err = 1'b1;
end
endcase
if (attr_err == 1'b1) #1 $finish;
end
always @(trig_attr) begin
#1;
if ((USE_MULT_REG == "NONE") && (MREG_REG !== 0)) begin
$display("Error : [Unisim %s-6] : Attribute USE_MULT is set to \"NONE\" and MREG is set to %d. MREG must be set to 0 when the multiplier is not used. Instance %m", MODULE_NAME, MREG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
// Connections between atoms
wire [44:0] U_DATA;
wire [44:0] V_DATA;
reg [26:0] A2A1;
reg [17:0] B2B1;
wire AMULT26_in;
wire BMULT17_in;
wire ALUMODE10_in;
wire CCOUT_in;
wire MULTSIGN_ALU_in;
wire P_FDBK_47_in;
wire [26:0] AD_DATA;
wire [26:0] AD_in;
wire [26:0] D_DATA;
wire [26:0] PREADD_AB;
wire [3:0] COUT_in;
wire [44:0] U_in;
wire [44:0] V_in;
wire [44:0] U_DATA_in;
wire [44:0] V_DATA_in;
wire [47:0] ALU_OUT_in;
wire [47:0] C_DATA_in;
wire [47:0] P_FDBK_in;
wire [7:0] XOR_MX_in;
// DSP_ALU wires
localparam MAX_ALU_FULL = 48;
localparam MAX_CARRYOUT = 4;
localparam A_WIDTH = 30;
localparam B_WIDTH = 18;
localparam C_WIDTH = 48;
localparam D_WIDTH = 27;
localparam M_WIDTH = 45;
localparam P_WIDTH = 48;
reg cci_drc_msg;
reg cis_drc_msg;
wire CARRYIN_mux;
reg CARRYIN_reg;
reg [3:0] ALUMODE_reg;
reg [2:0] CARRYINSEL_mux;
reg [2:0] CARRYINSEL_reg;
reg [8:0] OPMODE_mux;
reg [8:0] OPMODE_reg;
wire [47:0] x_mac_cascd;
reg [47:0] wmux;
reg [47:0] xmux;
reg [47:0] ymux;
reg [47:0] zmux;
wire [47:0] z_optinv;
wire cin;
reg cin_b;
wire rst_carryin_g;
reg qmultcarryin;
wire c_mult;
wire ce_m_g;
wire d_carryin_int;
wire dr_carryin_int;
wire multcarryin_data;
reg invalid_opmode;
reg opmode_valid_flag_dal; // used in OPMODE DRC
reg ping_opmode_drc_check;
wire [MAX_ALU_FULL-1:0] co;
wire [MAX_ALU_FULL-1:0] s;
wire [MAX_ALU_FULL-1:0] comux;
wire [MAX_ALU_FULL-1:0] comux_w;
wire [MAX_ALU_FULL-1:0] comux4simd;
wire [MAX_ALU_FULL-1:0] smux;
wire [MAX_ALU_FULL-1:0] smux_w;
wire [MAX_ALU_FULL:0] a_int;
wire [12:0] s0;
wire cout0;
wire intc1;
wire co12_lsb;
wire [12:0] s1;
wire cout1;
wire intc2;
wire co24_lsb;
wire [12:0] s2;
wire cout2;
wire intc3;
wire co36_lsb;
wire [13:0] s3;
wire cout3;
wire cout4;
wire xor_12a;
wire xor_12b;
wire xor_12c;
wire xor_12d;
wire xor_12e;
wire xor_12f;
wire xor_12g;
wire xor_12h;
wire xor_24a;
wire xor_24b;
wire xor_24c;
wire xor_24d;
wire xor_48a;
wire xor_48b;
wire xor_96;
wire cout_0;
wire cout_1;
wire cout_2;
wire cout_3;
wire mult_or_logic;
// DSP_A_B_DATA wires
reg [29:0] A1_reg;
reg [29:0] A2_reg;
wire [A_WIDTH-1:0] A_ALU;
reg [17:0] B2_reg;
reg [B_WIDTH-1:0] B1_DATA_out;
wire [B_WIDTH-1:0] B2_DATA;
wire [B_WIDTH-1:0] B_ALU;
// DSP_C_DATA wires
reg [C_WIDTH-1:0] C_reg;
// DSP_MULTIPLIER wires
reg [17:0] b_mult_mux;
reg [26:0] a_mult_mux;
reg [M_WIDTH-1:0] mult;
reg [M_WIDTH-2:0] ps_u_mask;
reg [M_WIDTH-2:0] ps_v_mask;
// DSP_M_DATA wires
reg [M_WIDTH-1:0] U_DATA_reg;
reg [M_WIDTH-1:0] V_DATA_reg;
// DSP_OUTPUT wires
wire the_auto_reset_patdet;
wire auto_reset_pri;
wire [47:0] the_mask;
wire [47:0] the_pattern;
reg opmode_valid_flag_dou = 1'b1; // TODO
reg [3:0] COUT_reg;
reg ALUMODE10_reg;
wire ALUMODE10_mux;
reg MULTSIGN_ALU_reg;
reg [47:0] ALU_OUT_reg;
reg [7:0] XOR_MX_reg;
wire pdet_o;
wire pdetb_o;
wire pdet_o_mux;
wire pdetb_o_mux;
wire overflow_data;
wire underflow_data;
reg pdet_o_reg1;
reg pdet_o_reg2;
reg pdetb_o_reg1;
reg pdetb_o_reg2;
// DSP_PREADD wires
wire [26:0] D_DATA_mux;
// DSP_PREADD_DATA wires
wire [4:0] INMODE_mux;
reg [4:0] INMODE_reg;
reg [D_WIDTH-1:0] AD_DATA_reg;
reg [D_WIDTH-1:0] D_DATA_reg;
// atom interconnect
assign U_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? U_DATA : 45'h100000000000;
assign V_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? V_DATA : 45'h100000000000;
reg [3:0] ALUMODE_DATA;
reg DREG_INT;
reg ADREG_INT;
// initialize regs
`ifndef XIL_XECLIB
initial begin
cci_drc_msg = 1'b0;
cis_drc_msg = 1'b0;
CARRYIN_reg = 1'b0;
ALUMODE_reg = 4'b0;
CARRYINSEL_mux = 3'b0;
CARRYINSEL_reg = 3'b0;
OPMODE_mux = 9'b0;
OPMODE_reg = 9'b0;
wmux = 48'b0;
xmux = 48'b0;
ymux = 48'b0;
zmux = 48'b0;
cin_b = 1'b0;
qmultcarryin = 1'b0;
invalid_opmode = 1'b1;
opmode_valid_flag_dal = 1'b1;
ping_opmode_drc_check = 1'b0;
A1_reg = 30'b0;
A2_reg = 30'b0;
B2_reg = 18'b0;
B1_DATA_out = {B_WIDTH{1'b0}};
C_reg = {C_WIDTH{1'b0}};
ps_u_mask = 44'h55555555555;
ps_v_mask = 44'haaaaaaaaaaa;
U_DATA_reg = {1'b0, {M_WIDTH-1{1'b0}}};
V_DATA_reg = {1'b0, {M_WIDTH-1{1'b0}}};
COUT_reg = 4'b0000;
ALUMODE10_reg = 1'b0;
MULTSIGN_ALU_reg = 1'b0;
ALU_OUT_reg = 48'b0;
XOR_MX_reg = 8'b0;
pdet_o_reg1 = 1'b0;
pdet_o_reg2 = 1'b0;
pdetb_o_reg1 = 1'b0;
pdetb_o_reg2 = 1'b0;
INMODE_reg = 5'b0;
AD_DATA_reg = {D_WIDTH{1'b0}};
D_DATA_reg = {D_WIDTH{1'b0}};
end
`endif
// DSP_ALU
//*** W mux NB
always @(OPMODE_mux[8:7] or P_FDBK_in or RND_REG or C_DATA_in)
case (OPMODE_mux[8:7])
2'b00 : wmux = 48'b0;
2'b01 : wmux = P_FDBK_in;
2'b10 : wmux = RND_REG;
2'b11 : wmux = C_DATA_in;
default : wmux = {48{1'bx}};
endcase
// To support MAC-cascade add multsignin to bit 1 of X
assign x_mac_cascd = (OPMODE_mux[6:4] == 3'b100) ? {{46{1'b0}},MULTSIGNIN_in,1'b0} : {48{1'b0}};
//*** X mux NB
always @(U_DATA_in or P_FDBK_in or A_ALU or B_ALU or OPMODE_mux[1:0] or x_mac_cascd)
case (OPMODE_mux[1:0])
2'b00 : xmux = x_mac_cascd;
2'b01 : xmux = {{3{U_DATA_in[44]}}, U_DATA_in};
2'b10 : xmux = P_FDBK_in;
2'b11 : xmux = {A_ALU, B_ALU};
default : xmux = {48{1'bx}};
endcase
//*** Y mux NB
always @(OPMODE_mux[3:2] or V_DATA_in or C_DATA_in)
case (OPMODE_mux[3:2])
2'b00 : ymux = 48'b0;
2'b01 : ymux = {{3{1'b0}}, V_DATA_in};
2'b10 : ymux = {48{1'b1}};
2'b11 : ymux = C_DATA_in;
default : ymux = {48{1'bx}};
endcase
//*** Z mux NB
always @(OPMODE_mux[6:4] or PCIN_in or P_FDBK_in or C_DATA_in or P_FDBK_47_in)
casex (OPMODE_mux[6:4])
3'b000 : zmux = 48'b0;
3'b001 : zmux = PCIN_in;
3'b010 : zmux = P_FDBK_in;
3'b011 : zmux = C_DATA_in;
3'b100 : zmux = P_FDBK_in;
3'b101 : zmux = {{9{PCIN_in[47]}}, {8{PCIN_in[47]}}, PCIN_in[47:17]};
3'b11x : zmux = {{9{P_FDBK_47_in}}, {8{P_FDBK_in[47]}}, P_FDBK_in[47:17]};
default : zmux = {48{1'bx}};
endcase
//*********************************************************
//*** CARRYINSEL and OPMODE with 1 level of register
//*********************************************************
always @(posedge CLK_in) begin
if (RSTCTRL_in || glblGSR) begin
OPMODE_reg <= 9'b0;
end
else if (CECTRL_in) begin
OPMODE_reg <= OPMODE_in;
end
end
always @(posedge CLK_in) begin
if (RSTCTRL_in || glblGSR) begin
CARRYINSEL_reg <= 3'b0;
end
else if (CECTRL_in) begin
CARRYINSEL_reg <= CARRYINSEL_in;
end
end
always @(*) CARRYINSEL_mux = (CARRYINSELREG_BIN == 1'b1) ? CARRYINSEL_reg : CARRYINSEL_in;
always @(*) begin
if (OPMODEREG_BIN == 1'b1) OPMODE_mux = OPMODE_reg;
else OPMODE_mux = OPMODE_in;
end
always @(CARRYINSEL_mux or CARRYCASCIN_in or MULTSIGNIN_in or OPMODE_mux) begin
if (CARRYINSEL_mux == 3'b010) begin
if (!((MULTSIGNIN_in === 1'bx) || (cci_drc_msg == 1'b1) ||
((OPMODE_mux == 9'b001001000) && !(MULTSIGNIN_in === 1'bx)) ||
((MULTSIGNIN_in == 1'b0) && (CARRYCASCIN_in == 1'b0)))) begin
$display("DRC warning : [Unisim %s-7] CARRYCASCIN can only be used in the current %s if the previous %s is performing a two input ADD or SUBRTACT operation or the current %s is configured in the MAC extend opmode 7'b1001000 at %.3f ns. Instance %m\n", MODULE_NAME, MODULE_NAME, MODULE_NAME, MODULE_NAME, $time/1000.0);
// CR 619940 -- Enhanced DRC warning
$display("The simulation model does not know the placement of the %s slices used, so it cannot fully confirm the above warning. It is necessary to view the placement of the %s slices and ensure that these warnings are not being breached\n", MODULE_NAME, MODULE_NAME);
cci_drc_msg = 1'b1;
end
if (!((MULTSIGNIN_in === 1'bx) || (OPMODE_mux[3:0] != 4'b0101))) begin
$display("DRC warning : [Unisim %s-10] CARRYINSEL is set to 010 with OPMODE set to multiplication (xxx0101). This is an illegal mode and may show deviation between simulation results and hardware behavior. %s instance %m at %.3f ns.", MODULE_NAME, MODULE_NAME, $time/1000.0);
end
if (!((MULTSIGNIN_in === 1'bx) || (cis_drc_msg == 1'b1) ||
(OPMODEREG_BIN == 1'b1))) begin
$display("DRC warning : [Unisim %s-11] CARRYINSEL is set to 010 with OPMODEREG set to 0. This causes unknown values after reset occurs. It is suggested to use OPMODEREG = 1 when cascading large adders. %s instance %m at %.3f ns.", MODULE_NAME, MODULE_NAME, $time/1000.0);
cis_drc_msg = 1'b1;
end
end
end
//*********************************************************
//*** ALUMODE with 1 level of register
//*********************************************************
always @(posedge CLK_in) begin
if (RSTALUMODE_in || glblGSR)
ALUMODE_reg <= 4'b0;
else if (CEALUMODE_in)
ALUMODE_reg <= ALUMODE_in;
end
always @(*) ALUMODE_DATA = (ALUMODEREG_BIN == 1'b1) ? ALUMODE_reg : ALUMODE_in;
//------------------------------------------------------------------
//*** DRC for OPMODE
//------------------------------------------------------------------
// needs PREG from output block
// ~2000 lines code - skip for now - copy/rework from DSP48E1.
//--####################################################################
//--##### ALU #####
//--####################################################################
// ADDSUB block - first stage of ALU develops sums and carries for Final Adder
// Invert Z for subtract operation using alumode<0>
assign z_optinv = {48{ALUMODE_DATA[0]}} ^ zmux;
// Add W, X, Y, Z carry-save style; basically full adder logic below
assign co = ((xmux & ymux)|(z_optinv & ymux)|(xmux & z_optinv));
// s has a fan-out of 2 (1) FA with W (2) second leg of XOR tree
assign s = (z_optinv^xmux^ymux);
// Mux S and CO to do 2 operands logic operations
// S = produce XOR/XNOR, NOT functions
// CO = produce AND/NAND, OR/NOR functions
assign comux = ALUMODE_DATA[2] ? 0 : co;
assign smux = ALUMODE_DATA[3] ? co : s;
// Carry mux to handle SIMD mode
// SIMD must be used here since addition of W requires carry propogation
assign comux4simd = {
comux[47:36],
comux[35]&&(USE_SIMD_BIN != USE_SIMD_FOUR12),
comux[34:24],
comux[23]&&(USE_SIMD_BIN == USE_SIMD_ONE48),
comux[22:12],
comux[11]&&(USE_SIMD_BIN != USE_SIMD_FOUR12),
comux[10:0]
};
// FA to combine W-mux with s and co
// comux must be shifted to properly reflect carry operation
assign smux_w = smux ^ {comux4simd[46:0],1'b0} ^ wmux;
assign comux_w = ((smux & {comux4simd[46:0],1'b0}) |
(wmux & {comux4simd[46:0],1'b0}) |
(smux & wmux));
// alumode10 indicates a subtraction, used to correct carryout polarity
assign ALUMODE10_in = (ALUMODE_DATA[0] & ALUMODE_DATA[1]);
// prepare data for Final Adder
// a[0] is in fact the cin bit, adder inputs: a[48:1], b[47:0], cin= a[0]
assign a_int = {comux_w, cin};
// assign b_int = smux_w;
// FINAL ADDER - second stage develops final sums and carries
assign s0 = a_int[11:0] + smux_w[11:0];
// invert if alumode10
assign cout0 = ALUMODE10_in ^ (a_int[12] ^ s0[12] ^ comux[11]);
// internal carry is zero'd out on mc_simd == 1
assign intc1 = (USE_SIMD_BIN != USE_SIMD_FOUR12) && s0[12];
// next lsb is zero'd out on mc_simd == 1
assign co12_lsb = (USE_SIMD_BIN != USE_SIMD_FOUR12) && a_int[12];
//
assign s1 = {a_int[23:13],co12_lsb} + smux_w[23:12] + intc1;
assign cout1 = ALUMODE10_in ^ (a_int[24] ^ s1[12] ^ comux[23]);
assign intc2 = (USE_SIMD_BIN == USE_SIMD_ONE48) && s1[12];
assign co24_lsb = (USE_SIMD_BIN == USE_SIMD_ONE48) && a_int[24];
//
assign s2 = {a_int[35:25],co24_lsb} + smux_w[35:24] + intc2;
assign cout2 = ALUMODE10_in ^ (a_int[36] ^ s2[12] ^ comux[35]);
assign intc3 = (USE_SIMD_BIN != USE_SIMD_FOUR12) && s2[12];
assign co36_lsb = (USE_SIMD_BIN != USE_SIMD_FOUR12) && a_int[36];
//
assign s3 = {a_int[48:37],co36_lsb} + {comux4simd[47],smux_w[47:36]} + intc3;
assign cout3 = ALUMODE10_in ^ s3[12];
// Not gated with alumode10 since used to propogate carry in wide multiply
assign cout4 = s3[13];
// Wide XOR
assign xor_12a = USE_WIDEXOR_BIN ? ^s[5:0] : 0;
assign xor_12b = USE_WIDEXOR_BIN ? ^s[11:6] : 0;
assign xor_12c = USE_WIDEXOR_BIN ? ^s[17:12] : 0;
assign xor_12d = USE_WIDEXOR_BIN ? ^s[23:18] : 0;
assign xor_12e = USE_WIDEXOR_BIN ? ^s[29:24] : 0;
assign xor_12f = USE_WIDEXOR_BIN ? ^s[35:30] : 0;
assign xor_12g = USE_WIDEXOR_BIN ? ^s[41:36] : 0;
assign xor_12h = USE_WIDEXOR_BIN ? ^s[47:42] : 0;
assign xor_24a = xor_12a ^ xor_12b;
assign xor_24b = xor_12c ^ xor_12d;
assign xor_24c = xor_12e ^ xor_12f;
assign xor_24d = xor_12g ^ xor_12h;
assign xor_48a = xor_24a ^ xor_24b;
assign xor_48b = xor_24c ^ xor_24d;
assign xor_96 = xor_48a ^ xor_48b;
// "X" carryout for multiply and logic operations
assign mult_or_logic = ((OPMODE_mux[3:0] == 4'b0101) ||
(ALUMODE_DATA[3:2] != 2'b00));
// allow carrycascout to not X in output atom
// assign cout_3 = mult_or_logic ? 1'bx : cout3;
assign cout_3 = cout3;
assign cout_2 = mult_or_logic ? 1'bx : cout2;
assign cout_1 = mult_or_logic ? 1'bx : cout1;
assign cout_0 = mult_or_logic ? 1'bx : cout0;
// drive signals to Output Atom
assign COUT_in[3] = cout_3;
assign COUT_in[2] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_2 : 1'bx;
assign COUT_in[1] = (USE_SIMD_BIN != USE_SIMD_ONE48 ) ? cout_1 : 1'bx;
assign COUT_in[0] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_0 : 1'bx;
assign MULTSIGN_ALU_in = s3[13]; // from alu rtl but doesn't seem right
assign #1 ALU_OUT_in = {48{ALUMODE_DATA[1]}} ^ {s3[11:0],s2[11:0],s1[11:0],s0[11:0]}; // break 0 delay feedback
assign XOR_MX_in[0] = XORSIMD_BIN ? xor_12a : xor_24a;
assign XOR_MX_in[1] = XORSIMD_BIN ? xor_12b : xor_48a;
assign XOR_MX_in[2] = XORSIMD_BIN ? xor_12c : xor_24b;
assign XOR_MX_in[3] = XORSIMD_BIN ? xor_12d : xor_96;
assign XOR_MX_in[4] = XORSIMD_BIN ? xor_12e : xor_24c;
assign XOR_MX_in[5] = XORSIMD_BIN ? xor_12f : xor_48b;
assign XOR_MX_in[6] = XORSIMD_BIN ? xor_12g : xor_24d;
assign XOR_MX_in[7] = xor_12h;
//--########################### END ALU ################################
//*** CarryIn Mux and Register
//------- input 0
always @(posedge CLK_in) begin
if (RSTALLCARRYIN_in || glblGSR)
CARRYIN_reg <= 1'b0;
else if (CECARRYIN_in)
CARRYIN_reg <= CARRYIN_in;
end
assign CARRYIN_mux = (CARRYINREG_BIN == 1'b1) ? CARRYIN_reg : CARRYIN_in;
// INTERNAL CARRYIN REGISTER
assign c_mult = !(AMULT26_in^BMULT17_in);
assign ce_m_g = CEM_in & ~glblGSR; // & gwe
assign rst_carryin_g = RSTALLCARRYIN_in & ~glblGSR; // & gwe
assign d_carryin_int = ce_m_g ? c_mult : qmultcarryin;
// rstallcarryin is injected through data path
assign dr_carryin_int = rst_carryin_g ? 0 : d_carryin_int;
always @(posedge CLK_in) begin
if (glblGSR)
qmultcarryin <= 1'b0;
else
qmultcarryin <= dr_carryin_int;
end
// bypass register mux
assign multcarryin_data = (MREG_BIN == 1'b1) ? qmultcarryin : c_mult;
//NB
always @(CARRYINSEL_mux or CARRYIN_mux or PCIN_in[47] or CARRYCASCIN_in or CCOUT_in or P_FDBK_in[47] or multcarryin_data) begin
case (CARRYINSEL_mux)
3'b000 : cin_b = ~CARRYIN_mux;
3'b001 : cin_b = PCIN_in[47];
3'b010 : cin_b = ~CARRYCASCIN_in;
3'b011 : cin_b = ~PCIN_in[47];
3'b100 : cin_b = ~CCOUT_in;
3'b101 : cin_b = P_FDBK_in[47];
3'b110 : cin_b = ~multcarryin_data;
3'b111 : cin_b = ~P_FDBK_in[47];
default : cin_b = 1'bx;
endcase
end
// disable carryin when performing logic operation
assign cin = (ALUMODE_DATA[3] || ALUMODE_DATA[2]) ? 1'b0 : ~cin_b;
// DSP_A_B_DATA
//*********************************************************
//*** Input register A with 2 level deep of registers
//*********************************************************
always @(posedge CLK_in) begin
if (RSTA_in || (AREG_BIN == 2'b00) || glblGSR) begin
A1_reg <= {A_WIDTH{1'b0}};
end else if (CEA1_in) begin
if (A_INPUT_BIN == A_INPUT_CASCADE) begin
A1_reg <= ACIN_in;
end else begin
A1_reg <= A_in;
end
end
end
always @(posedge CLK_in) begin
if (RSTA_in || (AREG_BIN == 2'b00) || glblGSR) begin
A2_reg <= {A_WIDTH{1'b0}};
end else if (CEA2_in) begin
if (AREG_BIN == 2'b10) begin
A2_reg <= A1_reg;
end else if (A_INPUT_BIN == A_INPUT_CASCADE) begin
A2_reg <= ACIN_in;
end else begin
A2_reg <= A_in;
end
end
end
assign A_ALU = (AREG_BIN != 2'b00) ? A2_reg :
(A_INPUT_BIN == A_INPUT_CASCADE) ? ACIN_in :
A_in;
// assumes encoding the same for ACASCREG and AREG
assign ACOUT = (ACASCREG_BIN == AREG_BIN) ? A_ALU : A1_reg;
//*********************************************************
//*** Input register B with 2 level deep of registers
//*********************************************************
always @(posedge CLK_in) begin
if (RSTB_in || (BREG_BIN == 2'b00) || glblGSR) begin
B1_DATA_out <= 18'b0;
end else if (CEB1_in) begin
if (B_INPUT_BIN == B_INPUT_CASCADE) B1_DATA_out <= BCIN_in;
else B1_DATA_out <= B_in;
end
end
always @(posedge CLK_in) begin
if (RSTB_in || glblGSR) B2_reg <= 18'b0;
else if (CEB2_in) begin
if (BREG_BIN == 2'b10) B2_reg <= B1_DATA_out;
else if (B_INPUT_BIN == B_INPUT_CASCADE) B2_reg <= BCIN_in;
else B2_reg <= B_in;
end
end
assign B_ALU = (BREG_BIN != 2'b00) ? B2_reg :
(B_INPUT_BIN == B_INPUT_CASCADE) ? BCIN_in :
B_in;
assign B2_DATA = (BREG_BIN != 2'b00) ? B2_reg :
(B_INPUT_BIN == B_INPUT_CASCADE) ? BCIN_in :
B_in;
// assumes encoding the same for BCASCREG and BREG
assign BCOUT = (BCASCREG_BIN == BREG_BIN) ? B2_DATA : B1_DATA_out;
// DSP_C_DATA
//*********************************************************
//*** Input register C with 1 level deep of register
//*********************************************************
always @(posedge CLK_in) begin
if (RSTC_in || (CREG_BIN == 1'b0) || glblGSR) begin
C_reg <= 48'b0;
end else if (CEC_in) begin
C_reg <= C_in;
end
end
assign C_DATA_in = (CREG_BIN == 1'b1) ? C_reg : C_in;
// DSP_MULTIPLIER
always @(*) begin
if (AMULTSEL_BIN == AMULTSEL_A) a_mult_mux = A2A1;
else a_mult_mux = AD_DATA;
end
always @(*) begin
if (BMULTSEL_BIN == BMULTSEL_B) b_mult_mux = B2B1;
else b_mult_mux = AD_DATA;
end
assign AMULT26_in = a_mult_mux[26];
assign BMULT17_in = b_mult_mux[17];
// U[44],V[44] 11 when mult[44]=0, 10 when mult[44]=1
assign U_in = {1'b1, mult[43:0] & ps_u_mask};
assign V_in = {~mult[44], mult[43:0] & ps_v_mask};
always @(*) begin
if (USE_MULT_BIN == USE_MULT_NONE) mult = 45'b0;
else mult = ({{18{a_mult_mux[26]}},a_mult_mux} * {{27{b_mult_mux[17]}},b_mult_mux});
end
// DSP_M_DATA
//*********************************************************
//*** Multiplier outputs U, V with 1 level deep of register
//*********************************************************
always @(posedge CLK_in) begin
if (RSTM_in || (MREG_BIN == 1'b0) || glblGSR) begin
U_DATA_reg <= {1'b0, {M_WIDTH-1{1'b0}}};
V_DATA_reg <= {1'b0, {M_WIDTH-1{1'b0}}};
end else if (CEM_in) begin
U_DATA_reg <= U_in;
V_DATA_reg <= V_in;
end
end
assign U_DATA = (MREG_BIN == 1'b1) ? U_DATA_reg : U_in;
assign V_DATA = (MREG_BIN == 1'b1) ? V_DATA_reg : V_in;
// DSP_OUTPUT
//--####################################################################
//--##### Pattern Detector #####
//--####################################################################
// select pattern
assign the_pattern = (SEL_PATTERN_BIN == SEL_PATTERN_PATTERN) ? PATTERN_REG : C_DATA_in;
// select mask
assign the_mask = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_NO_PATDET) ? {C_WIDTH{1'b1}} :
(SEL_MASK_BIN == SEL_MASK_C) ? C_DATA_in :
(SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE1) ? {~(C_DATA_in[C_WIDTH-2:0]),1'b0} :
(SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE2) ? {~(C_DATA_in[C_WIDTH-3:0]),2'b0} :
MASK_REG; // default or (SEL_MASK_BIN == SEL_MASK_MASK)
//-- now do the pattern detection
assign pdet_o = &(~(the_pattern ^ ALU_OUT_in) | the_mask);
assign pdetb_o = &( (the_pattern ^ ALU_OUT_in) | the_mask);
assign PATTERNDETECT = opmode_valid_flag_dou ? pdet_o_mux : 1'bx;
assign PATTERNBDETECT = opmode_valid_flag_dou ? pdetb_o_mux : 1'bx;
//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW
always @(posedge CLK_in) begin
if (RSTP_in || glblGSR || the_auto_reset_patdet) begin
pdet_o_reg1 <= 1'b0;
pdet_o_reg2 <= 1'b0;
pdetb_o_reg1 <= 1'b0;
pdetb_o_reg2 <= 1'b0;
end else if (CEP_in && PREG_BIN) begin
//-- the previous values are used in Underflow/Overflow
pdet_o_reg2 <= pdet_o_reg1;
pdetb_o_reg2 <= pdetb_o_reg1;
pdet_o_reg1 <= pdet_o;
pdetb_o_reg1 <= pdetb_o;
end
end
assign pdet_o_mux = (PREG_BIN == 1'b1) ? pdet_o_reg1 : pdet_o;
assign pdetb_o_mux = (PREG_BIN == 1'b1) ? pdetb_o_reg1 : pdetb_o;
assign overflow_data = (PREG_BIN == 1'b1) ? pdet_o_reg2 : pdet_o;
assign underflow_data = (PREG_BIN == 1'b1) ? pdetb_o_reg2 : pdetb_o;
//--####################################################################
//--##### AUTORESET_PATDET #####
//--####################################################################
assign auto_reset_pri = (AUTORESET_PRIORITY_BIN == AUTORESET_PRIORITY_RESET) || CEP_in;
assign the_auto_reset_patdet =
(AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_MATCH) ?
auto_reset_pri && pdet_o_mux :
(AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_NOT_MATCH) ?
auto_reset_pri && overflow_data && ~pdet_o_mux : 1'b0; // NO_RESET
//--####################################################################
//--#### CARRYOUT, CARRYCASCOUT. MULTSIGNOUT, PCOUT and XOROUT reg #####
//--####################################################################
//*** register with 1 level of register
always @(posedge CLK_in) begin
if (RSTP_in || glblGSR || the_auto_reset_patdet) begin
COUT_reg <= 4'b0000;
ALUMODE10_reg <= 1'b0;
MULTSIGN_ALU_reg <= 1'b0;
ALU_OUT_reg <= 48'b0;
XOR_MX_reg <= 8'b0;
end else if (CEP_in && PREG_BIN) begin
COUT_reg <= COUT_in;
ALUMODE10_reg <= ALUMODE10_in;
MULTSIGN_ALU_reg <= MULTSIGN_ALU_in;
ALU_OUT_reg <= ALU_OUT_in;
XOR_MX_reg <= XOR_MX_in;
end
end
assign ALUMODE10_mux = (PREG_BIN == 1'b1) ? ALUMODE10_reg : ALUMODE10_in;
assign CARRYOUT = (PREG_BIN == 1'b1) ? COUT_reg : COUT_in;
assign MULTSIGNOUT = (PREG_BIN == 1'b1) ? MULTSIGN_ALU_reg : MULTSIGN_ALU_in;
assign P = (PREG_BIN == 1'b1) ? ALU_OUT_reg : ALU_OUT_in;
assign XOROUT = (PREG_BIN == 1'b1) ? XOR_MX_reg : XOR_MX_in;
assign CCOUT_in = ALUMODE10_reg ^ COUT_reg[3];
assign CARRYCASCOUT = (PREG_BIN == 1'b1) ? ALUMODE10_reg ^ COUT_reg[3]:
ALUMODE10_in ^ COUT_in[3];
assign P_FDBK_in = ALU_OUT_reg;
assign P_FDBK_47_in = ALU_OUT_reg[47];
assign PCOUT = (PREG_BIN == 1'b1) ? ALU_OUT_reg : ALU_OUT_in;
//--####################################################################
//--##### Underflow / Overflow #####
//--####################################################################
assign OVERFLOW = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ?
~pdet_o_mux && ~pdetb_o_mux && overflow_data : 1'bx;
assign UNDERFLOW = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ?
~pdet_o_mux && ~pdetb_o_mux && underflow_data : 1'bx;
// DSP_PREADD
//*********************************************************
//*** Preaddsub AD
//*********************************************************
assign D_DATA_mux = INMODE_mux[2] ? D_DATA : 27'b0;
assign AD_in = INMODE_mux[3] ? (D_DATA_mux - PREADD_AB) : (D_DATA_mux + PREADD_AB);
// DSP_PREADD_DATA
always @ (*) begin
if (((AMULTSEL_BIN == AMULTSEL_A) &&
(BMULTSEL_BIN == BMULTSEL_B)) ||
(USE_MULT_BIN == USE_MULT_NONE)) begin
DREG_INT = 1'b0;
end else begin
DREG_INT = DREG_BIN;
end
end
always @ (*) begin
if (((AMULTSEL_BIN == AMULTSEL_A) && (BMULTSEL_BIN == BMULTSEL_B)) ||
(USE_MULT_BIN == USE_MULT_NONE)) begin
ADREG_INT = 1'b0;
end else begin
ADREG_INT = ADREG_BIN;
end
end
always @(*) begin
if ((PREADDINSEL_BIN==PREADDINSEL_A) && INMODE_mux[1]) A2A1 = 27'b0;
else if (INMODE_mux[0]==1'b1) A2A1 = A1_reg[26:0];
else A2A1 = A_ALU[26:0];
end
always @(*) begin
if ((PREADDINSEL_BIN==PREADDINSEL_B) && INMODE_mux[1]) B2B1 = 18'b0;
else if (INMODE_mux[4]==1'b1) B2B1 = B1_DATA_out;
else B2B1 = B2_DATA;
end
assign PREADD_AB = (PREADDINSEL_BIN==PREADDINSEL_B) ? {{9{B2B1[17]}}, B2B1} : A2A1;
//*********************************************************
//********** INMODE signal registering ************
//*********************************************************
// new
always @(posedge CLK_in) begin
if (RSTINMODE_in || (INMODEREG_BIN == 1'b0) || glblGSR) begin
INMODE_reg <= 5'b0;
end else if (CEINMODE_in) begin
INMODE_reg <= INMODE_in;
end
end
assign INMODE_mux = (INMODEREG_BIN == 1'b1) ? INMODE_reg : INMODE_in;
//*********************************************************
//*** Input register D with 1 level deep of register
//*********************************************************
always @(posedge CLK_in) begin
if (RSTD_in || (DREG_INT == 1'b0) || glblGSR) begin
D_DATA_reg <= {D_WIDTH{1'b0}};
end else if (CED_in) begin
D_DATA_reg <= D_in;
end
end
assign D_DATA = (DREG_INT == 1'b1) ? D_DATA_reg : D_in;
//*********************************************************
//*** Input register AD with 1 level deep of register
//*********************************************************
always @(posedge CLK_in) begin
if (RSTD_in || glblGSR) begin
AD_DATA_reg <= 27'b0;
end else if (CEAD_in) AD_DATA_reg <= AD_in;
end
assign AD_DATA = (ADREG_INT == 1'b1) ? AD_DATA_reg : AD_in;
always @(OPMODE_mux) begin
if (((OPMODE_mux[1:0] == 2'b11) && (USE_MULT_BIN == USE_MULT_MULTIPLY)) &&
((AREG_BIN==2'b00 && BREG_BIN==2'b00 && MREG_BIN==1'b0) ||
(AREG_BIN==2'b00 && BREG_BIN==2'b00 && PREG_BIN==1'b0) ||
(MREG_BIN==1'b0 && PREG_BIN==1'b0)))
$display("OPMODE Input Warning : [Unisim %s-8] The OPMODE[1:0] (%b) is invalid when using attributes USE_MULT = MULTIPLY and (A, B and M) or (A, B and P) or (M and P) are not REGISTERED at time %.3f ns. Please set USE_MULT to either NONE or DYNAMIC or REGISTER one of each group. (A or B) and (M or P) will satisfy the requirement. Instance %m", MODULE_NAME, OPMODE_mux[1:0], $time/1000.0);
if ((OPMODE_mux[3:0] == 4'b0101) &&
((USE_MULT_BIN == USE_MULT_NONE) || (USE_SIMD_BIN != USE_SIMD_ONE48)))
$display("OPMODE Input Warning : [Unisim %s-9] The OPMODE[3:0] (%b) is invalid when using attributes USE_MULT = NONE, or USE_SIMD = TWO24 or FOUR12 at %.3f ns. Instance %m", MODULE_NAME, OPMODE_mux[3:0], $time/1000.0);
end
// end behavioral model
endmodule
`endcelldefine
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A211O_FUNCTIONAL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a211o (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_8_V
`define SKY130_FD_SC_HS__NAND2_8_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2_8 (
Y ,
A ,
B ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_8_V
|
module slave(
input wire reset_n,
input wire en,
input wire [6:0] my_addr,
input wire [7:0] measurement,
input wire scl,
inout wire sda
);
reg stop;
reg start;
reg mode;
reg [7:0] data_in;
reg [6:0] address;
reg [2:0] slave_state;
reg [4:0] slave_counter;
reg sda_out;
reg sda_en;
reg sda_in;
parameter WAIT = 0;
parameter ADDRESS = 1;
parameter MODE = 2;
parameter ADDRESS_ACK = 3;
parameter WRITE_DATA = 4;
parameter READ_DATA = 5;
parameter WRITE_ACK = 6;
parameter READ_ACK = 7;
assign sda = (sda_en) ? ( sda_out ) ? 1'bz : 1'b0 : 1'bz;
always@(negedge sda or negedge reset_n)
begin
if(!reset_n)
begin
start <= 0;
end
else
begin
if( scl )
begin
start <= 1;
end
else
begin
start <= 0;
end
end
end
always@(posedge sda or negedge reset_n)
begin
if(!reset_n)
begin
stop <= 0;
end
else
begin
if( scl )
begin
stop <= 1;
end
else
begin
stop <= 0;
end
end
end
always@(posedge scl or negedge reset_n)
begin
sda_in <= sda;
end
always@( sda_in or slave_state or slave_counter or negedge reset_n)
begin
if( !reset_n )
begin
sda_en <= 0;
sda_out <= 0;
address <= 7'b0;
data_in <= 8'b0;
mode <= 0;
end
else
begin
case(slave_state)
WAIT:
begin
sda_en <= 0;
sda_out <= 0;
address <= {address, sda_in};
data_in <= 8'b0;
mode <= 0;
end
ADDRESS:
begin
sda_en <= 0;
sda_out <= 0;
address <= {address, sda_in};
data_in <= 8'b0;
mode <= 0;
end
MODE:
begin
sda_en <= 0;
sda_out <= 0;
address <= address;
data_in <= 8'b0;
mode <= sda;
end
ADDRESS_ACK:
begin
sda_en <= 1;
sda_out <= 0;
address <= address;
data_in <= 8'b0;
mode <= mode;
end
WRITE_DATA:
begin
sda_en <= 1;
sda_out <= measurement[7 - slave_counter];
address <= 7'b0;
data_in <= 8'b0;
mode <= mode;
end
WRITE_ACK:
begin
sda_en <= 0;
sda_out <= 0;
address <= address;
data_in <= 8'b0;
mode <= mode;
end
READ_DATA:
begin
sda_en <= 0;
sda_out <= 0;
address <= address;
data_in <= {data_in, sda_in};
mode <= mode;
end
READ_ACK:
begin
sda_en <= 1;
sda_out <= 0;
address <= address;
data_in <= data_in;
mode <= mode;
end
endcase
end
end
always@(negedge scl or negedge reset_n)
begin
if( !reset_n )
begin
slave_state = WAIT;
slave_counter = 0;
end
else
begin
case(slave_state)
WAIT:
begin
if( start && en )
begin
slave_state <= ADDRESS;
slave_counter <= 4'b0;
end
else
begin
slave_state <= WAIT;
slave_counter <= 4'b0;
end
end
ADDRESS:
begin
if(slave_counter < 6)
begin
slave_state <= ADDRESS;
slave_counter <= slave_counter + 1'b1;
end
else
begin
slave_state <= MODE;
slave_counter <= 0;
end
end
MODE:
begin
slave_state <= ADDRESS_ACK;
slave_counter <= 0;
end
ADDRESS_ACK:
begin
if((address == my_addr) || ( stop ))
begin
if( mode )
begin
slave_state <= WRITE_DATA;
slave_counter <= 0;
end
else
slave_state <= READ_DATA;
slave_counter <= 0;
end
else
begin
slave_state <= WAIT;
slave_counter <= 0;
end
end
WRITE_DATA:
begin
if(slave_counter < 7)
begin
slave_state <= WRITE_DATA;
slave_counter <= slave_counter + 1'b1;
end
else
begin
slave_state <= WRITE_ACK;
slave_counter <= 0;
end
end
WRITE_ACK:
begin
if( sda_in || stop )
begin
slave_state <= WAIT;
slave_counter = 0;
end
else
begin
slave_state <= WRITE_DATA;
slave_counter <= 0;
end
end
READ_DATA:
begin
if(slave_counter < 7)
begin
slave_state <= READ_DATA;
slave_counter <= slave_counter + 1;
end
else
begin
slave_state <= READ_ACK;
slave_counter <= 0;
end
end
READ_ACK:
begin
if( stop )
begin
slave_state <= WAIT;
slave_counter <= 0;
end
else
begin
slave_state <= READ_DATA;
slave_counter <= 0;
end
end
endcase
end
end
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Nnat ZArith_base ROmega ZArithRing Zdiv Morphisms.
Local Open Scope Z_scope.
(** This file provides results about the Round-Toward-Zero Euclidean
division [Z.quotrem], whose projections are [Z.quot] (noted ÷)
and [Z.rem].
This division and [Z.div] agree only on positive numbers.
Otherwise, [Z.div] performs Round-Toward-Bottom (a.k.a Floor).
This [Z.quot] is compatible with the division of usual
programming languages such as Ocaml. In addition, it has nicer
properties with respect to opposite and other usual operations.
The definition of this division is now in file [BinIntDef],
while most of the results about here are now in the main module
[BinInt.Z], thanks to the generic "Numbers" layer. Remain here:
- some compatibility notation for old names.
- some extra results with less preconditions (in particular
exploiting the arbitrary value of division by 0).
*)
Notation Ndiv_Zquot := N2Z.inj_quot (only parsing).
Notation Nmod_Zrem := N2Z.inj_rem (only parsing).
Notation Z_quot_rem_eq := Z.quot_rem' (only parsing).
Notation Zrem_lt := Z.rem_bound_abs (only parsing).
Notation Zquot_unique := Z.quot_unique (compat "8.6").
Notation Zrem_unique := Z.rem_unique (compat "8.6").
Notation Zrem_1_r := Z.rem_1_r (compat "8.6").
Notation Zquot_1_r := Z.quot_1_r (compat "8.6").
Notation Zrem_1_l := Z.rem_1_l (compat "8.6").
Notation Zquot_1_l := Z.quot_1_l (compat "8.6").
Notation Z_quot_same := Z.quot_same (compat "8.6").
Notation Z_quot_mult := Z.quot_mul (only parsing).
Notation Zquot_small := Z.quot_small (compat "8.6").
Notation Zrem_small := Z.rem_small (compat "8.6").
Notation Zquot2_quot := Zquot2_quot (compat "8.6").
(** Particular values taken for [a÷0] and [(Z.rem a 0)].
We avise to not rely on these arbitrary values. *)
Lemma Zquot_0_r a : a ÷ 0 = 0.
Proof. now destruct a. Qed.
Lemma Zrem_0_r a : Z.rem a 0 = a.
Proof. now destruct a. Qed.
(** The following results are expressed without the [b<>0] condition
whenever possible. *)
Lemma Zrem_0_l a : Z.rem 0 a = 0.
Proof. now destruct a. Qed.
Lemma Zquot_0_l a : 0÷a = 0.
Proof. now destruct a. Qed.
Hint Resolve Zrem_0_l Zrem_0_r Zquot_0_l Zquot_0_r Z.quot_1_r Z.rem_1_r
: zarith.
Ltac zero_or_not a :=
destruct (Z.eq_decidable a 0) as [->|?];
[rewrite ?Zquot_0_l, ?Zrem_0_l, ?Zquot_0_r, ?Zrem_0_r;
auto with zarith|].
Lemma Z_rem_same a : Z.rem a a = 0.
Proof. zero_or_not a. now apply Z.rem_same. Qed.
Lemma Z_rem_mult a b : Z.rem (a*b) b = 0.
Proof. zero_or_not b. now apply Z.rem_mul. Qed.
(** * Division and Opposite *)
(* The precise equalities that are invalid with "historic" Zdiv. *)
Theorem Zquot_opp_l a b : (-a)÷b = -(a÷b).
Proof. zero_or_not b. now apply Z.quot_opp_l. Qed.
Theorem Zquot_opp_r a b : a÷(-b) = -(a÷b).
Proof. zero_or_not b. now apply Z.quot_opp_r. Qed.
Theorem Zrem_opp_l a b : Z.rem (-a) b = -(Z.rem a b).
Proof. zero_or_not b. now apply Z.rem_opp_l. Qed.
Theorem Zrem_opp_r a b : Z.rem a (-b) = Z.rem a b.
Proof. zero_or_not b. now apply Z.rem_opp_r. Qed.
Theorem Zquot_opp_opp a b : (-a)÷(-b) = a÷b.
Proof. zero_or_not b. now apply Z.quot_opp_opp. Qed.
Theorem Zrem_opp_opp a b : Z.rem (-a) (-b) = -(Z.rem a b).
Proof. zero_or_not b. now apply Z.rem_opp_opp. Qed.
(** The sign of the remainder is the one of [a]. Due to the possible
nullity of [a], a general result is to be stated in the following form:
*)
Theorem Zrem_sgn a b : 0 <= Z.sgn (Z.rem a b) * Z.sgn a.
Proof.
zero_or_not b.
- apply Z.square_nonneg.
- zero_or_not (Z.rem a b).
rewrite Z.rem_sign_nz; trivial. apply Z.square_nonneg.
Qed.
(** This can also be said in a simplier way: *)
Theorem Zrem_sgn2 a b : 0 <= (Z.rem a b) * a.
Proof.
zero_or_not b.
- apply Z.square_nonneg.
- now apply Z.rem_sign_mul.
Qed.
(** Reformulation of [Z.rem_bound_abs] in 2 then 4 particular cases. *)
Theorem Zrem_lt_pos a b : 0<=a -> b<>0 -> 0 <= Z.rem a b < Z.abs b.
Proof.
intros; generalize (Z.rem_nonneg a b) (Z.rem_bound_abs a b);
romega with *.
Qed.
Theorem Zrem_lt_neg a b : a<=0 -> b<>0 -> -Z.abs b < Z.rem a b <= 0.
Proof.
intros; generalize (Z.rem_nonpos a b) (Z.rem_bound_abs a b);
romega with *.
Qed.
Theorem Zrem_lt_pos_pos a b : 0<=a -> 0<b -> 0 <= Z.rem a b < b.
Proof.
intros; generalize (Zrem_lt_pos a b); romega with *.
Qed.
Theorem Zrem_lt_pos_neg a b : 0<=a -> b<0 -> 0 <= Z.rem a b < -b.
Proof.
intros; generalize (Zrem_lt_pos a b); romega with *.
Qed.
Theorem Zrem_lt_neg_pos a b : a<=0 -> 0<b -> -b < Z.rem a b <= 0.
Proof.
intros; generalize (Zrem_lt_neg a b); romega with *.
Qed.
Theorem Zrem_lt_neg_neg a b : a<=0 -> b<0 -> b < Z.rem a b <= 0.
Proof.
intros; generalize (Zrem_lt_neg a b); romega with *.
Qed.
(** * Unicity results *)
Definition Remainder a b r :=
(0 <= a /\ 0 <= r < Z.abs b) \/ (a <= 0 /\ -Z.abs b < r <= 0).
Definition Remainder_alt a b r :=
Z.abs r < Z.abs b /\ 0 <= r * a.
Lemma Remainder_equiv : forall a b r,
Remainder a b r <-> Remainder_alt a b r.
Proof.
unfold Remainder, Remainder_alt; intuition.
- romega with *.
- romega with *.
- rewrite <-(Z.mul_opp_opp). apply Z.mul_nonneg_nonneg; romega.
- assert (0 <= Z.sgn r * Z.sgn a).
{ rewrite <-Z.sgn_mul, Z.sgn_nonneg; auto. }
destruct r; simpl Z.sgn in *; romega with *.
Qed.
Theorem Zquot_mod_unique_full a b q r :
Remainder a b r -> a = b*q + r -> q = a÷b /\ r = Z.rem a b.
Proof.
destruct 1 as [(H,H0)|(H,H0)]; intros.
apply Zdiv_mod_unique with b; auto.
apply Zrem_lt_pos; auto.
romega with *.
rewrite <- H1; apply Z.quot_rem'.
rewrite <- (Z.opp_involutive a).
rewrite Zquot_opp_l, Zrem_opp_l.
generalize (Zdiv_mod_unique b (-q) (-a÷b) (-r) (Z.rem (-a) b)).
generalize (Zrem_lt_pos (-a) b).
rewrite <-Z.quot_rem', Z.mul_opp_r, <-Z.opp_add_distr, <-H1.
romega with *.
Qed.
Theorem Zquot_unique_full a b q r :
Remainder a b r -> a = b*q + r -> q = a÷b.
Proof.
intros; destruct (Zquot_mod_unique_full a b q r); auto.
Qed.
Theorem Zrem_unique_full a b q r :
Remainder a b r -> a = b*q + r -> r = Z.rem a b.
Proof.
intros; destruct (Zquot_mod_unique_full a b q r); auto.
Qed.
(** * Order results about Zrem and Zquot *)
(* Division of positive numbers is positive. *)
Lemma Z_quot_pos a b : 0 <= a -> 0 <= b -> 0 <= a÷b.
Proof. intros. zero_or_not b. apply Z.quot_pos; auto with zarith. Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_quot_lt a b : 0 < a -> 2 <= b -> a÷b < a.
Proof. intros. apply Z.quot_lt; auto with zarith. Qed.
(** [<=] is compatible with a positive division. *)
Lemma Z_quot_monotone a b c : 0<=c -> a<=b -> a÷c <= b÷c.
Proof. intros. zero_or_not c. apply Z.quot_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a÷b) is always done toward 0: *)
Lemma Z_mult_quot_le a b : 0 <= a -> 0 <= b*(a÷b) <= a.
Proof. intros. zero_or_not b. apply Z.mul_quot_le; auto with zarith. Qed.
Lemma Z_mult_quot_ge a b : a <= 0 -> a <= b*(a÷b) <= 0.
Proof. intros. zero_or_not b. apply Z.mul_quot_ge; auto with zarith. Qed.
(** The previous inequalities between [b*(a÷b)] and [a] are exact
iff the modulo is zero. *)
Lemma Z_quot_exact_full a b : a = b*(a÷b) <-> Z.rem a b = 0.
Proof. intros. zero_or_not b. intuition. apply Z.quot_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zrem_le a b : 0 <= a -> 0 <= b -> Z.rem a b <= a.
Proof. intros. zero_or_not b. apply Z.rem_le; auto with zarith. Qed.
(** Some additional inequalities about Zdiv. *)
Theorem Zquot_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a÷b <= q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_le_upper_bound. Qed.
Theorem Zquot_lt_upper_bound:
forall a b q, 0 <= a -> 0 < b -> a < q*b -> a÷b < q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_lt_upper_bound. Qed.
Theorem Zquot_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a÷b.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_le_lower_bound. Qed.
Theorem Zquot_sgn: forall a b,
0 <= Z.sgn (a÷b) * Z.sgn a * Z.sgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
unfold Z.quot; simpl; destruct N.pos_div_eucl; simpl; destruct n; simpl; auto with zarith.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
(** First, a result that used to be always valid with Zdiv,
but must be restricted here.
For instance, now (9+(-5)*2) rem 2 = -1 <> 1 = 9 rem 2 *)
Lemma Z_rem_plus : forall a b c:Z,
0 <= (a+b*c) * a ->
Z.rem (a + b * c) c = Z.rem a c.
Proof. intros. zero_or_not c. apply Z.rem_add; auto with zarith. Qed.
Lemma Z_quot_plus : forall a b c:Z,
0 <= (a+b*c) * a -> c<>0 ->
(a + b * c) ÷ c = a ÷ c + b.
Proof. intros. apply Z.quot_add; auto with zarith. Qed.
Theorem Z_quot_plus_l: forall a b c : Z,
0 <= (a*b+c)*c -> b<>0 ->
b<>0 -> (a * b + c) ÷ b = a + c ÷ b.
Proof. intros. apply Z.quot_add_l; auto with zarith. Qed.
(** Cancellations. *)
Lemma Zquot_mult_cancel_r : forall a b c:Z,
c<>0 -> (a*c)÷(b*c) = a÷b.
Proof. intros. zero_or_not b. apply Z.quot_mul_cancel_r; auto. Qed.
Lemma Zquot_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)÷(c*b) = a÷b.
Proof.
intros. rewrite (Z.mul_comm c b). zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.quot_mul_cancel_l; auto.
Qed.
Lemma Zmult_rem_distr_l: forall a b c,
Z.rem (c*a) (c*b) = c * (Z.rem a b).
Proof.
intros. zero_or_not c. rewrite (Z.mul_comm c b). zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.mul_rem_distr_l; auto.
Qed.
Lemma Zmult_rem_distr_r: forall a b c,
Z.rem (a*c) (b*c) = (Z.rem a b) * c.
Proof.
intros. zero_or_not b. rewrite (Z.mul_comm b c). zero_or_not c.
rewrite (Z.mul_comm c b). apply Z.mul_rem_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zrem_rem: forall a n, Z.rem (Z.rem a n) n = Z.rem a n.
Proof. intros. zero_or_not n. apply Z.rem_rem; auto. Qed.
Theorem Zmult_rem: forall a b n,
Z.rem (a * b) n = Z.rem (Z.rem a n * Z.rem b n) n.
Proof. intros. zero_or_not n. apply Z.mul_rem; auto. Qed.
(** addition and modulo
Generally speaking, unlike with Zdiv, we don't have
(a+b) rem n = (a rem n + b rem n) rem n
for any a and b.
For instance, take (8 + (-10)) rem 3 = -2 whereas
(8 rem 3 + (-10 rem 3)) rem 3 = 1. *)
Theorem Zplus_rem: forall a b n,
0 <= a * b ->
Z.rem (a + b) n = Z.rem (Z.rem a n + Z.rem b n) n.
Proof. intros. zero_or_not n. apply Z.add_rem; auto. Qed.
Lemma Zplus_rem_idemp_l: forall a b n,
0 <= a * b ->
Z.rem (Z.rem a n + b) n = Z.rem (a + b) n.
Proof. intros. zero_or_not n. apply Z.add_rem_idemp_l; auto. Qed.
Lemma Zplus_rem_idemp_r: forall a b n,
0 <= a*b ->
Z.rem (b + Z.rem a n) n = Z.rem (b + a) n.
Proof.
intros. zero_or_not n. apply Z.add_rem_idemp_r; auto.
rewrite Z.mul_comm; auto.
Qed.
Lemma Zmult_rem_idemp_l: forall a b n, Z.rem (Z.rem a n * b) n = Z.rem (a * b) n.
Proof. intros. zero_or_not n. apply Z.mul_rem_idemp_l; auto. Qed.
Lemma Zmult_rem_idemp_r: forall a b n, Z.rem (b * Z.rem a n) n = Z.rem (b * a) n.
Proof. intros. zero_or_not n. apply Z.mul_rem_idemp_r; auto. Qed.
(** Unlike with Zdiv, the following result is true without restrictions. *)
Lemma Zquot_Zquot : forall a b c, (a÷b)÷c = a÷(b*c).
Proof.
intros. zero_or_not b. rewrite Z.mul_comm. zero_or_not c.
rewrite Z.mul_comm. apply Z.quot_quot; auto.
Qed.
(** A last inequality: *)
Theorem Zquot_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a÷b) <= (c*a)÷b.
Proof. intros. zero_or_not b. apply Z.quot_mul_le; auto with zarith. Qed.
(** Z.rem is related to divisibility (see more in Znumtheory) *)
Lemma Zrem_divides : forall a b,
Z.rem a b = 0 <-> exists c, a = b*c.
Proof.
intros. zero_or_not b. firstorder.
rewrite Z.rem_divide; trivial.
split; intros (c,Hc); exists c; subst; auto with zarith.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zquot2_odd_remainder : forall a,
Remainder a 2 (if Z.odd a then Z.sgn a else 0).
Proof.
intros [ |p|p]. simpl.
left. simpl. auto with zarith.
left. destruct p; simpl; auto with zarith.
right. destruct p; simpl; split; now auto with zarith.
Qed.
Lemma Zrem_odd : forall a, Z.rem a 2 = if Z.odd a then Z.sgn a else 0.
Proof.
intros. symmetry.
apply Zrem_unique_full with (Z.quot2 a).
apply Zquot2_odd_remainder.
apply Zquot2_odd_eqn.
Qed.
Lemma Zrem_even : forall a, Z.rem a 2 = if Z.even a then 0 else Z.sgn a.
Proof.
intros a. rewrite Zrem_odd, Zodd_even_bool. now destruct Z.even.
Qed.
Lemma Zeven_rem : forall a, Z.even a = Z.eqb (Z.rem a 2) 0.
Proof.
intros a. rewrite Zrem_even.
destruct a as [ |p|p]; trivial; now destruct p.
Qed.
Lemma Zodd_rem : forall a, Z.odd a = negb (Z.eqb (Z.rem a 2) 0).
Proof.
intros a. rewrite Zrem_odd.
destruct a as [ |p|p]; trivial; now destruct p.
Qed.
(** * Interaction with "historic" Zdiv *)
(** They agree at least on positive numbers: *)
Theorem Zquotrem_Zdiv_eucl_pos : forall a b:Z, 0 <= a -> 0 < b ->
a÷b = a/b /\ Z.rem a b = a mod b.
Proof.
intros.
apply Zdiv_mod_unique with b.
apply Zrem_lt_pos; auto with zarith.
rewrite Z.abs_eq; auto with *; apply Z_mod_lt; auto with *.
rewrite <- Z_div_mod_eq; auto with *.
symmetry; apply Z.quot_rem; auto with *.
Qed.
Theorem Zquot_Zdiv_pos : forall a b, 0 <= a -> 0 <= b ->
a÷b = a/b.
Proof.
intros a b Ha Hb. Z.le_elim Hb.
- generalize (Zquotrem_Zdiv_eucl_pos a b Ha Hb); intuition.
- subst; now rewrite Zquot_0_r, Zdiv_0_r.
Qed.
Theorem Zrem_Zmod_pos : forall a b, 0 <= a -> 0 < b ->
Z.rem a b = a mod b.
Proof.
intros a b Ha Hb; generalize (Zquotrem_Zdiv_eucl_pos a b Ha Hb);
intuition.
Qed.
(** Modulos are null at the same places *)
Theorem Zrem_Zmod_zero : forall a b, b<>0 ->
(Z.rem a b = 0 <-> a mod b = 0).
Proof.
intros.
rewrite Zrem_divides, Zmod_divides; intuition.
Qed.
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 14:30:00 10/31/2016
// Module Name: D_MEM_tb
// Project Name: MIPS
// Description: Testing the MIPS Data Memory (D_MEM) module in the MEMORY
// (MEM) stage.
//
// Dependencies: D_MEM.v
//
////////////////////////////////////////////////////////////////////////////////
module D_MEM_tb;
// Inputs
reg clk;
reg MemWrite;
reg MemRead;
reg [31:0] Address;
reg [31:0] Write_data;
// Outputs
wire [31:0] Read_data;
// Instantiate the Unit Under Test (UUT)
D_MEM mem (
.clk(clk),
.MemWrite(MemWrite),
.MemRead(MemRead),
.Address(Address),
.Write_data(Write_data),
.Read_data(Read_data)
);
initial begin
// Initialize Inputs
clk = 0;
MemWrite = 0;
MemRead = 0;
Address = 0;
Write_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Test
MemWrite = 1;
Write_data = 32'h002300AA;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h10654321;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h001000220;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h8C123456;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h8F123456;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'hAD654321;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h13012345;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'hAC654321;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h12012345;
#20;
MemWrite = 0;
MemRead = 1;
Address = 0;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
$finish;
end
initial begin
$monitor("INPUT: MemWrite = %b\tMemRead = %b\tAddress = %h\tWrite_data = %h",
MemWrite, MemRead, Address, Write_data,
"\tOUTPUT: Read_data = %h",
Read_data);
forever begin
#10 clk = ~clk;
end
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:33:48 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Initial/Initial_funcsim.v
// Design : Initial
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Initial,blk_mem_gen_v8_2,{}" *)
(* core_generation_info = "Initial,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Initial.mif,C_INIT_FILE=Initial.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=1600,C_READ_WIDTH_A=1600,C_WRITE_DEPTH_A=600,C_READ_DEPTH_A=600,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=1600,C_READ_WIDTH_B=1600,C_WRITE_DEPTH_B=600,C_READ_DEPTH_B=600,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=44,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 119.8268 mW}" *)
(* NotValidForBitStream *)
module Initial
(clka,
addra,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
input [9:0]addra;
output [1599:0]douta;
wire [9:0]addra;
wire clka;
wire [1599:0]douta;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [1599:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [1599:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "44" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 119.8268 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "Initial.mem" *)
(* C_INIT_FILE_NAME = "Initial.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "3" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "600" *)
(* C_READ_DEPTH_B = "600" *)
(* C_READ_WIDTH_A = "1600" *)
(* C_READ_WIDTH_B = "1600" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "600" *)
(* C_WRITE_DEPTH_B = "600" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "1600" *)
(* C_WRITE_WIDTH_B = "1600" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Initial_blk_mem_gen_v8_2__parameterized0 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
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0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[1599:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[1599:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.wea(1'b0),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module Initial_blk_mem_gen_generic_cstr
(douta,
clka,
addra);
output [1599:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [1599:0]douta;
Initial_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[17:0]));
Initial_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[377:342]));
Initial_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[413:378]));
Initial_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[449:414]));
Initial_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[485:450]));
Initial_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[521:486]));
Initial_blk_mem_gen_prim_width__parameterized14 \ramloop[15].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[557:522]));
Initial_blk_mem_gen_prim_width__parameterized15 \ramloop[16].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[593:558]));
Initial_blk_mem_gen_prim_width__parameterized16 \ramloop[17].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[629:594]));
Initial_blk_mem_gen_prim_width__parameterized17 \ramloop[18].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[665:630]));
Initial_blk_mem_gen_prim_width__parameterized18 \ramloop[19].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[701:666]));
Initial_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[53:18]));
Initial_blk_mem_gen_prim_width__parameterized19 \ramloop[20].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[737:702]));
Initial_blk_mem_gen_prim_width__parameterized20 \ramloop[21].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[773:738]));
Initial_blk_mem_gen_prim_width__parameterized21 \ramloop[22].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[809:774]));
Initial_blk_mem_gen_prim_width__parameterized22 \ramloop[23].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[845:810]));
Initial_blk_mem_gen_prim_width__parameterized23 \ramloop[24].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[881:846]));
Initial_blk_mem_gen_prim_width__parameterized24 \ramloop[25].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[917:882]));
Initial_blk_mem_gen_prim_width__parameterized25 \ramloop[26].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[953:918]));
Initial_blk_mem_gen_prim_width__parameterized26 \ramloop[27].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[989:954]));
Initial_blk_mem_gen_prim_width__parameterized27 \ramloop[28].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1025:990]));
Initial_blk_mem_gen_prim_width__parameterized28 \ramloop[29].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1061:1026]));
Initial_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[89:54]));
Initial_blk_mem_gen_prim_width__parameterized29 \ramloop[30].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1097:1062]));
Initial_blk_mem_gen_prim_width__parameterized30 \ramloop[31].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1133:1098]));
Initial_blk_mem_gen_prim_width__parameterized31 \ramloop[32].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1169:1134]));
Initial_blk_mem_gen_prim_width__parameterized32 \ramloop[33].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1205:1170]));
Initial_blk_mem_gen_prim_width__parameterized33 \ramloop[34].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1241:1206]));
Initial_blk_mem_gen_prim_width__parameterized34 \ramloop[35].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1277:1242]));
Initial_blk_mem_gen_prim_width__parameterized35 \ramloop[36].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1313:1278]));
Initial_blk_mem_gen_prim_width__parameterized36 \ramloop[37].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1349:1314]));
Initial_blk_mem_gen_prim_width__parameterized37 \ramloop[38].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1385:1350]));
Initial_blk_mem_gen_prim_width__parameterized38 \ramloop[39].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1421:1386]));
Initial_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[125:90]));
Initial_blk_mem_gen_prim_width__parameterized39 \ramloop[40].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1457:1422]));
Initial_blk_mem_gen_prim_width__parameterized40 \ramloop[41].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1493:1458]));
Initial_blk_mem_gen_prim_width__parameterized41 \ramloop[42].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1529:1494]));
Initial_blk_mem_gen_prim_width__parameterized42 \ramloop[43].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1565:1530]));
Initial_blk_mem_gen_prim_width__parameterized43 \ramloop[44].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[1599:1566]));
Initial_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[161:126]));
Initial_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[197:162]));
Initial_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[233:198]));
Initial_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[269:234]));
Initial_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[305:270]));
Initial_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[341:306]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width
(douta,
clka,
addra);
output [17:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [17:0]douta;
Initial_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized1
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized10
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized10 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized11
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized11 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized12
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized12 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized13
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized13 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized14
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized14 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized15
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized15 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized16
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized16 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized17
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized17 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized18
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized18 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized19
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized19 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized2
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized20
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized20 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized21
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized21 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized22
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized22 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized23
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized23 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized24
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized24 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized25
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized25 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized26
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized26 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized27
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized27 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized28
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized28 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized29
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized29 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized3
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized3 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized30
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized30 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized31
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized31 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized32
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized32 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized33
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized33 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized34
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized34 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized35
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized35 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized36
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized36 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized37
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized37 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized38
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized38 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized39
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized39 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized4
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized4 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized40
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized40 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized41
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized41 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized42
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized42 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized43
(douta,
clka,
addra);
output [33:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [33:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized43 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized5
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized5 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized6
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized6 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized7
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized7 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized8
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized8 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Initial_blk_mem_gen_prim_width__parameterized9
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Initial_blk_mem_gen_prim_wrapper_init__parameterized9 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra);
output [17:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [17:0]douta;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP({douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized1
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized10
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h5777777777777777777777764000000000000000000000000000000000000000),
.INITP_01(256'h7777777777777777777777FFFDDDDD555555555555DDDDDDDDD5555555555555),
.INITP_02(256'hEEEEEE00000000000CCCCCCCCCCCCCEEEEEEEEEEFFFF00000000777777777777),
.INITP_03(256'h000000000008FFFFFFFBBBBBBBBBBFFFFFFF73000000000008CCCCCCCCCCCCCC),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h07C0000000000000000000000000000000000000000000000000000000000000),
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.INIT_07(256'h07FFAA5507FFAA5507FFAA5507FFAA5507FFAA5507FFAA5507FFAA5507FFAA55),
.INIT_08(256'h07FFAA5507FFAA5507FFAA5507FFAA5507FFAA5507FFAA5507FFAA5507FFAA55),
.INIT_09(256'hFFFFAA55FFFFAA5587FFAA5507FFAA5507FFAA5507FFAA5507FFAA5507FFAA55),
.INIT_0A(256'hAA55AA55AFFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55),
.INIT_0B(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0C(256'hFFFFAA55FFFFAA55FFFFAA55FFFFAA55FFFFAA55FF55AA55AA55AA55AA55AA55),
.INIT_0D(256'h1FFFAA551FFFAA551FFFAA551FFFAA551FFFAA557FFFAA55FFFFAA55FFFFAA55),
.INIT_0E(256'h1FFFEA551FFFEA551FFFAA551FFFAA551FFFAA551FFFAA551FFFAA551FFFAA55),
.INIT_0F(256'h07FFEA5507FFEA5507FFEA5507FFEA5507FFEA5507FFEA5507FFEA5507FFEA55),
.INIT_10(256'h01FFFFFF01FFFFFF01FFFFFF07FFEA5507FFEA5507FFEA5507FFEA5507FFEA55),
.INIT_11(256'h0000000000000000000000000000000001FFFFFF01FFFFFF01FFFFFF01FFFFFF),
.INIT_12(256'hFFFFFF00FFFFFF00FFFFFF00FFFFFFC000000000000000000000000000000000),
.INIT_13(256'h5FFFE0005FFFE00057FFE00057FFF80057FFF800FFFFF800FFFFFE00FFFFFE00),
.INIT_14(256'hFFFC0000FFFC0000FFFC0000FFFF00007FFF00007FFF00007FFF80005FFF8000),
.INIT_15(256'h00000000FF000000FF000000FFC00000FFC00000FFC00000FFF00000FFF00000),
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.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1FFFFFFF0003FFFF000000FF00000000),
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.INIT_1D(256'hFFFFFFFFFFFFFFFFFFFFFFFF55ABFFFF55AA7FFF55AAFFFF55AAFFFF55AAFFFF),
.INIT_1E(256'h000000000000000000000000F8000000FFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFF),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized11
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h00000000000000000000000137FFFFFFDD55555555577FFFFFFEC80000000000),
.INITP_02(256'hFFFFFF000000000003FFFFFFFEAAAAAAAAAAAFFFFFF300000000000000000000),
.INITP_03(256'h0000000000CFFFFFFFAAAAAAAAEEFFFFF730000000000000EFFFFFFFAAAAAAAA),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h00C0000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000C00000800),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00FFF00000E00000000000000000000000),
.INIT_0A(256'hAA55AA55AA55AA55AA55AAFFAA57FFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFF5AA55EA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0C(256'h000FFFFF1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE55),
.INIT_0D(256'h00000000000000000000000000000000000000000000000000000003000007FF),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF00FFFFFF00000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AAFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFFFFFFFFFFF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'h00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000),
.INIT_18(256'h55AA55AF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AAD5AA55AA),
.INIT_19(256'hFFFF8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5FFFFFFF),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'hFFFFFFFF7FFFFFFF000FFFFF000000FF00000000000000000000000000000000),
.INIT_1C(256'h55AA55AA55AA55AAFFAA55AAFFFFFDAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1D(256'hFFFFFFFF7FFFFFFF55AA55FF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_1E(256'h0000000000000000FFFC0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000FF0000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000FE0000000000000000000000),
.INIT_49(256'h00000000000000000000000000000000000000000000000000000000FF000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized12
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h7777777777FFFFFFFE8000000000000000000000000000000000000000000000),
.INITP_01(256'h7777777777777777777777777777777777775555555555555555557777777777),
.INITP_02(256'hFFFFFFCCCCCCCCCCCEFFFFFFFFFAAAAAAAAAFFFFFFF00000000008EFFFFF7777),
.INITP_03(256'h000000000EFFFFFFBAAAAAAEEFFFFFFFFEECCCCCCCCCCCCFFFFFFFBAAAAAAAAF),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h8800000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000008888CCCCCCCC8888000000000000CCCC88),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'hAAF0000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000EAAAAAEAA),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFF0FFFF8000F80000000000000000000000000000000000000000000000),
.INIT_06(256'hAAFFFFF0FFFFFFF0FFFFFFF0FFFFFFF0FFFFFFF0FFFFFFF0FFFFFFF0FFFFFFF0),
.INIT_07(256'hAA57FFF0AA57FFF0AA57FFF0AA57FFF0AA57FFF0AA57FFF0AA57FFF0AA57FFF0),
.INIT_08(256'hAA55FFFCAA55FFFCAA55FFF0AA55FFF0AA55FFF0AA55FFF0AA55FFF0AA55FFF0),
.INIT_09(256'hAA55FFFFAA55FFFFAA55FFFFAA55FFFFAA55FFFFAA55FFFFAA55FFFCAA55FFFC),
.INIT_0A(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55ABFFAA55FFFFAA55FFFF),
.INIT_0B(256'hAA55FFFFAA55FFFFAA55FFD5AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0C(256'hAA57FFC0AA57FFC0AA57FFCFAA57FFFFAA57FFFFAA57FFFFAA55FFFFAA55FFFF),
.INIT_0D(256'hAA57FFC0AA57FFC0AA57FFC0AA57FFC0AA57FFC0AA57FFC0AA57FFC0AA57FFC0),
.INIT_0E(256'hAA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA57FFC0),
.INIT_0F(256'hAA5FFF00AA5FFF00AA5FFF00AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0),
.INIT_10(256'hFFFFFF00FFFFFF00FFFFFF00FFFFFF00BFFFFF00AA7FFF00AA7FFF00AA7FFF00),
.INIT_11(256'h000000000000000000000000000000000000000080000000FFFFE000FFFFFF00),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55AA55AA55AAFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'h5FFFFFFF5FFFFFFF5FFFFFAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'h7FFF00007FFF80007FFFFFFF7FFFFFFF5FFFFFFF5FFFFFFF5FFFFFFF5FFFFFFF),
.INIT_16(256'hFFFC0000FFFC0000FFFC0000FFFC0000FFFC00007FFF00007FFF00007FFF0000),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000FFF00000),
.INIT_18(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AAFFFFFFFF),
.INIT_19(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF55FFFFFF55AA55AA),
.INIT_1A(256'hFFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFF00000FFFFFFF0),
.INIT_1B(256'h7FFF81FF7FFF80007FFF8000FFFF0000FFFF0000FFFF0000FFFF0000FFFF0000),
.INIT_1C(256'h5FFFF5AA5FFFFFFE5FFFFFFF5FFFFFFF7FFFFFFF7FFFFFFF7FFFFFFF7FFFFFFF),
.INIT_1D(256'h55AFFFFF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA5FAA55AA),
.INIT_1E(256'h00000000FFFFF800FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized13
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h7777777777777777777740000000000000000000000000000000000000000000),
.INITP_01(256'h3333333333333333333333333333333333333333333333333333333333333777),
.INITP_02(256'hEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEAAAAEFFFFFFF000000000033333333333),
.INITP_03(256'h00000008FFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h7700000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000007777CCCC0000111133336666CCCCCCCC77),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h15E0000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000D51112111),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h01FFFFFF01FFFFFF07FFFFFF07FFFF0007FC0000000000000000000000000000),
.INIT_06(256'h01FFFA5501FFFA5501FFFA7F01FFFFFF01FFFFFF01FFFFFF01FFFFFF01FFFFFF),
.INIT_07(256'h01FFFA5501FFFA5501FFFA5501FFFA5501FFFA5501FFFA5501FFFA5501FFFA55),
.INIT_08(256'h00FFFA5500FFFA5500FFFA5500FFFA5500FFFA5501FFFA5501FFFA5501FFFA55),
.INIT_09(256'h00FFFE5500FFFE5500FFFE5500FFFE5500FFFE5500FFFE5500FFFA5500FFFA55),
.INIT_0A(256'h00FFFE5500FFFE5500FFFE5500FFFE5500FFFE5500FFFE5500FFFE5500FFFE55),
.INIT_0B(256'h003FFF55003FFE55003FFE55003FFE55003FFE55003FFE55003FFE5500FFFE55),
.INIT_0C(256'h003FFF55003FFF55003FFF55003FFF55003FFF55003FFF55003FFF55003FFF55),
.INIT_0D(256'h000FFF55003FFF55003FFF55003FFF55003FFF55003FFF55003FFF55003FFF55),
.INIT_0E(256'h000FFFD5000FFFD5000FFFD5000FFFD5000FFF55000FFF55000FFF55000FFF55),
.INIT_0F(256'h000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5),
.INIT_10(256'h0003FFFF0003FFFF0003FFFF0003FFFF000FFFD5000FFFD5000FFFD5000FFFD5),
.INIT_11(256'h00000000000000000000000000000000000300000003FFFF0003FFFF0003FFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000000),
.INIT_13(256'hFFAA55AAFFAA55AAFFAA55AAFFFF55AAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AA),
.INIT_15(256'hFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AA),
.INIT_16(256'hFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AA),
.INIT_17(256'hFFEA55ABFFEA55ABFFEA55ABFFEA55ABFFEA55ABFFEA55ABFFEA55AAFFEA55AA),
.INIT_18(256'hFFEA55AAFFEA55AAFFEA55AAFFEA55AAFFEA55AAFFEA55AAFFEA55AAFFEA55AB),
.INIT_19(256'hFFEA55ABFFEA55AFFFEA55AFFFEA55AFFFEA55AFFFEA55AFFFEA55AAFFEA55AA),
.INIT_1A(256'hFFFA55AAFFFA55AAFFFA55ABFFFA55ABFFFA55ABFFFA55ABFFFA55ABFFFA55AB),
.INIT_1B(256'hFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AA),
.INIT_1C(256'hFFFE55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AA),
.INIT_1D(256'hFFFE55AAFFFE55AAFFFE55AAFFFE55AAFFFE55AAFFFE55AAFFFE55AAFFFE55AA),
.INIT_1E(256'hFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE57FF),
.INIT_1F(256'h00000000000000000000000000000000000000000000000000000000FE000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h01FFFFFF01FFFFFF000000000000000000000000000000000000000000000000),
.INIT_30(256'hFFFC0000FFFC0000FFFC000FFFFC000FFFFC000FFFFC000F01FFFFFF01FFFFFF),
.INIT_31(256'h0003FFF00003FFF001FFF80001FFF80001FFF80001FFF800FFFC0000FFFC0000),
.INIT_32(256'h0000000F0000000F000007FF000007FF000007FF000007FF0003FFF00003FFF0),
.INIT_33(256'h01FFFFFF01FFFFFFFFFC000FFFFC000FFFFC000FFFFC000F0000000F0000000F),
.INIT_34(256'h00000000000000000000000000000000000000000000000001FFFFFF01FFFFFF),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h000F01C3010F0703FF0FFE030000000000000000000000000000000000000000),
.INIT_48(256'h010F01C3000F0103000F0703000F0703000FF803000F0703000F01C3000F01C3),
.INIT_49(256'h00000000000000000000000000000000000000000000000000000000FF0F01C3),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized14
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h6666777777FEECCC888000000000000000000000000000000000000000000000),
.INITP_01(256'hCCEEFF766666CCCCCCC888888000000000000000000008888888CCCCCC444666),
.INITP_02(256'hEEEEEEEEEEEEEEEEEEEEEEEEECCCC88800000000000000000000000000000088),
.INITP_03(256'h00000000000000000000000000000000000000000000088888CCCCCCEEEEEEEE),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h3300000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000003333333333337777FFFFBBBB3333333333),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h6660000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000880000022),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFE000000E0000000800000000000000000000000000000000000000000000000),
.INIT_06(256'hABFFFFF0BFFFFFF0FFFFFF00FFFFF800FFFFE000FFFF0000FFF00000FFC00000),
.INIT_07(256'hABFFE000ABFFF800AAFFFE00AAFFFE00AA7FFF00AA7FFF00AA5FFFC0AA7FFFC0),
.INIT_08(256'hFFF00000FFFC0000FFFC0000FFFF0000BFFF0000BFFF8000AFFF8000AFFFE000),
.INIT_09(256'hF8000000F8000000FE000000FE000000FF000000FF000000FFC00000FFC00000),
.INIT_0A(256'h00000000000000000000000000000000000000008000000080000000E0000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h8000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'hFFF00000FFC00000FF000000FE000000FE000000F8000000E000000080000000),
.INIT_0E(256'hAFFFF800AFFFF800BFFFE000FFFF8000FFFF0000FFFF0000FFFC0000FFF00000),
.INIT_0F(256'hFFF00000FFFF0000FFFFE000FFFFFE00FFFFFFC0FFFFFFC0FFFFFF00AFFFFE00),
.INIT_10(256'h000000000000000000000000000000000000000000000000E0000000FE000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000003F0000003F0000003F0000000000000000000000000000000000000000),
.INIT_13(256'h0000003F0000003F0000003F0000003F0000003F0000003F0000003F0000003F),
.INIT_14(256'hFFFF803FFFFC003FFFF0003FFFC0003FFF00003FFE00003FE000003F8000003F),
.INIT_15(256'h57FF803F57FF803F57FF803F57FF803F57FF803F5FFF803F7FFF803FFFFF803F),
.INIT_16(256'h57FF800F57FF800F57FF800F57FF800F57FF800F57FF800F57FF800F57FF803F),
.INIT_17(256'h57FF800F57FF800F57FF800F57FF800F57FF800F57FF800F57FF800F57FF800F),
.INIT_18(256'hFFFF800F7FFF800F5FFF800F5FFF800F5FFF800F5FFF800F57FF800F57FF800F),
.INIT_19(256'hF8000003FE00000FFF00000FFFC0000FFFF0000FFFF0000FFFFC000FFFFF000F),
.INIT_1A(256'h000000030000000300000003000000030000000380000003E0000003F8000003),
.INIT_1B(256'h0000000300000003000000030000000300000003000000030000000300000003),
.INIT_1C(256'h0000000300000003000000030000000300000003000000030000000300000003),
.INIT_1D(256'h0000000000000000000000000000000300000003000000030000000300000003),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0003FFF00003FFF0000000000000000000000000000000000000000000000000),
.INIT_30(256'h0003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF0),
.INIT_31(256'hFFFFFFF0FFFFFFF0FE03FFF0FE03FFF0FE03FFF0FE03FFF00003FFF00003FFF0),
.INIT_32(256'h0003FFF00003FFF001FFFFF001FFFFF001FFFFF001FFFFF0FFFFFFF0FFFFFFF0),
.INIT_33(256'h0003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF0),
.INIT_34(256'h0000000000000000000000000000000000000000000000000003FFF00003FFF0),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0700803C0700E00F0700E0000000000000000000000000000000000000000000),
.INIT_48(256'hE03C000F603C003C60F3003018C300F018C300F018C300F018C380F01EC08030),
.INIT_49(256'h00000000000000000000000000000000000000000000000000000000E03C0000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized15
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h55555555555555577FFFFFEEC000000000000000000000000000000000000000),
.INITP_01(256'h77555555555555DDFFFFFFF7331100000000000000000001133377FFFFDDDDDD),
.INITP_02(256'hAAAAAAAAAAAAAEEEEAAAAAAAAAABBBBBBBBFEEECCCCC000000000008CEEFFFF7),
.INITP_03(256'h000000000000000000000000000000000CEEEEABBBBBBBBBBBAAAAAAAAAAAAAA),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h3300000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000003333333333333333333333333333333333),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h4440000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000444666444),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'hFFFF000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hAA5FFFFFFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFC0FFFFFF00FFFFF800FFFF8000),
.INIT_06(256'hAA55AA55AA55AA55AA55AA55AA55AA5FAA55AAFFAA55ABFFAA55BFFFAA55FFFF),
.INIT_07(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_08(256'hFFFFFA55FFFFAA55FFFFAA55FFF5AA55FFD5AA55FE55AA55FA55AA55AA55AA55),
.INIT_09(256'h00007FFF0000FFFF000FFFFF00FFFFFF07FFFFFF7FFFFFFFFFFFFFD7FFFFFE57),
.INIT_0A(256'h00000000000000000000000000000000000000000000000F000000FF000007FF),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h000FFFFF0000FFFF00001FFC000001FC00000030000000000000000000000000),
.INIT_0D(256'hFFFFAA7FFFFFFAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFFFF),
.INIT_0E(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA57FE55AA57FFF5AA5F),
.INIT_0F(256'hAA7FFFFFAA57FFFFAA55FFFFAA55AFFFAA55AAFFAA55AA57AA55AA55AA55AA55),
.INIT_10(256'hFFF00000FFFF8000FFFFF800FFFFFF00FFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_11(256'h00000000000000000000000000000000000000000000000000000000E0000000),
.INIT_12(256'hFFFC0000FFF00000FFC00000FF00000000000000000000000000000000000000),
.INIT_13(256'h55AFFFFF55BFFFFC55FFFFC055FFFF005FFFFE00FFFFF800FFFFE000FFFF0000),
.INIT_14(256'h55AA55AB55AA55BF55AA55FF55AA55FF55AA57FF55AA5FFF55AAFFFF55ABFFFF),
.INIT_15(256'hFFAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_16(256'hFDAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AA),
.INIT_17(256'hD5AA55AAF5AA55AAF5AA55AAF5AA55AAF5AA55AAFDAA55AAFDAA55AAFDAA55AA),
.INIT_18(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AAD5AA55AAD5AA55AAD5AA55AA),
.INIT_19(256'h55AA57FF55AA55FF55AA55FF55AA55FF55AA55BF55AA55AF55AA55AB55AA55AB),
.INIT_1A(256'h55BFFFC055AFFFF055ABFFF055AAFFFC55AAFFFF55AA7FFF55AA5FFF55AA57FF),
.INIT_1B(256'h00000000FFFF0000FFFF8000FFFFE000FFFFF800FFFFF80055FFFE0055BFFF00),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h003FFF00003FFF00000000000000000000000000000000000000000000000000),
.INIT_30(256'h003FFFFF003FFFFF003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00),
.INIT_31(256'h003FFF00003FFF00003FFFFF003FFFFF003FFFFF003FFFFF003FFFFF003FFFFF),
.INIT_32(256'h003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00),
.INIT_33(256'h003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00),
.INIT_34(256'h000000000000000000000000000000000000000000000000003FFF00003FFF00),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h01F01E0C01F01E3C01C01E3C0000000000000000000000000000000000000000),
.INIT_48(256'h01C07E0001C07E0301C09E0301C09E0301C39E0301C31E0F01CC1E0F01CC1E0C),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000001C01E00),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized16
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h777755555555555DFFFFFFF70000000000000000000000000000000000000000),
.INITP_01(256'hDDD5555555555577777777DCCCCCCC888888000888888CCCCCCCCEE677777777),
.INITP_02(256'h999999999BFFFFFFFEAAAAAAAAAAAAAAAAAAAFFFFFF300000000003777FFFDDD),
.INITP_03(256'h00000004CCCCCCCCCCC88888888888888FFFFFAAAAAAAAAAAAAEFFFFFFB99999),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'hFF00000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h000000000000000000000000000000FFFF9999999999999999999999999999FF),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h6660000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000666777666),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h000000FF00000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFD5FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFF),
.INIT_06(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55FE55AA55),
.INIT_07(256'hAA5FFFFFAA57FFF5AA57FFD5AA55FE55AA55FA55AA55AA55AA55AA55AA55AA55),
.INIT_08(256'hFFFFF9FFBFFFFFFFAFFFFFFFAFFFFFFFABFFFFFFAAFFFFFFAA7FFFFFAA7FFFFF),
.INIT_09(256'hFFF00000FFF00000FFFC0000FFFF0000FFFF0000FFFF8000FFFFE003FFFFF83F),
.INIT_0A(256'h80000000E0000000F8000000F8000000FE000000FF000000FF000000FFC00000),
.INIT_0B(256'hF8000000E0000000E00000008000000000000000000000000000000080000000),
.INIT_0C(256'hFFFC0000FFF00000FFF00000FFC00000FF000000FF000000FE000000FE000000),
.INIT_0D(256'hAAFFFFFFABFFFFFFAFFFFFFFBFFFFFFFBFFFFFFFFFFFFFFFFFFF01FFFFFF0000),
.INIT_0E(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA7FFFFFAAFFFFFF),
.INIT_0F(256'hFE55AA55EA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_10(256'h07FFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDFFFFFFF5AA7FFF55AA55),
.INIT_11(256'h0000000000000000000000000000000000000000000C000000FFFF0001FFFFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF003FFFFF00000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AAFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'hFFFFFFFFFFFFD5AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_16(256'hE00001FF8003FFFF87FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_17(256'hF80007FFF80007FFF80007FFE00007FFE00007FFE00001FFE00001FFE00001FF),
.INIT_18(256'hFFFFFFFEFFFFFFFFFE3FFFFFFE001FFFFE001FFFF8001FFFF80007FFF80007FF),
.INIT_19(256'h55AA55AA55AA55AA55AA55AAFFFA55AAFFFFFFFAFFFFFFFEFFFFFFFEFFFFFFFE),
.INIT_1A(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_1B(256'hF8000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF55AA55AA55AA55AA),
.INIT_1C(256'hFE000000FE000000FE000000F8000000F8000000F8000000F8000000F8000000),
.INIT_1D(256'hFF000000FF000000FF000000FE000000FE000000FE000000FE000000FE000000),
.INIT_1E(256'hFFC00000FFC00000FFC00000FF000000FF000000FF000000FF000000FF000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000007C00000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'hFFFFFF00FFFFFF00000000000000000000000000000000000000000000000000),
.INIT_30(256'hE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFFFFFFF00FFFFFF00),
.INIT_31(256'hE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFF),
.INIT_32(256'hE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFF),
.INIT_33(256'hFFFFFF00FFFFFF00E0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFF),
.INIT_34(256'h000000000000000000000000000000000000000000000000FFFFFF00FFFFFF00),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0703E03C0703E03C0703803C0000000000000000000000000000000000000000),
.INIT_48(256'h070380FC070380FC0703813C0703813C0703873C0703863C0703983C0703983C),
.INIT_49(256'h000000000000000000000000000000000000000000000000000000000703803C),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized17
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h55555DDDDDDDDDFFFFFFFF300000000000000000000000000000000000000000),
.INITP_01(256'h1333777FFDDDDDD5555555555555555557777777777555555555555555555555),
.INITP_02(256'hAABBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAFFFFFF000000000000000000011),
.INITP_03(256'h0000000017FFFEEAAAAAAAAAAAAAAAAAAABBBBAAAAAAAAAAAAAAAAAAAAAAAAAA),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h8800000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000008888111111111111111111111111111188),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h11E0000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000E11000800),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000FFFFF00000000),
.INIT_06(256'hFA55AA55FA55AA55FE55AA55FF55AA55FF55AA55FFD5AA55FFFFEA55FFFFFFFF),
.INIT_07(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55EA55AA55EA55AA55),
.INIT_08(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_09(256'hAA55AAFFAA55AAFFAA55AA7FAA55AA5FAA55AA5FAA55AA57AA55AA55AA55AA55),
.INIT_0A(256'hAA57FFFFAA55FFFFAA55FFFFAA55FFFFAA55BFFFAA55BFFFAA55AFFFAA55ABFF),
.INIT_0B(256'hAA55FFFFAA55FFFFAA55FFFFAA57FFFFAA5FFFFFAA7FFFFFAA7FFFFFAA5FFFFF),
.INIT_0C(256'hAA55AA5FAA55AA5FAA55AA7FAA55AAFFAA55ABFFAA55ABFFAA55AFFFAA55BFFF),
.INIT_0D(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA57),
.INIT_0E(256'hFFFFAA55FFFFAA55FFF5AA55FFD5AA55FE55AA55FA55AA55AA55AA55AA55AA55),
.INIT_0F(256'h00007FFF0003FFFF000FFFFF00FFFFFD01FFFFF507FFFF557FFFFE55FFFFFA55),
.INIT_10(256'h0000000000000000000000000000000F0000003F000000FF000007FF00001FFF),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000000),
.INIT_13(256'hD5AA55AAD5AA55AAD5AA55AAD5AA55AAD5AA55AAFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hD5AA55AAD5AA55AAD5AA55AAD5AA55AAD5AA55AAD5AA55AAD5AA55AAD5AA55AA),
.INIT_15(256'hD5AA5FFFD5AA5FFFD5AA55AAD5AA55AAD5AA55AAD5AA55AAD5AA55AAD5AA55AA),
.INIT_16(256'h55AA55FF55AA57FF55AA57FF55AA57FF55AA57FF55AA57FF55AA57FF55AA5FFF),
.INIT_17(256'h55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_18(256'h55AA55BF55AA55BF55AA55BF55AA55BF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_19(256'h55AA55AA55AA55AA55AA55AA55AA55AF55AA55AF55AA55BF55AA55BF55AA55BF),
.INIT_1A(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_1B(256'h55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55AA55AA55AA),
.INIT_1C(256'h55AA55BF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_1D(256'h55AA55AF55AA55BF55AA55BF55AA55BF55AA55BF55AA55BF55AA55BF55AA55BF),
.INIT_1E(256'h00001FFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAFFFEA55AF55AA55AF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized18
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h3333333111111100000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000011333333333333333333333333333333333333333333333333333),
.INITP_02(256'h1111111111111111111111111111111111111111110800000000088888880000),
.INITP_03(256'h0000000000119DDDDDDDDD999999999999999991111111111111111111111111),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h7700000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000007777333333333333333333333333333377),
.INITP_07(256'h000000088888888888888888888888888888888CCCC000000000000000000000),
.INITP_08(256'h10E0000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000D10002811),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000003F0000000F0000000F0000000300000003000000000000000000000000),
.INIT_06(256'h00001FFF00001FFF000007FF000007FF000001FF000001FF000000FF0000003F),
.INIT_07(256'h000FFFF5000FFFF5000FFFFD0003FFFF0003FFFF0000FFFF0000FFFF00007FFF),
.INIT_08(256'h000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5),
.INIT_09(256'h000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5000FFFD5),
.INIT_0A(256'h0003FFD50003FFD50003FFD50003FFD50003FFD5000FFFD5000FFFD5000FFFD5),
.INIT_0B(256'h0003FFD50003FFD50003FFD50003FFD50003FFD50003FFD50003FFD50003FFD5),
.INIT_0C(256'h0003FFD50003FFD50003FFD50003FFD50003FFD50003FFD50003FFD50003FFD5),
.INIT_0D(256'h0003FFF50003FFD50003FFD50003FFD50003FFD50003FFD50003FFD50003FFD5),
.INIT_0E(256'h0000000F0000003F000000FF000007FF00001FFF0000FFFF0003FFFF0003FFFF),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'hE000000080000000800000008000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000E0000000E0000000E0000000),
.INIT_12(256'h000007FF000007FF000000FF8000000000000000000000000000000000000000),
.INIT_13(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_14(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_15(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_16(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_17(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_18(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_19(256'h00001FFE00001FFE00001FFE00001FFE00001FFE00001FFE00001FFE00001FFF),
.INIT_1A(256'h00007FFE00007FFE00007FFE00007FFE00001FFE00001FFE00001FFE00001FFE),
.INIT_1B(256'hFE007FFEFE007FFEFE007FFEFE007FFEFE007FFEFE007FFEFE007FFE00007FFE),
.INIT_1C(256'hFE007FFAFE007FFAFE007FFAFE007FFAFE007FFAFE007FFAFE007FFEFE007FFE),
.INIT_1D(256'hFF007FFAFF007FFAFF007FFAFF007FFAFF007FFAFF007FFAFE007FFAFE007FFA),
.INIT_1E(256'h000000000000000000007FFF00007FFFE0007FFFFF007FFFFF007FFFFF007FFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h01FFFFFF01FFFFFF000000000000000000000000000000000000000000000000),
.INIT_30(256'h0003FFF00003FFF00003FFF00003FFF00003FFF00003FFF001FFFFFF01FFFFFF),
.INIT_31(256'h0003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF0),
.INIT_32(256'h0003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF0),
.INIT_33(256'h01FFFFFF01FFFFFF0003FFF00003FFF00003FFF00003FFF00003FFF00003FFF0),
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.INIT_3A(256'hFFFF0000FFFF0000FFFF00000000000000000000000000000000000000000000),
.INIT_3B(256'h80000000800000008000000080000000800000008000000080000000FFFF0000),
.INIT_3C(256'h8000000080000000800000008000000080000000800000008000000080000000),
.INIT_3D(256'h8000000080000000800000008000000080000000800000008000000080000000),
.INIT_3E(256'h8000000080000000800000008000000080000000800000008000000080000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000080000000),
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.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h003C070F003C1E0FFF3FF80F0000000000000000000000000000000000000000),
.INIT_48(256'h003C070F003C060F003C1E0F003C1E0F003FE00FFE3C1E0F003C070F003C070F),
.INIT_49(256'h00000000000000000000000000000000000000000000000000000000FF3C070F),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized19
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h7777777777777666666666666664CCCCCCCCCCCCCCCC88888888888880000000),
.INITP_02(256'hFFFFFF00000000000CCEEEEEEEEEAABBBBBBBFFFFFFF000000000FFFFFF57777),
.INITP_03(256'h00000000000CFFFFFFFBABBBBBBBBFFFFFFF3100000000000CEEEEEEEEAAAAAA),
.INITP_04(256'h8888CCCC66666666666666660000000000000000000000000000000000000000),
.INITP_05(256'hEE00000000000000000000000000000000000000000000000000888888888888),
.INITP_06(256'h00000000000000000000000000000088888888888888888888888888888888EE),
.INITP_07(256'h0000000111111111111111111111111111111117777000000000000000000000),
.INITP_08(256'h4470000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h8000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'hF8000000F8000000F8000000E0000000E0000000E00000008000000080000000),
.INIT_0A(256'hFF000000FF000000FF000000FF000000FE000000FE000000FE000000F8000000),
.INIT_0B(256'hFFFC0000FFFC0000FFF00000FFF00000FFF00000FFC00000FFC00000FFC00000),
.INIT_0C(256'hFFFF8000FFFF8000FFFF8000FFFF0000FFFF0000FFFF0000FFFC0000FFFC0000),
.INIT_0D(256'hABFFFE00AFFFF800AFFFF800AFFFF800AFFFE000BFFFE000BFFFE000BFFF8000),
.INIT_0E(256'hAA7FFFC0AA7FFFC0AAFFFF00AAFFFF00AAFFFF00AAFFFE00ABFFFE00ABFFFE00),
.INIT_0F(256'hAA57FFFCAA57FFFCAA57FFFCAA5FFFF0AA5FFFF0AA5FFFF0AA7FFFC0AA7FFFC0),
.INIT_10(256'hFFFFFFFFFFFFFFFFFFFFFFFFAA55FFFFAA55FFFFAA55FFFFAA55FFFFAA57FFFF),
.INIT_11(256'h0000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000000000000000000000),
.INIT_13(256'h55BFFFC055BFFFC055AFFFC055AFFFF055AFFFF0FFFFFFF0FFFFFFFCFFFFFFFC),
.INIT_14(256'hFFFFF80055FFF80055FFF80055FFFE0055FFFE0055FFFE0055FFFF0055BFFF00),
.INIT_15(256'h00000000FFFF0000FFFF0000FFFF8000FFFF8000FFFF8000FFFFE000FFFFE000),
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.INIT_18(256'h5FFFF80055FFF80055FFFE0055FFFE0055FFFE0055FFFE0055BFFE0055BFFE00),
.INIT_19(256'h00000000FFFC0000FFFFE000FFFFE000FFFFE000FFFFF800FFFFF800FFFFF800),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF003FFFFF000007FF0000000000000000),
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.INIT_1D(256'hFFFFFFFFFFFFFFFFFFFFFFFF55AA57FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_1E(256'h000000000000000000000000FFF00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h01FFF80001FFF80001FFF80001FFF80001FFF80001FFF80001FFF80001FFF800),
.INIT_26(256'h01FFF80001FFF80001FFF80001FFF80001FFF80001FFF80001FFF80001FFF800),
.INIT_27(256'hFE000000FE000000FE000000FE000000FFFC0000FFFC0000FFFC0000FFFC0000),
.INIT_28(256'hFE000000FE000000FE000000FE000000FE000000FE000000FE000000FE000000),
.INIT_29(256'h00000000000000000000000000000000FE000000FE000000FE000000FE000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'hFFFFF800FFFFF800000000000000000000000000000000000000000000000000),
.INIT_30(256'hFE000000FE000000FE000000FE000000FE000000FE000000FFFFF800FFFFF800),
.INIT_31(256'hFE000000FE000000FE000000FE000000FE000000FE000000FE000000FE000000),
.INIT_32(256'hFE000000FE000000FE000000FE000000FE000000FE000000FE000000FE000000),
.INIT_33(256'hFE000000FE000000FE000000FE000000FE000000FE000000FE000000FE000000),
.INIT_34(256'h000000000000000000000000000000000000000000000000FE000000FE000000),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h07FFFFFF07FFFFFF07FFFFFF0000000000000000000000000000000000000000),
.INIT_3B(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF07FFFFFF),
.INIT_3C(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_3D(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_3E(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000001FFF),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h070F000F070F000F070FFF0F0000000000000000000000000000000000000000),
.INIT_48(256'h1F0F000F1F0F000F670F000F670F000FE70F000F870FFE0F070F000F070F000F),
.INIT_49(256'h00000000000000000000000000000000000000000000000000000000070FFF0F),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized2
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized20
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h77777777776EEEEEEEC800000000000000000000000000000000000000000000),
.INITP_01(256'h77777FFFFFFDDDD5555555555555DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDFFF7),
.INITP_02(256'hFFFFFF000000000001FFFFFFFEAAAAAAAAAAAFFFFFF300000000033333333377),
.INITP_03(256'h0000000000EFFFFFFBAAAAAAAAEFFFFFF310000000000008FFFFFFFBAAAAAAAE),
.INITP_04(256'h0000111133333333333333330000000000000000000000000000000000000000),
.INITP_05(256'h3300000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000033),
.INITP_07(256'h0000000EEEE33333333333333333333333333333333000000000000000000000),
.INITP_08(256'h8840000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000488004000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFF800FFFFE000FFF00000FE00000000000000000000000000000000000000),
.INIT_06(256'hAA7FFF00AA7FFF00ABFFFE00FFFFFE00FFFFFE00FFFFFE00FFFFF800FFFFF800),
.INIT_07(256'hAA57FFF0AA57FFF0AA57FFF0AA5FFFF0AA5FFFC0AA5FFFC0AA5FFFC0AA7FFF00),
.INIT_08(256'hEA55FFFFEA55FFFFEA55FFFFAA55FFFFAA55FFFFAA55FFFCAA55FFFCAA57FFFC),
.INIT_09(256'hFA55ABFFFA55AFFFFA55AFFFEA55AFFFEA55AFFFEA55BFFFEA55BFFFEA55BFFF),
.INIT_0A(256'hFE55AA7FFE55AA7FFE55AAFFFE55AAFFFA55AAFFFA55AAFFFA55ABFFFA55ABFF),
.INIT_0B(256'hFF55AA57FF55AA57FF55AA57FF55AA5FFE55AA5FFE55AA5FFE55AA7FFE55AA7F),
.INIT_0C(256'hAA55AA55AA55AA55AA55AA55ABD5AA55FF55AA55FF55AA55FF55AA55FF55AA57),
.INIT_0D(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0E(256'hFFFFAA55FFFFAA55FFFFAA55FFFDAA55FFD5AA55FE55AA55EA55AA55AA55AA55),
.INIT_0F(256'h01FFFA5501FFFA5507FFEA5507FFEA551FFFEA55FFFFEA55FFFFEA55FFFFAA55),
.INIT_10(256'h003FFFFF003FFFFF00FFFFFF00FFFE5500FFFE5500FFFE5501FFFA5501FFFA55),
.INIT_11(256'h0000000000000000000000000000000000000000000FFFFF003FFFFF003FFFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF0000FFFF00000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55AA55AA55AAFDAA55AAFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFFFFFFFFFFFFFAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'h0000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000),
.INIT_18(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AAFFAA55AA),
.INIT_19(256'hFFFFFF00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF55BFFFFF),
.INIT_1A(256'h00000000000000000000000000000000000000000000000000000000E0000000),
.INIT_1B(256'hFFFFFFFF00FFFFFF00001FFF0000000000000000000000000000000000000000),
.INIT_1C(256'h55AA55AAFDAA55AAFFFF55AAFFFFFFFAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1D(256'hFFFFFFFF55FFFFFF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_1E(256'h0000000000000000FFFFF800FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00),
.INIT_26(256'h003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00),
.INIT_27(256'h000000FF000000FF000000FF000000FF00007FFF00007FFF00007FFF00007FFF),
.INIT_28(256'h000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF),
.INIT_29(256'h00000000000000000000000000000000000000FF000000FF000000FF000000FF),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h003FFFFF003FFFFF000000000000000000000000000000000000000000000000),
.INIT_30(256'h000000FF000000FF000000FF000000FF000000FF000000FF003FFFFF003FFFFF),
.INIT_31(256'h000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF),
.INIT_32(256'h000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF),
.INIT_33(256'h000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF),
.INIT_34(256'h000000000000000000000000000000000000000000000000000000FF000000FF),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h000FFFC0000FFFC0000FFFC00000000000000000000000000000000000000000),
.INIT_3B(256'h000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0),
.INIT_3C(256'h000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0),
.INIT_3D(256'h000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0),
.INIT_3E(256'hFFFFE000FFFFE000FFFFE000000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0),
.INIT_3F(256'h00000000000000000000000000000000000000000000000000000000FFFFE000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h800078FCE03078FC1FF078F00000000000000000000000000000000000000000),
.INIT_48(256'hE03C78F0803C78F0003C78F0003C78F001FC78F0000078F0000078F3000078F3),
.INIT_49(256'h000000000000000000000000000000000000000000000000000000001FF078F0),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized21
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h775555DDDDDDDDFFFFFFFFE40000000000000000000000000000000000000000),
.INITP_01(256'h000000001133377FFFFDDDDD5555555777FFFFFEC8888CDDDDDD777777777777),
.INITP_02(256'hFFFFFFEEEEEEEAAAABBBBBBBBBBAAAAAAAAAFFFFFFF000000000000000000000),
.INITP_03(256'h000000008FFFFFFFBAAAAAAABBBBBBBBBBBEEEEEEEEEEEEFFFFFFFBAAAAAAAAF),
.INITP_04(256'hFFFFBBBBBBBBBBBBEEEE44440000000000000000000000000000000000000000),
.INITP_05(256'hEE00000000000000000000000000000000000000000000000000BBBBBBBBBBBB),
.INITP_06(256'h000000000000000000000000000000EEEEBBBBBBBB888888888888BBBBBBBBEE),
.INITP_07(256'h00000001111BBBBBBBBBBBBBBBBBBBBBBBBBBBB3333000000000000000000000),
.INITP_08(256'h1190000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000911111933),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h7E00000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00FFFFE0007FF00000),
.INIT_06(256'hEA55AA55EA55AA55FA55AA55FA55AA55FE55AAFFFF55BFFFFF5FFFFFFFFFFFFF),
.INIT_07(256'hAA55FFD5AA55FE55AA55EA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_08(256'hABFFFFFFABFFFFFFAAFFFFFFAAFFFFFFAA7FFFFFAA5FFFFFAA5FFFFFAA57FFFD),
.INIT_09(256'hFFF001FFFFFC01FFFFFC01FFFFFF01FFFFFF81FFBFFFE1FFBFFFE1FFAFFFF9FF),
.INIT_0A(256'hFFC000FFE00000FFF80000FFF80000FFFE0000FFFF0000FFFFC001FFFFC001FF),
.INIT_0B(256'hAAFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80FF),
.INIT_0C(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA7FAA55AFFFAA57FFFF),
.INIT_0D(256'hFFFFFFF5FFFFFF55FFFFEA55FFFFAA55FFF5AA55FF55AA55FA55AA55AA55AA55),
.INIT_0E(256'h000007FF00001FFF0000FFFF000FFFFF00FFFFFF07FFFFFF7FFFFFFFFFFFFFFF),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000F000000FF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55AA55AA55AAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'h55BFFFFF55BFFFFF55BFFFFF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'h55FFFE0055FFFF0055FFFFFF55FFFFFF55BFFFFF55BFFFFF55BFFFFF55BFFFFF),
.INIT_16(256'h55FFF80055FFF80055FFF80055FFF80055FFF80055FFFE0055FFFE0055FFFE00),
.INIT_17(256'h57FFFFFF57FFFFFF57FFFFFF57FFFFFF57FFFFFF57FFFFFF55FFF80055FFE000),
.INIT_18(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA57FFFFFF),
.INIT_19(256'h57FFFFFF5FFFFFFF5FFFFFFF5FFFFFFF5FFFFFFF5FFFFFFF55AAFFFF55AA55AA),
.INIT_1A(256'h55FFF80055FFF80057FFF80057FFF80057FFF80057FFF80057FFE00057FFFFFF),
.INIT_1B(256'h55FFFF0355FFFF0055FFFF0055FFFE0055FFFE0055FFFE0055FFFE0055FFFE00),
.INIT_1C(256'h55BFFFEA55BFFFFF55BFFFFF55BFFFFF55FFFFFF55FFFFFF55FFFFFF55FFFFFF),
.INIT_1D(256'h55AA5FFF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55BF55AA),
.INIT_1E(256'hF8000000FFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'hFFFFFE00FFFFFE00FFFFFE00FFFFFE007FFF00007FFF00007FFF00007FFF0000),
.INIT_26(256'h8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC),
.INIT_27(256'hFFFFFFFCFFFFFFFCFFFFFFFCFFFFFFFC8000FFFC8000FFFC8000FFFC8000FFFC),
.INIT_28(256'h8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC),
.INIT_29(256'h000000000000000000000000000000008000FFFC8000FFFC8000FFFC8000FFFC),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'hFFFFFE00FFFFFE00000000000000000000000000000000000000000000000000),
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.INIT_31(256'h8000000080000000800000008000000080000000800000008000FFFC8000FFFC),
.INIT_32(256'h8000FFFC8000FFFC800000008000000080000000800000008000000080000000),
.INIT_33(256'hFFFFFE00FFFFFE008000FFFC8000FFFC8000FFFC8000FFFC8000FFFC8000FFFC),
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.INIT_3A(256'h0000FFFC0000FFFC0000FFFC0000000000000000000000000000000000000000),
.INIT_3B(256'hE000FFFCE000FFFCE000FFFCE000FFFCE000FFFCE000FFFCE000FFFC0000FFFC),
.INIT_3C(256'hE000FFFCE000FFFCE000FFFCE000FFFCE000FFFCE000FFFCE000FFFCE000FFFC),
.INIT_3D(256'hE000FFFCE000FFFCE000FFFCE000FFFCE000FFFCE000FFFCE000FFFCE000FFFC),
.INIT_3E(256'h000001FF000001FF000001FFE000FFFCE000FFFCE000FFFCE000FFFCE000FFFC),
.INIT_3F(256'h00000000000000000000000000000000000000000000000000000000000001FF),
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.INIT_47(256'h003F01C3003F01C0FE3C01C00000000000000000000000000000000000000000),
.INIT_48(256'h003C07C0003C07C3003C19C3003C19CF003C79CFF83C61CF003C81CF003C81C3),
.INIT_49(256'h00000000000000000000000000000000000000000000000000000000FE3C01C0),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized22
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h3333333311111110000000000000000000000000000000000000000000000000),
.INITP_01(256'h888888CCCCCCCCCCCCF777777777555555555755DDDDDDDDDDDDDDDF77777773),
.INITP_02(256'h6666666666666666666666666666666666667777777000000000000000000000),
.INITP_03(256'h0000000477777776666666666666666666666666666666666666666666666666),
.INITP_04(256'h1111111111111111000000000000000000000000000000000000000000000000),
.INITP_05(256'hCC00000000000000000000000000000000000000000000000000DDDD11111111),
.INITP_06(256'h0000000000000000000000000000008888DDDDDDDDDDDDDDDDDDDDDDDDDDDDCC),
.INITP_07(256'h0000000FFFF9999999999999999999999999999FFFF000000000000000000000),
.INITP_08(256'h0220000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000800000444),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000003F0000003F0000000F0000000F00000003000000030000000000000000),
.INIT_06(256'h00007FFF00007FFF00001FFF000007FF000007FF000001FF000001FF000000FF),
.INIT_07(256'h00FFFFD5003FFFF5003FFFF5000FFFFD0003FFFD0003FFFF0000FFFF0000FFFF),
.INIT_08(256'h7FFFAA557FFFEA551FFFEA551FFFFA5507FFFE5507FFFE5501FFFF5500FFFF55),
.INIT_09(256'hFFD5AA5FFFD5AA57FFF5AA55FFF5AA55FFFDAA55FFFFAA55FFFFAA55FFFFAA55),
.INIT_0A(256'hAA55BFFFAA55AFFFEA55ABFFFA55ABFFFA55AAFFFE55AAFFFE55AA7FFF55AA5F),
.INIT_0B(256'hAA55AA55AA55AA55AA55AA5FAA55ABFFAA55FFFFAA55FFFFAA55FFFFAA55BFFF),
.INIT_0C(256'hABFFFFFDABFFFFD5AAFFFE55AAFFEA55AA7FAA55AA55AA55AA55AA55AA55AA55),
.INIT_0D(256'hFFFF003FFFFF00FFFFFF87FFFFFFFFFFFFFFFFFFBFFFFFFFAFFFFFFFAFFFFFFF),
.INIT_0E(256'hFFC00000FFC00000FFC00000FFF00000FFF00000FFFC0000FFFC0000FFFC0003),
.INIT_0F(256'hE0000000F8000000F8000000F8000000FE000000FE000000FF000000FF000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000060000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h7FFFFFFF7FFFFFFF7FFFFFFF0000000000000000000000000000000000000000),
.INIT_13(256'h7FFE55AA7FFE55AA7FFE55AA7FFFFFAA7FFFFFFF7FFFFFFF7FFFFFFF7FFFFFFF),
.INIT_14(256'h7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFE55AA),
.INIT_15(256'h7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA),
.INIT_16(256'h1FFF55AA1FFF55AA1FFF55AA1FFF55AA1FFF55AA1FFF55AA1FFF55AA7FFF55AA),
.INIT_17(256'h1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA),
.INIT_18(256'h1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA),
.INIT_19(256'h07FFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA1FFFD5AA),
.INIT_1A(256'h07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA),
.INIT_1B(256'h07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA),
.INIT_1C(256'h07FFFDAA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA07FFF5AA),
.INIT_1D(256'h01FFFDAA01FFFDAA01FFFDAA07FFFDAA07FFFDAA07FFFDAA07FFFDAA07FFFDAA),
.INIT_1E(256'h01FFFFFF01FFFFFF01FFFFFF01FFFFFF01FFFFFF01FFFFFF01FFFFFF01FFFDAF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000001FC0000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000003F0000003F0000003F0000003F00000000000000000000000000000000),
.INIT_26(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_27(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_28(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_29(256'h00000000000000000000000000000000FF001FFFFF001FFFFF001FFFFF001FFF),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'hFF00003FFF00003F000000000000000000000000000000000000000000000000),
.INIT_30(256'hFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF00003FFF00003F),
.INIT_31(256'hFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF001FFF),
.INIT_32(256'hFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF001FFF),
.INIT_33(256'h8000003F8000003FFF001FFFFF001FFFFF001FFFFF001FFFFF001FFFFF001FFF),
.INIT_34(256'h0000000000000000000000000000000000000000000000008000003F8000003F),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'hFFFFFFF0FFFFFFF0FFFFFFF00000000000000000000000000000000000000000),
.INIT_3B(256'hFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFFFFFFF0),
.INIT_3C(256'hFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FF),
.INIT_3D(256'hFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FFFE0007FF),
.INIT_3E(256'hFFFFFFF0FFFFFFF0FFFFFFF0FE0007FFFE0007FFFE0007FFFE0007FFFE0007FF),
.INIT_3F(256'h00000000000000000000000000000000000000000000000000000000FFFFFFF0),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0603003C1E03803C7800E03F0000000000000000000000000000000000000000),
.INIT_48(256'h00F0003C00F0003C00F0003C00F0003C00F0003C01FC003F010C003C070F003C),
.INIT_49(256'h00000000000000000000000000000000000000000000000000000000E0F0003F),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized23
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0013377FFFFFDDDDDDDDDDDDDF77777773333333311111110000000000000000),
.INITP_02(256'hCCCCCC000000000008888888888CCCCCCCCCCCCCEEEE00000000000000000000),
.INITP_03(256'h000000000000EFFFFFFFBBBBBBBBBBFFFFFFF710000000000088888888CCCCCC),
.INITP_04(256'hCCCCCCCCCCCCCCCCCCCCCCCC0000000000000000000000000000000000000000),
.INITP_05(256'hCC00000000000000000000000000000000000000000000000000FFFFCCCCCCCC),
.INITP_06(256'h0000000000000000000000000000007777CCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INITP_07(256'h00000008888CCCCCCCCCCCC8888CCCCCCCCCCCC8888000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h000000FF000000FF0000003F0000000F0000000F000000030000000300000000),
.INIT_0A(256'h0000FFFF00007FFF00007FFF00001FFF00001FFF000007FF000001FF000001FF),
.INIT_0B(256'h01FFFF5500FFFFD5003FFFD5003FFFF5000FFFFD000FFFFD0003FFFF0000FFFF),
.INIT_0C(256'hFFFFAA55FFFFAA557FFFEA551FFFEA551FFFFA5507FFFA5507FFFE5501FFFF55),
.INIT_0D(256'hFF55AA57FF55AA55FFD5AA55FFD5AA55FFF5AA55FFFDAA55FFFDAA55FFFFAA55),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAFFFFFFAA7FFFD5AA5FFE55AA5FFE55AA57),
.INIT_0F(256'h0000000F000000FF00001FFF0000FFFF003FFFFF01FFFFFF7FFFFFFFFFFFFFFF),
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.INIT_13(256'hFFF00000FFF00000FFF00000FFFC0000FFFC0000FFFC0000FFFF0000FFFF0000),
.INIT_14(256'hFE000000FE000000FE000000FF000000FF000000FF000000FFC00000FFC00000),
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.INIT_17(256'hFFC00000FFC00000FFC00000FFC00000FFC00000FFF000000000000000000000),
.INIT_18(256'hFE000000FE000000FF000000FF000000FF000000FF000000FF000000FF000000),
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.INIT_1B(256'hFFFFFF00FFFFFF00FFFFFF00FFFFFF00FFFFFF0001FFFF0000007F0000000000),
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.INIT_3B(256'hFFFC00FFFFFC00FFFFFC00FFFFFC00FFFFFC00FFFFFC00FFFFFC00FFFE000000),
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.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized24
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000089999999988888888888888888888888888888888888888888800000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized25
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h766666CCCCCCC888880000000000000000000000000000000000000000000000),
.INITP_01(256'h088CCEFFFF777555555555555555555555555555555555555555555557777777),
.INITP_02(256'hFFFFFF8888888CCCCCFFFFFFFFEAAAAAAAAAEFFFFFF000000000000000000000),
.INITP_03(256'h000000000CFFFFFFFAAAAAAAEEFFFFFFFCCCCCCC8888888EFFFFFFFAAAAAAAAF),
.INITP_04(256'h2222333322222222222233330000000000000000000000000000000000000000),
.INITP_05(256'h3300000000000000000000000000000000000000000000000000222222222222),
.INITP_06(256'h0000000000000000000000000000002222222222222222333322222222222233),
.INITP_07(256'h0000000333333333333FFFF333333333333EEEECCCC000000000000000000000),
.INITP_08(256'h3710000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000C62000001),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hE000000080000000000000000000000000000000000000000000000000000000),
.INIT_06(256'hFFFC0000FFF00000FFC00000FFC00000FF000000FE000000F8000000F8000000),
.INIT_07(256'hABFFFF00AFFFFE00AFFFFE00BFFFF800FFFFE000FFFF8000FFFF0000FFFF0000),
.INIT_08(256'hAA55FFFFAA55FFFFAA57FFFFAA5FFFFFAA5FFFFCAA7FFFF0AAFFFFF0AAFFFFC0),
.INIT_09(256'hAA55ABFFAA55ABFFAA55AAFFAA55ABFFAA55AFFFAA55AFFFAA55BFFFAA55FFFF),
.INIT_0A(256'hAA55ABFFAA55ABFFAA55ABFFAA55ABFFAA55ABFFAA55ABFFAA55ABFFAA55ABFF),
.INIT_0B(256'hAA55AFFFAA55AFFFAA55AFFFAA55AFFFAA55AFFFAA55AFFFAA55AFFFAA55ABFF),
.INIT_0C(256'hAA55BFFFAA55BFFFAA55BFFFAA55BFFFAA55BFFFAA55AFFFAA55AFFFAA55AFFF),
.INIT_0D(256'hAA55FFFFAA55FFFFAA55BFFFAA55BFFFAA55BFFFAA55BFFFAA55BFFFAA55BFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFBFFFFFFFAAFFFFFFAA5FFFFFAA55FFFFAA55FFFFAA55FFFF),
.INIT_0F(256'h0000000080000000F8000000FFC00000FFFC0000FFFFE000FFFFFF00FFFFFFF0),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55AA55AA55AAFFFFFFAAFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFFFFFFFFFFFFFFFFFFFD5AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'hFF000000FFC00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_16(256'hFE000000FE000000FE000000FE000000FE000000FF000000FF000000FF000000),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000F8000000),
.INIT_18(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AAFFFFFFEA),
.INIT_19(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFF55AA55AF),
.INIT_1A(256'hFE000000FE000000FE000000FE000000FE000000FE000000F8000000FFFFF800),
.INIT_1B(256'hFFC0FFFFFFC0003FFFC00000FF000000FF000000FF000000FF000000FF000000),
.INIT_1C(256'hFFFA55AAFFFFFFAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1D(256'h57FFFFFF55AA55BF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AAD5AA55AA),
.INIT_1E(256'h00000000FFFC0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h00FFFE0000FFFE0000FFFE0000FFFE0000FFFFFF00FFFFFF00FFFFFF00FFFFFF),
.INIT_26(256'h00FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE00),
.INIT_27(256'h00FFFE0000FFFE0000FFFE0000FFFE0000FFFFFF00FFFFFF00FFFFFF00FFFFFF),
.INIT_28(256'h00FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE00),
.INIT_29(256'h0000000000000000000000000000000000FFFE0000FFFE0000FFFE0000FFFE00),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h00FFFFFF00FFFFFF000000000000000000000000000000000000000000000000),
.INIT_30(256'h00FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFFFF00FFFFFF),
.INIT_31(256'h00FFFFFF00FFFFFF00FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE00),
.INIT_32(256'h00FFFE0000FFFE0000FFFE0300FFFE0300FFFE0300FFFE0300FFFFFF00FFFFFF),
.INIT_33(256'h00FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE00),
.INIT_34(256'h00000000000000000000000000000000000000000000000000FFFE0000FFFE00),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'hFFC00000FFC00000FFC000000000000000000000000000000000000000000000),
.INIT_3B(256'h003FFF00003FFF00003FFF00FFFF8000FFFF8000FFFF8000FFFF8000FFC00000),
.INIT_3C(256'h003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00),
.INIT_3D(256'h003FFF00003FFF00003FFF00FFFFFF00FFFFFF00FFFFFF00FFFFFF00003FFF00),
.INIT_3E(256'h003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00),
.INIT_3F(256'h00000000000000000000000000000000000000000000000000000000003FFF00),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h1E00E1C00703810000FF07000000000000000000000000000000000000000000),
.INIT_48(256'h0703800F1E00E0331800603078007830780078F0780078C0780078C0180061C0),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000081FF000F),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized26
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h555555555555577FFFFFFC800000000000000000000000000000000000000000),
.INITP_01(256'hFFF7775555555555555555555DDDDDDDDDDDD557FDDDDDDD5555555555555555),
.INITP_02(256'hBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAAAAAEFFFFFFF00000000000000008CCEE),
.INITP_03(256'h00000000EFFFFFFBAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBAAAAAAAAAB),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'hFF00000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h00000000000000000000000000000044444444444444444444444444444444FF),
.INITP_07(256'h0000000333333333333333333333333333311110000000000000000000000000),
.INITP_08(256'h1190000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000191119911),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFCFFFF0000E000000000000000),
.INIT_06(256'hAA55AA5FAA55AA5FAA55AA7FAA55AAFFAA55AAFFAA55FFFFBFFFFFFFFFFFFFFF),
.INIT_07(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA57),
.INIT_08(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_09(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0A(256'hFFFFAA55FFFDAA55FFF5AA55FFD5AA55FF55AA55FE55AA55FA55AA55AA55AA55),
.INIT_0B(256'hFFF5AA55FFF5AA55FFF5AA55FFFDAA55FFFDAA557FFFAA557FFFAA557FFFAA55),
.INIT_0C(256'hAA55AA55FA55AA55FE55AA55FE55AA55FF55AA55FF55AA55FFD5AA55FFD5AA55),
.INIT_0D(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0E(256'hAA55AA7FAA55AA57AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0F(256'hFFFFFFF0FFFFFFFFFFFFFFFFBFFFFFFFABFFFFFFAA5FFFFFAA55FFFFAA55AFFF),
.INIT_10(256'h000000000000000000000000F8000000FFC00000FFFC0000FFFFE000FFFFFE00),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_14(256'hD5AA55AFD5AA55AFD5AA55AFD5AA55AAD5AA55AAD5AA55AAD5AA55AA55AA55AA),
.INIT_15(256'hD5AA55BFD5AA55BFD5AA55BFD5AA55BFD5AA55AFD5AA55AFD5AA55AFD5AA55AF),
.INIT_16(256'hD5AA55FFD5AA55FFD5AA55FFD5AA55FFD5AA55FFD5AA55BFD5AA55BFD5AA55BF),
.INIT_17(256'hF5AA55FFF5AA55FFF5AA55FFF5AA55FFF5AA55FFF5AA55FFF5AA55FFF5AA55FF),
.INIT_18(256'hF5AA55AAF5AA55AAF5AA55AAF5AA55AAF5AA55AAF5AA55AAF5AA55AAF5AA55FF),
.INIT_19(256'hF5AA55FFF5AA57FFF5AA57FFF5AA57FFF5AA57FFF5AA57FFF5AA55AAF5AA55AA),
.INIT_1A(256'hFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FF),
.INIT_1B(256'hFDAA55BFFDAA55BFFDAA55BFFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FF),
.INIT_1C(256'hFFAA55AFFDAA55AFFDAA55AFFDAA55AFFDAA55BFFDAA55BFFDAA55BFFDAA55BF),
.INIT_1D(256'hFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AAFFAA55AF),
.INIT_1E(256'hFFFFFE00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFABFFFF),
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.INIT_3C(256'h0003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF0),
.INIT_3D(256'h0003FFF00003FFF00003FFF00003FFFF0003FFFF0003FFFF0003FFFF0003FFF0),
.INIT_3E(256'h0003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF00003FFF0),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized27
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h55555555555555557FFFFFFEC000000000000000000000000000000000000000),
.INITP_01(256'hDD55555555555555555555557777FFFFCCCCC888888CDDDFF777777555555555),
.INITP_02(256'h1111111111119999999999999999999111111111111000000000044EEFFFFFFF),
.INITP_03(256'h0000000000000000000111111111111111111111111111111111111111111111),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h9900000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000008888CCCCCCCC8888000000000000CCCC99),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0040000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'hFF00000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hAA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800),
.INIT_06(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55ABFF),
.INIT_07(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_08(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_09(256'hFFFFFFFFFFFFFFFDBFFFFFF5ABFFFFD5AA7FFF55AA5FFE55AA55EA55AA55AA55),
.INIT_0A(256'hF8000000F8000003F800000FFF0000FFFFC001FFFFFC07FFFFFF1FFFFFFFFFFF),
.INIT_0B(256'hFFC0000FFFC0000FFFC00003FF000003FF000000FE000000FE000000FE000000),
.INIT_0C(256'hBFFFFA55BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFFF),
.INIT_0D(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0E(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0F(256'hEA55AFFFAA55AAFFAA55AA57AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_10(256'hFFFFFE00FFFFFFF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5FFFFFFA55FFFF),
.INIT_11(256'h00000000000000000000000000000000000000001F0000007FFC0000FFFFE000),
.INIT_12(256'h00001FFF00001FFF00001FFF0000000000000000000000000000000000000000),
.INIT_13(256'h00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_14(256'hF8001FFFF8001FFFFE001FFFFE001FFFFE001FFFFE001FFFE0001FFF00001FFF),
.INIT_15(256'h80001FFFE0001FFFE0001FFFE0001FFFE0001FFFE0001FFFF8001FFFF8001FFF),
.INIT_16(256'h000007FF000007FF000007FF000007FF800007FF800007FF800007FF80001FFF),
.INIT_17(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_18(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_19(256'h000001FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_1A(256'h000001FF000001FF000001FF000001FF000001FF000001FF000001FF000001FF),
.INIT_1B(256'h000001FF000001FF000001FF000001FF000001FF000001FF000001FF000001FF),
.INIT_1C(256'h000001FF000001FF000001FF000001FF000001FF000001FF000001FF000001FF),
.INIT_1D(256'h000000FF000000FF000000FF000001FF000001FF000001FF000001FF000001FF),
.INIT_1E(256'h000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF),
.INIT_1F(256'h00000000000000000000000000000000000000000000000000000000000000FF),
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.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2F(256'h80001FFF80001FFF000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000FF000000FF000000FF000000FF00000080001FFF80001FFF),
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.INIT_33(256'h8000000080000000FF000000FF000000FF000000FF000000FF000000FF000000),
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.INIT_47(256'h00F0003006F0003001F0003F0000000000000000000000000000000000000000),
.INIT_48(256'h00F01EC000F0000000F0000000F0000000F0000000F000FF00F0003000F00030),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000F01EFF),
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.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized28
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h555DDDDDDDFFF777733331110000000000000000000000000000000000000000),
.INITP_01(256'h1333337777FFDDDDDDDDDD555555555555555555555555555555555555555555),
.INITP_02(256'hBBBBBBBBBBBBBBBBBBBBBBBBBBBFFFFFFECC8800000000000000000000000111),
.INITP_03(256'h0000000888888CCCCCCCCCCCCCCCCCCCCCCEEEEEEEEEEEEEEEEEEEBBBBBBBBBB),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h7700000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000007777CCCC0000111133336666CCCCCCCC77),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h9910000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000199113311),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000003F00000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h01FFFFFD003FFFFF000FFFFF0003FFFF0000FFFF00001FFF000007FF000001FF),
.INIT_06(256'hFFF5AA55FFFFAA55FFFFAA55FFFFEA55FFFFFA557FFFFE551FFFFFD507FFFFF5),
.INIT_07(256'hAA55AA55AA55AA55AA55AA55AA55AA55FA55AA55FE55AA55FF55AA55FFD5AA55),
.INIT_08(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_09(256'hAA55AA57AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0A(256'hAA55AAFFAA55ABFFAA55ABFFAA55AFFFAA55AFFFAA55AFFFAA55AAFFAA55AA7F),
.INIT_0B(256'hAA55AA57AA55AA5FAA55AA5FAA55AA5FAA55AA7FAA55AA7FAA55AAFFAA55AAFF),
.INIT_0C(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA57),
.INIT_0D(256'hFF55AA55FE55AA55FA55AA55EA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0E(256'h1FFFFE557FFFFA55FFFFEA55FFFFAA55FFFFAA55FFFDAA55FFF5AA55FFD5AA55),
.INIT_0F(256'h00007FFF0000FFFF0003FFFF000FFFFD003FFFF500FFFFF501FFFFD507FFFF55),
.INIT_10(256'h000000030000000F0000003F0000003F000000FF000001FF000007FF00001FFF),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'hFFFFFF00FFFFF800FFFF0000FFC00000FE000000800000000000000000000000),
.INIT_14(256'h55AA5FFF55AAFFFF55AFFFFFD5FFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC),
.INIT_15(256'h55AA7FFF55AA7FFF55AA5FFF55AA5FFF55AA5FFF55AA5FFF55AA57FF55AA57FF),
.INIT_16(256'h55AAFFFF55AAFFFF55AAFFFF55AAFFFF55AAFFFF55AA7FFF55AA7FFF55AA7FFF),
.INIT_17(256'h55AFFFF055AFFFF055AFFFF055AFFFFC55ABFFFC55ABFFFC55ABFFFC55ABFFFC),
.INIT_18(256'h55FFFF0055FFFF0055BFFFC055BFFFC055BFFFC055BFFFC055BFFFC055AFFFF0),
.INIT_19(256'h57FFF80055FFFE0055FFFE0055FFFE0055FFFE0055FFFE0055FFFF0055FFFF00),
.INIT_1A(256'h5FFFE0005FFFE0005FFFE0005FFFE00057FFE00057FFF80057FFF80057FFF800),
.INIT_1B(256'hFFFF0000FFFF0000FFFF00007FFF80007FFF80007FFF80007FFF80007FFF8000),
.INIT_1C(256'hFFF00000FFF00000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFF0000),
.INIT_1D(256'hFF000000FFC00000FFC00000FFC00000FFC00000FFC00000FFF00000FFF00000),
.INIT_1E(256'hFE000000FE000000FE000000FE000000FE000000FF000000FF000000FF000000),
.INIT_1F(256'h00000000000000000000000000000000000000000000000000000000F8000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h07FFFFFF07FFFFFF000000000000000000000000000000000000000000000000),
.INIT_30(256'hFFF00000FFF00000FFF0003FFFF0003FFFF0003FFFF0003F07FFFFFF07FFFFFF),
.INIT_31(256'h000FFFC0000FFFC007FFE00007FFE00007FFE00007FFE000FFF00000FFF00000),
.INIT_32(256'h0000003F0000003F00001FFF00001FFF00001FFF00001FFF000FFFC0000FFFC0),
.INIT_33(256'h07FFFFFF07FFFFFFFFF0003FFFF0003FFFF0003FFFF0003F0000003F0000003F),
.INIT_34(256'h00000000000000000000000000000000000000000000000007FFFFFF07FFFFFF),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'hE0FC070080FC070000F007000000000000000000000000000000000000000000),
.INIT_48(256'h80F01F00E0F01F0060F0670078F0670078F0E70078F0870078F3070060F30700),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000F00700),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized29
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h3333331111000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0088000000000000111133333333333333333333333333333333333333333333),
.INITP_02(256'h2233333333333333333333111111111111111111000000000000000000000000),
.INITP_03(256'h000000077777FEEEEEEEAAAAAAAAAAAAAAAAAAAEEEEEEEEEEEEEEEEEE6222222),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h3300000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000003333333333337777FFFFBBBB3333333333),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h8D40000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000954444088),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h000007FF000001FF0000003F0000000F00000003000000000000000000000000),
.INIT_07(256'h0003FFF50003FFFD0003FFFF0003FFFF0003FFFF0003FFFF00007FFF00001FFF),
.INIT_08(256'h0003FFF50003FFF50003FFF50003FFF50003FFF50003FFF50003FFF50003FFF5),
.INIT_09(256'h000FFFF5000FFFF5000FFFF50003FFF50003FFF50003FFF50003FFF50003FFF5),
.INIT_0A(256'h000FFFF5000FFFF5000FFFF5000FFFF5000FFFF5000FFFF5000FFFF5000FFFF5),
.INIT_0B(256'h000FFFD5000FFFD5000FFFF5000FFFF5000FFFF5000FFFF5000FFFF5000FFFF5),
.INIT_0C(256'h003FFFF5003FFFD5003FFFD5003FFFD5003FFFD5003FFFD5000FFFD5000FFFD5),
.INIT_0D(256'h000001FF000007FF00001FFF00007FFF0000FFFF0003FFFF000FFFFF003FFFFD),
.INIT_0E(256'h000000000000000000000000000000030000000F0000000F0000003F000000FF),
.INIT_0F(256'h0000000000000000800000008000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h00001FFF000007FF000007FF000007FF000007FF000007FF000007F000000100),
.INIT_14(256'h00007FFF00007FFF00007FFF00001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_15(256'h0000FFFA0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE00007FFF00007FFF),
.INIT_16(256'h000FFFEA000FFFEA000FFFEA0003FFEA0003FFFA0003FFFA0003FFFA0003FFFA),
.INIT_17(256'h003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA000FFFAA000FFFAA000FFFEA),
.INIT_18(256'h81FFFDAA01FFFDAA00FFFDAA00FFFDAA00FFFDAA00FFFFAA00FFFFAA003FFFAA),
.INIT_19(256'hFFFFD5AAFFFFD5AAFFFFD5AAFFFFF5AAF9FFF5AAF9FFF5AAE1FFF5AA81FFF5AA),
.INIT_1A(256'h57FE55AA5FFF55AA5FFF55AA7FFF55AAFFFF55AAFFFF55AAFFFFD5AAFFFFD5AA),
.INIT_1B(256'h55AA55AA55AA55AA55AA55AA55AA55AA55BE55AA55FE55AA55FE55AA55FE55AA),
.INIT_1C(256'hF5AA55AFF5AA55AFD5AA55ABD5AA55AB55AA55AB55AA55AB55AA55AB55AA55AA),
.INIT_1D(256'hFFFA55FFFFEA55BFFFAA55BFFFAA55BFFFAA55BFFFAA55AFFDAA55AFFDAA55AF),
.INIT_1E(256'h1FFFFFFF1FFFFFFF7FFFFFFF7FFFFFFFFFFFFFFFFFFE55FFFFFE55FFFFFA55FF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000007FFFFFF),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h000FFFC0000FFFC0000000000000000000000000000000000000000000000000),
.INIT_30(256'h000FFFC3000FFFC3000FFFC3000FFFC3000FFFC3000FFFC3000FFFC0000FFFC0),
.INIT_31(256'hFFFFFFC0FFFFFFC0F80FFFC0F80FFFC0F80FFFC0F80FFFC0000FFFC3000FFFC3),
.INIT_32(256'h000FFFC0000FFFC007FFFFC007FFFFC007FFFFC007FFFFC0FFFFFFC0FFFFFFC0),
.INIT_33(256'h000FFFC0000FFFC0000FFFC3000FFFC3000FFFC3000FFFC3000FFFC0000FFFC0),
.INIT_34(256'h000000000000000000000000000000000000000000000000000FFFC0000FFFC0),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h800F1E00E10F07037F0F00FF0000000000000000000000000000000000000000),
.INIT_48(256'h070F070301CF1E0001CF180001CF78001F0F7800780F7800E00F7800800F1800),
.INIT_49(256'h00000000000000000000000000000000000000000000000000000000FE0F01FF),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized3
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized30
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h6666667EECCCC888000000000000000000000000000000000000000000000000),
.INITP_01(256'h7775777776666CCCCC88880000000000008CCCCCCC6666666666666666666666),
.INITP_02(256'h2200000000000000000000000000000000000000000000000000000888CCC667),
.INITP_03(256'h000000000000000088888DDDDDDFFFFFBBBBBAAAAAAAAAAAEEEFFF7777733333),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h2200000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000002222222222222222222233333333222222),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h99E0000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000D9999AD99),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'hFFFFE000FFFF0000FFFC0000FFF00000FF000000FE000000E000000080000000),
.INIT_07(256'hAAFFFE00AAFFFE00AAFFFE00AAFFFE00ABFFFE00BFFFFE00FFFFFF00FFFFF800),
.INIT_08(256'hABFFF800ABFFF800ABFFF800ABFFF800ABFFF800ABFFF800AAFFF800AAFFFE00),
.INIT_09(256'hBFFF8000AFFFE000AFFFE000AFFFE000AFFFE000AFFFE000AFFFE000AFFFE000),
.INIT_0A(256'hFFFF0000FFFF0000FFFF8000BFFF8000BFFF8000BFFF8000BFFF8000BFFF8000),
.INIT_0B(256'h0000000000000000E0000000FF000000FFFC0000FFFF0000FFFF0000FFFF0000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'hFFC00000FF000000FE000000F8000000E0000000800000000000000000000000),
.INIT_0E(256'hAAFFFF00ABFFFE00AFFFF800BFFFE000FFFF8000FFFF0000FFFC0000FFF00000),
.INIT_0F(256'hAAFFFFF0AA5FFFFCAA57FFFFAA55FFFFAA55FFFFAA57FFFCAA5FFFF0AA7FFFC0),
.INIT_10(256'hF8000000FE000000FFC00000FFF00000FFFF0000FFFFE000BFFFF800ABFFFF00),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000080000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000FE000000F800000078000000000000000000000000000000000000000000),
.INIT_18(256'h1FFFFFFF07FFFFFF01FFFFFC00FFFFF0003FFFF0003FFFC0000FFF000003FF00),
.INIT_19(256'hFFAA55BFFFEA55BFFFEA55FFFFFA55FFFFFE55FFFFFF57FF7FFF5FFF1FFFDFFF),
.INIT_1A(256'h55AA55AA55AA55AA55AA55AAD5AA55AAF5AA55AAFDAA55AAFDAA55ABFFAA55AF),
.INIT_1B(256'h55FFFFFA55BFFFEA55AFFFEA55ABFFAA55AAFFAA55AA7FAA55AA5FAA55AA55AA),
.INIT_1C(256'hFFFC07FFFFFF1FFFFFFF1FFFFFFFFFFF7FFFFFFF5FFFFFFE57FFFFFE55FFFFFA),
.INIT_1D(256'h8000000FE000003FF800003FFE0000FFFE0000FFFF0001FFFFC001FFFFF007FF),
.INIT_1E(256'h000000000000000000000000000000000000000000000000000000030000000F),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h00FFFE0000FFFE00000000000000000000000000000000000000000000000000),
.INIT_30(256'h00FFFFFC00FFFFFC00FFFE0000FFFE0000FFFE0000FFFE0000FFFE0000FFFE00),
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.INIT_47(256'h800F01C3800F0700FFCFFE000000000000000000000000000000000000000000),
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.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized31
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h5555555555557777FFFEEECCC000000000000000000000000000000000000000),
.INITP_01(256'h77775DDDDDDDDDD5555555777776666EEF7777555555555DDDDDDDDDDDDD5555),
.INITP_02(256'hCCCCCCCCCCCCCCCCCC8888888888888888888800000000000000111113333337),
.INITP_03(256'h0000000EEEFFFBBBBBBBBBAAAAAAAAAAAAAABBBBBFFFFFFFEEEEEEEECCCCCCCC),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'hEE00000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h000000000000000000000000000000EEEE4444444444444444444444444444EE),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h1000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000002223111),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'hFFC0000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFFFFFFFFFF0FFFFFFC0FFFFFE00FFFFF800FFFFE000FFFF0000FFFC0000),
.INIT_06(256'hAA55AA7FAA55AAFFAA55AFFFAA55BFFFAA55FFFFAA57FFFFAA7FFFFFAAFFFFFF),
.INIT_07(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA57),
.INIT_08(256'hFF55AA55FE55AA55FA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_09(256'hEA55AA55FA55AA55FE55AA55FF55AA55FFD5AA55FFF5AA55FFF5AA55FFD5AA55),
.INIT_0A(256'hAA55AA5FAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0B(256'hFFFFFE00FFFFFFF0FFFFFFFFABFFFFFFAA7FFFFFAA55FFFFAA55BFFFAA55ABFF),
.INIT_0C(256'hAA5FFFF0AA7FFFC0AAFFFF00ABFFFE00AFFFF800BFFFE000FFFF8000FFFF8000),
.INIT_0D(256'hAA55AA7FAA55AAFFAA55ABFFAA55AFFFAA55BFFFAA55FFFFAA55FFFFAA57FFFC),
.INIT_0E(256'hFFD5AA55FF55AA55FE55AA55FA55AA55EA55AA55EA55AA55AA55AA57AA55AA5F),
.INIT_0F(256'h01FFFA5507FFEA551FFFEA557FFFAA557FFFAA55FFFDAA55FFF5AA55FFF5AA55),
.INIT_10(256'h00007FFF0000FFFF0003FFFF000FFFFF000FFFF7003FFFD500FFFF5501FFFE55),
.INIT_11(256'h0000000000000000000000000000000000000100000007F000001FFC00001FFF),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'hE000000080000000800000008000000080000000800000000000000000000000),
.INIT_14(256'hF8000000F8000000F8000000F8000000E0000000E0000000E0000000E0000000),
.INIT_15(256'hFF000000FF000000FE000000FE000000FE000000FE000000FE000000F8000000),
.INIT_16(256'hFFC00000FFC00000FFC00000FFC00000FF000000FF000000FF000000FF000000),
.INIT_17(256'hFFFC0000FFFC0000FFF00000FFF00000FFF00000FFF00000FFF00000FFC00000),
.INIT_18(256'h7FFF00007FFF00007FFF0000FFFF0000FFFF0000FFFC0000FFFC0000FFFC0000),
.INIT_19(256'h57FFE0FF57FFE03F5FFFE00F5FFF80035FFF80035FFF80005FFF80007FFF8000),
.INIT_1A(256'h55FFFFFE55FFFFFE55FFFFFF55FFFFFF55FFFFFF57FFFFFF57FFE1FF57FFE1FF),
.INIT_1B(256'h55BFF5AA55BFF5AA55BFFDAA55BFFFAA55FFFFAA55FFFFAA55FFFFEA55FFFFFA),
.INIT_1C(256'h55AA55AF55AA55AB55AA55AA55AA55AA55AA55AA55AE55AA55AF55AA55AFD5AA),
.INIT_1D(256'h55ABFFFF55AAFFFF55AA7FFF55AA5FFF55AA57FF55AA55FF55AA55FF55AA55BF),
.INIT_1E(256'hFFFFFE00FFFFFE00FFFFFF00FFFFFFC0FFFFFFF0FFBFFFFC55AFFFFC55AFFFFF),
.INIT_1F(256'h00000000000000000000000000000000000000000000000000000000FFFFF800),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'hFFFFFE00FFFFFE00000000000000000000000000000000000000000000000000),
.INIT_30(256'h7FFF00007FFF00007FFF00007FFF00007FFF00007FFF0000FFFFFE00FFFFFE00),
.INIT_31(256'h7FFF00007FFF00007FFF00007FFF00007FFF00007FFF00007FFF00007FFF0000),
.INIT_32(256'h7FFF00007FFF00007FFF00007FFF00007FFF00007FFF00007FFF00007FFF0000),
.INIT_33(256'hFFFFFE00FFFFFE007FFF00007FFF00007FFF00007FFF00007FFF00007FFF0000),
.INIT_34(256'h000000000000000000000000000000000000000000000000FFFFFE00FFFFFE00),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h000F01C3000C00C3003C00F30000000000000000000000000000000000000000),
.INIT_48(256'h0000780300009E030000860300008603000387030003070300030103000F01C3),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000007803),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized32
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h7777555555555555FFFFFFFF3000000000000000000000000000000000000000),
.INITP_01(256'h44444444444555555777777777555555555555555777FFFFDDCCCCCCC5555777),
.INITP_02(256'hEEEEEEEEEEAAAAAAAABBBBBBBBBBBBBBBFFFFFF733100000000000CCCCCCCC44),
.INITP_03(256'h000000033333333333322226666666666666666666666666EEEEEEEEEEEEEEEE),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0003FFFF00000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hBE55AA55BA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_07(256'hFFFFFE55FFFFFA55FFFFEA55FFFFAA55BFFFAA55BFFDAA55BFD5AA55BF55AA55),
.INIT_08(256'hFFF000FFFFF001FFFFF007FFFFF01FFFFFF07FFFFFF3FFFDFFFFFFF5FFFFFFD5),
.INIT_09(256'hFFFC07FFFFF001FFFFF000FFFFF0003FFFF0000FFFF00003FFF00003FFF0003F),
.INIT_0A(256'hAA55AA55AA55FE55AA7FFF55AFFFFFD5FFFFFFF5FFFFFFFDFFFFFFFFFFFFFFFF),
.INIT_0B(256'hAE55AA57AA55AA57AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0C(256'hBFFFEA55BFFFAA55BFFFAA55BFFDAA55AFF5AA55AFF5AA55AFD5AA55AF55AA55),
.INIT_0D(256'hBFF07FFDBFF0FFF5BFF3FFF5BFFFFFD5BFFFFF55BFFFFE55BFFFFA55BFFFEA55),
.INIT_0E(256'hFFF0000FFFF0003FFFF000FFFFF001FFFFF001FFBFF007FFBFF01FFFBFF07FFF),
.INIT_0F(256'hFFC00000FFF00000FFF00000FFF00000FFF00000FFF00000FFF00003FFF0000F),
.INIT_10(256'hFFC00000FFC00000FFC00000FFC00000FFC00000FFC00000FFC00000FFC00000),
.INIT_11(256'h000000000000000000000000000000000000000000000000FFC00000FFC00000),
.INIT_12(256'h00FFFFFF0000FFFF000007FF0000003C00000000000000000000000000000000),
.INIT_13(256'hFDAA7FFFFFAA7FFFFFFA7FFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFF1FFFFFFF),
.INIT_14(256'hF5AA57FFF5AA57FFF5AA57FFF5AA5FFFD5AA5FFFD5AA5FFFD5AA5FFFD5AA5FFF),
.INIT_15(256'hFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FFFDAA55FFF5AA55FFF5AA57FF),
.INIT_16(256'hFFAA55AFFFAA55BFFFAA55BFFFAA55BFFFAA55BFFFAA55BFFFAA55FFFFAA55FF),
.INIT_17(256'hFFEA55ABFFEA55ABFFEA55ABFFEA55ABFFAA55AFFFAA55AFFFAA55AFFFAA55AF),
.INIT_18(256'hFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFFA55AAFFEA55AAFFEA55AAFFEA55AA),
.INIT_19(256'hFFFF55AAFFFE55AAFFFE55AAFFFE55AAFFFE55AAFFFE55AAFFFE55AAFFFA55AA),
.INIT_1A(256'h1FFFD5AA1FFFD5AA7FFFD5AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA7FFF55AA),
.INIT_1B(256'h07FFF5AA07FFF5AA07FFF5AA1FFFF5AA1FFFF5AA1FFFD5AA1FFFD5AA1FFFD5AA),
.INIT_1C(256'h01FFFFAA01FFFDAA01FFFDAA01FFFDAA01FFFDAA07FFFDAA07FFFDAA07FFF5AA),
.INIT_1D(256'h003FFFAA00FFFFAA00FFFFAA00FFFFAA00FFFFAA00FFFFAA00FFFFAA01FFFFAA),
.INIT_1E(256'h000FFFFF000FFFFF000FFFFF003FFFFF003FFFFF003FFFFF003FFFAA003FFFAA),
.INIT_1F(256'h00000000000000000000000000000000000000000000000000000000000FFFFF),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000003F0000003F000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000003F0000003F),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000003F0000003F000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000003F0000003F),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized33
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'hDDDDDDDDDDDDDDDDFFFFFFFF0000000000000000000000000000000000000000),
.INITP_01(256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD),
.INITP_02(256'h0000000000000009999DDDD9999911111111110000000000000000FFFFF55DDD),
.INITP_03(256'h0000000000000000000000000000000000000000008888000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFA55AA55FA55AA55FA55AA55FA55AA55FA55AA55FA55AA55FA55AA55FA55AA55),
.INIT_07(256'hFA55AA55FA55AA55FA55AA55FA55AA55FA55AA55FA55AA55FA55AA55FA55AA55),
.INIT_08(256'hEA55AA55EA55AA55EA55AA55FA55AA55FA55AA55FA55AA55FA55AA55FA55AA55),
.INIT_09(256'hEA55AA55EA55AA55EA55AA55EA55AA55EA55AA55EA55AA55EA55AA55EA55AA55),
.INIT_0A(256'hEA55AA55EA55AA55EA55AA55EA55AA55EA55AA55EA55AA57EA55AA55EA55AA55),
.INIT_0B(256'hEA55AA55EA55AA55EA55AA55EA55AA55EA55AA55EA55AA55EA55AA55EA55AA55),
.INIT_0C(256'hAA55AA55AA55AA55AA55AA55AA55AA55EA55AA55EA55AA55EA55AA55EA55AA55),
.INIT_0D(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0E(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_0F(256'hAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_10(256'hFFFFFFFFFFFFFFFFFFFFFFFFAA55AA55AA55AA55AA55AA55AA55AA55AA55AA55),
.INIT_11(256'h000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h00001FFF00001FFF00007FFF00007FFF00007FFF000001FF0000000F00000000),
.INIT_14(256'hF80007FFF80007FFE00007FF80001FFF00001FFF00001FFF00001FFF00001FFF),
.INIT_15(256'hE00001FFF80001FFFE0001FFFF0001FFFFC001FFFFC007FFFF0007FFFE0007FF),
.INIT_16(256'h0000003F000000FF000000FF000000FF000000FF000000FF000000FF800001FF),
.INIT_17(256'h0000000F0000000F0000000F0000003F0000003F0000003F0000003F0000003F),
.INIT_18(256'h000000030000000300000003000000030000000F0000000F0000000F0000000F),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000300000003),
.INIT_1A(256'h00000000000000008000000080000000E0000000800000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized34
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h1111111100000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h1111111111111111111111111111111111111111111111111111111111111111),
.INITP_02(256'h000444EEEEFFBBBBBBBBAAABBBBBBBBBBBEEEEECCCCC00000000001111111111),
.INITP_03(256'h0000000000000000008CEEEEEEEAABBBBBBBBBBBBBBBBBFFFEECCC8800000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h000000FF000000FF000000FF000000FF000000FF000000FF000000FF0000000F),
.INIT_06(256'h000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF),
.INIT_07(256'h000001FF000001FF000001FF000001FF000001FF000001FF000001FF000001FF),
.INIT_08(256'h000001FF000001FF000001FF000001FF000001FF000001FF000001FF000001FF),
.INIT_09(256'h000001FF000001FF000001FF000001FF000001FF000001FF000001FF000001FF),
.INIT_0A(256'h000001FF000001FF000001FF000001FF000001FF000001FF000001FF000001FF),
.INIT_0B(256'h000001FF000001FF000001FF000001FF000001FF000001FF000001FF000001FF),
.INIT_0C(256'h000007FF000007FF000007FF000007FF000007FF000007FF000001FF000001FF),
.INIT_0D(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_0E(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_0F(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_10(256'h000007FF000007FF000007FF000007FF000007FF000007FF000007FF000007FF),
.INIT_11(256'h000000000000000000000000000000000000000000000000000007FF000007FF),
.INIT_12(256'hFFFC0000FFF00000FFF00000FFC0000000000000000000000000000000000000),
.INIT_13(256'h55BFFFC055FFFF0055FFFE0057FFF80057FFE000FFFFE000FFFF8000FFFF0000),
.INIT_14(256'h55AA57FF55AA5FFF55AA7FFF55AA7FFF55AAFFFF55ABFFFC55AFFFF055AFFFF0),
.INIT_15(256'h55AA5FFF55AA57FF55AA57FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_16(256'hFFFFF800FFFFFE00FFFFFF00FFBFFFC0FFAFFFF0F5ABFFFCD5AAFFFF55AA7FFF),
.INIT_17(256'h000000000000000000C0000001F0000007FC00007FFF0000FFFF8000FFFFE000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'hFFFFFF00FFFFF800FFFF8000FFFF0000FFF00000FF000000FE000000E0000000),
.INIT_1A(256'h55AA7FFF55AA7FFF55AA7FFF55ABFFFF55BFFFFF55FFFFFF57FFFFFC7FFFFFC0),
.INIT_1B(256'h55AFFFC055AFFFC055AFFFF055ABFFF055ABFFF055AAFFFC55AAFFFC55AAFFFF),
.INIT_1C(256'h7FFFF80055FFF80055FFF80055FFFE0055FFFE0055FFFF0055BFFF0055BFFF00),
.INIT_1D(256'h0000000000000000F8000000FFF00000FFFF8000FFFF8000FFFFE000FFFFE000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized35
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'hC8800000001113BBBFEEEEEEAAAAAAAAAAAAAFFFFFFF00000000000000000000),
.INITP_03(256'h0000000000008CCEFFFFBBBAAAAAAAAAAAAAAEEAAAAAAAAAAAABBBBBFFFEEECC),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA7FFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFAA55AAFDAA55AAD5AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'hE0FFFFFAFFFFFFAAFFFFFFAAFFFFF5AAFFFFD5AAFFFE55AAFFFA55AAFFEA55AA),
.INIT_16(256'h0000003F000000FF000001FF00001FFF00007FFF0000FFFF800FFFFF803FFFFE),
.INIT_17(256'hFF000000F8000000800000000000000000000000000000000000000000000003),
.INIT_18(256'h55FFFFFF57FFFFF07FFFFFC0FFFFFE00FFFFE000FFFF8000FFFC0000FFC00000),
.INIT_19(256'h55AA55AA55AA55AF55AA55FF55AA55FF55AA5FFF55AAFFFF55ABFFFF55BFFFFF),
.INIT_1A(256'hFDAA55AAF5AA55AAD5AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_1B(256'h55AA55AA55AA55AA55AA55AAD5AA55AAFDAA55AAFFAA55AAFFAA55AAFFAA55AA),
.INIT_1C(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_1D(256'hFFFFFFC0FFFFFFFFFFFFFFFF57FFFFFF55BFFFFF55AAFFFF55AA57FF55AA55BF),
.INIT_1E(256'h00000000000000000000000000000000E0000000FF000000FFFF0000FFFFF800),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized36
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'hBBBFFFABBBBBBBBBBBBBAAAAAAAAAAAEEEEEEEF7777700000000000000000000),
.INITP_03(256'h000000004EFFFFBBBAAAAAAAAAAAAEEEE7733311133333766EEEEEAAAAAAAABB),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h7FFFFFFF1FFFFFFF1FFFFFFF07FFFFFF00000000000000000000000000000000),
.INIT_13(256'hFFAA55AAFFEA55AAFFEA55AAFFFA55AAFFFE55AAFFFE55AAFFFFFFFF7FFFFFFF),
.INIT_14(256'h55AA55AFD5AA55ABF5AA55AAF5AA55AAFDAA55AAFDAA55AAFFAA55AAFFAA55AA),
.INIT_15(256'h55AA5FFF55AA57FF55AA55FF55AA55FF55AA55FF55AA55BF55AA55BF55AA55AF),
.INIT_16(256'h55BFFFC055AFFFC055ABFFF055ABFFFC55AAFFFC55AA7FFF55AA7FFF55AA5FFF),
.INIT_17(256'h55AAFFFF55AFFFFF55BFFFFF55FFFFFF55FFFFF055FFFF0055FFFE0055BFFF00),
.INIT_18(256'hF5AA55AAD5AA55AA55AA55AA55AA55AB55AA55AF55AA55FF55AA57FF55AA5FFF),
.INIT_19(256'h7FFFF5AAFFFFD5AAFFFF55AAFFFE55AAFFFA55AAFFAA55AAFFAA55AAFDAA55AA),
.INIT_1A(256'h00007FFF0000FFFF0003FFFF000FFFFE003FFFFA00FFFFEA07FFFFAA1FFFFFAA),
.INIT_1B(256'hFFFFFDAA7FFFFFAA07FFFFFE00FFFFFF000FFFFF0000FFFF00001FFF000007FF),
.INIT_1C(256'h55AA55AA55AA55AA55AA55AAF5AA55AAFFAA55AAFFEA55AAFFFE55AAFFFFD5AA),
.INIT_1D(256'h55AA5FFF55AA55FF55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_1E(256'h7FF00000FFFF8000FFFFFF00FFFFFFFCFFFFFFFFFFFFFFFFFDFFFFFFF5ABFFFF),
.INIT_1F(256'h000000000000000000000000000000000000000000000000000000001E000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized37
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'hEEEEEEEE66666662333333331111111000000000000000000000000000000000),
.INITP_03(256'h000000000000111333776EEE7733311000000000000000000000011133333766),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000003F0000003F0000000F0000000F00000003000000030000000000000000),
.INIT_14(256'h00007FFF00001FFF00001FFF000007FF000007FF000001FF000001FF000000FF),
.INIT_15(256'h00FFFFAA003FFFAA000FFFEA000FFFEA0003FFFA0003FFFE0000FFFE0000FFFF),
.INIT_16(256'h7FFF55AA1FFF55AA1FFFD5AA07FFF5AA07FFF5AA01FFFDAA01FFFDAA00FFFFAA),
.INIT_17(256'hFFFFD5AAFFFF55AAFFFE55AAFFEA55AAFFEA55AAFFFA55AAFFFE55AAFFFE55AA),
.INIT_18(256'h0000FFFF0003FFFF000FFFFE003FFFFA00FFFFEA01FFFFAA1FFFFDAA7FFFF5AA),
.INIT_19(256'h0000000000000000000000030000003F000000FF000001FF000007FF00001FFF),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000300000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h7FFFFFAA07FFFFFA00FFFFFF000FFFFF0000FFFF00001FFF000001FF0000003F),
.INIT_1D(256'h000FFFFF003FFFFE01FFFFEA07FFFFAA7FFFFDAAFFFFF5AAFFFFD5AAFFFFFDAA),
.INIT_1E(256'h00000000000000030000000F000000FF000001FF00001FFF00007FFF0003FFFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized38
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h00000000000000030000000F0000000F00000003000000030000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000F00000003),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized39
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized4
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized40
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized41
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized42
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized43
(douta,
clka,
addra);
output [33:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [33:0]douta;
wire \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[33:26],douta[24:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[25],\n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized5
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h8888CCCCCCCCCCCCCCCCCCCCCCCC888000000000000000000000000000000000),
.INITP_03(256'h0000000000000088CCCEEEEEEECCCCC888800000000000000000000888888888),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_16(256'hFF000000FF000000FF000000FFC00000FFC00000FFC00000FFC00000FFC00000),
.INIT_17(256'hFE000000FE000000FE000000FE000000FF000000FF000000FF000000FF000000),
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.INIT_19(256'h00000000000000000000000000000000000000000000000000000000E0000000),
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.INIT_1B(256'hF8000000E0000000800000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized6
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'hAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBFFFEEECCCC88000000000000000000000),
.INITP_03(256'h0000000022277777FEEEEEAAAAAAAAABBBBBBBBBEEEECCCCC88CEFFFFBBBBBAA),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'hFF000000F8000000E00000000000000000000000000000000000000000000000),
.INIT_13(256'h5FFFFFF0FFFFFF00FFFFFE00FFFFF800FFFF8000FFFF0000FFF00000FFC00000),
.INIT_14(256'h55AA55FF55AA55FF55AA5FFF55AAFFFF55ABFFFF55BFFFFF55FFFFFF57FFFFFC),
.INIT_15(256'h55AA55AF55AA55AB55AA55AB55AA55AB55AA55AB55AA55AB55AA55AB55AA55AF),
.INIT_16(256'hD5AA55BFD5AA55BF55AA55BF55AA55AF55AA55AF55AA55AF55AA55AF55AA55AF),
.INIT_17(256'h55AA55FF55AA55FF55AA55FF55AA55FF55AA55BF55AA55BF55AA55BF55AA55BF),
.INIT_18(256'h57FFFFFF55FFFFFF55AFFFFF55AA7FFF55AA57FF55AA55FF55AA55FF55AA55FF),
.INIT_19(256'hFF000000FE000000FE000000FFF00000FFFF8000FFFFFF00FFFFFFFCFFFFFFFF),
.INIT_1A(256'h55FFFE0057FFF8005FFFE0007FFF8000FFFF0000FFFC0000FFF00000FFC00000),
.INIT_1B(256'h55AA57FF55AA5FFF55AA7FFF55AAFFFF55ABFFFC55AFFFF055BFFFC055FFFF00),
.INIT_1C(256'hF5AA55AAD5AA55AAD5AA55AA55AA55AB55AA55AF55AA55BF55AA55FF55AA55FF),
.INIT_1D(256'hFFFF55FFFFFE55FFFFFA55AFFFEA55ABFFAA55AAFFAA55AAFFAA55AAFDAA55AA),
.INIT_1E(256'h003F800000FFE00000FFFE0001FFFFC007FFFFF01FFFFFFF7FFFFFFF7FFFDFFF),
.INIT_1F(256'h00000000000000000000000000000000000000000000000000000000000C0000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized7
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'hEEEBBBB999BBBBAEEEEEEEAAAAAAAAAAAAAFFFFFFFF700000000000000000000),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF1FFFFFFF00000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55ABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hF5AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'h9FFFF5AAFFFFD5AAFFFF55AAFFFA55AAFFEA55AAFFAA55AAFFAA55AAFDAA55AA),
.INIT_16(256'h80001FFF80001FFF8000FFFF8003FFFE800FFFFA803FFFEA80FFFFAA81FFFDAA),
.INIT_17(256'hFFFFF5AAFFFFFDAAFFFFFFAAE03FFFAA800FFFEA8003FFFA8000FFFE80007FFF),
.INIT_18(256'h55AA55AA55AA55AA55AA55AA55AA55AA57FA55AAFFFE55AAFFFF55AAFFFFD5AA),
.INIT_19(256'hD5AA55FF55AA55FF55AA57FF55AA5FFF55AA5FFF55AA55FF55AA55AF55AA55AA),
.INIT_1A(256'hFFFA55AAFFEA55AAFFAA55AAFFAA55AAFFAA55AAFDAA55ABF5AA55AFD5AA55BF),
.INIT_1B(256'h803FFFAA80FFFFAA81FFFDAA81FFF5AA87FFD5AA9FFFD5AAFFFF55AAFFFE55AA),
.INIT_1C(256'h800007FF80001FFF80007FFF80007FFF8000FFFE8003FFFA800FFFEA800FFFAA),
.INIT_1D(256'h00000000000000030000000F0000000F8000003F800000FF800001FF800001FF),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized8
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'hBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAFFFFFFFF000000000000000000000),
.INITP_03(256'h000000000FFFFFBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAB),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000000),
.INIT_13(256'h55AA55AA55AA55AA55AA55AAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'h55AA55FF55AA55FF55AA55FE55AA55FA55AA55EA55AA55AA55AA55AA55AA55AA),
.INIT_15(256'h55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_16(256'h55AA57FF55AA57FF55AA57FF55AA57FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_17(256'h55AA5FFF55AA57FF55AA57FF55AA57FF55AA57FF55AA57FF55AA57FF55AA57FF),
.INIT_18(256'h55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55AA55BF55AA57FF),
.INIT_19(256'h55AA55BF55AA55BF55AA55BE55AA55BA55AA55AA55AA55AA55AA55AA55AA55AA),
.INIT_1A(256'h55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55BF),
.INIT_1B(256'h55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_1C(256'h55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_1D(256'h55AA57FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF55AA55FF),
.INIT_1E(256'h00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF55AA57FF55AA57FF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
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.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Initial_blk_mem_gen_prim_wrapper_init__parameterized9
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h77777777777777FFFFFFEC000000000000000000000000000000000000000000),
.INITP_01(256'h6666666666666666666666666666666666666666666777777777777777777777),
.INITP_02(256'h3333333333333333333333333333333333333333331000000000CEEEEEE66666),
.INITP_03(256'h0000000003333BAAAAAAAA222222222222222222222222233333333333333333),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'hFFFFFFF0FFFFFFF0FFFFFFF0FFFFFFF0FFFF8000FF0000000000000000000000),
.INIT_06(256'hAA57FFF0AA57FFF0AA57FFF0AA57FFF0AA57FFF0ABFFFFF0FFFFFFF0FFFFFFF0),
.INIT_07(256'hAA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA57FFC0AA57FFF0AA57FFF0),
.INIT_08(256'hAA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0AA5FFFC0),
.INIT_09(256'hAA7FFF00AA7FFF00AA7FFF00AA7FFF00AA7FFF00AA5FFF00AA5FFF00AA5FFF00),
.INIT_0A(256'hAA7FFE00AA7FFE00AA7FFE00AA7FFF00AA7FFF00AA7FFF00AA7FFF00AA7FFF00),
.INIT_0B(256'hAAFFFE00AAFFFE00AAFFFE00AAFFFE00AAFFFE00AAFFFE00AA7FFE00AA7FFE00),
.INIT_0C(256'hAAFFF800AAFFF800AAFFF800AAFFF800AAFFF800AAFFFE00AAFFFE00AAFFFE00),
.INIT_0D(256'hABFFF800ABFFF800ABFFF800ABFFF800ABFFF800ABFFF800AAFFF800AAFFF800),
.INIT_0E(256'hABFFE000ABFFE000ABFFE000ABFFE000ABFFE000ABFFE000ABFFE000ABFFE000),
.INIT_0F(256'hAFFF8000AFFF8000AFFF8000AFFFE000AFFFE000AFFFE000ABFFE000ABFFE000),
.INIT_10(256'hFFFF8000FFFF8000FFFF8000AFFF8000AFFF8000AFFF8000AFFF8000AFFF8000),
.INIT_11(256'h00000000000000000000000000000000FFFF0000FFFF8000FFFF8000FFFF8000),
.INIT_12(256'h0003FFFF0003FFFF00007FFF0000000000000000000000000000000000000000),
.INIT_13(256'h0003FFEA0003FFEA0003FFEA0003FFFF0003FFFF0003FFFF0003FFFF0003FFFF),
.INIT_14(256'h000FFFEA000FFFEA000FFFEA0003FFEA0003FFEA0003FFEA0003FFEA0003FFEA),
.INIT_15(256'h000FFFEA000FFFEA000FFFEA000FFFEA000FFFEA000FFFEA000FFFEA000FFFEA),
.INIT_16(256'h000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFEA000FFFEA),
.INIT_17(256'h000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA),
.INIT_18(256'h000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA),
.INIT_19(256'h003FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA000FFFAA),
.INIT_1A(256'h003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA),
.INIT_1B(256'h003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA),
.INIT_1C(256'h003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA003FFFAA),
.INIT_1D(256'h803FFFAA803FFFAA803FFFAA803FFFAA803FFFAA803FFFAA003FFFAA003FFFAA),
.INIT_1E(256'h00000000003FFFFF003FFFFF003FFFFF003FFFFF803FFFFF803FFDAA803FFDAA),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module Initial_blk_mem_gen_top
(douta,
clka,
addra);
output [1599:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [1599:0]douta;
Initial_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* C_FAMILY = "artix7" *) (* C_XDEVICEFAMILY = "artix7" *)
(* C_ELABORATION_DIR = "./" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_SLAVE_TYPE = "0" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *) (* C_HAS_AXI_ID = "0" *) (* C_AXI_ID_WIDTH = "4" *)
(* C_MEM_TYPE = "3" *) (* C_BYTE_SIZE = "9" *) (* C_ALGORITHM = "1" *)
(* C_PRIM_TYPE = "1" *) (* C_LOAD_INIT_FILE = "1" *) (* C_INIT_FILE_NAME = "Initial.mif" *)
(* C_INIT_FILE = "Initial.mem" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_DEFAULT_DATA = "0" *)
(* C_HAS_RSTA = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RSTRAM_A = "0" *)
(* C_INITA_VAL = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "1600" *) (* C_READ_WIDTH_A = "1600" *) (* C_WRITE_DEPTH_A = "600" *)
(* C_READ_DEPTH_A = "600" *) (* C_ADDRA_WIDTH = "10" *) (* C_HAS_RSTB = "0" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_RSTRAM_B = "0" *) (* C_INITB_VAL = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_REGCEB = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_WEB_WIDTH = "1" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_B = "1600" *)
(* C_READ_WIDTH_B = "1600" *) (* C_WRITE_DEPTH_B = "600" *) (* C_READ_DEPTH_B = "600" *)
(* C_ADDRB_WIDTH = "10" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_ECC = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_HAS_INJECTERR = "0" *)
(* C_SIM_COLLISION_CHECK = "ALL" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_COUNT_36K_BRAM = "44" *)
(* C_COUNT_18K_BRAM = "1" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 119.8268 mW" *) (* downgradeipidentifiedwarnings = "yes" *)
module Initial_blk_mem_gen_v8_2__parameterized0
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [1599:0]dina;
output [1599:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [1599:0]dinb;
output [1599:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [1599:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [1599:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [1599:0]dina;
wire [1599:0]dinb;
wire [1599:0]douta;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [1599:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign doutb[1599] = \<const0> ;
assign doutb[1598] = \<const0> ;
assign doutb[1597] = \<const0> ;
assign doutb[1596] = \<const0> ;
assign doutb[1595] = \<const0> ;
assign doutb[1594] = \<const0> ;
assign doutb[1593] = \<const0> ;
assign doutb[1592] = \<const0> ;
assign doutb[1591] = \<const0> ;
assign doutb[1590] = \<const0> ;
assign doutb[1589] = \<const0> ;
assign doutb[1588] = \<const0> ;
assign doutb[1587] = \<const0> ;
assign doutb[1586] = \<const0> ;
assign doutb[1585] = \<const0> ;
assign doutb[1584] = \<const0> ;
assign doutb[1583] = \<const0> ;
assign doutb[1582] = \<const0> ;
assign doutb[1581] = \<const0> ;
assign doutb[1580] = \<const0> ;
assign doutb[1579] = \<const0> ;
assign doutb[1578] = \<const0> ;
assign doutb[1577] = \<const0> ;
assign doutb[1576] = \<const0> ;
assign doutb[1575] = \<const0> ;
assign doutb[1574] = \<const0> ;
assign doutb[1573] = \<const0> ;
assign doutb[1572] = \<const0> ;
assign doutb[1571] = \<const0> ;
assign doutb[1570] = \<const0> ;
assign doutb[1569] = \<const0> ;
assign doutb[1568] = \<const0> ;
assign doutb[1567] = \<const0> ;
assign doutb[1566] = \<const0> ;
assign doutb[1565] = \<const0> ;
assign doutb[1564] = \<const0> ;
assign doutb[1563] = \<const0> ;
assign doutb[1562] = \<const0> ;
assign doutb[1561] = \<const0> ;
assign doutb[1560] = \<const0> ;
assign doutb[1559] = \<const0> ;
assign doutb[1558] = \<const0> ;
assign doutb[1557] = \<const0> ;
assign doutb[1556] = \<const0> ;
assign doutb[1555] = \<const0> ;
assign doutb[1554] = \<const0> ;
assign doutb[1553] = \<const0> ;
assign doutb[1552] = \<const0> ;
assign doutb[1551] = \<const0> ;
assign doutb[1550] = \<const0> ;
assign doutb[1549] = \<const0> ;
assign doutb[1548] = \<const0> ;
assign doutb[1547] = \<const0> ;
assign doutb[1546] = \<const0> ;
assign doutb[1545] = \<const0> ;
assign doutb[1544] = \<const0> ;
assign doutb[1543] = \<const0> ;
assign doutb[1542] = \<const0> ;
assign doutb[1541] = \<const0> ;
assign doutb[1540] = \<const0> ;
assign doutb[1539] = \<const0> ;
assign doutb[1538] = \<const0> ;
assign doutb[1537] = \<const0> ;
assign doutb[1536] = \<const0> ;
assign doutb[1535] = \<const0> ;
assign doutb[1534] = \<const0> ;
assign doutb[1533] = \<const0> ;
assign doutb[1532] = \<const0> ;
assign doutb[1531] = \<const0> ;
assign doutb[1530] = \<const0> ;
assign doutb[1529] = \<const0> ;
assign doutb[1528] = \<const0> ;
assign doutb[1527] = \<const0> ;
assign doutb[1526] = \<const0> ;
assign doutb[1525] = \<const0> ;
assign doutb[1524] = \<const0> ;
assign doutb[1523] = \<const0> ;
assign doutb[1522] = \<const0> ;
assign doutb[1521] = \<const0> ;
assign doutb[1520] = \<const0> ;
assign doutb[1519] = \<const0> ;
assign doutb[1518] = \<const0> ;
assign doutb[1517] = \<const0> ;
assign doutb[1516] = \<const0> ;
assign doutb[1515] = \<const0> ;
assign doutb[1514] = \<const0> ;
assign doutb[1513] = \<const0> ;
assign doutb[1512] = \<const0> ;
assign doutb[1511] = \<const0> ;
assign doutb[1510] = \<const0> ;
assign doutb[1509] = \<const0> ;
assign doutb[1508] = \<const0> ;
assign doutb[1507] = \<const0> ;
assign doutb[1506] = \<const0> ;
assign doutb[1505] = \<const0> ;
assign doutb[1504] = \<const0> ;
assign doutb[1503] = \<const0> ;
assign doutb[1502] = \<const0> ;
assign doutb[1501] = \<const0> ;
assign doutb[1500] = \<const0> ;
assign doutb[1499] = \<const0> ;
assign doutb[1498] = \<const0> ;
assign doutb[1497] = \<const0> ;
assign doutb[1496] = \<const0> ;
assign doutb[1495] = \<const0> ;
assign doutb[1494] = \<const0> ;
assign doutb[1493] = \<const0> ;
assign doutb[1492] = \<const0> ;
assign doutb[1491] = \<const0> ;
assign doutb[1490] = \<const0> ;
assign doutb[1489] = \<const0> ;
assign doutb[1488] = \<const0> ;
assign doutb[1487] = \<const0> ;
assign doutb[1486] = \<const0> ;
assign doutb[1485] = \<const0> ;
assign doutb[1484] = \<const0> ;
assign doutb[1483] = \<const0> ;
assign doutb[1482] = \<const0> ;
assign doutb[1481] = \<const0> ;
assign doutb[1480] = \<const0> ;
assign doutb[1479] = \<const0> ;
assign doutb[1478] = \<const0> ;
assign doutb[1477] = \<const0> ;
assign doutb[1476] = \<const0> ;
assign doutb[1475] = \<const0> ;
assign doutb[1474] = \<const0> ;
assign doutb[1473] = \<const0> ;
assign doutb[1472] = \<const0> ;
assign doutb[1471] = \<const0> ;
assign doutb[1470] = \<const0> ;
assign doutb[1469] = \<const0> ;
assign doutb[1468] = \<const0> ;
assign doutb[1467] = \<const0> ;
assign doutb[1466] = \<const0> ;
assign doutb[1465] = \<const0> ;
assign doutb[1464] = \<const0> ;
assign doutb[1463] = \<const0> ;
assign doutb[1462] = \<const0> ;
assign doutb[1461] = \<const0> ;
assign doutb[1460] = \<const0> ;
assign doutb[1459] = \<const0> ;
assign doutb[1458] = \<const0> ;
assign doutb[1457] = \<const0> ;
assign doutb[1456] = \<const0> ;
assign doutb[1455] = \<const0> ;
assign doutb[1454] = \<const0> ;
assign doutb[1453] = \<const0> ;
assign doutb[1452] = \<const0> ;
assign doutb[1451] = \<const0> ;
assign doutb[1450] = \<const0> ;
assign doutb[1449] = \<const0> ;
assign doutb[1448] = \<const0> ;
assign doutb[1447] = \<const0> ;
assign doutb[1446] = \<const0> ;
assign doutb[1445] = \<const0> ;
assign doutb[1444] = \<const0> ;
assign doutb[1443] = \<const0> ;
assign doutb[1442] = \<const0> ;
assign doutb[1441] = \<const0> ;
assign doutb[1440] = \<const0> ;
assign doutb[1439] = \<const0> ;
assign doutb[1438] = \<const0> ;
assign doutb[1437] = \<const0> ;
assign doutb[1436] = \<const0> ;
assign doutb[1435] = \<const0> ;
assign doutb[1434] = \<const0> ;
assign doutb[1433] = \<const0> ;
assign doutb[1432] = \<const0> ;
assign doutb[1431] = \<const0> ;
assign doutb[1430] = \<const0> ;
assign doutb[1429] = \<const0> ;
assign doutb[1428] = \<const0> ;
assign doutb[1427] = \<const0> ;
assign doutb[1426] = \<const0> ;
assign doutb[1425] = \<const0> ;
assign doutb[1424] = \<const0> ;
assign doutb[1423] = \<const0> ;
assign doutb[1422] = \<const0> ;
assign doutb[1421] = \<const0> ;
assign doutb[1420] = \<const0> ;
assign doutb[1419] = \<const0> ;
assign doutb[1418] = \<const0> ;
assign doutb[1417] = \<const0> ;
assign doutb[1416] = \<const0> ;
assign doutb[1415] = \<const0> ;
assign doutb[1414] = \<const0> ;
assign doutb[1413] = \<const0> ;
assign doutb[1412] = \<const0> ;
assign doutb[1411] = \<const0> ;
assign doutb[1410] = \<const0> ;
assign doutb[1409] = \<const0> ;
assign doutb[1408] = \<const0> ;
assign doutb[1407] = \<const0> ;
assign doutb[1406] = \<const0> ;
assign doutb[1405] = \<const0> ;
assign doutb[1404] = \<const0> ;
assign doutb[1403] = \<const0> ;
assign doutb[1402] = \<const0> ;
assign doutb[1401] = \<const0> ;
assign doutb[1400] = \<const0> ;
assign doutb[1399] = \<const0> ;
assign doutb[1398] = \<const0> ;
assign doutb[1397] = \<const0> ;
assign doutb[1396] = \<const0> ;
assign doutb[1395] = \<const0> ;
assign doutb[1394] = \<const0> ;
assign doutb[1393] = \<const0> ;
assign doutb[1392] = \<const0> ;
assign doutb[1391] = \<const0> ;
assign doutb[1390] = \<const0> ;
assign doutb[1389] = \<const0> ;
assign doutb[1388] = \<const0> ;
assign doutb[1387] = \<const0> ;
assign doutb[1386] = \<const0> ;
assign doutb[1385] = \<const0> ;
assign doutb[1384] = \<const0> ;
assign doutb[1383] = \<const0> ;
assign doutb[1382] = \<const0> ;
assign doutb[1381] = \<const0> ;
assign doutb[1380] = \<const0> ;
assign doutb[1379] = \<const0> ;
assign doutb[1378] = \<const0> ;
assign doutb[1377] = \<const0> ;
assign doutb[1376] = \<const0> ;
assign doutb[1375] = \<const0> ;
assign doutb[1374] = \<const0> ;
assign doutb[1373] = \<const0> ;
assign doutb[1372] = \<const0> ;
assign doutb[1371] = \<const0> ;
assign doutb[1370] = \<const0> ;
assign doutb[1369] = \<const0> ;
assign doutb[1368] = \<const0> ;
assign doutb[1367] = \<const0> ;
assign doutb[1366] = \<const0> ;
assign doutb[1365] = \<const0> ;
assign doutb[1364] = \<const0> ;
assign doutb[1363] = \<const0> ;
assign doutb[1362] = \<const0> ;
assign doutb[1361] = \<const0> ;
assign doutb[1360] = \<const0> ;
assign doutb[1359] = \<const0> ;
assign doutb[1358] = \<const0> ;
assign doutb[1357] = \<const0> ;
assign doutb[1356] = \<const0> ;
assign doutb[1355] = \<const0> ;
assign doutb[1354] = \<const0> ;
assign doutb[1353] = \<const0> ;
assign doutb[1352] = \<const0> ;
assign doutb[1351] = \<const0> ;
assign doutb[1350] = \<const0> ;
assign doutb[1349] = \<const0> ;
assign doutb[1348] = \<const0> ;
assign doutb[1347] = \<const0> ;
assign doutb[1346] = \<const0> ;
assign doutb[1345] = \<const0> ;
assign doutb[1344] = \<const0> ;
assign doutb[1343] = \<const0> ;
assign doutb[1342] = \<const0> ;
assign doutb[1341] = \<const0> ;
assign doutb[1340] = \<const0> ;
assign doutb[1339] = \<const0> ;
assign doutb[1338] = \<const0> ;
assign doutb[1337] = \<const0> ;
assign doutb[1336] = \<const0> ;
assign doutb[1335] = \<const0> ;
assign doutb[1334] = \<const0> ;
assign doutb[1333] = \<const0> ;
assign doutb[1332] = \<const0> ;
assign doutb[1331] = \<const0> ;
assign doutb[1330] = \<const0> ;
assign doutb[1329] = \<const0> ;
assign doutb[1328] = \<const0> ;
assign doutb[1327] = \<const0> ;
assign doutb[1326] = \<const0> ;
assign doutb[1325] = \<const0> ;
assign doutb[1324] = \<const0> ;
assign doutb[1323] = \<const0> ;
assign doutb[1322] = \<const0> ;
assign doutb[1321] = \<const0> ;
assign doutb[1320] = \<const0> ;
assign doutb[1319] = \<const0> ;
assign doutb[1318] = \<const0> ;
assign doutb[1317] = \<const0> ;
assign doutb[1316] = \<const0> ;
assign doutb[1315] = \<const0> ;
assign doutb[1314] = \<const0> ;
assign doutb[1313] = \<const0> ;
assign doutb[1312] = \<const0> ;
assign doutb[1311] = \<const0> ;
assign doutb[1310] = \<const0> ;
assign doutb[1309] = \<const0> ;
assign doutb[1308] = \<const0> ;
assign doutb[1307] = \<const0> ;
assign doutb[1306] = \<const0> ;
assign doutb[1305] = \<const0> ;
assign doutb[1304] = \<const0> ;
assign doutb[1303] = \<const0> ;
assign doutb[1302] = \<const0> ;
assign doutb[1301] = \<const0> ;
assign doutb[1300] = \<const0> ;
assign doutb[1299] = \<const0> ;
assign doutb[1298] = \<const0> ;
assign doutb[1297] = \<const0> ;
assign doutb[1296] = \<const0> ;
assign doutb[1295] = \<const0> ;
assign doutb[1294] = \<const0> ;
assign doutb[1293] = \<const0> ;
assign doutb[1292] = \<const0> ;
assign doutb[1291] = \<const0> ;
assign doutb[1290] = \<const0> ;
assign doutb[1289] = \<const0> ;
assign doutb[1288] = \<const0> ;
assign doutb[1287] = \<const0> ;
assign doutb[1286] = \<const0> ;
assign doutb[1285] = \<const0> ;
assign doutb[1284] = \<const0> ;
assign doutb[1283] = \<const0> ;
assign doutb[1282] = \<const0> ;
assign doutb[1281] = \<const0> ;
assign doutb[1280] = \<const0> ;
assign doutb[1279] = \<const0> ;
assign doutb[1278] = \<const0> ;
assign doutb[1277] = \<const0> ;
assign doutb[1276] = \<const0> ;
assign doutb[1275] = \<const0> ;
assign doutb[1274] = \<const0> ;
assign doutb[1273] = \<const0> ;
assign doutb[1272] = \<const0> ;
assign doutb[1271] = \<const0> ;
assign doutb[1270] = \<const0> ;
assign doutb[1269] = \<const0> ;
assign doutb[1268] = \<const0> ;
assign doutb[1267] = \<const0> ;
assign doutb[1266] = \<const0> ;
assign doutb[1265] = \<const0> ;
assign doutb[1264] = \<const0> ;
assign doutb[1263] = \<const0> ;
assign doutb[1262] = \<const0> ;
assign doutb[1261] = \<const0> ;
assign doutb[1260] = \<const0> ;
assign doutb[1259] = \<const0> ;
assign doutb[1258] = \<const0> ;
assign doutb[1257] = \<const0> ;
assign doutb[1256] = \<const0> ;
assign doutb[1255] = \<const0> ;
assign doutb[1254] = \<const0> ;
assign doutb[1253] = \<const0> ;
assign doutb[1252] = \<const0> ;
assign doutb[1251] = \<const0> ;
assign doutb[1250] = \<const0> ;
assign doutb[1249] = \<const0> ;
assign doutb[1248] = \<const0> ;
assign doutb[1247] = \<const0> ;
assign doutb[1246] = \<const0> ;
assign doutb[1245] = \<const0> ;
assign doutb[1244] = \<const0> ;
assign doutb[1243] = \<const0> ;
assign doutb[1242] = \<const0> ;
assign doutb[1241] = \<const0> ;
assign doutb[1240] = \<const0> ;
assign doutb[1239] = \<const0> ;
assign doutb[1238] = \<const0> ;
assign doutb[1237] = \<const0> ;
assign doutb[1236] = \<const0> ;
assign doutb[1235] = \<const0> ;
assign doutb[1234] = \<const0> ;
assign doutb[1233] = \<const0> ;
assign doutb[1232] = \<const0> ;
assign doutb[1231] = \<const0> ;
assign doutb[1230] = \<const0> ;
assign doutb[1229] = \<const0> ;
assign doutb[1228] = \<const0> ;
assign doutb[1227] = \<const0> ;
assign doutb[1226] = \<const0> ;
assign doutb[1225] = \<const0> ;
assign doutb[1224] = \<const0> ;
assign doutb[1223] = \<const0> ;
assign doutb[1222] = \<const0> ;
assign doutb[1221] = \<const0> ;
assign doutb[1220] = \<const0> ;
assign doutb[1219] = \<const0> ;
assign doutb[1218] = \<const0> ;
assign doutb[1217] = \<const0> ;
assign doutb[1216] = \<const0> ;
assign doutb[1215] = \<const0> ;
assign doutb[1214] = \<const0> ;
assign doutb[1213] = \<const0> ;
assign doutb[1212] = \<const0> ;
assign doutb[1211] = \<const0> ;
assign doutb[1210] = \<const0> ;
assign doutb[1209] = \<const0> ;
assign doutb[1208] = \<const0> ;
assign doutb[1207] = \<const0> ;
assign doutb[1206] = \<const0> ;
assign doutb[1205] = \<const0> ;
assign doutb[1204] = \<const0> ;
assign doutb[1203] = \<const0> ;
assign doutb[1202] = \<const0> ;
assign doutb[1201] = \<const0> ;
assign doutb[1200] = \<const0> ;
assign doutb[1199] = \<const0> ;
assign doutb[1198] = \<const0> ;
assign doutb[1197] = \<const0> ;
assign doutb[1196] = \<const0> ;
assign doutb[1195] = \<const0> ;
assign doutb[1194] = \<const0> ;
assign doutb[1193] = \<const0> ;
assign doutb[1192] = \<const0> ;
assign doutb[1191] = \<const0> ;
assign doutb[1190] = \<const0> ;
assign doutb[1189] = \<const0> ;
assign doutb[1188] = \<const0> ;
assign doutb[1187] = \<const0> ;
assign doutb[1186] = \<const0> ;
assign doutb[1185] = \<const0> ;
assign doutb[1184] = \<const0> ;
assign doutb[1183] = \<const0> ;
assign doutb[1182] = \<const0> ;
assign doutb[1181] = \<const0> ;
assign doutb[1180] = \<const0> ;
assign doutb[1179] = \<const0> ;
assign doutb[1178] = \<const0> ;
assign doutb[1177] = \<const0> ;
assign doutb[1176] = \<const0> ;
assign doutb[1175] = \<const0> ;
assign doutb[1174] = \<const0> ;
assign doutb[1173] = \<const0> ;
assign doutb[1172] = \<const0> ;
assign doutb[1171] = \<const0> ;
assign doutb[1170] = \<const0> ;
assign doutb[1169] = \<const0> ;
assign doutb[1168] = \<const0> ;
assign doutb[1167] = \<const0> ;
assign doutb[1166] = \<const0> ;
assign doutb[1165] = \<const0> ;
assign doutb[1164] = \<const0> ;
assign doutb[1163] = \<const0> ;
assign doutb[1162] = \<const0> ;
assign doutb[1161] = \<const0> ;
assign doutb[1160] = \<const0> ;
assign doutb[1159] = \<const0> ;
assign doutb[1158] = \<const0> ;
assign doutb[1157] = \<const0> ;
assign doutb[1156] = \<const0> ;
assign doutb[1155] = \<const0> ;
assign doutb[1154] = \<const0> ;
assign doutb[1153] = \<const0> ;
assign doutb[1152] = \<const0> ;
assign doutb[1151] = \<const0> ;
assign doutb[1150] = \<const0> ;
assign doutb[1149] = \<const0> ;
assign doutb[1148] = \<const0> ;
assign doutb[1147] = \<const0> ;
assign doutb[1146] = \<const0> ;
assign doutb[1145] = \<const0> ;
assign doutb[1144] = \<const0> ;
assign doutb[1143] = \<const0> ;
assign doutb[1142] = \<const0> ;
assign doutb[1141] = \<const0> ;
assign doutb[1140] = \<const0> ;
assign doutb[1139] = \<const0> ;
assign doutb[1138] = \<const0> ;
assign doutb[1137] = \<const0> ;
assign doutb[1136] = \<const0> ;
assign doutb[1135] = \<const0> ;
assign doutb[1134] = \<const0> ;
assign doutb[1133] = \<const0> ;
assign doutb[1132] = \<const0> ;
assign doutb[1131] = \<const0> ;
assign doutb[1130] = \<const0> ;
assign doutb[1129] = \<const0> ;
assign doutb[1128] = \<const0> ;
assign doutb[1127] = \<const0> ;
assign doutb[1126] = \<const0> ;
assign doutb[1125] = \<const0> ;
assign doutb[1124] = \<const0> ;
assign doutb[1123] = \<const0> ;
assign doutb[1122] = \<const0> ;
assign doutb[1121] = \<const0> ;
assign doutb[1120] = \<const0> ;
assign doutb[1119] = \<const0> ;
assign doutb[1118] = \<const0> ;
assign doutb[1117] = \<const0> ;
assign doutb[1116] = \<const0> ;
assign doutb[1115] = \<const0> ;
assign doutb[1114] = \<const0> ;
assign doutb[1113] = \<const0> ;
assign doutb[1112] = \<const0> ;
assign doutb[1111] = \<const0> ;
assign doutb[1110] = \<const0> ;
assign doutb[1109] = \<const0> ;
assign doutb[1108] = \<const0> ;
assign doutb[1107] = \<const0> ;
assign doutb[1106] = \<const0> ;
assign doutb[1105] = \<const0> ;
assign doutb[1104] = \<const0> ;
assign doutb[1103] = \<const0> ;
assign doutb[1102] = \<const0> ;
assign doutb[1101] = \<const0> ;
assign doutb[1100] = \<const0> ;
assign doutb[1099] = \<const0> ;
assign doutb[1098] = \<const0> ;
assign doutb[1097] = \<const0> ;
assign doutb[1096] = \<const0> ;
assign doutb[1095] = \<const0> ;
assign doutb[1094] = \<const0> ;
assign doutb[1093] = \<const0> ;
assign doutb[1092] = \<const0> ;
assign doutb[1091] = \<const0> ;
assign doutb[1090] = \<const0> ;
assign doutb[1089] = \<const0> ;
assign doutb[1088] = \<const0> ;
assign doutb[1087] = \<const0> ;
assign doutb[1086] = \<const0> ;
assign doutb[1085] = \<const0> ;
assign doutb[1084] = \<const0> ;
assign doutb[1083] = \<const0> ;
assign doutb[1082] = \<const0> ;
assign doutb[1081] = \<const0> ;
assign doutb[1080] = \<const0> ;
assign doutb[1079] = \<const0> ;
assign doutb[1078] = \<const0> ;
assign doutb[1077] = \<const0> ;
assign doutb[1076] = \<const0> ;
assign doutb[1075] = \<const0> ;
assign doutb[1074] = \<const0> ;
assign doutb[1073] = \<const0> ;
assign doutb[1072] = \<const0> ;
assign doutb[1071] = \<const0> ;
assign doutb[1070] = \<const0> ;
assign doutb[1069] = \<const0> ;
assign doutb[1068] = \<const0> ;
assign doutb[1067] = \<const0> ;
assign doutb[1066] = \<const0> ;
assign doutb[1065] = \<const0> ;
assign doutb[1064] = \<const0> ;
assign doutb[1063] = \<const0> ;
assign doutb[1062] = \<const0> ;
assign doutb[1061] = \<const0> ;
assign doutb[1060] = \<const0> ;
assign doutb[1059] = \<const0> ;
assign doutb[1058] = \<const0> ;
assign doutb[1057] = \<const0> ;
assign doutb[1056] = \<const0> ;
assign doutb[1055] = \<const0> ;
assign doutb[1054] = \<const0> ;
assign doutb[1053] = \<const0> ;
assign doutb[1052] = \<const0> ;
assign doutb[1051] = \<const0> ;
assign doutb[1050] = \<const0> ;
assign doutb[1049] = \<const0> ;
assign doutb[1048] = \<const0> ;
assign doutb[1047] = \<const0> ;
assign doutb[1046] = \<const0> ;
assign doutb[1045] = \<const0> ;
assign doutb[1044] = \<const0> ;
assign doutb[1043] = \<const0> ;
assign doutb[1042] = \<const0> ;
assign doutb[1041] = \<const0> ;
assign doutb[1040] = \<const0> ;
assign doutb[1039] = \<const0> ;
assign doutb[1038] = \<const0> ;
assign doutb[1037] = \<const0> ;
assign doutb[1036] = \<const0> ;
assign doutb[1035] = \<const0> ;
assign doutb[1034] = \<const0> ;
assign doutb[1033] = \<const0> ;
assign doutb[1032] = \<const0> ;
assign doutb[1031] = \<const0> ;
assign doutb[1030] = \<const0> ;
assign doutb[1029] = \<const0> ;
assign doutb[1028] = \<const0> ;
assign doutb[1027] = \<const0> ;
assign doutb[1026] = \<const0> ;
assign doutb[1025] = \<const0> ;
assign doutb[1024] = \<const0> ;
assign doutb[1023] = \<const0> ;
assign doutb[1022] = \<const0> ;
assign doutb[1021] = \<const0> ;
assign doutb[1020] = \<const0> ;
assign doutb[1019] = \<const0> ;
assign doutb[1018] = \<const0> ;
assign doutb[1017] = \<const0> ;
assign doutb[1016] = \<const0> ;
assign doutb[1015] = \<const0> ;
assign doutb[1014] = \<const0> ;
assign doutb[1013] = \<const0> ;
assign doutb[1012] = \<const0> ;
assign doutb[1011] = \<const0> ;
assign doutb[1010] = \<const0> ;
assign doutb[1009] = \<const0> ;
assign doutb[1008] = \<const0> ;
assign doutb[1007] = \<const0> ;
assign doutb[1006] = \<const0> ;
assign doutb[1005] = \<const0> ;
assign doutb[1004] = \<const0> ;
assign doutb[1003] = \<const0> ;
assign doutb[1002] = \<const0> ;
assign doutb[1001] = \<const0> ;
assign doutb[1000] = \<const0> ;
assign doutb[999] = \<const0> ;
assign doutb[998] = \<const0> ;
assign doutb[997] = \<const0> ;
assign doutb[996] = \<const0> ;
assign doutb[995] = \<const0> ;
assign doutb[994] = \<const0> ;
assign doutb[993] = \<const0> ;
assign doutb[992] = \<const0> ;
assign doutb[991] = \<const0> ;
assign doutb[990] = \<const0> ;
assign doutb[989] = \<const0> ;
assign doutb[988] = \<const0> ;
assign doutb[987] = \<const0> ;
assign doutb[986] = \<const0> ;
assign doutb[985] = \<const0> ;
assign doutb[984] = \<const0> ;
assign doutb[983] = \<const0> ;
assign doutb[982] = \<const0> ;
assign doutb[981] = \<const0> ;
assign doutb[980] = \<const0> ;
assign doutb[979] = \<const0> ;
assign doutb[978] = \<const0> ;
assign doutb[977] = \<const0> ;
assign doutb[976] = \<const0> ;
assign doutb[975] = \<const0> ;
assign doutb[974] = \<const0> ;
assign doutb[973] = \<const0> ;
assign doutb[972] = \<const0> ;
assign doutb[971] = \<const0> ;
assign doutb[970] = \<const0> ;
assign doutb[969] = \<const0> ;
assign doutb[968] = \<const0> ;
assign doutb[967] = \<const0> ;
assign doutb[966] = \<const0> ;
assign doutb[965] = \<const0> ;
assign doutb[964] = \<const0> ;
assign doutb[963] = \<const0> ;
assign doutb[962] = \<const0> ;
assign doutb[961] = \<const0> ;
assign doutb[960] = \<const0> ;
assign doutb[959] = \<const0> ;
assign doutb[958] = \<const0> ;
assign doutb[957] = \<const0> ;
assign doutb[956] = \<const0> ;
assign doutb[955] = \<const0> ;
assign doutb[954] = \<const0> ;
assign doutb[953] = \<const0> ;
assign doutb[952] = \<const0> ;
assign doutb[951] = \<const0> ;
assign doutb[950] = \<const0> ;
assign doutb[949] = \<const0> ;
assign doutb[948] = \<const0> ;
assign doutb[947] = \<const0> ;
assign doutb[946] = \<const0> ;
assign doutb[945] = \<const0> ;
assign doutb[944] = \<const0> ;
assign doutb[943] = \<const0> ;
assign doutb[942] = \<const0> ;
assign doutb[941] = \<const0> ;
assign doutb[940] = \<const0> ;
assign doutb[939] = \<const0> ;
assign doutb[938] = \<const0> ;
assign doutb[937] = \<const0> ;
assign doutb[936] = \<const0> ;
assign doutb[935] = \<const0> ;
assign doutb[934] = \<const0> ;
assign doutb[933] = \<const0> ;
assign doutb[932] = \<const0> ;
assign doutb[931] = \<const0> ;
assign doutb[930] = \<const0> ;
assign doutb[929] = \<const0> ;
assign doutb[928] = \<const0> ;
assign doutb[927] = \<const0> ;
assign doutb[926] = \<const0> ;
assign doutb[925] = \<const0> ;
assign doutb[924] = \<const0> ;
assign doutb[923] = \<const0> ;
assign doutb[922] = \<const0> ;
assign doutb[921] = \<const0> ;
assign doutb[920] = \<const0> ;
assign doutb[919] = \<const0> ;
assign doutb[918] = \<const0> ;
assign doutb[917] = \<const0> ;
assign doutb[916] = \<const0> ;
assign doutb[915] = \<const0> ;
assign doutb[914] = \<const0> ;
assign doutb[913] = \<const0> ;
assign doutb[912] = \<const0> ;
assign doutb[911] = \<const0> ;
assign doutb[910] = \<const0> ;
assign doutb[909] = \<const0> ;
assign doutb[908] = \<const0> ;
assign doutb[907] = \<const0> ;
assign doutb[906] = \<const0> ;
assign doutb[905] = \<const0> ;
assign doutb[904] = \<const0> ;
assign doutb[903] = \<const0> ;
assign doutb[902] = \<const0> ;
assign doutb[901] = \<const0> ;
assign doutb[900] = \<const0> ;
assign doutb[899] = \<const0> ;
assign doutb[898] = \<const0> ;
assign doutb[897] = \<const0> ;
assign doutb[896] = \<const0> ;
assign doutb[895] = \<const0> ;
assign doutb[894] = \<const0> ;
assign doutb[893] = \<const0> ;
assign doutb[892] = \<const0> ;
assign doutb[891] = \<const0> ;
assign doutb[890] = \<const0> ;
assign doutb[889] = \<const0> ;
assign doutb[888] = \<const0> ;
assign doutb[887] = \<const0> ;
assign doutb[886] = \<const0> ;
assign doutb[885] = \<const0> ;
assign doutb[884] = \<const0> ;
assign doutb[883] = \<const0> ;
assign doutb[882] = \<const0> ;
assign doutb[881] = \<const0> ;
assign doutb[880] = \<const0> ;
assign doutb[879] = \<const0> ;
assign doutb[878] = \<const0> ;
assign doutb[877] = \<const0> ;
assign doutb[876] = \<const0> ;
assign doutb[875] = \<const0> ;
assign doutb[874] = \<const0> ;
assign doutb[873] = \<const0> ;
assign doutb[872] = \<const0> ;
assign doutb[871] = \<const0> ;
assign doutb[870] = \<const0> ;
assign doutb[869] = \<const0> ;
assign doutb[868] = \<const0> ;
assign doutb[867] = \<const0> ;
assign doutb[866] = \<const0> ;
assign doutb[865] = \<const0> ;
assign doutb[864] = \<const0> ;
assign doutb[863] = \<const0> ;
assign doutb[862] = \<const0> ;
assign doutb[861] = \<const0> ;
assign doutb[860] = \<const0> ;
assign doutb[859] = \<const0> ;
assign doutb[858] = \<const0> ;
assign doutb[857] = \<const0> ;
assign doutb[856] = \<const0> ;
assign doutb[855] = \<const0> ;
assign doutb[854] = \<const0> ;
assign doutb[853] = \<const0> ;
assign doutb[852] = \<const0> ;
assign doutb[851] = \<const0> ;
assign doutb[850] = \<const0> ;
assign doutb[849] = \<const0> ;
assign doutb[848] = \<const0> ;
assign doutb[847] = \<const0> ;
assign doutb[846] = \<const0> ;
assign doutb[845] = \<const0> ;
assign doutb[844] = \<const0> ;
assign doutb[843] = \<const0> ;
assign doutb[842] = \<const0> ;
assign doutb[841] = \<const0> ;
assign doutb[840] = \<const0> ;
assign doutb[839] = \<const0> ;
assign doutb[838] = \<const0> ;
assign doutb[837] = \<const0> ;
assign doutb[836] = \<const0> ;
assign doutb[835] = \<const0> ;
assign doutb[834] = \<const0> ;
assign doutb[833] = \<const0> ;
assign doutb[832] = \<const0> ;
assign doutb[831] = \<const0> ;
assign doutb[830] = \<const0> ;
assign doutb[829] = \<const0> ;
assign doutb[828] = \<const0> ;
assign doutb[827] = \<const0> ;
assign doutb[826] = \<const0> ;
assign doutb[825] = \<const0> ;
assign doutb[824] = \<const0> ;
assign doutb[823] = \<const0> ;
assign doutb[822] = \<const0> ;
assign doutb[821] = \<const0> ;
assign doutb[820] = \<const0> ;
assign doutb[819] = \<const0> ;
assign doutb[818] = \<const0> ;
assign doutb[817] = \<const0> ;
assign doutb[816] = \<const0> ;
assign doutb[815] = \<const0> ;
assign doutb[814] = \<const0> ;
assign doutb[813] = \<const0> ;
assign doutb[812] = \<const0> ;
assign doutb[811] = \<const0> ;
assign doutb[810] = \<const0> ;
assign doutb[809] = \<const0> ;
assign doutb[808] = \<const0> ;
assign doutb[807] = \<const0> ;
assign doutb[806] = \<const0> ;
assign doutb[805] = \<const0> ;
assign doutb[804] = \<const0> ;
assign doutb[803] = \<const0> ;
assign doutb[802] = \<const0> ;
assign doutb[801] = \<const0> ;
assign doutb[800] = \<const0> ;
assign doutb[799] = \<const0> ;
assign doutb[798] = \<const0> ;
assign doutb[797] = \<const0> ;
assign doutb[796] = \<const0> ;
assign doutb[795] = \<const0> ;
assign doutb[794] = \<const0> ;
assign doutb[793] = \<const0> ;
assign doutb[792] = \<const0> ;
assign doutb[791] = \<const0> ;
assign doutb[790] = \<const0> ;
assign doutb[789] = \<const0> ;
assign doutb[788] = \<const0> ;
assign doutb[787] = \<const0> ;
assign doutb[786] = \<const0> ;
assign doutb[785] = \<const0> ;
assign doutb[784] = \<const0> ;
assign doutb[783] = \<const0> ;
assign doutb[782] = \<const0> ;
assign doutb[781] = \<const0> ;
assign doutb[780] = \<const0> ;
assign doutb[779] = \<const0> ;
assign doutb[778] = \<const0> ;
assign doutb[777] = \<const0> ;
assign doutb[776] = \<const0> ;
assign doutb[775] = \<const0> ;
assign doutb[774] = \<const0> ;
assign doutb[773] = \<const0> ;
assign doutb[772] = \<const0> ;
assign doutb[771] = \<const0> ;
assign doutb[770] = \<const0> ;
assign doutb[769] = \<const0> ;
assign doutb[768] = \<const0> ;
assign doutb[767] = \<const0> ;
assign doutb[766] = \<const0> ;
assign doutb[765] = \<const0> ;
assign doutb[764] = \<const0> ;
assign doutb[763] = \<const0> ;
assign doutb[762] = \<const0> ;
assign doutb[761] = \<const0> ;
assign doutb[760] = \<const0> ;
assign doutb[759] = \<const0> ;
assign doutb[758] = \<const0> ;
assign doutb[757] = \<const0> ;
assign doutb[756] = \<const0> ;
assign doutb[755] = \<const0> ;
assign doutb[754] = \<const0> ;
assign doutb[753] = \<const0> ;
assign doutb[752] = \<const0> ;
assign doutb[751] = \<const0> ;
assign doutb[750] = \<const0> ;
assign doutb[749] = \<const0> ;
assign doutb[748] = \<const0> ;
assign doutb[747] = \<const0> ;
assign doutb[746] = \<const0> ;
assign doutb[745] = \<const0> ;
assign doutb[744] = \<const0> ;
assign doutb[743] = \<const0> ;
assign doutb[742] = \<const0> ;
assign doutb[741] = \<const0> ;
assign doutb[740] = \<const0> ;
assign doutb[739] = \<const0> ;
assign doutb[738] = \<const0> ;
assign doutb[737] = \<const0> ;
assign doutb[736] = \<const0> ;
assign doutb[735] = \<const0> ;
assign doutb[734] = \<const0> ;
assign doutb[733] = \<const0> ;
assign doutb[732] = \<const0> ;
assign doutb[731] = \<const0> ;
assign doutb[730] = \<const0> ;
assign doutb[729] = \<const0> ;
assign doutb[728] = \<const0> ;
assign doutb[727] = \<const0> ;
assign doutb[726] = \<const0> ;
assign doutb[725] = \<const0> ;
assign doutb[724] = \<const0> ;
assign doutb[723] = \<const0> ;
assign doutb[722] = \<const0> ;
assign doutb[721] = \<const0> ;
assign doutb[720] = \<const0> ;
assign doutb[719] = \<const0> ;
assign doutb[718] = \<const0> ;
assign doutb[717] = \<const0> ;
assign doutb[716] = \<const0> ;
assign doutb[715] = \<const0> ;
assign doutb[714] = \<const0> ;
assign doutb[713] = \<const0> ;
assign doutb[712] = \<const0> ;
assign doutb[711] = \<const0> ;
assign doutb[710] = \<const0> ;
assign doutb[709] = \<const0> ;
assign doutb[708] = \<const0> ;
assign doutb[707] = \<const0> ;
assign doutb[706] = \<const0> ;
assign doutb[705] = \<const0> ;
assign doutb[704] = \<const0> ;
assign doutb[703] = \<const0> ;
assign doutb[702] = \<const0> ;
assign doutb[701] = \<const0> ;
assign doutb[700] = \<const0> ;
assign doutb[699] = \<const0> ;
assign doutb[698] = \<const0> ;
assign doutb[697] = \<const0> ;
assign doutb[696] = \<const0> ;
assign doutb[695] = \<const0> ;
assign doutb[694] = \<const0> ;
assign doutb[693] = \<const0> ;
assign doutb[692] = \<const0> ;
assign doutb[691] = \<const0> ;
assign doutb[690] = \<const0> ;
assign doutb[689] = \<const0> ;
assign doutb[688] = \<const0> ;
assign doutb[687] = \<const0> ;
assign doutb[686] = \<const0> ;
assign doutb[685] = \<const0> ;
assign doutb[684] = \<const0> ;
assign doutb[683] = \<const0> ;
assign doutb[682] = \<const0> ;
assign doutb[681] = \<const0> ;
assign doutb[680] = \<const0> ;
assign doutb[679] = \<const0> ;
assign doutb[678] = \<const0> ;
assign doutb[677] = \<const0> ;
assign doutb[676] = \<const0> ;
assign doutb[675] = \<const0> ;
assign doutb[674] = \<const0> ;
assign doutb[673] = \<const0> ;
assign doutb[672] = \<const0> ;
assign doutb[671] = \<const0> ;
assign doutb[670] = \<const0> ;
assign doutb[669] = \<const0> ;
assign doutb[668] = \<const0> ;
assign doutb[667] = \<const0> ;
assign doutb[666] = \<const0> ;
assign doutb[665] = \<const0> ;
assign doutb[664] = \<const0> ;
assign doutb[663] = \<const0> ;
assign doutb[662] = \<const0> ;
assign doutb[661] = \<const0> ;
assign doutb[660] = \<const0> ;
assign doutb[659] = \<const0> ;
assign doutb[658] = \<const0> ;
assign doutb[657] = \<const0> ;
assign doutb[656] = \<const0> ;
assign doutb[655] = \<const0> ;
assign doutb[654] = \<const0> ;
assign doutb[653] = \<const0> ;
assign doutb[652] = \<const0> ;
assign doutb[651] = \<const0> ;
assign doutb[650] = \<const0> ;
assign doutb[649] = \<const0> ;
assign doutb[648] = \<const0> ;
assign doutb[647] = \<const0> ;
assign doutb[646] = \<const0> ;
assign doutb[645] = \<const0> ;
assign doutb[644] = \<const0> ;
assign doutb[643] = \<const0> ;
assign doutb[642] = \<const0> ;
assign doutb[641] = \<const0> ;
assign doutb[640] = \<const0> ;
assign doutb[639] = \<const0> ;
assign doutb[638] = \<const0> ;
assign doutb[637] = \<const0> ;
assign doutb[636] = \<const0> ;
assign doutb[635] = \<const0> ;
assign doutb[634] = \<const0> ;
assign doutb[633] = \<const0> ;
assign doutb[632] = \<const0> ;
assign doutb[631] = \<const0> ;
assign doutb[630] = \<const0> ;
assign doutb[629] = \<const0> ;
assign doutb[628] = \<const0> ;
assign doutb[627] = \<const0> ;
assign doutb[626] = \<const0> ;
assign doutb[625] = \<const0> ;
assign doutb[624] = \<const0> ;
assign doutb[623] = \<const0> ;
assign doutb[622] = \<const0> ;
assign doutb[621] = \<const0> ;
assign doutb[620] = \<const0> ;
assign doutb[619] = \<const0> ;
assign doutb[618] = \<const0> ;
assign doutb[617] = \<const0> ;
assign doutb[616] = \<const0> ;
assign doutb[615] = \<const0> ;
assign doutb[614] = \<const0> ;
assign doutb[613] = \<const0> ;
assign doutb[612] = \<const0> ;
assign doutb[611] = \<const0> ;
assign doutb[610] = \<const0> ;
assign doutb[609] = \<const0> ;
assign doutb[608] = \<const0> ;
assign doutb[607] = \<const0> ;
assign doutb[606] = \<const0> ;
assign doutb[605] = \<const0> ;
assign doutb[604] = \<const0> ;
assign doutb[603] = \<const0> ;
assign doutb[602] = \<const0> ;
assign doutb[601] = \<const0> ;
assign doutb[600] = \<const0> ;
assign doutb[599] = \<const0> ;
assign doutb[598] = \<const0> ;
assign doutb[597] = \<const0> ;
assign doutb[596] = \<const0> ;
assign doutb[595] = \<const0> ;
assign doutb[594] = \<const0> ;
assign doutb[593] = \<const0> ;
assign doutb[592] = \<const0> ;
assign doutb[591] = \<const0> ;
assign doutb[590] = \<const0> ;
assign doutb[589] = \<const0> ;
assign doutb[588] = \<const0> ;
assign doutb[587] = \<const0> ;
assign doutb[586] = \<const0> ;
assign doutb[585] = \<const0> ;
assign doutb[584] = \<const0> ;
assign doutb[583] = \<const0> ;
assign doutb[582] = \<const0> ;
assign doutb[581] = \<const0> ;
assign doutb[580] = \<const0> ;
assign doutb[579] = \<const0> ;
assign doutb[578] = \<const0> ;
assign doutb[577] = \<const0> ;
assign doutb[576] = \<const0> ;
assign doutb[575] = \<const0> ;
assign doutb[574] = \<const0> ;
assign doutb[573] = \<const0> ;
assign doutb[572] = \<const0> ;
assign doutb[571] = \<const0> ;
assign doutb[570] = \<const0> ;
assign doutb[569] = \<const0> ;
assign doutb[568] = \<const0> ;
assign doutb[567] = \<const0> ;
assign doutb[566] = \<const0> ;
assign doutb[565] = \<const0> ;
assign doutb[564] = \<const0> ;
assign doutb[563] = \<const0> ;
assign doutb[562] = \<const0> ;
assign doutb[561] = \<const0> ;
assign doutb[560] = \<const0> ;
assign doutb[559] = \<const0> ;
assign doutb[558] = \<const0> ;
assign doutb[557] = \<const0> ;
assign doutb[556] = \<const0> ;
assign doutb[555] = \<const0> ;
assign doutb[554] = \<const0> ;
assign doutb[553] = \<const0> ;
assign doutb[552] = \<const0> ;
assign doutb[551] = \<const0> ;
assign doutb[550] = \<const0> ;
assign doutb[549] = \<const0> ;
assign doutb[548] = \<const0> ;
assign doutb[547] = \<const0> ;
assign doutb[546] = \<const0> ;
assign doutb[545] = \<const0> ;
assign doutb[544] = \<const0> ;
assign doutb[543] = \<const0> ;
assign doutb[542] = \<const0> ;
assign doutb[541] = \<const0> ;
assign doutb[540] = \<const0> ;
assign doutb[539] = \<const0> ;
assign doutb[538] = \<const0> ;
assign doutb[537] = \<const0> ;
assign doutb[536] = \<const0> ;
assign doutb[535] = \<const0> ;
assign doutb[534] = \<const0> ;
assign doutb[533] = \<const0> ;
assign doutb[532] = \<const0> ;
assign doutb[531] = \<const0> ;
assign doutb[530] = \<const0> ;
assign doutb[529] = \<const0> ;
assign doutb[528] = \<const0> ;
assign doutb[527] = \<const0> ;
assign doutb[526] = \<const0> ;
assign doutb[525] = \<const0> ;
assign doutb[524] = \<const0> ;
assign doutb[523] = \<const0> ;
assign doutb[522] = \<const0> ;
assign doutb[521] = \<const0> ;
assign doutb[520] = \<const0> ;
assign doutb[519] = \<const0> ;
assign doutb[518] = \<const0> ;
assign doutb[517] = \<const0> ;
assign doutb[516] = \<const0> ;
assign doutb[515] = \<const0> ;
assign doutb[514] = \<const0> ;
assign doutb[513] = \<const0> ;
assign doutb[512] = \<const0> ;
assign doutb[511] = \<const0> ;
assign doutb[510] = \<const0> ;
assign doutb[509] = \<const0> ;
assign doutb[508] = \<const0> ;
assign doutb[507] = \<const0> ;
assign doutb[506] = \<const0> ;
assign doutb[505] = \<const0> ;
assign doutb[504] = \<const0> ;
assign doutb[503] = \<const0> ;
assign doutb[502] = \<const0> ;
assign doutb[501] = \<const0> ;
assign doutb[500] = \<const0> ;
assign doutb[499] = \<const0> ;
assign doutb[498] = \<const0> ;
assign doutb[497] = \<const0> ;
assign doutb[496] = \<const0> ;
assign doutb[495] = \<const0> ;
assign doutb[494] = \<const0> ;
assign doutb[493] = \<const0> ;
assign doutb[492] = \<const0> ;
assign doutb[491] = \<const0> ;
assign doutb[490] = \<const0> ;
assign doutb[489] = \<const0> ;
assign doutb[488] = \<const0> ;
assign doutb[487] = \<const0> ;
assign doutb[486] = \<const0> ;
assign doutb[485] = \<const0> ;
assign doutb[484] = \<const0> ;
assign doutb[483] = \<const0> ;
assign doutb[482] = \<const0> ;
assign doutb[481] = \<const0> ;
assign doutb[480] = \<const0> ;
assign doutb[479] = \<const0> ;
assign doutb[478] = \<const0> ;
assign doutb[477] = \<const0> ;
assign doutb[476] = \<const0> ;
assign doutb[475] = \<const0> ;
assign doutb[474] = \<const0> ;
assign doutb[473] = \<const0> ;
assign doutb[472] = \<const0> ;
assign doutb[471] = \<const0> ;
assign doutb[470] = \<const0> ;
assign doutb[469] = \<const0> ;
assign doutb[468] = \<const0> ;
assign doutb[467] = \<const0> ;
assign doutb[466] = \<const0> ;
assign doutb[465] = \<const0> ;
assign doutb[464] = \<const0> ;
assign doutb[463] = \<const0> ;
assign doutb[462] = \<const0> ;
assign doutb[461] = \<const0> ;
assign doutb[460] = \<const0> ;
assign doutb[459] = \<const0> ;
assign doutb[458] = \<const0> ;
assign doutb[457] = \<const0> ;
assign doutb[456] = \<const0> ;
assign doutb[455] = \<const0> ;
assign doutb[454] = \<const0> ;
assign doutb[453] = \<const0> ;
assign doutb[452] = \<const0> ;
assign doutb[451] = \<const0> ;
assign doutb[450] = \<const0> ;
assign doutb[449] = \<const0> ;
assign doutb[448] = \<const0> ;
assign doutb[447] = \<const0> ;
assign doutb[446] = \<const0> ;
assign doutb[445] = \<const0> ;
assign doutb[444] = \<const0> ;
assign doutb[443] = \<const0> ;
assign doutb[442] = \<const0> ;
assign doutb[441] = \<const0> ;
assign doutb[440] = \<const0> ;
assign doutb[439] = \<const0> ;
assign doutb[438] = \<const0> ;
assign doutb[437] = \<const0> ;
assign doutb[436] = \<const0> ;
assign doutb[435] = \<const0> ;
assign doutb[434] = \<const0> ;
assign doutb[433] = \<const0> ;
assign doutb[432] = \<const0> ;
assign doutb[431] = \<const0> ;
assign doutb[430] = \<const0> ;
assign doutb[429] = \<const0> ;
assign doutb[428] = \<const0> ;
assign doutb[427] = \<const0> ;
assign doutb[426] = \<const0> ;
assign doutb[425] = \<const0> ;
assign doutb[424] = \<const0> ;
assign doutb[423] = \<const0> ;
assign doutb[422] = \<const0> ;
assign doutb[421] = \<const0> ;
assign doutb[420] = \<const0> ;
assign doutb[419] = \<const0> ;
assign doutb[418] = \<const0> ;
assign doutb[417] = \<const0> ;
assign doutb[416] = \<const0> ;
assign doutb[415] = \<const0> ;
assign doutb[414] = \<const0> ;
assign doutb[413] = \<const0> ;
assign doutb[412] = \<const0> ;
assign doutb[411] = \<const0> ;
assign doutb[410] = \<const0> ;
assign doutb[409] = \<const0> ;
assign doutb[408] = \<const0> ;
assign doutb[407] = \<const0> ;
assign doutb[406] = \<const0> ;
assign doutb[405] = \<const0> ;
assign doutb[404] = \<const0> ;
assign doutb[403] = \<const0> ;
assign doutb[402] = \<const0> ;
assign doutb[401] = \<const0> ;
assign doutb[400] = \<const0> ;
assign doutb[399] = \<const0> ;
assign doutb[398] = \<const0> ;
assign doutb[397] = \<const0> ;
assign doutb[396] = \<const0> ;
assign doutb[395] = \<const0> ;
assign doutb[394] = \<const0> ;
assign doutb[393] = \<const0> ;
assign doutb[392] = \<const0> ;
assign doutb[391] = \<const0> ;
assign doutb[390] = \<const0> ;
assign doutb[389] = \<const0> ;
assign doutb[388] = \<const0> ;
assign doutb[387] = \<const0> ;
assign doutb[386] = \<const0> ;
assign doutb[385] = \<const0> ;
assign doutb[384] = \<const0> ;
assign doutb[383] = \<const0> ;
assign doutb[382] = \<const0> ;
assign doutb[381] = \<const0> ;
assign doutb[380] = \<const0> ;
assign doutb[379] = \<const0> ;
assign doutb[378] = \<const0> ;
assign doutb[377] = \<const0> ;
assign doutb[376] = \<const0> ;
assign doutb[375] = \<const0> ;
assign doutb[374] = \<const0> ;
assign doutb[373] = \<const0> ;
assign doutb[372] = \<const0> ;
assign doutb[371] = \<const0> ;
assign doutb[370] = \<const0> ;
assign doutb[369] = \<const0> ;
assign doutb[368] = \<const0> ;
assign doutb[367] = \<const0> ;
assign doutb[366] = \<const0> ;
assign doutb[365] = \<const0> ;
assign doutb[364] = \<const0> ;
assign doutb[363] = \<const0> ;
assign doutb[362] = \<const0> ;
assign doutb[361] = \<const0> ;
assign doutb[360] = \<const0> ;
assign doutb[359] = \<const0> ;
assign doutb[358] = \<const0> ;
assign doutb[357] = \<const0> ;
assign doutb[356] = \<const0> ;
assign doutb[355] = \<const0> ;
assign doutb[354] = \<const0> ;
assign doutb[353] = \<const0> ;
assign doutb[352] = \<const0> ;
assign doutb[351] = \<const0> ;
assign doutb[350] = \<const0> ;
assign doutb[349] = \<const0> ;
assign doutb[348] = \<const0> ;
assign doutb[347] = \<const0> ;
assign doutb[346] = \<const0> ;
assign doutb[345] = \<const0> ;
assign doutb[344] = \<const0> ;
assign doutb[343] = \<const0> ;
assign doutb[342] = \<const0> ;
assign doutb[341] = \<const0> ;
assign doutb[340] = \<const0> ;
assign doutb[339] = \<const0> ;
assign doutb[338] = \<const0> ;
assign doutb[337] = \<const0> ;
assign doutb[336] = \<const0> ;
assign doutb[335] = \<const0> ;
assign doutb[334] = \<const0> ;
assign doutb[333] = \<const0> ;
assign doutb[332] = \<const0> ;
assign doutb[331] = \<const0> ;
assign doutb[330] = \<const0> ;
assign doutb[329] = \<const0> ;
assign doutb[328] = \<const0> ;
assign doutb[327] = \<const0> ;
assign doutb[326] = \<const0> ;
assign doutb[325] = \<const0> ;
assign doutb[324] = \<const0> ;
assign doutb[323] = \<const0> ;
assign doutb[322] = \<const0> ;
assign doutb[321] = \<const0> ;
assign doutb[320] = \<const0> ;
assign doutb[319] = \<const0> ;
assign doutb[318] = \<const0> ;
assign doutb[317] = \<const0> ;
assign doutb[316] = \<const0> ;
assign doutb[315] = \<const0> ;
assign doutb[314] = \<const0> ;
assign doutb[313] = \<const0> ;
assign doutb[312] = \<const0> ;
assign doutb[311] = \<const0> ;
assign doutb[310] = \<const0> ;
assign doutb[309] = \<const0> ;
assign doutb[308] = \<const0> ;
assign doutb[307] = \<const0> ;
assign doutb[306] = \<const0> ;
assign doutb[305] = \<const0> ;
assign doutb[304] = \<const0> ;
assign doutb[303] = \<const0> ;
assign doutb[302] = \<const0> ;
assign doutb[301] = \<const0> ;
assign doutb[300] = \<const0> ;
assign doutb[299] = \<const0> ;
assign doutb[298] = \<const0> ;
assign doutb[297] = \<const0> ;
assign doutb[296] = \<const0> ;
assign doutb[295] = \<const0> ;
assign doutb[294] = \<const0> ;
assign doutb[293] = \<const0> ;
assign doutb[292] = \<const0> ;
assign doutb[291] = \<const0> ;
assign doutb[290] = \<const0> ;
assign doutb[289] = \<const0> ;
assign doutb[288] = \<const0> ;
assign doutb[287] = \<const0> ;
assign doutb[286] = \<const0> ;
assign doutb[285] = \<const0> ;
assign doutb[284] = \<const0> ;
assign doutb[283] = \<const0> ;
assign doutb[282] = \<const0> ;
assign doutb[281] = \<const0> ;
assign doutb[280] = \<const0> ;
assign doutb[279] = \<const0> ;
assign doutb[278] = \<const0> ;
assign doutb[277] = \<const0> ;
assign doutb[276] = \<const0> ;
assign doutb[275] = \<const0> ;
assign doutb[274] = \<const0> ;
assign doutb[273] = \<const0> ;
assign doutb[272] = \<const0> ;
assign doutb[271] = \<const0> ;
assign doutb[270] = \<const0> ;
assign doutb[269] = \<const0> ;
assign doutb[268] = \<const0> ;
assign doutb[267] = \<const0> ;
assign doutb[266] = \<const0> ;
assign doutb[265] = \<const0> ;
assign doutb[264] = \<const0> ;
assign doutb[263] = \<const0> ;
assign doutb[262] = \<const0> ;
assign doutb[261] = \<const0> ;
assign doutb[260] = \<const0> ;
assign doutb[259] = \<const0> ;
assign doutb[258] = \<const0> ;
assign doutb[257] = \<const0> ;
assign doutb[256] = \<const0> ;
assign doutb[255] = \<const0> ;
assign doutb[254] = \<const0> ;
assign doutb[253] = \<const0> ;
assign doutb[252] = \<const0> ;
assign doutb[251] = \<const0> ;
assign doutb[250] = \<const0> ;
assign doutb[249] = \<const0> ;
assign doutb[248] = \<const0> ;
assign doutb[247] = \<const0> ;
assign doutb[246] = \<const0> ;
assign doutb[245] = \<const0> ;
assign doutb[244] = \<const0> ;
assign doutb[243] = \<const0> ;
assign doutb[242] = \<const0> ;
assign doutb[241] = \<const0> ;
assign doutb[240] = \<const0> ;
assign doutb[239] = \<const0> ;
assign doutb[238] = \<const0> ;
assign doutb[237] = \<const0> ;
assign doutb[236] = \<const0> ;
assign doutb[235] = \<const0> ;
assign doutb[234] = \<const0> ;
assign doutb[233] = \<const0> ;
assign doutb[232] = \<const0> ;
assign doutb[231] = \<const0> ;
assign doutb[230] = \<const0> ;
assign doutb[229] = \<const0> ;
assign doutb[228] = \<const0> ;
assign doutb[227] = \<const0> ;
assign doutb[226] = \<const0> ;
assign doutb[225] = \<const0> ;
assign doutb[224] = \<const0> ;
assign doutb[223] = \<const0> ;
assign doutb[222] = \<const0> ;
assign doutb[221] = \<const0> ;
assign doutb[220] = \<const0> ;
assign doutb[219] = \<const0> ;
assign doutb[218] = \<const0> ;
assign doutb[217] = \<const0> ;
assign doutb[216] = \<const0> ;
assign doutb[215] = \<const0> ;
assign doutb[214] = \<const0> ;
assign doutb[213] = \<const0> ;
assign doutb[212] = \<const0> ;
assign doutb[211] = \<const0> ;
assign doutb[210] = \<const0> ;
assign doutb[209] = \<const0> ;
assign doutb[208] = \<const0> ;
assign doutb[207] = \<const0> ;
assign doutb[206] = \<const0> ;
assign doutb[205] = \<const0> ;
assign doutb[204] = \<const0> ;
assign doutb[203] = \<const0> ;
assign doutb[202] = \<const0> ;
assign doutb[201] = \<const0> ;
assign doutb[200] = \<const0> ;
assign doutb[199] = \<const0> ;
assign doutb[198] = \<const0> ;
assign doutb[197] = \<const0> ;
assign doutb[196] = \<const0> ;
assign doutb[195] = \<const0> ;
assign doutb[194] = \<const0> ;
assign doutb[193] = \<const0> ;
assign doutb[192] = \<const0> ;
assign doutb[191] = \<const0> ;
assign doutb[190] = \<const0> ;
assign doutb[189] = \<const0> ;
assign doutb[188] = \<const0> ;
assign doutb[187] = \<const0> ;
assign doutb[186] = \<const0> ;
assign doutb[185] = \<const0> ;
assign doutb[184] = \<const0> ;
assign doutb[183] = \<const0> ;
assign doutb[182] = \<const0> ;
assign doutb[181] = \<const0> ;
assign doutb[180] = \<const0> ;
assign doutb[179] = \<const0> ;
assign doutb[178] = \<const0> ;
assign doutb[177] = \<const0> ;
assign doutb[176] = \<const0> ;
assign doutb[175] = \<const0> ;
assign doutb[174] = \<const0> ;
assign doutb[173] = \<const0> ;
assign doutb[172] = \<const0> ;
assign doutb[171] = \<const0> ;
assign doutb[170] = \<const0> ;
assign doutb[169] = \<const0> ;
assign doutb[168] = \<const0> ;
assign doutb[167] = \<const0> ;
assign doutb[166] = \<const0> ;
assign doutb[165] = \<const0> ;
assign doutb[164] = \<const0> ;
assign doutb[163] = \<const0> ;
assign doutb[162] = \<const0> ;
assign doutb[161] = \<const0> ;
assign doutb[160] = \<const0> ;
assign doutb[159] = \<const0> ;
assign doutb[158] = \<const0> ;
assign doutb[157] = \<const0> ;
assign doutb[156] = \<const0> ;
assign doutb[155] = \<const0> ;
assign doutb[154] = \<const0> ;
assign doutb[153] = \<const0> ;
assign doutb[152] = \<const0> ;
assign doutb[151] = \<const0> ;
assign doutb[150] = \<const0> ;
assign doutb[149] = \<const0> ;
assign doutb[148] = \<const0> ;
assign doutb[147] = \<const0> ;
assign doutb[146] = \<const0> ;
assign doutb[145] = \<const0> ;
assign doutb[144] = \<const0> ;
assign doutb[143] = \<const0> ;
assign doutb[142] = \<const0> ;
assign doutb[141] = \<const0> ;
assign doutb[140] = \<const0> ;
assign doutb[139] = \<const0> ;
assign doutb[138] = \<const0> ;
assign doutb[137] = \<const0> ;
assign doutb[136] = \<const0> ;
assign doutb[135] = \<const0> ;
assign doutb[134] = \<const0> ;
assign doutb[133] = \<const0> ;
assign doutb[132] = \<const0> ;
assign doutb[131] = \<const0> ;
assign doutb[130] = \<const0> ;
assign doutb[129] = \<const0> ;
assign doutb[128] = \<const0> ;
assign doutb[127] = \<const0> ;
assign doutb[126] = \<const0> ;
assign doutb[125] = \<const0> ;
assign doutb[124] = \<const0> ;
assign doutb[123] = \<const0> ;
assign doutb[122] = \<const0> ;
assign doutb[121] = \<const0> ;
assign doutb[120] = \<const0> ;
assign doutb[119] = \<const0> ;
assign doutb[118] = \<const0> ;
assign doutb[117] = \<const0> ;
assign doutb[116] = \<const0> ;
assign doutb[115] = \<const0> ;
assign doutb[114] = \<const0> ;
assign doutb[113] = \<const0> ;
assign doutb[112] = \<const0> ;
assign doutb[111] = \<const0> ;
assign doutb[110] = \<const0> ;
assign doutb[109] = \<const0> ;
assign doutb[108] = \<const0> ;
assign doutb[107] = \<const0> ;
assign doutb[106] = \<const0> ;
assign doutb[105] = \<const0> ;
assign doutb[104] = \<const0> ;
assign doutb[103] = \<const0> ;
assign doutb[102] = \<const0> ;
assign doutb[101] = \<const0> ;
assign doutb[100] = \<const0> ;
assign doutb[99] = \<const0> ;
assign doutb[98] = \<const0> ;
assign doutb[97] = \<const0> ;
assign doutb[96] = \<const0> ;
assign doutb[95] = \<const0> ;
assign doutb[94] = \<const0> ;
assign doutb[93] = \<const0> ;
assign doutb[92] = \<const0> ;
assign doutb[91] = \<const0> ;
assign doutb[90] = \<const0> ;
assign doutb[89] = \<const0> ;
assign doutb[88] = \<const0> ;
assign doutb[87] = \<const0> ;
assign doutb[86] = \<const0> ;
assign doutb[85] = \<const0> ;
assign doutb[84] = \<const0> ;
assign doutb[83] = \<const0> ;
assign doutb[82] = \<const0> ;
assign doutb[81] = \<const0> ;
assign doutb[80] = \<const0> ;
assign doutb[79] = \<const0> ;
assign doutb[78] = \<const0> ;
assign doutb[77] = \<const0> ;
assign doutb[76] = \<const0> ;
assign doutb[75] = \<const0> ;
assign doutb[74] = \<const0> ;
assign doutb[73] = \<const0> ;
assign doutb[72] = \<const0> ;
assign doutb[71] = \<const0> ;
assign doutb[70] = \<const0> ;
assign doutb[69] = \<const0> ;
assign doutb[68] = \<const0> ;
assign doutb[67] = \<const0> ;
assign doutb[66] = \<const0> ;
assign doutb[65] = \<const0> ;
assign doutb[64] = \<const0> ;
assign doutb[63] = \<const0> ;
assign doutb[62] = \<const0> ;
assign doutb[61] = \<const0> ;
assign doutb[60] = \<const0> ;
assign doutb[59] = \<const0> ;
assign doutb[58] = \<const0> ;
assign doutb[57] = \<const0> ;
assign doutb[56] = \<const0> ;
assign doutb[55] = \<const0> ;
assign doutb[54] = \<const0> ;
assign doutb[53] = \<const0> ;
assign doutb[52] = \<const0> ;
assign doutb[51] = \<const0> ;
assign doutb[50] = \<const0> ;
assign doutb[49] = \<const0> ;
assign doutb[48] = \<const0> ;
assign doutb[47] = \<const0> ;
assign doutb[46] = \<const0> ;
assign doutb[45] = \<const0> ;
assign doutb[44] = \<const0> ;
assign doutb[43] = \<const0> ;
assign doutb[42] = \<const0> ;
assign doutb[41] = \<const0> ;
assign doutb[40] = \<const0> ;
assign doutb[39] = \<const0> ;
assign doutb[38] = \<const0> ;
assign doutb[37] = \<const0> ;
assign doutb[36] = \<const0> ;
assign doutb[35] = \<const0> ;
assign doutb[34] = \<const0> ;
assign doutb[33] = \<const0> ;
assign doutb[32] = \<const0> ;
assign doutb[31] = \<const0> ;
assign doutb[30] = \<const0> ;
assign doutb[29] = \<const0> ;
assign doutb[28] = \<const0> ;
assign doutb[27] = \<const0> ;
assign doutb[26] = \<const0> ;
assign doutb[25] = \<const0> ;
assign doutb[24] = \<const0> ;
assign doutb[23] = \<const0> ;
assign doutb[22] = \<const0> ;
assign doutb[21] = \<const0> ;
assign doutb[20] = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[1599] = \<const0> ;
assign s_axi_rdata[1598] = \<const0> ;
assign s_axi_rdata[1597] = \<const0> ;
assign s_axi_rdata[1596] = \<const0> ;
assign s_axi_rdata[1595] = \<const0> ;
assign s_axi_rdata[1594] = \<const0> ;
assign s_axi_rdata[1593] = \<const0> ;
assign s_axi_rdata[1592] = \<const0> ;
assign s_axi_rdata[1591] = \<const0> ;
assign s_axi_rdata[1590] = \<const0> ;
assign s_axi_rdata[1589] = \<const0> ;
assign s_axi_rdata[1588] = \<const0> ;
assign s_axi_rdata[1587] = \<const0> ;
assign s_axi_rdata[1586] = \<const0> ;
assign s_axi_rdata[1585] = \<const0> ;
assign s_axi_rdata[1584] = \<const0> ;
assign s_axi_rdata[1583] = \<const0> ;
assign s_axi_rdata[1582] = \<const0> ;
assign s_axi_rdata[1581] = \<const0> ;
assign s_axi_rdata[1580] = \<const0> ;
assign s_axi_rdata[1579] = \<const0> ;
assign s_axi_rdata[1578] = \<const0> ;
assign s_axi_rdata[1577] = \<const0> ;
assign s_axi_rdata[1576] = \<const0> ;
assign s_axi_rdata[1575] = \<const0> ;
assign s_axi_rdata[1574] = \<const0> ;
assign s_axi_rdata[1573] = \<const0> ;
assign s_axi_rdata[1572] = \<const0> ;
assign s_axi_rdata[1571] = \<const0> ;
assign s_axi_rdata[1570] = \<const0> ;
assign s_axi_rdata[1569] = \<const0> ;
assign s_axi_rdata[1568] = \<const0> ;
assign s_axi_rdata[1567] = \<const0> ;
assign s_axi_rdata[1566] = \<const0> ;
assign s_axi_rdata[1565] = \<const0> ;
assign s_axi_rdata[1564] = \<const0> ;
assign s_axi_rdata[1563] = \<const0> ;
assign s_axi_rdata[1562] = \<const0> ;
assign s_axi_rdata[1561] = \<const0> ;
assign s_axi_rdata[1560] = \<const0> ;
assign s_axi_rdata[1559] = \<const0> ;
assign s_axi_rdata[1558] = \<const0> ;
assign s_axi_rdata[1557] = \<const0> ;
assign s_axi_rdata[1556] = \<const0> ;
assign s_axi_rdata[1555] = \<const0> ;
assign s_axi_rdata[1554] = \<const0> ;
assign s_axi_rdata[1553] = \<const0> ;
assign s_axi_rdata[1552] = \<const0> ;
assign s_axi_rdata[1551] = \<const0> ;
assign s_axi_rdata[1550] = \<const0> ;
assign s_axi_rdata[1549] = \<const0> ;
assign s_axi_rdata[1548] = \<const0> ;
assign s_axi_rdata[1547] = \<const0> ;
assign s_axi_rdata[1546] = \<const0> ;
assign s_axi_rdata[1545] = \<const0> ;
assign s_axi_rdata[1544] = \<const0> ;
assign s_axi_rdata[1543] = \<const0> ;
assign s_axi_rdata[1542] = \<const0> ;
assign s_axi_rdata[1541] = \<const0> ;
assign s_axi_rdata[1540] = \<const0> ;
assign s_axi_rdata[1539] = \<const0> ;
assign s_axi_rdata[1538] = \<const0> ;
assign s_axi_rdata[1537] = \<const0> ;
assign s_axi_rdata[1536] = \<const0> ;
assign s_axi_rdata[1535] = \<const0> ;
assign s_axi_rdata[1534] = \<const0> ;
assign s_axi_rdata[1533] = \<const0> ;
assign s_axi_rdata[1532] = \<const0> ;
assign s_axi_rdata[1531] = \<const0> ;
assign s_axi_rdata[1530] = \<const0> ;
assign s_axi_rdata[1529] = \<const0> ;
assign s_axi_rdata[1528] = \<const0> ;
assign s_axi_rdata[1527] = \<const0> ;
assign s_axi_rdata[1526] = \<const0> ;
assign s_axi_rdata[1525] = \<const0> ;
assign s_axi_rdata[1524] = \<const0> ;
assign s_axi_rdata[1523] = \<const0> ;
assign s_axi_rdata[1522] = \<const0> ;
assign s_axi_rdata[1521] = \<const0> ;
assign s_axi_rdata[1520] = \<const0> ;
assign s_axi_rdata[1519] = \<const0> ;
assign s_axi_rdata[1518] = \<const0> ;
assign s_axi_rdata[1517] = \<const0> ;
assign s_axi_rdata[1516] = \<const0> ;
assign s_axi_rdata[1515] = \<const0> ;
assign s_axi_rdata[1514] = \<const0> ;
assign s_axi_rdata[1513] = \<const0> ;
assign s_axi_rdata[1512] = \<const0> ;
assign s_axi_rdata[1511] = \<const0> ;
assign s_axi_rdata[1510] = \<const0> ;
assign s_axi_rdata[1509] = \<const0> ;
assign s_axi_rdata[1508] = \<const0> ;
assign s_axi_rdata[1507] = \<const0> ;
assign s_axi_rdata[1506] = \<const0> ;
assign s_axi_rdata[1505] = \<const0> ;
assign s_axi_rdata[1504] = \<const0> ;
assign s_axi_rdata[1503] = \<const0> ;
assign s_axi_rdata[1502] = \<const0> ;
assign s_axi_rdata[1501] = \<const0> ;
assign s_axi_rdata[1500] = \<const0> ;
assign s_axi_rdata[1499] = \<const0> ;
assign s_axi_rdata[1498] = \<const0> ;
assign s_axi_rdata[1497] = \<const0> ;
assign s_axi_rdata[1496] = \<const0> ;
assign s_axi_rdata[1495] = \<const0> ;
assign s_axi_rdata[1494] = \<const0> ;
assign s_axi_rdata[1493] = \<const0> ;
assign s_axi_rdata[1492] = \<const0> ;
assign s_axi_rdata[1491] = \<const0> ;
assign s_axi_rdata[1490] = \<const0> ;
assign s_axi_rdata[1489] = \<const0> ;
assign s_axi_rdata[1488] = \<const0> ;
assign s_axi_rdata[1487] = \<const0> ;
assign s_axi_rdata[1486] = \<const0> ;
assign s_axi_rdata[1485] = \<const0> ;
assign s_axi_rdata[1484] = \<const0> ;
assign s_axi_rdata[1483] = \<const0> ;
assign s_axi_rdata[1482] = \<const0> ;
assign s_axi_rdata[1481] = \<const0> ;
assign s_axi_rdata[1480] = \<const0> ;
assign s_axi_rdata[1479] = \<const0> ;
assign s_axi_rdata[1478] = \<const0> ;
assign s_axi_rdata[1477] = \<const0> ;
assign s_axi_rdata[1476] = \<const0> ;
assign s_axi_rdata[1475] = \<const0> ;
assign s_axi_rdata[1474] = \<const0> ;
assign s_axi_rdata[1473] = \<const0> ;
assign s_axi_rdata[1472] = \<const0> ;
assign s_axi_rdata[1471] = \<const0> ;
assign s_axi_rdata[1470] = \<const0> ;
assign s_axi_rdata[1469] = \<const0> ;
assign s_axi_rdata[1468] = \<const0> ;
assign s_axi_rdata[1467] = \<const0> ;
assign s_axi_rdata[1466] = \<const0> ;
assign s_axi_rdata[1465] = \<const0> ;
assign s_axi_rdata[1464] = \<const0> ;
assign s_axi_rdata[1463] = \<const0> ;
assign s_axi_rdata[1462] = \<const0> ;
assign s_axi_rdata[1461] = \<const0> ;
assign s_axi_rdata[1460] = \<const0> ;
assign s_axi_rdata[1459] = \<const0> ;
assign s_axi_rdata[1458] = \<const0> ;
assign s_axi_rdata[1457] = \<const0> ;
assign s_axi_rdata[1456] = \<const0> ;
assign s_axi_rdata[1455] = \<const0> ;
assign s_axi_rdata[1454] = \<const0> ;
assign s_axi_rdata[1453] = \<const0> ;
assign s_axi_rdata[1452] = \<const0> ;
assign s_axi_rdata[1451] = \<const0> ;
assign s_axi_rdata[1450] = \<const0> ;
assign s_axi_rdata[1449] = \<const0> ;
assign s_axi_rdata[1448] = \<const0> ;
assign s_axi_rdata[1447] = \<const0> ;
assign s_axi_rdata[1446] = \<const0> ;
assign s_axi_rdata[1445] = \<const0> ;
assign s_axi_rdata[1444] = \<const0> ;
assign s_axi_rdata[1443] = \<const0> ;
assign s_axi_rdata[1442] = \<const0> ;
assign s_axi_rdata[1441] = \<const0> ;
assign s_axi_rdata[1440] = \<const0> ;
assign s_axi_rdata[1439] = \<const0> ;
assign s_axi_rdata[1438] = \<const0> ;
assign s_axi_rdata[1437] = \<const0> ;
assign s_axi_rdata[1436] = \<const0> ;
assign s_axi_rdata[1435] = \<const0> ;
assign s_axi_rdata[1434] = \<const0> ;
assign s_axi_rdata[1433] = \<const0> ;
assign s_axi_rdata[1432] = \<const0> ;
assign s_axi_rdata[1431] = \<const0> ;
assign s_axi_rdata[1430] = \<const0> ;
assign s_axi_rdata[1429] = \<const0> ;
assign s_axi_rdata[1428] = \<const0> ;
assign s_axi_rdata[1427] = \<const0> ;
assign s_axi_rdata[1426] = \<const0> ;
assign s_axi_rdata[1425] = \<const0> ;
assign s_axi_rdata[1424] = \<const0> ;
assign s_axi_rdata[1423] = \<const0> ;
assign s_axi_rdata[1422] = \<const0> ;
assign s_axi_rdata[1421] = \<const0> ;
assign s_axi_rdata[1420] = \<const0> ;
assign s_axi_rdata[1419] = \<const0> ;
assign s_axi_rdata[1418] = \<const0> ;
assign s_axi_rdata[1417] = \<const0> ;
assign s_axi_rdata[1416] = \<const0> ;
assign s_axi_rdata[1415] = \<const0> ;
assign s_axi_rdata[1414] = \<const0> ;
assign s_axi_rdata[1413] = \<const0> ;
assign s_axi_rdata[1412] = \<const0> ;
assign s_axi_rdata[1411] = \<const0> ;
assign s_axi_rdata[1410] = \<const0> ;
assign s_axi_rdata[1409] = \<const0> ;
assign s_axi_rdata[1408] = \<const0> ;
assign s_axi_rdata[1407] = \<const0> ;
assign s_axi_rdata[1406] = \<const0> ;
assign s_axi_rdata[1405] = \<const0> ;
assign s_axi_rdata[1404] = \<const0> ;
assign s_axi_rdata[1403] = \<const0> ;
assign s_axi_rdata[1402] = \<const0> ;
assign s_axi_rdata[1401] = \<const0> ;
assign s_axi_rdata[1400] = \<const0> ;
assign s_axi_rdata[1399] = \<const0> ;
assign s_axi_rdata[1398] = \<const0> ;
assign s_axi_rdata[1397] = \<const0> ;
assign s_axi_rdata[1396] = \<const0> ;
assign s_axi_rdata[1395] = \<const0> ;
assign s_axi_rdata[1394] = \<const0> ;
assign s_axi_rdata[1393] = \<const0> ;
assign s_axi_rdata[1392] = \<const0> ;
assign s_axi_rdata[1391] = \<const0> ;
assign s_axi_rdata[1390] = \<const0> ;
assign s_axi_rdata[1389] = \<const0> ;
assign s_axi_rdata[1388] = \<const0> ;
assign s_axi_rdata[1387] = \<const0> ;
assign s_axi_rdata[1386] = \<const0> ;
assign s_axi_rdata[1385] = \<const0> ;
assign s_axi_rdata[1384] = \<const0> ;
assign s_axi_rdata[1383] = \<const0> ;
assign s_axi_rdata[1382] = \<const0> ;
assign s_axi_rdata[1381] = \<const0> ;
assign s_axi_rdata[1380] = \<const0> ;
assign s_axi_rdata[1379] = \<const0> ;
assign s_axi_rdata[1378] = \<const0> ;
assign s_axi_rdata[1377] = \<const0> ;
assign s_axi_rdata[1376] = \<const0> ;
assign s_axi_rdata[1375] = \<const0> ;
assign s_axi_rdata[1374] = \<const0> ;
assign s_axi_rdata[1373] = \<const0> ;
assign s_axi_rdata[1372] = \<const0> ;
assign s_axi_rdata[1371] = \<const0> ;
assign s_axi_rdata[1370] = \<const0> ;
assign s_axi_rdata[1369] = \<const0> ;
assign s_axi_rdata[1368] = \<const0> ;
assign s_axi_rdata[1367] = \<const0> ;
assign s_axi_rdata[1366] = \<const0> ;
assign s_axi_rdata[1365] = \<const0> ;
assign s_axi_rdata[1364] = \<const0> ;
assign s_axi_rdata[1363] = \<const0> ;
assign s_axi_rdata[1362] = \<const0> ;
assign s_axi_rdata[1361] = \<const0> ;
assign s_axi_rdata[1360] = \<const0> ;
assign s_axi_rdata[1359] = \<const0> ;
assign s_axi_rdata[1358] = \<const0> ;
assign s_axi_rdata[1357] = \<const0> ;
assign s_axi_rdata[1356] = \<const0> ;
assign s_axi_rdata[1355] = \<const0> ;
assign s_axi_rdata[1354] = \<const0> ;
assign s_axi_rdata[1353] = \<const0> ;
assign s_axi_rdata[1352] = \<const0> ;
assign s_axi_rdata[1351] = \<const0> ;
assign s_axi_rdata[1350] = \<const0> ;
assign s_axi_rdata[1349] = \<const0> ;
assign s_axi_rdata[1348] = \<const0> ;
assign s_axi_rdata[1347] = \<const0> ;
assign s_axi_rdata[1346] = \<const0> ;
assign s_axi_rdata[1345] = \<const0> ;
assign s_axi_rdata[1344] = \<const0> ;
assign s_axi_rdata[1343] = \<const0> ;
assign s_axi_rdata[1342] = \<const0> ;
assign s_axi_rdata[1341] = \<const0> ;
assign s_axi_rdata[1340] = \<const0> ;
assign s_axi_rdata[1339] = \<const0> ;
assign s_axi_rdata[1338] = \<const0> ;
assign s_axi_rdata[1337] = \<const0> ;
assign s_axi_rdata[1336] = \<const0> ;
assign s_axi_rdata[1335] = \<const0> ;
assign s_axi_rdata[1334] = \<const0> ;
assign s_axi_rdata[1333] = \<const0> ;
assign s_axi_rdata[1332] = \<const0> ;
assign s_axi_rdata[1331] = \<const0> ;
assign s_axi_rdata[1330] = \<const0> ;
assign s_axi_rdata[1329] = \<const0> ;
assign s_axi_rdata[1328] = \<const0> ;
assign s_axi_rdata[1327] = \<const0> ;
assign s_axi_rdata[1326] = \<const0> ;
assign s_axi_rdata[1325] = \<const0> ;
assign s_axi_rdata[1324] = \<const0> ;
assign s_axi_rdata[1323] = \<const0> ;
assign s_axi_rdata[1322] = \<const0> ;
assign s_axi_rdata[1321] = \<const0> ;
assign s_axi_rdata[1320] = \<const0> ;
assign s_axi_rdata[1319] = \<const0> ;
assign s_axi_rdata[1318] = \<const0> ;
assign s_axi_rdata[1317] = \<const0> ;
assign s_axi_rdata[1316] = \<const0> ;
assign s_axi_rdata[1315] = \<const0> ;
assign s_axi_rdata[1314] = \<const0> ;
assign s_axi_rdata[1313] = \<const0> ;
assign s_axi_rdata[1312] = \<const0> ;
assign s_axi_rdata[1311] = \<const0> ;
assign s_axi_rdata[1310] = \<const0> ;
assign s_axi_rdata[1309] = \<const0> ;
assign s_axi_rdata[1308] = \<const0> ;
assign s_axi_rdata[1307] = \<const0> ;
assign s_axi_rdata[1306] = \<const0> ;
assign s_axi_rdata[1305] = \<const0> ;
assign s_axi_rdata[1304] = \<const0> ;
assign s_axi_rdata[1303] = \<const0> ;
assign s_axi_rdata[1302] = \<const0> ;
assign s_axi_rdata[1301] = \<const0> ;
assign s_axi_rdata[1300] = \<const0> ;
assign s_axi_rdata[1299] = \<const0> ;
assign s_axi_rdata[1298] = \<const0> ;
assign s_axi_rdata[1297] = \<const0> ;
assign s_axi_rdata[1296] = \<const0> ;
assign s_axi_rdata[1295] = \<const0> ;
assign s_axi_rdata[1294] = \<const0> ;
assign s_axi_rdata[1293] = \<const0> ;
assign s_axi_rdata[1292] = \<const0> ;
assign s_axi_rdata[1291] = \<const0> ;
assign s_axi_rdata[1290] = \<const0> ;
assign s_axi_rdata[1289] = \<const0> ;
assign s_axi_rdata[1288] = \<const0> ;
assign s_axi_rdata[1287] = \<const0> ;
assign s_axi_rdata[1286] = \<const0> ;
assign s_axi_rdata[1285] = \<const0> ;
assign s_axi_rdata[1284] = \<const0> ;
assign s_axi_rdata[1283] = \<const0> ;
assign s_axi_rdata[1282] = \<const0> ;
assign s_axi_rdata[1281] = \<const0> ;
assign s_axi_rdata[1280] = \<const0> ;
assign s_axi_rdata[1279] = \<const0> ;
assign s_axi_rdata[1278] = \<const0> ;
assign s_axi_rdata[1277] = \<const0> ;
assign s_axi_rdata[1276] = \<const0> ;
assign s_axi_rdata[1275] = \<const0> ;
assign s_axi_rdata[1274] = \<const0> ;
assign s_axi_rdata[1273] = \<const0> ;
assign s_axi_rdata[1272] = \<const0> ;
assign s_axi_rdata[1271] = \<const0> ;
assign s_axi_rdata[1270] = \<const0> ;
assign s_axi_rdata[1269] = \<const0> ;
assign s_axi_rdata[1268] = \<const0> ;
assign s_axi_rdata[1267] = \<const0> ;
assign s_axi_rdata[1266] = \<const0> ;
assign s_axi_rdata[1265] = \<const0> ;
assign s_axi_rdata[1264] = \<const0> ;
assign s_axi_rdata[1263] = \<const0> ;
assign s_axi_rdata[1262] = \<const0> ;
assign s_axi_rdata[1261] = \<const0> ;
assign s_axi_rdata[1260] = \<const0> ;
assign s_axi_rdata[1259] = \<const0> ;
assign s_axi_rdata[1258] = \<const0> ;
assign s_axi_rdata[1257] = \<const0> ;
assign s_axi_rdata[1256] = \<const0> ;
assign s_axi_rdata[1255] = \<const0> ;
assign s_axi_rdata[1254] = \<const0> ;
assign s_axi_rdata[1253] = \<const0> ;
assign s_axi_rdata[1252] = \<const0> ;
assign s_axi_rdata[1251] = \<const0> ;
assign s_axi_rdata[1250] = \<const0> ;
assign s_axi_rdata[1249] = \<const0> ;
assign s_axi_rdata[1248] = \<const0> ;
assign s_axi_rdata[1247] = \<const0> ;
assign s_axi_rdata[1246] = \<const0> ;
assign s_axi_rdata[1245] = \<const0> ;
assign s_axi_rdata[1244] = \<const0> ;
assign s_axi_rdata[1243] = \<const0> ;
assign s_axi_rdata[1242] = \<const0> ;
assign s_axi_rdata[1241] = \<const0> ;
assign s_axi_rdata[1240] = \<const0> ;
assign s_axi_rdata[1239] = \<const0> ;
assign s_axi_rdata[1238] = \<const0> ;
assign s_axi_rdata[1237] = \<const0> ;
assign s_axi_rdata[1236] = \<const0> ;
assign s_axi_rdata[1235] = \<const0> ;
assign s_axi_rdata[1234] = \<const0> ;
assign s_axi_rdata[1233] = \<const0> ;
assign s_axi_rdata[1232] = \<const0> ;
assign s_axi_rdata[1231] = \<const0> ;
assign s_axi_rdata[1230] = \<const0> ;
assign s_axi_rdata[1229] = \<const0> ;
assign s_axi_rdata[1228] = \<const0> ;
assign s_axi_rdata[1227] = \<const0> ;
assign s_axi_rdata[1226] = \<const0> ;
assign s_axi_rdata[1225] = \<const0> ;
assign s_axi_rdata[1224] = \<const0> ;
assign s_axi_rdata[1223] = \<const0> ;
assign s_axi_rdata[1222] = \<const0> ;
assign s_axi_rdata[1221] = \<const0> ;
assign s_axi_rdata[1220] = \<const0> ;
assign s_axi_rdata[1219] = \<const0> ;
assign s_axi_rdata[1218] = \<const0> ;
assign s_axi_rdata[1217] = \<const0> ;
assign s_axi_rdata[1216] = \<const0> ;
assign s_axi_rdata[1215] = \<const0> ;
assign s_axi_rdata[1214] = \<const0> ;
assign s_axi_rdata[1213] = \<const0> ;
assign s_axi_rdata[1212] = \<const0> ;
assign s_axi_rdata[1211] = \<const0> ;
assign s_axi_rdata[1210] = \<const0> ;
assign s_axi_rdata[1209] = \<const0> ;
assign s_axi_rdata[1208] = \<const0> ;
assign s_axi_rdata[1207] = \<const0> ;
assign s_axi_rdata[1206] = \<const0> ;
assign s_axi_rdata[1205] = \<const0> ;
assign s_axi_rdata[1204] = \<const0> ;
assign s_axi_rdata[1203] = \<const0> ;
assign s_axi_rdata[1202] = \<const0> ;
assign s_axi_rdata[1201] = \<const0> ;
assign s_axi_rdata[1200] = \<const0> ;
assign s_axi_rdata[1199] = \<const0> ;
assign s_axi_rdata[1198] = \<const0> ;
assign s_axi_rdata[1197] = \<const0> ;
assign s_axi_rdata[1196] = \<const0> ;
assign s_axi_rdata[1195] = \<const0> ;
assign s_axi_rdata[1194] = \<const0> ;
assign s_axi_rdata[1193] = \<const0> ;
assign s_axi_rdata[1192] = \<const0> ;
assign s_axi_rdata[1191] = \<const0> ;
assign s_axi_rdata[1190] = \<const0> ;
assign s_axi_rdata[1189] = \<const0> ;
assign s_axi_rdata[1188] = \<const0> ;
assign s_axi_rdata[1187] = \<const0> ;
assign s_axi_rdata[1186] = \<const0> ;
assign s_axi_rdata[1185] = \<const0> ;
assign s_axi_rdata[1184] = \<const0> ;
assign s_axi_rdata[1183] = \<const0> ;
assign s_axi_rdata[1182] = \<const0> ;
assign s_axi_rdata[1181] = \<const0> ;
assign s_axi_rdata[1180] = \<const0> ;
assign s_axi_rdata[1179] = \<const0> ;
assign s_axi_rdata[1178] = \<const0> ;
assign s_axi_rdata[1177] = \<const0> ;
assign s_axi_rdata[1176] = \<const0> ;
assign s_axi_rdata[1175] = \<const0> ;
assign s_axi_rdata[1174] = \<const0> ;
assign s_axi_rdata[1173] = \<const0> ;
assign s_axi_rdata[1172] = \<const0> ;
assign s_axi_rdata[1171] = \<const0> ;
assign s_axi_rdata[1170] = \<const0> ;
assign s_axi_rdata[1169] = \<const0> ;
assign s_axi_rdata[1168] = \<const0> ;
assign s_axi_rdata[1167] = \<const0> ;
assign s_axi_rdata[1166] = \<const0> ;
assign s_axi_rdata[1165] = \<const0> ;
assign s_axi_rdata[1164] = \<const0> ;
assign s_axi_rdata[1163] = \<const0> ;
assign s_axi_rdata[1162] = \<const0> ;
assign s_axi_rdata[1161] = \<const0> ;
assign s_axi_rdata[1160] = \<const0> ;
assign s_axi_rdata[1159] = \<const0> ;
assign s_axi_rdata[1158] = \<const0> ;
assign s_axi_rdata[1157] = \<const0> ;
assign s_axi_rdata[1156] = \<const0> ;
assign s_axi_rdata[1155] = \<const0> ;
assign s_axi_rdata[1154] = \<const0> ;
assign s_axi_rdata[1153] = \<const0> ;
assign s_axi_rdata[1152] = \<const0> ;
assign s_axi_rdata[1151] = \<const0> ;
assign s_axi_rdata[1150] = \<const0> ;
assign s_axi_rdata[1149] = \<const0> ;
assign s_axi_rdata[1148] = \<const0> ;
assign s_axi_rdata[1147] = \<const0> ;
assign s_axi_rdata[1146] = \<const0> ;
assign s_axi_rdata[1145] = \<const0> ;
assign s_axi_rdata[1144] = \<const0> ;
assign s_axi_rdata[1143] = \<const0> ;
assign s_axi_rdata[1142] = \<const0> ;
assign s_axi_rdata[1141] = \<const0> ;
assign s_axi_rdata[1140] = \<const0> ;
assign s_axi_rdata[1139] = \<const0> ;
assign s_axi_rdata[1138] = \<const0> ;
assign s_axi_rdata[1137] = \<const0> ;
assign s_axi_rdata[1136] = \<const0> ;
assign s_axi_rdata[1135] = \<const0> ;
assign s_axi_rdata[1134] = \<const0> ;
assign s_axi_rdata[1133] = \<const0> ;
assign s_axi_rdata[1132] = \<const0> ;
assign s_axi_rdata[1131] = \<const0> ;
assign s_axi_rdata[1130] = \<const0> ;
assign s_axi_rdata[1129] = \<const0> ;
assign s_axi_rdata[1128] = \<const0> ;
assign s_axi_rdata[1127] = \<const0> ;
assign s_axi_rdata[1126] = \<const0> ;
assign s_axi_rdata[1125] = \<const0> ;
assign s_axi_rdata[1124] = \<const0> ;
assign s_axi_rdata[1123] = \<const0> ;
assign s_axi_rdata[1122] = \<const0> ;
assign s_axi_rdata[1121] = \<const0> ;
assign s_axi_rdata[1120] = \<const0> ;
assign s_axi_rdata[1119] = \<const0> ;
assign s_axi_rdata[1118] = \<const0> ;
assign s_axi_rdata[1117] = \<const0> ;
assign s_axi_rdata[1116] = \<const0> ;
assign s_axi_rdata[1115] = \<const0> ;
assign s_axi_rdata[1114] = \<const0> ;
assign s_axi_rdata[1113] = \<const0> ;
assign s_axi_rdata[1112] = \<const0> ;
assign s_axi_rdata[1111] = \<const0> ;
assign s_axi_rdata[1110] = \<const0> ;
assign s_axi_rdata[1109] = \<const0> ;
assign s_axi_rdata[1108] = \<const0> ;
assign s_axi_rdata[1107] = \<const0> ;
assign s_axi_rdata[1106] = \<const0> ;
assign s_axi_rdata[1105] = \<const0> ;
assign s_axi_rdata[1104] = \<const0> ;
assign s_axi_rdata[1103] = \<const0> ;
assign s_axi_rdata[1102] = \<const0> ;
assign s_axi_rdata[1101] = \<const0> ;
assign s_axi_rdata[1100] = \<const0> ;
assign s_axi_rdata[1099] = \<const0> ;
assign s_axi_rdata[1098] = \<const0> ;
assign s_axi_rdata[1097] = \<const0> ;
assign s_axi_rdata[1096] = \<const0> ;
assign s_axi_rdata[1095] = \<const0> ;
assign s_axi_rdata[1094] = \<const0> ;
assign s_axi_rdata[1093] = \<const0> ;
assign s_axi_rdata[1092] = \<const0> ;
assign s_axi_rdata[1091] = \<const0> ;
assign s_axi_rdata[1090] = \<const0> ;
assign s_axi_rdata[1089] = \<const0> ;
assign s_axi_rdata[1088] = \<const0> ;
assign s_axi_rdata[1087] = \<const0> ;
assign s_axi_rdata[1086] = \<const0> ;
assign s_axi_rdata[1085] = \<const0> ;
assign s_axi_rdata[1084] = \<const0> ;
assign s_axi_rdata[1083] = \<const0> ;
assign s_axi_rdata[1082] = \<const0> ;
assign s_axi_rdata[1081] = \<const0> ;
assign s_axi_rdata[1080] = \<const0> ;
assign s_axi_rdata[1079] = \<const0> ;
assign s_axi_rdata[1078] = \<const0> ;
assign s_axi_rdata[1077] = \<const0> ;
assign s_axi_rdata[1076] = \<const0> ;
assign s_axi_rdata[1075] = \<const0> ;
assign s_axi_rdata[1074] = \<const0> ;
assign s_axi_rdata[1073] = \<const0> ;
assign s_axi_rdata[1072] = \<const0> ;
assign s_axi_rdata[1071] = \<const0> ;
assign s_axi_rdata[1070] = \<const0> ;
assign s_axi_rdata[1069] = \<const0> ;
assign s_axi_rdata[1068] = \<const0> ;
assign s_axi_rdata[1067] = \<const0> ;
assign s_axi_rdata[1066] = \<const0> ;
assign s_axi_rdata[1065] = \<const0> ;
assign s_axi_rdata[1064] = \<const0> ;
assign s_axi_rdata[1063] = \<const0> ;
assign s_axi_rdata[1062] = \<const0> ;
assign s_axi_rdata[1061] = \<const0> ;
assign s_axi_rdata[1060] = \<const0> ;
assign s_axi_rdata[1059] = \<const0> ;
assign s_axi_rdata[1058] = \<const0> ;
assign s_axi_rdata[1057] = \<const0> ;
assign s_axi_rdata[1056] = \<const0> ;
assign s_axi_rdata[1055] = \<const0> ;
assign s_axi_rdata[1054] = \<const0> ;
assign s_axi_rdata[1053] = \<const0> ;
assign s_axi_rdata[1052] = \<const0> ;
assign s_axi_rdata[1051] = \<const0> ;
assign s_axi_rdata[1050] = \<const0> ;
assign s_axi_rdata[1049] = \<const0> ;
assign s_axi_rdata[1048] = \<const0> ;
assign s_axi_rdata[1047] = \<const0> ;
assign s_axi_rdata[1046] = \<const0> ;
assign s_axi_rdata[1045] = \<const0> ;
assign s_axi_rdata[1044] = \<const0> ;
assign s_axi_rdata[1043] = \<const0> ;
assign s_axi_rdata[1042] = \<const0> ;
assign s_axi_rdata[1041] = \<const0> ;
assign s_axi_rdata[1040] = \<const0> ;
assign s_axi_rdata[1039] = \<const0> ;
assign s_axi_rdata[1038] = \<const0> ;
assign s_axi_rdata[1037] = \<const0> ;
assign s_axi_rdata[1036] = \<const0> ;
assign s_axi_rdata[1035] = \<const0> ;
assign s_axi_rdata[1034] = \<const0> ;
assign s_axi_rdata[1033] = \<const0> ;
assign s_axi_rdata[1032] = \<const0> ;
assign s_axi_rdata[1031] = \<const0> ;
assign s_axi_rdata[1030] = \<const0> ;
assign s_axi_rdata[1029] = \<const0> ;
assign s_axi_rdata[1028] = \<const0> ;
assign s_axi_rdata[1027] = \<const0> ;
assign s_axi_rdata[1026] = \<const0> ;
assign s_axi_rdata[1025] = \<const0> ;
assign s_axi_rdata[1024] = \<const0> ;
assign s_axi_rdata[1023] = \<const0> ;
assign s_axi_rdata[1022] = \<const0> ;
assign s_axi_rdata[1021] = \<const0> ;
assign s_axi_rdata[1020] = \<const0> ;
assign s_axi_rdata[1019] = \<const0> ;
assign s_axi_rdata[1018] = \<const0> ;
assign s_axi_rdata[1017] = \<const0> ;
assign s_axi_rdata[1016] = \<const0> ;
assign s_axi_rdata[1015] = \<const0> ;
assign s_axi_rdata[1014] = \<const0> ;
assign s_axi_rdata[1013] = \<const0> ;
assign s_axi_rdata[1012] = \<const0> ;
assign s_axi_rdata[1011] = \<const0> ;
assign s_axi_rdata[1010] = \<const0> ;
assign s_axi_rdata[1009] = \<const0> ;
assign s_axi_rdata[1008] = \<const0> ;
assign s_axi_rdata[1007] = \<const0> ;
assign s_axi_rdata[1006] = \<const0> ;
assign s_axi_rdata[1005] = \<const0> ;
assign s_axi_rdata[1004] = \<const0> ;
assign s_axi_rdata[1003] = \<const0> ;
assign s_axi_rdata[1002] = \<const0> ;
assign s_axi_rdata[1001] = \<const0> ;
assign s_axi_rdata[1000] = \<const0> ;
assign s_axi_rdata[999] = \<const0> ;
assign s_axi_rdata[998] = \<const0> ;
assign s_axi_rdata[997] = \<const0> ;
assign s_axi_rdata[996] = \<const0> ;
assign s_axi_rdata[995] = \<const0> ;
assign s_axi_rdata[994] = \<const0> ;
assign s_axi_rdata[993] = \<const0> ;
assign s_axi_rdata[992] = \<const0> ;
assign s_axi_rdata[991] = \<const0> ;
assign s_axi_rdata[990] = \<const0> ;
assign s_axi_rdata[989] = \<const0> ;
assign s_axi_rdata[988] = \<const0> ;
assign s_axi_rdata[987] = \<const0> ;
assign s_axi_rdata[986] = \<const0> ;
assign s_axi_rdata[985] = \<const0> ;
assign s_axi_rdata[984] = \<const0> ;
assign s_axi_rdata[983] = \<const0> ;
assign s_axi_rdata[982] = \<const0> ;
assign s_axi_rdata[981] = \<const0> ;
assign s_axi_rdata[980] = \<const0> ;
assign s_axi_rdata[979] = \<const0> ;
assign s_axi_rdata[978] = \<const0> ;
assign s_axi_rdata[977] = \<const0> ;
assign s_axi_rdata[976] = \<const0> ;
assign s_axi_rdata[975] = \<const0> ;
assign s_axi_rdata[974] = \<const0> ;
assign s_axi_rdata[973] = \<const0> ;
assign s_axi_rdata[972] = \<const0> ;
assign s_axi_rdata[971] = \<const0> ;
assign s_axi_rdata[970] = \<const0> ;
assign s_axi_rdata[969] = \<const0> ;
assign s_axi_rdata[968] = \<const0> ;
assign s_axi_rdata[967] = \<const0> ;
assign s_axi_rdata[966] = \<const0> ;
assign s_axi_rdata[965] = \<const0> ;
assign s_axi_rdata[964] = \<const0> ;
assign s_axi_rdata[963] = \<const0> ;
assign s_axi_rdata[962] = \<const0> ;
assign s_axi_rdata[961] = \<const0> ;
assign s_axi_rdata[960] = \<const0> ;
assign s_axi_rdata[959] = \<const0> ;
assign s_axi_rdata[958] = \<const0> ;
assign s_axi_rdata[957] = \<const0> ;
assign s_axi_rdata[956] = \<const0> ;
assign s_axi_rdata[955] = \<const0> ;
assign s_axi_rdata[954] = \<const0> ;
assign s_axi_rdata[953] = \<const0> ;
assign s_axi_rdata[952] = \<const0> ;
assign s_axi_rdata[951] = \<const0> ;
assign s_axi_rdata[950] = \<const0> ;
assign s_axi_rdata[949] = \<const0> ;
assign s_axi_rdata[948] = \<const0> ;
assign s_axi_rdata[947] = \<const0> ;
assign s_axi_rdata[946] = \<const0> ;
assign s_axi_rdata[945] = \<const0> ;
assign s_axi_rdata[944] = \<const0> ;
assign s_axi_rdata[943] = \<const0> ;
assign s_axi_rdata[942] = \<const0> ;
assign s_axi_rdata[941] = \<const0> ;
assign s_axi_rdata[940] = \<const0> ;
assign s_axi_rdata[939] = \<const0> ;
assign s_axi_rdata[938] = \<const0> ;
assign s_axi_rdata[937] = \<const0> ;
assign s_axi_rdata[936] = \<const0> ;
assign s_axi_rdata[935] = \<const0> ;
assign s_axi_rdata[934] = \<const0> ;
assign s_axi_rdata[933] = \<const0> ;
assign s_axi_rdata[932] = \<const0> ;
assign s_axi_rdata[931] = \<const0> ;
assign s_axi_rdata[930] = \<const0> ;
assign s_axi_rdata[929] = \<const0> ;
assign s_axi_rdata[928] = \<const0> ;
assign s_axi_rdata[927] = \<const0> ;
assign s_axi_rdata[926] = \<const0> ;
assign s_axi_rdata[925] = \<const0> ;
assign s_axi_rdata[924] = \<const0> ;
assign s_axi_rdata[923] = \<const0> ;
assign s_axi_rdata[922] = \<const0> ;
assign s_axi_rdata[921] = \<const0> ;
assign s_axi_rdata[920] = \<const0> ;
assign s_axi_rdata[919] = \<const0> ;
assign s_axi_rdata[918] = \<const0> ;
assign s_axi_rdata[917] = \<const0> ;
assign s_axi_rdata[916] = \<const0> ;
assign s_axi_rdata[915] = \<const0> ;
assign s_axi_rdata[914] = \<const0> ;
assign s_axi_rdata[913] = \<const0> ;
assign s_axi_rdata[912] = \<const0> ;
assign s_axi_rdata[911] = \<const0> ;
assign s_axi_rdata[910] = \<const0> ;
assign s_axi_rdata[909] = \<const0> ;
assign s_axi_rdata[908] = \<const0> ;
assign s_axi_rdata[907] = \<const0> ;
assign s_axi_rdata[906] = \<const0> ;
assign s_axi_rdata[905] = \<const0> ;
assign s_axi_rdata[904] = \<const0> ;
assign s_axi_rdata[903] = \<const0> ;
assign s_axi_rdata[902] = \<const0> ;
assign s_axi_rdata[901] = \<const0> ;
assign s_axi_rdata[900] = \<const0> ;
assign s_axi_rdata[899] = \<const0> ;
assign s_axi_rdata[898] = \<const0> ;
assign s_axi_rdata[897] = \<const0> ;
assign s_axi_rdata[896] = \<const0> ;
assign s_axi_rdata[895] = \<const0> ;
assign s_axi_rdata[894] = \<const0> ;
assign s_axi_rdata[893] = \<const0> ;
assign s_axi_rdata[892] = \<const0> ;
assign s_axi_rdata[891] = \<const0> ;
assign s_axi_rdata[890] = \<const0> ;
assign s_axi_rdata[889] = \<const0> ;
assign s_axi_rdata[888] = \<const0> ;
assign s_axi_rdata[887] = \<const0> ;
assign s_axi_rdata[886] = \<const0> ;
assign s_axi_rdata[885] = \<const0> ;
assign s_axi_rdata[884] = \<const0> ;
assign s_axi_rdata[883] = \<const0> ;
assign s_axi_rdata[882] = \<const0> ;
assign s_axi_rdata[881] = \<const0> ;
assign s_axi_rdata[880] = \<const0> ;
assign s_axi_rdata[879] = \<const0> ;
assign s_axi_rdata[878] = \<const0> ;
assign s_axi_rdata[877] = \<const0> ;
assign s_axi_rdata[876] = \<const0> ;
assign s_axi_rdata[875] = \<const0> ;
assign s_axi_rdata[874] = \<const0> ;
assign s_axi_rdata[873] = \<const0> ;
assign s_axi_rdata[872] = \<const0> ;
assign s_axi_rdata[871] = \<const0> ;
assign s_axi_rdata[870] = \<const0> ;
assign s_axi_rdata[869] = \<const0> ;
assign s_axi_rdata[868] = \<const0> ;
assign s_axi_rdata[867] = \<const0> ;
assign s_axi_rdata[866] = \<const0> ;
assign s_axi_rdata[865] = \<const0> ;
assign s_axi_rdata[864] = \<const0> ;
assign s_axi_rdata[863] = \<const0> ;
assign s_axi_rdata[862] = \<const0> ;
assign s_axi_rdata[861] = \<const0> ;
assign s_axi_rdata[860] = \<const0> ;
assign s_axi_rdata[859] = \<const0> ;
assign s_axi_rdata[858] = \<const0> ;
assign s_axi_rdata[857] = \<const0> ;
assign s_axi_rdata[856] = \<const0> ;
assign s_axi_rdata[855] = \<const0> ;
assign s_axi_rdata[854] = \<const0> ;
assign s_axi_rdata[853] = \<const0> ;
assign s_axi_rdata[852] = \<const0> ;
assign s_axi_rdata[851] = \<const0> ;
assign s_axi_rdata[850] = \<const0> ;
assign s_axi_rdata[849] = \<const0> ;
assign s_axi_rdata[848] = \<const0> ;
assign s_axi_rdata[847] = \<const0> ;
assign s_axi_rdata[846] = \<const0> ;
assign s_axi_rdata[845] = \<const0> ;
assign s_axi_rdata[844] = \<const0> ;
assign s_axi_rdata[843] = \<const0> ;
assign s_axi_rdata[842] = \<const0> ;
assign s_axi_rdata[841] = \<const0> ;
assign s_axi_rdata[840] = \<const0> ;
assign s_axi_rdata[839] = \<const0> ;
assign s_axi_rdata[838] = \<const0> ;
assign s_axi_rdata[837] = \<const0> ;
assign s_axi_rdata[836] = \<const0> ;
assign s_axi_rdata[835] = \<const0> ;
assign s_axi_rdata[834] = \<const0> ;
assign s_axi_rdata[833] = \<const0> ;
assign s_axi_rdata[832] = \<const0> ;
assign s_axi_rdata[831] = \<const0> ;
assign s_axi_rdata[830] = \<const0> ;
assign s_axi_rdata[829] = \<const0> ;
assign s_axi_rdata[828] = \<const0> ;
assign s_axi_rdata[827] = \<const0> ;
assign s_axi_rdata[826] = \<const0> ;
assign s_axi_rdata[825] = \<const0> ;
assign s_axi_rdata[824] = \<const0> ;
assign s_axi_rdata[823] = \<const0> ;
assign s_axi_rdata[822] = \<const0> ;
assign s_axi_rdata[821] = \<const0> ;
assign s_axi_rdata[820] = \<const0> ;
assign s_axi_rdata[819] = \<const0> ;
assign s_axi_rdata[818] = \<const0> ;
assign s_axi_rdata[817] = \<const0> ;
assign s_axi_rdata[816] = \<const0> ;
assign s_axi_rdata[815] = \<const0> ;
assign s_axi_rdata[814] = \<const0> ;
assign s_axi_rdata[813] = \<const0> ;
assign s_axi_rdata[812] = \<const0> ;
assign s_axi_rdata[811] = \<const0> ;
assign s_axi_rdata[810] = \<const0> ;
assign s_axi_rdata[809] = \<const0> ;
assign s_axi_rdata[808] = \<const0> ;
assign s_axi_rdata[807] = \<const0> ;
assign s_axi_rdata[806] = \<const0> ;
assign s_axi_rdata[805] = \<const0> ;
assign s_axi_rdata[804] = \<const0> ;
assign s_axi_rdata[803] = \<const0> ;
assign s_axi_rdata[802] = \<const0> ;
assign s_axi_rdata[801] = \<const0> ;
assign s_axi_rdata[800] = \<const0> ;
assign s_axi_rdata[799] = \<const0> ;
assign s_axi_rdata[798] = \<const0> ;
assign s_axi_rdata[797] = \<const0> ;
assign s_axi_rdata[796] = \<const0> ;
assign s_axi_rdata[795] = \<const0> ;
assign s_axi_rdata[794] = \<const0> ;
assign s_axi_rdata[793] = \<const0> ;
assign s_axi_rdata[792] = \<const0> ;
assign s_axi_rdata[791] = \<const0> ;
assign s_axi_rdata[790] = \<const0> ;
assign s_axi_rdata[789] = \<const0> ;
assign s_axi_rdata[788] = \<const0> ;
assign s_axi_rdata[787] = \<const0> ;
assign s_axi_rdata[786] = \<const0> ;
assign s_axi_rdata[785] = \<const0> ;
assign s_axi_rdata[784] = \<const0> ;
assign s_axi_rdata[783] = \<const0> ;
assign s_axi_rdata[782] = \<const0> ;
assign s_axi_rdata[781] = \<const0> ;
assign s_axi_rdata[780] = \<const0> ;
assign s_axi_rdata[779] = \<const0> ;
assign s_axi_rdata[778] = \<const0> ;
assign s_axi_rdata[777] = \<const0> ;
assign s_axi_rdata[776] = \<const0> ;
assign s_axi_rdata[775] = \<const0> ;
assign s_axi_rdata[774] = \<const0> ;
assign s_axi_rdata[773] = \<const0> ;
assign s_axi_rdata[772] = \<const0> ;
assign s_axi_rdata[771] = \<const0> ;
assign s_axi_rdata[770] = \<const0> ;
assign s_axi_rdata[769] = \<const0> ;
assign s_axi_rdata[768] = \<const0> ;
assign s_axi_rdata[767] = \<const0> ;
assign s_axi_rdata[766] = \<const0> ;
assign s_axi_rdata[765] = \<const0> ;
assign s_axi_rdata[764] = \<const0> ;
assign s_axi_rdata[763] = \<const0> ;
assign s_axi_rdata[762] = \<const0> ;
assign s_axi_rdata[761] = \<const0> ;
assign s_axi_rdata[760] = \<const0> ;
assign s_axi_rdata[759] = \<const0> ;
assign s_axi_rdata[758] = \<const0> ;
assign s_axi_rdata[757] = \<const0> ;
assign s_axi_rdata[756] = \<const0> ;
assign s_axi_rdata[755] = \<const0> ;
assign s_axi_rdata[754] = \<const0> ;
assign s_axi_rdata[753] = \<const0> ;
assign s_axi_rdata[752] = \<const0> ;
assign s_axi_rdata[751] = \<const0> ;
assign s_axi_rdata[750] = \<const0> ;
assign s_axi_rdata[749] = \<const0> ;
assign s_axi_rdata[748] = \<const0> ;
assign s_axi_rdata[747] = \<const0> ;
assign s_axi_rdata[746] = \<const0> ;
assign s_axi_rdata[745] = \<const0> ;
assign s_axi_rdata[744] = \<const0> ;
assign s_axi_rdata[743] = \<const0> ;
assign s_axi_rdata[742] = \<const0> ;
assign s_axi_rdata[741] = \<const0> ;
assign s_axi_rdata[740] = \<const0> ;
assign s_axi_rdata[739] = \<const0> ;
assign s_axi_rdata[738] = \<const0> ;
assign s_axi_rdata[737] = \<const0> ;
assign s_axi_rdata[736] = \<const0> ;
assign s_axi_rdata[735] = \<const0> ;
assign s_axi_rdata[734] = \<const0> ;
assign s_axi_rdata[733] = \<const0> ;
assign s_axi_rdata[732] = \<const0> ;
assign s_axi_rdata[731] = \<const0> ;
assign s_axi_rdata[730] = \<const0> ;
assign s_axi_rdata[729] = \<const0> ;
assign s_axi_rdata[728] = \<const0> ;
assign s_axi_rdata[727] = \<const0> ;
assign s_axi_rdata[726] = \<const0> ;
assign s_axi_rdata[725] = \<const0> ;
assign s_axi_rdata[724] = \<const0> ;
assign s_axi_rdata[723] = \<const0> ;
assign s_axi_rdata[722] = \<const0> ;
assign s_axi_rdata[721] = \<const0> ;
assign s_axi_rdata[720] = \<const0> ;
assign s_axi_rdata[719] = \<const0> ;
assign s_axi_rdata[718] = \<const0> ;
assign s_axi_rdata[717] = \<const0> ;
assign s_axi_rdata[716] = \<const0> ;
assign s_axi_rdata[715] = \<const0> ;
assign s_axi_rdata[714] = \<const0> ;
assign s_axi_rdata[713] = \<const0> ;
assign s_axi_rdata[712] = \<const0> ;
assign s_axi_rdata[711] = \<const0> ;
assign s_axi_rdata[710] = \<const0> ;
assign s_axi_rdata[709] = \<const0> ;
assign s_axi_rdata[708] = \<const0> ;
assign s_axi_rdata[707] = \<const0> ;
assign s_axi_rdata[706] = \<const0> ;
assign s_axi_rdata[705] = \<const0> ;
assign s_axi_rdata[704] = \<const0> ;
assign s_axi_rdata[703] = \<const0> ;
assign s_axi_rdata[702] = \<const0> ;
assign s_axi_rdata[701] = \<const0> ;
assign s_axi_rdata[700] = \<const0> ;
assign s_axi_rdata[699] = \<const0> ;
assign s_axi_rdata[698] = \<const0> ;
assign s_axi_rdata[697] = \<const0> ;
assign s_axi_rdata[696] = \<const0> ;
assign s_axi_rdata[695] = \<const0> ;
assign s_axi_rdata[694] = \<const0> ;
assign s_axi_rdata[693] = \<const0> ;
assign s_axi_rdata[692] = \<const0> ;
assign s_axi_rdata[691] = \<const0> ;
assign s_axi_rdata[690] = \<const0> ;
assign s_axi_rdata[689] = \<const0> ;
assign s_axi_rdata[688] = \<const0> ;
assign s_axi_rdata[687] = \<const0> ;
assign s_axi_rdata[686] = \<const0> ;
assign s_axi_rdata[685] = \<const0> ;
assign s_axi_rdata[684] = \<const0> ;
assign s_axi_rdata[683] = \<const0> ;
assign s_axi_rdata[682] = \<const0> ;
assign s_axi_rdata[681] = \<const0> ;
assign s_axi_rdata[680] = \<const0> ;
assign s_axi_rdata[679] = \<const0> ;
assign s_axi_rdata[678] = \<const0> ;
assign s_axi_rdata[677] = \<const0> ;
assign s_axi_rdata[676] = \<const0> ;
assign s_axi_rdata[675] = \<const0> ;
assign s_axi_rdata[674] = \<const0> ;
assign s_axi_rdata[673] = \<const0> ;
assign s_axi_rdata[672] = \<const0> ;
assign s_axi_rdata[671] = \<const0> ;
assign s_axi_rdata[670] = \<const0> ;
assign s_axi_rdata[669] = \<const0> ;
assign s_axi_rdata[668] = \<const0> ;
assign s_axi_rdata[667] = \<const0> ;
assign s_axi_rdata[666] = \<const0> ;
assign s_axi_rdata[665] = \<const0> ;
assign s_axi_rdata[664] = \<const0> ;
assign s_axi_rdata[663] = \<const0> ;
assign s_axi_rdata[662] = \<const0> ;
assign s_axi_rdata[661] = \<const0> ;
assign s_axi_rdata[660] = \<const0> ;
assign s_axi_rdata[659] = \<const0> ;
assign s_axi_rdata[658] = \<const0> ;
assign s_axi_rdata[657] = \<const0> ;
assign s_axi_rdata[656] = \<const0> ;
assign s_axi_rdata[655] = \<const0> ;
assign s_axi_rdata[654] = \<const0> ;
assign s_axi_rdata[653] = \<const0> ;
assign s_axi_rdata[652] = \<const0> ;
assign s_axi_rdata[651] = \<const0> ;
assign s_axi_rdata[650] = \<const0> ;
assign s_axi_rdata[649] = \<const0> ;
assign s_axi_rdata[648] = \<const0> ;
assign s_axi_rdata[647] = \<const0> ;
assign s_axi_rdata[646] = \<const0> ;
assign s_axi_rdata[645] = \<const0> ;
assign s_axi_rdata[644] = \<const0> ;
assign s_axi_rdata[643] = \<const0> ;
assign s_axi_rdata[642] = \<const0> ;
assign s_axi_rdata[641] = \<const0> ;
assign s_axi_rdata[640] = \<const0> ;
assign s_axi_rdata[639] = \<const0> ;
assign s_axi_rdata[638] = \<const0> ;
assign s_axi_rdata[637] = \<const0> ;
assign s_axi_rdata[636] = \<const0> ;
assign s_axi_rdata[635] = \<const0> ;
assign s_axi_rdata[634] = \<const0> ;
assign s_axi_rdata[633] = \<const0> ;
assign s_axi_rdata[632] = \<const0> ;
assign s_axi_rdata[631] = \<const0> ;
assign s_axi_rdata[630] = \<const0> ;
assign s_axi_rdata[629] = \<const0> ;
assign s_axi_rdata[628] = \<const0> ;
assign s_axi_rdata[627] = \<const0> ;
assign s_axi_rdata[626] = \<const0> ;
assign s_axi_rdata[625] = \<const0> ;
assign s_axi_rdata[624] = \<const0> ;
assign s_axi_rdata[623] = \<const0> ;
assign s_axi_rdata[622] = \<const0> ;
assign s_axi_rdata[621] = \<const0> ;
assign s_axi_rdata[620] = \<const0> ;
assign s_axi_rdata[619] = \<const0> ;
assign s_axi_rdata[618] = \<const0> ;
assign s_axi_rdata[617] = \<const0> ;
assign s_axi_rdata[616] = \<const0> ;
assign s_axi_rdata[615] = \<const0> ;
assign s_axi_rdata[614] = \<const0> ;
assign s_axi_rdata[613] = \<const0> ;
assign s_axi_rdata[612] = \<const0> ;
assign s_axi_rdata[611] = \<const0> ;
assign s_axi_rdata[610] = \<const0> ;
assign s_axi_rdata[609] = \<const0> ;
assign s_axi_rdata[608] = \<const0> ;
assign s_axi_rdata[607] = \<const0> ;
assign s_axi_rdata[606] = \<const0> ;
assign s_axi_rdata[605] = \<const0> ;
assign s_axi_rdata[604] = \<const0> ;
assign s_axi_rdata[603] = \<const0> ;
assign s_axi_rdata[602] = \<const0> ;
assign s_axi_rdata[601] = \<const0> ;
assign s_axi_rdata[600] = \<const0> ;
assign s_axi_rdata[599] = \<const0> ;
assign s_axi_rdata[598] = \<const0> ;
assign s_axi_rdata[597] = \<const0> ;
assign s_axi_rdata[596] = \<const0> ;
assign s_axi_rdata[595] = \<const0> ;
assign s_axi_rdata[594] = \<const0> ;
assign s_axi_rdata[593] = \<const0> ;
assign s_axi_rdata[592] = \<const0> ;
assign s_axi_rdata[591] = \<const0> ;
assign s_axi_rdata[590] = \<const0> ;
assign s_axi_rdata[589] = \<const0> ;
assign s_axi_rdata[588] = \<const0> ;
assign s_axi_rdata[587] = \<const0> ;
assign s_axi_rdata[586] = \<const0> ;
assign s_axi_rdata[585] = \<const0> ;
assign s_axi_rdata[584] = \<const0> ;
assign s_axi_rdata[583] = \<const0> ;
assign s_axi_rdata[582] = \<const0> ;
assign s_axi_rdata[581] = \<const0> ;
assign s_axi_rdata[580] = \<const0> ;
assign s_axi_rdata[579] = \<const0> ;
assign s_axi_rdata[578] = \<const0> ;
assign s_axi_rdata[577] = \<const0> ;
assign s_axi_rdata[576] = \<const0> ;
assign s_axi_rdata[575] = \<const0> ;
assign s_axi_rdata[574] = \<const0> ;
assign s_axi_rdata[573] = \<const0> ;
assign s_axi_rdata[572] = \<const0> ;
assign s_axi_rdata[571] = \<const0> ;
assign s_axi_rdata[570] = \<const0> ;
assign s_axi_rdata[569] = \<const0> ;
assign s_axi_rdata[568] = \<const0> ;
assign s_axi_rdata[567] = \<const0> ;
assign s_axi_rdata[566] = \<const0> ;
assign s_axi_rdata[565] = \<const0> ;
assign s_axi_rdata[564] = \<const0> ;
assign s_axi_rdata[563] = \<const0> ;
assign s_axi_rdata[562] = \<const0> ;
assign s_axi_rdata[561] = \<const0> ;
assign s_axi_rdata[560] = \<const0> ;
assign s_axi_rdata[559] = \<const0> ;
assign s_axi_rdata[558] = \<const0> ;
assign s_axi_rdata[557] = \<const0> ;
assign s_axi_rdata[556] = \<const0> ;
assign s_axi_rdata[555] = \<const0> ;
assign s_axi_rdata[554] = \<const0> ;
assign s_axi_rdata[553] = \<const0> ;
assign s_axi_rdata[552] = \<const0> ;
assign s_axi_rdata[551] = \<const0> ;
assign s_axi_rdata[550] = \<const0> ;
assign s_axi_rdata[549] = \<const0> ;
assign s_axi_rdata[548] = \<const0> ;
assign s_axi_rdata[547] = \<const0> ;
assign s_axi_rdata[546] = \<const0> ;
assign s_axi_rdata[545] = \<const0> ;
assign s_axi_rdata[544] = \<const0> ;
assign s_axi_rdata[543] = \<const0> ;
assign s_axi_rdata[542] = \<const0> ;
assign s_axi_rdata[541] = \<const0> ;
assign s_axi_rdata[540] = \<const0> ;
assign s_axi_rdata[539] = \<const0> ;
assign s_axi_rdata[538] = \<const0> ;
assign s_axi_rdata[537] = \<const0> ;
assign s_axi_rdata[536] = \<const0> ;
assign s_axi_rdata[535] = \<const0> ;
assign s_axi_rdata[534] = \<const0> ;
assign s_axi_rdata[533] = \<const0> ;
assign s_axi_rdata[532] = \<const0> ;
assign s_axi_rdata[531] = \<const0> ;
assign s_axi_rdata[530] = \<const0> ;
assign s_axi_rdata[529] = \<const0> ;
assign s_axi_rdata[528] = \<const0> ;
assign s_axi_rdata[527] = \<const0> ;
assign s_axi_rdata[526] = \<const0> ;
assign s_axi_rdata[525] = \<const0> ;
assign s_axi_rdata[524] = \<const0> ;
assign s_axi_rdata[523] = \<const0> ;
assign s_axi_rdata[522] = \<const0> ;
assign s_axi_rdata[521] = \<const0> ;
assign s_axi_rdata[520] = \<const0> ;
assign s_axi_rdata[519] = \<const0> ;
assign s_axi_rdata[518] = \<const0> ;
assign s_axi_rdata[517] = \<const0> ;
assign s_axi_rdata[516] = \<const0> ;
assign s_axi_rdata[515] = \<const0> ;
assign s_axi_rdata[514] = \<const0> ;
assign s_axi_rdata[513] = \<const0> ;
assign s_axi_rdata[512] = \<const0> ;
assign s_axi_rdata[511] = \<const0> ;
assign s_axi_rdata[510] = \<const0> ;
assign s_axi_rdata[509] = \<const0> ;
assign s_axi_rdata[508] = \<const0> ;
assign s_axi_rdata[507] = \<const0> ;
assign s_axi_rdata[506] = \<const0> ;
assign s_axi_rdata[505] = \<const0> ;
assign s_axi_rdata[504] = \<const0> ;
assign s_axi_rdata[503] = \<const0> ;
assign s_axi_rdata[502] = \<const0> ;
assign s_axi_rdata[501] = \<const0> ;
assign s_axi_rdata[500] = \<const0> ;
assign s_axi_rdata[499] = \<const0> ;
assign s_axi_rdata[498] = \<const0> ;
assign s_axi_rdata[497] = \<const0> ;
assign s_axi_rdata[496] = \<const0> ;
assign s_axi_rdata[495] = \<const0> ;
assign s_axi_rdata[494] = \<const0> ;
assign s_axi_rdata[493] = \<const0> ;
assign s_axi_rdata[492] = \<const0> ;
assign s_axi_rdata[491] = \<const0> ;
assign s_axi_rdata[490] = \<const0> ;
assign s_axi_rdata[489] = \<const0> ;
assign s_axi_rdata[488] = \<const0> ;
assign s_axi_rdata[487] = \<const0> ;
assign s_axi_rdata[486] = \<const0> ;
assign s_axi_rdata[485] = \<const0> ;
assign s_axi_rdata[484] = \<const0> ;
assign s_axi_rdata[483] = \<const0> ;
assign s_axi_rdata[482] = \<const0> ;
assign s_axi_rdata[481] = \<const0> ;
assign s_axi_rdata[480] = \<const0> ;
assign s_axi_rdata[479] = \<const0> ;
assign s_axi_rdata[478] = \<const0> ;
assign s_axi_rdata[477] = \<const0> ;
assign s_axi_rdata[476] = \<const0> ;
assign s_axi_rdata[475] = \<const0> ;
assign s_axi_rdata[474] = \<const0> ;
assign s_axi_rdata[473] = \<const0> ;
assign s_axi_rdata[472] = \<const0> ;
assign s_axi_rdata[471] = \<const0> ;
assign s_axi_rdata[470] = \<const0> ;
assign s_axi_rdata[469] = \<const0> ;
assign s_axi_rdata[468] = \<const0> ;
assign s_axi_rdata[467] = \<const0> ;
assign s_axi_rdata[466] = \<const0> ;
assign s_axi_rdata[465] = \<const0> ;
assign s_axi_rdata[464] = \<const0> ;
assign s_axi_rdata[463] = \<const0> ;
assign s_axi_rdata[462] = \<const0> ;
assign s_axi_rdata[461] = \<const0> ;
assign s_axi_rdata[460] = \<const0> ;
assign s_axi_rdata[459] = \<const0> ;
assign s_axi_rdata[458] = \<const0> ;
assign s_axi_rdata[457] = \<const0> ;
assign s_axi_rdata[456] = \<const0> ;
assign s_axi_rdata[455] = \<const0> ;
assign s_axi_rdata[454] = \<const0> ;
assign s_axi_rdata[453] = \<const0> ;
assign s_axi_rdata[452] = \<const0> ;
assign s_axi_rdata[451] = \<const0> ;
assign s_axi_rdata[450] = \<const0> ;
assign s_axi_rdata[449] = \<const0> ;
assign s_axi_rdata[448] = \<const0> ;
assign s_axi_rdata[447] = \<const0> ;
assign s_axi_rdata[446] = \<const0> ;
assign s_axi_rdata[445] = \<const0> ;
assign s_axi_rdata[444] = \<const0> ;
assign s_axi_rdata[443] = \<const0> ;
assign s_axi_rdata[442] = \<const0> ;
assign s_axi_rdata[441] = \<const0> ;
assign s_axi_rdata[440] = \<const0> ;
assign s_axi_rdata[439] = \<const0> ;
assign s_axi_rdata[438] = \<const0> ;
assign s_axi_rdata[437] = \<const0> ;
assign s_axi_rdata[436] = \<const0> ;
assign s_axi_rdata[435] = \<const0> ;
assign s_axi_rdata[434] = \<const0> ;
assign s_axi_rdata[433] = \<const0> ;
assign s_axi_rdata[432] = \<const0> ;
assign s_axi_rdata[431] = \<const0> ;
assign s_axi_rdata[430] = \<const0> ;
assign s_axi_rdata[429] = \<const0> ;
assign s_axi_rdata[428] = \<const0> ;
assign s_axi_rdata[427] = \<const0> ;
assign s_axi_rdata[426] = \<const0> ;
assign s_axi_rdata[425] = \<const0> ;
assign s_axi_rdata[424] = \<const0> ;
assign s_axi_rdata[423] = \<const0> ;
assign s_axi_rdata[422] = \<const0> ;
assign s_axi_rdata[421] = \<const0> ;
assign s_axi_rdata[420] = \<const0> ;
assign s_axi_rdata[419] = \<const0> ;
assign s_axi_rdata[418] = \<const0> ;
assign s_axi_rdata[417] = \<const0> ;
assign s_axi_rdata[416] = \<const0> ;
assign s_axi_rdata[415] = \<const0> ;
assign s_axi_rdata[414] = \<const0> ;
assign s_axi_rdata[413] = \<const0> ;
assign s_axi_rdata[412] = \<const0> ;
assign s_axi_rdata[411] = \<const0> ;
assign s_axi_rdata[410] = \<const0> ;
assign s_axi_rdata[409] = \<const0> ;
assign s_axi_rdata[408] = \<const0> ;
assign s_axi_rdata[407] = \<const0> ;
assign s_axi_rdata[406] = \<const0> ;
assign s_axi_rdata[405] = \<const0> ;
assign s_axi_rdata[404] = \<const0> ;
assign s_axi_rdata[403] = \<const0> ;
assign s_axi_rdata[402] = \<const0> ;
assign s_axi_rdata[401] = \<const0> ;
assign s_axi_rdata[400] = \<const0> ;
assign s_axi_rdata[399] = \<const0> ;
assign s_axi_rdata[398] = \<const0> ;
assign s_axi_rdata[397] = \<const0> ;
assign s_axi_rdata[396] = \<const0> ;
assign s_axi_rdata[395] = \<const0> ;
assign s_axi_rdata[394] = \<const0> ;
assign s_axi_rdata[393] = \<const0> ;
assign s_axi_rdata[392] = \<const0> ;
assign s_axi_rdata[391] = \<const0> ;
assign s_axi_rdata[390] = \<const0> ;
assign s_axi_rdata[389] = \<const0> ;
assign s_axi_rdata[388] = \<const0> ;
assign s_axi_rdata[387] = \<const0> ;
assign s_axi_rdata[386] = \<const0> ;
assign s_axi_rdata[385] = \<const0> ;
assign s_axi_rdata[384] = \<const0> ;
assign s_axi_rdata[383] = \<const0> ;
assign s_axi_rdata[382] = \<const0> ;
assign s_axi_rdata[381] = \<const0> ;
assign s_axi_rdata[380] = \<const0> ;
assign s_axi_rdata[379] = \<const0> ;
assign s_axi_rdata[378] = \<const0> ;
assign s_axi_rdata[377] = \<const0> ;
assign s_axi_rdata[376] = \<const0> ;
assign s_axi_rdata[375] = \<const0> ;
assign s_axi_rdata[374] = \<const0> ;
assign s_axi_rdata[373] = \<const0> ;
assign s_axi_rdata[372] = \<const0> ;
assign s_axi_rdata[371] = \<const0> ;
assign s_axi_rdata[370] = \<const0> ;
assign s_axi_rdata[369] = \<const0> ;
assign s_axi_rdata[368] = \<const0> ;
assign s_axi_rdata[367] = \<const0> ;
assign s_axi_rdata[366] = \<const0> ;
assign s_axi_rdata[365] = \<const0> ;
assign s_axi_rdata[364] = \<const0> ;
assign s_axi_rdata[363] = \<const0> ;
assign s_axi_rdata[362] = \<const0> ;
assign s_axi_rdata[361] = \<const0> ;
assign s_axi_rdata[360] = \<const0> ;
assign s_axi_rdata[359] = \<const0> ;
assign s_axi_rdata[358] = \<const0> ;
assign s_axi_rdata[357] = \<const0> ;
assign s_axi_rdata[356] = \<const0> ;
assign s_axi_rdata[355] = \<const0> ;
assign s_axi_rdata[354] = \<const0> ;
assign s_axi_rdata[353] = \<const0> ;
assign s_axi_rdata[352] = \<const0> ;
assign s_axi_rdata[351] = \<const0> ;
assign s_axi_rdata[350] = \<const0> ;
assign s_axi_rdata[349] = \<const0> ;
assign s_axi_rdata[348] = \<const0> ;
assign s_axi_rdata[347] = \<const0> ;
assign s_axi_rdata[346] = \<const0> ;
assign s_axi_rdata[345] = \<const0> ;
assign s_axi_rdata[344] = \<const0> ;
assign s_axi_rdata[343] = \<const0> ;
assign s_axi_rdata[342] = \<const0> ;
assign s_axi_rdata[341] = \<const0> ;
assign s_axi_rdata[340] = \<const0> ;
assign s_axi_rdata[339] = \<const0> ;
assign s_axi_rdata[338] = \<const0> ;
assign s_axi_rdata[337] = \<const0> ;
assign s_axi_rdata[336] = \<const0> ;
assign s_axi_rdata[335] = \<const0> ;
assign s_axi_rdata[334] = \<const0> ;
assign s_axi_rdata[333] = \<const0> ;
assign s_axi_rdata[332] = \<const0> ;
assign s_axi_rdata[331] = \<const0> ;
assign s_axi_rdata[330] = \<const0> ;
assign s_axi_rdata[329] = \<const0> ;
assign s_axi_rdata[328] = \<const0> ;
assign s_axi_rdata[327] = \<const0> ;
assign s_axi_rdata[326] = \<const0> ;
assign s_axi_rdata[325] = \<const0> ;
assign s_axi_rdata[324] = \<const0> ;
assign s_axi_rdata[323] = \<const0> ;
assign s_axi_rdata[322] = \<const0> ;
assign s_axi_rdata[321] = \<const0> ;
assign s_axi_rdata[320] = \<const0> ;
assign s_axi_rdata[319] = \<const0> ;
assign s_axi_rdata[318] = \<const0> ;
assign s_axi_rdata[317] = \<const0> ;
assign s_axi_rdata[316] = \<const0> ;
assign s_axi_rdata[315] = \<const0> ;
assign s_axi_rdata[314] = \<const0> ;
assign s_axi_rdata[313] = \<const0> ;
assign s_axi_rdata[312] = \<const0> ;
assign s_axi_rdata[311] = \<const0> ;
assign s_axi_rdata[310] = \<const0> ;
assign s_axi_rdata[309] = \<const0> ;
assign s_axi_rdata[308] = \<const0> ;
assign s_axi_rdata[307] = \<const0> ;
assign s_axi_rdata[306] = \<const0> ;
assign s_axi_rdata[305] = \<const0> ;
assign s_axi_rdata[304] = \<const0> ;
assign s_axi_rdata[303] = \<const0> ;
assign s_axi_rdata[302] = \<const0> ;
assign s_axi_rdata[301] = \<const0> ;
assign s_axi_rdata[300] = \<const0> ;
assign s_axi_rdata[299] = \<const0> ;
assign s_axi_rdata[298] = \<const0> ;
assign s_axi_rdata[297] = \<const0> ;
assign s_axi_rdata[296] = \<const0> ;
assign s_axi_rdata[295] = \<const0> ;
assign s_axi_rdata[294] = \<const0> ;
assign s_axi_rdata[293] = \<const0> ;
assign s_axi_rdata[292] = \<const0> ;
assign s_axi_rdata[291] = \<const0> ;
assign s_axi_rdata[290] = \<const0> ;
assign s_axi_rdata[289] = \<const0> ;
assign s_axi_rdata[288] = \<const0> ;
assign s_axi_rdata[287] = \<const0> ;
assign s_axi_rdata[286] = \<const0> ;
assign s_axi_rdata[285] = \<const0> ;
assign s_axi_rdata[284] = \<const0> ;
assign s_axi_rdata[283] = \<const0> ;
assign s_axi_rdata[282] = \<const0> ;
assign s_axi_rdata[281] = \<const0> ;
assign s_axi_rdata[280] = \<const0> ;
assign s_axi_rdata[279] = \<const0> ;
assign s_axi_rdata[278] = \<const0> ;
assign s_axi_rdata[277] = \<const0> ;
assign s_axi_rdata[276] = \<const0> ;
assign s_axi_rdata[275] = \<const0> ;
assign s_axi_rdata[274] = \<const0> ;
assign s_axi_rdata[273] = \<const0> ;
assign s_axi_rdata[272] = \<const0> ;
assign s_axi_rdata[271] = \<const0> ;
assign s_axi_rdata[270] = \<const0> ;
assign s_axi_rdata[269] = \<const0> ;
assign s_axi_rdata[268] = \<const0> ;
assign s_axi_rdata[267] = \<const0> ;
assign s_axi_rdata[266] = \<const0> ;
assign s_axi_rdata[265] = \<const0> ;
assign s_axi_rdata[264] = \<const0> ;
assign s_axi_rdata[263] = \<const0> ;
assign s_axi_rdata[262] = \<const0> ;
assign s_axi_rdata[261] = \<const0> ;
assign s_axi_rdata[260] = \<const0> ;
assign s_axi_rdata[259] = \<const0> ;
assign s_axi_rdata[258] = \<const0> ;
assign s_axi_rdata[257] = \<const0> ;
assign s_axi_rdata[256] = \<const0> ;
assign s_axi_rdata[255] = \<const0> ;
assign s_axi_rdata[254] = \<const0> ;
assign s_axi_rdata[253] = \<const0> ;
assign s_axi_rdata[252] = \<const0> ;
assign s_axi_rdata[251] = \<const0> ;
assign s_axi_rdata[250] = \<const0> ;
assign s_axi_rdata[249] = \<const0> ;
assign s_axi_rdata[248] = \<const0> ;
assign s_axi_rdata[247] = \<const0> ;
assign s_axi_rdata[246] = \<const0> ;
assign s_axi_rdata[245] = \<const0> ;
assign s_axi_rdata[244] = \<const0> ;
assign s_axi_rdata[243] = \<const0> ;
assign s_axi_rdata[242] = \<const0> ;
assign s_axi_rdata[241] = \<const0> ;
assign s_axi_rdata[240] = \<const0> ;
assign s_axi_rdata[239] = \<const0> ;
assign s_axi_rdata[238] = \<const0> ;
assign s_axi_rdata[237] = \<const0> ;
assign s_axi_rdata[236] = \<const0> ;
assign s_axi_rdata[235] = \<const0> ;
assign s_axi_rdata[234] = \<const0> ;
assign s_axi_rdata[233] = \<const0> ;
assign s_axi_rdata[232] = \<const0> ;
assign s_axi_rdata[231] = \<const0> ;
assign s_axi_rdata[230] = \<const0> ;
assign s_axi_rdata[229] = \<const0> ;
assign s_axi_rdata[228] = \<const0> ;
assign s_axi_rdata[227] = \<const0> ;
assign s_axi_rdata[226] = \<const0> ;
assign s_axi_rdata[225] = \<const0> ;
assign s_axi_rdata[224] = \<const0> ;
assign s_axi_rdata[223] = \<const0> ;
assign s_axi_rdata[222] = \<const0> ;
assign s_axi_rdata[221] = \<const0> ;
assign s_axi_rdata[220] = \<const0> ;
assign s_axi_rdata[219] = \<const0> ;
assign s_axi_rdata[218] = \<const0> ;
assign s_axi_rdata[217] = \<const0> ;
assign s_axi_rdata[216] = \<const0> ;
assign s_axi_rdata[215] = \<const0> ;
assign s_axi_rdata[214] = \<const0> ;
assign s_axi_rdata[213] = \<const0> ;
assign s_axi_rdata[212] = \<const0> ;
assign s_axi_rdata[211] = \<const0> ;
assign s_axi_rdata[210] = \<const0> ;
assign s_axi_rdata[209] = \<const0> ;
assign s_axi_rdata[208] = \<const0> ;
assign s_axi_rdata[207] = \<const0> ;
assign s_axi_rdata[206] = \<const0> ;
assign s_axi_rdata[205] = \<const0> ;
assign s_axi_rdata[204] = \<const0> ;
assign s_axi_rdata[203] = \<const0> ;
assign s_axi_rdata[202] = \<const0> ;
assign s_axi_rdata[201] = \<const0> ;
assign s_axi_rdata[200] = \<const0> ;
assign s_axi_rdata[199] = \<const0> ;
assign s_axi_rdata[198] = \<const0> ;
assign s_axi_rdata[197] = \<const0> ;
assign s_axi_rdata[196] = \<const0> ;
assign s_axi_rdata[195] = \<const0> ;
assign s_axi_rdata[194] = \<const0> ;
assign s_axi_rdata[193] = \<const0> ;
assign s_axi_rdata[192] = \<const0> ;
assign s_axi_rdata[191] = \<const0> ;
assign s_axi_rdata[190] = \<const0> ;
assign s_axi_rdata[189] = \<const0> ;
assign s_axi_rdata[188] = \<const0> ;
assign s_axi_rdata[187] = \<const0> ;
assign s_axi_rdata[186] = \<const0> ;
assign s_axi_rdata[185] = \<const0> ;
assign s_axi_rdata[184] = \<const0> ;
assign s_axi_rdata[183] = \<const0> ;
assign s_axi_rdata[182] = \<const0> ;
assign s_axi_rdata[181] = \<const0> ;
assign s_axi_rdata[180] = \<const0> ;
assign s_axi_rdata[179] = \<const0> ;
assign s_axi_rdata[178] = \<const0> ;
assign s_axi_rdata[177] = \<const0> ;
assign s_axi_rdata[176] = \<const0> ;
assign s_axi_rdata[175] = \<const0> ;
assign s_axi_rdata[174] = \<const0> ;
assign s_axi_rdata[173] = \<const0> ;
assign s_axi_rdata[172] = \<const0> ;
assign s_axi_rdata[171] = \<const0> ;
assign s_axi_rdata[170] = \<const0> ;
assign s_axi_rdata[169] = \<const0> ;
assign s_axi_rdata[168] = \<const0> ;
assign s_axi_rdata[167] = \<const0> ;
assign s_axi_rdata[166] = \<const0> ;
assign s_axi_rdata[165] = \<const0> ;
assign s_axi_rdata[164] = \<const0> ;
assign s_axi_rdata[163] = \<const0> ;
assign s_axi_rdata[162] = \<const0> ;
assign s_axi_rdata[161] = \<const0> ;
assign s_axi_rdata[160] = \<const0> ;
assign s_axi_rdata[159] = \<const0> ;
assign s_axi_rdata[158] = \<const0> ;
assign s_axi_rdata[157] = \<const0> ;
assign s_axi_rdata[156] = \<const0> ;
assign s_axi_rdata[155] = \<const0> ;
assign s_axi_rdata[154] = \<const0> ;
assign s_axi_rdata[153] = \<const0> ;
assign s_axi_rdata[152] = \<const0> ;
assign s_axi_rdata[151] = \<const0> ;
assign s_axi_rdata[150] = \<const0> ;
assign s_axi_rdata[149] = \<const0> ;
assign s_axi_rdata[148] = \<const0> ;
assign s_axi_rdata[147] = \<const0> ;
assign s_axi_rdata[146] = \<const0> ;
assign s_axi_rdata[145] = \<const0> ;
assign s_axi_rdata[144] = \<const0> ;
assign s_axi_rdata[143] = \<const0> ;
assign s_axi_rdata[142] = \<const0> ;
assign s_axi_rdata[141] = \<const0> ;
assign s_axi_rdata[140] = \<const0> ;
assign s_axi_rdata[139] = \<const0> ;
assign s_axi_rdata[138] = \<const0> ;
assign s_axi_rdata[137] = \<const0> ;
assign s_axi_rdata[136] = \<const0> ;
assign s_axi_rdata[135] = \<const0> ;
assign s_axi_rdata[134] = \<const0> ;
assign s_axi_rdata[133] = \<const0> ;
assign s_axi_rdata[132] = \<const0> ;
assign s_axi_rdata[131] = \<const0> ;
assign s_axi_rdata[130] = \<const0> ;
assign s_axi_rdata[129] = \<const0> ;
assign s_axi_rdata[128] = \<const0> ;
assign s_axi_rdata[127] = \<const0> ;
assign s_axi_rdata[126] = \<const0> ;
assign s_axi_rdata[125] = \<const0> ;
assign s_axi_rdata[124] = \<const0> ;
assign s_axi_rdata[123] = \<const0> ;
assign s_axi_rdata[122] = \<const0> ;
assign s_axi_rdata[121] = \<const0> ;
assign s_axi_rdata[120] = \<const0> ;
assign s_axi_rdata[119] = \<const0> ;
assign s_axi_rdata[118] = \<const0> ;
assign s_axi_rdata[117] = \<const0> ;
assign s_axi_rdata[116] = \<const0> ;
assign s_axi_rdata[115] = \<const0> ;
assign s_axi_rdata[114] = \<const0> ;
assign s_axi_rdata[113] = \<const0> ;
assign s_axi_rdata[112] = \<const0> ;
assign s_axi_rdata[111] = \<const0> ;
assign s_axi_rdata[110] = \<const0> ;
assign s_axi_rdata[109] = \<const0> ;
assign s_axi_rdata[108] = \<const0> ;
assign s_axi_rdata[107] = \<const0> ;
assign s_axi_rdata[106] = \<const0> ;
assign s_axi_rdata[105] = \<const0> ;
assign s_axi_rdata[104] = \<const0> ;
assign s_axi_rdata[103] = \<const0> ;
assign s_axi_rdata[102] = \<const0> ;
assign s_axi_rdata[101] = \<const0> ;
assign s_axi_rdata[100] = \<const0> ;
assign s_axi_rdata[99] = \<const0> ;
assign s_axi_rdata[98] = \<const0> ;
assign s_axi_rdata[97] = \<const0> ;
assign s_axi_rdata[96] = \<const0> ;
assign s_axi_rdata[95] = \<const0> ;
assign s_axi_rdata[94] = \<const0> ;
assign s_axi_rdata[93] = \<const0> ;
assign s_axi_rdata[92] = \<const0> ;
assign s_axi_rdata[91] = \<const0> ;
assign s_axi_rdata[90] = \<const0> ;
assign s_axi_rdata[89] = \<const0> ;
assign s_axi_rdata[88] = \<const0> ;
assign s_axi_rdata[87] = \<const0> ;
assign s_axi_rdata[86] = \<const0> ;
assign s_axi_rdata[85] = \<const0> ;
assign s_axi_rdata[84] = \<const0> ;
assign s_axi_rdata[83] = \<const0> ;
assign s_axi_rdata[82] = \<const0> ;
assign s_axi_rdata[81] = \<const0> ;
assign s_axi_rdata[80] = \<const0> ;
assign s_axi_rdata[79] = \<const0> ;
assign s_axi_rdata[78] = \<const0> ;
assign s_axi_rdata[77] = \<const0> ;
assign s_axi_rdata[76] = \<const0> ;
assign s_axi_rdata[75] = \<const0> ;
assign s_axi_rdata[74] = \<const0> ;
assign s_axi_rdata[73] = \<const0> ;
assign s_axi_rdata[72] = \<const0> ;
assign s_axi_rdata[71] = \<const0> ;
assign s_axi_rdata[70] = \<const0> ;
assign s_axi_rdata[69] = \<const0> ;
assign s_axi_rdata[68] = \<const0> ;
assign s_axi_rdata[67] = \<const0> ;
assign s_axi_rdata[66] = \<const0> ;
assign s_axi_rdata[65] = \<const0> ;
assign s_axi_rdata[64] = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
Initial_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module Initial_blk_mem_gen_v8_2_synth
(douta,
clka,
addra);
output [1599:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [1599:0]douta;
Initial_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module util_pmod_fmeter_core (
ref_clk,
reset,
square_signal,
signal_freq);
input ref_clk;
input reset;
input square_signal;
output [31:0] signal_freq;
// registers
reg [31:0] signal_freq = 'h0;
reg [31:0] signal_freq_counter = 'h0;
reg [ 2:0] square_signal_buf = 'h0;
wire signal_freq_en;
assign signal_freq_en = ~square_signal_buf[2] & square_signal_buf[1];
// internal signals
always @(posedge ref_clk) begin
square_signal_buf[0] <= square_signal;
square_signal_buf[2:1] <= square_signal_buf[1:0];
end
always @(posedge ref_clk) begin
if (reset == 1'b1) begin
signal_freq <= 32'b0;
signal_freq_counter <= 32'b0;
end else begin
if(signal_freq_en == 1'b1) begin
signal_freq <= signal_freq_counter;
signal_freq_counter <= 32'h0;
end else begin
signal_freq_counter <= signal_freq_counter + 32'h1;
end
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Wed Aug 18 12:44:01 2004
// cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../constant.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.3 2004/08/18 10:47:12 wig Exp $
// $Date: 2004/08/18 10:47:12 $
// $Log: inst_t_e.v,v $
// Revision 1.3 2004/08/18 10:47:12 wig
// reworked some testcases
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
//
// Generator: mix_0.pl Revision: 1.32 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No `defines in this module
module inst_t_e
//
// Generated module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_a
inst_a_e inst_a(
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_e
inst_e_e inst_e(
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_ctlif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output reg bypass,
output reg sdram_rst,
output reg sdram_cke,
output reg sdram_cs_n,
output reg sdram_we_n,
output reg sdram_cas_n,
output reg sdram_ras_n,
output reg [12:0] sdram_adr,
output reg [1:0] sdram_ba,
/* Clocks we must wait following a PRECHARGE command (usually tRP). */
output reg [2:0] tim_rp,
/* Clocks we must wait following an ACTIVATE command (usually tRCD). */
output reg [2:0] tim_rcd,
/* CAS latency, 0 = 2 */
output reg tim_cas,
/* Auto-refresh period (usually tREFI). */
output reg [10:0] tim_refi,
/* Clocks we must wait following an AUTO REFRESH command (usually tRFC). */
output reg [3:0] tim_rfc,
/* Clocks we must wait following the last word written to the SDRAM (usually tWR). */
output reg [1:0] tim_wr,
output reg idelay_rst,
output reg idelay_ce,
output reg idelay_inc,
output reg idelay_cal
);
wire csr_selected = csr_a[13:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
bypass <= 1'b1;
sdram_rst <= 1'b1;
sdram_cke <= 1'b0;
sdram_adr <= 13'd0;
sdram_ba <= 2'd0;
tim_rp <= 3'd2;
tim_rcd <= 3'd2;
tim_cas <= 1'b0;
tim_refi <= 11'd620;
tim_rfc <= 4'd6;
tim_wr <= 2'd2;
idelay_cal <= 0;
end else begin
sdram_cs_n <= 1'b1;
sdram_we_n <= 1'b1;
sdram_cas_n <= 1'b1;
sdram_ras_n <= 1'b1;
idelay_rst <= 1'b0;
idelay_ce <= 1'b0;
idelay_inc <= 1'b0;
csr_do <= 32'd0;
if(csr_selected) begin
if(csr_we) begin
case(csr_a[1:0])
2'b00: begin
bypass <= csr_di[0];
sdram_rst <= csr_di[1];
sdram_cke <= csr_di[2];
end
2'b01: begin
sdram_cs_n <= ~csr_di[0];
sdram_we_n <= ~csr_di[1];
sdram_cas_n <= ~csr_di[2];
sdram_ras_n <= ~csr_di[3];
sdram_adr <= csr_di[16:4];
sdram_ba <= csr_di[18:17];
end
2'b10: begin
tim_rp <= csr_di[2:0];
tim_rcd <= csr_di[5:3];
tim_cas <= csr_di[6];
tim_refi <= csr_di[17:7];
tim_rfc <= csr_di[21:18];
tim_wr <= csr_di[23:22];
end
2'b11: begin
idelay_rst <= csr_di[0];
idelay_ce <= csr_di[1];
idelay_inc <= csr_di[2];
idelay_cal <= csr_di[3];
end
endcase
end
case(csr_a[1:0])
2'b00: csr_do <= {sdram_cke, sdram_rst, bypass};
2'b01: csr_do <= {sdram_ba, sdram_adr, 4'h0};
2'b10: csr_do <= {tim_wr, tim_rfc, tim_refi, tim_cas, tim_rcd, tim_rp};
2'b11: csr_do <= 4'd0;
endcase
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`include "../../models/udp_dff_ps/sky130_fd_sc_hvl__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_receivecontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_receivecontrol.v,v $
// Revision 1.5 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.4 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
`include "timescale.v"
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
);
parameter Tp = 1;
input MTxClk;
input MRxClk;
input TxReset;
input RxReset;
input [7:0] RxData;
input RxValid;
input RxStartFrm;
input RxEndFrm;
input RxFlow;
input ReceiveEnd;
input [47:0]MAC;
input DlyCrcEn;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmOut;
input ReceivedLengthOK;
input ReceivedPacketGood;
input TxUsedDataOutDetected;
input RxStatusWriteLatched_sync2;
input r_PassAll;
output Pause;
output ReceivedPauseFrm;
output AddressOK;
output SetPauseTimer;
reg Pause;
reg AddressOK; // Multicast or unicast address detected
reg TypeLengthOK; // Type/Length field contains 0x8808
reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
reg OpCodeOK; // PAUSE opcode detected (0x0001)
reg [2:0] DlyCrcCnt;
reg [4:0] ByteCnt;
reg [15:0] AssembledTimerValue;
reg [15:0] LatchedTimerValue;
reg ReceivedPauseFrm;
reg ReceivedPauseFrmWAddr;
reg PauseTimerEq0_sync1;
reg PauseTimerEq0_sync2;
reg [15:0] PauseTimer;
reg Divider2;
reg [5:0] SlotTimer;
wire [47:0] ReservedMulticast; // 0x0180C2000001
wire [15:0] TypeLength; // 0x8808
wire ResetByteCnt; //
wire IncrementByteCnt; //
wire ByteCntEq0; // ByteCnt = 0
wire ByteCntEq1; // ByteCnt = 1
wire ByteCntEq2; // ByteCnt = 2
wire ByteCntEq3; // ByteCnt = 3
wire ByteCntEq4; // ByteCnt = 4
wire ByteCntEq5; // ByteCnt = 5
wire ByteCntEq12; // ByteCnt = 12
wire ByteCntEq13; // ByteCnt = 13
wire ByteCntEq14; // ByteCnt = 14
wire ByteCntEq15; // ByteCnt = 15
wire ByteCntEq16; // ByteCnt = 16
wire ByteCntEq17; // ByteCnt = 17
wire ByteCntEq18; // ByteCnt = 18
wire DecrementPauseTimer; //
wire PauseTimerEq0; //
wire ResetSlotTimer; //
wire IncrementSlotTimer; //
wire SlotFinished; //
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
AddressOK <= #Tp 1'b0;
else
if(DetectionWindow & ByteCntEq0)
AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
else
if(DetectionWindow & ByteCntEq1)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
else
if(DetectionWindow & ByteCntEq2)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
else
if(DetectionWindow & ByteCntEq3)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
else
if(DetectionWindow & ByteCntEq4)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
else
if(DetectionWindow & ByteCntEq5)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
else
if(ReceiveEnd)
AddressOK <= #Tp 1'b0;
end
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
TypeLengthOK <= #Tp 1'b0;
else
if(DetectionWindow & ByteCntEq12)
TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
else
if(DetectionWindow & ByteCntEq13)
TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
else
if(ReceiveEnd)
TypeLengthOK <= #Tp 1'b0;
end
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
OpCodeOK <= #Tp 1'b0;
else
if(ByteCntEq16)
OpCodeOK <= #Tp 1'b0;
else
begin
if(DetectionWindow & ByteCntEq14)
OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
if(DetectionWindow & ByteCntEq15)
OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
end
end
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
ReceivedPauseFrmWAddr <= #Tp 1'b0;
else
if(ReceiveEnd)
ReceivedPauseFrmWAddr <= #Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
ReceivedPauseFrmWAddr <= #Tp 1'b1;
end
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
AssembledTimerValue[15:0] <= #Tp 16'h0;
else
if(RxStartFrm)
AssembledTimerValue[15:0] <= #Tp 16'h0;
else
begin
if(DetectionWindow & ByteCntEq16)
AssembledTimerValue[15:8] <= #Tp RxData[7:0];
if(DetectionWindow & ByteCntEq17)
AssembledTimerValue[7:0] <= #Tp RxData[7:0];
end
end
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
DetectionWindow <= #Tp 1'b1;
else
if(ByteCntEq18)
DetectionWindow <= #Tp 1'b0;
else
if(ReceiveEnd)
DetectionWindow <= #Tp 1'b1;
end
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
LatchedTimerValue[15:0] <= #Tp 16'h0;
else
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
else
if(ReceiveEnd)
LatchedTimerValue[15:0] <= #Tp 16'h0;
end
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
DlyCrcCnt <= #Tp 3'h0;
else
if(RxValid & RxEndFrm)
DlyCrcCnt <= #Tp 3'h0;
else
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ByteCnt[4:0] <= #Tp 5'h0;
else
if(ResetByteCnt)
ByteCnt[4:0] <= #Tp 5'h0;
else
if(IncrementByteCnt)
ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
end
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
PauseTimer[15:0] <= #Tp 16'h0;
else
if(SetPauseTimer)
PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
else
if(DecrementPauseTimer)
PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
end
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
PauseTimerEq0_sync1 <= #Tp 1'b1;
PauseTimerEq0_sync2 <= #Tp 1'b1;
end
else
begin
PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
end
end
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
Pause <= #Tp 1'b0;
else
if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
end
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
Divider2 <= #Tp 1'b0;
else
if(|PauseTimer[15:0] & RxFlow)
Divider2 <= #Tp ~Divider2;
else
Divider2 <= #Tp 1'b0;
end
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer = Pause & RxFlow & Divider2;
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
SlotTimer[5:0] <= #Tp 6'h0;
else
if(ResetSlotTimer)
SlotTimer[5:0] <= #Tp 6'h0;
else
if(IncrementSlotTimer)
SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
end
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ReceivedPauseFrm <=#Tp 1'b0;
else
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
ReceivedPauseFrm <=#Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
ReceivedPauseFrm <=#Tp 1'b1;
end
endmodule
|
/**
* datapath.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "aludefs.v"
module datapath(
/* regular inputs */
input wire [ 7 : 0] immediate, /* instruction predicate */
input wire [ 7 : 0] mdr_in, /* memory data register input */
/* toplevel signals */
input wire clk, /* clock signal */
input wire res, /* reset signal */
/* control signals */
input wire [ 1 : 0] ac_source, /* accumulator source */
input wire write_ac, /* write accumulator */
input wire mar_source, /* memory address register source */
input wire write_mar, /* write memory address register */
input wire [ 1 : 0] mdr_source, /* memory data register source */
input wire write_mdr, /* write memory data register */
input wire write_flags, /* write flags register */
input wire [ 1 : 0] pc_source, /* program counter source */
input wire write_pc, /* write program counter */
input wire [ 2 : 0] ALU_op_select, /* ALU operand source */
input wire [`ALUCTLW - 1: 0] ALUctl, /* ALU control signal bus */
/* output signals */
output wire [ 7 : 0] mar_out, /* memory address */
output wire [ 7 : 0] mdr_out, /* data */
output wire [ 7 : 0] pc_out, /* program counter */
output wire [`FWIDTH - 1 : 0] flags /* ALU flags */
);
/* internal signals */
wire [ 7 : 0] ALU_feedback, /* ALU output and feedback path */
pc_next, /* next program counter */
ac_out, /* accumulator data output */
ac_in, /* accumulator data input */
alu_operand, /* second ALU operand */
mar_data, /* memory address register data source */
mdr_data; /* memory data register data source */
wire [`FWIDTH - 1 : 0] flags_out; /* flags */
/* program counter jump select
* pc_source:
* 00: regular execution
* 01: direct jump
* 10: indirect jump
* 11: jump with offset
* rationale:
* mechanism allows for implementation of both direct jumps
* and indirect jumps.
*/
mux4 #(.WIDTH(8)) pc_mux (
.in0(pc_out + 8'b1),
.in1(immediate),
.in2(ac_out),
.in3(pc_out + ac_out),
.sel(pc_source),
.mux_out(pc_next)
);
/* program counter register */
ff_d #(.WIDTH(8)) pc (
.D(pc_next),
.en(write_pc),
.clk(clk),
.res(res),
.Q(pc_out)
);
/* flags register
* rationale:
* keep ALU flags for new operations/CPU status
*/
ff_d #(.WIDTH(`FWIDTH)) flags_register (
.D(flags_out),
.en(write_flags),
.clk(clk),
.res(res),
.Q(flags)
);
/* accumulator input select:
* ac_source:
* 00: store value in memory address register
* 01: store value in memory data register
* 10: store result from ALU into accumulator
* 11: store immediate into accumulator
* rationale:
* mechanism allows for accumulator behaviour and for loading
* a numeric constant into accumulator.
*/
mux4 #(.WIDTH(8)) ac_mux (
.in0(mar_out),
.in1(mdr_out),
.in2(ALU_feedback),
.in3(immediate),
.sel(ac_source),
.mux_out(ac_in)
);
/* accumulator register */
ff_d #(.WIDTH(8)) ac (
.D(ac_in),
.en(write_ac),
.clk(clk),
.res(res),
.Q(ac_out)
);
/* memory address register data source select
* mar_source:
* 1: use source from immediate constant
* 0: use source from accumulator register
* rationale:
* allows for both direct and indirect addressing of memory data
*/
assign mar_data = mar_source ? immediate : ac_out;
/* memory address register */
ff_d #(.WIDTH(8)) mar (
.D(mar_data),
.en(write_mar),
.clk(clk),
.res(res),
.Q(mar_out)
);
/* memory data register data source select
* mdr_source:
* 00: the constant 0
* 01: memory bus value
* 10: immediate value
* 11: accumulator register
* rationale:
* allows for both direct and indirect
* addressing of memory data
* allows to easily clear a memory address
*/
mux4 #(.WIDTH(8)) mdr_mux (
.in0(8'b0),
.in1(mdr_in),
.in2(immediate),
.in3(ac_out),
.sel(mdr_source),
.mux_out(mdr_data)
);
/* memory data register */
ff_d #(.WIDTH(8)) mdr (
.D(mdr_data),
.en(write_mdr),
.clk(clk),
.res(res),
.Q(mdr_out)
);
/* ALU operand source select
* ALU_op_select:
* 000: the constant 0
* 001: the constant 1
* 010: the constant 2
* 011: the constant -1
* 100: the constant -2
* 101: accumulator register
* 110: immediate constant
* 111: memory data register
* rationale:
* allows for the ease of implementation of
* arithmetic/logic instructions
*/
mux8 #(.WIDTH(8)) ALU_op_mux (
.in0(8'b0),
.in1(8'b01),
.in2(8'b10),
.in3(8'hff),
.in4(8'hfe),
.in5(ac_out),
.in6(immediate),
.in7(mdr_out),
.sel(ALU_op_select),
.mux_out(alu_operand)
);
/* ALU */
ALU alu0 (
.op1(ac_out),
.op2(alu_operand),
.ctl(ALUctl),
.flags_in(flags),
.result(ALU_feedback),
.flags_out(flags_out)
);
endmodule
`include "aluundefs.v"
/* vim: set ts=4 tw=79 syntax=verilog */
|
/*Este modulo tiene como funcion principal tomar las instrucciones y decidir si se debe continuar el flujo normal del programa
o hacer algun salto, ademas le da la informacion adicional a otros modulos sobre que hacer, como la direccion donde se debe
saltar o si se debe operar con constantes en vez de los registros de uso general, y tambien en caso de saltos relativos la
direccion del salto y la cantidad de espacios en memoria que se debe saltar.
*/
module decodificador(
input wire Clock,
input wire[15:0] wInstruction,
input wire wZa, wZb, wCa, wCb, wNa, wNb,
output reg rBranch_taken,
output reg rJumpTaken,
output reg[9:0] rBranch_dir,
output reg[7:0] rC,
output reg rMux_a_sel,
output reg rMux_b_sel
);
always @( posedge Clock)
begin
case(wInstruction[15:10])
`LDA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`LDB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`STA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`STB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ADDA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ADDB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`SUBA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`SUBB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ANDA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ANDB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ORA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ORB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ASLA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ASRA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`LDCA:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'd1;
rC=wInstruction[7:0];
end
`LDCB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ADDCA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ADDCB:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`SUBCA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`SUBCB:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ANDCA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ANDCB:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ORCA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ORCB:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`JMP:
begin
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rJumpTaken<=1;
rBranch_dir<=wInstruction[9:0];
rC<=8'b0;
end
`BAEQ:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wZa==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BANE:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wZa==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BACS:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wCa==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BACC:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wCa==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BAMI:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wNa==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BAPL:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wNa==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBEQ:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wZb==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBNE:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wZb==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBCS:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wCb==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBCC:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wCb==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBMI:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wNb==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBPL:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wNb==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
default:
begin
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rJumpTaken<=0;
rBranch_dir<=10'b0;
rC=8'b0;
end
endcase
end
endmodule
|
/* VGA Adapter
* ----------------
*
* This is an implementation of a VGA Adapter. The adapter uses VGA mode signalling to initiate
* a 640x480 resolution mode on a computer monitor, with a refresh rate of approximately 60Hz.
* It is designed for easy use in an early digital logic design course to facilitate student
* projects on the Altera DE2 Educational board.
*
* This implementation of the VGA adapter can display images of varying colour depth at a resolution of
* 320x240 or 160x120 superpixels. The concept of superpixels is introduced to reduce the amount of on-chip
* memory used by the adapter. The following table shows the number of bits of on-chip memory used by
* the adapter in various resolutions and colour depths.
*
* -------------------------------------------------------------------------------------------------------------------------------
* Resolution | Mono | 8 colours | 64 colours | 512 colours | 4096 colours | 32768 colours | 262144 colours | 2097152 colours |
* -------------------------------------------------------------------------------------------------------------------------------
* 160x120 | 19200 | 57600 | 115200 | 172800 | 230400 | 288000 | 345600 | 403200 |
* 320x240 | 78600 | 230400 | ############## Does not fit ############################################################## |
* -------------------------------------------------------------------------------------------------------------------------------
*
* By default the adapter works at the resolution of 320x240 with 8 colours. To set the adapter in any of
* the other modes, the adapter must be instantiated with specific parameters. These parameters are:
* - RESOLUTION - a string that should be either "320x240" or "160x120".
* - MONOCHROME - a string that should be "TRUE" if you only want black and white colours, and "FALSE"
* otherwise.
* - BITS_PER_COLOUR_CHANNEL - an integer specifying how many bits are available to describe each colour
* (R,G,B). A default value of 1 indicates that 1 bit will be used for red
* channel, 1 for green channel and 1 for blue channel. This allows 8 colours
* to be used.
*
* In addition to the above parameters, a BACKGROUND_IMAGE parameter can be specified. The parameter
* refers to a memory initilization file (MIF) which contains the initial contents of video memory.
* By specifying the initial contents of the memory we can force the adapter to initially display an
* image of our choice. Please note that the image described by the BACKGROUND_IMAGE file will only
* be valid right after your program the DE2 board. If your circuit draws a single pixel on the screen,
* the video memory will be altered and screen contents will be changed. In order to restore the background
* image your circuti will have to redraw the background image pixel by pixel, or you will have to
* reprogram the DE2 board, thus allowing the video memory to be rewritten.
*
* To use the module connect the vga_adapter to your circuit. Your circuit should produce a value for
* inputs X, Y and plot. When plot is high, at the next positive edge of the input clock the vga_adapter
* will change the contents of the video memory for the pixel at location (X,Y). At the next redraw
* cycle the VGA controller will update the contants of the screen by reading the video memory and copying
* it over to the screen. Since the monitor screen has no memory, the VGA controller has to copy the
* contents of the video memory to the screen once every 60th of a second to keep the image stable. Thus,
* the video memory should not be used for other purposes as it may interfere with the operation of the
* VGA Adapter.
*
* As a final note, ensure that the following conditions are met when using this module:
* 1. You are implementing the the VGA Adapter on the Altera DE2 board. Using another board may change
* the amount of memory you can use, the clock generation mechanism, as well as pin assignments required
* to properly drive the VGA digital-to-analog converter.
* 2. Outputs VGA_* should exist in your top level design. They should be assigned pin locations on the
* Altera DE2 board as specified by the DE2_pin_assignments.csv file.
* 3. The input clock must have a frequency of 50 MHz with a 50% duty cycle. On the Altera DE2 board
* PIN_N2 is the source for the 50MHz clock.
*
* During compilation with Quartus II you may receive the following warnings:
* - Warning: Variable or input pin "clocken1" is defined but never used
* - Warning: Pin "VGA_SYNC" stuck at VCC
* - Warning: Found xx output pins without output pin load capacitance assignment
* These warnings can be ignored. The first warning is generated, because the software generated
* memory module contains an input called "clocken1" and it does not drive logic. The second warning
* indicates that the VGA_SYNC signal is always high. This is intentional. The final warning is
* generated for the purposes of power analysis. It will persist unless the output pins are assigned
* output capacitance. Leaving the capacitance values at 0 pf did not affect the operation of the module.
*
* If you see any other warnings relating to the vga_adapter, be sure to examine them carefully. They may
* cause your circuit to malfunction.
*
* NOTES/REVISIONS:
* July 10, 2007 - Modified the original version of the VGA Adapter written by Sam Vafaee in 2006. The module
* now supports 2 different resolutions as well as uses half the memory compared to prior
* implementation. Also, all settings for the module can be specified from the point
* of instantiation, rather than by modifying the source code. (Tomasz S. Czajkowski)
*/
module vga_adapter(
resetn,
clock,
colour,
x, y, plot,
/* Signals for the DAC to drive the monitor. */
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
VGA_BLANK,
VGA_SYNC,
VGA_CLK);
parameter BITS_PER_COLOUR_CHANNEL = 1;
/* The number of bits per colour channel used to represent the colour of each pixel. A value
* of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity
* of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours.
* In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL ) colours. The number of colours is
* limited by the screen resolution and the amount of on-chip memory available on the target device.
*/
parameter MONOCHROME = "FALSE";
/* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce
* the amount of memory you will use by a factor of 3. */
// parameter RESOLUTION = "320x240";
parameter RESOLUTION = "160x120";
/* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
* the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
* It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
* to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
*/
parameter BACKGROUND_IMAGE = "background.mif";
// parameter BACKGROUND_IMAGE = "image.colour.mif";
/* The initial screen displayed when the circuit is first programmed onto the DE2 board can be
* defined useing an MIF file. The file contains the initial colour for each pixel on the screen
* and is placed in the Video Memory (VideoMemory module) upon programming. Note that resetting the
* VGA Adapter will not cause the Video Memory to revert to the specified image. */
parameter USING_DE1 = "TRUE";
/* If set to "TRUE" it adjust the offset of the drawing mechanism to account for the differences
* between the DE2 and DE1 VGA digital to analogue converters. Set to "TRUE" if and only if
* you are running your circuit on a DE1 board. */
/*****************************************************************************/
/* Declare inputs and outputs. */
/*****************************************************************************/
input resetn;
input clock;
/* The colour input can be either 1 bit or 3*BITS_PER_COLOUR_CHANNEL bits wide, depending on
* the setting of the MONOCHROME parameter.
*/
input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] colour;
/* Specify the number of bits required to represent an (X,Y) coordinate on the screen for
* a given resolution.
*/
input [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
input [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
/* When plot is high then at the next positive edge of the clock the pixel at (x,y) will change to
* a new colour, defined by the value of the colour input.
*/
input plot;
/* These outputs drive the VGA display. The VGA_CLK is also used to clock the FSM responsible for
* controlling the data transferred to the DAC driving the monitor. */
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output VGA_HS;
output VGA_VS;
output VGA_BLANK;
output VGA_SYNC;
output VGA_CLK;
/*****************************************************************************/
/* Declare local signals here. */
/*****************************************************************************/
wire valid_160x120;
wire valid_320x240;
/* Set to 1 if the specified coordinates are in a valid range for a given resolution.*/
wire writeEn;
/* This is a local signal that allows the Video Memory contents to be changed.
* It depends on the screen resolution, the values of X and Y inputs, as well as
* the state of the plot signal.
*/
wire [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] to_ctrl_colour;
/* Pixel colour read by the VGA controller */
wire [((RESOLUTION == "320x240") ? (16) : (14)):0] user_to_video_memory_addr;
/* This bus specifies the address in memory the user must write
* data to in order for the pixel intended to appear at location (X,Y) to be displayed
* at the correct location on the screen.
*/
wire [((RESOLUTION == "320x240") ? (16) : (14)):0] controller_to_video_memory_addr;
/* This bus specifies the address in memory the vga controller must read data from
* in order to determine the colour of a pixel located at coordinate (X,Y) of the screen.
*/
wire clock_25;
/* 25MHz clock generated by dividing the input clock frequency by 2. */
wire vcc, gnd;
/*****************************************************************************/
/* Instances of modules for the VGA adapter. */
/*****************************************************************************/
assign vcc = 1'b1;
assign gnd = 1'b0;
vga_address_translator user_input_translator(
.x(x), .y(y), .mem_address(user_to_video_memory_addr) );
defparam user_input_translator.RESOLUTION = RESOLUTION;
/* Convert user coordinates into a memory address. */
assign valid_160x120 = (({1'b0, x} >= 0) & ({1'b0, x} < 160) & ({1'b0, y} >= 0) & ({1'b0, y} < 120)) & (RESOLUTION == "160x120");
assign valid_320x240 = (({1'b0, x} >= 0) & ({1'b0, x} < 320) & ({1'b0, y} >= 0) & ({1'b0, y} < 240)) & (RESOLUTION == "320x240");
assign writeEn = (plot) & (valid_160x120 | valid_320x240);
/* Allow the user to plot a pixel if and only if the (X,Y) coordinates supplied are in a valid range. */
/* Create video memory. */
altsyncram VideoMemory (
.wren_a (writeEn),
.wren_b (gnd),
.clock0 (clock), // write clock
.clock1 (clock_25), // read clock
.clocken0 (vcc), // write enable clock
.clocken1 (vcc), // read enable clock
.address_a (user_to_video_memory_addr),
.address_b (controller_to_video_memory_addr),
.data_a (colour), // data in
.q_b (to_ctrl_colour) // data out
);
defparam
VideoMemory.WIDTH_A = ((MONOCHROME == "FALSE") ? (BITS_PER_COLOUR_CHANNEL*3) : 1),
VideoMemory.WIDTH_B = ((MONOCHROME == "FALSE") ? (BITS_PER_COLOUR_CHANNEL*3) : 1),
VideoMemory.INTENDED_DEVICE_FAMILY = "Cyclone II",
VideoMemory.OPERATION_MODE = "DUAL_PORT",
VideoMemory.WIDTHAD_A = ((RESOLUTION == "320x240") ? (17) : (15)),
VideoMemory.NUMWORDS_A = ((RESOLUTION == "320x240") ? (76800) : (19200)),
VideoMemory.WIDTHAD_B = ((RESOLUTION == "320x240") ? (17) : (15)),
VideoMemory.NUMWORDS_B = ((RESOLUTION == "320x240") ? (76800) : (19200)),
VideoMemory.OUTDATA_REG_B = "CLOCK1",
VideoMemory.ADDRESS_REG_B = "CLOCK1",
VideoMemory.CLOCK_ENABLE_INPUT_A = "BYPASS",
VideoMemory.CLOCK_ENABLE_INPUT_B = "BYPASS",
VideoMemory.CLOCK_ENABLE_OUTPUT_B = "BYPASS",
VideoMemory.POWER_UP_UNINITIALIZED = "FALSE",
VideoMemory.INIT_FILE = BACKGROUND_IMAGE;
vga_pll mypll(clock, clock_25);
/* This module generates a clock with half the frequency of the input clock.
* For the VGA adapter to operate correctly the clock signal 'clock' must be
* a 50MHz clock. The derived clock, which will then operate at 25MHz, is
* required to set the monitor into the 640x480@60Hz display mode (also known as
* the VGA mode).
*/
vga_controller controller(
.vga_clock(clock_25),
.resetn(resetn),
.pixel_colour(to_ctrl_colour),
.memory_address(controller_to_video_memory_addr),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK),
.VGA_SYNC(VGA_SYNC),
.VGA_CLK(VGA_CLK)
);
defparam controller.BITS_PER_COLOUR_CHANNEL = BITS_PER_COLOUR_CHANNEL ;
defparam controller.MONOCHROME = MONOCHROME;
defparam controller.RESOLUTION = RESOLUTION;
defparam controller.USING_DE1 = USING_DE1;
endmodule
|
`include"axi2ocp.v"
/*
* AXI to OCP translation block test bench
* Author: Michael Walton
*
* This module validates the AXI to OCP translation block
*/
module axi2ocp_tb();
// Declarations/*{{{*/
// axi2ocp hookups
reg clk;
reg reset;
// AXI FIFO/*{{{*/
reg m_aclk;
wire s_aclk;
reg m_axis_tvalid;
wire m_axis_tready;
reg [`fifo_wdth - 1:0] m_axis_tdata;
reg [`data_wdth - 1:0] m_axis_tkeep;
reg m_axis_tlast;
wire s_axis_tvalid;
reg s_axis_tready;
wire [`fifo_wdth - 1:0] s_axis_tdata;
wire [`data_wdth - 1:0] s_axis_tkeep;
wire s_axis_tlast;
wire axis_overflow;
wire axis_underflow;
/*}}}*/
// OCP 2.2 Interface/*{{{*/
wire [`addr_wdth - 1:0] address;
wire enable;
wire [2:0] burst_seq;
wire burst_single_req;
wire [9:0] burst_length;
wire data_valid;
wire read_request;
wire ocp_reset;
wire sys_clk;
wire [`data_wdth - 1:0] write_data;
wire write_request;
wire writeresp_enable;
/*}}}*/
/*}}}*/
// AXI FIFO containing simulation data/*{{{*/
FIFO axi_rx_fifo (
.m_aclk(m_aclk),
.s_aclk(s_aclk),
.s_aresetn(reset),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.axis_overflow(axis_overflow),
.axis_underflow(axis_underflow)
);/*}}}*/
axi2ocp U0(/*{{{*/
.clk(clk),
.reset(reset),
// AXI FIFO/*{{{*/
.m_aclk(m_aclk),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.axis_underflow(axis_underflow),
/*}}}*/
// OCP 2.2 Interface/*{{{*/
.address(address),
.enable(enable),
.burst_seq(burst_seq),
.burst_single_req(burst_single_req),
.burst_length(burst_length),
.data_valid(data_valid),
.read_request(read_request),
.ocp_reset(ocp_reset),
.sys_clk(sys_clk),
.write_data(write_data),
.write_request(write_request),
.writeresp_enable(writeresp_enable)
/*}}}*/
);/*}}}*/
// Begin test stimuli/*{{{*/
initial begin
clk <= 0;
reset <= 1;
// FIFO initialization
m_aclk <= 1'b0;
m_axis_tvalid <= 1'b0;
m_axis_tdata <= `fifo_wdth'bx;
m_axis_tkeep <= `data_wdth'bx;
m_axis_tlast <= 1'b0;
forever begin
#10 clk <= ~clk;
end
end
initial begin
// Simulate an idle queue/*{{{*/
#20 reset <= 0;
// FIFO initialization
m_aclk <= 1'b0;
m_axis_tvalid <= 1'b0;
m_axis_tdata <= `fifo_wdth'bx;
m_axis_tkeep <= `data_wdth'bx;
m_axis_tlast <= 1'b0;/*}}}*/
// Simulate a read from a 64-bit address for 10 bytes worth of data/*{{{*/
// TLP consists of just a header, which will be in 4 parts we will
// need to pull from the FIFO.
// Fmt: 001 - 4 DW header, no data
// Type: 0 0000 - Memory read request
// Header 1: 00X0 0000 0000 0000 0000 0000 0000 0000
// Header 2 [ requester id ] [ tag ] [lbe][be]
// Header 3: eeee eeee eeee eeee eeee eeee eeee eeee Test addr1
// Header 4: ffff ffff ffff ffff ffff ffff ffff ffff Test addr2
// Header 1 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h20000000;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 2 of 4
// Fill in with 0xXXXXXXFF since request is greater than 1 DW
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'b0; // FILL IN WITH READ R INF
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 3 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'heeeeeeee;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 4 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hffffffff;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b1;
// Wait for bridge to finish translating the read request and for
// it to asseart m_axis_tready on the FIFO
#200/*}}}*/ // 20 unit clock period * 10 bytes
// Simulate a write to a 64-bit address for 13 bytes/*{{{*/
// TLP consists of just a header, which will be in 4 parts we will
// need to pull from the FIFO.
// Fmt: 001 - 4 DW header, no data
// Type: 0 0000 - Memory read request
// Header 1: 01X0 0000 0000 0000 0000 0000 0000 1101
// Header 2 [ requester id ] [ tag ] [lbe][be]
// Header 3: dddd dddd dddd dddd dddd dddd dddd dddd Test addr1
// Header 4: cccc cccc cccc cccc cccc cccc cccc cccc Test addr2
// Header 1 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h6000000d;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 2 of 4
#100 m_axis_tvalid <= 1'b1;
// Fill in with 0xXXXXXXFF since request is greater than 1 DW
m_axis_tdata <= `fifo_wdth'b0; // FILL IN WITH WRITE R INF
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 3 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hdddddddd;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 4 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hcccccccc;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 1 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hffffffff;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 2 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'heeeeeeee;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 3 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hdddddddd;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 4 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hcccccccc;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 5 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hbbbbbbbb;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 6 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'haaaaaaaa;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 7 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h99999999;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 8 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h88888888;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 9 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h77777777;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 10 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h66666666;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 11 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h55555555;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 12 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h44444444;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 13 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h33333333;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b1;
#100/*}}}*/
// Finish test bench/*{{{*/
#100 m_aclk <= 1'b0;
m_axis_tvalid <= 1'b0;
m_axis_tdata <= `fifo_wdth'bx;
m_axis_tkeep <= `data_wdth'bx;
m_axis_tlast <= 1'b0;/*}}}*/
end/*}}}*/
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
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